Dept.

of Electronics and Electrical Communication Engineering

Indian Institute of Technology Kharagpur

COMMUNICATION - II
LAB(EC31204)

Experiment 5: CDR using Alexander Phase

Detector
Date of submission: 02-03-2024

Instructors: Name: Abhinav Raj

Prof. Jithin R. Roll Number: 21EC10002
Prof. P Sasi Vinay Group number: 6 (Monday)
Introduction:
CDR circuits play a critical role in high-speed transceivers, extracting clock signals from
received asynchronous and noisy data and retiming the data to remove accumulated jitter.
However, designing high-performance CDR circuits poses challenges like managing jitter,
skews, and reliably acquiring phase lock. Different phase detector circuits are used, with
trade-offs in performance - the Hogge detector provides linear operation, the Alexander
detector has a bang-bang characteristic along with inherent data retiming and no output for
long data runs, and half-rate detectors allow sensing data at full rate with clock recovery at
half rate. CDR architectures utilize these phase detectors while balancing performance
factors like jitter versus complexity. Techniques include using dual loops for frequency and
phase locking, external frequency references, decomposing control into fine and coarse
components, and sequencing locking loops.
The focus of the experiment is applying an advanced Alexander phase detector to a 10 Gbps
CDR circuit and evaluating resulting parameters like clock jitter and frequency locking range.
The core goals are assessing high-speed CDR improvements enabled by advanced detectors
like the Alexander, and further analysing detector performance in a real high-speed
application. The Alexander detector works by sampling the input data stream at three
points within a clock period to determine if the clock leads or lags the data. It provides
inherent data retiming and a bang-bang characteristic useful for high speeds. However,
basic CDR circuits using simple phase detectors can suffer from issues like systematic phase
offsets and data feedthrough to the VCO output. In summary, specialized detector circuits
and overall architectures are necessary to optimize CDR operation, and research like the
experiment provides insight into applying emerging approaches.
We will use the following IC 566 IC for this experiment. Here is the diagram for the same.
Key Objectives:
Design an advanced clock data recovery (CDR) circuit using the Alexander phase detector.
Components:
❖ IC 566
❖ IC741 (Op-Amp)
❖ D flip-flops (IC 7474)
❖ XOR gates (IC 7486)
❖ NOT gate (IC 7404)
❖ Potentiometer
❖ Resistors
❖ Capacitors
❖ Digital oscilloscope
❖ Function generator
❖ Breadboard
❖ Connecting wires
❖ Power supply
Circuit Design:

Phase-detector based clock data recovery circuit

Free running frequency of VCO = 50 kHz (With no signal at pin-5 of VCO, adjust the
potentiometer 10 kΩ to get oscillation frequency (fo) = 50 kHz)
Bit rate of PN sequence = 50 kbps
Results and Figures:

X and Y
 Subtractor output

Recovered Clock data

Circuit:

Discussion:
The experiment commenced by supplying a 50 kbps pseudorandom binary sequence (PRBS)
to the Alexander phase detector. We first characterized the phase detector operation by
directly applying a 50 kHz clock and observing the resulting X and Y outputs. These signals
were supplied to a subtraction circuit to generate an error voltage.
We then connected the components for closed-loop clock recovery. The voltage-controlled
oscillator (VCO) centre frequency was calibrated to match the 50 kbps data rate through
adjustment of a control potentiometer, with no signal input. By feeding the subtractor's
error voltage to the frequency modulation port of the VCO, we coupled the VCO clock back
to drive the Alexander detector instead of the initial fixed reference clock.
This closed-loop system aims to extract a synchronized timing signal from the noisy PRBS
data. We observed the VCO output until clear indications of frequency and phase-lock were
attained. The quality of the recovered 50 kHz clock was assessed by the lock range and jitter
performance. We experimentally established robust operation from 45 to 55 kHz, closely
centred on the target 50 kHz PRBS bit rate.
This demonstrates a key improvement over basic CDR circuits through using an advanced
phase detector design specifically suited for high-speed operation. By providing inherent
data retiming and a bang-bang characteristic, the Alexander detector avoids issues like static
phase offset while supporting clock recovery up to the target data rate. Our measurements
confirm the increased frequency locking range enabled by this approach. In conclusion,
specialized detector circuits like the Alexander enable improved CDR performance critical
for emerging high-speed applications.

Conclusion:
In conclusion, we successfully demonstrated advanced high-speed clock recovery using the
Alexander phase detector. The closed-loop circuit extracted the embedded clock from noisy
input data, leveraging the Alexander detector's benefits of inherent retiming and bang-bang
operation. Compared to basic recovery circuits, the experiment realized a 45-55 kHz locking
range and acceptable jitter, enabling more robust performance critical for next-generation
transceivers meeting stringent speed and reliability requirements. Our techniques help pave
the way for reliable high-data-rate systems via specialized detector designs.