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DE Manual
DE Manual
Lab Manual
Digital Electronics
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List of Experiment
Expt.
Experiment Name Page No.
No
Verify the truth tables of logic gates OR, AND, NOT, NOR and
1 3-6
NAND.
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Experiment No: 1
Verify the truth tables of logic gates OR, AND,
NOT, NOR and NAND.
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Experiment No. 1
Aim: Verify the truth tables of logic gates OR, AND, NOT, NOR and NAND.
Apparatus: Atanua Software
Theory:
1. OR Gate: The OR gate is a circuit which gives a high output if one or more of its
inputs are high. A plus sign (+) is used to indicate the OR operation.
2. AND Gate: The AND gate is a circuit which gives a high output (logic 1) if all its
inputs are high. A dot (.) is used to indicate the AND operation.
3. NOT Gate: The NOT gate is a circuit which produces at its output the negated
(inverted) version of its input logic. The circuit is also known as an inverter. If the
input variable is A, the inverted output is written as A’.
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4. NOR Gate: The NOR gate is a NOT-OR circuit which is equivalent to an OR circuit
followed by a NOT circuit. The output of the NOR gate is low if any of its inputs is
high.
5. NAND Gate: The NAND gate is a NOT-AND circuit which is equivalent to an AND
circuit followed by a NOT circuit. The output of the NAND gate is high if any of its
inputs is low.
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Procedure:
Precautions:
Result:
Different logic gates are constructed and their truth tables are verified.
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Experiment No: 2
Design and implement 4-bit binary to Gray code
converter.
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Experiment No. 2
Aim: Design and implement 4-bit Gray to Binary code converter.
Theory:
Gray Code system is a binary number system in which every successive pair of numbers
differs in only one bit. It is used in applications in which the normal sequence of binary
numbers generated by the hardware may produce an error or ambiguity during the
transition from one number to the next. For example, the states of a system may change
from 3(011) to 4(100) as- 011 — 001 — 101 — 100. Therefore there is a high chance of
a wrong state being read while the system changes from the initial state to the final state.
This could have serious consequences for the machine using the information. The Gray
code eliminates this problem since only one bit changes its value during any transition
between two numbers.
Truth Table:
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Circuit Diagram:
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Procedure:
Result:
Precautions:
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Experiment No: 3
Realization of 2:4 decoder using basic gates.
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Experiment No. 3
Aim: Realization of 2:4 decoder using basic gates.
Theory:
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n output
lines. One of these outputs will be active High based on the combination of inputs
present, when the decoder is enabled. That means decoder detects a particular code. The
outputs of the decoder are nothing but the min terms of ‘n’ input variables lines, when it
is enabled.
2: 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0.
The block diagram of 2 to 4 decoder is shown in the following figure.
One of these four outputs will be ‘1’ for each combination of inputs when enable, E is
‘1’. The Truth table of 2 to 4 decoder is shown below.
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Truth Table:-
From Truth table, we can write the Boolean functions for each output as:
Each output is having one product term. So, there are four product terms in total. We can
implement these four product terms by using four AND gates having three inputs each &
two inverters. The circuit diagram of 2 to 4 decoder is shown in the following figure.
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Procedure: -
Result:
Precautions:
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Experiment No: 4
Realization of 8:1 Mux using basic gates
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Experiment No: 4
Aim: Realization of 8:1 Mux using basic gates.
Apparatus: Atanua Software
Theory:
Multiplexer: The multiplexer is a device that has multiple inputs and single line output.
The select lines determine which input is connected to the output, and also increase the
amount of data that can be sent over a network within a certain time. It is also called a
data selector.
Multiplexers are capable of handling both analog and digital applications. In analog
applications, multiplexers are made up of relays and transistor switches, whereas in
digital applications, the multiplexers are built from standard logic gates. When the
multiplexer is used for digital applications, it is called a digital multiplexer.
Demultiplexer: De-multiplexer is also a device with one input and multiple output lines.
It is used to send a signal to one of the many devices. The main difference between a
multiplexer and a de-multiplexer is that a multiplexer takes two or more signals and
encodes them on a wire, whereas a de-multiplexer does reverse to what the multiplexer
does.
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6,
and A7, 3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the
combination of inputs that are present at the selection lines S0, S1, and S2, one of these 8
inputs are connected to the output. The block diagram and the truth table of the 8×1
multiplexer are given below:
Block Diagram:
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Truth Table:
Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2
A5+S0'.S1.S2 .A6+S0.S1.S3.A7
Circuit Diagram:
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Procedure: -
Result:
Precautions:
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Experiment No: 5
Verify the truth table of J-K, t and D flip-flop
using IC’s.
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Experiment No. 5
Aim: - Verify the truth table of J-K, t and D flip-flop using IC’s.
A flip–flop is a “bit bucket”; it holds a single binary bit .Flip flops are actually an
application of logic gates. With the help of Boolean logic we can create memory with
them. Flip flops can also be considered as the most basic idea of a Random Access
Memory [RAM]. The most commonly used application of flip flops is in the
implementation of a feedback circuit. As a memory relies on the feedback concept, flip
flops can be used to design it.
1. J-K Flip-flop
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions.
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2. D Flip-flop
D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal.
3. T Flip-flop
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Procedure: -
Result:
Precautions:
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