DESIGN FOR TESTABILITY

(PROFESSIONAL ELECTIVE-II)

Course Code: 20EC1157 L T P C

3 0 0 3

Pre requisites: Digital Logic Design.

Course Outcomes: At the end of the course the student will be able to
CO1: Describe the Testability of Combinational Circuits (L2)
CO2: Explain the Testability of Sequential Circuits (L2)
CO3: Illustrate the concepts of Built In Self-Test (L3)
CO4: Demonstrate the design for Testability of Memory Circuits (L3)
CO5: Illustrate Self Checking Circuits using various techniques (L3)

UNIT I 10 Lectures
Design for Testability for Combinational Circuits
Stuck at Faults, Fault diagnosis by Path Sensitization Technique, Reed Muller’s expansion
technique, OR-AND-OR design, Automatic Synthesis of Testable Logic, Testable design of
Multilevel Combinational Circuits.

Learning outcomes: At the end of this unit, the student will be able to
1. explain about Stuck at Faults in digital circuits (L2)
2. describe Reed Muller’s expansion technique (L2)
3. discuss about various testable design of Multilevel Combinational Circuits (L2)

UNIT-II 10 Lectures
Design for Testability for Sequential Circuits
Controllability and observability, Ad-Hoc Design Rules for Improving Testability, Scan Path
Technique for testable Sequential Circuit design, Level Sensitive Scan Design (LSSD), Random
Access Scan Technique, partial Scan, Boundary Scan.

Learning outcomes: At the end of this unit, the student will be able to
1. explain the concepts of Controllability and observability (L2)
2. discuss various design rules of Ad-Hoc Design (L2)
3. describe about various scan based techniques (L2)

UNIT-III 10 Lectures
Built-In Self-Test
Test Pattern generation for BIST, Output Response Analysis, Circular BIST, Built-In logic Block
observer, Self-Testing using an MISR and Parallel Shift register Sequence generator, LSSD
On-Chip Self-Test.
Learning outcomes: At the end of this unit, the student will be able to
1. explain about various test Pattern generation techniques for BIST(L2)
2. describe various techniques of Output Response Analysis (L2)
3. demonstrate various BIST architectures (L3)

UNIT- IV 10 Lectures
Testable Memory Design
RAM fault Models, Test Algorithms for RAMs-Galloping 0’s and 1’s,Walking 0’s and 1’s,
March Test, MATS Check Board Test, Detection of Pattern-Sensitive Faults, BIST Techniques
for RAM Chips.

Learning outcomes: At the end of this unit, the student will be able to
1. discuss about various RAM models (L2)
2. demonstrate various test algorithms for RAM’s (L3)
3. explain about detection of Pattern-Sensitive Faults (L2)

UNIT-V 10 Lectures
Self - Checking Circuits
Basic concepts of Self checking circuits, Design of Totally Self Checking checker- Self
Checking using m/n codes, Equality Checkers, Berger code, Self-Checking Combinational
Circuits, Self -Checking Sequential Circuit.

Learning outcomes: At the end of this unit, the student will be able to
1. illustrate about basic concepts of Self checking circuits (L3)
2. demonstrate various methods of Self-Checking circuits (L3)
3. use the concepts of self–checking checkers in Combinational and Sequential circuits
(L3)

Text Books:
1. Lala, Parag K. An Introduction to Logic Circuit Testing, Morgan & Claypool, 2009.
2. Parag K. Lala, Digital Circuits Testing and Testability, Academic Press, 1997.
3. M. Abramovili, M.A. Breues, A. D. Friedman, Digital Systems Testing and Testable
Design, Jaico publications, 2001.

References:
1. Zainalabedin Navabi, Digital System Test and Testable Design Using HDL Models and
Architectures, Springer, 2011.
2. Parag K. Lala, Fault Tolerant & Fault Testable Hardware Design, PS Publications, 2002.
3. Weste and Eshraghian, Principles of CMOS VLSI Design, Pearson Education, 2nd edition,
2000.

***