Priyadarshini College of Engineering, Nagpur

Sessional Examination (2022-23) Odd Semester

B.Tech. Fifth Semester (Artificial Intelligence and Data Science) (C.B.C.S)
SUBJECT: DSD
UNIT 1:

Introduction to Verilog:
Verilog as HDL, Levels of design Description, Concurrency, Simulation and
Synthesis, Functional Verification , System Tasks, Programming Language
Interface(PLI), Module, Simulation and Synthesis Tools, Test Benches.
Language Constructs and Conventions: Introduction, Keywords, Identifiers,
White space characters, Comments, Numbers , Strings, Logic Values,
Strengths, DAta Types, Scalars and Vectors, Parameters, Operators.
SR.NO. QUESTION MARKS

Q.1. Explain verilog as HDL and how it is different from other languages. 5

Q.2. Explain the components of a Verilog module with block diagram. 7

Q.3. Explain Different styles of modeling .

Q.4. What are the different models of verilog HDL programming explain them with
suitable examples.

Q.5. Explain Different styles of modeling .

Q.6. Write difference between tasks and function 7

Q.7. Differentiate between module and a test bench in verilog.

Q.8. Illustrate with an example Array of Instances of Primitives

Q.9. Explain the following “lexical conventions” with examples. i) White space ii) Strengths 7

Q.10. a)Explain identifiers, comments and strings in verilog. 4

b) Give details of strengths in Verilog.

Q.11. Explain bidirectional gates with suitable diagram. 4

Q.12. a) Define concurrency. [2] 9

b) Explain about identifiers. [3]

 c) Discuss about latch.[2]

d) Define system task. [2]

Q.13. Explain about following terms: 7

i) Scalars and vectors

ii) Operators

Explain about Operators with examples.

Q.14. Explain test bench with example. 5

Q.15. What is test bench? Why it is needed. 5

Q.16. what is PLI ? explain types of built in system calls. 8

Q.17. With examples explain instantiation with ‘strengths’ and ‘Delays’ 5

Q.18. Explain parameters and memory with example 7

Q.19. what is Simulation and Synthesis ? 6

Q.20. List any data types used in verilog. 7

UNIT 2:

Gate Level Modeling and Gate Primitive, Module structure, other GATE
primitives, Illustrative Examples, Tri-State Gates,Arrays of Instances of
Primitives , Design of Flip-flops with Gate Primitives, Delays, Strength and
Contention Resolution, Net Types, Design of Basic Circuits.
Modeling at Data Flow Level Introduction, Continuous assignment structures, Delays and
Continuous Assignments ,Assignment to vectors, Operators.
Sr.no. QUESTION Marks

Q.1. Define tri-gate state. 5

Q.2. What are the user defined primitives and write any program using these. 5

Q.3. Explain Gate Level Modeling in detail. 7

Q.4. Discuss about the AND Gate primitive. 7

Q.5. By talking one example, explain gate level modeling. 7

Q.6. How to introduce delays in verilog HDL programming? Why these are needed. 7

Q.7. Design any one Flip-flops with Gate Primitives 7

Q.8. Design a 4 bit full adder using gate level primitives. 7

Q.9. What is gate Delays and its types ? 6

Q.10. State various Gate Primitives used in verilog. 6

Q.11. Explain Continuous assignment,with net declaration and strength ,delay in gate level 8
modeling .

Q.12. What is Arrays of Instances of Primitives in gate level modeling. 5

Q.13. What is gate delay in gate level modeling. 6

Q.14. Design and implement D flip flop using Data flow modeling. 7

Q.15. What is dataflow modeling ,explain with one example. 7

UNIT 3:
Behavioral Modeling
Introduction, Operations and Assignments, Functional Bifurcation, Initial
Construct, Always Construct, Behavioral modeling of Flip Flops and
latches, Assignments with Delays, Wait construct, Multiple Always Blocks,
Blocking and Non blocking Assignments, The case statement, if and if-else
constructs, Assign-de-assign construct, repeat construct, for loop, The
disable construct, while loop, forever loop, Parallel blocks, Force-release,
construct, Event.
Sr.no. QUESTION MARKS
Q.1. Explain behavioral modeling with the help of verilog code example 7

Q.2. what is construct and its types ?, explain any two of it . 8

Q.3. Design and implement 8:1 Multiplexure using Behavioral Modeling. 7
Q.4. Explain If else Construct with suitable example 5

Q.5. Explain with example case construct . 6

Q.6. explain loops in verilog . 8

Q.7. what is Behavioral modeling , explain with one example. 6

Q.8. Explain blocking and non-blocking statement with examples. 7

Q.9. Explain CASX construct . 5

Q.10. what is blocks in verilog ? explain different types of blocks with example. 6

Q.11. Design jk flip flop using behavioral modeling. 7

Q.12. what is latch ? explain with example. 5

Q.13. design D flip flop using behavioral modeling. 7

Q.14. explain Functional Bifurcation and what is force-release construct? 7
UNIT 4:

Synthesis of Digital Sub-systems:

Synthesis of Combinational Sub-systems: Introduction to Synthesis,
Synthesis of Combinational Logic, Synthesis of Sequential Logic with
latches, Synthesis of Three-state Devices and Bus Interfaces.
Synthesis of Sequential Sub-systems:
Synthesis of Seqeuntial Logic with Flip-Flops, Syntheisis of Explicit State
Machines, Registered Logic, State Encoding, Synthesis of Implicit State
Machines, Registers and Counters.
Sr.no. QUESTION MARKS

Q.1. what is Combinational Sub-systems and sequential sub-systems. 7

Q.2. Explain synthesis 5

Q.3. What is Synthesis of a digital systems? Explain in brief. 6

Q.4. what is registers and counters in verilog ? and its types. 7

Q.5. explain synthesis of combinational logic. 7

Q.6. explain synthesis of sequential logic with any one flip flop. 7

Q.7. design Synthesis of Seqeuntial Logic with Flip-Flops. 7

Q.8. design verilog code for verilog ripple counter . 6

Q.9. explain Synthesis of Three-state Devices . 6

Q.10. Explain Synthesis of Three-state Devices and Bus Interfaces. 7

Q.11 Design verilog code for register and counter. 6

UNIT 5:

System Implementation and User-Defined Primitives:

Introduction of Programmable Logic Array (PLA), Programmable Array
Logic(PAL), Programmability of PLDs, Complex PLDs (CPLDs), Field
Programmable GAte Arrays, The role of FPGAs in the ASIC Market,
FPGA Technologies, Verilog-Based Design Flows for FPGAs and ASICs.
Comparison of design implementation using CPLDs, FPGA and ASIC.

SR.NO. QUESTION MARKS

Q.1. what is PLA ? 7

Q.2. Explain PAL. With its advantages and disadvantages. 7

Q.3. What are the programmable logic devices ? write its advantages. 7

Q.4. what is ASIC ? give any two disadvantages of ASIC. 6

Q.5. List various internal blocks of FPGA. 6

Q.6. Explain the ASIC design flow in brief. Write short note on FPGA . 7

Q.7. Explain the difference between CPLD and FPGA and ASIC 8

Q.8. Difference between PLA and PAL. 7

Q.9. Explain design flows for FPGAs and ASICs. 7

Q.10. What is complex programmable logic devices ? 7
Q.11. Explain FPGAs and its applications. 7