Electrical & Electronic Equipment for Industrial Machinery

Digital

Phuong-Tung Pham, Ph.D.

Department of Mechatronics
Faculty of Mechanical Engineering

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CONTENTS

Digital Signals and Boolean Algebra

Logic Gates

Boolean Rules

Latch and Flip-flop

Counter

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 Digital Signals

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 Digital Signals
In digital circuits, binary bit values of 0 and 1
are represented by voltage signals measured in
reference to a common circuit point called
ground. An absence of voltage represents a
binary “0” and the presence of full DC supply
voltage represents a binary “1.”

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 Digital Signals

A single positive-going pulse is generated when the voltage goes from its normally
LOW level to its HIGH level then back to its LOW level.
A single negative-going pulse is generated when the voltage goes from its normally
HIGH level to its LOW level then back to its HIGH level

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Digital Signals

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 Boolean Algebra
Boolean algebra (Đại số Boole)
In Boolean algebra, a variable is a symbol used to
represent an action, a condition, or data. A single
variable only have a value of 1 or 0
Logic 0 Logic 1
False True
Off On
Low High
George Boole
No Yes (1815–1864)

Open switch Closed switch

A B x
Truth table (Bảng chân trị) 0 0 ?
0 1 ?
A 1 0 ?
Gate x
B 1 1 ?
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 Logic Gates

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 Logic Gate

A logic gate, or simply gate, is a special form of amplifler circuit designed to

input and output logic level voltages (voltages intended to represent binary
bits).
Gate circuits are most commonly represented in a schematic by their own unique
symbols rather than by their constituenttransistors and resistors.

The power supply connections to gates are often omitted in schematic diagrams for the
sake of simplicity

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 NOT Gate

An inverter, or NOT, gate is one that outputs the opposite state as what is
input. That is, a “low” input (0) gives a "high" output (1), and vice versa.

NOT
A x=A
0 1
1 0

x=A
A

NOT gate

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NOT Gate

Input Output

Input Output

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 OR Gate

The output of an OR gate will be “high“ (1) if any of the inputs are “high” (1).
The output of an OR gate goes "low" (0) if and only if all inputs are "low" (0).

OR
A B x=A+B
0 0 0
0 1 1
1 0 1
1 1 1

A x=A+B
B

OR gate
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 OR Gate
Boolean addition corresponds to the logical function of an “OR” gate, as well
as to parallel switch contacts:

A x=A+B
B

OR gate

Input A

Input B

Output

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 OR Gate
Application

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 AND Gate

The output of an AND gate will be “high“ (1) if and only if all inputs are “high” (1).
The output of an AND gate goes "low" (0) if any of the inputs are "low" (0).

AND
A B x = A.B
0 0 0
0 1 0
1 0 0
1 1 1

A x = A.B

AND gate

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 AND Gate
Boolean multiplication corresponds to the logical function of an “AND” gate, as
well as to series switch contacts:

A x = A.B

AND gate

Input A

Input B

Output

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 NOR Gate and NAND Gate
NOR gate
A x=A+B A B A+B A+B
B 0 0 0 1

NOR gate
0 1 1 0
1 0 1 0
A x=A+B 1 1 1 0
B

NAND gate

A x = A.B A B A.B A.B

B 0 0 0 1
NAND gate 0 1 0 1
1 0 0 1
A x = A.B
1 1 1 0
B

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 Negative-AND Gate and Negative-OR Gate
Negative-AND gate Negative-OR gate

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 XOR Gate and XNOR Gate
XOR gate XNOR gate

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 Utility of NOR Gate and NAND Gate
INVERTER
A A A A
1 1

AND

A AB x = AB A A
1 2 1
B x = AB
3
B B
2

OR
A A
1
x=A+B A A+B x=A+B
3 1 2
B
B B
2

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 Combinational Logic Circuits

A x = (A + B)·C A
A+B A·B x = A·B + C
B B
C C

A B C A+B (A + B)C A B C AB AB + C
0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 0 0
1 0 0 1 0 1 0 0 0 0
1 1 0 1 0 1 1 0 1 1
0 0 1 0 0 0 0 1 0 1
0 1 1 1 1 0 1 1 0 1
1 0 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1

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 Combinational Logic Circuits
Give the scheme

A
A
ABC
B
C
ABC(A + D)

A
A+D A+D
D

Determine the Boolean expression

x = ABC(A + D)
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 Combinational Logic Circuits
Give the Boolean expression
x = AB+BC

Draw the scheme

A AB x = AB + BC
B

B
BC
C

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 Boolean Rules

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Boolean Algebraic Identities

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Boolean Algebraic Properties

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Boolean Algebraic Properties

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 DeMorgan’s Theorems

DeMorgan’s Theorems describe the equivalence between gates with inverted

inputs and gates with inverted outputs. Simply put, a NAND gate is equivalent
to a Negative-OR gate, and a NOR gate is equivalent to a Negative-AND gate.

A+ B = A⋅B
A⋅ B = A + B

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Circuit simplification examples

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 Circuit simplification examples
A flame detection circuit for a toxic waste incinerator.
The intense heat of the fire is intended to neutralize the toxicity of the waste introduced into
the incinerator.
Due to the high degree of hazard involved with potentially passing un-neutralized waste out
the exhaust of this incinerator, it is decided that the flame detection system be made
redundant (multiple sensors)
Using "two out of three" sensor logic, whereby the waste valve is opened if at least two
out of the three sensors show good flame.

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 Circuit simplification examples
A flame detection circuit for a toxic waste incinerator.

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 Circuit simplification examples
A flame detection circuit for a toxic waste incinerator.
Using Boolean algebra techniques, the expression may be signiflcantly
simplifled:

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 Circuit simplification examples
A flame detection circuit for a toxic waste incinerator.

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 Minterm and Maxterm
Minterm (tích chuẩn) and Maxterm (tổng chuẩn)

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 Minterm and Maxterm
A flame detection circuit for a toxic waste incinerator.

Minterm
F ( A, B, C ) = ABC + ABC + ABC + ABC
= m3 + m5 + m6 + m7
Maxterm

F ( A, B, C ) = ( A + B + C )( A + B + C )( A + B + C )( A + B + C )
= M 0 + M1 + M 2 + M 4

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 Logic Gate Integrated Circuits

Logic gates can be

connected inside an IC
to create timers,
counters, latches, shift
registers, and other
basic logic circuitry.

IC 74LS00 IC 74LS08

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 Examples
Car safety alarm
Design a car safety alarm using Logic gates considering four input.
Alarm (A) should sound if:
Etheir (a) The key is in, and door is not closed
or (b) The door is closed, the key is in, and the driver is on seat, but the seat
belt is not strapped

Input Binary value Status

1 Door closed
Door (D)
0 Door open
1 Key is plugged into the car
Key (K)
0 Key is not plugged into the car
1 Driver is on seat
Seat (S)
0 Driver is not on seat
1 Seat belt is strapped
Belt (B)
0 Seat belt is not strapped

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 Examples
Car safety alarm
Design a car safety alarm using Logic gates considering four input.
Alarm (A) should sound if:
Statement (a) (K = 1) AND (D = NOT 1)
Statement (b) (D = 1) AND (K = 1) AND (S = 1) AND (B = NOT 1)

Binary
Input Status D
value
1 Door closed K
Door (D) Logic A
0 Door open
S Circuits
1 Key is plugged into the car
Key (K)
0 Key is not plugged into the car B
1 Driver is on seat
Seat (S)
0 Driver is not on seat
1 Seat belt is strapped
Belt (B)
0 Seat belt is not strapped
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 Examples
Car safety alarm
Design a car safety alarm using Logic gates considering four input.
Alarm (A) should sound if:
Statement (a) (K = 1) AND (D = NOT 1)
Statement (b) (D = 1) AND (K = 1) AND (S = 1) AND (B = NOT 1)

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Examples

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 Latch and Flip-flop

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 Latch and Flip-flop
In the same way that gates are the building blocks of combinatorial circuits,
latches and flip-flops are the building blocks of sequential circuits.

While gates had to be built directly from transistors, latches can be built from
gates, and flip-flops can be built from latches.

Both latches and flip-flops are circuit elements whose output depends not only
on the current inputs, but also on previous inputs and outputs.
The difference between a latch and a flip-flop is that a latch does not have a
clock signal, whereas a flip-flop always does.

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 Latch
S-R Latch: Activation of the S input sets the circuit, while activation of the R
input resets the circuit. If both S and R inputs are activated simultaneously, the
circuit will be in an invalid condition.

Invalid!

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 Latch
Gated S-R Latch

D Latch

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 Flip-flop
Flip-flop: A flip-flop is a latch circuit with a “pulse detector” circuit connected
to the enable (E) input, so that it is enabled only for a brief moment on either
the rising or falling edge of a clock pulse.
Pulse detector circuits may be made from time-delay relays for ladder logic applications, or
from semiconductor gates (exploiting the phenomenon of propagation delay)

Positive edge-triggered Negative edge-triggered

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 Flip-flop
S-R Flip-flop

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 Flip-flop
J-K flip-flop: A J-K flip-flop is an S-R flip-flop with an added layer of feedback.
This feedback selectively enables one of the two set/reset inputs so that they
cannot both carry an active signal to the multivibrator circuit, thus eliminating
the invalid condition.
When both J and K inputs are activated, and the clock input is pulsed, the
outputs (Q and not-Q) will swap states. That is, the circuit will toggle from a set
state to a reset state, or vice versa.

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 Flip-flop
J-K flip-flop

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 Counter
J-K flip-flop

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 Counter

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Binary count sequence
A four-bit binary count sequence from 0000 to 1111

Most signiflcant bit

(MSB)

Least signiflcant bit

(LSB)

• Circuits may be built that “count” in a binary sequence,

using J-K flip-flops set up in the “toggle” mode.
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 Asynchronous counters
Four J-K flip-flops
connected in such a
way to always be in
the "toggle" mode

Count up

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 Asynchronous counters
An "up" counter may be made by connecting the
clock inputs of positive-edge triggered J-K flip-
flops to the Q’ outputs of the preceding flip-flops.

Another way is to use negative-edge triggered flip-flops,

connecting the clock inputs to the Q outputs of the preceding
flip-flops.

In either case, the J and K inputs of all flip-flops

are connected to Vcc or Vdd so as to always be
"high.

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 Asynchronous counters
Ripple effect

Counter circuits made from cascaded J-K flip-flops where each clock input receives
its pulses from the output of the previous flip-flop invariably exhibit a ripple
effect, where false output counts are generated between some steps of the count
sequence.
These types of counter circuits are called asynchronous counters, or ripple counters.

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 Asynchronous counters
In many applications, the ripple effect is tolerable, since the ripple happens very, very
quickly
Ex: Drive a set of light-emitting diodes (LEDs) with the counter’s outputs
If we use this counter to drive the “select” inputs of a multiplexer, index a memory
pointer in a microprocessor (computer) circuit, it would not be acceptable.
There is a way to use this type of counter circuit in applications sensitive to false, ripple-
generated outputs, and it involves a principle known as strobing.

Essentially, the enable input of

such a circuit is connected to
the counter’s clock pulse in
such a way that it is enabled
only when the counter outputs
are not changing, and will be
disabled during those periods
of changing counter outputs
where ripple occurs

Another disadvantage of the asynchronous, or ripple, counter circuit is limited speed.

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 Synchronous counters
A synchronous counter, in contrast to an asynchronous counter, is one whose output
bits change state simultaneously, with no ripple.

Does this circuit function as a counter?

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Synchronous counters

A B C D

A B C D

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 Synchronous counters
Counter Circuit with Selectable “up” and “down” Count Modes

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 Applications
Up/down counter circuits are very useful devices.

A common application is in machine motion control, where devices called rotary shaft
encoders convert mechanical rotation into a series of electrical pulses, these pulses
“clocking” a counter circuit to track total motion:

As the machine moves, it turns the encoder shaft, making and breaking the
light beam between LED and phototransistor, thereby generating clock
pulses to increment the counter circuit.

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 Applications
If we re-design the encoder to have two sets of LED/phototransistor pairs, those pairs
aligned such that their square-wave output signals are 90o out of phase with each other,
we have what is known as a quadrature output encoder (the word “quadrature” simply
refers to a 90o angular separation).

A phase detection circuit may be made from a D-type flip-flop, to distinguish

a clockwise pulse sequence from a counter-clockwise pulse sequence

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 Counter IC
Asynchronous counter IC
• 74LS293: 4 bit counter
• 74HC4024: 7 bit counter (CMOS)
Synchronous counter IC
• 74LS163: synchronous 4-bit counter
• 74LS192:synchronous UP/DOWN
• 74LS193:synchronous UP/DOWN
IC 74LS293
• Four J-K Flip-flop (Q3Q2Q1Q0)
• Each flip-flop has a CP input, similar
to the CLK input.
• CP inputs of Q1 and Q0 are connected
with pin 11 and pin 10, respectively.
• Clear inputs of flip-flops are conneted
with output of a NAND gate which
has two inputs MR1 and MR2
• Q3Q2Q1 are a 3-bit counter
• Q0 is not connected with orther flip-
flop

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