1. Which model is used to denote the boolean functions?

I. switch level
II. gate level model
III. circuit level
IV. layout model

ANSWER: gate level model

2. Which among the following is a process of transforming design entry

information of the circuit into a set of logic equations?
I. Simulation
II. Optimization
III. Synthesis
IV. Verification

ANSWER: Synthesis

3. A FSM with 6 states requires at least:

I. 2-bit states
II. 3-bit states
III. 4-bit states
IV. None of the above

ANSWER: 3-bit states

4. The value of a displayed by the following code at time 30 is

#20 a <= 10;
#5 a <= 20;
I. 10
II. 20
III. 5
IV. None of the above

ANSWER: 10
5. The value of a displayed by the following code at time 30 is

#20 a = 10;
#5 a = 20;

I. 10
II. 20
III. 5
IV. None of the above

ANSWER: 20

6. What’s the keyword in Verilog testbenches to indicate that interrupts

the simulation with the possibility of resuming it?
I. $finish
II. $monitor
III. $stop
IV. $fish

ANSWER: $stop

7. Compared to the carry-lookahead adder, the ripple-carry adder is:

a. Slower

b. Faster

c. Smaller

d. Bigger

I. a & c
II. a & d
III. b & c
IV. b & d

ANSWER: a & c
8. _________ is the fundamental architecture block or element of a
target PLD.
I. System Partitioning
II. Pre-layout Simulation
III. Logic cell
IV. Post-layout Simulation

ANSWER: Logic cell

9. Which type of simulation mode is used to check the timing

performance of a design?
I. Behavioural
II. Switch-level
III. Transistor-level
IV. Gate-level

ANSWER: Gate-level

10. Which among the following is an output generated by synthesis

process?
I. Attributes & Library
II. RTL VHDL description
III. Circuit constraints
IV. Gate-level net list

ANSWER: Gate-level net list

11. Which type of digital systems exhibit the necessity for the existence of
at least one feedback path from output to input?
I. Combinational System
II. Sequential system
III. Both a and b
IV. None of the above

ANSWER: Sequential system

12. Hold time is defined as the time required for the data to ________
after the triggering edge of clock.
I. Increase
II. Decrease
III. Remain stable
IV. All of the above
ANSWER: Remain stable

13. Which type of MOSFET exhibits no current at zero gate voltage?

I. Depletion MOSFET
II. Enhancement MOSFET
III. Both a and b
IV. None of the above

ANSWER: Enhancement MOSFET

14. In logic synthesis, ________ is an EDIF that gives the description of

logic cells & their interconnections.
I. Netlist
II. Checklist
III. Datalist
IV. Dualist

ANSWER: Netlist

15.In floorplanning, placement and routing are __________ tools.

I. Front end
II. Back end
III. Both a and b
IV. None of the above
ANSWER: Back end

16.What is the difference between wire and reg?

Answer:
Wire is a net data type, represents connections between hardware elements.
It's default value is z. Where asreg is a register data type, which represent
data storage elements. Registers retain value until another value is placed
onto them. It's default value is x.

17.What is the difference between blocking and non-blocking

assignments?
Answer:
Blocking assignment statements are executed in the order they are specified
in a sequential block. A blocking assignment will not block execution of
statements that follow in a parallel block. The " = " operator is used to
 specify blocking assignments.
Nonblocking assignments allow scheduling of assignments without blocking
execution of the statements that follow in a sequential block. A " <= "
operator is used to specify nonblocking assignments.

18.What is the difference between ( = = , ! = ) and ( = = = , ! = = )?

Answer:
The equality operators ( = = , ! = ) will yield an x if either operand has x or z
in its bits. Where as the case equality operators ( = = = , ! = = ) compare
both operands bit by bit and compare all bits, including x and z.

19.What are the difference between Verilog and VHDL?

Answer:
Verilog is similar to C programming language (syntactically) and VHDL is
similar to ADA. Verilog is simple to learn and simple to write code where
as VHDL takes longer time to learn and is bit complicated when it comes to
write codes. Verilog supports lower level logic representation as well
(transistor level) where as VHDL does not.

20.How Latch are created in Verilog ?

Answer:

Latches are caused when all the possible cases of assignment to variable are not
covered.