Name: Bamidele Rafiyat Morolayo

Matric no: 22/47cs/2394

Level: 200l
Course: csc205 (assignment)
Department: Computer Science
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1. (a)
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(i) Assembly language is a low-level programming language that is closely related to machine
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language. It uses mnemonic codes to represent machine instructions.
(ii) The general format of an assembly language instruction consists of a label (optional), an
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operation code (opcode), and operands.
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(iii) Four advantages of assembly language are:
1. Direct hardware manipulation.
2. Increased speed and efficiency.
3. Easy debugging and testing.
4. Flexibility and control over program flow.

(b)
(i) Four problems of machine language leading to the development of assembly language are:
1. Difficulty in programming and understanding.
2. Lack of portability.
3. Error-prone due to binary representation.
4. Tedious and time-consuming programming process.
(ii) Three major types of language translator in computing are:
1. Assemblers: Translate assembly language code to machine language.
2. Compilers: Translate high-level language code to machine language.
3. Interpreters: Execute high-level language code directly without translation.

. (a)
. (i) Registers in the Central Processing Unit (CPU) are small, fast storage locations within
the CPU used to store data temporarily during processing.
. (ii) Functions of five important registers in the CPU:
. 1. Instruction Pointer (IP): Stores the address of the next instruction to be executed.
. 2. Accumulator (AX): Stores the results of arithmetic and logic operations.
. 3. Base Pointer (BP): Used for referencing parameters and local variables in procedures.
. 4. Stack Pointer (SP): Points to the top of the stack and is used for managing function calls
and local variables.
. 5. Status Register (FLAGS): Stores status information such as carry, zero, sign flags, etc.
(b)
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. (i) Differences between Complex Instruction Set Computer (CISC) and Reduced Instruction
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Set Computer (RISC):
. 1. CISC: Emphasizes complex instructions that can perform multiple low-level operations in
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a single instruction.
. RISC: Emphasizes a simpler instruction set with fewer instructions, each performing a
single operation.
. 2. CISC typically has variable-length instructions.
. RISC typically has fixed-length instructions.
. 3. CISC often has microcode control.
. RISC uses hardwired control.
. 4. CISC instructions may have different execution times.
. RISC instructions are uniform in execution time.
. 5. CISC tends to have more addressing modes.
. RISC tends to have fewer addressing modes.
. (ii) Two types of primary memory are:
. 1. Random Access Memory (RAM): Volatile memory used for temporary storage of data
and program instructions.
. 2. Read-Only Memory (ROM): Non-volatile memory that stores firmware instructions and
data that do not change during normal operation.

3. (a)
(i) 32 bits contain 4 nibbles.
(ii) 64 bits contain 8 bytes.
(iii) 1 gigabyte is equal to 1024 megabytes, so 1 gigabyte is equal to 1024 * 1024 kilobytes,
which is 1048576 kilobytes.
(iv) With 16 address lines, the computer can access \(2^{16}\) memory locations, which is 64K
(kilobytes) of memory.
(v) 24 kilobytes is equal to \(24 \times 1024\) bytes, which is 24576 bytes.
(vi) Intel data representation format is based on little endian.
(vii) The 2's complement of 1001010 is 0110110.
(viii) The 2's complement of 6A3D1 is 9592F.

(b)
(i) Given DS = 3499H and offset = 2500H:
(i) The physical address = DS:offset = 3499H:2500H = 5999H.
(ii) The logical address of the data being fetched = offset = 2500H.
(iii) The lower range of the data segment = DS = 3499H.
(iv) The upper range of the data segment = DS + segment size - 1 = 3499H + 64KB - 1 =
3499H + FFFFH = 12498H.
4. (a)
(i) A system bus is a communication system that transfers data between components inside a
computer or between computers.
(ii) Address bus is unidirectional while data bus is bidirectional.
(iii) Pipelining is a technique used in CPU design to improve performance by allowing multiple
instructions to be processed simultaneously in different stages of execution.

(b)
(i) Three features of 8086 microprocessor that were improvements over 8080/8085
microprocessor are:
1. 16-bit architecture instead of 8-bit.
2. Increased memory addressing capability.
3. Support for segmented memory model.
(ii) The major difference between 8088 and 8086 microprocessors is the data bus width. 8088
has an 8-bit data bus while 8086 has a 16-bit data bus.
(iii) The 8088 microprocessor has the larger queue, with a queue size of 4 bytes.

5. (a) Here are the operations performed on the given numbers:

(i) \(7C41_6 + 3BE1_6 = B002_6\)
(ii) \(59F1_6 - 2B81_6 = 2D70_6\)
(iii) \(23D9_16 + 94BE_16 = C895_16\)
(iv) \(1111_2 + 1010_2 = 11001_2\)
(v) \(11101_2 + 10101_2 = 110010_2\)
(vi) \(6A21_6 + 49A_6 = 6FBB_6\)
(vii) \(9FF2_16 - 4DD9_16 = 51B9_16\)
(viii) \(1066_16 + ABCD_16 = BB33_16\)

(b) Listing the 8086 registers:

(i) 16-bit general-purpose registers: AX, BX, CX, DX, SI, DI, BP, SP.
(ii) Pointer registers: IP (Instruction Pointer).
(iii) Index registers: SI (Source Index), DI (Destination Index).
(iv) Segment registers: CS (Code Segment), DS (Data Segment), SS (Stack Segment), ES
(Extra Segment).

6. (a) Reasons why each of the following instructions cannot be coded in 8088/86 assembly
language:
(i) MOV CS, 23AB: The `CS` (Code Segment) register cannot be directly loaded with an
immediate value. It is typically set by the system during initialization.
(ii) MOV BL, AX: The destination register (`BL`) is 8-bit, while the source register (`AX`) is 16-
bit. Direct copying from a 16-bit register to an 8-bit register is not allowed without explicitly
specifying the high or low byte.
(iii) MOV AL, 3CB5: The immediate value 3CB5 is 16 bits, but the destination register (`AL`) is
only 8 bits. Directly loading a 16-bit value into an 8-bit register is not possible.
(iv) MOV AX, 36DE5: The immediate value 36DE5 is 20 bits, which exceeds the size of the 16-
bit AX register. The 8088/86 architecture does not support immediate values of more than 16
bits.

(b)
(i) Assembly language instructions to add the values 16H and ABH and place the result in
register AX:
```
MOV AX, 16H
ADD AX, ABH
```
(ii) If AX = 24F6H and the instruction "MOV [1450], AX" were executed:
The contents of memory locations at offsets 1450 and 1451 would be 24F6H (in little-endian
format).

(iii) After the execution of the instruction "MOV [SI], AX":

The contents of memory locations at offset SI (2498) and SI+1 (2499) would be 17FEH and
24H, respectively.

7. (a)
(i) A stack is a data structure in computer systems used to store temporary data and manage
function calls and returns. It is needed to efficiently manage memory allocation and deallocation
during program execution.
(ii) When data is pushed onto the stack, the stack pointer is decremented, but when data is
popped off the stack, the stack pointer is incremented.
(iii) Contents of the stack as each instruction is executed:
```
PUSH AX: SP = 1234, [1234] = 24B6
PUSH BX: SP = 1232, [1232] = 85C2
PUSH DX: SP = 1230, [1230] = 5F93
 ```

(b) Using 2’s complement method:

(i) \(16_{10} - 25_{10} = -9_{10}\) in decimal or \(F7_{16}\) in hexadecimal.
(ii) \(19_{10} - 13_{10} = 6_{10}\) in decimal or \(6_{16}\) in hexadecimal.
(iii) \(27_{10} - 11_{10} = 16_{10}\) in decimal or \(10_{16}\) in hexadecimal.
(iv) \(13_{10} - 19_{10} = -6_{10}\) in decimal or \(FA_{16}\) in hexadecimal.

8. (a) Functions of each bit of the 8086 microprocessor flag register:

(i) Carry flag (CF): Indicates if an arithmetic operation resulted in a carry out of the most
significant bit.
(ii) Parity flag (PF): Indicates the parity (even or odd) of the result.
(iii) Auxiliary Carry flag (AF): Used for binary-coded decimal (BCD) arithmetic operations.
(iv) Zero flag (ZF): Indicates if the result of an operation is zero.

(b) Status of the CF, PF, AF, ZF, and SF bits of the flag register for the given operations:
(i) For the operation MOV BH, 38H; ADD BH, 2FH:
CF = 0, PF = 0, AF = 0, ZF = 0, SF = 0.
(ii) For the operation MOV BX, 94C2H; ADD BX, 323EH:
CF = 1, PF = 0, AF = 0, ZF = 0, SF = 1.

9. Conversions:
(i) 6DF₁₆ to decimal = 2783.
(ii) 0.375₁₀ to binary = 0.011₁₀.
(iii) 111010₁₀ to decimal = 58.
(iv) 438₁₀ to binary = 110110₁₀.
(v) 36₁₀ to binary = 100100₁₀.
(vi) 110011.11₂ to decimal = 51.75.
(vii) A6₁₆ to binary = 10100110₂.
(viii) 16₁₀ to decimal = 22.
(ix) 1474₁₀ to hexadecimal = 5C2₁₆.
(x) 11010011₂ to hexadecimal = D3₁₆.
(xi) 58₁₀ to hexadecimal = 3A₁₆.
(xii) 42₁₀ to binary = 101010₂.
(xiii) 0.5625₁₀ to binary = 0.1001₁₀.
(xiv) 111011.10₂ to decimal = 59.75.
(xv) FEC₁₆ to decimal = 4076.
10. (a) Physical address of the memory location and its contents after the execution of the given
instructions:
Assuming DS = 1512H:
MOV AL, 99H → No memory change.
MOV [3518], AL → Physical address: DS * 16 + 3518 = 1512H * 16 + 3518 = 241F8H. Contents:
99H.

(b) (i) Difference between ADD AX, BX and ADD AX, [BX]:
ADD AX, BX performs addition of the contents of BX register to AX register.
ADD AX, [BX] performs addition of the contents of the memory location addressed by BX
to AX.

(ii) Seven types of 8086 microprocessor addressing modes:

1. Immediate addressing
2. Register addressing
3. Direct addressing
4. Indirect addressing
5. Indexed addressing
6. Base addressing
7. Relative addressing

11. (a) Physical memory location where AX is stored for each instruction:
(i) MOV [BP] + 12, AX: Physical address = SS * 16 + (BP + 12) = 2000H * 16 + (7814H + 12) =
24012H.
(ii) MOV [SI] + 10, AX: Physical address = DS * 16 + (SI + 10) = 4500H * 16 + (1486H + 10) =
703A6H.
(iii) MOV [BX] + 20, AX: Physical address = DS * 16 + (BX + 20) = 4500H * 16 + (2100H + 20) =
84820H.

(b) 8086 microprocessor's addressing mode for each instruction:

(i) MOV AX, 32DEH: Immediate addressing.
(ii) MOV AL, [BX]: Direct addressing.
(iii) MOV DX, [BP + DI + 4]: Indexed addressing.
(iv) MOV AX, DX: Register addressing.
(v) MOV CX, [BX + 10]: Indexed addressing.
(vi) MOV DL, [2400]: Direct addressing.
(vii) MOV BL, [SI + 10]: Indexed addressing.