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En - APEC2017 Exhibitor Seminar DigitalControl IC 1
En - APEC2017 Exhibitor Seminar DigitalControl IC 1
• PFC Basics
• Interleaved PFC Concept
• Analog Vs Digital Control
• The STNRGPF01 Digital Controller
• Main Functions
• Edesign suite GUI
• Application Example:
• 3kW Three channel Interleaved PFC
• Performance Evaluation
• Conclusions
Power Factor Correction 5
A PFC pre-regulator placed between the bridge and the bulk capacitor draws a
quasi-sinusoidal current from the mains, in-phase with the line voltage
Maximize the energy delivery to load means to reduce the Total Harmonic
Distortion (THD) and therefore maximize the Power Factor
Introduction to PFC 4
EMI Main
Rectifier PFC Load
Filter Converter
SMPS Structure
• Operation modes:
• Continuous Conduction Mode (CCM) > 350W
• Transition Mode (TM) <350W
• Discontinuous Conduction Mode (DCM)
PFC – Control Technique 8
Average current control Low distortion on input current Two control loops
Peak Current control Fast current correction High distortion on input current
I1
L1
DC/DC
Load
M1
+ or
PFC
controller
Ic DC/AC
Phase1
In
LN
Mn
Phase n
Example: 3kW iPFC 10
Switching frequency 100kHz
Single Channel
Interleaved 3 Channels
45% Less!
Output Capacitor Ripple Current Reduction 11
0.5
Triple Channel
0
0 0.5 1
%D
• TSSOP38 Package
• Mixed Signal Control
• Configurable By GUI
The STNRGPF01: Overview 14
• Semi-digital control
• Analog current controller
• Voltage controller, feed-forward compensation, multiplier, PWM clock generator and non-
time critical protection functions are implemented digitally.
• ZVD Sensing
STNRGPF01: Current Loop 17
Itot_ref
Itot_fb
STNRGPF01: Driving and Interleaving 18
BoM + SCHEMATIC
The device performance have been evaluated developing a 3kW Three channels PFC.
• Pout = 3kW @ Vin = 230Vac; 1.5kW @ Vin = 110Vac • Load feed forward
• Vout = 400V • Working frequency = 111kHz per channel
• PF > 0.98 @ 20% load • Thermal protection set at 120°C
• THD < 5% @ 20% load • Current protection set at 33A
• CCM with analog current control loop • Direct fan driving
(cycle by cycle regulation) • Current reference realized by internal map (200 pt)
• Input Voltage feed forward
PWM master
Experimental Results: Load Feed Forward 22
DC Bus voltage
Input current
The load feed forward when load step is applied reduces the over and
under voltage of the output dc bus voltage!
Experimental Results: Load Feed Forward 23
DC Bus voltage
Input current
The load feed forward when load step is applied reduces the over and
under voltage of the output dc bus voltage!
Experimental Results: Load Feed Forward 24
DC Bus voltage
Input current
The PFC interrupts the Burst Mode to meet the load requirement and
when load is disconnected it returns in Burst Mode.
Experimental Results 25
Efficiency and ITHD%
Conclusions 26
Thank You!