UD001 4.7 Hardware UserManual

SIEMENS EDA
proFPGA Hardware User

Guide
Software Version 2022A-SP2
Document Revision 4.7
Unpublished work. © 2022 Siemens
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Revision History
Note
The previous versions of this document contained section, table, and figure numbers that are
no longer relevant. The current version of this document does not include section numbers.
Also, tables and figures follow a different nomenclature. Therefore, this revision history does
not include hyperlinks.
This document has been converted to the Siemens documentation standards in revision 4.06
which supports both HTML and PDF outputs.
Revision Date Author Comments

0.1 2012/11/27 sfluegel initial document setup
0.2 2012/11/29 sfluegel increased version after initial revision
of TOC
0.3 2012/12/06 cfranke table of contents updated
table 12 in chapter 3.1.6 updated
0.4 2012/12/06 sfluegel added chapter 4 (FPGA modules)
0.5 2013/01/02 mberger document reviewed and cleaned up
1.0 2013/03/01 cfranke chapter 1 Picture added
chapter 2.1.3 Picture added
chapter 3.1.2 Pictures and Board
description added
cleaned up
1.1 2013/03/13 sfluegel corrected clock #0 frequency to 100
MHz
1.2 2013/05/15 sfluegel document style updated
1.3 2013/06/06 sfluegel update of chapter 4 (added more
FPGA modules)
started chapter 5 (extension boards)
1.4 2013/07/04 mberger some more extension boards added
1.5 2013/07/09 mdjekic updated sections about IC-PDS-
CABLE-R1, IC-PDS-EW-R2 and IC-
PDS-NS-R2
proFPGA Hardware User Guide, v2022A-SP2
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
1.6 2013/07/09 cfranke updated sections about extension
boards: EB-PDS-MGT-MMCX-R1,
EB-PDS-FMC-R1, FMC-
PROFPGA-R1
1.7 2013/07/11 msteinacker updated chapter 6.7 4-way
Interconnect (IC-PDS-4WAY-R1)
1.8 2013/07/11 mdjekic updated figures in sections about IC-
PDS-EW-R2 and IC-PDS-NS-R2
1.9 2013/07/18 ddukaric Updated section PCIe Cable Kit
1.10 2013/07/25 mberger corrected clock #0 frequency to 100
MHz
power-up sequence corrected
proFPGA PCIe DMBI Kit added
more details to FPGA modules added
proFPGA PCIe gen2 8-lane Kit
corrected
EB-PDS-DEBUG-R1 added
MGT Debug Board corrected
FMC Mezzanine Board adapter
corrected
FMC Carrier Board adapter corrected
1.11 2013/07/29 mberger some images corrected which were
not visible correctly in PDF view
1.12 2013/08/15 msteinacker added chapter for EB-PDS-USB3-R1
added comment in chapter 5.22.1
added changes regarding ac coupling
of MGT board
1.13 2013/08/27 sfluegel update to new document naming
style
1.14 2013/08/27 sfluegel complete review
1.15 2013/09/03 msteinacker updated chapter 5.41 USB 3.0 Board
(EB-PDS-USB3-R1)
1.16 2013/09/10 msteinacker reviewed
1.17 2013/11/28 sfluegel TOC updated
1.18 2014/01/16 mberger MB-2M and MB-1M added; MB-4M
updated
4 proFPGA Hardware User Guide, v2022A-SP2
1.19 2014/01/30 kkohl Added chapter 5.8 – EB-PDS-DDR3-
SODIMM-R2
1.20 2014/02/12 mberger Added chapter 5.43 GBit Ethernet
Board (EB-PDS-GBITETHERNET-
R1)
1.21 2014/03/14 cfranke Changed revision of FMC extension
board (EB-PDS-FMC) to R2
1.22 2014/03/18 sfluegel images compressed
1.23 2014/04/09 mberger (re-)added EB-PDS-FMC-R1
1.24 2014/04/14 droeder Added chapter 5.44 DVI Input and
Output Board (EB-PDS-DVI-R1)
1.25 2014/04/22 sfluegel added MGT pins to 2000T floorplan
1.26 2014/04/22 msteinacker added chapter 5.61 Riser Board (EB-
PDS-RISER-R1)
1.27 2014/05/15 msteinacker added chapter 5.45 QSFP+ Extension
Board (EB-PDS-QSFP+-R1)
added chapter 5.28 PCIe 4-lane host
interface card
(PCIex4_HostCableAdaptor-R1)
updated chapter 3.2.4 proFPGA PCIe
DMBI Kit
1.28 2014/06/11 droeder added chapter 5.47 MIPI DPHY RX
(EB-PDS-MIPI-DPHY-RX-R1)
1.29 2014/06/26 droeder updated chapter 5.47 MIPI DPHY
RX (EB-PDS-MIPI-DPHY-RX-R1)
1.30 2014/07/29 droeder updated chapter 5.55.2 Table 341:
EB-PDS-DVI-R1– extension board
operating conditions
FPGA Extension Site Compatibility
updated chapter 5.47.3 Table 358:
EB-PDS-MIPI-DPHY-RX-R1 –
extension board operating conditions
1.31 2014/09/11 cfranke added chapter 4.2 concerning Zynq
FMs
added chapter 5.2
updated table 65
proFPGA Hardware User Guide, v2022A-SP2 5
1.32 2014/09/25 cfranke updated chapter 4.2 Zynq7000 FPGA
Modules
1.33 2014/10/27 cfranke added chapter regarding X485T
FPGA
1.34 2014/11/26 cfranke Added chapter 5.16 proFPGA
Interface Board
1.35 2014/11/26 kkohl Added chapter 5.17 proFPGA EB-
PDS-SATA-R2
1.36 2014/11/26 sfluegel update of EB-PDS-FMC
compatibility matrix, review of
figures
1.37 2015/02/04 msteinacker, updated chapter 5.41.1 Functional
sfluegel Description (USB 3.0 Board (EB-
PDS-USB3-R1))
added description of User FPGA
LEDs (section 4.1.1)
1.38 2015/02/04 cfranke Added EB-PDS-DEBUG-R2
extension board chapter
1.39 2015/02/12 cfranke Updated chapter 4.2 Zynq7000
FPGA Modules
1.40 2015/02/26 mberger Release 2015A
1.41 2015/03/19 msteinacker Added chapter 5.42 USB 2.0(UTMI)
& 3.0(ULPI) Interface Board (EB-
PDS-USB2-3-R1/R2)
1.42 2015/03/25 sfluegel added direction of UART pins
correct connector naming f UNO MB
1.43 2015/04/10 cfranke Figure 64 updated
msteinacker Updated chapter 5.22 PCIe gen1 8-
lane Kit (EB-PDS-PCIe-Cable-R2)
Added chapter 5.24 PCIe gen3 8-lane
Kit (EB-PDS-PCIe-Cable-R5)
Updated chapter 5.44.5 Related
Work
1.44 2015/05/20 msteinacker added chapter 4.3 Virtex Ultrascale
FPGA Module
updated FPGA extension site
compatibility tables with FM-
XCVU440-R1 and FM-
XC7VX485T-R3
1.45 2015/06/12 msteinacker corrected error in broken link for
Table 209 where the table was shown
twice
1.46 2015/07/07 msteinacker updated Figure 64 and Table 51
1.47 2015/07/21 cfranke Added Table 381
1.48 2015/07/22 sfluegel added bank assignment of
XCVU440-R2 FPGA
1.49 2015/08/31 mberger clock frequency range for multi-
motherboard clock distribution added
1.50 2015/09/01 cfranke chapter 5.50 updated
1.51 2015/09/07 mberger Support for CLK_DIR signal
removed for FMC-PROFPGA-R1
and EB-PDS-FMC-R1/R2
1.52 2015/09/10 msteinacker added chapter 5.59 ADC Board (EB-
PDS-ADC250x16-R2)
1.53 2015/09/11 droeder
kkohl
1.54 2015/09/14 mberger IC-PDS-CABLE-R2/R3 added
Zynq 7000 to extension board
compatibility matrices added
extension board sections reorganized
document reviewed
1.55 2015/09/14 mribke added chapter 6.6 Breakout
Board(EB-PDS-BREAKOUT-R1)
1.56 2015/09/16 mberger EB-FM-XCVU440-R1 added
1.57 2015/09/18 mberger EB-PDS-DDR4-R2/R3 added
support email address added
chapter 6.6 updated
1.58 2015/09/22 kkohl EB-PDS-INTERFACE-R2
Description refined
1.59 2015/09/22 mberger images compressed
order codes for EB-FM-XCVU440-
R1 added
1.60 2015/09/29 msteinacker corrected Figure 179
corrected contents of FPGA
extension site compatibility tables for
FM-XC7V2000T-R1
updated Figure 33, Figure 34, Figure
35
1.61 2015/11/06 msteinacker updated Figure 64
updated chapter 5.1 DDR4 Extension
Board with 2.5 Gbyte (EB-PDS-
DDR4-R2/R3)
1.62 2015/11/17 cfranke/ mberger EB-PDS-ARM-EXPRESS-R1 added
1.63 2015/11/19 mberger typo fixed in feature description of
EB-PDS-GBITETHERNET-R1
1.64 2016/01/07 msteinacker updated Table 51
1.65 2016/01/13 msteinacker updated 5.1.4 FPGA Pin Constraints:
added a hint by using the XILINX
MIG to not change the automatically
generated FPGA pin constraints
1.66 2016/02/03 mribke add EB-PDS-RnS-Tester R1, EP-
PDS-DEBUG-R3 and update EB-
PDS-BREAKOUT-R2
1.67 2016/02/04 msteinacker updated Figure 45: Mapping of FM-
XC7VX485T-R3 I/O banks to
connectors. All banks are 7-series
High-Performance banks
(PV_IOmax=1.8V).
updated Table 29: FM-XC7VX485T-
R3 – Board connectors.
Updated chapter 5.1.5 Related Work
updated chapter 5.42.1 Functional
Description
added chapter 5.19 286490
Flash Board (EB-PDS-FLASH-R1/
R2)
1.68 2016/02/12 cfranke added hint to chapter 5.50 regarding
stacking height
chapter 5.50.1 updated
1.69 2016/03/10 msteinacker Updated chapter 5.11 DDR3
Extension Board with 2 Gbyte (EB-
PDS-DDR3-R2) due to component
discontinuation
1.70 2016/03/14 kkohl Added Erratum in SATA Extension
Board (EB-PDS-SATA-R2/R3)
1.71 2016/03/21 mberger License agreement changed; link
fixed in section 5.57; I/O constraints
for clock and sync signals added;
document name of reference
[UD006] fixed; I/O standards of
UART and user LEDs added to each
FPGA module; description for
200 MHz fixed reference clock to
EB-PDS-DDR3-R2/R3 added
1.72 2016/03/30 cfranke Figure 8 updated
1.73 2016/05/03 cfranke Zynq FPGA added to compatibility
lists in chapters 5.22.3, 5.23.3, 5.25.3
1.74 2016/05/04 msteinacker updated chapter 5.1 DDR4 Extension
Board with 2.5 Gbyte (EB-PDS-
DDR4-R2/R3)
1.75 2016/05/18 mribke EB-PDS-MULTIMEMORY-R1
added
1.76 2016/06/06 msteinacker updated chapter 5.41 USB 3.0 Board
(EB-PDS-USB3-R1)
updated chapter 5.23 PCIe gen3 8-
lane Kit (EB-PDS-PCIe-Cable-R2/
R3)
updated chapter 5.24 PCIe gen3 8-
lane Kit (EB-PDS-PCIe-Cable-R5)
PCIe 4-lane host interface card
1.77 2016/06/21 droeder added revision R3 of FMC extension
board
added EB-PDS-FMC-LPC-R1
1.78 2016/07/04 cfranke Warning about limitation of ARM
JTAG connector added to chapters
5.31, 5.32 and 5.33
1.79 2016/07/29 cfranke Table 153, Table 157, Table 53, and
Table 172 updated
1.80 2016/08/10 msteinacker updated Table 203, Table 209
1.81 2016/09/05 msteinacker updated chapter 2.3.2 Clocking
Hardware
updated chapter 2.5 JTAG
updated chapter 2.6 MMI-64
Communication
updated chapter 2.7.1 Clock
Distribution
updated Table 203, Table 209, Table
232
1.82 2016/09/27 msteinacker added chapter 5.26 PCIe Root
Complex and M.2 Extension Board
(EB-PDS-ROOT-COMPLEX-M.2-
R1)
1.83 2016/10/21 droeder added chapter 4.4 Kintex Ultrascale
FPGA Module
added FM-XCVU190-R1
added FM-XCVU160-R1
added FM-XCVU125-R1
added FM-XCVU095-R1
added FM-XCVU080-R1
added FM-XCKU115-R1
compatibility tables with new FPGA
Modules
1.84 2016/10/28 cfranke chapter 4 reviewed
demo designs updated
1.85 2016/12/12 msteinacker updated Table 203, Table 209, Table
232, Table 238 for Ultrascale
Devices
added additional information for
boards which uses Si5338 clock
generator for better usability
1.86 2017/01/06 cfranke Chapter ‘Known Issues’ added to
5.51 Interface Board (EB-PDS-
INTERFACE-R2)
1.87 2017/01/16 cfranke added EB-PDS-DEBUG-R4 board
chapter
Warnings regarding JTAG debugger
drive strength added to chapters 5.31,
5.32, 5.33 and 0
1.88 2017/01/20 mlangner added package of FPGAs and
minimum firmware requirements,
information regarding 200MHz
refclk of EB-PDS-DDR3-R2/3 board
added
1.89 2017/02/01 cfranke updated Table 60: FM-XCVUxxx
FPGA pin constraints
updated Table 68: FM-XCKU115-R1
FPGA pin constraints
updated chapter 2.3.3
added chapter 4.1.10, 4.2.17, 4.3.10
and 0
1.90 2017/02/08 msteinacker updated chapter 5.1.2 Table 108: EB-
PDS-DDR4-R2/R3 – extension board
operating conditions
EB-PDS-FLASH-R1/R2– extension
board operating conditions
FPGA Extension Site Compatibility,
EB-PDS-SRAM-R1/2 – extension
FPGA Extension Site Compatibility,
EB-PDS-PCIE-Cable-R2 – extension
updated chapter 5.25.3 Table 231: :
EB-PDS-ROOT-COMPLEX-M.2-
R1 – extension board operating
conditions
1.91 2017/02/17 mribke Update chapter 5.33
1.92 2017/02/27 mberger Legal information updated, images
compressed
1.93 2017/03/07 msteinacker Added chapter 5.17 LPDDR4
PDS-LPDDR4-R1)
Added chapter 5.29 Mini PCIe host
interface card
Updated chapter 5.28 PCIe 4-lane
host interface card
1.94 2017/03/20 kkohl Updated chapter 5.50.2 Table 387:
EB-PDS-INTERFACE-R2 –
extension board operating conditions
1.95 2017/04/06 kkohl Corrected 5.57.4 example config
entries
1.96 2017/04/10 kkohl Corrected CLK1/3_SEL in Figure
374
1.97 2017/04/13 cfranke Added chapter 5.3.4
1.98 2017/04/20 droeder Added chapter 4.5 Virtex Ultrascale+
FPGA Module
added FM-XCVU7P-R1
compatibility tables with new FPGA
Modules
1.99 2017/04/21 mribke Add Chapter 5.2 EB-PDS-DDR4-R4
board
2.0 2017/04/26 msteinacker Added several order codes
Updated titles of memory boards
with capacity
Updated DDR4 memory groups that
can be used in 40- / 48-bit mode
2.1 2017/05/04 kkohl Cross reference restored in 5.57
2.2 2017/05/22 mribke Add DDR4 18Gbyte Board
2.3 2017/06/07 cfranke Table 321 added for VIO voltage
jumper settings
2.4 2017/07/18 droeder Add Stratix 10 FPGA Module
2.5 2017/07/21 msteinacker Updated chapter 5.29 Mini PCIe host
interface card
(MPCIe_HostCableAdapter-R1)
Updated description of Table 109
2.6 2017/07/27 ddukaric Updated sections for 5.2 and 5.3
2.7 2017/08/01 kkohl Updated chapter 5.20
2.8 2017/08/11 mribke Update EB-PDS-DEBUG-SWDIO-
R3
2.9 2017/08/18 cfranke Figure 409 in chapter 6.1 updated/
reworked
2.10 2017/08/23 cfranke Figure 409 in chapter 6.1 simplified
2.11 2017/09/01 droeder Updated Figure 75 and Table 62 in
Chapter 4.4
2.12 2017/09/06 cfranke Wrong reference to non-existing
clock reference manual removed
2.13 2017/09/14 mberger I/O standard for DMBI/UART/LED
signals of 7-Series FPGAs corrected
2.14 2017/09/14 droeder Added Table 99: Stratix10
Temperature Monitor IP Status
2.15 2017/09/15 cfranke Outdated references to AN034
changed to AN037
2.16 2017/11/01 cfranke Removed mistakenly documented
MGT connections in East-West and
North-South EB chapters
2.17 2017/11/17 cfranke Added FM-XCVU9P FPGA module
2.18 2018/02/09 cfranke Added Stratix X Extension Board
Compatibilities
2.19 2018/02/22 mberger Added draft for Zynq Ultrascale+
FPGA modules
2.20 2018/02/22 cfranke Added EB-FM-XCZUxxEG-R2
chapter
3.00 2018/02/23 mribke Add MB-4M-R3 (Generation 2
Motherboard)
3.01 2018/03/02 droeder Added FM-XCVU5P-R1 FPGA
chapter
Added FM-XCVU440-HP-R1 FPGA
chapter
Added FM-1SG280L-S2-R1 chapter
3.02 2018/03/13 kkohl Added chapter Flexible Riser Board
(EB-PDS-FLEXRISER-R1)
3.03 2018/03/13 msteinacker Reviewed chapter Motherboards
Added PCIe DMBI Kit Gen2
Reviewed chapter ZYNQ Ultrascale+
modules
3.04 2018/03/13 Mribke Added a distinction of Generation 1
and Generation 2
motherboards in Chapter:
Systemoverview -> Board Types and
Board Connections, Coordinate
System, Naming Conventions
Added differences between
Generation 1 and Generation 2 in
chapter Clocks, JTAG and MMI64
Added Advice for Multimotherboard
system
Expanded an example for
Multmotherboard system with a
Generation 2 Motherboard
Splitted chapter Motherboards into
Generation 1 and Generation 2
Motherboards
Added list of Generation 2 feautures
Moved Chapter Motherboards ->
PCIe DMBI Kit into Motherboard ->
Generation 1 -> PCIe DMBI Kit
Updated DDR4-R4/R5 compatibility
list
3.5 2018/03/13 vscholz Typo review
3.6 2018/03/15 mribke Added note for multi motherboard
setup with Gen1 and Gen2 in chapter
Mutli-Motherboard-Systems
3.7 2018/03/27 droeder Added FM-1SG280L-S2-R2 chapter
updated Table 232
3.8 2018/04/12 cfranke Fixed Figure 179
3.9 2018/04/16 droeder Added DDR4 Extension Board for
Intel FPGAs with 4 GByte (EB-PDS-
DDR4-R8)
Added Known issues to FM-
1SG280L-R1 chapter
Added Chapter Differences between
FM-1SG280L-R1 and FM-
1SG280L-R2
3.10 2018/04/20 kkohl Updated chapter 5.51.13 SD Card
Slot
Added chapter Interface Board (EB-
PDS-INTERFACE-R3)
PDS-INTERFACE-R4)
PDS-INTERFACE-R5)
3.11 2018/04/24 msteinacker Updated Chapter 5.66 Zynq US+
Interface Board (EB-FM-
XCZUxxEG-R2/R3)
Updated Table 238
mberger
Usage of XILINX Memory Interface
Generator for EB-PDS-DDR4-R4
and EB-PDS-DDR4-R5 updated
3.12 2018/05/28 msteinacker Updated chapter 5.66.13 Clock
Generator
Updated Figure 103: Zynq
Ultrascale+ FPGA Module Overview
3.13 2018/08/06 mstacheter Added chapter FMC Bank A
Mezzanine Board Adapter (EB-PDS-
FMC-BANK-A-R1)
3.14 2018/09/11 cfranke Missing VU+ modules added to
compatibility lists
rwinkler ZU+ modules added to compatibility
lists
FM-XC7Z100 and FMXC7Z045
compatibilities of TA1 connector
fixed
3.15 2018/09/21 cfranke Noise values of the system added
3.16 2018/10/16 kkohl EB-PDS-INTERFACE-R2 – R4
marked as obsolete (ch. 5.51, 5.52,
5.53)
3.17 2018/10/17 ddukaric Added FM-1SG280H-S3-R1 module
3.18 2018/10/19 droeder FM-1SG280L-R2 module added to
compatibility lists
3.19 2018/11/09 mribke Added EB-PDS-INTERFACE-R7
3.20 2018/11/20 msteinacker Updated Table 460: EB-FM-
XCZUxxEG-R2/R3– FPGA
extension site compatibility
3.21 2018/11/26 mstacheter Added R2 device to Chapter 5.42
USB 2.0(UTMI) & 3.0(ULPI)
Interface Board (EB-PDS-USB2-3-
R1/R2)
3.22 2019/02/01 kkohl Added chapter 5.15 DDR3 SODIMM
Board (EB-PDS-DDR3-SODIMM-
R4)
3.23 2019/02/08 msteinacker Updated 5.19 Flash Board (EB-PDS-
FLASH-R1/R2) with information
about EB-PDS-FLASH-R2
3.24 2019/02/08 mribke Updated 5.23 EB-PDS-DEBUG-
SWDIO-R3)
3.25 2019/02/20 cfranke Examples in chapter 2.1.2.2 fixed
3.26 2019/04/08 cfranke Missing flash memories in chapter
msteinacker 5.19 added
Updated chapter 5.66 Zynq US+
Interface Board (EB-FM-
XCZUxxEG-R2/R3)Updated Figure
103: Zynq Ultrascale+ FPGA
Module Overview
3.27 2019/04/12 droeder added chapter 4.8 Arria 10 FPGA
Module
FM-10AX115-R1 module added to
compatibility lists
3.28 2019/04/17 cfranke Updated chapter 5.44.5 concerning
Register Map Generation
3.29 2019/04/24 mberger Discontinued EB-PDS-DDR4-R4.
3.30 2019/04/26 mberger Order code PROF-A-I-PCIe-4-AO
replaced with PROF-A-MI-HICPCI
and PROF-A-MI-HIC
3.31 2019/05/02 mribke Update EB-PDS-DDR4-R5 with new
measurement results
3.32 2019/05/10 cfranke Figure 133 fixed
Title of chapter 5.56 fixed
3.33 2019/05/10 mribke Added option for plugin-async-event
to:
all DDR4 Ebs
PCIe Root Complex and M.2 EB
DVI Input Output EB
QSFP+ EB
SATA EB
ADC EB
DUAL DAC EB
ZYNQ US+ Interface EB
Set order status of LPDDR4 EB to
discontinued
3.34 2019/05/15 mberger Hints to generate MIG for EB-PDS-
DDR3-R3 added
3.35 2019/05/16 cfranke Warning message in chapter 5.54.12
fixed
3.36 2019/05/27 ddukaric Update EB-PDS-DDR4-R8 with
Arria 10 results
3.37 2019/06/14 mribke Added additional informations for a
plugin async event option
Update EB-Interface-R7 product
picture
3.38 2019/06/19 cfranke Reviewed changes for plugin async
event option
3.39 2019/07/01 mribke Added workaround proFPGA file
generation in Builder for ARM
Express Adapter Board
3.40 2019/07/12 cfranke Compatibiliy list of chapter 5.60.2
for VUS+ fixed
3.41 2019/08/22 msteinacker Added chapter 4.6.8 PUDC_B
(ZYNQ Ultrascale+)
3.42 2019/08/28 mberger Legal notice added
3.43 2019/09/29 msteinacker Changed Pro Design to PRO
DESIGN in several cases
Fixed Table 125: EB-PDS-DDR4-R8
– FPGA extension site compatibility
Fixed Table 92: FM-XCZUxxEG-R2
FPGA Modules Demo Designs
Added ordercode for EB-PDS-
FLASH-R2 (5.19.6)
3.44 2019/10/18 msteinacker Updated Figure 409 in chapter 6.1
Interconnect Cable (IC-PDS-
CABLE-R1/R6)
3.45 2019/10/24 mberger Misleading sub section “Signal
Mapping” of IC-PDS-CABLE-R2/
R3 removed.
3.46 2019/11/05 droeder added FM-1SG280H-R2
3.47 2019/11/07 msteinacker Added FM-1SG10M-R1
3.48 2019/11/08 cfranke Figure 390 fixed
3.49 2019/11/27 mberger proFPGA PCIe gen3 8-lane Kit for
Stratix 10 added to section 5.23 PCIe
gen3 8-lane Kit (EB-PDS-PCIe-
Cable-R2/R3)
3.50 2020/01/06 msteinacker Added FM-XCVU13P-R1
Added IC-PHS-CABLE-R1
3.51 2020/01/30 cfranke Chapter 4.5 concerning MGT
reference clocks at V2 connectors
3.52 2020/02/10 cfranke chapter 6.2 for 1:1 Interconnection
Cable added
3.53 2020/02/12 pudhardt Added FM-XCVU37P-R1
3.54 2020/02/12 mribke Added EB-PDS-QSFP28-R1
3.55 2020/02/19 mribke Added EB-PDS-FMC-REDUCED-
R1
3.56 2020/02/24 pudhardt Virtex Ultrascale+ rework, XCVU-
x7P-R1 optionally supporting power
connector added
3.57 2020/02/25 mstacheter Added SATA Extension Board (EB-
PDS-SATA-R4)
Added hint to SATA Extension
Board (EB-PDS-SATA-R2/R3) that
boards are obsolete
3.58 2020/03/05 cfranke Footnotes of Note 1 : XMBA2 does
not provide an I/O Voltage, the
PV_IO_RUN is driven low by the
FPGA Module
Note 2 : XMBB2 supports only an I/
O voltage of 1.8V
Table 73 fixed
3.59 2020/03/13 mribke Added additional information for
Clock generation of QSFP28
Extension Board (EB-PDS-QSFP28-
R1)
3.60 2020/04/02 ddukaric Updated multi-motherboard
frequency range for distributed
clocks
3.61 2020/04/03 msteinacker Merged UD013 information for FM-
1SG10M-R1 into this document (4.7)
Added motherboard compatibility
information for FM-1SG10M-R1
(4.7.6)
3.62 2020/04/03 cfranke Direction of Display Port clarified in
5.66
3.63 2020/04/17 droeder Added FM-XCVU19P-R1 (4.5.2.6)
Added FM-XCVU47P-R1 (4.5.2.5)
Updated FPGA extension site
compatibility tables
3.64 2020/04/24 msteinacker Added chapter 5.62 V2 Riser Board
(EB-PHS-RISER-R1)
Added chapter 6.9 V2 Breakout
Board (EB-PDS-BREAKOUT-R3)
Updated chapter 6.8 Breakout Board
(EB-PDS-BREAKOUT-R2)
3.65 2020/05/08 msteinacker Added additional information for
Stratix FPGA modules (4.7.1)
3.66 2020/05/19 msteinacker Added additional information for
EB-PDS-BREAKOUT-R3 (6.9.4)
3.67 2020/05/27 msteinacker Added EB-PDS-USB2-3-R3 (5.42)
Added explanation for vref_source
and oct_resistor to Stratix 10 FPGAs
(4.7.2.2, 4.7.2.3)
3.68 2020/07/14 mribke Added EB-PDS-DDR3-R6
3.69 2020/08/19 msteinacker Updated chapter 4.5.3 Reference
Clocks at V2 Connectors
3.70 2020/09/04 droeder Added DDR4 Extension Board for
Intel FPGAs witch 8 GByte (EB-
PDS-DDR4-R10)
3.71 2020/09/15 msteinacker Added chapter 5.27 PCIe Root
Complex Extension Board (EB-PDS-
ROOT-COMPLEX-R1)
3.72 2020/10/30 droeder Added chapter 5.7 DDR4 Extension
Board for Intel FPGAs with 16
GByte (EB-PDS-DDR4-R11)
Added memory capacity to chapters
DDR4 Extension Board for Intel
FPGAs with 4 GByte (EB-PDS-
DDR4-R8) and DDR4 Extension
Board for Intel FPGAs witch 8
Added FM-XCVU19P-R1 device
package to chapter 4.5.8 Order Codes
Packages
3.73 2020/11/09 pudhardt EB-PDS-PCIe-Cable-R3 Redriver
configuration added to chapter 5.23
3.74 2020/11/18 msteinacker Added chapter 5.63 V2 QSFP28
Extension Board (EB-PHS-QSFP28-
R1)
Updated chapter 5.62.6 Order Code
Updated chapter 5.46.3 FPGA
Extension Site Compatibility
3.75 2020/11/26 msteinacker Added chapter 6.9.7 Firmware
Requirement
3.76 2020/12/02 cfranke Fixed given voltage for Bank 500 in
chapter 4.6.3.1
Added warning regarding UART on
VU19P and VU37P in chapter 4.5.4
3.77 2021/01/15 rdill Added chapter DisplayPort
Extension Board (EB-PDS-DP-R1)
3.78 2021/02/10 msteinacker Updated chapter 2.3.2.2 Generation 2
Updated chapter 4.7.2.3 FM-
1SG10M-R1
Updated chapter 6.7 4-way
Interconnect (IC-PDS-4WAY-R1)
3.79 2021/03/04 mribke Added chapter 5.25 M.2 Endpoint
Extension Board (EB-PDS-M.2-EP-
FLEX-R2
3.80 2021/04/07 cfranke Chapter 5.30 reviewed
3.81 2021/05/18 msteinacker Updated Table 5
3.82 2021/05/20 cfranke Changes reviewed
3.83 2021/08/10 mribke Update 5.40 QSFP+ Extension Board
3.84 2021/09/28 mribke Added additional DDR4-Memory to
EB-PDS-DDR4-R2/R3
Added IC-FMC-CABLE-A/B-R2 to
FMC-PROFPGA-R1
3.85 2021/10/28 kkohl Added EB-PDS-MIPI-DPHY-TX-R1
(chapter 5.48)
3.86 2021/10/29 kkohl Added IC-PDS-CABLE-R6 (chapter
6.1)
3.87 2021/11/16 droeder Added EB-PDS-DDR3-R7 (chapter
5.13)
Added EB-PDS-INTERFACE-R8
(chapter 5.50)
3.88 2022/02/02 msteinacker Updated chapter 6.9.2 Signal
mapping
3.89 2022/03/08 rdill Added chapter 5.20 Single MCP
HyperBus Flash/RAM Board (EB-
PDS-HYPER-RAM-FLASH-R1)
3.90 2022/03/11 kkohl Added EB-PDS-PCIe-Cable-R5
(chapter 5.24)
3.91 2022/03/18 msteinacker Changed document owner to
Siemens and added legal information
Changed styles to Siemens
3.92 2022/03/21 msteinacker Updated chapter 5.4 DDR4
PDS-DDR4-R6)
Added chapter 5.8 DDR4 Extension
Board with 5 Gbyte (EB-PDS-
DDR4-R12)
Added chapter 5.9 V3-SODIMM-R3
Board (EB-PDS-V3-SODIMM-R3)
Added chapter 5.10 V3-SODIMM-
R4 Board (EB-PDS-V3-SODIMM-
R4)
Changed Altera to Intel
Corrected some typing errors
Replaced Order Codes
3.93 2022/03/31 kkohl Removed support for Xilinx 7-series
FPGA modules in Table 221
3.94 2022/04/11 droeder Fixed memory timing for DDR4
Extension Board for Intel FPGAs
with 16 GByte (EB-PDS-DDR4-
R11)
3.95 2022/04/12 msteinacker Added chapter 5.67 Multi-Cluster
Clock Synchronization Boards
Added order code for EB-PDS-
DDR3-R7 (Fehler! Verweisquelle
konnte nicht gefunden werden.)
4.0 2022/05/20 Nikgau3n Added Siemens template
4.1 2022/06/16 pudhardt Removed license agreement link
4.2 2022/06/21 kkohl Edited order codes of selected
products
Edited PCIe 4-lane host interface
card (to Rev. 2)
Edited PCIe gen2 dual 4-lane Kit
Added PCIe gen3 8-lane Kit
4.3 2022/07/14 susehgal Updated the Document Title to
remove the extra ‘User Guide‘
subtitle.
4.4 2022/08/03 droeder Added I/O Voltage foot note on FM-
XCVU19P – Board connectors table
4.5 2022/08/03 mdonauer Corrected order codes for:
IC-PDS-CABLE-R1 (80cm)
IC-PDS-CABLE-R4
IC-PDS-CABLE-R5
EB-PDS-SATA-R4
EB-PDS-FMC-BANK-A-R1
Remove speed grade “-3” from
availability list of FM-XCVU19P-R1
4.6 2022/10/07 sunuma8x • Converted the document to the
Siemens documentation standards
that supports both HTML and
PDF outputs.
• Added section EB-PDS-
FIREFLY-R1 under Extension
Boards.
• Added section Skew under
Interconnect Cable (IC-PHS-
CABLE-R1).
• Added section Skew under EB-
PDS-FIREFLY-R1.
• Added order codes to the
following sections:
• FMC Mezzanine Board
Adapter (EB-PDS-FMC-R1/
R2/R3)
• FMC LPC Mezzanine Board
Adapter (EB-PDS-FMC-LPC-
R1)
• FMC Carrier Board Adapter
(FMC-PROFPGA-R1)
• Added a note to section
Interconnect Cable (IC-PHS-
CABLE-R1).
• Replaced section “Flash Board
(EB-PDS-FLASH-R1/R2)” with
Flash Board (EB-PDS-FLASH-
R1/R2/R3).
• Updated the following figures:
• EB-PDS-MGT-MMCX-R1
Components under “Functional
Description” on page 538.
• MGT Debug Board (EB-PDS-
MGT-MMCX-R1) under
“Functional Description” on
page 538.
• EB-PDS-BREAKOUT-R3:
Functional Description under
“Signal mapping” on page 976.
• Updated table FM-XCVU19P –
Board Connectors under
“Extension Board Connector
Bank Assignment” on page 187.
4.7 2022/11/15 ctyagi • Removed “Specification” from
the document title
• Updated the following figures:
• Figure 7-17 under Signal
mapping
• Figure 6-171 under Functional
Description
• Added two cautions to the topic
Reference Clocks at V2
Connectors
• Updated the following tables:
• Table 5-69 under Extension
Board Connector Bank
Assignment
• Table 5-55 under Functional
Description
• Updated the description for ONFI
flash in the topic Functional
Description
Table of Contents
Revision History
Chapter 1
References and Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 2
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Chapter 3
System-Level Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Board Types and Board Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Coordinate System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
System Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Extension Board Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Power and Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Master Beats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Clocking Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Generation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Generation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Clocks inside User FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Using Native Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Using Advanced Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Providing User Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Generation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Generation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
MMI-64 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Multi-Motherboard Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Data Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
External Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Connector Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Motherboard Interconnect Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Extension Board Connectors and FPGA Module Connectors . . . . . . . . . . . . . . . . . . . . . . 90
Noise values of system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table of Contents
Chapter 4
Motherboards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Generation 1 Motherboards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
MB-4M-R1, MB-4M-R2 (Quad Motherboard) and MB-2M-R1 (Duo Motherboard) . . . 98
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
MB-1M-R1, MB-1M-R2 (Uno Motherboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
proFPGA PCIe DMBI Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Generation 2 Motherboards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
MB-4M-R3 (Quad Motherboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
proFPGA PCIe DMBI Kit Gen 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Motherboard Interconnect Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Chapter 5
FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Virtex 7 FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Extension Board Connector Bank Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Other Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Firmware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Service Banks Pin Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Zynq7000 FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Reset Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SD Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
USB OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Local clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DDR3 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Dual Quad SPI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Virtex Ultrascale FPGA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table of Contents

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Firmware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Kintex Ultrascale FPGA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Virtex Ultrascale+ FPGA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Reference Clocks at V2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Firmware requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Zynq Ultrascale+ MPSoC FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
PS Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
PUDC_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table of Contents
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Stratix 10 FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
FM-1SG10M-R1 Motherboard Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Arria 10 FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Chapter 6
Extension Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
DDR4 Extension Board with 2.5 Gbyte (EB-PDS-DDR4-R2/R3) . . . . . . . . . . . . . . . . . . . 264
Extension Board Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
FPGA Extension Site Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
FPGA Pin Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
DDR4 Extension Board with 9 Gbyte (EB-PDS-DDR4-R4) . . . . . . . . . . . . . . . . . . . . . . . . 272
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
DDR4 Extension Board with 18 Gbyte (EB-PDS-DDR4-R5) . . . . . . . . . . . . . . . . . . . . . . . 280

Table of Contents

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
DDR4 Extension Board for Intel FPGAs with 4 GByte (EB-PDS-DDR4-R8) . . . . . . . . . . 297
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
DDR4 Extension Board for Intel FPGAs witch 8 GByte (EB-PDS-DDR4-R10) . . . . . . . . 305
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
DDR4 Extension Board for Intel FPGAs with 16 GByte (EB-PDS-DDR4-R11) . . . . . . . . 313
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
DDR4 Extension Board with 5 Gbyte (EB-PDS-DDR4-R12) . . . . . . . . . . . . . . . . . . . . . . . 320
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
V3-SODIMM-R3 Board (EB-PDS-V3-SODIMM-R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
V3-SODIMM-R4 Board (EB-PDS-V3-SODIMM-R4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Table of Contents

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
DDR3 Extension Board with 4 Gbyte (EB-PDS-DDR3-R6/R7) . . . . . . . . . . . . . . . . . . . . . 357
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
DDR3 SODIMM Board (EB-PDS-DDR3-SODIMM-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
DDR3 SODIMM Board (EB-PDS-DDR3-SODIMM-R4) . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
LPDDR2 Extension Board with 512 MByte (EB-PDS-LPDDR2-R1) . . . . . . . . . . . . . . . . 374
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
LPDDR4 Extension Board with 2 Gbyte (EB-PDS-LPDDR4-R1) . . . . . . . . . . . . . . . . . . . 381

Table of Contents

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Multi Memory Board (EB-PDS-MULTIMEMORY-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Flash Board (EB-PDS-FLASH-R1/R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Single MCP HyperBus Flash/RAM Board (EB-PDS-HYPER-RAM-FLASH-R1) . . . . . . . 409
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
HyperBus Memory S71KS512SC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Pin Mapping of XEBA1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Triple SSRAM Board (EB-PDS-SRAM-R1/R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
SSRAM Assembly Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
PCIe gen1 8-lane Kit (EB-PDS-PCIe-Cable-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Top-side extension board connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

Table of Contents

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Redriver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
PCIe gen2 dual-4-lane Kit (EB-PDS-PCIe-Cable-R6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
PCIe Root Complex and M.2 Extension Board (EB-PDS-ROOT-COMPLEX-M.2-R1) . . 465
Top-side Extension Board Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
PCIe Root Complex Extension Board (EB-PDS-ROOT-COMPLEX-R1) . . . . . . . . . . . . . 475
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
PCIe 4-lane Host Interface Card (PCIex4_HostCableAdaptor-R2) . . . . . . . . . . . . . . . . . . . 483
DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Mini PCIe Host Interface Card (MPCIe_HostCableAdapter-R1) . . . . . . . . . . . . . . . . . . . . 486
DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
M.2 Endpoint Extension Board (EB-PDS-M.2-EP-FLEX-R2) . . . . . . . . . . . . . . . . . . . . . . 489

Table of Contents

USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
SMBUS Interface and ID-PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Debug Board (EB-PDS-DEBUG-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Debug Board (EB-PDS-DEBUG-SWDIO-R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
MGT Debug Board (EB-PDS-MGT-MMCX-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
FMC Mezzanine Board Adapter (EB-PDS-FMC-R1/R2/R3) . . . . . . . . . . . . . . . . . . . . . . . 543
Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

Table of Contents

Differences between EB-PDS-FMC-R1 and EB-PDS-FMC-R2 . . . . . . . . . . . . . . . . . . . . 549
Differences between EB-PDS-FMC-R2 and EB-PDS-FMC-R3 . . . . . . . . . . . . . . . . . . . . 550
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
FMC Bank A Mezzanine Board Adapter (EB-PDS-FMC-BANK-A-R1) . . . . . . . . . . . . . . 553
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
FMC Reduced Mezzanine Board Adapter (EB-PDS-FMC-REDUCED-R1) . . . . . . . . . . . 559
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
FMC LPC Mezzanine Board Adapter (EB-PDS-FMC-LPC-R1) . . . . . . . . . . . . . . . . . . . . . 565
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
FMC Carrier Board Adapter (FMC-PROFPGA-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
USB 3.0 Board (EB-PDS-USB3-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
USB 2.0(UTMI) & 3.0(ULPI) Interface Board (EB-PDS-USB2-3-R1/R2) . . . . . . . . . . . . . 588
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
GBit Ethernet Board (EB-PDS-GBITETHERNET-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Table of Contents

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
DVI Input and Output Board (EB-PDS-DVI-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
QSFP+ Extension Board (EB-PDS-QSFP+-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
QSFP28 Extension Board (EB-PDS-QSFP28-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
EB-PDS-FIREFLY-R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

Table of Contents
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
DisplayPort Extension Board (EB-PDS-DP-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
I²C Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
DisplayPort – Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Interface Board (EB-PDS-INTERFACE-R1/R8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
DIP Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
FAN Control IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
I²C Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
PMBUS Power Supply Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
PMBUS Controller Isolated PSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
EJTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
SGPIO Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
GPIO Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Interface Board (EB-PDS-INTERFACE-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
proFPGA Bottom Connector Signal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
LIN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
QSPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
I²S Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
I²C EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
SD Card Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Quad USB to UART Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Lauterbach ARM JTAG/ETM Debugger Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
TotalPhase Aardvark I²C/SPI Host Adapter Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Additional 2x10-pin JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Spare I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Debug Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

Table of Contents
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754

Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
LIN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
QSPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
I²S Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
I²C EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
SD Card Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
Debug Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
LIN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
QSPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
I²S Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
I²C EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
SD Card Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Debug Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

Table of Contents

CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
LIN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
I²S Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
I²C EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
SD Card Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
Debug Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Parallel NOR FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Serial NAND FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
EJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
IrDA UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
MICTOR Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Protocol Tester Board (EB-PDS-RnS-TESTER-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
SATA Extension Board (EB-PDS-SATA-R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Erratum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

Table of Contents
SATA Extension Board (EB-PDS-SATA-R4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
ADC Board (EB-PDS-ADC250x16-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
Dual DAC Extension Board (EB-PDS-DAC1600x16-R2) . . . . . . . . . . . . . . . . . . . . . . . . . 863
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
Riser Board (EB-PDS-RISER-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
V2 Riser Board (EB-PHS-RISER-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
V2 QSFP28 Extension Board (EB-PHS-QSFP28-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
ARM Express Adapter Board (EB-PDS-EXPRESS-ADAPTER-R1) . . . . . . . . . . . . . . . . . 884
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Workaround for Error during Verilog Top Level generation . . . . . . . . . . . . . . . . . . . . . . 887
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Flexible Riser Board (EB-PDS-FLEXRISER-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888

Table of Contents

Speed Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Zynq US+ Interface Board (EB-FM-XCZUxxEG-R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . 893
MIO Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
ProFPGA Connector Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
SATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
CAN Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Display Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
I²C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
GPIO Pin Header, Buttons and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
Multi-Cluster Clock Synchronization Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Power Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Clock and Sync Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
Chapter 7
Interconnect Boards and Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Interconnect Cable (IC-PDS-CABLE-R1/R6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
1:1 Interconnect Cable (IC-PDS-CABLE-R4/R5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
Interconnect Cable (IC-PDS-CABLE-R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

Table of Contents

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Interconnect Cable (IC-PHS-CABLE-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
East-West Interconnect (IC-PDS-EW-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
North-South Interconnect (IC-PDS-NS-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
4-way Interconnect (IC-PDS-4WAY-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Breakout Board (EB-PDS-BREAKOUT-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
V2 Breakout Board (EB-PDS-BREAKOUT-R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976

Table of Contents

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Firmware Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
TA1V1/TA2V1 Adapter Board (EB-FM-XCVU440-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Chapter 8
Board Assembly Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989

Chapter 1
References and Glossary
This chapter contains the references and the glossary.

References
Reference By Title
[UD002] Siemens proFPGA Software Reference Manual
[UD003] Siemens proFPGA Extension Board Design Guide
[UD004] Siemens proFPGA Builder User Manual
[UD006] Siemens proFPGA HDL Design Library Reference Manual
[UD011] Siemens proFPGA ARM Express Adapter User Manual
[FMC] VITA ANSI/VITA 57.1; FPGA Mezzanine Card (FMC)
Standard; Approved July 2008 (Revised February 2010)
Glossary
The following terms and abbreviations are used:
• ACM - Advanced Clock Manager

• DMBI - Device Message Box Interface
• MMI-64 - Module Message Interface
References and Glossary
Chapter 2
Abstract
The proFPGA prototyping system consists of a set of modular building blocks. This allows
highly customized prototyping solutions to match the project-specific resource requirements
with a minimum of system complexity.
Figure 2-1. proFPGA Hardware Assembly
Each building block is a piece of individual hardware, either a board or a cable.
• Chapter 3: system level (infrastructure, common functions for all proFPGA boards)
• Chapters 4 to 6: board-specific properties
Abstract
Chapter 3
System-Level Hardware
This chapter discusses topics that involve multiple proFPGA boards.
System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Board Types and Board Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Coordinate System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
System Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Power and Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Master Beats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Clocking Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Clocks inside User FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Generation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Generation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
MMI-64 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Multi-Motherboard Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Data Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Connector Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Motherboard Interconnect Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Extension Board Connectors and FPGA Module Connectors . . . . . . . . . . . . . . . . . . . . . . 90
Noise values of system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
System Overview
System Overview
This section discusses system overview of proFPGA boards.
Board Types and Board Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Coordinate System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
System Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Board Types and Board Connections

The proFPGA prototyping system consists of a set of modular hardware units.
In the figure below, FPGA module connectors (between motherboard and FPGA modules) are
shown in grey. Extension board connectors (towards extension boards) are shown in white.
Figure 3-1. Modular hardware approach of the proFPGA prototyping system.
Motherboards
Motherboards provide the proFPGA system infrastructure. They offer mechanical fixture,
power supply, I²C-based system management, clocking infrastructure, and MMI-64
communication for multiple FPGA modules.
Motherboards have FPGA module connectors (carrying user I/O, power supply, service) on the
top side and Extension board connectors (carrying user I/O, power supply) on the bottom side.
The user I/O pins of top-side and bottom-side connectors are directly connected with each other,
providing a transparent connection from the FPGA module on the top-side to the extension
board on the bottom side.
Board Types and Board Connections
Note
With release of 2018A there are two generation of Motherboards (Generation 1 and
Generation 2). This manual describes the different behaviours or features of the different
Motherboard generations in separate chapters. The description of common behaviours and
features are ummarized for both generations in the appropriate chapters.
FPGA Modules
The FPGA modules contain the user design. They offer up to 8 connectors to extension sites (4x
top, 4x bottom). Each FPGA module has access to MMI-64 communication from the
motherboard.
FPGA modules have 4 FPGA module connectors (user I/O, power supply, service) on the
bottom side and up to 4 Extension board connectors (user I/O, power supply) on the top-side.
Because the motherboard transparently converts the FPGA module connector into an Extension
board connector, each FPGA module can access up to 8 extension boards.
Note
The FPGA module must be assembled with the FPGA facing downwards. The holes in the
motherboard are intended for the FPGA heat sinks.
Extension Boards
Extension boards provide hardware functions to user designs inside the FPGA modules, e.g.
SDRAM memory, user PCIe connection, debug access. One extension board occupies one or
more extension board connectors of one FPGA module, giving the user design inside the FPGA
module exclusive access to the extension board. The Extension board connectors of the FPGA
module are located on the bottom side.
Note
Extension boards and interconnect boards on the bottom side of the motherboard must be
assembled upside-down.
Some extension boards (e.g. the user PCIe adapter) are stackable. Unused I/O pins from the
FPGA module are mapped to a top-side connector, allowing further extension boards to be
added.
Note
Only use extension boards provided by Siemens or boards that comply with the proFPGA
extension board design guide. DO NOT CONNECT BOARDS WITH OTHER
CONNECTOR STANDARDS, EVEN IF THEY FIT MECHANICALLY (E.G. FMC).
Coordinate System
Interconnects
Interconnects are special extension boards to connect I/O pins of different FPGA modules. They
are available as boards and cables. Interconnect cables connect two extension sites. Interconnect
boards connect two or more extension sites. Connections are either broadcast (e.g. the 4-way
interconnect board) or point-to-point (e.g. all two-way interconnect boards and cables).
System Extension Boards

The system functionality may be extended by special hardware, such as motherboard PCIe
adapter board or motherboard-to-motherboard connector cable. This hardware uses dedicated
connectors on the motherboard.
Coordinate System
This section discusses the coordinate systems in proFPGA boards.
Note
The Coordinate system has been changed from generation 1 to generation 2 motherboards.
The reason is to have the option to support larger FPGA modules in the future on all FPGA
sites.
Generation 1
The modules of the proFPGA prototyping system are assembled into a 3-dimensional structure.
To identify the location of any board connector, there are two coordinate systems.
World Coordinate System

The world coordinate system describes the connector location inside any assembled proFPGA
prototyping system. As shown in Figure 2-1, the X and Y coordinates describe the location on
the table, whereas Z describes the height above the table.
• X letter (A, B, C, …), origin on leftmost connector on the table

• Y number (1, 2, 3, …), origin on closest connector to the back of the table
• Z signed number (-n, …, -1, +0, +1, …, +m), origin on motherboard-to-FPGA
connector (or bottom MB for multi-MB configurations)
Examples:
• A1+0 top-left connection between motherboard and FPGA module

• B1-1 2nd column, top row, 1st bottom-side extension board connector
• C4+2 3rd column, 4th row, 2nd top-side extension board connector
Coordinate System
Board Coordinate System

The board coordinate system describes the location on a single proFPGA module. Figure 3-2
shows an example of the board coordinate system for a quad motherboard.
Figure 3-2. Board Coordinate System for a Quad Motherboard
The coordinates are defined as follows:
• Z letter, T=top-side, B=bottom-side

• X letter (A, B, C, …), origin on the leftmost connector of the board. Because the
distance A B (equal to C D) is different from B C, the origin starts either with A or B.
starting with A: extension boards connecting A and B, or single-column extension
boards
starting with B: interconnect board connecting B and C
• Y digit (1, 2, 3, …), origin on the closest connector to the top (as shown in
Figure 3-2)
The X or Y coordinate is ‘0’ if the coordinate is not applicable.
Examples:
• TA1 top-left connector on top side

• BA1 top-left connector on bottom side
• TB1 top-side, 2nd column, 1st row
• BA2 bottom side, 1st column, 2nd row
Coordinate System
Generation 2
The modules of the proFPGA prototyping system are assembled into a 3-dimensional structure.
Any location of the extension boards can be identified by the coordinate systems.
The horizontal and vertical directions in the coordinate system are counted in different ways. In
horizontal direction it is counted with characters (A,B,C,…). In vertical direction it is counted
with numbers (1,2,3,…).
If an FPGA mounted onto an FPGA module has such amount of IOs, the FPGA module has to
be expanded. The expansion will be done in “north” direction, because it is the only possibility
to expand it without colliding with other FPGA modules. The connectors for this expansion are
called “0” connectors. This is done to have a reference to the motherboard where A1 connectors
are aligned. These new connectors are not connected to the motherboard on the bottom
connector.
The first part of the coordinate is the number of the motherboard where the board is plugged on.
If only one motherboard is used, it is always MB1. Other examples are MB2, MB3, …
The second part of the coordinate is the coordinate of the FPGA module plugged on the
motherboard. Possible options are shown in Figure 3-3. For a quad motherboard FA1, FA2,
FB1 and FB2 are possible.
Figure 3-3. Board coordinate system for a Quad Motherboard
The third part of the coordinate is a combination of two things. First of all, the direction where
the board is plugged - top or bottom (T for top and B for bottom). The second part is the
System Management
connector on the FPGA module where the board is plugged (see Figure 3-3 for reference). For
example TB2 or BA2.
The last part of the coordinate is the height level where the extension board is plugged. Because
extension boards can have top connectors where other extension boards can be plugged onto,
the height of the coordinate is also an important information.
Figure 3-3 shows that FA2 and FB2 are turned by 180° in comparison to FA1 and FB2. The
idea is that even if a proFPGA FPGA module is bigger, it will fit on every position on the
motherboard.
Examples:
• MB1 FA1 TA1 1 - motherboard 1, top-left FPGA module, top side, top-left connector,
level 1
• MB2 FB1 BA1 3 - motherboard 2, top-right FPGA module, bottom side, top-left
connector, level 3
System Management
The system management is conducted by the motherboard. It consists of a Supervisor CPU and
a Control FPGA.
Naming Conventions
Figure 3-4. proFPGA Motherboard Bottom Side
Number Function Notes

1 Supervisor CPU Atmel ARM SAM9
2 Control FPGA with Heat Sink Xilinx Virtex 6
Naming Conventions
This section discusses the naming convention of proFPGA boards.
Note
The Naming Conventions has been changed due the change of the Coordinate system.
Generation 1: Board Naming Conventions

The proFPGA boards are named by the following conventions:
<BoardName> ::= <BoardTypeAndAttributes> <MajorRevision>
Naming Conventions
<BoardTypeAndAttributes> ::= <MotherBoard>

| <FPGAModule>
| <ExtensionBoard>
| <InterconnectBoard>
<MotherBoard> ::= “MB” <MBNumberOfSites> <Attribute>*
<FPGAModule> ::= “FM” <Attribute>+
<ExtensionBoard> ::= “EB” <ConnectorType> <Attribute>+
<InterconnectBoard> ::= “IC” <ConnectorType> <Attribute>+
<MBNumberOfSites > ::= “-“ <Number> “M”
<ConnectorType> ::= “-“ “PDS”// Siemens Extension Board
| “-“ “MB” // Dedicated motherboard connector
<Attribute> ::= “-“ <StringWithoutSpaces>
<MajorRevision> ::= “-“ “R” <Number>
Examples:
MB-4M-R2 quad motherboard (revision 2)
FM-XC7V2000T-R2 FPGA module Virtex-7 2000T (revision 2)
EB-PDS-DDR3-R2 DDR3 extension board (revision 2)
IC-PDS-EW-R1 East-West interconnect board with Siemens connector (revision
1)
EB-MB-PCIe-Cable-R1 PCIe cable adapter for proFPGA motherboard (revision 1)
Generation 1: Board Connector Naming Conventions

Each board connector has a name consisting of 5 characters.
‘X’ ‘M’ or ‘E’ z coord x coord y coord
1. The first letter is always ‘X’.

2. The second letter denotes the connector type:
o ‘M’ = FPGA module connector
o ‘E’ = extension board connector
3. The third letter denotes the Z coordinate (‘T’ = top, ‘B’ = bottom).
4. The fourth letter denotes the X coordinate (‘A’, ‘B’, …) or ‘0’ if the X coordinate is not
applicable.
Naming Conventions
5. The fifth letter denotes the Y coordinate (‘1’, ‘2’, …) or ‘0’ if the Y coordinate is not
applicable.
Generation 2: Board Naming Conventions

The proFPGA boards are named by the following conventions:
<BoardName> ::= <BoardTypeAndAttributes> <MajorRevision> .
<BoardTypeAndAttributes> ::= <MotherBoard>
| <FPGAModule>
| <ExtensionBoard>
| <InterconnectBoard> .
<MotherBoard> ::= “MB” <MBNumberOfSites> <Attribute>* .
<FPGAModule> ::= “FM” <Attribute>+ .
<ExtensionBoard> ::= “EB” <ConnectorType> <Attribute>+ .
<InterconnectBoard> ::= “IC” <ConnectorType> <Attribute>+ .
<MBNumberOfSites > ::= “-“ <Number> “M” .
<ConnectorType> ::= “-“ “PDS”// Siemens Extension Board
| “-“ “MB” // Dedicated motherboard connector.
<Attribute> ::= “-“ <StringWithoutSpaces> .
<MajorRevision> ::= “-“ “R” <Number> .
Examples:
MB-4M-R3 quad motherboard (revision 3)
FM- FPGA module Virtex-7 2000T (revision 2)
XC7V2000T-
R2
EB-PDS- DDR3 extension board (revision 2)
DDR3-R2
IC-PDS-EW- East-West interconnect board with Siemens connector (revision 1)
R1
EB-MB-PCIe- PCIe cable adapter for proFPGA motherboard (revision 1)
Cable-R1
Generation 2: Board Connector Naming Conventions

The name of each board connector is equal to the coordinate in the coordinate system except for
the numbering of the motherboard. Each board connector has a name consisting of 8 characters.
‘X’ ‘M’ or ‘E’ z coord FPGA site x coord y coord
Naming Conventions
1. The first letter is always ‘X’.

2. The second letter denotes the connector type:
o ‘M’ = FPGA module connector
o ‘E’ = extension board connector
3. The third letter denotes the Z coordinate (‘T’ = top, ‘B’ = bottom).
4. Letter 4, 5 & 6 denote the FPGA site F[A,B][1,2].
5. The seventh letter denotes the X coordinate (‘A’, ‘B’, …).
6. The eighth letter denotes the Y coordinate (‘1’, ‘2’, …).
Power Supply
Power Supply
This section discusses power supply in proFPGA boards.
External Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Power and Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
External Power Supply

This section discusses external power supply in proFPGA prototyping system.
The proFPGA prototyping system requires 12V DC power supplies provided through standard
6-pin PCIe power connectors. In Figure 3-5 below, an example of the PCIe power connector is
shown, for example the Molex Mini-Fir Jr. series.
Figure 3-5. PCIe Power Connector Pin Assignment
Each FPGA extension site1of the proFPGA prototyping system has its individual external
power supply. The proFPGA prototyping system supports separate power supplies (or different
power rails of one power supply) on each of the power connectors by keeping the power
domains separated.
Note
All power connectors on the motherboard must be connected to 12V power supplies,
regardless if FPGA modules are plugged.
Custom-specific external power supplies must provide at least 25 A (300 W) per connector.
Extension Board Power Supply

Each extension board connector provides 4 voltages.
1. FPGA extension sites include the FPGA module and all 8 extension sites connected to it.
Power and Temperature Protection
Table 3-1. Extension Board Power Supply

Power Voltage Source Purpose
P12V 12 V ext. power supply main power supply for user
logic
P3V3 3.3 V motherboard additional power supply for
user logic
P3V3_AUX 3.3 V motherboard I2C system management logic
only
PV_IO variable FPGA module or extension power supply for user I/O
board drivers
User logic on the extension board can be powered by P12V and P3V3.
P3V3_AUX is exclusively reserved for I²C system management.
PV_IO will be provided either by the FPGA module or the extension board, depending on the
results of the hardware scan and the system configuration.
Note
Do not short-circuit power pins from different extension board connectors! Only data
signals and ground may be connected.
Further information:
• proFPGA Software User Manual

• proFPGA Extension Board Design Guide
Power and Temperature Protection

The following protection mechanisms are integrated into the proFPGA prototyping system.
Table 3-2. Power and Temperature Protection Mechanisms

Power / Temp. Who Protection Alert Indicator
Power Protection
P12V (per connector) MB inverse-polarity protection system will not
over-voltage protection power up
under-voltage protection
over-current protection
Power Sequences
Table 3-2. Power and Temperature Protection Mechanisms (cont.)

Power / Temp. Who Protection Alert Indicator
P12V(all connectors) MB power off if only a part of the system will not
power connectors has been power up
connected
PV_IO FM ADC-based voltage monitor, green LEDs on
all FPGA sites powered off FPGA modules go
on error off
Temperature Protection
User FPGA FM self-reset on over- red LED on FPGA
temperature module
Ctrl FPGA MB self-reset on over- red LED on
temperature motherboard
Motherboard MB system powers off red LED on
motherboard, rest of
the system is
powered off
None of these alerts should occur under normal operating conditions.
Note
Power protection alerts indicate electrical problems that must be corrected before powering
up the system again.
Note
Temperature alerts may indicate rough ambient conditions. Consider increasing the air flow
or lowering the ambient temperature.
After removing the cause of the protection alert, the proFPGA prototyping system is ready for
operation again, with one exception:
Note
In case of a motherboard temperature alert, the user must turn off or disconnect all external
power supplies and wait until the system has cooled down, before powering up again.
Power Sequences
This section discusses power sequences in proFPGA prototyping system.
Power Sequences
Power-up sequence
The following sequence is executed after turning on the external power supply:
1. Wait until all power connectors are within operating range

2. Power up all DC-DC converters on motherboard
3. Boot Supervisor CPU, configure Control FPGA
4. Wait until user launches system run
5. Power up system management (P3V3_AUX)
6. Check system compatibility with system configuration file
7. Power up user logic for selected FPGA extension sites (P12V, P3V3)
8. Power up user I/O logic for each extension board connector depending on configured
driver and I/O voltage
9. Configure clock and sync signal infrastructure
10. configure FPGAs with bitfiles
11. Process sync events (reset signals)
Consecutive power-up sequences start with step 4.
Power-down
Either of the following actions will turn off the whole system:
• Turn off the external power supply.

• Use the power switch on motherboard to turn off all power.
The proFPGA prototyping system will be unavailable until it is turned on again.
The following actions will turn off the FPGA extension sites, but leave the motherboard active:
• Software power-down command turns off P3V3_AUX, P3V3, P12V, and PV_IO.
• Launching a new system run implies a software power-down during system
initialization.
Clocks
Clocks
This section discusses clocks used in proFPGA boards.
Master Beats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Clocking Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Clocks inside User FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Master Beats
This section discusses master beats clocking mechanism.
The proFPGA prototyping system uses a special clocking mechanism where every clock signal
CLK[i] is associated with a synchronization signal SYNC[i]. The clock signal is free-running at
constant frequency. The synchronization signal carries event information which arrives
simultaneously on all user FPGAs. The 8-bit event ID is transmitted serially, as shown in
Figure 3-6. SYNC[i] flip-flops are triggered by CLK[i].
In the figure below, the signals clk[i] and sync[i] are input pins of the User FPGA,
event_id[i][7:0] and event_en[i] are internal registers which are triggered by clk[i].
Figure 3-6. Master Beat Consisting Of Clock And Synchronization Signal
Clocking Hardware
Clocking Hardware
This section discusses clocking hardware in proFPGA.
Note
This section describes the clocking hardware for MB-4M motherboards. On MB-2M
motherboards ‘User FPGA #3’ and ‘User FPGA #4’ do not exists. On MB-1M
motherboards only ‘User FPGA #1’ exists and there is no clock mux.
Each proFPGA motherboard contains LVDS clock multiplexers and buffers for 8 master beats.
The signal layout on both, motherboard and FPGA module ensures that clock and sync arrive
simultaneously on all User FPGAs.
Generation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Generation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Generation 1
This section discusses generation 1 clocking hardware in proFPGA.
Figure 3-7. Clocking Hardware on Each Motherboard
Each clock buffer is driven by a clock multiplexing scheme as shown in Figure 3-8.
In the figure below, all signals are implemented as LVDS pairs. CLK and SYNC signal
multiplexers are implemented identically.
Clocking Hardware
Figure 3-8. Clock Multiplexing Hardware on Motherboard
The following sources are available on each motherboard:
• GEN.clk/sync[0:7]: 8 generated clocks (clock generators are described below)

• {TA1,TC1,TA3,TC3}.srcclk/sync[0:3]: 4 source master beats from each User FPGA
• PMB.clk/sync[0:7]: 8 master beats from the previous motherboard in a multi-
motherboard system
• NMB.clk/sync[0:7]: 8 master beats from the next motherboard of a multi-motherboard
system
Note
The frequency of clk/sync[0] is fixed to 100 MHz.
The mapping of clock sources to clock multiplexers is shown in Table 3-3.
In the table beneath user FPGAs TA3 and TC3 are not available on the Duo motherboard (MB-
2M). Since clk/sync[0] is fixed to 100 MHz, it cannot be driven by user FPGAs.
Table 3-3. Clock Multiplexer Sources
Master Beat ClkMux=0 ClkMux=1 ClkMux=2 ClkMux=3 ClkMux=3
SrcClkMux SrcClkMux
=0 =1
clk/sync[0] PMB.clk/ NMB.clk/ GEN.clk/ n/a n/a
sync[0] sync[0] sync[0]
clk/sync[1] PMB.clk/ NMB.clk/ GEN.clk/ TA1.srcclk/ TA3.srcclk/
sync[1] sync[1] sync[1] sync[1] sync[1]
clk/sync[2] PMB.clk/ NMB.clk/ GEN.clk/ TC1.srcclk/ TC3.srcclk/
Clocking Hardware
Table 3-3. Clock Multiplexer Sources (cont.)

Master Beat ClkMux=0 ClkMux=1 ClkMux=2 ClkMux=3 ClkMux=3
SrcClkMux SrcClkMux
=0 =1
Further information on clock multiplexer configuration:
Configurable Clock Generators

Note
MB-1M motherboards do not have configurable clock generators. All clock frequencies are
fixed to the following frequency values:
Table 3-4. Master Clock Frequencies on MB-1M Motherboards

Master Clock Frequency
clk[0] 100 MHz (same as on all motherboards)
clk[1] 50 MHz
clk[2] 125 MHz
clk[3] 60 MHz
clk[4] 18.432 MHz
clk[5] 10 MHz
clk[6] 120 MHz
clk[7] 36.864 MHz
Note
Sync event generators are implemented to provide ‘internal generated’ sync events only.
External sync event s inputs are missing.
The clock generators are implemented inside the control FPGA. Figure 3-9 gives a functional
overview.
Clocking Hardware
Figure 3-9. Configurable Clock Generator Inside Control FPGA
The generated clock frequency can be derived from one of the following sources:
• one of the Quartz oscillators (125 MHz, 60 MHz, 18.432 MHz)

• an external clock provided through RF connectors
The selected clock is multiplied and divided by a Virtex-6 MMCM.
As explained earlier, the SYNC signals carry serially encoded event information. The event can
either be issued by the software (write to SYNC_EVENT register) or through external SYNC
strobes (signals on RF connectors). The SYNC transmitter requires 10 cycles of the generated
clock to transmit the event. When using ACM with very slow derived clocks, the SYNC
transmitter will automatically insert additional delay cycles between events to ensure that every
single event reaches the target clock domain (can be several thousand cycles). This may reduce
the sampling rate of external sync signals.
Note
Software-generated events will never get lost because of the design of MMI-64
communication.
For further information regarding clock configuration and sync transmitter/receiver, consult:
Generation 2
This section discusses generation 2 clocking hardware in proFPGA.
Clocking Hardware
Each proFPGA motherboard has crossbars for 8 master beats. The signal layout on both,
motherboard and FPGA module ensures that clock and sync signals arrive simultaneously on all
User FPGAs.
Figure 3-10. Clocking Hardware on each Motherboard
The following sources are available on each motherboard:
• {FA1,FB1,FA2,FB2}.srcclk/sync[0:3]: 4 source master beats from each User FPGA.

• D-GEN.clk: 4 direct clocks from the clock generator (to avoid PLL inside the Controller
FPGA).
• D-DIFF-EXT.clk: 2 direct external differential clock inputs (to avoid PLL inside the
Controller FPGA).
• GEN.clk/sync[0:7]: 8 generated clocks from the controller FPGA.
• PMB.clk/sync[0:7]: 8 master beats from the previous motherboard in a multi-
motherboard system.
• NMB.clk/sync[0:7]: 8 master beats from the next motherboard of a multi-motherboard
system.
• EXT.clk/sync[0:3]: 4 master beats from external sources connected to the motherboard.
• DIFF-EXT.clk[0:1]: 2 differential clock inputs from external sources connected to the
motherboard.
Note
The frequency of clk/sync[0] is fixed to 100 MHz.
Clocking Hardware
The mapping of clock sources to clock multiplexers is shown in Table 3-5.
Note
Since clk/sync[0] is fixed to 100 MHz, it cannot be driven by user FPGAs.
Table 3-5. Clock Multiplexer Sources

Master ClkMux=0 ClkMux=1 ClkMux=2 ClkMux=3 ClkMux=3
Beat SrcClkMux=0 SrcClkMux=1
clk/sync[0] PMB.clk/ NMB.clk/ GEN.clk/ n/a n/a
sync[0] sync[0] sync[0]
clk/sync[1] PMB.clk/ NMB.clk/ GEN.clk/ FA1.srcclk/ FA2.srcclk/
clk/sync[2] PMB.clk/ NMB.clk/ GEN.clk/ FB1.srcclk/ FB2.srcclk/
Further information on clock multiplexer configuration:
Configurable Clock Generators

The clock generators are implemented inside the controller FPGA. Figure 3-11 gives a
functional overview.
Clocking Hardware
Figure 3-11. Configurable Clock Generator Inside Control FPGA
The generated clock frequency can be derived from one of the following sources:
• an external clock provided through RF connectors

• a clock generated by the clock generator
• an external differential clock provided through RF connectors
The selected clock is multiplied and divided by a ZYNQ-7 MMCM.
As explained earlier, the SYNC signals carry serially encoded event information. The event can
either be issued by the software (write to SYNC_EVENT register) or through external SYNC
strobes (signals on RF connectors). The SYNC transmitter requires 10 cycles of the generated
clock to transmit the event. When using ACM with very slow derived clocks, the SYNC
transmitter will automatically insert additional delay cycles between events to ensure that every
single event reaches the target clock domain (can be several thousand cycles). This may reduce
the sampling rate of external sync signals.
Note
Software-generated events will never get lost because of the design of MMI-64
communication.
For further information regarding clock configuration and sync transmitter/receiver, consult:
Clocks inside User FPGAs

Clock signals may be used natively or through Advanced Clock Managers (ACM).
Using Native Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Using Advanced Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Providing User Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Using Native Clock Signals

Clock signals require an LVDS input clock buffer with 100 Ω termination (e.g. IBUFGDS for
Virtex-7). The output of the LVDS buffer is available for user designs.
Figure 3-12. HDL Infrastructure using Native Clock Signals
Sync signals must be decoded using a SYNC receiver HDL module. The SYNC receiver HDL
module provides raw event information as well as the pre-decoded signals reset, user_strobe1,
and user_strobe2. The user strobes at the output of the SYNC receiver are delayed copies of the
user strobes at the clock generator. The SYNC signal propagation mechanism ensures that
changes in the user strobes as well as all other events arrive simultaneously on all user FPGAs.
Tip
To achieve timing closure for user FPGA designs using a PLL, consider providing the
SYNC receiver with a 1:1 source synchronous PLL output rather than the raw clock input.
Using Advanced Clock Managers

The ACM HDL module converts LVDS clock and sync signals into an arbitrary number of
globally synchronous ACM clocks and up to 5 fully configurable local clocks.
Figure 3-13. HDL Infrastructure using Advanced Clock Manager
Providing User Clock Signals

User FPGAs may provide clock signals, which must be transformed into LVDS signals.
User events and user strobes must be encoded using a SYNC transmitter, for example Xilinx
Virtex-7, as shown in Figure 3-14. The clock multiplexing hardware on the motherboard must
be configured to select the clock from the user FPGA.
Figure 3-14. HDL Infrastructure for Providing User Clock Signals
Further Information:
• proFPGA HDL User Manual: ACM

• proFPGA Software User Manual: ACM configuration API
I/O Constraints
The differential clk and sync input signals operate at LVDS standard using FPGA internal
termination. Depends on the used FPGA technology the following constraints must be set for
each input pair:
For all Virtex-7 based FPGA modules:
set_property -quiet IOSTANDARD LVDS [get_ports {clk_n[x]}]

set_property -quiet IOSTANDARD LVDS [get_ports {clk_p[x]}]
set_property -quiet IOSTANDARD LVDS [get_ports {sync_n[x]}]
set_property -quiet IOSTANDARD LVDS [get_ports {sync_p[x]}]
For all Zynq-7000 based FPGA modules:
set_property -quiet IOSTANDARD LVDS_25 [get_ports {clk_n[x]}]

set_property -quiet IOSTANDARD LVDS_25 [get_ports {clk_p[x]}]
set_property -quiet IOSTANDARD LVDS_25 [get_ports {sync_n[x]}]
set_property -quiet IOSTANDARD LVDS_25 [get_ports {sync_p[x]}]
For all Virtex Ultrascale based FPGA modules:
set_property -quiet IOSTANDARD LVDS [get_ports {clk_n[x]}]

set_property -quiet IOSTANDARD LVDS [get_ports {clk_p[x]}]
set_property -quiet DIFF_TERM_ADV TERM_100 [get_ports {clk_p[x]}]
set_property -quiet IOSTANDARD LVDS [get_ports {sync_n[x]}]
set_property -quiet IOSTANDARD LVDS [get_ports {sync_p[x]}]
set_property -quiet DIFF_TERM_ADV TERM_100 [get_ports {sync_p[x]}]
I²C
For all Kintex Ultrascale based FPGA modules:
set_property -quiet IOSTANDARD LVDS_25 [get_ports {clk_n[0]}]

set_property -quiet IOSTANDARD LVDS_25 [get_ports {clk_p[0]}]
set_property -quiet DIFF_TERM_ADV TERM_100 [get_ports {clk_p[0]}]
set_property -quiet IOSTANDARD LVDS_25 [get_ports {sync_n[0]}]
set_property -quiet IOSTANDARD LVDS_25 [get_ports {sync_p[0]}]
set_property -quiet DIFF_TERM_ADV TERM_100 [get_ports {sync_p[0]}]
set_property -quiet IOSTANDARD LVDS [get_ports {clk_n[2]}]
set_property -quiet IOSTANDARD LVDS [get_ports {clk_p[2]}]
set_property -quiet IOSTANDARD LVDS [get_ports {sync_n[2]}]
set_property -quiet IOSTANDARD LVDS [get_ports {sync_p[2]}]
I²C
The I²C busses are controlled by the Control FPGA.
I²C
Each FPGA extension site has its individual I²C bus. The I²C components on the motherboard
are connected to a separate I²C bus, as shown in Figure 3-15. The I²C devices on each board are
described in the board-specific sections later in this document.
In the image below the duo motherboard (MB-2M), the I²C chains A3 and C3 are not available.
Each FPGA site has its separate I²C bus. The I²C commands are controlled by the supervisor
CPU to avoid potentially harmful settings (e.g. bad I/O voltage)
Figure 3-15. I²C topology on the quad Motherboard (MB-4M)
Each of the FPGA site I²C busses is switchable. This allows the use of the same I²C address on
several extension boards, e.g. when using the same extension board multiple times. As shown in
Figure 3-16, there are two types of I²C switches.
In the figure below, for each FPGA site, there is a separate 1:8 mux for the eight extension-sites.
Stackable extension boards provide a 1:2 mux to walk along the extension board. The I²C
address of the 1:2 mux address can be reconfigured to avoid aliasing with other stackable
extension boards.
I²C
Figure 3-16. I²C Bus Switching
Further information:
• proFPGA Software User Manual: I²C commands and board configuration

• proFPGA Extension Board Design Guide: I²C hardware requirements for custom
extension boards
JTAG
JTAG
This section discusses JTAG chains in proFPGA
Generation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Generation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Generation 1
This section discusses generation 1 JTAG.
The proFPGA prototyping system contains two independent JTAG chains. By default, the User
JTAG Chain is selected. It provides access to all FPGA modules and extension boards of the
proFPGA prototyping system. The Control JTAG Chain is required for firmware update, as
described in the proFPGA Firmware Update Guide.
The JTAG chain operates at 2.5V supply voltage. Devices with other JTAG voltages (e.g.
Virtex-7) require level shifters.
The JTAG devices appear in the scan chain as shown in Figure 3-17. If multiple boards are
stacked, devices on the boards closest to the motherboard appear first.
Example: The top-left FPGA module (connected to TA1, etc.) is always the first device in the
JTAG chain.
For each board connector, there is a bypass switch that connects TDI with TDO. The bypass
will be activated on either of the following conditions:
• There is no FPGA module or extension board plugged in.

• The connected board does not use JTAG (i.e. the JTAG_PRESENT pin is left floating).
In the image below the duo motherboard, the lower half (TA3 through BD4) is not available.
The JTAG connectors for Xilinx (Platform Cable) and Intel (FPGA Download Cable II) can be
connected alternatively. The User FPGAs are accessible over the grey connectors.
Generation 2
Figure 3-17. JTAG chain on the Quad Motherboard (MB-4M)
Generation 2
This section discusses generation 2 JTAG.
Note
In Comparison to the generation 1 motherboards the JTAG is reduced to TA1 connector of
the FPGA modules. Extension boards which need JTAG have to be placed on TA1 of the
FPGA module.
The proFPGA prototyping system contains two independent JTAG chains. By default, the User
JTAG Chain is selected. It provides access to all FPGA modules and extension boards of the
proFPGA prototyping system.
The JTAG chain operates at 2.5V supply voltage. Devices with other JTAG voltages (e.g.
Virtex-7) require level shifters.
The JTAG devices appear in the scan chain as shown in Figure 3-18. If multiple boards are
stacked, devices on the boards closest to the motherboard appear first.
Example: The top-left FPGA module (connected to FA1TA1, etc.) is always the first device in
the JTAG chain.
MMI-64 Communication
On each FPGA module there is a bypass switch that connects TDI with TDO. The bypass will
be activated on either of the following conditions:
• There is no extension board plugged in.

• The connected board does not use JTAG (i.e. the JTAG_PRESENT pin is left floating).
In the image below the JTAG connectors for Xilinx (Platform Cable) and Intel (FPGA
Download Cable II) can be connected alternatively.
Figure 3-18. JTAG chain on the quad motherboard (MB-4M-R3).
• proFPGA Software User Manual: I²C commands and board configuration
The proFPGA communication infrastructure is based on MMI-64.
It serves two purposes:
• System setup and FPGA configuration

• User communication
Tip
MMI-64 acts as the transport medium for DMBI system management tools.
The MMI-64 infrastructure communicates upon commands by the host software. The host PC
can use one of the following access methods:
• USB 2.0 via mini USB connector

• 100-BaseTX via RJ-45 connector
• PCIe (4 lanes, Gen.1) via PCIe cable and motherboard PCIe adapter board (EB-MB-
PCIe-Cable)
Note
100-BaseTX is not available on MB-1M-R1 motherboards.
PCIe interface is not available on MB-1M-R1 and MB-1M-R2 motherboards
The system can be configured without host PC by inserting a prepared USB stick into the USB
connector.
Multiple motherboards can be combined into a single prototyping system using a motherboard
interconnect cable.
The proFPGA prototyping system supports only one external communication channel.
1. If the motherboard interconnect cable (IC-MB-Cable) is connected, all other

connections are ignored.
2. Else, if there is a valid link over the motherboard PCIe adapter board, the remaining
connections will be ignored.
3. Else, if there is a prepared USB stick plugged in, it will be used.
4. Else, the supervisor CPU listens to connections from XUSB1 and XETH2.
Note
The Control FPGA of Generation 2 is able to communicate via a QSFP to PCIe bridge with
a PC. Even if a QSFP connector and cable is used, there is no QSFP protocol used for
communication to the PC.
In the image below the numbers in circles indicate the priority of external connections.
M=communication master, S=communication slave.
The figure below, shows quad motherboard MB-4M (Generation 1).
Figure 3-19. MMI-64 Communication Channels of the proFPGA Prototyping

System
The incoming connections will be multiplexed and processed by the MMI-64 main router
(Figure 3-20).
Figure 3-20. MMI-64 System Address Map (simplified) Left: Generation 1, Right:
Generation 2
For a complete list of MMI-64 system addresses and configuration registers, see:
Multi-Motherboard Systems
Multi-Motherboard Systems
This section discusses multi-motherboard systems.
Note
MB-1M motherboards do not support multi-motherboard systems.
Note
The Multi-Motherboard System implementation for Generation 1 and Generation 2
Motherboards is equal. Both generations can be connected together in various
configurations.
Note
The following feature of a multi motherboards setup, which includes Generation 1 and
Generation 2, are not implemented yet:
Clock synchronization
Note
The following issue of a multi motherboards setup which includes Generation 1 and
Generation 2 exists:
Reset for MB-4M-R3 Motherboard does not work correctly. If system hangs a power cycle is
needed.
The proFPGA prototyping system supports combined operations of multiple motherboards.

Each motherboard provides two connectors for this purpose:
• XNMB1 connector to next motherboard (top side)

• XPMB1 connector to previous motherboard (bottom side)
A multi-motherboard system is created by plugging the motherboard interconnect cable (IC MB
Cable) between XNMB1 of one motherboard (master) and XPMB1 of another motherboard
(slave). The cable provides the connections for MMI-64 communication and exchange of clock
signals between motherboards. Additional motherboards may be added to the system by daisy-
chaining of motherboard interconnect cables.
Note
Only the master motherboard (the one without connection on XPMB1) is able to
communicate with the user. A yellow LED on the motherboard indicates who is master.
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Data Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Clock Distribution
Clock Distribution
This section discusses clock distribution in multi-motherboard systems.
Clock signals can be distributed over multiple motherboards using motherboard-to-motherboard
interconnect cables. Without additional effort, the clock signal on the target motherboard will be
delayed by the motherboard interconnect cable and the clock multiplexer on the target
motherboard. The proFPGA prototyping system uses a PLL-based phase compensation
technique which is located on the source motherboard (Figure 3-21a). The phase compensation
is accomplished in an initial training sequence which involves a special training hardware
configuration.
Figure 3-21. Clock Distribution over Multiple Motherboards. (a) Location of

Phase Compensation, (b) Distribution Example
Data Connections
The phase-compensated clocks can be either distributed over multiple motherboards or

generated on each motherboard locally, as shown in the above distribution example.
Note
Clocks which are distributed across multiple motherboards must stay within the frequency
range of 20MHz to 220MHz for generation 1 motherboards (MB-4M-R<1,2> and MB-2M-
R1) and 22MHz to 220MHz for generation 2 motherboard (MB-4M-R3).
Further information on clock configuration and motherboard clock synchronization:
Data Connections
This section discusses data connections in multi-motherboard systems.
In addition to clock and control, the user may want to exchange signals between FPGAs on
different motherboards by using interconnects.
• East-West interconnect boards connect FPGAs on two horizontally adjacent

motherboards (e.g. column D on left motherboard with column A on right motherboard).
• North-South interconnect boards connect FPGAs on two vertically adjacent
motherboards (e.g. row 4 on first motherboard with row 1 on second motherboard).
• Vertical interconnect boards and Backbone interconnect boards connect FPGAs on two
stacked motherboards, as shown in Figure 3-22.
• When using interconnect cables, the physical location of the motherboards is not fixed.
Figure 3-22. Stacked Motherboard System
External Communication
This section discusses external communication in multi-motherboard systems.
Multiple motherboards can be combined into a single prototyping system by connecting them
through motherboard interconnect cables. The cable determines which motherboard is system
master Figure 3-23.
Note
Motherboards different generations cannot be combined into single prototyping system.
In the image below the XPMB1 connector on the master motherboard is open. The other
connectors are available for host and system communication. Slave motherboards (with
XPMB1 connected to the previous motherboard) will ignore communication attempts on the
other connectors.
Figure 3-23. External Communication Access for Multi-motherboard Systems
The cascaded structure of the motherboards also reflects in the MMI-64 addresses
(Figure 3-24).
Figure 3-24. Cascaded MMI-64 Routers
Figure 3-25 shows the MMI addressing scheme in multi-motherboard systems. The MMI
address is extended by a route through XNMB1 (port 0) for every preceding motherboard.
In the image below : (a) address of User FPGA A1 at master MB, (b) address of User FPGA A1
at master MB when using router inside user HDL design, (c) address of User FPGA A1 on slave
MB, (d) with router inside user HDL
Figure 3-25. MMI Addressing of Cascaded Motherboards Design
Connector Layouts
Connector Layouts
This section discusses connector layouts.
Motherboard Interconnect Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Extension Board Connectors and FPGA Module Connectors . . . . . . . . . . . . . . . . . . . . 90
Motherboard Interconnect Cable

This section discusses motherboard interconnected cable.
Figure 3-26. Samtec QSH-DP Connectors
In the table below, PMB=Previous Motherboard, NMB=Next Motherboard.

Table 3-6. Pin Assignment of the Motherboard-to-motherboard Connectors
Pin XNMB1 connector XPMB1 connector IOSTAN Description
DARD
1, 3 SYNC6_IN{N,P} SYNC6_OUT{N,P} LVDS25 sync[6] PMB —> NMB
2, 4 SYNC7_IN{N,P} SYNC7_OUT{N,P} LVDS25 sync[7]PMB —> NMB
9, 11 CLK6_IN{N,P} CLK6_OUT{N,P} LVDS25 clk[6]PMB —> NMB
14, 16 CLK5_IN{N,P} CLK5_OUT{N,P} LVDS25 clk[5]PMB—> NMB
17, 19 CLK6_OUT{N,P} CLK6_IN{N,P} LVDS25 clk[6]NMB —> PMB
25, 27 SYNC6_OUT{N,P} SYNC6_IN{N,P} LVDS25 sync[6]NMB —> PMB
Table 3-6. Pin Assignment of the Motherboard-to-motherboard Connectors

Pin XNMB1 connector XPMB1 connector IOSTAN Description
DARD
57, 59 SYNC2_IN{N,P} SYNC2_OUT{N,P} LVDS25 sync[2] PMB —> NMB
65, 67 MMI_TX1{N,P} MMI_RX1{N,P} CML MMI MGT1NMB —>
PMB
PMB
PMB
70, 72 MMI_TXACCEPT{ MMI_RXACCEPT{ LVCMOS MMI accept by PMB
1,2} 1,2} 25
73, 75 MMI_RX1{N,P} MMI_TX1{N,P} CML MMI MGT1PMB —>
NMB
NMB
NMB
78, 80 MMI_RXACCEPT{ MMI_TXACCEPT{ LVCMOS MMI acceptby NMB
1,2} 1,2} 25
Extension Board Connectors and FPGA Module Connectors
Extension Board Connectors and FPGA Module

Connectors
This section discusses extension board connectors and FPGA module connectors.
Figure 3-27. Samtec Connectors Provide 10 Rows of 40 Pins
The following naming conventions are used for the pins:

• GND ground
• P12V 12V main supply voltage
• P3V3 3.3V supply voltage
• P3V3_AUX system management supply voltage
• PV_REF I/O bank reference voltage (only used for
Intel FPGA modules)
• PV_IO I/O bank supply voltage
• PV_IO_RUN activate I/O bank supply voltage (if provided
by extension board)
• IO_nnn data I/O pin connecting User FPGA pin with
extension board
• CLK_IO_{N,P}_n data I/O pin connecting User FPGA pin with
extension board
-or- clock input to User FPGA
• SDA,SCL I²C bus
• TCK,TMS,TDI,TDO JTAG chain
• JTAG_PRESENT JTAG devices present, active high
• MGT_{RX,TX]_x_nn high-speed I/O signal (RX=to
FPGA,TX=from FPGA)
• n.c. not connected
Common Pin Assignment of Board Connectors

In the table below, the first part of the pin assignment is identical for all proFPGA connectors
Table 3-7. Common pins 1 to 280

+1 +2 +3 +4 +5 +6 +7 +8 +9 +10
0 P12V P12V P3V3 JTAG_ IO_14 GND GND PV_IO PV_IO PV_IO
PRES 6
ENT
10 P12V P12V P3V3 IO_14 IO_14 GND IO_14 PV_IO GND PV_IO
4 7 2 _RUN
20 P12V GND IO_14 IO_14 GND IO_13 IO_14 GND IO_13 PV_IO
0 5 8 3 6
30 PRES IO_13 IO_14 GND IO_13 IO_13 GND IO_13 IO_13 GND
ENT_ 4 1 2 9 0 7
N
40 IO_12 IO_13 GND IO_12 IO_13 GND IO_12 IO_13 GND IO_12
8 5 6 3 4 1 2
50 IO_12 GND IO_12 IO_12 GND IO_11 IO_12 GND IO_11 IO_12
9 0 7 8 5 6 3
60 GND IO_11 IO_12 GND IO_11 IO_11 GND IO_11 IO_11 GND
4 1 2 9 0 7
8 5 6 3 4 1 2
9 0 7 8 5 6 3
4 1 2 9 0 7
8 5 6 3 4 1 2
9 0 7 8 5 6 3
4 1 2 9 0 7
5 6 3 4 1 2
9 0 7 8 5 6 3
4 1 2 9 0 7
8 5 6 3 4 1 2
Table 3-7. Common pins 1 to 280 (cont.)

+1 +2 +3 +4 +5 +6 +7 +8 +9 +10
9 0 7 8 5 6 3
4 1 2 9 0 7
8 5 6 3 4 1 2
9 0 7 8 5 6 3
210 GND IO_01 IO_02 GND IO_01 IO_01 GND IO_01 IO_01 P3V3_
4 1 2 9 0 7 AUX
220 IO_00 IO_01 GND IO_00 IO_01 GND IO_00 IO_01 GND SCL
8 5 6 3 4 1
230 IO_00 GND IO_00 IO_00 GND GND IO_00 GND SDA GND
9 2 7 5
240 GND IO_00 IO_00 GND TCK TMS GND PV_R GND CLK_I
0 3 EF O_N_0
250 GND IO_00 GND TDO GND TDI GND GND GND CLK_I
1 O_P_0
260 CLK_I GND CLK_I GND CLK_I GND CLK_I GND CLK_I GND
O_N_7 O_N_5 O_N_3 O_N_2 O_N_1
270 CLK_I GND CLK_I GND CLK_I GND CLK_I GND CLK_I GND
O_P_7 O_P_5 O_P_3 O_P_2 O_P_1
A1 Motherboard-to-FPGA Connector
Table 3-8. Pins 281 to 400 of the Connectors XMTA1, XMTC1, XMTA3, and
XMTC3 (on Motherboard) and XMBA1 (on FPGA Module)
+1 +2 +3 +4 +5 +6 +7 +8 +9 +10
280 GND CLK_I GND CLK_I GND n.c. GND SRC_S GND SRC_S
O_N_6 O_N_4 YNC_ YNC_
N_3 N_2
290 GND CLK_I GND CLK_I GND n.c. GND SRC_S GND SRC_S
O_P_6 O_P_4 YNC_ YNC_
P_3 P_2
300 n.c. GND n.c. GND n.c. GND SRC_ GND SRC_ GND
CLK_ CLK_
N_3 N_2
XMTC3 (on Motherboard) and XMBA1 (on FPGA Module) (cont.)
+1 +2 +3 +4 +5 +6 +7 +8 +9 +10
310 n.c. GND n.c. GND n.c. GND SRC_ GND SRC_ GND
CLK_ CLK_
P_3 P_2
320 GND SRC_S GND SRC_S GND SYNC GND SYNC GND SYNC
YNC_ YNC_ _N_7 _N_6 _N_5
N_1 N_0
330 GND SRC_S GND SRC_S GND SYNC GND SYNC GND SYNC
YNC_ YNC_ _P_7 _P_6 _P_5
P_1 P_0
340 SRC_ GND SRC_ GND CLK_ GND CLK_ GND CLK_ GND
CLK_ CLK_ N_7 N_6 N_5
N_1 N_0
350 SRC_ GND SRC_ GND CLK_ GND CLK_ GND CLK_ GND
CLK_ CLK_ P_7 P_6 P_5
P_1 P_0
360 GND SYNC GND SYNC GND SYNC GND SYNC GND SYNC
_N_4 _N_3 _N_2 _N_1 _N_0
370 GND SYNC GND SYNC GND SYNC GND SYNC GND SYNC
_P_4 _P_3 _P_2 _P_1 _P_0
380 CLK_ GND CLK_ GND CLK_ GND CLK_ GND CLK_ GND
N_4 N_3 N_2 N_1 N_0
390 CLK_ GND CLK_ GND CLK_ GND CLK_ GND CLK_ GND
P_4 P_3 P_2 P_1 P_0
A2 Motherboard-to-FPGA Connector
XMTC4 (on Motherboard) and XMBA2 (on FPGA Module)
+1 +2 +3 +4 +5 +6 +7 +8 +9 +10
280 GND CLK_I GND CLK_I GND n.c. GND n.c. GND n.c.
O_N_6 O_N_4
290 GND CLK_I GND CLK_I GND n.c. GND n.c. GND n.c.
O_P_6 O_P_4
300 DMBI GND DMBI GND DMBI GND DMBI GND DMBI GND
_F2H_ _F2H_ _F2H_ _F2H_ _F2H_
18 16 14 12 10
XMTC4 (on Motherboard) and XMBA2 (on FPGA Module) (cont.)
+1 +2 +3 +4 +5 +6 +7 +8 +9 +10
_F2H_ _F2H_ _F2H_ _F2H_ _F2H_
19 17 15 13 11
320 GND DMBI GND DMBI GND DMBI GND DMBI GND DMBI
_F2H_ _F2H_ _F2H_ _F2H_ _F2H_
08 06 04 02 00
_F2H_ _F2H_ _F2H_ _F2H_ _F2H_
09 07 05 03 01
_H2F_ _H2F_ _H2F_ _H2F_ _H2F_
18 16 14 12 10
_H2F_ _H2F_ _H2F_ _H2F_ _H2F_
19 17 15 13 11
_H2F_ _H2F_ _H2F_ _H2F_ _H2F_
08 06 04 02 00
_H2F_ _H2F_ _H2F_ _H2F_ _H2F_
09 07 05 03 01
380 CFG_n GND CFG_ GND CFG_n GND CFG_ GND CFG_ GND
CS CLK_ CLEA DONE STAT
N R US
390 CFG_ GND CFG_ GND n.c. GND n.c. GND n.c. GND
RDnW CLK_
R P
Extension Board Connectors and B1/B2 Motherboard-to-FPGA Connector

Table 3-10. Pins 281 to 400 of the Connectors Xexxx (Extension Board
Connectors), XMTBx and XMTDx (on Motherboard), and XMBBx (on FPGA
Module)
+1 +2 +3 +4 +5 +6 +7 +8 +9 +10
280 GND CLK_I GND CLK_I GND MGT_ GND MGT_ GND MGT_
O_N_6 O_N_4 RX_N RX_N RX_N
_11 _10 _09
Table 3-10. Pins 281 to 400 of the Connectors Xexxx (Extension Board
Connectors), XMTBx and XMTDx (on Motherboard), and XMBBx (on FPGA
Module) (cont.)
+1 +2 +3 +4 +5 +6 +7 +8 +9 +10
290 GND CLK_I GND CLK_I GND MGT_ GND MGT_ GND MGT_
O_P_6 O_P_4 RX_P_ RX_P_ RX_P_
11 10 09
300 MGT_ GND MGT_ GND MGT_ GND MGT_ GND MGT_ GND
RX_N RX_N RX_N RX_N RX_N
_08 _07 _06 _05 _04
RX_P_ RX_P_ RX_P_ RX_P_ RX_P_
08 07 06 05 04
320 GND MGT_ GND MGT_ GND MGT_ GND MGT_ GND MGT_
RX_N RX_N RX_N RX_N TX_N
_03 _02 _01 _00 _11
RX_P_ RX_P_ RX_P_ RX_P_ TX_P_
03 02 01 00 11
TX_N TX_N TX_N TX_N TX_N
_10 _09 _08 _07 _06
TX_P_ TX_P_ TX_P_ TX_P_ TX_P_
10 09 08 07 06
TX_N TX_N TX_N TX_N TX_N
_05 _04 _03 _02 _01
TX_P_ TX_P_ TX_P_ TX_P_ TX_P_
05 04 03 02 01
TX_N REFC REFC REFC REFC
_00 LK_N LK_N LK_N LK_N
_3 _2 _1 _0
TX_P_ REFC REFC REFC REFC
00 LK_P_ LK_P_ LK_P_ LK_P_
3 2 1 0
Noise values of system
Noise values of system

The fans on each motherboard, ATX Power Supply and FPGA module produce a certain
amount of noise. Even if the systems are quite silent, they can be heard in a silent environment.
Therefore, we have measured the noise of them as a reference.
One system contains the following components:
• ATX Power Supply with FAN setting to ‘Normal’ (FAN on all the time)
• Quad Motherboard
• Four FM-XCVU440-R2 FPGA modules
Table 3-11. Measured Noise Values of Multi-FPGA proFPGA Systems

No. of systems No. of FPGAs Noise value in Idle Noise value in
Mode booted up mode
1 4 31.0 dB 42.0 dB
2 8 34.1 dB 45.0 dB
3 12 35.8 dB 46.8 dB
4 16 37.0 dB 48.0 dB
5 20 38.0 dB 49.0 dB
6 24 38.8 dB 49.8 dB
Chapter 4
Motherboards
This chapter lists special implementation details of each mother board. A general description of
motherboard functionality is provided in the previous chapter.
Generation 1 Motherboards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Generation 2 Motherboards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Motherboard Interconnect Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Functional Description
This topic is about Functional Description.
The proFPGA motherboard provides the majority of system-level hardware, including:
• Power Supply and Power Protection

• Configurable Clock Generators and Clock Distribution
• I²C based System Management
• JTAG Chain
• MMI-64 Communication Access
• Multi-motherboard System Extension
Motherboards
Generation 1 Motherboards
This topic is about Generation 1 Motherboards.
MB-4M-R1, MB-4M-R2 (Quad Motherboard) and MB-2M-R1 (Duo Motherboard) . 98
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
MB-1M-R1, MB-1M-R2 (Uno Motherboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
proFPGA PCIe DMBI Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
MB-4M-R1, MB-4M-R2 (Quad Motherboard) and MB-

2M-R1 (Duo Motherboard)
This topic is about MB-4M-R1, MB-4M-R2 (Quad Motherboard) and MB-2M-R1 (Duo
Motherboard)
Hardware Overview
Figure 4-1. MB-4M-R2 Top-side Components
Motherboards
MB-4M-R1, MB-4M-R2 (Quad Motherboard) and MB-2M-R1 (Duo Motherboard)
Table 4-1. MB-4M-R2 and MB-2M-R1 Top-side Connectors and Switches

Number Designator Function Notes
1 S7 On/Off Switch
2 XETH2 Ethernet Connector 100 Mbit Fast
Ethernet for MMI64
communication
access
3 - System status LEDs
4 XMTA1 FPGA A1 Connector
8 XMTB1 FPGA A1 Connector
12 XMTC1 FPGA C1 Connector
16 XMTD1 FPGA C1 Connector
Motherboards

20 XNMB1 Next Motherboard Connection to next
Connector MB via cable
Figure 4-3. MB-4M-R2 Bottom-side Components
Motherboards
Table 4-2. MB-4M-R2 and MB-2M-R1 Bottom-side Connectors and Switches

1 XPWR2 12V Power Connector Power Input for
proFPGA system
proFPGA system
proFPGA system
proFPGA system
5 XUSB1 Mini USB Connector supervisor CPU USB
OTG connector
6 XUSB2 USB-B Connector Connector for USB
Stick
7 XUSB3 Mini USB Connector Supervisor CPU TTY
8 XUSD1 Micro SD-Card Hard Disk for
Connector Supervisor CPU
9 XCLKIO{0…3}XSY MMCX Connectors External Clock/Sync
NCIO{0…3} Inputs and Outputs
10 XJTAG1 Xilinx JTAG JTAG Connector for
Connector programming User
FPGAs via Xilinx
Programmer
11 XJTAG2 Intel JTAG Connector JTAG Connector for
programming User
FPGAs via Intel
FPGA Download
Cable
12 XEBA1 Extension Board connected to FPGA
Connector A1
Connector A1
Connector A3
Connector A3
16 XEBB1 Extension Board connected to FPGA
Connector A1
Motherboards
Status LEDs
Table 4-2. MB-4M-R2 and MB-2M-R1 Bottom-side Connectors and Switches

Connector A1
Connector A3
Connector A3
20 XEBC1 Extension Board connected to FPGA
Connector C1
Connector C1
Connector C3
Connector C3
24 XEBD1 Extension Board connected to FPGA
Connector C1
Connector C1
Connector C3
Connector C3
28 XPCIE1 PCI-Express Connector for
Extension Board Extension Board
Connector making it possible to
use PCIe Gen 1 with 4
lanes
29 XPMB1 Previous Motherboard Connection to
Connector previous MB via cable
Status LEDs
This topic is about Status LEDs
In the table below, elements marked with (1) are not available on MB-4M-R1 motherboards.
Motherboards
Status LEDs
Table 4-3. LEDs on MB-4M

LED Marking Color Description
Temperature Alerts
D47: CtrlFPGA overtemp red control FPGA temperature
alert
D61: MB overtemp(1) red motherboard temperature alert
System Status
D54: Master(1) yellow master motherboard (or single
motherboard)
D57: User Run(1) blue User FPGA configuration
done, system ready for user
run
D55: PCIe Link(1) green PCIe link established
D13: ETH Link(1) green MMI-64 connection via

Ethernet established
D56: MMI Active(1) green MMI-64 activity
D33: CtrlFPGA done green control FPGA configuration
done
D12: Heart Beat green supervisor CPU running
Ethernet Status
D29: Full Duplex green Ethernet link full-duplex
D30: Speed 100 green Ethernet link 100 Mbit (LED
off: 10 Mbit)
D31: Link & Act green Ethernet link activity
Voltage Status
D24: P3V3_AUX green 3.3V power supply for I²C
system management(all
extension board sites)
D23: P3V3 green 3.3V additional power supply
for user logic (all extension
board sites)
D50: A1 green 12V main power for FPGA
site A1 (connectors XMTA1,
XEBA1, …, XMTB2,
XEBB2)
Motherboards
Status LEDs
Table 4-3. LEDs on MB-4M (cont.)

D51: C1 green 12V main power for FPGA
site C1 (connectors XMTC1,
XEBC1, …, XMTD2,
XEBD2)
D52: A3 green 12V main power for FPGA
site A3 (connectors XMTA3,
XEBA3, …, XMTB4,
XEBB4)
D53: C3 green 12V main power for FPGA
site C3(connectors XMTC3,
XEBC3, …, XMTD4,
XEBD4)
Electrical Characteristics
Table 4-4. MB-4M Electrical Characteristics

Parameter Description Min Max
V(XPWR1…4) external supply voltage 10V 14V
Note: min/max is limited by overvoltage/
undervoltage protection
I(XPWR1…4) supply current (per power connector) - 25A
Note: max is limited by overcurrent
detection
Power Protection
- Overcurrent detection - 25A
- Voltage Reverse Detection - -
Note: Detection of wrong polarity of power
input voltage
- Short circuit protection - -
- All Inputs powered detection - -
Note: Detection if all XPWR are connected
and powered
- Overvoltage detection 14V -
- Undervoltage detection - 10V
Motherboards
Status LEDs
Table 4-4. MB-4M Electrical Characteristics (cont.)

V(P12V) 12V supply voltage tolerance ±5%
I(P12V_FPGA) 12V supply current limit per FPGA site - 20A
I(P12V_conn) 12V supply current limit per connector - 5A
V(P3V3) 3.3V supply voltage tolerance - ±5%
I(P3V3_MB) 3.3V supply current limit for whole MB - 15A
I(P3V3_conn) 3.3V supply current limit per connector - 2A
V(P3V3AUX) 3.3V auxiliary voltage tolerance ±5%
I(P3V3AUX_MB) 3.3V auxiliary current limit for whole MB - 6A
I(P3V3AUX_conn) 3.3V auxiliary current limit per connector - 1A
Configurable Clock Generator
V(XCLKIO[i]) external input clock voltage LVCMOS25
f(XCLKIO[i]) external input clock frequency 10 MHz 125 MHz
f(GEN.VCO) intermediate MMCM clock frequency 600 MHz 1200
(after multiplication, before division) MHz
f(GEN.clk[i]) clock frequency to motherboard 4.69 MHz 400 MHz
Clock Distribution
f(CLK_MB) clock frequency on single motherboard 0 400 MHz
f(CLK_MB2MB) clock frequency for multi-motherboard 20 MHz 250 MHz
systems
Data Rates
Config(MB-FPGA) SelectMap configuration 200
MByte/s
MMI(MB-FPGA) MMI-64 data rate between MB and FPGA
MMI(MB-PCIe) MMI-64 data rate over PCIe
MMI(MB-MB) MMI-64 data rate between two MBs
JTAG JTAG TCK frequency 6 MHz
I²C I²C system clock (SCL)
Order Codes
286413 (MB-4M-R2)
286412 (MB-2M-R1)
Motherboards
MB-1M-R1, MB-1M-R2 (Uno Motherboard)

This topic is about MB-1M-R1,MB-1M-R2 (Uno Motherboard).
Variants
Two variants exist of the 1-FPGA motherboard:
Table 4-5. Variants of MB-1M Motherboards
Board/ Comment
Product
Name
MB-1M-R1 • Four extension board site connectors (top site)
• USB 2.0 MMI64 communication interface
MB-1M-R2 • Eight extension board site connectors (top and bottom site)
• USB 2.0 MMI64 communication interface
• 100 Mbit/s Ethernet MMI64 communication interface
Compared to the MB-2M and MB-4M motherboards there are the following major differences:
• Support for one FPGA module only

• Fixed master clock signal generation
• No clock/sync routing from FPGA into the clock/sync network
• No motherboard-to-motherboard connection (cannot be used to enhance MB-2M/4M
systems)
• No 100 Mbit/s Ethernet MMI64 communication interface on MB-1M-R1
• No PCIe MMI64 communication interface
• Four extension board site connectors on MB-1M-R1 (eight on MB-1M-R2)
Motherboards
Hardware Overview
Figure 4-5. MB-1M-R1 and MB-1M-R2 Top-side Components
In the table below elements marked with (1) are not available on MB-1M-R1 motherboards
1 S7 On/Off Switch
8 XMTB1 FPGA B1 Connector
9 XMTB2 FPGA B2 Connector
Motherboards
Motherboards
Table 4-7. MB-1M Bottom-side Connectors and Switches

1 XPWR2 12V Power Power Input for
Connector proFPGA system
2 XETH2(1) Ethernet Connector 100 Mbit Fast
Ethernet for MMI64
communication
access
5 XUSB1 Mini USB Connector supervisor CPU USB
OTG connector
Stick
7 XUSB3 Mini USB Connector Supervisor CPU
TTY
8 XUSD1 Micro SD-Card Hard Disk for
Connector Supervisor CPU
FPGAs via Xilinx
Programmer
11 XJTAG2 Intel JTAG JTAG Connector for
FPGAs via Intel
FPGA Download
Cable
Connector A1
Connector A1
Connector A1
Connector A1
Status LEDs
In the table below, elements marked with (R2) are only available MB-1M-R2.
Table 4-8. LEDs On MB-1M
System Status
Motherboards
Table 4-8. LEDs On MB-1M (cont.)

ETH Link(R2) green MMI-64 connection via Ethernet
established
FPGA done green control FPGA configuration done
Heart Beat green supervisor CPU running
Ethernet Status
Full Duplex(R2) green Ethernet link full-duplex
Speed 100(R2) green Ethernet link 100 Mbit (LED off: 10 Mbit)
Link & Act(R2) green Ethernet link activity

Voltage Status
P3V3_AUX green 3.3V power supply for I²C system
management(all extension board sites)
PGOOD green Power-good for all motherboard power
supplies
A1 green Power-good for all motherboard power
supplies
Table 4-9. MB-1M Electrical Characteristics
V(XPWR1) external supply voltage Note: min/max is limited 10V 14V
by overvoltage/undervoltage protection
I(XPWR1) supply current (per power connector)Note: max is - 25A
limited by overcurrent detection
Power Protection
- Overcurrent detection - 25A
- Voltage Reverse DetectionNote: Detection of - -
wrong polarity of power input voltage
- Short circuit protection - -
- All Inputs powered detectionNote: Detection if all - -
XPWR are connected and powered
- Overvoltage detection 14V -
Motherboards
proFPGA PCIe DMBI Kit
Table 4-9. MB-1M Electrical Characteristics (cont.)

- Undervoltage detection - 10V
V(P12V) 12V supply voltage tolerance ±5%
I(P12V_FPGA) 12V supply current limit per FPGA site - 20A
I(P12V_conn) 12V supply current limit per connector - 5A
V(P3V3) 3.3V supply voltage tolerance - ±5%
I(P3V3_MB) 3.3V supply current limit for whole MB - 15A
I(P3V3_conn) 3.3V supply current limit per connector - 2A
V(P3V3AUX) 3.3V auxiliary voltage tolerance ±5%
I(P3V3AUX_MB) 3.3V auxiliary current limit for whole MB - 6A
I(P3V3AUX_conn) 3.3V auxiliary current limit per connector - 1A
Data Rates
Config(MB-FPGA) SelectMap configuration 200
MByt
e/s
MMI(MB-FPGA) MMI-64 data rate between MB and FPGA
JTAG JTAG TCK frequency 6
MHz
I²C I²C system clock (SCL)
Oder Codes
286411

This topic is about proFPGA PCIe DMBI Kit.
Note
This section does not apply to MB-1M motherboards.
Motherboards
Figure 4-8. proFPGA PCIe DMBI Kit
The proFPGA solution provides the user the possibility to configure, monitor and manage the
system remotely from the host with help of the DMBI (Device Message Box Interface) over
several interfaces like USB2.0 and Ethernet. While the Ethernet or USB interface offers the user
a data exchange rate of max. 100 Mbps the proFPGA PCIe DMBI Interface Kit significantly
increases the data exchange performance with up to 3.2 Gbps, which is 32 times faster than over
the Ethernet interface.
Because of this high data exchange rate, the user can benefit besides the remote system
configuration from the capability to use this high speed interface most efficiently for debugging
purposes like data streaming or sending and receiving of test pattern and so on.
The kit consists of a proFPGA PCIe gen1 DMBI connector board, which will be plugged on a
dedicated connector of the proFPGA duo or quad system, a proFPGA PCIe gen3 4-lane host
interface card and a dedicated high performance cable.
For further information to the proFPGA PCIe gen3 4-lane host interface card please refer to
PCIe 4-lane Host Interface Card (PCIex4_HostCableAdaptor-R2).
DIP Switch Settings for EB-MB-PCIe-Cable-R3

Table 4-10. EB-MB-PCIe-Cable-R3: Settings for DIP Switch S1
Pin Signal Switch Position Logic Signal
1 S0_A ON 0
2 [S1_A] OFF 1
3 [SEL0_A] OFF 1
Motherboards
Table 4-10. EB-MB-PCIe-Cable-R3: Settings for DIP Switch S1 (cont.)

4 SEL1_A OFF 1
5 [SEL2_A] OFF 1
6 [D0_A] OFF 1
7 P1_A__D1_A ON 0
8 nRDX_RES__D2_A OFF 1
9 VTH0__DE_A OFF 1
10 VTH1 OFF 1
Table 4-11. EB-MB-PCIe-Cable-R3: Settings for DIP Switch S2

1 S0_B ON 0
2 S1_B] OFF 1
3 [SEL0_B] OFF 1
4 SEL1_B OFF 1
5 [SEL2_B] OFF 1
6 [D0_B] OFF 1
7 P1_B__D1_B ON 0
8 [D2_B] OFF 1
9 [DE_A] OFF 1
10 - - -
Order Code
Content Order Code

EB-MB-PCIe-Cable-R3, 4-lane compatible 3 m length cable, 286548
PCIeGen3x4_HostCableAdaptor-R1
EB-MB-PCIe-Cable-R3 286547
Motherboards
This chapter is about generation 2 motherboards.
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
MB-4M-R3 (Quad Motherboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
proFPGA PCIe DMBI Kit Gen 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Features
This topic is about features.
Generation 2 is a further development of the Motherboards with updated and extended features.
Additional to the improvements of performance in comparision to Generation 1, the Generation
2 Motherboards are prepared for future demands of new FPGA generations. Following list will
give an overview of the improvements and new features:
• The use of PCIe is possible without rebooting the PC because the PCIe PHY is on the
extension board card.
• The motherboard PCIe connection is upgraded to PCIe gen 2 x4.
• Due to the turn of the TA3 and TC3 FPGA sections by 180° (now called FA2 and FB2)
there is more room for extensions because the direction of the upper edge of each FPGA
module is now away from the motherboard.
• Ethernet speed is now 1 Gbit/s instead of 100 Mbit/s.
• The generation 2 motherboard has a more powerful controller.
• Firmware upgrades on the board are easier to handle.
MB-4M-R3 (Quad Motherboard)

This topic is about MB-4M-R3 (Quad Motherboard)
Motherboards
Hardware Overview
Table 4-12. MB-4M-R3 Top-side Interfaces

1 S7 On/Off Switch
2 XETH1 Ethernet Connector Gigabit Fast Ethernet
for MMI64
communication
access
4 FA1TA1 FPGA FA1
Connector
5 FA1TA2 FPGA FA1
Connector
Motherboards
Table 4-12. MB-4M-R3 Top-side Interfaces (cont.)

6 FA2TB2 FPGA FA2
Connector
7 FA2TB1 FPGA FA2
Connector
8 FA1TB1 FPGA FA1
Connector
9 FA1TB2 FPGA FA1
Connector
10 FA2TA2 FPGA FA2
Connector
11 FA2TA1 FPGA FA2
Connector
12 FB1TA1 FPGA FB1
Connector
13 FB1TA2 FPGA FB1
Connector
14 FB2TB2 FPGA FB2
Connector
15 FB2TB1 FPGA FB2
Connector
16 FB1TB1 FPGA FB1
Connector
17 FB1TB2 FPGA FB1
Connector
18 FB2TA2 FPGA FB2
Connector
19 FB2TA1 FPGA FB2
Connector
20 XNMB1 Next Motherboard Connection to next
Connector MB via cable
21 XUSD1 Micro SD-Card Non volatile memory
Connector for Supervisor CPU
22 XJTAG2 Intel JTAG JTAG Connector for
FPGAs via Intel
FPGA Download
Cable
Motherboards
Table 4-12. MB-4M-R3 Top-side Interfaces (cont.)

23 S8 MB Soft Reset Resets Supervisor
Pushbutton CPU
24 XQSFP1 QSFP+ Port Enables PCI-Express
Gen 2 (4-Lanes)
connection to host
PC via proFPGA
PCIe DMBI Kit
Gen2
25 - Function-Module
power status LEDs
26 - Function modul
orientation indication
Figure 4-10. MB-4M-R3 Bottom-side Interfaces and Components
Caution
Please consider changed function modul orientation for Sites FA2 and FB2!
Motherboards
Table 4-13. MB-4M-R3 Top-side Interfaces and Components

1 FB1BB1 FPGA FB1
Connector
2 FB1BB2 FPGA FB1
Connector
3 FB2BA1 FPGA FB2
Connector
4 FB2BA1 FPGA FB2
Connector
5 FB1BA1 FPGA FB1
Connector
6 FB1BA2 FPGA FB1
Connector
7 FB2BB2 FPGA FB2
Connector
8 FB2BB1 FPGA FB2
Connector
9 FA1BB1 FPGA FA1
Connector
10 FA1BB2 FPGA FA1
Connector
11 FA2BA2 FPGA FA2
Connector
12 FA2BA1 FPGA FA2
Connector
13 FA1BA1 FPGA FA1
Connector
14 FA1BA2 FPGA FA1
Connector
15 FA2BB2 FPGA FA2
Connector
16 FA2BB1 FPGA FA2
Connector
17 XUSB3 Mini USB Connector Supervisor CPU
TTY
Stick
Motherboards
Table 4-13. MB-4M-R3 Top-side Interfaces and Components (cont.)

19 XUSB1 Mini USB Connector Connector for USB
Devices
20 XCLKIO{0…3} External Clock/Sync
XSYNCIO{0…3} Inputs and Outputs
XDCLKIO{}
25 XBAT1 Battery for Real
Time Clock
26 XPMB1 Previous Connection to
Motherboard previous MB via
Connector cable
27 XSD1 RFU
FPGAs via Xilinx
Programmer
29 XEXT1 RFU
30 - Function modul
orientation indication
31 S8 MB Soft Reset Resets Supervisor
Pushbutton CPU
Status LEDs
Table 4-14. Status LEDs of MB-4M-R3
Temperature
Alerts
Motherboards
Table 4-14. Status LEDs of MB-4M-R3 (cont.)

MB overtemp red motherboard
temperature
alert
FPGA TEMP red control FPGA
temperature
alert
Ethernet Status
D29: Full green Ethernet link
Duplex full-duplex
D30: Speed green Ethernet link
1000 1000 Mbit
(LED off: 100
Mbit)
D31: Link & green Ethernet link
Act activity
System Status Figure 4-11. Status LEDs
Master yellow master
motherboard (or
single
motherboard)
User Run blue User FPGA
configuration
done, system
ready for user
run
PCIe Link green PCIe link
established
ETH Link green MMI-64
connection via
Ethernet
established
MMI Active green MMI-64
activity
FPGA done green control FPGA
configuration
done
Heart Beat green supervisor CPU
running
Motherboards

Voltage Status
Motherboards

P3V3_AUX green 3.3V power Figure 4-12. Power Status
supply for I²C LEDs
system
management
(all extension
board sites)
P3V3 green 3.3V additional
power supply
for user
logic(all
extension board
sites)
D50 FA1 green 12V main
power for
FPGA site
FA1(connectors
FA1TA1,
FA1BA1, …,
FA1TB2,
FA1BB2)
D51 FB1 green 12V main
power for
FPGA site FB1
(connectors
FB1TA1,
FB1BA1, …,
FB1TB2,
FB1BB2)
D52 FA2 green 12V main
power for
FPGA site FA2
(connectors
FA2TA1,
FA2BA1, …,
FA2TB2,
FA2BB2)
D53 FB2 green 12V main
power for
FPGA site FB2
(connectors
FB2TA1,
FB2BA1, …,
FB2TB2,
FB2BB2)
Motherboards
Table 4-15. Electrical Characteristics of MB-4M-R3
V(XPWR1…4) external supply 10V 14V
voltageNote: min/
max is limited by
over-/undervoltage
protection
I(XPWR1…4) supply current (per - 25A
power connector)
Note: max is limited
by overcurrent
detection
Power Protection
- Overcurrent - 25A
detection
- Voltage Reverse - -
DetectionNote:
Detection of wrong
polarity of power
input voltage
- Short circuit - -
protection
- All Inputs powered - -
detectionNote:
Detection if all
XPWR are
connected and
powered
- Overvoltage 14V -
detection
- Undervoltage - 10V
detection
V(P12V) 12V supply voltage ±5%
tolerance
I(P12V_FPGA) 12V supply current - 20A
limit per FPGA site
Motherboards
Table 4-15. Electrical Characteristics of MB-4M-R3 (cont.)

I(P12V_conn) 12V supply current - 5A
limit per connector
V(P3V3) 3.3V supply voltage - ±5%
tolerance
I(P3V3_MB) 3.3V supply current - 15A
limit for whole MB
I(P3V3_conn) 3.3V supply current - 2A
limit per connector
V(P3V3AUX) 3.3V auxiliary ±5%
voltage tolerance
I(P3V3AUX_MB) 3.3V auxiliary - 6A
current limit for
whole MB
I(P3V3AUX_conn) 3.3V auxiliary - 1A
current limit per
connector
Configurable Clock Generator
V(XCLKIO[i]) external input clock LVCMOS25
voltage
f(XCLKIO[i]) external input clock 10 MHz 125 MHz
frequency
f(GEN.VCO) intermediate MMCM 600 MHz 1200 MHz
clock frequency
(after multiplication,
before division)
f(GEN.clk[i]) clock frequency to 4.69 400 MHz
motherboard
Clock Distribution
f(CLK_MB) clock frequency on 0 400 MHz
single motherboard
f(CLK_MB2MB) clock frequency for 20 MHz 250 MHz
multi-motherboard
systems
Data Rates
Config(MB-FPGA) SelectMap 200 MByte/s
configuration
Motherboards
proFPGA PCIe DMBI Kit Gen 2
Table 4-15. Electrical Characteristics of MB-4M-R3 (cont.)

MMI(MB-FPGA) MMI-64 data rate
between MB and
FPGA
MMI(MB-PCIe) MMI-64 data rate
over PCIe
MMI(MB-MB) MMI-64 data rate
between two MBs
JTAG JTAG TCK 6 MHz
frequency
I2C I²C system clock
(SCL)
Order Codes
286414 (MB-4M-R3)
proFPGA PCIe DMBI Kit Gen 2

This topic is about proFPGA PCIe
Motherboards
Figure 4-13. proFPGA PCIe DMBI Kit Gen 2
Generation 2 motherboards PCIe connection is realized with new adapter card plugged into the
PC. The connection between proFPGA motherboard and adapter board is established with a
QSFP+ cable. A PCIe gen 2 x4 connection will be established between the PC and the proFPGA
motherboard. The PCIe core is running on the adapter board. Therefore, the proFPGA
motherboard can be started and rebooted at any time without rebooting the PC.
Order Code
286549

This topic is about Motherboard Internconnect Cable
Functional description
Caution
This section does not apply to MB-1M motherboards.
Motherboards
Functional description
The motherboard interconnect cable (IC-MB-CABLE) provides connections for bidirectional
DMBI communication and clock distribution. Each motherboard has two connectors:
• XNMB1 next motherboard

• XPMB1 previous motherboard
The motherboard interconnect cable connects XNMB1 on the first motherboard with XPMB1
on the second motherboard. The motherboard with only XNMB1 connection (i.e. without
XPMB1 connection) is denoted as the “master”. The first slave is connected directly to the
master (master.XNMB1->slave1.XPMB1). Further motherboards can be added by daisy
chaining (slave1.XNMB1->slave2.XPMB1, slave2.XNMB1->slave3.XPMB1, …).
Figure 4-14. IC-MB-Cable Motherboard Chaining
Only the master motherboard is available for external DMBI access (USB cable, Ethernet,
DMBI PCIe cable).
Caution
Motherboards with a valid connection on XPMB1 will ignore external communication
channels.
Clocks can be distributed from any motherboard.
Tip
For systems with three or more motherboards, it is recommended to distribute the clock
from a motherboard close to the system center (e.g. Slave #1 in Figure 4-14). This will
decrease the system clock skew.
Related Work
Multi-motherboard system operations are described in Multi-Motherboard Systems. The
connector pin layout is described in Motherboard Interconnect Cable.
Order Code
286529
Motherboards
Chapter 5
FPGA Modules
This chapter discusses different FPGA modules.
Virtex 7 FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Zynq7000 FPGA Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Reset Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SD Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
USB OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Local clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DDR3 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Dual Quad SPI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Virtex Ultrascale FPGA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
FPGA Modules
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Firmware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Kintex Ultrascale FPGA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Firmware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Virtex Ultrascale+ FPGA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Reference Clocks at V2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Firmware requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Zynq Ultrascale+ MPSoC FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
PS Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
PUDC_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
FPGA Modules

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Stratix 10 FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Temperature Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
FM-1SG10M-R1 Motherboard Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Arria 10 FPGA Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
I/O Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
FPGA Modules
Virtex 7 FPGA Modules
Virtex 7 FPGA Modules

This topic discusses Virtex 7 FPGA modules.

Extension Board Connector Bank Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Other Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
I/O Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
The proFPGA FPGA modules are intended for the user designs.
Several FPGA types and speed grades are available. Each proFPGA FPGA module provides the
following functions:
• specific for every FPGA type

o specific for every FPGA type
• common for all FPGA types
o debug connectors
o status LEDs
o I/O power supply
o JTAG connection
This chapter will combine the descriptions for most of the FPGA modules whenever possible.
Extension Board Connector Bank Assignment

This topic discusses extension board connector bank assignment in Virtex 7 FPGA modules.
FPGA Modules
Note
The detailed pin assignment is specified in the UCF/XDC constraints files provided with the
design data.
Note
With the profpga_brdgen tool top level HDL files and pin location constraints files can be
generated depending on the FPGA module and connector position the extension board is
plugged onto.
Please refer to the “proFPGA Software Reference Manual” [SWRM] and the “proFPGA
Builder User Manual” [UD004] for more information.
Note
Information about the I/O connector pin assignment and the mapping of the MGTs within
the FPGA can be found in the “proFPGA Extension Board Design Guide” [UD003].
FM-XC7V2000T-R1/R2 (Virtex-7 2000T)

Figure 5-1. Mapping of FM-XC7V2000T I/O Banks to Connectors
In the table below, the resources marked with (R1) or (R2) are only available on FM-
XC7V2000T-R1 or FM-XC7V2000T-R2 respectively. R2 boards support DCI and require two
pins per connector for reference voltage.
FPGA Modules
Table 5-1. FM-XC7V2000T – Board Connectors

Connector I/O Banks Pins MGT Banks Channels Service
XETA1 20, 21, 22 150(R1)/
148(R2)
XETA2 34, 35, 36 150(R1)/
148(R2)
XETB1 37, 38, 39 150(R1) none(R1) 8xTX,
8xRX(R2)
148(R2) 114, 115(R2)
XETB2 31, 32, 33 150(R1) 114, 115(R1) 8xTX, 8xRX
148(R2) 112, 113(R2)

XMBA1 17, 18, 19 150(R1)/ clk/sync,
srcclk/
148(R2)
srcsync
XMBA2 11, 12, 13 150(R1)/ MMI-64,
FPGA
148(R2)
config.
XMBB1 40, 41, 42 150(R1)/
148(R2)
XMBB2 16 50(R1) 112, 113(R1) 8xTX,
8xRX(R1)
48(R2) none(R2)
FM-XC7VX330T-R3 (Virtex-7 X330T)

In the image below, “HR” marks 7-series High-Range banks (PV_IOmax=3.3V). All other
banks are “HP” 7-series High-Performance banks (PV_IOmax=1.8V).
Figure 5-2. Mapping of FM-XC7VX330T-R3 I/O Banks to Connectors
FPGA Modules
In the table below, “HR” marks 7-series High-Range banks (PV_IOmax=3.3V). All other banks
are “HP” 7-series High-Performance banks (PV_IOmax=1.8V).
Table 5-2. FM-XC7VX330T-R3 – Board Connectors
XETA1 17,18,19 148 118, 119 8x RX, 8x
TX
XETA2HR 13 HR 48
XETB1 37,38,39 148 116,117 8x RX, 8x
TX
XETB2 33 48 113, 114,115 12x RX, 12x
TX
XMBA1 34,35,36 148 clk/sync,
srcclk/
srcsync
XMBA2 16 48 MMI-64,
FPGA
configuration
XMBB1 -
XMBB2 -

In the image below, all banks are 7-series High-Performance banks (PV_IOmax=1.8V).
FPGA Modules

XETA1 17,18,19 148 118, 119 8x RX, 8x
TX
XETA2HR 13 HR 48
XETB1 37,38,39 148 116,117 8x RX, 8x
TX
XETB2 33 48 113, 114,115 12x RX, 12x
TX
XMBA1 34,35,36 148 clk/sync,
srcclk/
srcsync
XMBA2 16 48 MMI-64,
FPGA
configuration
XMBB1 -
XMBB2 -
FM-XC7V585T-R3 (Virtex-7 585T)

Figure 5-4. Mapping of FM-XC7V585T-R3 I/O Banks to Connectors
are 7-series “HP” High-Performance banks (PV_IOmax=1.8V).
FPGA Modules
Table 5-4. FM-XC7V585T-R3 – Board Connectors

XETA1 17,18,19 148 118,119 8x RX, 8x
TX
XETA2HR 12HR13HR 98 111,112 8x RX, 8x
TX
XETB1 37,38,39 148 116,117 8x RX, 8x
TX
XETB2 31,32,33 148 113, 114,115 12x RX, 12x
TX
XMBA1 34,35,36 148 clk/sync,
srcclk/
srcsync
XMBA2 16 48 MMI-64,
FPGA
configuration
XMBB1 -
XMBB2 -

FPGA Modules
Other Connectors

XETA1 17,18,19 148 118,119 8x RX, 8x
TX
XETA2 12,13 98 111,112 8x RX, 8x
TX
XETB1 37,38,39 148 116,117 8x RX, 8x
TX
XETB2 31,32,33 148 113, 114,115 12x RX, 12x
TX
XMBA1 34,35,36 148 clk/sync,
srcclk/
srcsync
XMBA2 16 48 MMI-64,
FPGA
configuration
XMBB1 -
XMBB2 -
Other Connectors
This topic discusses other connectors in Virtex 7 FPGA modules.
Table 5-6. FPGA Modules – Other connectors

Connector Peer Description
XDBG1 UART/custom User debug port (compatible
with FTDI TTL-232R-3V3
cable)
XBAT1 Backup battery Backup battery for
encryption key (Varta
55996101501 1.2V)
The debug connector XDBG1 provides 4 user debug pins (Figure 5-6). The pin assignment is
compatible with the FTDI TTL-232R-3V3 cable which provides a UART. As the signals are
directly accessible by the user FPGA design, the pins may be used otherwise.
Note
All signals on XDBG1 run at 3.3V.
FPGA Modules
Status LEDs
Note
Because of the presence of voltage level shifters, there are two dedicated FPGA inputs
(UART_RXD, UART_CTS_B) and two dedicated FPGA outputs (UART_TXD,
UART_RTS_B).
Figure 5-6. FPGA Modules – XDBG1 connector. All pins run at 3.3V.
The direction of each pin is shown in the following table:

Signal FPGA Host
UART_TXD output input
UART_RXD input output
UART_CTSN input output
UART_RTSN output input
I/O standard of the UART signals: LVCMOS18
Status LEDs
This topic discusses status LEDs in Virtex 7 FPGA modules.
In the table below, LEDs marked with (R2/R3) are only available on FM-XC7V2000T-R2 and
FM-XC7Vxxx-R3.
Table 5-7. FPGA Modules – Status LEDs.
Power Supply
D1: BB2 green XMBB2 IO power good
D3: BA2 green XMBA2 IO power good
D4: BA1 green XMBA1 IO power good
D5: TB2 green XETB2 IO power good
D7: TA2 green XETA2 IO power good
FPGA Modules
I/O Power Supply
Table 5-7. FPGA Modules – Status LEDs. (cont.)

FPGA Status
D9: FPGA green FPGA core power good
D10: PROGDONE blue FPGA programming done
D11: FPGATemp red FPGA temperature alert
User LEDs
D13/D17: green(R2/R3) green driven by User FPGA
D14/D18: red(R2/R3) red driven by User FPGA
D15/D19: yellow(R2/R3) yellow driven by User FPGA
D16/D20: blue(R2/R3) blue driven by User FPGA
Two groups of four LEDs with different colors (green, red, yellow, blue) are available on each
FPGA module. One group is placed in the upper left (TA1) and one group in the lower left
corner (TB2) of the FPGA. The LEDs with the same color are connected to each other. This
means only four outputs are available at the FPGA: LED_green, LED_red, LED_yellow, and
LED_blue. E.g. when output LED_green is driven high by the FPGA, both green LEDs will
glow.
I/O standard of the user LEDs: LVCMOS18
Figure 5-7. Debug LEDs
I/O Power Supply

This topic discusses I/O power supply in Virtex 7 FPGA modules.
Each of the 8 board connectors has its individual power supply.
FPGA Modules
JTAG
Figure 5-8. FPGA Modules – I/O Power Supply
JTAG
This topic discusses JTAG in Virtex 7 FPGA modules.
The Virtex-7 JTAG port links into the A1 JTAG chain, making it the first device in the list. If no
JTAG devices are present (i.e. JTAG_PRESENT is 0 or floating), the JTAG chain will short-
circuit back to XMBA1. On all other board connectors, JTAG signals of top and bottom side are
directly connected (Figure 5-9).
Figure 5-9. FPGA Modules – JTAG chain
Order Codes
This topic discusses order codes of Virtex 7 FPGA modules.
FPGA Modules
Packages
FPGA Module Speed Grade Order Code

FM-XC7V2000T-R2 2 286645
The other Virtex 7 FPGAs are no longer available.
Packages
This topic discusses packages of Virtex 7 FPGA modules.
FPGA Module Part Number Package Available

Speed
Grades (*)
FM-XC7V2000T-R1/R2 XC7V2000T FLG1925 -1, -2
FM-XC7VX330T-R3 XC7VX330T FFG1761 -1, -2, -3
FM-XC7V585T-R3 XC7V585T FFG1761 -1, -2, -3
(*) Speed grades also depend on temperature rating
Firmware Requirements
This topic discusses firmware requirements for Virtex 7 FPGA modules.
FPGA Module Min. proFPGA Firmware

FM-XC7V2000T-R1/R2 -
FM-XC7VX330T-R3 2015A
FM-XC7V585T-R3 2015A
Service Banks Pin Constraints

This topic discusses service banks pin constraints in Virtex 7 FPGA modules.
FPGA Modules
Related Work
Table 5-8. FM-XC7Vxxx FPGA Pin Constraints

Signal IOSTANDARD
clk_n[*] IOSTANDARD = LVDS
clk_p[*]
sync_n[*]
sync_p[*]
src_clk_n[*]
src_clk_p[*]
src_sync_n[*]
src_sync_p[*]
dmbi_h2f[*] IOSTANDARD = LVCMOS18
dmbi_f2h[*]
led_*
uart_*
Related Work
This section discusses related work of Virtex 7 FPGA modules.
Board File Generator

plugged onto.
Demo Designs
Table 5-9. Virtex 7 FPGA Modules Demo Designs
Title Author Description
blinking_led Siemens User LED demo for Virtex 7
devices
mmi64_basic Siemens MMI64 demo for Virtex 7
devices
mmi64_axim Siemens MMI64 AXI Master demo
for Virtex 7 devices
mmi64_fm_pcie Siemens MMI64 PCIe Extension
Board demo for FM-
XC7V2000T-R2 and
XC7VX690T-R3
FPGA Modules
Related Work
Table 5-9. Virtex 7 FPGA Modules Demo Designs (cont.)

mmi64_reg Siemens MMI64 Register Interface
demo for Virtex 7 devices
mmi64_upstream Siemens MMI64 Upstream demo for
Virtex 7 devices
pd_muxdemux2 Siemens pd_muxdemux2 demo for
FM-XC7V2000T-R2
reset Siemens Reset demo for Virtex 7
devices
FPGA Modules
Zynq7000 FPGA Modules
Zynq7000 FPGA Modules

This topic discusses Zynq7000 FPGA modules.

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I/O Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Reset Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SD Memory Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
USB OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Local clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
DDR3 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Dual Quad SPI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
The proFPGA Zynq FPGA modules combine a user FPGA with an ARM Core processor
(System-On-Chip) and are intended for user designs.
The main features of all Zynq FPGA modules are:
• PL (Programmable Logic)
• PS (Processing System) – ARM Cortex A9 Dual Core
• USB 2.0 OTG
• USB UART Debug interface
• Gigabit Ethernet
• SD memory card holder for programming files
FPGA Modules
• Dual Quad SPI Flash

• DDR3 Memory
Figure 5-10. Zynq FPGA Module Bottom Side
FPGA Modules
Figure 5-11. Zynq FPGA Module Top Side
Table 5-10. Zynq FM Top Side Connectors and Switches

1 XSD1 SD-Card Holder User Data for Zynq FPGA
2 XETA1, XETA2 Extension Board Connectors for stackable
Connectors Extension Boards
3 S9, S10 Reset Buttons USB-Reset and System Reset
Buttons
4 XUSB1 USB 2.0 OTG Mini USB connector for USB
2.0 interface to PS
5 XUSB5 USB UART UART interface for
Programming Logic
6 XUSB2 USB UART UART interface for Processing
System
7 X15 Gigabit Ethernet GigE interface for Processing
System
8 XJTAG2 ARM JTAG JTAG Connector for Debug
Purposes of Processing System
FPGA Modules
Table 5-10. Zynq FM Top Side Connectors and Switches (cont.)

9 XMBA1, XMBA2 Mainboard Connectors to proFPGA
Connectors motherboard

This topic discusses extension board connector bank assignment in Zynq7000 FPGA modules.
Note
design data.
Note
plugged onto.
Note
FM-XC7Z100-R1 (Zynq7000 Z100)

FPGA Modules
Figure 5-12. Mapping of FM-XC7Z100-R1 I/O Banks to Connectors
are “HP” 7-series High-Performance banks (PV_IOmax=1.8V).
Table 5-11. FM-XC7Z100-R1 – Board Connectors
XETA1HR 9, 10, 11 112 109, 110 8x RX, 8x
TX
XETA2 33, 34, 35 148 111, 112 8x RX, 8x
TX
XMBA1 clk/sync,
srcclk/
srcsync
XMBA2 MMI-64
FM-XC7Z045-R1 (Zynq7000 Z045)

FPGA Modules
Other Connectors
Figure 5-13. Mapping of FM-XC7T045-R1 I/O Banks to Connectors
are 7-series “HP” High-Performance banks (PV_IOmax=1.8V).
Table 5-12. FM-XC7Z045-R1 – Board Connectors
XETA1HR 9, 10, 11 112 109, 110 8x RX, 8x
TX
XETA2 33, 34, 35 148 111, 112 8x RX, 8x
TX
XMBA1 clk/sync,
srcclk/
srcsync
XMBA2 MMI-64
Other Connectors
This topic discusses other connectors in Zynq7000 FPGA modules.
Table 5-13. Zynq FPGA Modules – Other connectors

XUSB1 Mini USB Port USB2.0 OTG interface to PS ARM Core
XUSB2 Debug Port PS USB UART Debug Interface to PS ARM
XUSB5 Debug Port PL USB UART Debug Interface to PL FPGA
X15 RJ45 connector Gigabit Ethernet connector for PS ARM
FPGA Modules
Status LEDs
Table 5-13. Zynq FPGA Modules – Other connectors (cont.)

XBAT1 Backup battery backup battery for encryption key (Varta
55996101501 1.2V)
The XUSB2 and XUSB5 connectors can be used for debug purposes of FPGA and ARM Core
via a Terminal application.
Status LEDs
This topic discusses status LEDs in Zynq7000 FPGA modules.
Table 5-14. Zynq FPGA Modules – Status LEDs.

Power Supply
D15: USB red USB Power good
FPGA Status
Reset LED
D24: Reset red System Reset Status
Ethernet LEDs
D16: PHY LED0 green GigE PHY Status LED 0
User LEDs
D5: green green driven by User FPGA
D6: red red driven by User FPGA
D7: yellow yellow driven by User FPGA
D8: blue blue driven by User FPGA
FPGA Modules
I/O Power Supply
I/O Power Supply

This topic discusses I/O power supply in Zynq7000 FPGA modules.
In the image below, each of the 2 board connectors has its individual power supply.
Figure 5-14. FPGA Modules – I/O Power Supply
JTAG
This topic discusses JTAG in Zynq7000 FPGA modules.
The Zynq7000 JTAG port links into the A1 JTAG chain, making it the first device in the list. If
no JTAG devices are present (i.e. JTAG_PRESENT is 0 or floating), the JTAG chain will short-
FPGA Modules
Reset Buttons
Figure 5-15. Zynq FPGA Modules - JTAG Chain
In addition the ARM core can be programmed and debugged via a JTAG ICE interface
connector which is located on the FM (X23).
Figure 5-16. ARM JTAG Connector
Reset Buttons
This section discusses reset buttons in Zynq7000 FPGA modules.
FPGA Modules
SD Memory Card
The following user resets are available on the Zynq FM:

Table 5-15. Zynq FPGA Modules – Resets
Designator Signal Name Description
S6 PS_nPOR ARM POR
S7 PS_nSRST ARM System Reset
S9 USB_MAN_nReset USB 2.0 OTG Reset
SD Memory Card
This section discusses SD memory card in Zynq7000 FPGA modules.
With the SD-Card Holder X8 and a compatible SD memory card the Zynq can be programmed
with files stored on the SD without any programming cables connected. With the Zynq FM
there will be an 8GB memory card provided.
Gigabit Ethernet
This section discusses gigabit ethernet in Zynq7000 FPGA modules.
The ARM PS supports a Gigabit Ethernet interface which is provided on the FM-XC7Zxxx-R1
boards via connector X15. It can be configured via GPIO expanders and the status of the
Ethernet link can be seen by three status LEDs (see Table 5-14).
The following PHY is used on the Zynq FM:

Table 5-16. GigE PHY component
Manufacturer Description Order Code
Marvell GigE transceiver 88E1116R
FPGA Modules
USB OTG
Figure 5-17. Schematic of GigE PHY on Zynq FM
USB OTG
This section discusses USB OTG in Zynq7000 FPGA modules.
The Zynq FPGA Module has an USB 2.0 OTG interface which is provided by the Processing
System and which can be used in Host or Device mode to connect peripherals.
The following USB 2.0 Transceiver is assembled on the Zynq FM:

Table 5-17. USB 2.0 Transceiver Component
Microchip ULPI Transceiver USB3320C-EZK
FPGA Modules
Local clock sources
Figure 5-18. Schematic of USB 2.0 ULPI Transceiver
Local clock sources

This section discusses local clock sources in Zynq7000 FPGA modules.
Two local clock generators are available on the Zynq FPGA Modules. A 33.333 MHz clock is
generated for the ARM Core as system clock and 50 MHz are provided to the FPGA PL.
Table 5-18. Zynq Clock Generators
Manufacturer Frequency Order Code
Abracon 50MHz CMOS ASFLMB-50.000MHZ-EC-
T
SiTime 33.33333MHz SIT8103AC-23-18E-
33.33333
FPGA Modules
DDR3 memory
Figure 5-19. Local Clock Sources on the Zynq FM
Table 5-19. Pin Locations Local Clock Generators

Clock signal Frequency Pin location at Zynq
Pin location at Zynq 50 MHz AA25
PS_CLK 33.33333 MHz A22
DDR3 memory
This section discusses DDR3 memory in Zynq7000 FPGA modules.
The Processing System of the Zynq FPGA Module can draw on 1GB DDR3 dynamic memory.
Through an AXI interface this memory can be also available for the PL. The memory consists
of four memory modules which provide a 32 Bit wide data interface to the ARM processor.
FPGA Modules
Dual Quad SPI Memory
The signals between PS and memory are shown below:
Figure 5-20. DDR3 PS Interface
Table 5-20. Zynq DDR3 Memory Component

Nanya 2Gbit 667MHz DDR3 NT5CB256M8FN-DI
Memory 78BGA
Dual Quad SPI Memory

This section discusses dual quad SPI memory in Zynq7000 FPGA modules.
The flash memory on the Zynq FMs can be used to store data which persists when the board is
powered off. Using this storage option a programming of the Zynq device with programming
cables after powering up can be avoided.
Table 5-21. Dual Quad SPI Memory
Memory Interface Size
Serial NOR Flash Quad-SPI 256 Mbit
FPGA Modules
Order Codes
The following memory is used:

Table 5-22. Zynq SPI Memory Component
Spansion Serial NOR Flash 128Mbit S25FL128SAGMFIR01
133MHz
Order Codes
This section discusses order codes of Zynq7000 FPGA modules.
These FPGA modules are no longer available.
Packages
This section discusses packages of Zynq7000 FPGA modules.
FPGA Module Part Number Package Available Speed

Grades (*)
FM-XC7Z100-R1 XC7Z100 FFG900 -1, -2
FM-XC7Z045-R1 XC7Z045 FFG900 -1, -2, -3
This section discusses firmware requirements for Zynq7000 FPGA modules.

FM-XC7Z100-R1 2015A
FM-XC7Z045-R1 2015A

This section discusses service banks pin constraints in Zynq7000 FPGA modules.
FPGA Modules
Related Work
Table 5-23. FM-XC7Zxxx-R1 FPGA Pin Constraints

Signal IOSTANDARD
clk_n[*] IOSTANDARD = LVDS_25
clk_p[*]
sync_n[*]
sync_p[*]
src_clk_n[*]
src_clk_p[*]
src_sync_n[*]
src_sync_p[*]
dmbi_f2h[*]
led_*
uart_*
Related Work
This section discusses related work of Zynq7000 FPGA modules.

plugged onto.
FPGA Modules
Virtex Ultrascale FPGA Module
Virtex Ultrascale FPGA Module

This topic discusses Virtex Ultrascale FPGA module.

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
I/O Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
This topic discusses functional description of Virtex Ultrascale FPGA module.
The proFPGA Virtex Ultrascale FPGA module is intended for the user designs. Several FPGA
types and speed grades are available. The proFPGA FPGA module provides the following
functions:
• Extension board connectors (specific for every FPGA type)

• Debug connectors
• Status LEDs
• I/O power supply
• JTAG connection

This topic discusses extension board connector bank assignment in Virtex Ultrascale FPGA
module.
Note
design data.
FPGA Modules
Note
plugged onto.
Note
FM-XCVU440-R1/R2 (Virtex-Ultrascale 440)

Figure 5-21. Mapping of FM-XCVU440 I/O Banks to Connectors
FPGA Modules
Table 5-24. FM-XCVU440 – Board Connectors

XETA1 41, 42, 43 153 219, 220 8xTX, 8xRX
XETA2 61, 62, 63 153 221, 222 8xTX, 8xRX
XETB1 46, 47, 48 153 224, 225 8xTX, 8xRX
XETB2 70, 71, 72 153 226, 227 8xTX, 8xRX
XMBA1 66, 67, 68 153 clk/sync,
srcclk/
srcsync
XMBA2 39, 40, 60 153 MMI-64,
FPGA
config.
XMBB1 49, 50, 51 153 229, 230 8xTX, 8xRX
XMBB2 52, 53, 73 153 231, 232 8xTX, 8xRX
XETA1V1 44 51
XETA2V1 84, 94 52
FPGA Modules
FM-XCVU440-HP-R1 (Virtex-Ultrascale 440)

Figure 5-22. Mapping of FM-XCVU440-HP I/O Banks to Connectors
Table 5-25. FM-XCVU440-HP – Board Connectors

XETA1 41, 42, 43 153 219, 220 8xTX, 8xRX
XETA2 61, 62, 63 153 221, 222 8xTX, 8xRX
XETB1 46, 47, 48 153 224, 225 8xTX, 8xRX
XETB2 70, 71, 72 153 226, 227 8xTX, 8xRX
XMBA1 66, 67, 68 153 clk/sync,
srcclk/
srcsync
XMBA2 39, 40, 60 153 MMI-64,
FPGA
config.
XMBB1 49, 50, 51 153 229, 230 8xTX, 8xRX
FPGA Modules
Table 5-25. FM-XCVU440-HP – Board Connectors (cont.)

XMBB2 52, 53, 73 153 231, 232 8xTX, 8xRX
XETA1V1 44 51
XETA2V1 84, 94 52
FM-XCVU190-R1 (Virtex-Ultrascale 190)

Table 5-26. FM-XCVU440-HP – Board Connectors

XETA1 50, 51, 52 153 131, 132, 133 12xTX,
12xRX
XETA2 44, 45, 46 153 126, 127, 128 12xTX,
12xRX
XETB1 70, 71, 72 153 231, 232, 233 12xTX,
12xRX
FPGA Modules
Table 5-26. FM-XCVU440-HP – Board Connectors (cont.)

XETB2 67, 68 76 226, 227, 228 12xTX,
12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
XMBB12 84 25 229, 230 8xTX, 8xRX
XMBB22 94 25 224, 225 8xTX, 8xRX
1. XMBA[12] does not provide an I/O Voltage, the PV_IO_RUN is driven low by the FPGA Module
2. XMBB[12] supports only an I/O voltage of 1.8V

FPGA Modules

Connector I/O Banks Pins MGT Channels Service
Banks
XETA1 50, 51, 52 153 131, 132, 12xTX,
133 12xRX
XETA2 44, 45, 46 153 126, 127, 12xTX,
128 12xRX
XETB1 70, 71, 72 153 231, 232, 12xTX,
233 12xRX
XETB2 67, 68 76 226, 227, 12xTX,
228 12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
XMBB12 84 25 229, 230 8xTX,
8xRX
XMBB22 94 25 224, 225 8xTX,
8xRX

Figure 5-25. FM-XCVU125 – Board connectors
FPGA Modules
Table 5-28. FM-XCVU160 – Board connectors

Banks
XETA1 50, 51, 52 153 131, 132, 12xTX,
133 12xRX
XETA2 44, 45, 46 153 126, 127, 12xTX,
128 12xRX
XETB1 70, 71, 72 153 231, 232, 12xTX,
233 12xRX
XETB2 67, 68 76 226, 227, 12xTX,
228 12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
XMBB12 84 25 229, 230 8xTX,
8xRX
XMBB22 94 25 224, 225 8xTX,
8xRX

FPGA Modules

XETA1 49, 50, 51 153 130, 131 8xTX, 8xRX
XETA2 44, 45, 46 153 125, 126, 127 12xTX,
12xRX
XETB1 69, 70, 71 153 231 4xTX, 4xRX
XETB2 67, 68 76 226, 227, 228 12xTX,
12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
XMBB12 84 25 229, 230 8xTX, 8xRX
XMBB22 94 25 224, 225 8xTX, 8xRX


XETA1 49, 50, 51 153 130, 131 8xTX, 8xRX
FPGA Modules
Other Connectors
Table 5-30. FM-XCVU095 – Board Connectors (cont.)

XETA2 44, 45, 46 153 125, 126, 127 12xTX,
12xRX
XETB1 69, 70, 71 153 231 4xTX, 4xRX
XETB2 67, 68 76 226, 227, 228 12xTX,
12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
XMBB12 84 25 229, 230 8xTX, 8xRX
XMBB22 94 25 224, 225 8xTX, 8xRX
Other Connectors
This topic discusses other connectors in Virtex Ultrascale FPGA module.
Table 5-31. Other Connectors on UltraScale Modules

XDBG1 UART/custom user debug port (compatible with FTDI TTL-
232R-3V3 cable)
XBAT1 Backup battery backup battery for encryption key (Renata
SR621SW/1V55)
Note
FPGA Modules
Status LEDs
Note
UART_RTS_B).
Figure 5-28. FPGA Modules – XDBG1 connector. All Pins Run at 3.3V.

Table 5-32. Pin assignment of XDGB1 Connector at FM-XCVU440.
Signal FPGA Host
Status LEDs
This topic discusses status LEDs in Virtex Ultrascale FPGA module.

Power Supply
D3: BA2 green XMBA2 IO power good1
D4: BA1 green XMBA1 IO power good1
FPGA Modules
Status LEDs
Table 5-33. Zynq FPGA Modules – Status LEDs. (cont.)

FPGA Status
User LEDs
D13/D17: green green driven together by User
FPGA, USR1
D14/D18: red red driven together by User
FPGA, USR1
D15/D19: yellow yellow driven together by User
FPGA, USR1
D16/D20: blue blue driven together by User
FPGA, USR1
FPGA, USR2
FPGA, USR2
FPGA, USR2
FPGA, USR2
1. not available at FM-XCVU190/160/125/095/080
Four groups of four LEDs with different colors (green, red, yellow, blue) are available on each
FPGA module. Two groups are placed in the upper left (TA1) and two groups in the lower left
corner (TB2) of the FPGA module. The LED groups are labeled with USR1 and USR1. The
LEDs with the same color and the same label are connected to each other. This means only eight
outputs are available at the FPGA: LED_green1, LED_green2, LED_red1, LED_red2,
LED_yellow1, LED_yellow2, LED_blue1 and LED_blue2. E.g. when output LED_green1 is
driven high by the FPGA, both green LEDs will glow.
FPGA Modules
I/O Power Supply
I/O Power Supply

This topic discusses I/O power supply in Virtex Ultrascale FPGA module.
In the image below, each of the board connectors has its individual power supply.
Figure 5-30. Ultrascale FPGA Modules – I/O Power Supply
JTAG
This topic discusses JTAG in Virtex Ultrascale FPGA module.
The Virtex-Ultrascale JTAG port links into the A1 JTAG chain, making it the first device in the
list. If no JTAG devices are present (i.e. JTAG_PRESENT is 0 or floating), the JTAG chain will
short-circuit back to XMBA1. On all other board connectors, JTAG signals of top and bottom
side are directly connected (Figure 5-31).
FPGA Modules
Order Codes
Figure 5-31. FM-XCVU440 – JTAG Chain
Figure 5-32. FPGA Modules (except FM-XCVU440) – JTAG Chain
Order Codes
This topic discusses order codes for Virtex Ultrascale FPGA module.

FM-XCVU440-R2 1 286445
FM-XCVU440-R2 2 286446
FM-XCVU440-R2 Without FPGA 286415
Packages
This topic discusses packages of Virtex Ultrascale FPGA module.
FPGA Module Device Name Package Available Speed

Grades (*)
FM-XCVU440-R1/ XCVU440 A2892 -1, -2, -3
R2
FM-XCVU190-R1 XCVU190 B2104 -1, -2, -3
FM-XCVU160-R1 XCVU160 B2104 -1, -2, -3
FM-XCVU125-R1 XCVU125 B2104 -1, -2, -3
FPGA Modules
Firmware requirements

Grades (*)
FM-XCVU095-R1 XCVU095 B2104 -1, -2, -3
FM-XCVU080-R1 XCVU080 B2104 -1, -2, -3
This topic discusses firmware requirements for Virtex Ultrascale FPGA module.

FM-XCVU440-R1/R2 2015C
FM-XCVU190-R1 2016B
FM-XCVU160-R1 2016B
FM-XCVU125-R1 2016B
FM-XCVU095-R1 2016B
FM-XCVU080-R1 2016B

This topic discusses service banks pin constrains in Virtex Ultrascale FPGA module.
Table 5-34. FM-XCVUxxx FPGA Pin Constraints

Signal IOSTANDARD
clk_p[*]
sync_n[*]
sync_p[*]
src_clk_n[*]
src_clk_p[*]
src_sync_n[*]
src_sync_p[*]
dmbi_f2h[*]
led_*
uart_*
FPGA Modules
Related Work
Related Work
This section discusses related work of Virtex Ultrascale FPGA module.

plugged onto.
Demo Designs
Table 5-35. Virtex-Ultrascale FPGA Modules Demo Designs
mmi64_basic Siemens MMI64 demo for FM-XCVUXXX-R1/R2
mmi64_axim Siemens MMI64 AXI Master demo for FM-XCVUXXX-
R1/R2
mmi64_fm_pcie Siemens MMI64 PCIe Extension Board demo for FM-
XCVU440-R2
mmi64_reg Siemens MMI64 Register Interface demo for FM-
XCVUXXX-R1/R2
mmi64_upstream Siemens MMI64 Upstream demo for FM-XCVUXXX-R1/
R2
pd_muxdemux2 Siemens pd_muxdemux2 demo for FM-XCVU440-R2
reset Siemens Reset demo for FM-XCVUXXX-R1/R2
FPGA Modules
Kintex Ultrascale FPGA Module
Kintex Ultrascale FPGA Module

This topic discusses Kintex Ultrascale FPGA module.

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
I/O Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
This topic discusses functional description of Kintex Ultrascale FPGA module.
The proFPGA Kintex Ultrascale FPGA module is intended for the user designs. At the moment
one FPGA type is available in several speed grades. The proFPGA FPGA module provides the

• Status LEDs
• JTAG connection

This topic discusses extension board connector bank assignment of Kintex Ultrascale FPGA
module.
Note
design data.
FPGA Modules
Note
plugged onto.
Note
FM-XCKU115-R1 (Kintex-Ultrascale 115)

Figure 5-33. Mapping of FM-XCKU115 I/O Banks to Connectors
Table 5-36. FM-XCKU115 – Board Connectors

XETA1 51, 52, 53 153 132, 133 8xTX, 8xRX
XETA2 44, 45, 46 153 127, 128 8xTX, 8xRX
XETB1 71, 72, 73 153 231, 232, 233 12xTX,
12xRX
XETB2 67, 68 76 226, 227, 228 12xTX,
12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
FPGA Modules
Other Connectors
Table 5-36. FM-XCKU115 – Board Connectors (cont.)

XMBA21 - MMI-64,
FPGA
config.
XMBB12 84 25 229, 230 8xTX, 8xRX
XMBB22 94 25 224, 225 8xTX, 8xRX
Other Connectors
This topic discusses other connectors in Kintex Ultrascale FPGA module.
Table 5-37. Untrascale FPGA Modules Other Connectors

XDBG1 UART/custom user debug port (compatible with FTDI TTL-232R-
3V3 cable)
XBAT1 Backup battery backup battery for encryption key (Renata
SR621SW/1V55)
Note
Note
UART_RTS_B).
FPGA Modules
Status LEDs
Figure 5-34. FPGA Modules – XDBG1 Connector. All Pins Run at 3.3V.

Table 5-38. Pin Assignment of XDGB1 Connector at Kintex Ultrascale FPGA
Modules.
Signal FPGA Host
Status LEDs
This topic discusses status LEDs in Kintex Ultrascale FPGA module.
Table 5-39. Status LEDs at Kintex Ultrascale FPGA Module

Power Supply
FPGA Status
FPGA Modules
I/O Power Supply
Table 5-39. Status LEDs at Kintex Ultrascale FPGA Module (cont.)

User LEDs
FPGA, USR1
FPGA, USR1
FPGA, USR1
FPGA, USR1
FPGA, USR2
FPGA, USR2
FPGA, USR2
FPGA, USR2
FPGA module. Two groups are placed in the upper left (TA1) and two groups in the lower left
corner (TB2) of the FPGA module. The LED groups are labeled with USR1 and USR2. The
LEDs with the same color and the same label are connected to each other. This means only eight
outputs are available at the FPGA: LED_green1, LED_green2, LED_red1, LED_red2,
LED_yellow1, LED_yellow2, LED_blue1 and LED_blue2. E.g. when output LED_green1 is
driven high by the FPGA, both green LEDs will glow.
I/O standard of the user LEDs: LED_yellow2 LVCMOS25, all other LEDs LVCMOS18
I/O Power Supply

This topic discusses status I/O power supply in Kintex Ultrascale FPGA module.
FPGA Modules
JTAG
JTAG
This topic discusses status JTAG in Kintex Ultrascale FPGA module.
The Kintex-Ultrascale JTAG port links into the A1 JTAG chain, making it the first device in the
side are directly connected (Figure 5-37).
Figure 5-37. FPGA Modules – JTAG Chain
FPGA Modules
Order Codes
Order Codes
This topic discusses status order codes of Kintex Ultrascale FPGA module.

FM-XCKU115-R1 1 286430
FM-XCKU115-R1 2 286431
FM-XCKU115-R1 3 286432
Packages
This topic discusses packages of Kintex Ultrascale FPGA module.
Table 5-40. FM-XCKU115-R1 Available FPGA Packages

Grades (*)
FM-XCKU115-R1 KU115 B2104 -1, -2, -3
This topic discusses firmware requirements of Kintex Ultrascale FPGA module.
Table 5-41. FM-XCKU115-R1 FPGA Firmware Requirement

FPGA Module Min. required proFPGA firmware
FM-XCKU115-R1 2016B

This topic discusses service banks pin constraints in Kintex Ultrascale FPGA module.
FPGA Modules
Table 5-42. FM-XCKU115-R1 FPGA Pin Constraints

Signal IOSTANDARD
clk_n[0] IOSTANDARD = LVDS_25
clk_p[0]
clk_n[1]
clk_p[1]
clk_n[4]
clk_p[4]
clk_n[5]
clk_p[5]
sync_n[0]
sync_p[0]
sync_n[1]
sync_p[1]
sync_n[4]
sync_p[4]
sync_n[5]
sync_p[5]
src_clk_n[0]
src_clk_p[0]
src_clk_n[1]
src_clk_p[1]
src_sync_n[0]
src_sync_p[0]
src_sync_n[1]
src_sync_p[1]
FPGA Modules
Table 5-42. FM-XCKU115-R1 FPGA Pin Constraints (cont.)

Signal IOSTANDARD
clk_n[2] IOSTANDARD = LVDS
clk_p[2]
clk_n[3]
clk_p[3]
clk_n[6]
clk_p[6]
clk_n[7]
clk_p[7]
sync_n[2]
sync_p[2]
sync_n[3]
sync_p[3]
sync_n[6]
sync_p[6]
sync_n[7]
sync_p[7]
src_clk_n[2]
src_clk_p[2]
src_clk_n[3]
src_clk_p[3]
src_sync_n[2]
src_sync_p[2]
src_sync_n[3]
src_sync_p[3]
led_yellow2
uart_*
FPGA Modules
Related Work
Table 5-42. FM-XCKU115-R1 FPGA Pin Constraints (cont.)

Signal IOSTANDARD
dmbi_f2h[*] IOSTANDARD=LVCMOS18
led_yellow
led_blue
led_green
led_red
led_blue2
led_green2
led_red2
Related Work
This topic discusses related work in Kintex Ultrascale FPGA module.

plugged onto.
Demo Designs
Table 5-43. Kintex-Ultrascale FPGA Modules Demo Designs
mmi64_axim Siemens MMI64 AXI Master demo for FM-XCVUXXX-R1/
R2
XCVUXXX-R1/R2
mmi64_upstream Siemens MMI64 Upstream demo for FM-XCVUXXX-R1/R2
FPGA Modules
Virtex Ultrascale+ FPGA Module
Virtex Ultrascale+ FPGA Module

This topic discusses Virtex Ultrascale+ FPGA module.

Reference Clocks at V2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
I/O Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
This topic discusses functional description in Virtex Ultrascale+ FPGA module.
The proFPGA Virtex Ultrascale+ FPGA module is intended for the user designs. At the moment
one FPGA type is available in several speed grades. The proFPGA FPGA module provides the

• Status LEDs
• JTAG connection

This topic discusses extension board connector bank assignment in Virtex Ultrascale+ FPGA
module.
FPGA Modules
Note
design data.
Note
plugged onto.
Note
FM-XCVU5P-R1 (Virtex-Ultrascale+ 5)
Figure 5-38. Mapping of FM-XCVU5P I/O Banks to Connectors
Table 5-44. FM-XCVU5P – Board Connectors

XETA1 50,51, 52 153 131,132, 133 12xTX,
12xRX
XETA2 44, 45, 46 153 126,127, 128 12xTX,
12xRX
FPGA Modules
Table 5-44. FM-XCVU5P – Board Connectors (cont.)

XETB1 71, 72, 73 153 231, 232, 233 12xTX,
12xRX
XETB2 67, 68 76 226, 227, 228 12xTX,
12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
XMBB12 64 25 229, 230 8xTX, 8xRX
XMBB22 64 25 224, 225 8xTX, 8xRX

XETA1 50,51, 52 153 131,132, 133 12xTX,
12xRX
FPGA Modules

XETA2 44, 45, 46 153 126,127, 128 12xTX,
12xRX
XETB1 71, 72, 73 153 231, 232, 233 12xTX,
12xRX
XETB2 67, 68 76 226, 227, 228 12xTX,
12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
XMBB12 64 25 229, 230 8xTX, 8xRX
XMBB22 64 25 224, 225 8xTX, 8xRX
FPGA Modules

XETA1 50,51, 52 153 131,132, 133 12xTX,
12xRX
XETA2 44, 45, 46 153 126,127, 128 12xTX,
12xRX
XETB1 71, 72, 73 153 231, 232, 233 12xTX,
12xRX
XETB2 67, 68 76 226, 227, 228 12xTX,
12xRX
XMBA11 - clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
FPGA Modules

XMBB12 64 25 229, 230 8xTX, 8xRX
XMBB22 64 25 224, 225 8xTX, 8xRX
FM-XCVU13P-R1 (Virtex-Ultrascale+ 13P)


XETA2 69, 70, 71 153 129, 130, 131 12xTX,
12xRX
FPGA Modules

XETB2 60, 61, 62 153 125, 126, 127 12xTX,
12xRX
XETB1V2 63 10 231 4xTX, 4xRX
XETD1V2 63 10 229, 230 8xTX, 8xRX
XETF1V2 63 10 226, 227 8xTX, 8xRX
XETH1V2 63 10 224, 225 8xTX, 8xRX
XMBA1 73, 74, 75 153 clk/sync,
srcclk/
srcsync
XMBA21 - MMI-64,
FPGA
config.
XMBB1 64, 66, 67 153
XMBB22 63, 72 62
1. XMBA2 does not provide an I/O Voltage, the PV_IO_RUN is driven low by the FPGA Module
2. XMBB2 supports only an I/O voltage of 1.8V
FPGA Modules


XETA1 73, 74, 75 153 133, 134, 135 12xTX,
12xRX
XETA2 64, 66, 67 153 125, 126, 127 12xTX,
12xRX
XETB1 72 51 233, 234, 235 12xTX,
12xRX
XETB2 68, 69, 71 153 229, 230, 231 12xTX,
12xRX
XMBA11 clk/sync,
srcclk/
srcsync
XMBA21 MMI-64,
FPGA
config.
XMBB12 226, 227 8xTX, 8xRX
FPGA Modules

XMBB22 224, 225 8xTX, 8xRX


XETA0 76, 77, 78 153 235, 236, 237 12xTX,
12xRX
XETA1 69, 70, 71 153 230, 231, 232 12xTX,
12xRX
XETA2 34, 35, 36 153
XETB0 59, 60, 61 153 220, 221, 222 12xTX,
12xRX
XETB1 20, 21, 22 153 225, 226, 227 12xTX,
12xRX
FPGA Modules
Reference Clocks at V2 Connectors

XETB2 68, 69, 71 153
XMBA0 38, 74, 75 153
XMBA1 30, 72, 73 153 clk/sync,
srcclk/
srcsync
XMBA2 31, 32, 33 153 MMI-64,
FPGA
config.
XMBB0 19, 62, 63 153
XMBB1 24, 25, 66 153
XMBB2 23, 29, 37 153
XETA1V11 83, 88 48
XETA2V11 93, 98 48
1. supports up to 3.3V I/O Voltage

This topic discusses reference clocks at V2 connectors in Virtex Ultrascale+ FPGA module.
FPGA Modules
Figure 5-44. Schematic of V2 Clock Generator IC Si5332
The MGT reference clock inputs of the FPGA are driven by a Si5332 clock generator. There are
3 possible input clocks: XA/XB (internal 50MHz crystal), CLKIN_2 (driven by
MGT_REFCLK_0 from the extension board) or CLKIN_3 (driven by MGT_REFCLK_1 from
the extension board). If only one FPGA MGT bank is connected to the V2 connector CLKIN_3
is not being driven and therefore not available as reference clock. Please refer to the FPGA
subsection Extension Board Connector Bank Assignment to determine if one or two FPGA
banks are being used.
Caution
If two connectors are interconnected with a cable, no clock will be transferred in the cable
because there is no driver. In this case, an asynchronous clock must be generated on each
side of the connector using the clock generator.
FPGA Modules
The connection scheme is shown in the picture below:
Figure 5-45. Connection Scheme V2 Connectors
Each clock input at the clock generator can either be fed through a buffer without modifications
or routed through a PLL with the possibility of modifying the frequency of the clock.
Caution
The clocks are inputs for the V2 connectors. If two connectors are interconnected with a
cable, no clock will be transferred in the cable because there is no driver. In this case, an
asynchronous clock must be generated on each side of the connector using the clock generator.
Generating register map files for Si5332

The Si5332 needs to be programmed through a register map file. This file can be generated by
the ‘Clock Builder Pro Software’ from SiLabs. It can be downloaded here: http://
www.silabs.com/products/clocksoscillators/Pages/Timing-Software-Development-Tools.aspx
The generation of the Register Map File in the Clock Builder Pro Software is guided through a
wizard.
After ‘Create New Project’ > ‘Clock Generators’ > ‘Si5332-GM2/AM2’
FPGA Modules
Figure 5-46. SI5332 Part Selection in ClockBuilder Pro
The following steps have to be performed:
• ‘Wizard Overview’: Nothing has to be done here.

a. An optional Design ID can be added.
FPGA Modules
b. Choose the chip revision ‘D’:

Figure 5-47. SI5332 Device Revision Selection in ClockBuilder Pro
c. In the package selection window select ‘Si5332-GM Embedded Crystal (Grades E,

F, G or H):
Figure 5-48. SI5332 Package Selection in ClockBuilder Pro
FPGA Modules
d. ‘Multi Profile’ Selection can be left disabled.

e. Pin configuration of ‘INPUT1’ to ‘INPUT7’ has to be left to ‘None’.
f. The I2C Address Select pin has to be left at value ‘None’.
g. If one or both input frequencies (MGT_REFCLK_IN_[0,1]) are used (only
applicable for extension boards, cable connections use the embedded crystal
connected to XA/XB), their value in MHz has to be defined as reference clock inputs
‘CLKIN2’ (corresponds to MGT_REF_CLK_IN_[0]) and ‘CLKIN3’ (corresponds
to MGT_REF_CLK_IN_[1]). The dropdown menu ‘Use’ can be either set to ‘PLL’
in case a new frequency on the basis of the input clock shall be generated or ‘Buffer’
which will route the clock to the output as it is. The embedded crystal with 50 MHz
connected to XA/XB is directly connected to the PLL:
Figure 5-49. SI5332 Input Clocks Definition in ClockBuilder Pro
h. The outputs and their desired frequency values (in case of a PLL selection
previously) can be defined here.
Note
If a cable is used to connect MGTs of 2 FPGAs with each other the internal
crystal (XA/XB) needs to be used as clock source.
FPGA Modules
Figure 5-50. SI5332 Output Clocks Configuration in ClockBuilder Pro
i. The spread spectrum can be activated. Nothing has to be done here.

j. The values have to be set to ‘LVDS Fast 1.8V’!
Figure 5-51. SI5332 Output Drivers Settings in ClockBuilder Pro
FPGA Modules
k. The output skew can be changed. Noting has to be done here.

l. The output enable pins can be assigned here. Since the INPUT[1..7] are not
connected, nothing can be done here.
• After finishing the wizard click onto ‘Export’ to generate the register map file.
• In the ‘Export’ menu select the tab ‘Register File’.
• As ‘Export Type’ select ‘Comma Separated Values (CSV) File’.
Figure 5-52. SI5332 File Generation in ClockBuilder Pro
• To generate the file click onto ‘Save To File …’ button and choose the location and the
name of the file.
• It is also recommended to save the ‘ClockBuilder Pro’ project. In this case the project
can be opened again at a later point to easily change a single parameter.
FPGA Modules
Other Connectors
Other Connectors
This topic discusses other connectors in Virtex Ultrascale+ FPGA module.
Table 5-50. Ultrascale+ FPGA Modules Other Connectors

XDBG1 UART/custom user debug port (compatible
cable)
XBAT1 Backup battery backup battery for
encryption key (Renata
SR621SW/1V55)
Note
The modules FM-XCVU19P-R1 and FM-XCVU37P-R1 don’t have the UART connector
available.
Note
Note
UART_RTS_B).
FPGA Modules
Status LEDs

Table 5-51. Pin Assignment of XDGB1 Connector at Virtex Ultrascale+ FPGA
Modules.
Signal FPGA Host
Status LEDs
This topic discusses status LEDs in Virtex Ultrascale+ FPGA module.
FPGA Modules
Status LEDs
FM-XCVU5P-R1, FM-XCVU7P-R1, FM-XCVU9P-R1

Figure 5-54. FM-XCVU5P-R1, FM-XCVU7P-R1, FM-XCVU9P-R1 Status LED
FPGA Modules
Status LEDs
FM-XCVU13P-R1
Figure 5-55. FM-XCVU13P-R1 Status LED
FPGA Modules
Status LEDs
FM-XCVU37P-R1/ FM-XCVU47P-R1
Figure 5-56. FM-XCVU37P, FM-XCVU47P Status LED
FPGA Modules
I/O Power Supply
FM-XCVU19P-R1
Figure 5-57. FM-XCVU19P Status LED
I/O Power Supply

This topic discusses I/O power supply in Virtex Ultrascale+ FPGA module.
FPGA Modules
I/O Power Supply
Additional Power Connector FM-XCVU37P/FM-XCVU47P/FM-XCVU19P-R1

The maximum current per FPGA module is limited to 20A. If designs require more than 240W,
an additional power supply can be provided via the marked connector of the FPGA top side in
Figure 5-59.
Figure 5-59. Additional Power Connector on FM-XCVU37P/FM-XCVU47P

Modules
FPGA Modules
JTAG
JTAG
This topic discusses JTAG in Virtex Ultrascale+ FPGA module.
The Virtex-Ultrascale+ JTAG port links into the A1 JTAG chain, making it the first device in
the list. If no JTAG devices are present (i.e. JTAG_PRESENT is 0 or floating), the JTAG chain
will short-circuit back to XMBA1. On all other board connectors, JTAG signals of top and
bottom side are directly connected (Figure 5-60).
Figure 5-60. FPGA Modules – JTAG chain
Order Codes
This topic discusses order codes of Virtex Ultrascale+ FPGA module.

FM-XCVU9P-R1 1 286439
FM-XCVU9P-R1 2 286440
FM-XCVU9P-R1 3 286441
FM-XCVU9P-R1 Without FPGA 286417
FM-XCVU13P-R1 1 286442
FM-XCVU13P-R1 2 286443
FM-XCVU13P-R1 3 286444
FM-XCVU19P-R1 2 286448
FM-XCVU37P-R1 2 286447
Packages
This topic discusses packages of Virtex Ultrascale+ FPGA module.
FPGA Modules
Firmware requirement

Grades (*)
FM-XCVU7P-R1 VU7P B2104 -1, -2, -3
FM-XCVU9P-R1 VU9P B2104 -1, -2, -3
FM-XCVU13P-R1 VU13P A2104 -1, -2, -3
FM-XCVU19P-R1 VU19P A3824 -1, -2
FM-XCVU37P-R1 VU37P H2892 -1, -2, -3
FM-XCVU47P-R1 VU47P H2892 -1, -2, -3
This topic discusses firmware requirements of Virtex Ultrascale+ FPGA module.

FM-XCVU7P-R1 2017A
FM-XCVU13P-R1 2019C
FM-XCVU37P-R1 2020A

This topic discusses service banks pin constraints of Virtex Ultrascale+ FPGA module.
Table 5-52. Ultrascale+ FPGA Pin Constraints

Signal IOSTANDARD
clk_p[*]
sync_n[*]
sync_p[*]
src_clk_n[*]
src_clk_p[*]
src_sync_n[*]
src_sync_p[*]
FPGA Modules
Related Work
Table 5-52. Ultrascale+ FPGA Pin Constraints (cont.)

Signal IOSTANDARD
dmbi_f2h[*]
led_*
uart_*
Related Work
This topic discusses related work of Virtex Ultrascale+ FPGA module.

plugged onto.
Profpga_run in case of FM-XCVU13P FPGA

For this board the following entry is required within the system configuration file:
fpga_module_fa1:
{
type = "FM-XCVU13P-R1";
speed_grade = 1;
temp_grade = "E";
bitstream = "output/top.bit";
v_io_ta2 = "AUTO";
v_io_tb2 = "AUTO";
v_io_ba1 = "AUTO";
v_io_bb1 = "AUTO";
v_io_bb2 = "AUTO";
v_io_tb1v2 = "AUTO";
v_io_td1v2 = "AUTO";
v_io_tf1v2 = "AUTO";
v_io_th1v2 = "AUTO";
tb1v2_si5332_registermap_file = "RegisterMap.txt";
td1v2_si5332_registermap_file = "RegisterMap.txt";
tf1v2_si5332_registermap_file = "OFF";
th1v2_si5332_registermap_file = "OFF";
};
For each V2 connector a Register Map file generated from the ClockBuilder Pro Tool has to be
given in case the reference clock inputs are meant to be used. In case they are not needed, the
value “OFF” can be used as a valid value.
FPGA Modules
Related Work
Profpga_run in case of other UltraScale+ FPGA modules

fpga_module_fa1:
{
type = "FM-XCVU7P-R1";
speed_grade = 1;
bitstream = "output/top.bit";
v_io_ba1 = "AUTO";
v_io_ba2 = "AUTO";
v_io_bb1 = "AUTO";
v_io_bb2 = "AUTO";
v_io_ta1 = "AUTO";
v_io_ta2 = "AUTO";
v_io_tb1 = "AUTO";
v_io_tb2 = "AUTO";
};
Demo Designs
Table 5-53. Virtex-Ultrascale+ FPGA Modules Demo Designs
mmi64_axim Siemens MMI64 AXI Master demo for FM-
XCVUXXX-R1/R2
XCVUXXX-R1/R2
mmi64_upstream Siemens MMI64 Upstream demo for FM-
XCVUXXX-R1/R2
FPGA Modules
Zynq Ultrascale+ MPSoC FPGA Modules
Zynq Ultrascale+ MPSoC FPGA Modules

This topic discusses Zynq Ultrascale+ MPSoC FPGA module.

PS Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
I/O Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
PUDC_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
This topic discusses functional description of Zynq Ultrascale+ MPSoC FPGA module.
The proFPGA Zynq Ultrascale+ MPSoC FPGA modules combine a user FPGA with ARM
Core processors (System-On-Chip) and are intended for user designs. The main features of all
Zynq Ultrascale+ FPGA modules are:
• PL (Programmable Logic)
• PS (Processing System) – ARM Cortex-A53 Based Application Processing Unit (APU)
and Dual-core ARM Cortex-R5 Based Real-Time Processing Unit (RPU)
• 3 (2 in case of the XCZU11) x153 I/Os to top and bottom side connectors (HP)
• I/O voltage up to 1.8V on HP bank
• 1x72 I/Os to 1 top connector (HD)
• I/O voltage up to 3.3V on HD bank
• 8 global clock and sync signal inputs
• 4 global clock and sync signal outputs
• 16 MGTs (16.0 Gb/s)
FPGA Modules
• XADC not supported

• DDR4 memory via SO DIMM module
• Single QSPI flash
• SDIO interface (µSD card slot)
• USB UART interface
• Additional PS interfaces can flexible be added with extension boards. Examples of such
interfaces are:
o CAN interface
o Display port interface
o Gbit Ethernet interface
o GPIO interface
o I²C interface
o PMU access
o SATA interface
o USB 3.0 interface
o PCIe interface
FPGA Modules
Figure 5-61. Zynq Ultrascale+ FPGA Module Overview
FPGA Modules
Figure 5-62. ZYNQ Ultrascale+ FPGA Module Bottom Side
Table 5-54. Zynq Ultrascale+ FM Bottom Side Interfaces

1, 2, 3, 4 XMBB2, XMBB1, Mainboard Connectors to proFPGA
XMBA2, XMBA1, Connectors motherboard
FPGA Modules
Figure 5-63. Zynq Ultrascale+ FPGA Module Top Side
Table 5-55. Zynq Ultrascale+ FM Top Side Interfaces and Components

5, 6, 7 XETB1, XETB2, Extension board Connectors for stackable
XETA2 connectors Extension Boards
8 XSODIMM1 DDR4 SO-DIMM The first version of the
board was shipped with a 4
GB SODIMM module
installed. Due to
availability, the memory
module was replaced by an
8 GB SODIMM module and
then by a 16 GB SODIMM
module. These are the
possible SODIMM
modules:
• KVR21SE15S8
• KVR24SE17S8/8
• KSM26SES8/16ME
FPGA Modules
Table 5-55. Zynq Ultrascale+ FM Top Side Interfaces and Components (cont.)
9, 12 XUSB1, XUSB2 PS (ARM) USB Both UARTs are identical.
UART Depending on the
mechanical space either the
XUSB1 or XUSB2
connector can be used.
Using both connectors at the
same time is not supported.
10 XBAT1 Encryption key SR621SW /1V55
backup battery
11 XDBG1 USB UART UART interface for PL
(FPGA)
13 S2 nSRST reset button
14 S1 nPOS reset button
15 XUSB1 SD-Card Holder Connected to PS

This topic discusses extension board connector bank assignment of Zynq Ultrascale+ MPSoC
FPGA module.
Note
design data.
Note
plugged onto.
Note
FPGA Modules
FM-XCZU19EG-R2
Figure 5-64. Mapping of FM-XCZU19EG-R2 I/O Banks to Connectors
In the table below, “HD” marks Ultrascale+ High Density-Range banks (PV_IOmax=3.3V).
“PS” marks Ultrascale+ PS banks (PV_IOmax=3.3V). All other I/O banks are “HP”
Ultrascale+ High-Performance banks (PV_IOmax=1.8V).
Table 5-56. FM-XCZU19EG-R2 – Board Connectors
XETA2 64, 65, 66 153 224, 225 8x RX, 8x
TX
XETB1 67, 68, 69 153
XETB2HD 90, 91, 93 72 226, 227 8x RX, 8x
TX
FPGA Modules
Table 5-56. FM-XCZU19EG-R2 – Board Connectors (cont.)

XMBA1 clk/sync,
srcclk/
srcsync
XMBA2 MMI-64
XMBB1PS 501, 502 52 505 4x RX, 4x
TX
XMBB2 72, 73, 74 153
FM-XCZU17EG-R2
FPGA Modules
In the table below, “HD” marks Ultrascale+ High Density-Range banks (PV_IOmax=3.3V).
“PS” marks Ultrascale+ PS banks (PV_IOmax=3.3V). All other I/O banks are “HP”
Ultrascale+ High-Performance banks (PV_IOmax=1.8V).
XETA2 64, 65, 66 153 224, 225 8x RX, 8x
TX
XETB1 67, 68, 69 153
XETB2HD 90, 91, 93 72 226, 227 8x RX, 8x
TX
XMBA1 clk/sync,
srcclk/
srcsync
XMBA2 MMI-64
XMBB1PS 501, 502 52 505 4x RX, 4x
TX
XMBB2 72, 73, 74 153
FPGA Modules
FM-XCZU11EG-R2
In the table below, “PS” marks Ultrascale+ PS banks (PV_IOmax=3.3V). All other I/O banks
are “HP” Ultrascale+ High-Performance banks (PV_IOmax=1.8V).
XETA2 64, 65, 66 153 224, 225 8x RX, 8x
TX
XETB1 67, 68, 69 153
XETB2HD 88, 89, 90 72 226, 227 8x RX, 8x
TX
XMBA1 clk/sync,
srcclk/
srcsync
XMBA2 MMI-64
XMBB1PS 501, 502 52 505 4x RX, 4x
TX
FPGA Modules
PS Specific
PS Specific
This topic discusses PS specific of Zynq Ultrascale+ MPSoC FPGA module.
PS Interface Concept
Only Bank 500 with MIO[0..25] signals are fixed connected to the on-board functions QSPI,
SDIO and UART interfaces. The bank 500 is powered with 3.3 V.
Table 5-59. Zynq Ultrascale+ Bank 500 Pin Assignment
MIO Pin Interface Signal Function
MIO0 QSPI QSPI0_CLK
MIO1 QSPI0_IO1
MIO2 QSPI0_IO2
MIO3 QSPI0_IO3
MIO4 QSPI0_IO0
MIO5 QSPI0_nCS
MIO8 PS UART UART_PS_T Connected to the PS USB UART connectors XUSB1/

X_FTDI_RX XUSB2 via a FT232RQ UART to USB converter
MIO9 UART_PS_R
X_FTDI_TX
MIO10 I2C PS_SCL DDR4 SO-DIMM I2C interface
MIO11 PS_SDA
MIO13 SD Card SDIO_DAT0
MIO14 SDIO_DAT1
MIO15 SDIO_DAT2
MIO16 SDIO_DAT3
MIO21 SDIO_CMD
MIO22 SDIO_CLK
MIO24 SDIO_CD
MIO6 TP63 Testpoint

MIO7 TP64 Testpoint
MIO12 TP65 Testpoint
FPGA Modules
PS Specific
Table 5-59. Zynq Ultrascale+ Bank 500 Pin Assignment (cont.)

MIO Pin Interface Signal Function
The PS banks 501, 502 and 505 are connected to the BB1 extension board connector. Using this
approach a various range of proFPGA extension boards can be used with the PS part of the
FPGA. The default extension board is the EB-FM-XCZUXXEG-R2/R3 (see Zynq US+
Interface Board (EB-FM-XCZUxxEG-R2/R3)for more details).
Please refer to the compatibility list of each extension board in this document for other
interfaces.
Examples of such extension boards are:
• EB-PDS-PCIe-Cable-R3
• EB-PDS-ROOT-COMPLEX-M.2-R1
• EB-PDS-SATA-R2
Note
The SDIO_CLK speed has to be set to fast. All other SDIO_* speeds have to staty at slow.
Local clock sources

A 33.333 MHz clock is generated for the ARM Core as system clock.
Table 5-60. Zynq Ultrascale+ Clock Generators
Manufacturer Frequency Connected To… Order Code
IDT 33.33333MHz PS_CLK ITD-33.33333MBD-T
MGT Lane Switching for PS MGTs

For more flexibility and compatibility to other proFPGA extension boards than the EB-FM-
XCZUxxEG-R2/R3, MGT lane switching was added to the PS MGTs of the ZYNQ Ultrascale+
FPGA
FPGA Modules
PS Specific
Figure 5-67. Zynq Ultrascale+ FPGA Modules - MGT Lane Switching for PS
MGTs
With the MGT lane switching it is possible to use for example the
• EB-PDS-PCIe-Cable-R3 and the

• EB-PDS-ROOT-COMPLEX-M.2-R1
Extension boards on PS of the ZYNQ Ultrascale+ FPGA. As mentioned in Figure 5-67 there are
2 possibilities where PS MGT can be routed:
Table 5-61. Zynq Ultrascale+ FPGA Modules - MGT Lane Switching for PS
MGTs
MGT Lane Routing Target Constraint in
Configuration File
PS_MGTR0_505 BB1_MGT_3 ps_mgt_lane_0 =
„profpga_mgt_03“;
BB1_MGT_7 ps_mgt_lane_0 =
FPGA Modules
Other Connectors
Other Connectors
This topic discusses other connectors in Zynq Ultrascale+ MPSoC FPGA module.
Table 5-62. Ultrascale+ FPGA Modules Other Connectors

cable)
XBAT1 Backup battery backup battery for
SR621SW/1V55)
Note
Note
UART_RTS_B).

Modules.
Signal FPGA Host
FPGA Modules
Status LEDs

Modules. (cont.)
Signal FPGA Host
Status LEDs
This topic discusses status LEDs in Zynq Ultrascale+ MPSoC FPGA module.

LED Marking Color Description Comment
Power Supply
TA2 green XETA2 IO power
good
TB1 green XETB1 IO power
good
TB2 green XETB2 IO power
good
BB1 green XMBB1 IO power
good
BB2 green XMBB2 IO power
good
FPGA Status
FPGA green FPGA core power
good
PROG DONE blue FPGA programming
done
TEMP red FPGA temperature
alert
PS Status LEDs
D4: PS reset active red System Reset Status
D2: red
PS_ERROR_OUT
D3: red
PS_ERROR_STAT
US
User LEDs (from tot o bottom)
FPGA Modules
I/O Power Supply
Table 5-64. Zynq FPGA Modules – Status LEDs. (cont.)

LED Marking Color Description Comment
USR 2: blue blue driven by User
FPGA
USR 2: yellow yellow driven by User
FPGA
USR 2: red red driven by User
FPGA
USR 2: green green driven by User
FPGA
USR 1: blue blue driven by User
FPGA
USR 1: yellow yellow driven by User
FPGA
USR 1: red red driven by User
FPGA
USR 1: green green driven by User
FPGA
FPGA module. Two groups are placed in the upper left (DDR4 SODIMM socket) and two
groups in the lower left corner (TB2) of the FPGA module. The LED groups are labeled with
USR1 and USR1. The LEDs with the same color and the same label are connected to each other.
This means only eight outputs are available at the FPGA: LED_green1, LED_green2,
LED_red1, LED_red2, LED_yellow1, LED_yellow2, LED_blue1 and LED_blue2. E.g. when
output LED_green1 is driven high by the FPGA, both green LEDs will glow.
I/O Power Supply

This topic discusses I/O power supply in Zynq Ultrascale+ MPSoC FPGA module.
In the image below, each of the proFPGA connectors has its individual power supply
FPGA Modules
JTAG
Figure 5-69. ZYNQ Ultrascale+ FPGA Modules – I/O Power Supply
JTAG
This topic discusses JTAG in Zynq Ultrascale+ MPSoC FPGA module.
The Zynq Ultrascale+ JTAG port links into the A1 JTAG chain, making it the first device in the
side are directly connected.
Figure 5-70. Zynq Ultrascale+ FPGA Modules - JTAG Chain
PUDC_B
This topic discusses PUDC_B in Zynq Ultrascale+ MPSoC FPGA module.
FPGA Modules
Order Codes
The Pull-Up-During-Configuration-Bar pin can be controlled via configuration file. It is an

optional parameter. If this value is not set, the PUDC_B pin is set to low on startup.
• LOW means, that weak preconfiguration I/O pull-up resistors are enabled.
• HIGH means, that weak preconfiguration I/O pull-up resistors are disabled.
Each FPGA module has to have its own pudc_b entry if needed. The syntax is as followed:
pudc_b = “LOW”; # optional entry, can be “LOW” or “HIGH”

pudc_b = “HIGH”; # optional entry, can be “LOW” or “HIGH”
Order Codes
This topic discusses order codes of Zynq Ultrascale+ MPSoC FPGA module.

FM-XCZU11EG-R2 1 286449
FM-XCZU11EG-R2 2 286450
FM-XCZU17EG-R2 1 286451
FM-XCZU17EG-R2 2 286452
FM-XCZU19EG-R2 1 286453
FM-XCZU19EG-R2 2 286454
FM-XCZU19EG-R2 3 286455
Packages
This topic discusses packages of Zynq Ultrascale+ MPSoC FPGA module.
FPGA Module Part Number Package Available Speed

Grades (*)
FM-XCZU11EG-R2 XCZU11EG FFVB1517 -1, -2, -3
FPGA Modules
This topic discusses firmware requirements of Zynq Ultrascale+ MPSoC FPGA module.

FM-XCZU19EG-R2 2018A

This topic discusses service banks pin constraints of Zynq Ultrascale+ MPSoC FPGA module.
Table 5-65. FM-XCZUxxEG-R2 FPGA Pin Constraints

Signal IOSTANDARD
clk_p[*]
sync_n[*]
sync_p[*]
src_clk_n[*]
src_clk_p[*]
src_sync_n[*]
src_sync_p[*]
dmbi_f2h[*]
led_*
uart_*
Related Work
This topic discusses related work of Zynq Ultrascale+ MPSoC FPGA module.

plugged onto.
FPGA Modules
Related Work
Profpga_run
fpga_module_ta1:
{
type = „FM-XCZU19EG-R2”;
speed_grade = 1;
temp_grade = „E”;
v_io_ta1 = „AUTO”; # for connector TA1
v_io_ta2 = „AUTO”; # for connector TA2
v_io_tb1 = „AUTO”; # for connector TB1
v_io_tb2 = “AUTO”; # for connector TB2
v_io_ba1 = “AUTO”; # for connector BA1
v_io_ba2 = “AUTO”; # for connector BA2
v_io_bb1 = “AUTO”; # for connector BB1
v_io_bb2 = “AUTO”; # for connector BB2
boot_mode = “SD-CARD”;
ps_npor = “SWITCH”;
ps_nsrst = “SWITCH”;
ps_mgt_lane_0 = “profpga_mgt_03”;
pudc_b = “LOW”; # optional entry, can be “LOW” or “HIGH”
};
FPGA Modules
Related Work
Demo Designs
Table 5-66. FM-XCZUxxEG-R2 FPGA Modules Demo Designs
Title FPGAs Author Description
EB-PDS-GBITETHERNET- ZU19EG Siemens This verification design
R1_GMII supports GMII GbitEthernet
via EMIO and EB-PDS-
GBITETHERNET-R1
extension board.
EB-PDS-GBITETHERNET- This verification design
R1_RGMII supports RGMII GbitEthernet
via EMIO and EB-PDS-
GBITETHERNET-R1
extension board.
EB-PDS-ROOT-COMPLEX- This verification design
M.2-R1_PCIe supports a PCIe interfacevia
EB-PDS-ROOT-COMPLEX-
M.2-R1 extension board.
NVME device supportis
included.
blinking_led all Siemens Blinking User LED demo
EB-FM-XCZUxx-R2 This verification design
supports the
basicfunctionality with all
interfaces with EB-FM-
XCZUxxEG-R2
extensionboard.
EB-PDS-ROOT-COMPLEX- This verification design
M.2-R1 supports an M.2 interfacevia
EB-PDS-ROOT-COMPLEX-
M.2-R1 extension board.
NVME device supportis
included.
mmi64_ahbm ???
mmi64_basic MMI64 demo
mmi64_reg MMI64 register interface
demo
profpga_acm ACM demo
reset Reset demo
FPGA Modules
Stratix 10 FPGA Modules
Stratix 10 FPGA Modules

This topic discusses Stratix 10 FPGA module.

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
I/O Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
FM-1SG10M-R1 Motherboard Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
This topic discusses functional description of Stratix 10 FPGA module.
The proFPGA Stratix 10 FPGA modules are intended for the user designs. At the moment two
FPGA types are available in several speed grades. The proFPGA FPGA modules provide the

• Status LEDs
• JTAG connection
Note
Master clock signals clk[6] and clk[7] generated by the proFPGA motherboard are
connected on Stratix proFPGA FPGA modules to non-clock-capable IO pins. It is not
possible to connect them directly to a PLL.
To workaround this limitation, use a “Clock Control Intel FPGA IP” between pin and PLL.
FPGA Modules

This topic discusses extension board connector bank assignment of Stratix 10 FPGA module.
Note
The detailed pin assignment is specified in the SDC/TCL constraints files provided with the
design data.
Note
plugged onto.
Note
FM-1SG280L-R1 (Intel Stratix 10)

Table 5-67. FM-1SG280L-R1 – Board Connectors
XETA1 2A,2B,2C 141 1C,1D 12xTX,
12xRX
XETA2 3D,3E,3F 141 1E 6xTX, 6xRX
XETB1 2L,2M,2N 141 1F 6xTX, 6xRX
XETB2 3G,3H,3I 141
XMBA1 2F,2G,2H 141 clk/sync,
srcclk/
srcsync
XMBA2 3C 23 MMI-64,
FPGA
config.
XMBB1 2I,2J,2K 141
XMBB 3J,3K,3L 141
FPGA Modules
Caution
Know Issues:
• Three signals at TA1, TA2, TB1, TB2, BA1, BB1 and BB2 are not delay matched
(IO122, IO123 and IO124). This can cause issues with Highspeed Interfaces using these
signals (e.g. Intel EMIF).
• The transceiver tile related I/O Bank 6A is not available to customers. Some Stratix 10
IPs require their sideband signals located in this bank (e.g. NPERSTL for PCIe). These
signals cannot be remapped to other banks.
FM-1SG280L-R2/ FM-1SG280H-R1/ FM-1SG280H-R2 (Intel Stratix 10)

Table 5-68. FM-1SG280L-R2/ FM-1SG280H-R1/ FM-1SG280H-R2 – Board
Connectors
XETA1 2A,2B,2C 141 1C,1D 12xTX,
12xRX
XETA2 3D,3E,3F 141 1E 6xTX, 6xRX
XETB1 2L,2M,2N 141 1F 6xTX, 6xRX
XETB2 3G,3H,3I 141
XMBA1 2F,2G,2H 141 clk/sync,
srcclk/
srcsync
XMBA2 3C,6A 27/431234 MMI-64,
FPGA
config.
XMBB1 2I,2J,2K 141
XMBB 3J,3K,3L 141
1. PHY Lite IP can not be used at this connector
2. The boot option “tile_io” determines the number of available pins at XMBA2
3. This connector supports only an I/O-Voltage of 1.8V
4. Bank 6A has limited I/O functionality, see Intel documentation for further details
Some Intel PSG Transceiver IPs (e.g. PCIe) require some sideband signals at the Transceiver
Tile related I/O bank (nPERSTL in case of PCIe) which cannot be remapped to other pins. Due
to this fact the Transceiver Tile I/O bank (bank 6A) is now available for the customer. There are
two options how the signals of this bank can be connected. Both options are controlled by the
boot option “tile_io” in the system config file by setting it either to “ONBOARD” or
“EXTERN”.
FPGA Modules
• Option 1: The bank 6A signals can be connected to the I/O bank 3C on the FPGA
Module itself (see Figure 5-71). To use this option the “tile_io” must be set to
“ONBOARD”. If an extension board is plugged onto the system (at any site) which uses
those dedicated sideband signals, the user needs to route them to the related pins at bank
3C in the FPGA design. The on board loopback requires eight pins of the bank 3C,
therefore only 27 signals are available at XMBA2 (IO000…IO010 and all CLKIOs).
• Option 2: The bank 6A is available at XMBA2 (IO019…IO026, see Figure 5-72). The
user needs an extension board connected to XMBA2 to have access to these signals. For
this purpose, the Debug Board (EB-PDS-DEBUG-R1) can be used. This feature must be
enabled by setting “tile_io” to “EXTERN”. Because there are no additional I/O pins
from bank 3C needed, the eight signals (required for option 1) are also available at
XMBA2 (IO011…IO018).
Figure 5-71. FM-1SG280L-R2 Tile I/O Onboard Loopback (option 1)
Figure 5-72. FM-1SG280L-R2 Tile I/O Connected to XMBA2 (option 2)
FPGA Modules
vref_source
The VREF is required for some I/O standards (refer to Intel Stratix 10 documentation for
detailed information). With this option it can be defined if the VREF will be
generated on the extension board (“vref_source_[tb][ab][12]” is set to "EB") or on the FPGA
module via resistance divider from the corresponding PV_IO voltage
(“vref_source_[tb][ab][12]” is set to "FM"). All I/O-banks connected to an extension board
connector will use the same setting.
oct_resistor
This option can be used to select the resistance value on the RZQ pins of the I/O banks. This
value depends on the I/O standard (refer to Intel Stratix 10 documentation for detailed
information). Each I/O-bank has its own resistor, but all I/O-banks of an extension board
connector will use the same value (“oct_resistor_[tb][ab][12]” can be set to “100R” or “240R”).
Differences between FM-1SG280L-R1 and FM-1SG280L-R2/ FM-1SG280H-R1
All known issues of the FM-1SG280L-R1 are fixed in this revision.
The Transceiver tile I/O bank is available at connector BA2 or can be connected to I/O Bank 3C
via onboard loopback (see above).
The I/O voltage of BA2 supports only 1.8V and cannot be changed.
Due to this modification the following pin assignments have been changed:
• Temperature sensor IP (I2C)

• DMBI UART
• BA2 connector and the related I/O bank 3C
Differences between FM-1SG280H-R1 and FM-1SG280H-R2
The FM-1SG280H-R2 are assembled with Stratix10 AS devices (advanced security) which
supports Intel Bitstream encryption.
FM-1SG10M-R1
On this FPGA module, a Stratix 10 GX 10M is mounted. The main difference to other FPGAs
is, that it consists of 2 dies. These dies are connected internally wit the DIB interface with 6,480
connections. The dies are named F1 and F2.
Table 5-69. FM-1SG10M-R1 – Board Connectors
Connector Die I/O Banks Pins MGT Channels Service
Banks
XETA0 F2 2A, 2B, 2C 141
FPGA Modules
Table 5-69. FM-1SG10M-R1 – Board Connectors (cont.)

Connector Die I/O Banks Pins MGT Channels Service
Banks
XETA1 F2 3D, 3E, 3F 141 1C,1D, 1E 12xTX,
12xRX
XETA1V1 F2 3C, T3, T4 51/35/191
XETA2 F1 2L, 2M, 141 1K, 1L, 12xTX,
2N 1M 12xRX
XETA2V1 F1 3C, T1, T2 51/35/
19121
XETAB0 F2 2F, 2G, 2H 141
XETB0 F2 2L, 2M, 141
2N
XETB1 F2 3J, 3K, 3L 141 1K, 1L, 12xTX,
1M 12xRX
XETB2 F1 2A, 2B, 2C 141 1C,1D, 1E 12xTX,
12xRX
XEBA0 F1 3J, 3K, 3L 141
XMBA1 F1 3G, 3H, 3I 141 clk/sync,
srcclk/
srcsync
XMBA2 F1 2I, 2J, 2K 141 MMI-64,
FPGA
config
XEBAB0 F2 2I, 2J, 2K 141
XEBB0 F2 3G, 3H, 3I 141
XMBB1 F1 3D, 3E, 3F 141
XMBB2 F1 2F, 2G, 2H 141
1. Banks T[1..4] have limited I/O functionality, see Intel documentation for further details
Some Intel PSG Transceiver IPs (e.g. PCIe) require some sideband signals at the Transceiver
Tile related I/O bank (nPERSTL in case of PCIe) which cannot be remapped to other pins. Due
to this fact the Transceiver Tile I/O banks T[1..4] cab be remapped. There are two options how
the signals of these banks can be connected. Both options are controlled by the boot option
“tile[1..4]_io” in the system configuration file by setting it either to “ONBOARD” or
“EXTERN”.
• Option 1: The signals of banks T[1..4] can be connected to the I/O bank 3C of each
concerning FPGA die on the FPGA Module itself (see Figure 5-73). To use this option
FPGA Modules
the “tile[1..4]_io” must be set to “ONBOARD”. If an extension board is plugged onto

the system (at any site) which uses those dedicated sideband signals, the user needs to
route them to the related pins at bank 3C in the FPGA design. The on board loopback
requires eight pins of the bank 3C, therefore only 35 respectively 19 signals are
available at XETA[1,2]V1 (IO000..IO009, IO026 and all 8 CLKIOs).
• Option 2: The banks T[1..4] are available at XETA[1,2]V1 (IO027..IO034, repectivley
IO035..IO042, see Figure 5-74). The user needs an extension board connected to
XETA[1,2]V1 to have access to these signals. For this purpose, the Debug Board (EB-
PDS-DEBUG-R1) can be used. This feature must be enabled by setting “tile[1..4]_io” to
“EXTERN”. Because there are no additional I/O pins from bank 3C needed, the 8 / 16
signals (required for option 1) are also available at XETA[1,2]V1 (IO010..IO017,
respectively IO018..IO025).
In the profpga_brdgen output, the signals connected to the FPGA banks 3C of both banks are
marked with the suffix “default”. The signals connected to the FPGA banks T[1..4] are marked
with the suffix “switched”.
Figure 5-73. FM-1SG10M-R1 Tile I/O Onboard Loopback (option 1)
Figure 5-74. FM-1SG10M-R1 Tile I/O Connected to XETA[1,2]V1 (option 2)
vref_source
The VREF is required for some I/O standards (refer to Intel Stratix 10 documentation for
detailed information). With this option it can be defined if the VREF will be generated on the
FPGA Modules
Other Connectors
extension board (“vref_source_[t,b][a,ab,b][012][,v1]” is set to "EB") or on the FPGA module

via resistance divider from the corresponding PV_IO voltage
(“vref_source_[t,b][a,ab,b][012][,v1]” is set to "FM"). All I/O-banks connected to an extension
board connector will use the same setting.
oct_resistor
value depends on the I/O standard (refer to Intel Stratix 10 documentation for detailed
connector will use the same value (“oct_resistor_[t,b][a,ab,b][012][,v1]” can be set to “100R”
or “240R”).
Other Connectors
This topic discusses other connectors of Stratix 10 FPGA module.
Table 5-70. Stratix 10 FPGA Modules Other Connectors

cable)
XDBG1XBAT1 Backup battery backup battery for
SR621SW/1V55)
Note
Note
UART_RTS_B).
FPGA Modules
Status LEDs

Table 5-71. Pin Assignment of XDGB1 Connector at Intel Stratix 10 FPGA
Modules
Signal FPGA Host
Additional information for FM-1SG10M-R1 FPGA module

One UART connector is available on the board. It is connected with an analog switch to both
dies. Only one die can use the interface at a time. Therefore, the attribute “uart_switch” has to
be used in the configuration file. It can be set to:
uart_switch = "F1";
or
uart_switch = "F2";
to choose either the F1 or F2 die.
Status LEDs
This topic discusses status LEDs of Stratix 10 FPGA module.
FPGA Modules
Status LEDs
FM-1SG280[H,L]-R[1,2]
Table 5-72. Status LEDs at FM-1SG280X-R[1,2]
Power Supply
D22:BA2 green XMBA2 IO power good
D23:BA1 green XMBA1 IO power good
D34: PMBUS Fault red PMBus Error indicator
Stratix 10 Status
D28: S10 Core green FPGA core power good
D29: S10 DONE blue FPGA programming and
initialization done
D11: Temp Fault red FPGA temperature alert
User LEDs
FPGA
FPGA
FPGA
FPGA
FM Controller FPGA
D36: A7 Core green FM Controller core power
good
D37: A7 Done blue FM Controller programming
done
FPGA Modules
Status LEDs
corner (TB2) of the FPGA module. The LED groups are labeled with USR. The LEDs with the
same color and the same label are connected to each other. This means four outputs are
available at the FPGA: LED_green, LED_red, LED_yellow, and LED_blue. E.g. when output
LED_green is driven high by the FPGA, both green LEDs will glow.
FM-1SG10M-R1
Figure 5-76. Status LEDs at FM-1SG10M-R1 FPGA Module
Two groups of four LEDs with different colors (green, red, yellow, blue) are available for each
FPGA die.
LEDs of die F1 are located in the middle left and on the right lower corner.
LEDs of die F2 are located in the left upper corner and on the right upper corner.
FPGA Modules
I/O Power Supply
The LED groups are labeled with USR LED. The LEDs with the same color and the same
FPGA die are connected to each other. This means four outputs are available at the each FPGA
die:
• F[1,2]_LED_GREEN
• F[1,2]_LED_RED
• F[1,2]_LED_YELLOW
• F[1,2]_LED_BLUE
• E.g. when output F1_LED_GREEN is driven high by the FPGA, both green LEDs will
glow.
I/O Power Supply

This topic discusses I/O power supply of Stratix 10 FPGA module.
Figure 5-77. Stratix 10 FPGA Modules – I/O Power Supply
JTAG
This topic discusses JTAG of Stratix 10 FPGA module.
FPGA Modules
Temperature Monitoring
The Stratix 10 JTAG port links into the A1 JTAG chain, making it the first device in the list. If
no JTAG devices are present (i.e. JTAG_PRESENT is 0 or floating), the JTAG chain will short-
Temperature Monitoring
This topic discusses temperature monitoring of Stratix 10 FPGA module.
FM-1SG280[H,L]-R[1,2]
The user needs to implement the Stratix 10 temperature monitor IP provide with the proFPGA
HDL in every user design. The monitoring and fault detection procedure is running in the FM
System Controller. One second after the Stratix 10 has been configured, the monitoring starts. If
the IP is not implemented or an over temperature occurs, the Power supply of the Stratix 10 will
be turned off immediately and the temperature error LED will be activated.
Table 5-73. Stratix10 Temperature Monitor IP Status
FM Temperature Monitor Temperature Fault LED proFPGA Board Status
Status (on FM) (proFPGA Builder and
Command line)
User FPGA is not configured OFF FPGA xxxx temperature :
NO IP
FPGA temperature error :
OK
Temperature Monitoring is OFF FPGA xxxx temperature :
active Shows temperature
OK
No Temperature Monitoring Blinkling FPGA xxxx temperature :
IP was found NO IP
FAIL
FPGA Modules
Order Codes
Table 5-73. Stratix10 Temperature Monitor IP Status (cont.)

FM Temperature Monitor Temperature Fault LED proFPGA Board Status
Status (on FM) (proFPGA Builder and
Command line)
Overtemperature ON FPGA xxxx temperature :
Shows last temperature
FAIL
For information on how to implement the IP please refer to the Demo designs.
FM-1SG10M-R1
Remote diode temperature sensors are used to measure the temperatures of the FPGA dies as
well as the temperatures of the transceiver tiles.
Order Codes
This topic discusses order codes of Stratix 10 FPGA module.

FM-1SG280H-R2 2 286456
FM-1SG280H-R2 Without FPGA 286416
FM-1SG10M-R1 2 286457
FM-1SG10M-R1 Without FPGA 286419
Packages
This topic discusses packages of Stratix 10 FPGA module.

Grades 1
FM-1SG280L-S1-R1 GX 2800, L-Tile F55 -1, -2, -3
FM-1SG280H-R2 GX 2800, H-Tile F55 -1, -2, -3
FM-1SG10M-R1 10 GX 10M NF74 -2
1. Speed grades also depend on temperature rating
FPGA Modules
This topic discusses firmware requirement of Stratix 10 FPGA module.

FM-1SG280L-S1-R1 2017B
FM-1SG280H-R2 2019B
FM-1SG10M-R1 2019C

This topic discusses service banks pin constraints of Stratix 10 FPGA module.
Table 5-74. Stratix 10 FPGA Modules: FPGA Pin Constraints

Signal IOSTANDARD
*clk_n[*] IOSTANDARD = LVDS
*clk_p[*]
*sync_n[*]
*sync_p[*]
*src_clk_n[*]
*src_clk_p[*]
*src_sync_n[*]
*src_sync_p[*]
*dmbi_h2f[*] IOSTANDARD = LVCMOS18
*dmbi_f2h[*]
*led_*
*uart_*
Related Work
This topic discusses related work of Stratix 10 FPGA module.
Synthesis constraints
The Synthesis of the User design requires a specific set of constrains in order to setup the
configuration and the SmartVID feature of the FPGA. If the constraints are not used the FPGA
will not be configured or initialized. Please refer to the Demo designs for more information.
FPGA Modules
FM-1SG10M-R1 Motherboard Compatibility

plugged onto.
Demo Designs
Table 5-75. Stratix 10 FPGA Modules Demo Designs
blinking_led Siemens Blinking User LED demo
mmi64_reg Siemens MMI64 Register Interface
demo for FM-1SG280L-S1-
R1 and FM-1SG10M-R1
mmi64_upstream Siemens MMI64 Upstream demo for
FM-1SG280L-S1-R1 and
FM-1SG10M-R1
FM-1SG10M-R1 Motherboard Compatibility

This topic discusses FM-1SG10M-R1 motherboard compatibility in Stratix 10 FPGA module.
According to the size of the FM-1SG10M-R1 FPGA module, it is not compatible with the MB-
4M-R1 and MB-4M-R2 motherboards on sites TA3 and TC3 because it would collide. It is
compatible with the MB-4M-R1 and MB-4M-R2 motherboards on sites TA1 and TC3 and all
other proFPGA motherboards.
FPGA Modules
Arria 10 FPGA Modules
Arria 10 FPGA Modules

This topic discusses Arria 10 FPGA module.

Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
I/O Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
This topic discusses functional description of Arria 10 FPGA module.
The proFPGA Arria 10 FPGA module is intended for the user designs. At the moment one
FPGA type is available in several speed grades. The proFPGA FPGA module provides the

• Status LEDs
• JTAG connection

This topic discusses extension board connector bank assignment of Arria 10 FPGA module.
FPGA Modules
Note
The detailed pin assignment is specified in the SDC/TCL constraints files provided with the
design data.
Note
plugged onto.
Note
FM-10AX115-R1 (Intel Arria 10)

Table 5-76. FM-10AX115-R1 – Board Connectors
Banks
XETA1 2F,2G,2H 141 1C,1D 12xTX,
12xRX
XETA2 3B,3C,3D 141 4C,4D 12xTX,
12xRX
XETB1 2J,2K,2L 141 1E,1F 12xTX,
12xRX
XETB2 3E,3F,3G 141 4E,4F 12xTX,
12xRX
XMBA11 clk/sync,
srcclk/
srcsync
XMBA21 MMI-64,
FPGA
config.
XMBB1 2I 39
XMBB2 3H 35/432
1. This connector does not provide an I/O Voltage, the PV_IO_RUN is driven low by the FPGA Module
2. the boot option “tile_io” determines the number of available pins at XMBB2
FPGA Modules
Other Connectors
Caution
Know Issues
• The volatile security key storage (using backup battery) is not available, due to the high
VCCBAT current of the Arria 10 (see Intel Arria10 Device Errata ES-1057).
Other Connectors
This topic discusses other connectors of Arria 10 FPGA module.
Table 5-77. Arria 10 FPGA Modules Other Connectors

XDBG1 UART/ User debug port (compatible with FTDI TTL-232R-3V3
custom cable)
XBAT11 Backup Backup battery for encryption key (Renata SR621SW/
battery 1V55)
1. not available on FM-10AX115-R1
Note
Note
UART_RTS_B).
Figure 5-79. FPGA Modules – XDBG1 connector. All Pins Run at 3.3V.
FPGA Modules
Status LEDs

Table 5-78. Pin Assignment of XDGB1 Connector at Intel Arria 10 FPGA
Modules.
Signal FPGA Host
Status LEDs
This topic discusses status LEDs of Arria 10 FPGA module.
Table 5-79. Status LEDs at Intel Arria 10 FPGA module

Power Supply
D34: PMBUS Fault red PMBus error indicator
Arria 10 Status
D28: A10 Core green FPGA core power good
D29: A10 DONE blue FPGA programming and
initialization done
D11: Temp Fault red FPGA temperature alert
User LEDs
D12/D16: green green driven together by User FPGA
D13/D17: red red driven together by User FPGA
D14/D18: yellow yellow driven together by User FPGA
FPGA Modules
I/O Power Supply
Table 5-79. Status LEDs at Intel Arria 10 FPGA module (cont.)

D15/D119: blue blue driven together by User FPGA
FM Controller FPGA
D36: A7 Core green FM Controller core power
good
D37: A7 Done blue FM Controller programming
done
corner (TB2) of the FPGA module. The LED groups are labeled with USR. The LEDs with the
same color and the same label are connected to each other. This means four outputs are
available at the FPGA: LED_green, LED_red, LED_yellow, and LED_blue. E.g. when output
LED_green is driven high by the FPGA, both green LEDs will glow.
I/O Power Supply

This topic discusses I/O power supply of Arria 10 FPGA module.
Figure 5-80. Stratix 10 FPGA Modules – I/O Power Supply
FPGA Modules
JTAG
JTAG
This topic discusses JTAG of Arria 10 FPGA module.
The Arria 10 JTAG port links into the A1 JTAG chain, making it the first device in the list. If no
JTAG devices are present (i.e. JTAG_PRESENT is 0 or floating), the JTAG chain will short-
Order Codes
This topic discusses order codes of Arria 10 FPGA module.
This FPGA module is not available anymore.
Packages
This topic discusses packages of Arria 10 FPGA module.

Grades (*)
FM-10AX115-R1 AX 1500 NF45 -1, -2, -3
This topic discusses firmware requirements of Arria 10 FPGA module.

FM-10AX115-R1 2019A-SP1
FPGA Modules

This topic discusses service banks pin constraints of Arria 10 FPGA module.
Table 5-80. Arria 10 FPGA Pin Constraints

Signal IOSTANDARD
clk_p[*]
sync_n[*]
sync_p[*]
src_clk_n[*]
src_clk_p[*]
src_sync_n[*]
src_sync_p[*]
dmbi_f2h[*]
led_*
uart_*
Boot options
This topic discusses boot options for Arria 10 FPGA module.
tile_io
The Intel Arria 10 PCIe Hard IPs assume their nPERST[LH][01] signals on specific I/O-Pins at
I/O bank 2A. But this bank is used for MMI-64, FPGA configuration and clocking. However,
these signals are available for the customer. There are two options how they can be connected.
Both options are controlled by the boot option “tile_io” in the system configuration file by
setting it either to “onboard” or “extern”.
• Option 1: The nPERST signals can be connected to the I/O bank 3H on the FPGA
Module itself (see Figure 5-82). To use this option the “tile_io” must be set to
“onboard”. If an extension board is plugged onto the system (at any site) which uses
those dedicated sideband signals, the user needs to route them to the related pins at bank
3H in the FPGA design. The on board loopback requires four pins of the bank 3H,
therefore only 35 signals are available at XMBB2 (IO000…IO018 and all CLKIOs).
• Option 2: The nPERST signals are available at XMBB2 (IO023…IO026, see
Figure 5-83). The user needs an extension board connected to XMBB2 to have access to
these signals. For this purpose, the Debug Board (EB-PDS-DEBUG-R1) can be used.
FPGA Modules
Boot options
This feature must be enabled by setting “tile_io” to “extern”. Because there are no
additional I/O pins from bank 3C needed, the eight signals (required for option 1) are
also available at XMBB2 (IO019…IO022).
Figure 5-82. FM-10AX115-R1 Tile I/O Onboard Loopback (option 1)
Figure 5-83. FM-10AX115-R1 Tile I/O Connected to XMBB2 (option 2)
bitstream_option
The Arria 10 configuration interface (FPP x16) requires a different DCLK-to-DATA ratio when
the compression or the encryption is used. Therefore, the proFPGA toolchain needs to know
which setting is used for bitstream generation in Quartus. If the bitstream compression is on, the
“bitstream_option” must be set to “compressed” - otherwise it should be set to “uncompressed”.
Encrypted bitstreams are currently not supported by the proFPGA toolchain.
vref_source
The VREF is required for some I/O standards (refer to Intel Arria 10 documentation for detailed
information). With this option it can be defined if the VREF will be generated on the extension
board (“vref_source_[tb][ab][12]” is set to "EB") or on the FPGA module via resistance divider
FPGA Modules
Related Work
from the corresponding PV_IO voltage (“vref_source_[tb][ab][12]” is set to "FM"). All I/O-
banks connected to an extension board connector will use the same setting.
oct_resistor
value depends on the I/O standard (refer to Intel Arria 10 documentation for detailed
connector will use the same value (“oct_resistor_[tb][ab][12]” can be set to “100R” or “240R”).
Related Work
This topic discusses related work of Arria 10 FPGA module.

plugged onto.
Demo Designs
Table 5-81. Arria 10 FPGA Modules Demo Designs
mmi64_reg Siemens MMI64 register interface
demo for FM-10AX115-R1
Chapter 6
Extension Boards
This chapter is about Extension Boards.
DDR4 Extension Board with 2.5 Gbyte (EB-PDS-DDR4-R2/R3) . . . . . . . . . . . . . . . . . . 264

DDR4 Extension Board with 9 Gbyte (EB-PDS-DDR4-R4) . . . . . . . . . . . . . . . . . . . . . . 272
DDR4 Extension Board with 18 Gbyte (EB-PDS-DDR4-R5) . . . . . . . . . . . . . . . . . . . . . 280
DDR4 Extension Board for Intel FPGAs with 4 GByte (EB-PDS-DDR4-R8) . . . . . . . . 297
DDR4 Extension Board for Intel FPGAs witch 8 GByte (EB-PDS-DDR4-R10) . . . . . . 305
DDR4 Extension Board for Intel FPGAs with 16 GByte (EB-PDS-DDR4-R11) . . . . . . 313
DDR4 Extension Board with 5 Gbyte (EB-PDS-DDR4-R12) . . . . . . . . . . . . . . . . . . . . . 320
V3-SODIMM-R3 Board (EB-PDS-V3-SODIMM-R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
V3-SODIMM-R4 Board (EB-PDS-V3-SODIMM-R4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
DDR3 Extension Board with 4 Gbyte (EB-PDS-DDR3-R6/R7) . . . . . . . . . . . . . . . . . . . 357
DDR3 SODIMM Board (EB-PDS-DDR3-SODIMM-R2) . . . . . . . . . . . . . . . . . . . . . . . . 364
DDR3 SODIMM Board (EB-PDS-DDR3-SODIMM-R4) . . . . . . . . . . . . . . . . . . . . . . . . 369
LPDDR2 Extension Board with 512 MByte (EB-PDS-LPDDR2-R1). . . . . . . . . . . . . . . 374
LPDDR4 Extension Board with 2 Gbyte (EB-PDS-LPDDR4-R1) . . . . . . . . . . . . . . . . . 381
Multi Memory Board (EB-PDS-MULTIMEMORY-R1) . . . . . . . . . . . . . . . . . . . . . . . . 387
Flash Board (EB-PDS-FLASH-R1/R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Single MCP HyperBus Flash/RAM Board (EB-PDS-HYPER-RAM-FLASH-R1) . . . . 409
Triple SSRAM Board (EB-PDS-SRAM-R1/R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
PCIe gen1 8-lane Kit (EB-PDS-PCIe-Cable-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
PCIe gen2 dual-4-lane Kit (EB-PDS-PCIe-Cable-R6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
PCIe Root Complex and M.2 Extension Board (EB-PDS-ROOT-COMPLEX-M.2-R1) 465
PCIe Root Complex Extension Board (EB-PDS-ROOT-COMPLEX-R1). . . . . . . . . . . 475
PCIe 4-lane Host Interface Card (PCIex4_HostCableAdaptor-R2) . . . . . . . . . . . . . . . . 483
Extension Boards
Mini PCIe Host Interface Card (MPCIe_HostCableAdapter-R1) . . . . . . . . . . . . . . . . . 486

M.2 Endpoint Extension Board (EB-PDS-M.2-EP-FLEX-R2) . . . . . . . . . . . . . . . . . . . . 489
Debug Board (EB-PDS-DEBUG-SWDIO-R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
MGT Debug Board (EB-PDS-MGT-MMCX-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
FMC Mezzanine Board Adapter (EB-PDS-FMC-R1/R2/R3) . . . . . . . . . . . . . . . . . . . . . 543
FMC Bank A Mezzanine Board Adapter (EB-PDS-FMC-BANK-A-R1) . . . . . . . . . . . 553
FMC Reduced Mezzanine Board Adapter (EB-PDS-FMC-REDUCED-R1). . . . . . . . . 559
FMC LPC Mezzanine Board Adapter (EB-PDS-FMC-LPC-R1) . . . . . . . . . . . . . . . . . . 565
FMC Carrier Board Adapter (FMC-PROFPGA-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
USB 3.0 Board (EB-PDS-USB3-R1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
USB 2.0(UTMI) & 3.0(ULPI) Interface Board (EB-PDS-USB2-3-R1/R2). . . . . . . . . . . 588
GBit Ethernet Board (EB-PDS-GBITETHERNET-R1) . . . . . . . . . . . . . . . . . . . . . . . . . 598
DVI Input and Output Board (EB-PDS-DVI-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
QSFP+ Extension Board (EB-PDS-QSFP+-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
QSFP28 Extension Board (EB-PDS-QSFP28-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
EB-PDS-FIREFLY-R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
DisplayPort Extension Board (EB-PDS-DP-R1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Interface Board (EB-PDS-INTERFACE-R1/R8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Interface Board (EB-PDS-INTERFACE-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Protocol Tester Board (EB-PDS-RnS-TESTER-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
SATA Extension Board (EB-PDS-SATA-R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
SATA Extension Board (EB-PDS-SATA-R4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
ADC Board (EB-PDS-ADC250x16-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
Dual DAC Extension Board (EB-PDS-DAC1600x16-R2) . . . . . . . . . . . . . . . . . . . . . . . . 863
Riser Board (EB-PDS-RISER-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
V2 Riser Board (EB-PHS-RISER-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
Extension Boards
V2 QSFP28 Extension Board (EB-PHS-QSFP28-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 878

ARM Express Adapter Board (EB-PDS-EXPRESS-ADAPTER-R1) . . . . . . . . . . . . . . 884
Flexible Riser Board (EB-PDS-FLEXRISER-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
Zynq US+ Interface Board (EB-FM-XCZUxxEG-R2/R3). . . . . . . . . . . . . . . . . . . . . . . . 893
Multi-Cluster Clock Synchronization Boards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
Extension Boards
DDR4 Extension Board with 2.5 Gbyte (EB-PDS-DDR4-R2/R3)
DDR4 Extension Board with 2.5 Gbyte (EB-

PDS-DDR4-R2/R3)
This topic is about DDR4 Extension Board with 2.5 Gbyte (EB-PDS-DDR4-R2/R3).

Extension Board Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
FPGA Pin Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
The DDR4 extension board provides:
• One proFPGA extension board connector (bottom-side)

• 2.5 Gbyte of DDR4-2400 memory
• Programmable clock generator to create a clock for the memory generator (optimized to
meet the XILINX MIG requirements)
• Three pushbuttons
• 8 user LEDs
Extension Boards
Figure 6-1. EB-PDS-DDR-R2/R3
Figure 6-2. EB-PDS-DDR4-R2/R3 Components
Memory data sheet:
• Possible assembled devices:

o Micron Technology EDY4016AABG-DR-F-D
o Nanya Technology NT5AD256M16B2-GN
• memory organization 80-bit x 256M (5 x 16 bit x 256M)
• speed grade -DR (2400 MT/s)
• row addressing 32k (a[14:0])
• column addressing 1k (a[9:0])
• page size 2kB
Extension Boards
Extension Board Operating Conditions
• target tRCD-tRP-CL16-16-16

This topic is about Extension Board Operating Conditions.
Table 6-1. EB-PDS-DDR4-R2/R3 – Extension Board Operating Conditions

IO voltage (min…recommended…max) 1.140V…1.2V…1.260V
IO voltage provider FPGA module
Top-side extension board connector not available

This topic is about FPGA Extension Site Compatibility.
All DDR3 and DDR4 memory extension boards are optimized to meet pin location
requirements for the XILILNX Memory Interface Generator (MIG). There for if the XILNX
MIG should be used the following constraints exist:
• The DDR3 memory extension boards (EB-PDS-DDR3-R2/R3, EB-PDS-DDR3-

SODIMM-R2) should be used on all Virtex-7 and Zynq-7000 based FPGA modules.
• The DDR4 memory extension board EB-PDS-DDR4-R2 should be used on the Virtex-
Ultrascale based FPGA module FM-XCVU440-R1.
• The DDR4 memory extension boards EB-PDS-DDR4-R3/R4/R6 should be used on the
Virtex-Ultrascale based FPGA module FM-XCVU440-R2.
For applications which uses their own memory controller (e.g., Rapid Prototyping of ASIC
designs) such constraints do not exists since the FPGA internal memory controller is not used.
This means for such applications all DDR3/DDR4 memory extension boards can be used on all
FPGA technologies according to the table below.
In the table below, (*) not usable with XILINX MIG,
(1)
EB-PDS-DDR4-R2 usable with 80Bit memory data bus and XILINX MIG(**),
(2)
EB-PDS-DDR4-R2 usable with 48Bit memory data bus and XILINX MIG(**) - DQ groups
DQ[0,1,4,5,6,7] (as mentioned in the generated xdc file),
(3)
(4)
DQ[0,1,4,5,6,7] (as mentioned in the generated xdc file)
Extension Boards
(5)
(**)
Usage of AXI4 interface with XILINX MIG restricts data bus to 8, 16, 32, 64bit or 64bit +
ECC.
Table 6-2. EB-PDS-DDR4-R2/R3 – FPGA Extension Site Compatibility
FPGA Module TA1 TA2 TB1 TB1 BA1 BA2 BB1 BB2 TA1 TA2
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1 √(1) √(1) √(1) √(1) √(1) √(2) √(1) √(2)
FM-XCVU440-R2 √(3) √(3) √(3) √(3) √(3) √(4) √(3) √(4)
FM-XCVU190-R1 √(3) √(3) √(3)
FM-XCVU160-R1 √(3) √(3) √(3)
FM-XCVU125-R1 √(3) √(3) √(3)
FM-XCVU095-R1 √(3) √(3) √(3)
FM-XCVU080-R1 √(3) √(3) √(3)
FM-XCKU115-R1 √(3) √(3) √(3)
FM-XCVU5P-R1 √(3) √(3) √(3)
FM-XCVU5P-R1 √(3) √(3) √(3)
FM-XCVU7P-R1 √(3) √(3) √(3)
FM-XCVU9P-R1 √(3) √(3) √(3)
FM-XCVU13P-R1 √(3) √(3) √(3) √(3)
FM-XCVU19P-R1 √(3) √(3) √(3) √(3) √(5) √(3) √(4)
FM-XCVU37P-R1 √(3) √(3) √(3)
Extension Boards
FPGA Pin Constraints
Table 6-2. EB-PDS-DDR4-R2/R3 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU47P-R1 √(3) √(3) √(3)
FM-1SG280<L,H>-R1
FM-XCZU19EG-R2 √(3) √(3) √(3)
FM-XCZU17EG-R2 √(3) √(3) √(3)
FM-XCZU11EG-R2 √(3) √(3)
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1
In the table below, (1) EB-PDS-DDR4-R3 usable with 80Bit memory data bus and XILINX
MIG(**),
(2)
DQ[2,3,4,5,8,9] (as mentioned in the generated xdc file
(**)
ECC
Table 6-3. EB-PDS-DDR4-R2/R3 – FPGA Extension Site Compatibility,
[B,T][A,AB,B]0 Connectors
FPGA Module TA0 TAB0 TB0 BA0 BAB0 BB0
FM-1SG10M-R1
FM-XCVU19P-R1 √(1) √(1) √(2) √(2)

This topic is about FPGA Pin Constraints.
Table 6-4. EB-PDS-DDR4-R2/R3 –FPGA Pin Constraints

Signal Xilinx FPGA Intel FPGA
dq[*] IOSTANDARD =
SSTL12_DCI
dqs_p[*] IOSTANDARD =
dqs_n[*] DIFF_SSTL12_DCI
Extension Boards
Related Work
Table 6-4. EB-PDS-DDR4-R2/R3 –FPGA Pin Constraints (cont.)

ck_pck_n IOSTANDARD =
DIFF_SSTL12_DCI
dm[*] IOSTANDARD =
a[*] SSTL12_DCI
ba[*]
ras_n
cas_n
cke
odt
cs_n
reset_n IOSTANDARD =
led[*] LVCMOS12
sw[*]
Tip
Please be advised that these FPGA pin constraints recommendations are intended for the use
of an (user specific) IP core.
Caution
By using the XILILNX Memory Interface Generator (MIG) the FPGA pin constraints in the
xdc files can differ (e.g. POD12_DCI, DIFF_POD12_DCI). Please do not change these
automatically generated FPGA pin constraints.
Caution
When the DDR4 board is placed on a Virtex 7 FPGA module, not all switches and LEDs are
available. If DDR4 on a Virtex 7 is needed, please use the EB-PDS-DDR4-R1 extension
board (please ask for availability of this board). Since there is no integrated DDR4 controller for
the Virtex 7 available, it is needed that the customer has to use his own memory controller or IP
core.
Related Work
This topic is about Related Work.

Please refer to Related Work for details how to generate register map files for the Si5338.
Extension Boards
Related Work
Tip
Please use 3.3 V LVDS as output type because the output driver is connected to 3.3 V.
Because the clock is ac-coupled the offset of the voltage does not matter.
Profpga_run
If the Si5338 is used, it will be configured with a profpga plugin. To load the plugin the
plugin_list entry before the system_configuration section must be added:
...
plugin_list = ( “si5338 ProDesign EB-PDS-DDR4-R3” );
system_configuration:
{
...
If there is already a plugin_list entry the plugin list must be extended. Example:
...
plugin_list = (“dp83865dvh ProDesign EB-PDS-GBITETHERNET-R1”, “si5338
ProDesign EB-PDS-DDR4-R3” );
{
...
This will load the Si5338 plugin.
For this board the following x-board entry is required within the system configuration file:
<instance name>:
{
type = “BOARD”;
vendor = “ProDesign”;
name = „EB-PDS-DDR4-R3“;
size = “A1A1”;
positions = (“<position>”);
v_io_ba1 = “AUTO”;
# Si5338 Plugin settings

si5338_registermap_file = “<register map file>”;
si5338_validate_input_clocks_1_2_3 = “yes”;
si5338_validate_input_clocks_4_5_6 = “no”;
si5338_execute_plugin_async_event = “no”;
};
<instance name> and <position> must be replaced with the correct value according to the
system configuration. Please refer to the „proFPGA Software Reference Manual” [UD002] for
more information.
<register map file> must be replaced with the path and the filename to the register map file
created with the Si5338 software.
Extension Boards
Order Code
si5338_execute_plugin_async_event: A "yes" for this option enables the ability for

reconfiguration of the Si5338 clock generator during runtime. The reconfiguration, based on the
register map file, is triggered by the command line option --plugin-async-events for
profpga_run. Please refer to the „proFPGA Software Reference Manual” [UD002] for more
information.

plugged onto.
Please ensure that the system configuration file which is the input to the profpga_brdgen tool
contains a valid x-board entry using the extension board name “EB-PDS-DDR4-R2” or “EB-
PDS-DDR4-R3”. The system configuration file can be created manually or with the
profpga_builder tool.
Please refer to the „proFPGA Software Reference Manual” [SWRM] and the “proFPGA
Order Code
This topic is about Order Code.
286472
Extension Boards
DDR4 Extension Board with 9 Gbyte (EB-PDS-DDR4-R4)
DDR4 Extension Board with 9 Gbyte (EB-PDS-

DDR4-R4)
This topic is about DDR4 Extension Board with 9 Gbyte (EB-PDS-DDR4-R4).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
This topic is about Functional description.

• 9x 8 Gb of DDR4-2400 memory (9 x Micron MT40A1G8PM-083E chips)
• programmable clock generator to create a clock for the memory generator (optimized to
• Three push-buttons
• 6 user LEDs
The Memory was successfully tested with the version 2.2 of the XILINX External
Memory Interface (previously MIG) up to app. 677 MT/s). The test ran with an input
clock of 87.6666MHz, which was generated by the onboard clock generator.
Caution
The demonstration design can be found in the $PROFPGA/hdl/demo_designs/EB-PDS-
DDR4-R4 directory for reference.
The design was generated using Vivado 2017.4.
Tip
In order to reproduce test with the XILINX External Memory Interface during IP generation
please select the custom memory part and choose the ‘MT40A1G8PM-083E.csv ‘file from
the $PROFPGA/hdl/demo_designs/EB-PDS-DDR4-R4/source/constraints. With this file the
memory device ‘MT40A1G8PM-083E’ must be chosen.
Extension Boards
Tip
Based on 1600ps must be selected for the memory clock period and 6400ps for the memory
interface input clock. The CAS latency value must be set to 16.
Once bitsteam is available the reference clock frequency must be set to 87.6666MHz using the
si5338 register map file Si5338_RegisterMap_87.6666MHz.txt which can be found in the
$PROFPGA/hdl/demo_designs/EB-PDS-DDR4-R4/ready_to_run directory.
Figure 6-3. EB-PDS-DDR4-R4
Figure 6-4. EB-PDS-DDR4-R4 Components
Extension Boards
Memory data sheet:

• device name Micron MT40A1G8PM-083E
• memory organization 72 bit x 1Gb (9 x 8 bit x 1Gb)
• page size 1kB
• target tRCD-tRP-CL 16-16-16

This topic is about Extension Board Operating Conditions
Table 6-5. EB-PDS-DDR4-R4 – Extension Board Operating Conditions



designs) such constraints do not exist since the FPGA internal memory controller is not used.
Extension Boards
Table 6-6. EB-PDS-DDR4-R4 – FPGA Extension Site Compatibility

FPGA Module TA1 TA2 TB1 TB2 BA1 BA2 BB1 BB2 TA1 Ta2
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1 √(1) √(1) √(1) √(1) √(1) √(2) √(1) √(2)
FM-XCVU440-R2 √(1) √(1) √(1) √(1) √(1) √(2) √(1) √(2)
FM-XCVU190-R1 √(1) √(1) √(1)
FM-XCVU160-R1 √(1) √(1) √(1)
FM-XCVU125-R1 √(1) √(1) √(1)
FM-XCVU095-R1 √(1) √(1) √(1)
FM-XCVU080-R1 √(1) √(1) √(1)
FM-XCKU115-R1 √(1) √(1) √(1)
FM-XCVU5P-R1 √(1) √(1) √(1)
FM-XCVU7P-R1 √(1) √(1) √(1)
FM-XCVU9P-R1 √(1) √(1) √(1)
FM-XCVU13P-R1 √(1) √(1) √(1) √(1)
FM-XCVU19P-R1 √(1) √(1) √(1) √(1) √(3) √(1) √(2)
FM-XCVU37P-R1 √(1) √(1) √(1)
FM-XCVU47P-R1 √(1) √(1) √(1)
FM-1SG280<L,H>-R1
FM-XCZU19EG-R2 √(1) √(1) √(1)
FM-XCZU17EG-R2 √(1) √(1) √(1)
Extension Boards
Table 6-6. EB-PDS-DDR4-R4 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCZU11EG-R2 √(1) √(1)
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1
(*)
not useable with XILINX MIG,
(1)
usable with 72Bit memory data bus and XILINX MIG(**),
(2)
usable with 40Bit memory data bus and XILINX MIG(**) - DQ groups DQ[0,1,4,5,7] (as
mentioned in the generated xdc file),
(3)
mentioned in the generated xdc file)
(**) Usage
of AXI4 interface with XILINX MIG restricts data bus to 8, 16, 32, 64bit or 64bit +
ECC.
Table 6-7. EB-PDS-DDR4-R4 – FPGA Extension Site Compatibility,
FM-1SG10M-R1
FM-XCVU19P-R1 √(1) √(1) √(2) √(2)
(1) usable with 72Bit memory data bus and XILINX MIG(**),
(2)
(**) Usage of AXI4 interface with XILINX MIG restricts data bus to 8, 16, 32, 64bit or 64bit +
ECC.

Extension Boards
Related Work
Table 6-8. EB-PDS-DDR4-R4 –FPGA Pin Constraints

dq[*] IOSTANDARD =
SSTL12_DCI
ck_p IOSTANDARD =
ck_n DIFF_SSTL12_DCI
dm[*]a[*]ba[*]ras_ncas_nck IOSTANDARD =
eodtcs_n SSTL12_DCI
reset_nled[*]sw[*] IOSTANDARD =
LVCMOS12
Tip
Caution
Caution
core.
Related Work
This topic is about Related Work

Tip
Extension Boards
Related Work
Profpga_run
...
{
...
...
{
...
This will load the Si5338 plugin. For this board the following x-board entry is required within
the system configuration file:
<instance name>:
{
type = “BOARD”;
name = "EB-PDS-DDR4-R4“;
size = “A1A1”;

};
more information.

profpga_run. Please refer to the “proFPGA Software Reference Manual” [UD002] for more
information.
Extension Boards
Order Code

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-DDR4-R4”. The
system configuration file can be created manually or with the profpga_builder tool.
Order Code
This topic is about Order ode.
Discontinued.
Extension Boards
DDR4 Extension Board with 18 Gbyte (EB-

PDS-DDR4-R5)
This topic is about DDR4 Extension Board with 18 Gbyte (EB-PDS-DDR4-R5).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

• 9x 16 Gb of DDR4-2400 memory (9 x Micron MT40A2G8FSE-083E chips)
• 6 user LEDs
Caution
The design, created with Vivado 2017.4 and the XILINX external memory interface
(previously MIG) with the V2.2 (Rev. 3), was successfully tested up to app. 677 MT/s. The
test ran with an input clock of 87.6666MHz, which was generated by the onboard clock
generator.
The design, created with Vivado 2018.03 and the XILINX external memory interface
(previously MIG) with the V2.2 (Rev. 6), was successfully tested up to app. 1259 MT/s on TA1,
TA2, TB1 and TB2. The test ran with an input clock of 90MHz, which was generated by the
onboard clock generator. The demonstration design can be found in the $PROFPGA/hdl/
demo_designs/EB-PDS-DDR4-R5 directory for reference.
Extension Boards
Tip
please select the custom memory part and choose the ‘MT40A2G8FSE-083E.csv‘ file from
the $PROFPGA/hdl/demo_designs/EB-PDS-DDR4-R5/source/constraints. With this file the
memory device ‘EB-PDS-DDR4-R5_MT40A2G8FSE-083E’1must be chosen.
Tip
For external memory interface V2.2 (Rev. 3) (Vivado 2017.4):
• Based on 1600ps must be selected for the memory clock period and 6400ps for the
memory interface input clock. The CAS latency value must be set to 16.
• Once bitsteam is available the reference clock frequency must be set to 87.6666MHz
using the si5338 register map file Si5338_RegisterMap_87.6666MHz.txt which can be
found in the $PROFPGA/hdl/demo_designs/EB-PDS-DDR4-R5/ready_to_run
directory.
Tip
For external memory interface V2.2 (Rev. 6) (Vivado 2018.3):
• Based on 938ps must be selected for the memory clock period and 6567ps for the
memory interface input clock. The CAS latency value must be set to 16.
• Once bitsteam is available the reference clock frequency must be set to 90MHz using the
si5338 register map file Si5338_RegisterMap_90Hz.txt which can be found in the
$PROFPGA/hdl/demo_designs/EB-PDS-DDR4-R5/ready_to_run directory.
1. Please do not select the ‘MT40A2G8FSE-083E’ which is predefined by XILINX.
Extension Boards
Memory data sheet:

• device name Micron MT40A2G8FSE-083E
• memory organization 72 bit x 2Gb (9 x 8 bit x 2Gb)
• page size 1kB



Extension Boards

(1) EB-PDS-DDR4-R6
usable with 80Bit memory data bus and XILINX MIG(**),
(2) EB-PDS-DDR4-R6
usable with 48Bit memory data bus and XILINX MIG(**) - DQ groups
DQ[2,3,4,5,8,9] (as mentioned in the generated xdc file
(**) Usage of AXI4 interface with XILINX MIG restricts data bus to 8, 16, 32, 64bit or 64bit +
ECC
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1 √(1) √(1) √(1) √(1) √(1) √(2) √(1) √(2)
FM-XCVU440-R2 √(1) √(1) √(1) √(1) √(1) √(2) √(1) √(2)
FM-XCVU190-R1 √(1) √(1) √(1)
FM-XCVU160-R1 √(1) √(1) √(1)
Extension Boards

V1 V1
FM-XCVU125-R1 √(1) √(1) √(1)
FM-XCVU095-R1 √(1) √(1) √(1)
FM-XCVU080-R1 √(1) √(1) √(1)
FM-XCKU115-R1 √(1) √(1) √(1)
FM-XCVU5P-R1 √(1) √(1) √(1)
FM-XCVU7P-R1 √(1) √(1) √(1)
FM-XCVU9P-R1 √(1) √(1) √(1)
FM-XCVU13P-R1 √(1) √(1) √(1) √(1)
FM-XCVU19P-R1 √(1) √(1) √(1) √(1) √(3) √(1) √(2)
FM-XCVU37P-R1 √(1) √(1) √(1)
FM-XCVU47P-R1 √(1) √(1) √(1)
FM-1SG280<L,H>-R1
FM-XCZU19EG-R2 √(1) √(1) √(1)
FM-XCZU17EG-R2 √(1) √(1) √(1)
FM-XCZU11EG-R2 √(1) √(1)
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1
In the table below, (1) usable with 72Bit memory data bus and XILINX MIG(**),
(2)
(**)
ECC.
FM-1SG10M-R1
Extension Boards

[B,T][A,AB,B]0 Connectors (cont.)
FM-XCVU19P-R1 √(1) √(1) √(2) √(2)

Table 6-12. EB-PDS-DDR4-R5 – FPGA Pin Constraints

dq[*] IOSTANDARD =
SSTL12_DCI
DIFF_SSTL12_DCI
dm[*] IOSTANDARD =
a[*] SSTL12_DCI
ba[*]
ras_n
cas_ncke
odt
cs_n
LVCMOS12
Note
Caution
Extension Boards
Related Work
Caution
core.
Related Work
This topic is about Related work.

Note
Profpga_run
...
{
...
...
plugin_list = (“dp83865dvh ProDesign EB-PDS-GBITETHERNET-R1”,
“si5338 ProDesign EB-PDS-DDR4-R5” );
{
Extension Boards
Order Code
<instance name>:
{
type = “BOARD”;
size = “A1A1”;
};
more information.

information.

plugged onto.
Order Code
Extension Boards
Order Code
286473
Extension Boards

DDR4-R6)
This topic is about DDR4 Extension Board with 5 Gbyte (EB-PDS-DDR4-R6)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

• 5 Gbyte of DDR4-2400 memory (5x Micron MT40A512M16HA-083E chips)
• 8 user LEDs
Extension Boards
Figure 6-7. EB-PDS-DDR-R6
Memory data sheet:

• device name Micron MT40A512M16HA-083E
• memory organization 80-bit x 512M (5 x 16-bit x 512M)
• speed grade -083E (2400 MT/s)
• page size 2kB
Extension Boards



requirements for the XILILNX Memory Interface Generator (MIG). Therefore, if the XILNX

In the table below, (*) not usable with XILINX MIG,
(3)
(4)
DQ[0,1,4,5,6,7]
(5)
DQ[2,3,4,5,8,9]
Extension Boards
(**)
ECC.
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1
FM-XCVU440-R2 √(3) √(3) √(3) √(3) √(3) √(4) √(3) √(4)
FM-XCVU190-R1 √(3) √(3) √(3)
FM-XCVU160-R1 √(3) √(3) √(3)
FM-XCVU125-R1 √(3) √(3) √(3)
FM-XCVU095-R1 √(3) √(3) √(3)
FM-XCVU080-R1 √(3) √(3) √(3)
FM-XCKU115-R1 √(3) √(3) √(3)
FM-XCVU5P-R1 √(3) √(3) √(3)
FM-XCVU7P-R1 √(3) √(3) √(3)
FM-XCVU9P-R1 √(3) √(3) √(3)
FM-XCVU13P-R1 √(1) √(1) √(1) √(1)
FM-XCVU19P-R1 √(3) √(3) √(3) √(3) √(5) √(3) √(4)
FM-XCVU37P-R1 √(3) √(3) √(3)
FM-XCVU47P-R1 √(3) √(3) √(3)
FM-1SG280<L,H>-R1
FM-XCZU19EG-R2 √(3) √(3) √(3)
Extension Boards

V1 V1
FM-XCZU17EG-R2 √(3) √(3) √(3)
FM-XCZU11EG-R2 √(3) √(3)
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1
MIG(**),
(2)EB-PDS-DDR4-R6
usable with 48Bit memory data bus and XILINX MIG(**) - DQ groups
(**)
ECC
Table 6-15. FPGA Extension Site Compatibility, [B,T][A,AB,B]0 Connectors
FM-1SG10M-R1
FM-XCVU19P-R1 √(1) √(1) √(2) √(2)

This topic is about FPGA Pin Constraints

dq[*] IOSTANDARD =
SSTL12_DCI
dqs_p[*]dqs_n[*] IOSTANDARD =
DIFF_SSTL12_DCI
DIFF_SSTL12_DCI
eodtcs_n SSTL12_DCI
Extension Boards
Related Work
Table 6-16. EB-PDS-DDR4-R6 – FPGA Pin Constraints (cont.)

LVCMOS12
Tip
Caution
Caution
core.
Related Work

Note
Profpga_run
...
{
...
Extension Boards
Related Work
...
{
...
<instance name>:
{
type = “BOARD”;
size = “A1A1”;

};
more information.

information.

plugged onto.
Extension Boards
Order Code
Order Code
286483
Extension Boards
DDR4 Extension Board for Intel FPGAs with 4 GByte (EB-PDS-DDR4-R8)
DDR4 Extension Board for Intel FPGAs with 4

This section is about DDR4 Extension Board for Intel FPGAs with 4 GBye (EB-PDS-DDR4-
R8).
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

• 4 Gbyte of DDR4-2400 memory (4x Micron MT40A512M16HA-083E chips)
meet the Intel EMIF IP requirements)
• 12 user LEDs
Extension Boards
Memory data sheet:

• device name Micron MT40A512M16HA-083E
• memory organization 64 bit x 512M (4 x 16 bit x 512M)
• chip select 1 (cs_n)
• bank group addressing 2 (bg[0])
• bank addressing 4 (ba[1:0])
• page size 2kB

Table 6-17. EB-PDS-DDR4-R8 – eXtension Board Operating Conditions

Extension Boards

The DDR4 memory extension board is optimized to meet pin location requirements for the Intel
Stratix 10 EMIF. For applications which use their own memory controller (e.g., Rapid
Prototyping of ASIC designs) such constraints do not exist since the FPGA internal memory
controller is not used. This means for such applications all DDR3/DDR4 memory extension
boards can be used on all FPGA technologies according to the table below.
In the table below, (1) Intel EMIF IP example design (Quartus 17.1.1, Synthesis timing models
are not final in this version)
(2)
Tests for this connector pending
(3)
tested with 1866 MT/s (tests with higher rates pending)
(4)
(5)
(6) Intel EMIF IP example design (Quartus 19.1.0)(7) tested with 2000 MT/s(8) tested with 2400
MT/s
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1
FM-XCVU440-R2
FM-XCVU190-R1
FM-XCVU160-R1
FM-XCVU125-R1
Extension Boards

V1 V1
FM-XCVU095-R1
FM-XCVU080-R1
FM-XCKU115-R1
FM-XCVU5P-R1
FM-XCVU7P-R1
FM-XCVU9P-R1
FM-XCVU13P-R1
FM-XCVU19P-R1
FM-XCVU37P-R1
FM-XCVU47P-R1
FM-1SG280L-R1
FM-1SG280L-R2 √(1,3 (1,2) √(1,5 √(1,4 (1,2) √(1,4 √(1,4
) ) ) ) )
FM-XCZU19EG-R2
FM-XCZU17EG-R2
FM-XCZU11EG-R2
FM-1SG280H-R<1,2> √(6,8 √(6,8 √(6,8 √(6,8 √(6,7 √(6,7 √(6,7
) ) ) ) ) ) )
FM-10AX115-R1 √(6,7 √(6,7 √(6,7 √(6,7

) ) ) )
FM-1SG10M-R1 √(6,8 √(6,8 √(6,8 √(6,8 √(6,7 √(6,8 √(6,7 √(6,8

) ) ) ) ) ) ) )
MIG(**),
(2)
(**)
ECC
Extension Boards

FM-1SG10M-R1 √(6.8) √(6.8) √(6.8) √(6.8) √(6.8) √(6.8)
FM-XCVU19P-R1


Signal Xilinx Intel FPGA
FPGA
local_reset_req set_location_assignment
PIN_BA21
local_reset_done set_location_assignment
PIN_BC22
emif_s10_0_pll_ref_clk_clk set_instance_assignment -
name IO_STANDARD
LVDS
set_instance_assignment -
name
INPUT_TERMINATION
DIFFERENTIAL
emif_s10_0_tg_0_traffic_gen_timeout set_instance_assignment -
emif_s10_0_status_local_cal_fail name IO_STANDARD “1.2
V”
emif_s10_0_tg_0_traffic_gen_pass
emif_s10_0_tg_0_traffic_gen_fail
emif_s10_0_status_local_cal_success
Note
of an EMIF from Intel.
Extension Boards
Related Work
Related Work
Under demo design folder of proFPGA installation the EB-PDS-DDR4-R8 folder can be found
containing scripts for generation of Intel EMIF test design with all required settings for this
board.

Note
Profpga_run
...
{
...
...
{
...
Extension Boards
Order Code
<instance name>:
{
type = “BOARD”;
size = “A1A1”;

};
more information.

information.

plugged onto.
Order Code
This topic is about Order Code
Extension Boards
Order Code
286474
Extension Boards
DDR4 Extension Board for Intel FPGAs witch 8 GByte (EB-PDS-DDR4-R10)
DDR4 Extension Board for Intel FPGAs witch 8

This topic is about DDR4 Extension Board for Intel FPGAs with 8 GByte (EB-PDS-DDR4-
R10).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

• 8 Gbyte of DDR4-3200 memory (4x Micron MT40A1G16RC-062E chips)
• 12 user LEDs
Extension Boards
Memory data sheet:

• device name Micron MT40A1G16RC-062E
• bank group addressing 2 (bg[0])
Extension Boards
• page size 2kB




Stratix 10 EMIF. For applications which use their own memory controller (e.g., Rapid
Prototyping of ASIC designs) such constraints do not exist since the FPGA internal memory
controller is not used. This means for such applications all DDR3/DDR4 memory extension
boards can be used on all FPGA technologies according to the table below.
In the table below, (1) Intel EMIF IP example design (Quartus 17.1.1, Synthesis timing models
are not final in this version)
(2) Tests
for this connector pending
(3)
(4)
(5) tested with 1333 MT/s (tests with higher rates pending)
(6) Intel EMIF IP example design (Quartus 19.1.0)
(7) tested with 2000 MT/s
(8)
tested with 2400 MT/s
Extension Boards

V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1
FM-XCVU440-R2
FM-XCVU190-R1
FM-XCVU160-R1
FM-XCVU125-R1
FM-XCVU095-R1
FM-XCVU080-R1
FM-XCKU115-R1
FM-XCVU5P-R1
FM-XCVU7P-R1
FM-XCVU9P-R1
FM-XCVU13P-R1
FM-XCVU19P-R1
FM-XCVU37P-R1
FM-XCVU47P-R1
FM-1SG280L-R1
FM-1SG280L-R2 √(1,3 (1,2)
√(1,5 √(1,4 (1,2)
√(1,4 √(1,4
) ) ) ) )
FM-XCZU19EG-R2
FM-XCZU17EG-R2
FM-XCZU11EG-R2
Extension Boards

V1 V1
FM-1SG280H-R<1,2> √(6,8 √(6,8 √(6,8 √(6,8 √(6,7 √(6,7 √(6,7
) ) ) ) ) ) )
FM-10AX115-R1 √(6,7 √(6,7 √(6,7 √(6,7

) ) ) )
FM-1SG10M-R1 √(6,8 √(6,8 √(6,8 √(6,8 √(6,7 √(6,8 √(6,7 √(6,8

) ) ) ) ) ) ) )

FM-1SG10M-R1 √(6,8) √(6,8) √(6,/8) √(6,8) √(6,8) √(6,8)
FM-XCVU19P-R1


PIN_BA21
PIN_BC22
name IO_STANDARD
LVDSset_instance_assignm
ent -name
INPUT_TERMINATION
DIFFERENTIAL
Extension Boards
Related Work
Table 6-24. EB-PDS-DDR4-R10 – FPGA Pin Constraints (cont.)

emif_s10_0_tg_0_traffic_ge set_instance_assignment -
n_timeout name IO_STANDARD “1.2
emif_s10_0_status_local_cal V”
_fail
emif_s10_0_tg_0_traffic_ge
n_pass
n_fail
emif_s10_0_status_local_cal
_success
Note
Related Work
containing schripts for generation of Intel EMIF test design with all required settings for this
board.

Note
Profpga_run
...
{
...
Extension Boards
Related Work
...
{
...
<instance name>:
{
type = “BOARD”;
size = “A1A1”;

};
more information.

information.

plugged onto.
Extension Boards
Order Code
Order Code
286491
Extension Boards
DDR4 Extension Board for Intel FPGAs with 16 GByte (EB-PDS-DDR4-R11)
DDR4 Extension Board for Intel FPGAs with 16

This topic is about DDR4 Extension Board for intel FPGAs with 16 GByte (EB-PDS-DDR4-
R11)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

• 16 Gbyte of DDR4-2400 memory (8x Micron MT40A2G8NRE-083E chips)
• 12 user LEDs
Extension Boards
Figure 6-14. EB-PDS-DDR4-R11- Components
Memory data sheet:

• device name Micron MT40A2G8NRE-083E
• bank group addressing 4 (bg[1:0])
Extension Boards




This topic is about FPGA Extension Site Compatbility.
Stratix 10 EMIF.
For applications which use their own memory controller (e.g., Rapid Prototyping of ASIC
In the table below, (1) Intel EMIF IP example design (Quartus 20.3.0)
(2) Tests
for this connector pending.
(3)
(4)
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
Extension Boards

V1 V1
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1
FM-XCVU440-R2
FM-XCVU190-R1
FM-XCVU160-R1
FM-XCVU125-R1
FM-XCVU095-R1
FM-XCVU080-R1
FM-XCKU115-R1
FM-XCVU5P-R1
FM-XCVU7P-R1
FM-XCVU9P-R1
FM-XCVU13P-R1
FM-XCVU19P-R1
FM-XCVU37P-R1
FM-XCVU47P-R1
FM-1SG280L-R1
FM-1SG280L-R2
FM-XCZU19EG-R2
FM-XCZU17EG-R2
FM-XCZU11EG-R2
FM-1SG280H-R<1,2> (2) (2) (2) (2) (2) (2) (2)
FM-10AX115-R1 (2) (2) (2) (2)
FM-1SG10M-R1 √(1,4 √(1,4 √(1,4 √(1,4 √(1,3 √(1,3 √(1,3 √(1,3

) ) ) ) ) ) ) )
Extension Boards

FPGA Module
FM-1SG10M-R1 √(1,4) √(1,4) √(1,4) √(1,4) √(1,4) √(1,4)
FM-XCVU19P-R1


PIN_BA21
PIN_BC22
name IO_STANDARD
LVDS
set_instance_assignment -
name
INPUT_TERMINATION
DIFFERENTIAL
emif_s10_0_tg_0_traffic_ge set_instance_assignment -
n_timeout name IO_STANDARD “1.2
emif_s10_0_status_local_cal V”
_fail
n_pass
n_fail
emif_s10_0_status_local_cal
_success
Note
Extension Boards
Related Work
Related Work
containing scripts for generation of Intel EMIF test design with all required settings for this
board.

Tip
Profpga_run
...
{
...
...
{
...
Extension Boards
Order Code
<instance name>:
{
type = “BOARD”;
size = “A1A1”;

};
system configuration. Please refer to the “proFPGA Software Reference Manual” [UD002] for
more information.

information.

plugged onto.
Order Code
286492
Extension Boards

DDR4-R12)
This topic is about DDR4 Extension Board with 5 GByte.

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

• R12: 5 Gbyte of DDR4-2666 memory (5x Micron MT40A512M16LY-75E chips)
• 8 user LEDs
Extension Boards
Figure 6-15. EB-PDS-DDR-R12
Figure 6-16. EB-PDS-DDR4 Components
Memory data sheet:

• device name Micron MT40A512M16LY-075E
• memory organisation 80-bit x 512M (5 x 16-bit x 512M)
Extension Boards

• page size 2kB



The FPGA extension site compatibility is splitted into two use cases:
• DDR4 SODIMM -> only FPGA modules which have full support will be listed
Table 6-30. EB-PDS-V3-SODIMM-R4– DDR4 SODIMM FPGA Extension Site

Compatibility.
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1
Extension Boards

Compatibility. (cont.)
V1 V1
FM-XCVU440-R2
FM-XCVU190-R1
FM-XCVU160-R1
FM-XCVU125-R1
FM-XCVU095-R1
FM-XCVU080-R1
FM-XCKU115-R1
FM-XCVU5P-R1
FM-XCVU7P-R1
FM-XCVU9P-R1
FM-XCVU13P-R1
FM-XCVU19P-R1
FM-XCVU37P-R1
FM-XCVU47P-R1
FM-XCZU11EG-R2
FM-XCZU17EG-R2
FM-XCZU19EG-R2
FM-1SG280<L,H>-R1
FM-1SG280<L,H>-R2 (p) (p) (p) (p) (p) (p)
FM-10AX115-R1 (p) (p) (p) (p)
FM-1SG10M-R1 √(1) √(1) √(1) √(1) √(2) √(1) √(1) √(1)

4 Since all regular IO and CLK_IO signals are simply routed through from bottom to top
connector this board does not have any specific requirements regarding the IO voltage. If an
extension board or cable is used on top of this board the IO voltage requirements of this upper-
level hardware will be applied.
(p) Tests for this connector pending
Extension Boards
(1) Tested
with 64-bit dual rank 18ASF4G72HZ-3G2B1 / M471A4G43MB1-CTD and speed
grade 2 FPGA @ 2400Mbit/s, tested with 72-bit single rank without DM / DBI 9ASF1G72HZ-
2G6E2 and speed grade 2 FPGA @ 2400Mbit
(2)Tested with 64-bit dual rank 18ASF4G72HZ-3G2B1 / M471A4G43MB1-CTD and speed

Table 6-31. EB-PDS-V3-SODIMM-R4 – DDR4 SODIMM FPGA Extension Site
Compatibility, [B,T][A,AB,B]0 Connectors
FM-XCVU19P-R1
FM-1SG10M-R1 √(1) √(1) √(1) √(1) √(1) √(1)
• Custom extension boards -> all combinations will be listet, independently from the
number of available IOs
Table 6-32. EB-PDS-V3-SODIMM-R4– Custom Extension Board FPGA

Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √ √ √ √ √ √
FM-XC7VX485T-R3 √ √ √ √ √ √ √ √
FM-XC7V585T-R3 √ √ √ √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(EB √(EB
) )
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(EB √(EB

) )
FM-XCVU190-R1 √ √ √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √ √ √
Extension Boards
Table 6-32. EB-PDS-V3-SODIMM-R4– Custom Extension Board FPGA

Extension Site Compatibility (cont.)
V1 V1
FM-XCVU080-R1 √ √ √ √ √ √
FM-XCKU115-R1 √ √ √ √ √ √
FM-XCVU5P-R1 √ √ √ √ √ √
FM-XCVU7P-R1 √ √ √ √ √ √
FM-XCVU9P-R1 √ √ √ √ √ √
FM-XCVU13P-R1 √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(EB √(EB
) )
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √ √
FM-XCZU19EG-R2 √ √ √ √ √
FM-XCZU17EG-R2 √ √ √ √ √
FM-XCZU11EG-R2 √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √ √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(EB √(EB
) )
(EB)
using EB-FM-XCVU440-R1.
Table 6-33. EB-PDS-V3-SODIMM-R4 – Custom Extension Board FPGA
Extension Site Compatibility, [B,T][A,AB,B]0 Connectors
FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Extension Boards
Related Work

dq[*] IOSTANDARD =
SSTL12_DCI
dqs_p[*]dqs_n[*] IOSTANDARD =
DIFF_SSTL12_DCI
DIFF_SSTL12_DCI
dm[*]a[*] IOSTANDARD =
ba[*] SSTL12_DCI
ras_n
cas_n
cke
odt
cs_n
LVCMOS12
Note
Caution
Caution
core.
Related Work
Extension Boards
Related Work

Note
Profpga_run
...
plugin_list = ( “si5338 Siemens EB-PDS-DDR4-R12” );
{
...
...
plugin_list = (“dp83865dvh ProDesign EB-PDS-GBITETHERNET-R1”,
“si5338 Siemens EB-PDS-DDR4-R12” );
{
...
<instance name>:
{
type = “BOARD”;
vendor = “Siemens”;
size = “A1A1”;
};
more information.
Extension Boards
Order Code

information.

plugged onto.
Order Code
The Order Code is mentioned in this topic.
290084 Veloce PF DDR4 w/o SODIMM Xilinx
Extension Boards
V3-SODIMM-R3 Board (EB-PDS-V3-SODIMM-R3)
V3-SODIMM-R3 Board (EB-PDS-V3-SODIMM-

R3)
This topic is about V3-SODIMM-R3 Board (EB-PDS-V3-SODIMM-R3)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
The V3-SODIMM-R3 board was developed for Xilinx FPGA modules to make SODIMM
modules available. It can be used with every common DDR4-SODIMM module available on
the market. For bringup it was tested with the following 3 SODIMM modules:
• 18ASF4G72HZ-3G2B1 (Micron)
• 9ASF1G72HZ-2G6E2 (Micron)
• M471A4G43MB1-CTD (Samsung)
Beside the support of DDR4-SODIMM modules, also custom extension boards can be used.
Features of the extension board:

• One DDR4-SODIMM slot
• Programmable clock generator to create a clock for the IP inside the FPGA
• 12V power connector – only needed for custom SODIMM extension boards
Extension Boards
Figure 6-17. EB-PDS-V3-SODIMM-R3

Table 6-35. EB-PDS-V3-SODIMM-R3 – Extension Board Operating Conditions

[DDR4]
IO voltage (min…recommended…max) any1
[custom extension boards]
IO voltage provider FPGA module for FPGA Bank and DDR4
SODIMM connector
Top-side extension board connector yes – V3 / DDR4 SODIMM connector
1. Since all regular IO and CLK_IO signals are simply routed through from bottom to top connector this
board does not have any specific requirements regarding the IO voltage. If an extension board or cable
is used on top of this board the IO voltage requirements of this upper-level hardware will be applied.
Extension Boards

In the table below, (p) Tests for this connector pending
(1) Tested with 18ASF4G72HZ-3G2B1 and speed grade 2 FPGA @ 1600Mbit/s
(2)
Tested with 18ASF4G72HZ-3G2B1 and speed grade 3 FPGA @ 1866Mbit/s
(3)Since all regular IO and CLK_IO signals are simply routed through from bottom to top
level hardware will be applied.
Compatibility
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1 (p) (p) (p) (p) (p) (p)
FM-XCVU440-R2 √(1) √(1) √(1) √(1) √(1) √(1)

FM-XCVU190-R1 (p) (p) (p)
Extension Boards

Compatibility (cont.)
V1 V1
FM-XCKU115-R1 (p) (p) (p)
FM-XCVU5P-R1 (p) (p) (p)
FM-XCVU13P-R1 √(2) √(2) (p)
FM-XCVU19P-R1 (p) (p) (p) (p) (p)
FM-XCZU11EG-R2 (p) (p)
FM-1SG280<L,H>-R1
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1

FM-XCVU19P-R1 (p) (p)
FM-1SG10M-R1
• Custom extension boards -> all combinations will be listet, independently from the number of
available IOs
Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √
Extension Boards

V1 V1
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √ √ √ √ √ √
FM-XC7VX485T-R3 √ √ √ √ √ √ √ √
FM-XC7V585T-R3 √ √ √ √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(EB √(EB
) )
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(EB √(EB

) )
FM-XCVU190-R1 √ √ √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √ √ √
FM-XCVU080-R1 √ √ √ √ √ √
FM-XCKU115-R1 √ √ √ √ √ √
FM-XCVU5P-R1 √ √ √ √ √ √
FM-XCVU7P-R1 √ √ √ √ √ √
FM-XCVU9P-R1 √ √ √ √ √ √
FM-XCVU13P-R1 √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(EB √(EB
) )
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √ √
FM-XCZU19EG-R2 √ √ √ √ √
FM-XCZU17EG-R2 √ √ √ √ √
Extension Boards

V1 V1
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √ √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(EB √(EB
) )
Table 6-39. EB-PDS-V3-SODIMM-R3 – Custom Extension Board Fpga

Extension Site Compatibility, [B,T][A,AB,B]0 Connectors
FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Table 6-40. EB-PDS-V3-SODIMM-R3–FPGA Pin Constraints

all IO signals [custom <any> <any>
extension board on top]
all IO signals [DDR4] Refer to Xilinx MIG
example design
Related Work
This topic is about Related Work

Extension Boards
Related Work
Caution
profpga_run
If the Si5338 is used, it will be configured with a profpga plugin. To load the plugin, the
...
plugin_list = ( "si5338 Siemens EB-PDS-V3-SODIMM-R3" );
{
...
...
plugin_list = ("dp83865dvh ProDesign EB-PDS-GBITETHERNET-R1",
"si5338 Siemens EB-PDS-V3-SODIMM-R3" );
{
...
<instance name>:
{
type = "BOARD";
vendor = "Siemens";
name = "EB-PDS-V3-SODIMM-R3";
size = "A1A1";
positions = ("<position>");
v_io_ba1 = "AUTO";
si5338_registermap_file = "<register map file>";
si5338_validate_input_clocks_1_2_3 = "yes";
si5338_validate_input_clocks_4_5_6 = "no";
};
more information.<register map file> must be replaced with the path and the filename to the
register map file created with the Si5338 software.si5338_execute_plugin_async_event: A
"yes" for this option enables the ability for reconfiguration of the Si5338 clock generator during
runtime. The reconfiguration, based on the register map file, is triggered by the command line
option --plugin-async-events for profpga_run. Please refer to the „proFPGA Software
Reference Manual” [UD002] for more information.
Extension Boards
Order Code

plugged onto.Please ensure that the system configuration file which is the input to the
profpga_brdgen tool contains a valid x-board entry using the extension board name “EB-PDS-
V3-SODIMM-R3”. The system configuration file can be created manually or with the
profpga_builder tool.Please refer to the „proFPGA Software Reference Manual” [UD002] and
the “proFPGA Builder User Manual” [UD004] for more information.
Order Code
Order code not yet available
Extension Boards
V3-SODIMM-R4 Board (EB-PDS-V3-SODIMM-R4)
V3-SODIMM-R4 Board (EB-PDS-V3-SODIMM-

R4)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
The V3-SODIMM-R4 board was developed for Stratix 10 FPGA modules to make SODIMM
modules available. It can be used with every common DDR4-SODIMM module available on
the market. For bringup it was tested with the following 3 SODIMM modules:
• 18ASF4G72HZ-3G2B1 (Micron)
• 9ASF1G72HZ-2G6E2 (Micron)
• M471A4G43MB1-CTD (Samsung)
Beside the support of DDR4-SODIMM modules, also custom extension boards can be used.

• One DDR4-SODIMM slot
• Programmable clock generator to create a clock for the IP inside the FPGA
• 12V power connector – only needed for custom SODIMM extension boards
Extension Boards
Figure 6-18. EB-PDS-V3-SODIMM-R4
At the FPGA module 3 FPGA banks are connected to one proFPGA V0 connector. At 3 banks,
the Intel Stratix 10 FPGA supports DDR4 SODIMM in the following constellations:
• 64-bit dual rank

• 72-bit single rank without DM / DBI support
The board supports both modes with the limitation, that 72-bit is only usable without DM / DBI
support because there are no pins left at the FPGA to connect DM8.Due to the limitation of the
Stratix 10 it is not possible to use 72-bit dual rank within 3 FPGA banks. Up-to 3 banks are
connected to a proFPGA (V0) connector.

Table 6-41. EB-PDS-V3-SODIMM-R4 – Extension Board Operating Conditions

[DDR4]
[custom extension boards]
IO voltage provider FPGA module for FPGA Bank and DDR4
SODIMM connector
Top-side extension board connector yes – V3 / DDR4 SODIMM connector
Extension Boards

In the table below, (p) Tests for this connector pending
(1)
Tested with 64-bit dual rank 18ASF4G72HZ-3G2B1 / M471A4G43MB1-CTD and speed
(2) Tested
with 64-bit dual rank 18ASF4G72HZ-3G2B1 / M471A4G43MB1-CTD and speed
Compatibility
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1
FM-XCVU440-R2
FM-XCVU190-R1
FM-XCVU160-R1
FM-XCVU125-R1
Extension Boards

V1 V1
FM-XCVU095-R1
FM-XCVU080-R1
FM-XCKU115-R1
FM-XCVU5P-R1
FM-XCVU7P-R1
FM-XCVU9P-R1
FM-XCVU13P-R1
FM-XCVU19P-R1
FM-XCVU37P-R1
FM-XCVU47P-R1
FM-XCZU11EG-R2
FM-XCZU17EG-R2
FM-XCZU19EG-R2
FM-1SG280<L,H>-R1
FM-1SG280<L,H>-R2 (p) (p) (p) (p) (p) (p)
FM-10AX115-R1 (p) (p) (p) (p)
FM-1SG10M-R1

Table 6-43. EB-PDS-V3-SODIMM-R4 – FPGA Pin Constraints

all IO signals [custom <any> <any>
extension board on top]
all IO signals [DDR4] Refer to Intel EMIF example
design
Extension Boards
Related Work
Related Work

Caution
Please use 3.3 V LVDS as output type because the output driver is connected to 3.3 V. The
clock is dc-coupled. No other IO standard than LVDS should be chosen. Otherwise, the
FPGA could be damaged.
profpga_run
If the Si5338 is used, it will be configured with a profpga plugin. To load the plugin, the
...
plugin_list = ( "si5338 Siemens EB-PDS-V3-SODIMM-R4" );
{
...
...
"si5338 Siemens EB-PDS-V3-SODIMM-R4" );
{
...
<instance name>:
{
type = "BOARD";
vendor = "Siemens";
name = "EB-PDS-V3-SODIMM-R4";
size = "A1A1";
v_io_ba1 = "AUTO";
};
Extension Boards
Order Code
more information.<register map file> must be replaced with the path and the filename to the
register map file created with the Si5338 software.si5338_execute_plugin_async_event: A
"yes" for this option enables the ability for reconfiguration of the Si5338 clock generator during
runtime. The reconfiguration, based on the register map file, is triggered by the command line
option --plugin-async-events for profpga_run. Please refer to the „proFPGA Software

V3-SODIMM-R4”. The system configuration file can be created manually or with the
Order Code
Order code not yet available.
Extension Boards

DDR3-R2)
This topic is about DDR3 Extension Board with 2 Gbyte (EB-PDS-DDR3-R2)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
This topic is about is Functional Description.

• Two Gbyte of DDR3-1600 memory (4x Micron MT41J256M16-125 modules OR 4x
Micron MT41K256M16-107)
• 16 user LEDs
• Optional 200 MHz fixed reference clock (by default the clock generator is not placed on
the board)
Extension Boards
Memory data sheet:

• device name Micron MT41J256M16-125
• speed grade -125 (1600 MT/s)
• page size 2kB
Memory data sheet:

• device size Micron MT41K256M16-107
• speed grade -107 (1866 MT/s)
• page size 2kB
• target tRCD-tRP-CL(1866 MT/s) 13-13-13
• target tRCD-tRP-CL (1600MT/s) 11-11-11
Caution
The DDR3 memory devices MT41J256M16-125 were replaced because of component
discontinuation by the MT41K256M16-107. For maximum compatibility the boards with
the older and the newer DDR3 memory devices have the same name and can be replaced by
each other. Due to this and changes in the Vivado MIG from version 2.3 and higher, the
maximum recommended operating speed is 1500 MT/s. Please use the new verification designs
to validate your DDR3 hardware.


IO voltage (min... recommended...max) 1.425V...1.5V...1.575V
Extension Boards


For applications which uses their own memory controller (e.g. Rapid Prototyping of ASIC
FPGA technologies.
In the table below, (*) not useable with MIG/EMIF

V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
FM-XC7Z100-R1 √(*)
FM-XC7Z045-R1 √(*)
FM-XCVU440-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU440-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU190-R1 √(*) √(*) √(*)
FM-XCVU160-R1 √(*) √(*) √(*)
FM-XCVU125-R1 √(*) √(*) √(*)
Extension Boards

V1 V1
FM-XCVU095-R1 √(*) √(*) √(*)
FM-XCVU080-R1 √(*) √(*) √(*)
FM-XCKU115-R1 √(*) √(*) √(*)
FM-XCVU5P-R1 √(*) √(*) √(*)
FM-XCVU7P-R1 √(*) √(*) √(*)
FM-XCVU9P-R1 √(*) √(*) √(*)
FM-XCVU13P-R1 √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU37P-R1 √(*) √(*) √(*)
FM-XCVU47P-R1 √(*) √(*) √(*)
FM-1SG280<L,H>-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCZU19EG-R2 √(*) √(*) √(*)
FM-XCZU17EG-R2 √(*) √(*) √(*)
FM-XCZU11EG-R2 √(*) √(*)
FM-1SG280<L,H>-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-10AX115-R1 √(*) √(*) √(*) √(*)
FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)

FPGA TA0 TAB0 TB0 BA0 BAB0 BB0
Module
FM- √(*) √(*) √(*) √(*) √(*) √(*)
1SG10M-
R1
FM- √(*) √(*) √(*) √(*)
XCVU19P
-R1
Extension Boards
It is recommended to connect the board on one of the top-side connectors (TA1, TA2, TB1,
TB2) to achieve maximum signal integrity.It is not recommended to plug this board on top of
other stackable extension boards, because this will decrease signal integrity.


dq[*] IOSTANDARD =
SSTL15_T_DCIVCCAUX_
IO = HIGH
dqs_n[*] DIFF_SSTL15_T_DCIVCC
AUX_IO = HIGH
DIFF_SSTL15VCCAUX_I
O = HIGH
eodtcs_n SSTL15VCCAUX_IO =
HIGH
LVCMOS15
clk_200mhz,clk_200mhzn IOSTANDARD = LVDS
(optional, by default not
available)
Related Work
Extension Boards
Order Code
profpga_run
<instance name>:
{
type = “BOARD”;
size = “A1A1”;
top_connectors = ();
};

plugged onto.
Table 6-48. Specification
4Gb_DDR3_SDRAM.pdf Micron DDR3 memory module data
sheet
Order Code
286479
Extension Boards

DDR3-R3)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

• Four Gbyte of DDR3-1600 memory (4x Micron MT41K512M16TNA-125:E modules)
• 16 user LEDs
• Optional 200 MHz fixed reference clock (by default the clock generator is not placed on
the board)
Extension Boards
Memory data sheet:

• device name Micron MT41K512M16TNA-125
• memory organisation 64 bit x 512M x 2 ranks (4 x 16 bit x 512M x
2 ranks)
• speed grade -125(1600 MT/s)
• row addressing 32k(a[14:0])
• column addressing 1k(a[9:0])
• page size 2kB
Note
Some considorations apply if this board should be used with the XILINX DDR3 SDRAM
controller (MIG). XILINX Vivado does not have direct support for the
MT41K512M16TNA-125 device. Neverless, following there are instructions how to configure
the MIG IP to get this to work.
Extension Boards
Caution
The maximum throuput which can be achieved with a 7-Series FPGAs (speed grade 1) is
750MT/s. This was tested with the XILINX MIG 4.2 and Vivado 2018.3. The reasons for
this limit are:
• Due to the fact that this memory is a dual-rank chip the FPGA pin load is doubled.
Especially the load of the address and control signals increases from 4 to 8.
• The XILINX MIG does not really support dual-rank memories. For a full support the
SDRAM controller should train (read and write leveling) each rank separately and adjust
the I/O delays dynamically depends on which rank is currently being accessed. Instead
of the MIG only train on one rank and uses the delay values for both.
There is an example design $PROFPGA/hdl/demo_designs/EB-PDS-DDR3-R3.BIST which

demonstrates how to generate and use the XILINX MIG and which is dedicated to show the
maximum performance.
There are some issues with the MIG IP generator to propagate the SDRAM device parameters
correctly to the IP core. The following steps are recommended to generated and synthesize a
correct IP core:
1. Use profpga_brdgen to generate a MIG project file (e.g. mig.prj) which fits to your
FPGA module (see the sessions/bist.profpga_brdgen for more details). The project file
uses the MT41K1G8TRF-125 device to generate the core. Some parameters will be
asjusted later to make the core fully compatible to the MT41K512M16TNA-125. Also
this project file contains the pin locations constraints.
2. Generate the MIG IP using the following Tcl script (replace the FPGA part if different):
set FPGA_PART xc7v2000tflg1925-1
set IP_NAME ddr3_0
set MIG_PRJ_FILE "mig.prj"
create_project ip_syntesis -force
set_property part ${FPGA_PART} [current_project]
create_ip -name mig_7series -vendor xilinx.com -library ip \
-version 4.2 -module_name ${IP_NAME}
file copy ${MIG_PRJ_FILE}
ip_syntesis.srcs/sources_1/ip/${IP_NAME}/mig.prj
set_property -dict [list \
CONFIG.XML_INPUT_FILE {mig.prj} \
CONFIG.RESET_BOARD_INTERFACE {Custom} \
CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips
${IP_NAME}]
generate_target all [get_ips]
close_project
Extension Boards
3. Patch the generated MIG source files (the automatically patching via Tcl scripting is
demonstrated in the sessions/bist.vivado/generate_ip.tcl file):
./ip_syntesis.srcs/sources_1/ip/ddr3_0/
ddr3_0/user_design/rtl/ddr3_0.v
- change bit width of ddr3_addr to 14:0
- change bit width of app_add to 28:0
./ip_syntesis.srcs/sources_1/ip/ddr3_0/ddr3_0/user_design/rtl/
ddr3_0_mig.v
./ip_syntesis.srcs/sources_1/ip/ddr3_0/ddr3_0/user_design/rtl/
ddr3_0_mig_sim.v
- change value of parameter ROW_WIDTH to 15
- change value of parameter ADDR_WIDTH to 29
- change value of parameter MEM_SPEEDGRADE to "125"
- change value of parameter MEM_DEVICE_WIDTH to 16
- change value of parameter PHY_0_BITLANES to
48'h3FE_3FE_3FE_2FF
4. Synthezise the MIG together with the other design sources as shown in the sessions/
bist.vivado/vivado.tcl file.
By default the MIG core is generated for a input clock frequency of 375MHz (2.667ps clock
period). These values can be changed in the mig.prj file.


Note
Prior to 2019B this boards was ratet with a IO voltage of 1.35V. For higher performance
especially with the XILINX DDR3 SDRAM controller (MIG 4.2) the IO voltage was
changed to 1.5V. If your board is programmed for 1.35V operation, please contact the proFPGA
support to get instructions how to re-program it for 1.5V operation.

Extension Boards

FPGA technologies.
In the table below, (*) not usable with MIG/EMIF

V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
FM-XC7Z100-R1 √(*)
FM-XC7Z045-R1 √(*)
FM-XCVU440-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU440-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU190-R1 √(*) √(*) √(*)
FM-XCVU160-R1 √(*) √(*) √(*)
FM-XCVU125-R1 √(*) √(*) √(*)
FM-XCVU095-R1 √(*) √(*) √(*)
FM-XCVU080-R1 √(*) √(*) √(*)
Extension Boards

V1 V1
FM-XCKU115-R1 √(*) √(*) √(*)
FM-XCVU5P-R1 √(*) √(*) √(*)
FM-XCVU7P-R1 √(*) √(*) √(*)
FM-XCVU9P-R1 √(*) √(*) √(*)
FM-XCVU13P-R1 √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU37P-R1 √(*) √(*) √(*)
FM-XCVU47P-R1 √(*) √(*) √(*)
FM-1SG280<L,H>-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCZU19EG-R2 √(*) √(*) √(*)
FM-XCZU17EG-R2 √(*) √(*) √(*)
FM-XCZU11EG-R2 √(*) √(*)
FM-1SG280<L,H>-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-10AX115-R1 √(*) √(*) √(*) √(*)
FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)

FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*)
TB2) to achieve maximum signal integrity.
It is not recommended to plug this board on top of other stackable extension boards, because
this will decrease signal integrity.
Extension Boards


dq[*] IOSTANDARD =
SSTL15_T_DCI
VCCAUX_IO = HIGH
dqs_n[*] DIFF_SSTL15_T_DCI
VCCAUX_IO = HIGH
ck_p IOSTANDARD =
ck_n DIFF_SSTL15
VCCAUX_IO = HIGH
dm[*] IOSTANDARD = SSTL15
a[*] VCCAUX_IO = HIGH
ba[*]
ras_n
cas_n
cke
odt
cs_n
led[*] LVCMOS15
sw[*]
clk_200mhz, IOSTANDARD = LVDS
clk_200mhzn (optional, by default not
available)
Related Work
Extension Boards
Order Code
profpga_run
<instance name>:
{
type = “BOARD”;
size = “A1A1”;
};
system configuration. Please refer to the „proFPGA Software Reference Manual” [SWRM] for
more information.

plugged onto.
sheet
Order Code
286481
Extension Boards
DDR3 Extension Board with 4 Gbyte (EB-PDS-DDR3-R6/R7)

DDR3-R6/R7)
This topic is about DDR3 Extension Board with 4 Gbyte (EB-PDS-DDR3-R6/R7)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

• Four Gbyte of DDR3-1600 memory
• Three pushbuttons
• 16 user LEDs
Extension Boards
Memory data sheet for EB-PDS-DDR3-R6:

• device name ISSI IS43TR16512AL-125KBLI
• memory organisation 64 bit x 512M x 2 ranks (4 x 16 bit x 512M x
2 ranks)
• row addressing 32k(a[14:0])
• page size 2kB
Memory data sheet for EB-PDS-DDR3-R7:

• device name Micron MT41K512M16HA-125
• memory organisation 64 bit x 512M (4 x 16 bit x 64M x 8 banks x
1 rank)
• page size 2kB
Tip
please select the custom memory part and choose the ‘custom_mems.csv‘ file from the
$PROFPGA/hdl/demo_designs/EB-PDS-DDR3-R6/source/vivado/. With this file the memory
device ‘IS43TR16512AL-125KBLI’ must be chosen.
Once bitsteam is available the reference clock frequency must be set to 125MHz using the
si5338 register map file 125MHZ_CLK0.txt which can be found in the $PROFPGA/hdl/
demo_designs/EB-PDS-DDR3-R6/ready_to_run directory.

Extension Boards
Table 6-54. EB-PDS-DDR3-R6/R7– Extension Board Operating Conditions


This topic is about FPGA Extension Site Compatibility
requirements for the XILILNX Memory Interface Generator (MIG). The EB-PDS-DDR3-R6/
R7 is especially designed for met the MIG Constraints of the Xilinx Ultrascale architecture.
FPGA technologies.

Table 6-55. EB-PDS-DDR3-R6/R7 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
FM-XC7Z100-R1 √(*)
FM-XC7Z045-R1 √(*)
FM-XCVU440-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU440-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU190-R1 √(*) √(*) √(*)
FM-XCVU160-R1 √(*) √(*) √(*)
FM-XCVU125-R1 √(*) √(*) √(*)
Extension Boards
Table 6-55. EB-PDS-DDR3-R6/R7 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU080-R1 √(*) √(*) √(*)
FM-XCVU095-R1 √(*) √(*) √(*)
FM-XCKU115-R1 √(*) √(*) √(*)
FM-XCVU5P-R1 √(*) √(*) √(*)
FM-XCVU7P-R1 √(*) √(*) √(*)
FM-XCVU9P-R1 √(*) √(*) √(*)
FM-XCVU13P-R1 √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU37P-R1 √(*) √(*) √(*)
FM-XCVU47P-R1 √(*) √(*) √(*)
FM-1SG280<L,H>-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCZU19EG-R2 √(*) √(*) √(*)
FM-XCZU17EG-R2 √(*) √(*) √(*)
FM-XCZU11EG-R2 √(*) √(*)
FM-1SG280<L,H>-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-10AX115-R1 √(*) √(*) √(*) √(*)
FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
Table 6-56. EB-PDS-DDR3-R6/R7 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*)
Extension Boards


dq[*] IOSTANDARD =
SSTL15_T_DCI
VCCAUX_IO = HIGH
dqs_n[*] DIFF_SSTL15_T_DCI
VCCAUX_IO = HIGH
ck_p IOSTANDARD =
ck_n DIFF_SSTL15
VCCAUX_IO = HIGH
dm[*] IOSTANDARD = SSTL15
a[*] VCCAUX_IO = HIGH
ba[*]
ras_n
cas_n
cke
odt
cs_n
led[*] LVCMOS15
sw[*]
CLK_IN_P,CLK_IN_N IOSTANDARD = LVDS
Related Work

Extension Boards
Related Work
Note
Profpga_run
...
{
...
...
{
...
profpga_run
<instance name>:
{
type = “BOARD”;
size = “A1A1”;
};
more information.

Extension Boards
Order Code
information.

plugged onto.
sheet
Order Code
The EB-PDS-DDR3-R6 has been discontinued. Please consider the latest version of this
Memory board (EB-PDS-DDR3-R7) instead.
Extension Board Order Code
EB-PDS-DDR3-R7 289438 Veloce PF DDR3 SDRAM 4GB VU440 R2
Extension Boards
DDR3 SODIMM Board (EB-PDS-DDR3-SODIMM-R2)
DDR3 SODIMM Board (EB-PDS-DDR3-

SODIMM-R2)
This topic is about DDR3 SODIUM Board (EB-PDS-DDR3-SODIUMM-R2).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
This topic is about Functional Description
The EB-PDS-DDR3-SODIMM-R2 uses one site and provides the following.
• one SODIMM socket intended for DDR3 memory modules

• three pushbuttons with user definable function
• ten user LEDs
• two power good LEDs (red and green) indicating DDR3 VTT and VREF are stable
Figure 6-22. EB-PDS-DDR3-SODIMM-R2 Top View
Extension Boards

Table 6-59. EB-PDS-DDR3-R6/R7 – Extension Board Operating Conditions


requirements for the XILINX Memory Interface Generator (MIG). Therefore, if the XILNX

For applications that use their own memory controller (e.g. Rapid Prototyping of ASIC designs)
such constraints do not apply since the FPGA internal memory controller is not used. This
means for such applications all DDR3/DDR3 memory extension boards can be used on all
FPGA technologies.
In the table below, (*) Not compatible with MIG/EMIF

Table 6-60. EB-PDS-DDR3-SODIMM-R4 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
Extension Boards

V1 V1
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU440-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU190-R1 √(*) √(*) √(*)
FM-XCVU160-R1 √(*) √(*) √(*)
FM-XCVU125-R1 √(*) √(*) √(*)
FM-XCVU080-R1 √(*) √(*) √(*)
FM-XCVU095-R1 √(*) √(*) √(*)
FM-XCKU115-R1 √(*) √(*) √(*)
FM-XCVU5P-R1 √(*) √(*) √(*)
FM-XCVU7P-R1 √(*) √(*) √(*)
FM-XCVU9P-R1 √(*) √(*) √(*)
FM-XCVU13P-R1 √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU37P-R1 √(*) √(*) √(*)
FM-XCVU47P-R1 √(*) √(*) √(*)
FM-1SG280<L,H>-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCZU19EG-R2 √(*) √(*) √(*)
FM-XCZU17EG-R2 √(*) √(*) √(*)
FM-XCZU11EG-R2 √(*) √(*)
FM-1SG280<L,H>-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-10AX115-R1 √(*) √(*) √(*) √(*)
FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
Extension Boards
Table 6-61. EB-PDS-DDR3-SODIMM-R4 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*)

This topic is about Pin Constraints.

all IO signals IOSTANDARD =
LVCMOS15
Related Work
proFPGA_run
<instance name>:
{
type = “BOARD”;
name = „EB-PDS-DDR3-SODIMM-R2“;
size = “A1A1”;
};
more information.
Order Code
Extension Boards
Order Code
286477
Extension Boards
DDR3 SODIMM Board (EB-PDS-DDR3-SODIMM-R4)
DDR3 SODIMM Board (EB-PDS-DDR3-

SODIMM-R4)
This topic is about DDR3 SODIMM Board (EB-PDS-DDR3-SODIMM-R4).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
The EB-PDS-DDR3-SODIMM-R4 uses one site and provides the following.
• one SODIMM socket intended for DDR3 memory modules

• three push-buttons with user definable function
• ten user LEDs
• two power good LEDs (red and green) for DDR3 VTT and VREF
Extension Boards
Figure 6-23. EB-PDS-DDR3-SODIMM-R4 Top View

Table 6-62. EB-PDS-DDR3-SODIMM-R4 – Extension Board Operating

Conditions
Top-side extension board connector no

Extension Boards
requirements for the XILINX Memory Interface Generator (MIG). Therefore, if the XILNX

For applications that use their own memory controller (e.g. Rapid Prototyping of ASIC designs)
such constraints do not apply since the FPGA internal memory controller is not used. This
means for such applications all DDR3/DDR3 memory extension boards can be used on all
FPGA technologies.
In the table below, (*) Not compatible with MIG/EMIF

V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU440-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU190-R1 √(*) √(*) √(*)
FM-XCVU160-R1 √(*) √(*) √(*)
FM-XCVU125-R1 √(*) √(*) √(*)
FM-XCVU080-R1 √(*) √(*) √(*)
FM-XCVU095-R1 √(*) √(*) √(*)
Extension Boards

V1 V1
FM-XCKU115-R1 √(*) √(*) √(*)
FM-XCVU5P-R1 √(*) √(*) √(*)
FM-XCVU7P-R1 √(*) √(*) √(*)
FM-XCVU9P-R1 √(*) √(*) √(*)
FM-XCVU13P-R1 √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU37P-R1 √(*) √(*) √(*)
FM-XCVU47P-R1 √(*) √(*) √(*)
FM-1SG280<L,H>-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCZU19EG-R2 √(*) √(*) √(*)
FM-XCZU17EG-R2 √(*) √(*) √(*)
FM-XCZU11EG-R2 √(*) √(*)
FM-1SG280<L,H>-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-10AX115-R1 √(*) √(*) √(*) √(*)
FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
Table 6-64. EB-PDS-DDR3-SODIMM-R4 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*)

Extension Boards
Related Work

LVCMOS15
Related Work
profpga_run
<instance name>:
{
type = “BOARD”;
name = „EB-PDS-DDR3-SODIMM-R4“;
size = “A1A1”;
};
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-DDR3-SODIMM-
R4”. The system configuration file can be created manually or with the profpga_builder tool.
Order Code
No Order Code available.
Extension Boards
LPDDR2 Extension Board with 512 MByte (EB-PDS-LPDDR2-R1)
LPDDR2 Extension Board with 512 MByte (EB-

PDS-LPDDR2-R1)
This topic is about LPDDR2 Extension Board with 512 MByte

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
The LPDDR2 extension board provides:

• Four Gbit of LPDDR2-800 memory (2x Two Gbit Winbond W97BH2KBQX devices)
• Two SoftTouch Connectors
• Three push-buttons (active high)
• 16 user LEDs (active high)
Figure 6-24. EB-PDS-LPDDR2-R1 Overview
Extension Boards
Figure 6-25. EB-PDS-LPDDR2-R1 Schematic Diagram
Caution
Due to limitation of Xilinx MIG it is not possible to generate memory controller using both
memory devices. It can only be used to generate a controller for either device 1 or device 2.
If only one memory is used, MEM_CS_N and MEM_CKE of the unused device need to be
driven by the FPGA design where MEM_CS_N must be high and MEM_CKE low.
Memory data sheet:

• device Winbond W97BH2KBQX
name
• memory 32 bit x 64M
organisatio
n
• speed 800 Mb/s/pin
grade
There are two softtouch probe connectors at the board to make the memory signals available for
logic analyzer. The pinout of both connectors is shown below.
Table 6-65. Softtouch Probes Pinout
Pin name Pin Number Probe 1(X1) Probe 2(X2)
CK2N_Even/D11N B20 n.c. MEM_DQS_N2
CK2P_Even/D11P B21 n.c. MEM_DQS_P2
CK1N_Odd/D4N AB MEM_CK_N MEM_DQS_N0
CK1P_Odd/D4P A7 MEM_CK_P MEM_DQS_P0
Extension Boards
Table 6-65. Softtouch Probes Pinout (cont.)

D0_Even/CLKN B14 MEM_CA6 MEM_DQ20
D0_Odd/D0P A1 MEM_CKE0 MEM_DQ4
D1_Even/CLKP B15 n.c. MEM_DQ22
D1_Odd/D0N A2 n.c. MEM_DQ6
D2_Even/D8P A16 n.c. MEM_DQ18
D2_Odd/D1N B2 MEM_DM2 MEM_DQ2
D3_Even/D8N A17 n.c. MEM_DQ19
D3_Odd/D1P B3 MEM_DM3 MEM_DQ0
D4_Even/D9N B17 n.c. MEM_DQ16
D4_Odd/D2P A4 MEM_CS_N0 MEM_DQ3
D5_Even/D9P B18 n.c. MEM_DQ17
D5_Odd/D2N A5 MEM_CS_N1 MEM_DQ1
D6_Even/D10P A19 n.c. MEM_DQ21
D6_Odd/D3N B5 MEM_DM0 MEM_DQ7
D7_Even/D10N A20 n.c. MEM_DQ23
D7_Odd/D3P B6 MEM_DM1 MEM_DQ5
D8_Even/D12P A22 MEM_CA3 MEM_DQ24
D8_Odd/D5N B8 MEM_DQS_N3 MEM_DQ8
D9_Even/D12N A23 MEM_CA5 MEM_DQ25
D9_Odd/D5P B9 MEM_DQS_P3 MEM_DQ9
D10_Even/D13N B23 MEM_CA0 MEM_DQ26
D10_Odd/D6P A10 MEM_CKE1 MEM_DQ10
D11_Even/D13P B24 MEM_CA2 MEM_DQ27
D11_Odd/D6N A11 n.c. MEM_DQ11
D12_Even/D14P A25 MEM_CA8 MEM_DQ28
D12_Odd/D7N B11 MEM_DQS_N1 MEM_DQ12
D13_Even/D14N A26 MEM_CA7 MEM_DQ29
D13_Odd/D7P B12 MEM_DQS_P1 MEM_DQ13
D14_Even/D15N B26 MEM_CA9 MEM_DQ30
D14_Odd/NC A13 MEM_CA4 MEM_DQ14
Extension Boards
Table 6-65. Softtouch Probes Pinout (cont.)

D15_Even/D15P B27 n.c. MEM_DQ31
D15_Odd/NC A14 MEM_CA1 MEM_DQ15

This topic is about Extension Board C
Table 6-66. EB-PDS-LPDDR2-R1 – Extension Board Operating Conditions


Table 6-67. EB-PDS-LPDDR2-R1– FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
FM-XC7Z100-R1 √(*)
FM-XC7Z045-R1 √(*)
FM-XCVU440-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU440-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU190-R1 √(*) √(*) √(*)
FM-XCVU160-R1 √(*) √(*) √(*)
Extension Boards
Table 6-67. EB-PDS-LPDDR2-R1– FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU125-R1 √(*) √(*) √(*)
FM-XCVU095-R1 √(*) √(*) √(*)
FM-XCVU080-R1 √(*) √(*) √(*)
FM-XCKU115-R1 √(*) √(*) √(*)
FM-XCVU5P-R1 √(*) √(*) √(*)
FM-XCVU7P-R1 √(*) √(*) √(*)
FM-XCVU9P-R1 √(*) √(*) √(*)
FM-XCVU13P-R1 √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU37P-R1 √(*) √(*) √(*)
FM-XCVU47P-R1 √(*) √(*) √(*)
FM-1SG280<L,H>-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCZU19EG-R2 √(*) √(*) √(*)
FM-XCZU17EG-R2 √(*) √(*) √(*)
FM-XCZU11EG-R2 √(*) √(*)
FM-1SG280<L,H>-R2 √(*) √(*) √(*) √(*) √(*) √(*) √(*)
FM-10AX115-R1 √(*) √(*) √(*) √(*)
FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*) √(*) √(*)
Table 6-68. EB-PDS-LPDDR2-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU19P-R1 √(*) √(*) √(*) √(*)
Extension Boards

This topic is about FPGA Pin Constraints
Table 6-69. EB-PDS-LPDDR2-R1 FPGA Pin Constraints

MEM_DQ[*] IOSTANDARD =
MEM_CA[*] HSUL_12SLEW = FAST
MEM_DM[*] VCCAUX_IO = NORMAL

MEM_CKE[*]
MEM_CS_N[*]
MEM_DQS_P[*] IOSTANDARD =
MEM_DQS_N[*] DIFF_HSUL_12SLEW =
FASTVCCAUX_IO =
MEM_CK_P MEM_CK_N NORMAL
LED[*]SW[*] IOSTANDARD =
LVCMOS12 DRIVE=8
Related Work
profpga_run
<instance name>:
{
type = “BOARD”;
name = „EB-PDS-LPDDR2-R1“;
size = “A1A1”;
};
Extension Boards
Order Code
more information.

LPDDR2-R1”. The system configuration file can be created manually or with the
profpga_builder tool.Please refer to the „proFPGA Software Reference Manual” [SWRM] and
Order Code
286486
Extension Boards
LPDDR4 Extension Board with 2 Gbyte (EB-PDS-LPDDR4-R1)
LPDDR4 Extension Board with 2 Gbyte (EB-

PDS-LPDDR4-R1)
This topic is about LPDDR4 Extension Board with 2 Gbyte (EB-PDS-LPDDR4-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
This topic is about Functional description.
The LPDDR4 extension board provides:

• 2 Gbyte of LPDDR4-3200 memory (2x Samsung K4F8E304HB-MGCJ chips)
• 8 user LEDs
Extension Boards
Figure 6-26. EB-PDS-LPDDR4-R1
Figure 6-27. EB-PDS-LPDDR4-R1 Components

Extension Boards
Table 6-70. EB-PDS-LPDDR4-R1 – Extension Board Operating Conditions


This topic is about FPGA Extension Board.
Due to limitations of the IO voltage of the LPDDR4 memory (1.1 V) and the IO voltage
specification of the Xilinx Virtex 7 FPGAs it is not possible to use the board on Xilinx Virtex 7
FPGAs.
Table 6-71. EB-PDS-LPDDR4-R1 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √ √ √
FM-XCVU080-R1 √ √ √
FM-XCKU115-R1 √ √ √
FM-XCVU5P-R1 √ √ √
Extension Boards
Table 6-71. EB-PDS-LPDDR4-R1 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1
FM-XCZU19EG-R2 √ √ √
FM-XCZU11EG-R2 √ √
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1
Table 6-72. EB-PDS-LPDDR4-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1
FM-XCVU19P-R1 √ √ √ √

Extension Boards
Related Work
Table 6-73. EB-PDS-LPDDR4-R1 – FPGA Pin Constraints

dq[*] IOSTANDARD = HSUL_12
ca[*] (VCCO is set to 1.1 V, see
AR# 63305)
dmi[*]
cs
cke
odt
ck_c IOSTANDARD =
ck_t DIFF_HSUL12_DCI
(VCCO is set to 1.1 V, see
dqs[*]_c AR# 63305)
dqs[*]_t
led[*] LVCMOS11
sw[*]
Tip
Related Work
profpga_run
<instance name>:
{
type = “BOARD”;
name = "EB-PDS-LPDDR4-R1“;
size = “A1A1”;
};
more information.
Extension Boards
Order Code

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-LPDDR4-R1”. The
Order Code
This Extension Board has been discontinued.
Extension Boards
Multi Memory Board (EB-PDS-MULTIMEMORY-R1)
Multi Memory Board (EB-PDS-MULTIMEMORY-

R1)
This topic is about Multi-Memory Board (EB-PDS-MULTIMEMORY-R1)

Signal mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
The Multimemory Board provides 3 different types of memory with several debug
opportunities:
• 16 Mbit SRAM (CY62167EV18)

• 256 Kbit MRAM (MR256D08B)
• 512 Mb NOR Flash (JS28F512M29EWHA)
• 2x Buttons for debugging
• 4x LEDs (green, red, yellow, blue) for debugging
• 2x MICTOR Connectors for debugging
• DIP-SWITCH for changing Pull-Ups and -Downs for some address-pins
• Level shifters for operating independent from PVIO
Extension Boards
Figure 6-28. System overview Multimemory Board
Peripherals
Figure 6-29. 2x4 GPIO Header
Extension Boards
Signal mapping
Figure 6-30. MICTOR Connectors for Debugging
Signal mapping
This topic is about Signal mapping.
Table 6-74. Signal Mapping of Top Connector for EB-PDS-MULTIMEMORY-R1
Signal Class No. of Pins Connect

GND all GND pins are connected to the GND net
V3P3_AUX 1 power supply for I2C sub system
PV_IO 5 connected to top connectors
P12V 5 connected to top connectors
P3V3 2 connected to top connectors
I2C 2 IDPROM and I2C sub system
IO 95 IO_[147:053]
CLK_IO 1 x 8 Pairs CLK_IO_N[7:0], CLK_IO_P[7:0]
Extension Boards
Table 6-74. Signal Mapping of Top Connector for EB-PDS-MULTIMEMORY-R1

(cont.)
MGT 48 XEBB1.MGT_RX_N_i – XEBC1.MGT_TX_N_i
XEBB1.MGT_RX_P_i – XEBC1.MGT_TX_P_i
XEBB1.MGT_TX_N_i – XEBC1.MGT_RX_N_i
XEBB1.MGT_TX_P_i – XEBC1.MGT_RX_P_i
e.g.
XEBB1.MGT_RX_N_00 – XEBC1.MGT_TX_N_00
XEBB1.MGT_RX_P_00 – XEBC1.MGT_TX_P_00
XEBB1.MGT_RX_N_01 – XEBC1.MGT_TX_N_01
XEBB1.MGT_RX_P_01 – XEBC1.MGT_TX_P_01
…
Note: The wire length within each P/N-pair must match (+/-
1ps).
Note: These connections cannot be used on all FPGA
modules. There are dependencies on the number of
available MGT pins on each FPGA module connector.
All other pins not connected

Table 6-75. Multimemory Board Operation Conditions

IO voltage (min…recommended…max) 1.2V-3.3V
IO voltage provider FPGA module for FPGA Bank
Top-side extension board connector yes

Caution
Depends on the number of available I/Os on the FPGA module connectors some functions
on EB-PDS-MULTIMEMORY-R1 may be unconnected.
Extension Boards
Table 6-76. EB-PDS-MULTIMEMORY-R1 – FPGA Extension Site Compatibility

V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √
FM-XCVU125-R1 √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
FM-XCVU5P-R1 √ √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-XCZU19EG-R2 √ √ √ √ √
FM-XCZU17EG-R2 √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
Extension Boards
Related Work
Table 6-76. EB-PDS-MULTIMEMORY-R1 – FPGA Extension Site Compatibility

V1 V1
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-77. EB-PDS-MULTIMEMORY-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √
Related Work
Tis topic is about Related Work.
profpga_run
<instance name>:
{
type = “BOARD”;
name = “EB-PDS-FLASH-R1”;
size = “A1A1”;
};
<instance name>:
{
type = “BOARD”;
name = “EB-PDS-FLASH-R2”;
size = “A1A1”;
};
more information.
Extension Boards
Order Code

FLASH-R1” or “EB-PDS-FLASH-R2”. The system configuration file can be created manually
or with the profpga_builder tool.Please refer to the „proFPGA Software Reference Manual”
[UD002] and the “proFPGA Builder User Manual” [UD004] for more information.
Order Code
286490
Extension Boards
Flash Board (EB-PDS-FLASH-R1/R2/R3)
Flash Board (EB-PDS-FLASH-R1/R2/R3)

This topic is about Flash Board (EB-PDS-FLASH-R1/R2/R3).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
The flash board provides several different memory devices and several debug opportunities:
• 128 Gbit ONFI flash (MT29F128G08AMCDBJ5-6) at EB-PDS-FLASH-R1

• 256 Gbit ONFI flash (MT29F256G08CBCBBJ4-37) at EB-PDS-FLASH-R2
• 512 Gbit ONFI flash (MT29F512G08CMCEBJ4-37) at EB-PDS-FLASH-R3
• Debug interface for ONFI flash with 38-pin MICTOR connector
• 512 Mbit QSPI flash (S25FL512SAGMFI011 or S25FL512SAGMFIR10)
• 1 Mbit NVSRAM (CY14V101Q3)
• 1 Mbit quad SPI MRAM (MR10Q010SC)
• Debug interface for all SPI signals of all SPI devices listed previously
• Two I²C 64 kbit EEPROMs (AT24C64D-XHM-T)
• One debug interface for each I²C EEPROM
• I²C EEPROM address selection via DIP switch
• A15 Dstream connector
• PMBus header
• Three UART headers
• One heartbeat LED
• Three debug LEDs
Extension Boards
• One push button

• Debug header with 4 IO signals connected with pull-ups and the possibility to assemble
jumpers to set a low input signal
• Debug header with 8 IO signals connected with pull-ups, the possibility to assemble
pull-downs and the possibility to assemble jumpers to set a low input signal.
Additionally green LEDs are connected to each GPIO line.
Figure 6-31. proFPGA PROF-A-M-ONFL
Peripherals
• ONFI debug connector

o The operating voltage is fixed to 1.8 V.
Note
Be careful by connecting external peripherals here. Voltages higher than 1.8 V
will permanently damage the ONFI flash.
o The pin assignment can be seen in Figure 6-32.
Extension Boards
Figure 6-32. Pin Assignment of the ONFI Debug Connector (MICTOR-38)
• SPI debug
o Is connected to the common SPI interface where the quad SPI flash, quad SPI
MRAM and the NVSRAM is connected.
o The operating voltage is PV_IO.
Caution
Be careful when connecting external peripherals here. Voltages higher than
PV_IO will permanently damage the FPGA.

Figure 6-33. Pin Assignment of the SPI Debug Header
• The heartbeat LED is controlled by FPGA. A high signal at the output pin of the FPGA
means the blue LED is on. A low signal will turn off the LED.
• I²C debug
o Is connected to the I²C interface of each EEPROM.
o The pin assignment can be seen in Figure 6-34. It is identical for both connectors.
Extension Boards
Figure 6-34. Pin Assignment of the I²C Debug Header
• I²C EEPROM addressing

o Is connected to the address pins of both I²C EEPROMs.
o The signal assignment can be seen in Figure 6-35.
Figure 6-35. Pin Assignment of DIP Switch to Adjust the I²C Address
• UART headers (can also be used as user defined headers, RX and TX is dependent on
the FPGA settings)
o Is directly connected to FPGA pins.
Note
Be careful by connecting external peripherals here. Voltages higher than PV_IO
will permanently damage the FPGA.

Figure 6-36. Pin Assignment of the UART Headers
• The three debug LEDs (1 red LED, 2 green LEDs) are controlled by FPGA. A high
signal at the output pin of the FPGA means the LED is on. A low signal will turn of the
LED.
• PMBus header (can also be used as user defined header)
Extension Boards

o Pins are pulled high.
Caution

Figure 6-37. Pin Assignment of the PMBus Header
• Debug header
o Each pin can be set in input mode to low with a jumper.
Caution
Extension Boards
Figure 6-38. Pin Assignment of the Debug Header
• Push button
o The signal of the push button (DBG_PB) is normally pulled high and low if the
button is pressed.
• A15 Dstream connector
Note

Figure 6-39. Pin Assignment of the A15 Dstream Connector
• GPIO header
Extension Boards

o The pins can be manually pulled low be disassembling the pull-up resistor (R101 ..
R108) and assembling the pull-down (R109 .. R116) resistor.
o Each signal is connected to an LED.
o Each pin can be set in input mode to low with a jumper.
Note

Figure 6-40. Pin Assignment of the GPIO Header
Devices
• ONFI flash: MT29F128G08AMCDBJ5-6 at EB-PDS-FLASH-R1

MT29F256G08CBCBBJ4-37 at EB-PDS-FLASH-R2
o The voltage level of the ONFI flash is fixed to the voltage level mentioned in the
data sheet. Therefore, it is connected with bidirectional level shifters
(TXB0108RGYR) to the FPGA. So, operating with different PV_IO voltage levels
is possible. The maximum operating speed depends on the level shifters. For PV_IO
= 1.8 V, it is 52 MBPS. For PV_IO = 2.5 V and PV_IO = 3.3 V, it is 60 MBPS.
Extension Boards
Figure 6-41. Pin Assignment of the ONFI Flash
Table 6-78. EB-PDS-FLASH-R1/R2 – ONFI Pin Assignments

ONFI Flash signal Connection proFPGA connector
ONFI_ALE_0 IO_000
ONFI_nCE0_0 IO_001
ONFI_nCE1_0 IO_002
ONFI_CLE_0 IO_003
ONFI_DQ[0..7]_0 IO_004..IO_011
ONFI_DQS_0_t IO_012
Extension Boards
Table 6-78. EB-PDS-FLASH-R1/R2 – ONFI Pin Assignments (cont.)

ONFI Flash signal Connection proFPGA connector
ONFI_DQS_0_c IO_013
ONFI_nRE_W_nR_0 IO_014
ONFI_RE_0_c IO_015
ONFI_nWE_CLK_0 IO_016
ONFI_nWP_0 IO_017
ONFI_R_nB0_0 IO_018
ONFI_R_nB1_0 IO_019
ONFI_ALE_1 IO_020
ONFI_nCE0_1 IO_021
ONFI_nCE1_1 IO_022
ONFI_CLE_1 IO_023
ONFI_DQ[0..7]_1 IO_024..IO_031
ONFI_DQS_1_t IO_032
ONFI_DQS_1_c IO_033
ONFI_nRE_W_nR_1 IO_034
ONFI_RE_1_c IO_035
ONFI_nWE_CLK_1 IO_036
ONFI_nWP_1 IO_037
ONFI_R_nB0_1 IO_038
ONFI_R_nB1_1 IO_039
• QSPI flash:
o S25FL512SAGMFI011 at EB-PDS-FLASH-R1
o S25FL512SAGMFIR10 at EB-PDS-FLASH-R2
Extension Boards
Figure 6-42. Pin Assignment of QSPI Flash
Table 6-79. EB-PDS-FLASH-R1/R2 – QSPI Pin Assignments

SPI Flash signal name proFPGA net name Connection proFPGA
connector
SCK SPI_SCLK IO_058
SI/IO0 SPI_SI IO_050
SO/IO1 SPI_IO1 IO_051
nWP/IO2 SPI_IO2 IO_052
nHOLD/IO3 SPI_IO3 IO_053
nCS SPI_CS0 IO_054
nRESET SPI_RST IO_057
• 1 Mbit NVSRAM (CY14V101Q3)

Figure 6-43. Pin Assignment of NVSRAM
Table 6-80. EB-PDS-FLASH-R1/R2/R3 – NVSRAM Pin Assignments

MRAM signal name proFPGA net name Connection proFPGA
connector
SCK SPI_SCLK IO_058
SI SPI_SI IO_050
Extension Boards
Table 6-80. EB-PDS-FLASH-R1/R2/R3 – NVSRAM Pin Assignments (cont.)

connector
SO SPI_IO1 IO_051
nWP SPI_IO2 IO_052
nHOLD SPI_IO3 IO_053
nCS SPI_CS1 IO_055
nHSB PV_IO -
• 1 Mbit quad SPI MRAM (MR10Q010SC)
Figure 6-44. Pin Assignment of MRAM
• 2 x 64kb EEPROM (AT24C64D-XHM-T)

Figure 6-45. EEPROMs
Table 6-81. EB-PDS-FLASH-R1/R2/R3 – MRAM Pin Assignments

connector
SCK SPI_SCLK IO_058
SI/100 SPI_SI IO_050
SO/IO1 SPI_IO1 IO_051
nWP/IO2 SPI_IO2 IO_052
nHOLD/IO3 SPI_IO3 IO_053
nCS SPI_CS2 IO_055
Extension Boards
Note
The signals WP, HOLD, CS and RESET are low active.

Table 6-82. EB-PDS-FLASH-R1/R2/R3 – Extension Board Operating

Conditions

In the table below, (a) debug headers are not available,
(b) without
GPIO 6 and GPIO 7
Table 6-83. EB-PDS-FLASH-R1/R2/R3 – FPGA extension site compatibility
V1 V1
FM-C7V2000T-R1 √ √ √ √ √ √ √
FM-C7V2000T-R2 √ √ √ √ √ √ √
FM-C7V330T-R3 √ √ √
FM-C7V485T-R3 √ √ √
FM-C7V585T-R3 √ √(a) √ √ √
FM-C7V690T-R3 √ √(a) √ √ √
FM-C7Z100-R1 √(b) √
FM-C7Z045-R1 √(b) √
FM-CVU440-R1 √ √ √ √ √ √ √ √
FM-CVU440-R2 √ √ √ √ √ √ √ √
FM-CVU190-R1 √ √ √ √(a)
Extension Boards
Table 6-83. EB-PDS-FLASH-R1/R2/R3 – FPGA extension site compatibility

V1 V1
FM-CVU160-R1 √ √ √ √(a)
FM-CVU125-R1 √ √ √ √(a)
FM-CVU095-R1 √ √ √ √(a)
FM-CVU080-R1 √ √ √ √(a)
FM-CKU115-R1 √ √ √ √(a)
FM-CVU5P-R1 √ √ √ √(a)
FM-CVU7P-R1 √ √ √ √(a)
FM-CVU9P-R1 √ √ √ √(a)
FM-CVU13P-R1 √ √ √ √
FM-CVU19P-R1 √ √ √ √ √ √ √ √
FM-CVU37P-R1 √ √ √
FM-CVU47P-R1 √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √
FM-CZU19EG-R2 √ √ √
FM-CZU17EG-R2 √ √ √
FM-CZU11EG-R2 √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10A115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-84. EB-PDS-MULTIMEMORY-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Extension Boards
Related Work
Table 6-85. EB-PDS-FLASH-R1/R2/R3 – FPGA Pin Constraints

LVCMOS18
Related Work
This topic is about Related
profpga_run
<instance name>:
{
type = "BOARD";
vendor = "ProDesign";
name = "EB-PDS-FLASH-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
<instance name>:
{
type = "BOARD";
size = "A1A1";
v_io_ba1 = "AUTO";
};
<instance name>:
{
type = "BOARD";
vendor = "Siemens";
size = "A1A1";
v_io_ba1 = "AUTO";
};
system configuration. Please refer to the “proFPGA Software Reference Manual" [SWRM] for
more information.
Extension Boards
Order Code

plugged onto.
contains a valid x-board entry using the extension board name "EB-PDS-FLASH-R1", "EB-
PDS-FLASH-R2" or "EB-PDS-FLASH-R3". The system configuration file can be created
manually or with the profpga_builder tool.
Please refer to the “proFPGA Software Reference Manual" [UD002] and the "proFPGA Builder
User Manual" [UD004] for more information.
Order Code

EB-PDS-FLASH-R1 286475
Extension Boards
Single MCP HyperBus Flash/RAM Board (EB-PDS-HYPER-RAM-FLASH-R1)
Single MCP HyperBus Flash/RAM Board (EB-

PDS-HYPER-RAM-FLASH-R1)
This topic is about Single MCP HyperBus Flash/RAM Board (EB-PDS-HYPER-RAM-
FLASH-R1 )

HyperBus Memory S71KS512SC0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Pin Mapping of XEBA1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
The EB-PDS-HYPER-RAM-FLASH-R1 delivers a JESD251A conformal interface for the
MCP HyperBus device S71KS512SC0, containing a HyperRAM and HyprFlash chip within the
same 24-FBGA package and connected to an octal SPI data interface.
• One proFPGA bottom connector for connection to the proFPGA system.

• One proFPGA top connector to make all unused regular IOs and MGTs of the bottom
connector available for further use (e.g., to connect a cable for interconnections to other
FPGA)
• One IDPROM for board identification
• One JESD251A conformal 24-FBGA primary socket for xSPI flash devices with 1.8V
supply voltage support only (populated with S71KS512SC0 per default)
• One JESD251A conformal 24-FBGA secondary socket for xSPI flash devices with 1.8V
supply voltage support only (not populated per default)
• xSPI devices are powered from the proFPGA conformal PV_IO rail as delivered by
bottom connector
• S71KS512SC0 – HyperRAM: 64Mbit, 8Bit Data, 166MHz DDR, 333Mbit/s
• S71KS512SC0 – HyperFlash: 512Mbit, 8Bit Data, 166MHz DDR, 333Mbit/s
Extension Boards
Figure 6-46. EB-PDS-HYPER-RAM-FLASH-R1

Table 6-86. EB-PDS-HYPER-RAM-FLASH-R1 - Extension Board Operating

Conditions
IO voltage provider FPGA module for FPGA Bank and
extension board
Top-side extension board connector Yes

The following compatibility listing only contains the valid connectors for an exclusive usage of
the primary xSPI FBGA socket. The functionality of the secondary socket is beyond the scope
of the EB-PDS-HYPER-RAM-FLASH-R1.
Nethertheless, as long as the common DQ/DQS distribution among the I/O banks is respected
on the FPGA module side and the first 36 pins (IO_[000:035]) of the proFPGA connectors are
connected to FPGA pins, the secondary socket should be valid as well.
Table 6-87. EB-PDS-HYPER-RAM-FLASH-R1 - FPGA Extension Site
Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √
Extension Boards
Table 6-87. EB-PDS-HYPER-RAM-FLASH-R1 - FPGA Extension Site

V1 V1
FM-XC7VX330T-R3 √ √ √ √ √
FM-XC7VX485T-R3 √ √ √ √ √ √
FM-XC7V585T-R3 √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √
FM-XCVU125-R1 √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
FM-XCVU13P-R1 √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Extension Boards
Table 6-88. EB-PDS-HYPER-RAM-FLASH-R1 FPGA Extension Site

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Table 6-89. EB-PDS-HYPER-RAM-FLASH-R1 FPGA Pin-Constraints

all IO signals IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
MGT/XCVR IO_STANDARD "HIGH
SPEED DIFFERENTIAL I/
O"
MGT/XCVR REFCLK IO_STANDARD “LVDS”
Functional Block Diagram

This topic is about Functional Block Diagram.
Whereas the EB-PDS-HYPER-RAM-FLASH-R1 delivers 2 identical 24-FBGA conformal
sockets, only the so-called primary socket is populated by default. The overall system structure
is shown in , consisting of the xSPI interfaces, as well as the proFPGA specific infrastructure.
Extension Boards
HyperBus Memory S71KS512SC0
Figure 6-47. EB-PDS-HYPER-RAM-FLASH-R1 – fUnctional Diagram

This topic is about HyperBus Memory S71KS512SC0
The standard assembly option of the EB-PDS-HYPER-RAM-FLASH-R1 is the S71KS512SC0,
which consists of a so called HyperRAM and HyperFlash chip within the same package. Based
on an octal xSPI data bus and some sideband signals, the S71KS512SC0 delivers a HyperBus
interface to the proFPGA ecosystem.
Extension Boards
According to the internal structure of the S71KS512SC0 as shown in Figure 173, both chips can
be accessed individually via separated low-active CS signals. This allows to use the flash and
RAM chips in a combined multiplexed operation mode, as well as in a stand-alone mode. An
appropriate IP/HDL design acting as the master in any of the previously described operation
modes is mandatory.
One should note, that S71KS512SC0 only supports 1.8V on both VCC and VCCQ supply rails,
making the EB-PDS-HYPER-RAM-FLASH-R1 incompatible with 3.3V flash memories. The
supply voltage to be used by the proFPGA system is defined based on the IDPROM
configuration.
Table 6-90. EB-PDS-HYPER-RAM-FLASH-R1 MCP Hyperbus Memory
Manufacturer Description Mounting Order Code
Cypress FLASH, DRAM 24-FBGA S71KS512SC0BHV
Semiconductor Memory IC 512Mbit 00x
Flash, 64Mbit RAM
Parallel 166MHz
Figure 6-48. S71KS512SC0 - MCP HyperBus RAM/Flash memory
Extension Boards
Pin Mapping of XEBA1 Connector
Pin Mapping of XEBA1 Connector

This topic is about Pin Mapping of XEBA1 Connector.
The I/Os and clock I/Os building the HyperBus conformal interface are routed to the XEBA1
connector in a way, that the typical DQ/DQS mapping scheme of the proFPGA FM modules is
considered as far as possible.
Table 6-91. EB-PDS-HYPER-RAM-FLASH-R1 XEBA1 HyperBus Pinout
Signal Name Pin Number proFPGA Pin Name on
XEBA1 Connector
XSPI_0_IO0_DQ0 242 IO_000_N_00
XSPI_0_IO1_DQ1 252 IO_001_P_00
XSPI_0_IO2_DQ2 233 IO_002_N_01
XSPI_0_IO3_DQ3 243 IO_003_P_01
XSPI_0_IO4_DQ4 227 IO_004_N_02
XSPI_0_IO5_DQ5 237 IO_005_P_02
XSPI_0_IO6_DQ6 224 IO_006_N_03
XSPI_0_IO7_DQ7 234 IO_007_P_03
XSPI_0_CS1_N 221 IO_008_N_04
XSPI_0_DS_RWDS 231 IO_009_P_04
XSPI_0_CK_N 218 IO_010_N_05
XSPI_0_CK_P 228 IO_011_P_05
XSPI_1_IO0_DQ0 215 IO_012_N_06
XSPI_1_IO1_DQ1 225 IO_013_P_06
XSPI_1_IO2_DQ2 212 IO_014_N_07
XSPI_1_IO3_DQ3 222 IO_015_P_07
XSPI_1_IO4_DQ4 209 IO_016_N_08
XSPI_1_IO5_DQ5 219 IO_017_P_08
XSPI_1_IO6_DQ6 206 IO_018_N_09
XSPI_1_IO7_DQ7 216 IO_019_P_09
XSPI_1_CS1_N 203 IO_020_N_10
XSPI_1_DS_RWDS 213 IO_021_P_10
XSPI_1_CK_N 200 IO_022_N_11
XSPI_1_CK_P 210 IO_023_P_11
Extension Boards
Related Work
Table 6-91. EB-PDS-HYPER-RAM-FLASH-R1 XEBA1 HyperBus Pinout (cont.)

Signal Name Pin Number proFPGA Pin Name on
XEBA1 Connector
XSPI_0_RESET_N 197 IO_024_N_12
XSPI_0_CS2_N 207 IO_025_P_12
XSPI_0_RSTO_N 194 IO_026_N_13
XSPI_0_INT_ECS_N 204 IO_027_P_13
XSPI_0_WP_N 191 IO_028_N_14
XSPI_0_RFU_B5 201 IO_029_P_14
XSPI_1_RESET_N 188 IO_030_N_15
XSPI_1_CS2_N 198 IO_031_P_15
XSPI_1_RSTO_N 185 IO_032_N_16
XSPI_1_INT_ECS_N 195 IO_033_P_16
XSPI_1_WP_N 182 IO_034_N_17
XSPI_1_RFU_B5 192 IO_035_P_17
Concerning the MGTs and their corresponding reference clocks, the EB-PDS-HYPER-RAM-
FLASH-R1 can be used transparently. The unused I/Os are rooted to the proFPGA top
connector, based on the mapping scheme given by the “Extension Board Design Guide”
[UD003].
Related Work
profpga_run
<instance name>:
{
type = “BOARD”;
name = “ EB-PDS-HYPER-RAM-FLASH-R1”;
size = “A1A1”;
top_connectors = (“TA1”);
};
Extension Boards
Order Code
more information.

HYPER-RAM-FLASH-R1”. The system configuration file can be created manually or with the
Order Code
No order code available.
Extension Boards
Triple SSRAM Board (EB-PDS-SRAM-R1/R2)
Triple SSRAM Board (EB-PDS-SRAM-R1/R2)

This topic is about Triple SSRAM Board (EB-PDS-SRAM-R1/R2)

SSRAM Assembly Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
The EB-PDS-SRAM board has one proFPGA bottom connector. Since it uses all I/Os there is
no proFPGA top connector. It provides fast and flexible memory expansion to the user FPGAs.
• A1A1 sized proFPGA extension board

• Possible SRAM types
o EB-PDS-SRAM-R1: 3x CY7C1518KV18-250BZXC (500Mbit/s)
o EB-PDS-SRAM-R2: 3x CY7C1618KV18-333BZXC (666Mbit/s)
• 18 bit wide data bus
• 250 MHz or 333 MHz (depending on assembled SRAM type)
• 72 Mbit or 144 Mbit memory depth per SRAM (depending on assembled SRAM type)
• 5 Debugging LEDs
Extension Boards
Figure 6-49. EB-PDS-SRAM-R1/2

Table 6-92. EB-PDS-SRAM-R1/2 – Extension Board Operating Conditions

Top-side extension board connector No

In the table below, (a) only SRAM1 available,
(b) LEDs don’t work

Table 6-93. EB-PDS-SRAM-R1/2 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √
Extension Boards
Table 6-93. EB-PDS-SRAM-R1/2 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XC7Z100-R1 √(a,b √(a,b
) )
FM-XC7Z045-R1 √(a,b √(a,b

) )
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √ √ √
FM-XCVU080-R1 √ √ √
FM-XCKU115-R1 √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1
FM-1SG280<L,H>-R2
FM-10AX115-R1
Extension Boards
Table 6-94. EB-PDS-SRAM-R1/2 – FPGA Extension Site Compatibility,

Module
FM-
1SG10M-
R1
FM- √ √ √ √
XCVU19P
-R1

Table 6-95. EB-PDS-SRAM-R1-FPGA Pin Constraints

all IO signals LVCMOS15

Extension Boards
SSRAM Assembly Options
Figure 6-50. EB-PDS-SRAM-R1 Functional Block Diagram
This Extension Board features three synchronous SRAMs connected in parallel to the proFPGA
connector. For maximum flexibility no signals are shared between devices. Thus each SRAM
can be used standalone which gives three 144 Mbit (72 Mbit) memories with an 18 bit wide data
bus. They can also be combined for maximum bandwidth with up to 54 bit data bus width
depending on the actual SRAM controller implementation in the FPGA.
SSRAM Assembly Options

This topic is about SSRAM Assembly Options.
The memory devices listed below are compatible with the EB-PDS-SRAM Extension Board.
Table 6-96. EB-PDS-SRAM Compatible SSRAM Devices
Cypress 72 Mbit DDR II 165-FBGA CY7C1518KV18-
SRAM Two-Word 250BZXC
Burst
Architecture250
MHz
Extension Boards
Related Work
Table 6-96. EB-PDS-SRAM Compatible SSRAM Devices (cont.)

Cypress 144 Mbit DDR II 165-FBGA CY7C1618KV18-
SRAM Two-Word 333BZXC
Burst
Architecture333
MHz
Related Work
profpga_run
<instance name>:
{
type = “BOARD”;
name = “ EB-PDS-SRAM-R1”;
size = “A1”;
};
more information.

SRAM-R1/R2”. The system configuration file can be created manually or with the
Order Code
Extension Boards
Order Code

EB-PDS-SRAM-R2 286488
Extension Boards
PCIe gen1 8-lane Kit (EB-PDS-PCIe-Cable-R2)

This topic is about PCIe gen1 8-lane Kit (EB-PDS-PCIe-Cable-R2)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
proFPGA PCIe Kit provides up to 8 lanes gen1 PCIe communication interface between PC and
FPGA Module to implement a PCIe downstream system at the proFPGA system. All unused
FPGA Module pins are routed to top side connector and are available for user applications.
The kit consists of:
• proFPGA PCIe gen1 8-lane daughter card, which will be plugged on a free extension
site of the proFPGA FPGA Module, which provides the required high speed serial
transceivers (MGTs)
• PCIe gen1 8-lane host interface card
• Dedicated high performance cable
Figure 6-51. proFPGA PCIe gen1 8-lane Kit (Host Interface Board, PCIe Cable,
EB-PDS-PCIe-Cable-R2 proFPGA Extension Board)
The beneath figure shows the pin assignment of the external PCIe connector. All sideband
signals are decoupled from the host system via optocouplers (Figure 6-53 on page 426).
Extension Boards
Figure 6-52. EB-PDS-PCIe-Cable-R2 - PCIe Connector Pin Assignment
Figure 6-53. EB-PDS-PCIe-Cable-R2 - Sideband Signals

Extension Boards
Table 6-97. EB-PDS-PCIE-Cable-R2 – Extension Board Operating Conditions


In the table below, (*) not officially supported by Xilinx Integrated Block for PCI Express or not
supported with all lanes
(**) Arria
10 PCIe Hard IP is not supported
Table 6-98. EB-PDS-PCIE-Cable-R2 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √
FM-XC7V2000T-R2 √ √
FM-XC7VX330T-R3 √(*) √(*) √(*)
FM-XC7VX485T-R3 √(*) √(*) √(*)
FM-XC7V585T-R3 √(*) √ √(*) √(*)
FM-XC7VX690T-R3 √(*) √ √(*) √(*)
FM-XC7Z100-R1 √(*) √
FM-XC7Z045-R1 √(*) √
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU160-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU125-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU095-R1 √(*) √(*) √(*) √(*) √(*) √(*)
FM-XCVU080-R1 √(*) √(*) √(*) √ √(*) √
FM-XCKU115-R1 √(*) √(*) √ √ √ √
Extension Boards

V1 V1
FM-XCVU5P-R1 √(*) √(*) √ √ √ √
FM-XCVU7P-R1 √(*) √(*) √ √ √ √
FM-XCVU9P-R1 √(*) √(*) √ √ √ √
FM-XCVU13P-R1 √(*) √(*) √
FM-XCVU19P-R1 √ √
FM-1SG280<L,H>-R1 √
FM-XCZU19EG-R2 √ √ √(*)
FM-XCZU17EG-R2 √ √ √(*)
FM-XCZU11EG-R2 √ √ √(*)
FM-1SG280<L,H>-R2 √
FM-10AX115-R1 √(**) √(**) √(**) √(**)
FM-1SG10M-R1 √ √ √ √
Table 6-99. EB-PDS-PCIE-Cable-R2 – FPGA Extension Site Compatibility,

Module
FM-
1SG10M-
R1
FM- √ √
XCVU19P
-R1
Note
Please refer to AN037 for further information on using the Xilinx Integrated Block for PCI
Express.
Extension Boards

Note
Please refer to “proFPGA Extension Board Design Guide” [UD003] for information about
MGT placement constraints depending on FPGA module type and connector position.
Table 6-100. EB-PDS-PCIE-Cable-R2 – FPGA Pin Constraints

(P1V8_)nCPERST IOSTANDARD =
LVCMOS18
(P1V8_)nCWAKE IOSTANDARD =
LVCMOS18
(P1V8_)nCPRSNT IOSTANDARD =
LVCMOS18
(P1V8_)CPWRON IOSTANDARD =
LVCMOS18
Top-side extension board connector

This topic is about Top-side extension board connector.
Top side extension connector provides pin unused by daughter card with following mapping:
MGT Pins:
Table 6-101. EB-PDS-PCIE-Cable-R2 - Top Connector Pin Mapping of MGT
pins
Top connector Bottom connector / FPGA Module
MGT_REFCLK_<N,P>_0 MGT_REFCLK_<N,P>_1
MGT_<RX,TX>_<N,P>_00 MGT_<RX,TX>_<N,P>_08
IO_000 IO_004
Extension Boards
Related Work

pins (cont.)
IO_001 IO_005
... ...
IO_143 IO_147
CLK_IO_<N,P>_0 CLK_IO_<N,P>_0
... …
Related Work
profpga_run
<instance name>:
{
type = “BOARD”;
name = “EB-PDS-PCIe-Cable-R2”;
size = “A1A1”;
};
more information.

PCIe-Cable-R2”. The system configuration file can be created manually or with the
Extension Boards
Order Code
Demo Designs

fmxc7v2000tr2_pciecore Siemens PCIe reference design for
FM-XC7V2000T-R2
Order Code
286520 (EB-PDS-PCIe-Cable-R2, 3m PCIe Cable, PCIe gen1, 8-lane host interface card)
Extension Boards
PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R2/R3)
PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R2/

R3)
This topic is about PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R2/R3)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Redriver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
transceivers (MGTs)
Extension Boards
Figure 6-54. proFPGA PCIe gen3 8-lane Kit (Host Interface Board, PCIe Cable,
There are two different kits available. One kit is dedicated to XILINX FPGA which identifies
itself as EB-PDS-PCIe_Cable-R3. The second kit is specific to all INTEL Arria-10 and Stratix-
10 FPGAs which identifies itself as EB-PDS-PCIe_Cable-R2.
Figure 6-55 shows the pin assignment of the external PCIe connector. All sideband signals are
decoupled from the host system via optocouplers (Figure 6-56).
Caution
The EB-PDS-PCIe-Cable-R3 extension board contained in the proFPGA PCIe gen3 8-lane
Kit for Xilinx is no longer available for new orders. It has been replaced by EB-PDS-PCIe-
Cable-R5. Please refer to chapter PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R5)for more
information.
Extension Boards
Extension Boards
Peripherals
• The LED D1 (silkscreen nCPERST) signals the reset signal of the PCIe port. On means,
the reset is active and the FPGA is an off-state. Off means, the reset is not active. The
signal is driven by the PCIe host.
• The LED D3 (silkscreen nCPRSNT) signals the present signal of the PCIe port. On
means, the present signal is on. Off means, the present signal is off. The signal is driven
by the FPGA and is therefore an output of the FPGA. It has to be driven low and then the
LED is on.
• The DIP switches do not have to be changed. They are set in the factory.



Extension Boards

V1 V1
FM-XC7V2000T-R1 √ √
FM-XC7V2000T-R2 √ √
FM-XC7VX330T-R3 √(*) √(*) √(*)
FM-XC7VX485T-R3 √(*) √(*) √(*)
FM-XC7V585T-R3 √(*) √ √(*) √(*)
FM-XC7VX690T-R3 √(*) √ √(*) √(*)
FM-XC7Z100-R1 √(*) √
FM-XC7Z045-R1 √(*) √
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU160-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU125-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU095-R1 √(*) √(*) √(*) √(*) √(*) √
FM-XCVU080-R1 √(*) √(*) √(*) √ √(*) √
FM-XCKU115-R1 √(*) √(*) √ √ √ √
FM-XCVU5P-R1 √(*) √(*) √ √ √ √
FM-XCVU7P-R1 √(*) √(*) √ √ √ √
FM-XCVU9P-R1 √(*) √(*) √ √ √ √
FM-XCVU13P-R1 √(*) √(*)
FM-XCZU19EG-R2 √ √ √(*)
FM-XCZU17EG-R2 √ √ √(*)
FM-XCZU11EG-R2 √ √ √(*)
Extension Boards

Module
FM- √ √
XCVU19P
-R1
In the table below, (**) Arria 10 PCIe Hard IP is not supported

V1 V1
FM-1SG280<L,H>-R1 √
FM-1SG280<L,H>-R2 √
FM-10AX115-R1 √(**) √(**) √(**) √(**)
FM-1SG10M-R1 √ √ √ √

FM-1SG10M-R1
Note
Express.

Note
Extension Boards
Table 6-107. EB-PDS-PCIE-Cable-R3 –FPGA Pin Constraints

(FPGA_)nCPERST IOSTANDARD =
LVCMOS18
(FPGA _)nCWAKE IOSTANDARD =
LVCMOS18
(FPGA _)nCPRSNT IOSTANDARD =
LVCMOS18
(FPGA _)CPWRON IOSTANDARD =
LVCMOS18

This topic is about Top-side extension.
MGT Pins:
Pins
General purpose pins:

Table 6-109. EB-PDS-PCIE-Cable-R3 - Top Connector Pin Mapping of GPIO
Pins
Top connector Bottom connector/FPGA Module
IO_000 IO_004
IO_001 IO_005
Extension Boards
Related Work

Pins (cont.)
... ...
IO_143 IO_147
... ...
Related Work
profpga_run
<instance name>:
{
type = “BOARD”;
size = “A1A1”;
};
more information.

Extension Boards
Redriver Configuration
This topic is about Redriver Configuration.
The extension board EB-PDS-PCIe-Cable-R3 includes two PCIe redrivers between the FPGA
and host system side. The first redriver is for channels 0 to 3, the second one for channels 4 to 7.
Both of the redrivers can be configured by a profpga plugin or by the DIP-switches S3 - S6
itself.
Figure 6-57. EB-PDS-PCIe-Cable-R3 Redriver Configuration DIP-Switches
If the I2C redriver configuration is used, it will be configured with a profpga plugin. To load the
plugin, the plugin_list entry before the system_configuration section must be added:
...
plugin_list = ( "pi2eqx8804 ProDesign EB-PDS-PCIe-Cable-R3" );
{
...
Extension Boards
This will load the PI2EQX8804 plugin. For this board the following x-board entry is required
within the system configuration file:
<instance name>:
{
type = "BOARD";
name = "EB-PDS-PCIe-Cable-R3";
size = "A1A1";
v_io_ba1 = "AUTO";
# pi2eqx8804 Plugin settings
A0:
{
EQ = <Equalization Setting>; # Expected values 0 - 15
PREEMP = <Pre-emphasis Setting>; # Expected values 0 - 3
SWING = <Swing Setting>; # Expected values 0 - 1
PRESHOT = <Pre-shoot Setting>; # Expected values 0 - 1
};
A1:
{
EQ = <Equalization Setting>;
PREEMP = <Pre-emphasis Setting>;
SWING = <Swing Setting>;
PRESHOT = <Pre-shoot Setting>;
};
.
.
.
A7:
{
};
B0:
{
};
B1:
{
};
.
.
.
B7:
{
Extension Boards

};
};
more information.
The redriver configuration plugin expects up to 8 channels with 4 parameter each. Each channel
is divided in two directions. A0 - A7 configures the equalization circuit between the host system
and the EB-PDS-PCIe-Cable-R3 extension board. B0 - B7 adjusts the equalization circuit
between the FPGA and the EB-PDS-PCIe-Cable-R3 extension board. Each channel and
equalization circuit can be configured separately. All parameters of a channel have to be
configured. Otherwise, these channels will not be configured. The same applies to channels
which have no entry in the configuration file. A channel that is omitted due to missing entries
will be marked with a hint during the power up sequence of the proFPGA system.
Note
Figure 6-57 on page 440 shows the structure of the EB-PDS-PCIe-Cable-R3 extension
board. Bit 0 of DIP-switchs S4 and S6 are makred in red. All configurations made by the
plugin are only accepted by the redriver if both red marked bits are set. If these two bits are not
set, the values will be written into the redriver, but the redriver will ignore it.
Table 6-110 to Table 6-113 on page 443 show the adjustable configuration parameters of the
PI2EQX8804 through the corresponding plugin.
Table 6-110. PI2EQX8804 Equalization Setting (EQ)
EQ @ 1.25 GHz @ 2.5GHz [dB] @ 4GHz [dB] @ 5GHz [dB]
[dB]
0 0.5 1.6 2.9 3.5
1 0.8 2.4 4.1 4.7
2 0.9 2.7 4.5 5.2
3 1.2 3.5 5.6 6.3
4 1.7 4.3 6.6 7.3
5 2 5.2 7.7 8.5
6 3.2 6.8 9.3 10.1
7 3.5 7.6 10.5 11.2
8 5.1 9.3 11.9 12.6
9 5.3 10.1 13 13.7
10 5.7 10.2 12.8 13.6
Extension Boards
Order Code
Table 6-110. PI2EQX8804 Equalization Setting (EQ) (cont.)

[dB]
11 6 11 14 14.7
12 8.1 12.8 15.3 16.1
13 8.3 13.6 16.5 17.2
14 9.5 14.4 17 17.8
15 9.8 15.3 18.2 18.9
Table 6-111. PI2EQX8804 Pre-emphasis Setting (PREEMP)

PREEMP Bias Current Pre-emphasis Pre-emphasis Pre-emphasis
gain@8Gbps, gain@8Gbps, gain@8Gbps,
S0_A/B=1 S0_A/B=1 S0_A/B=1
&PRE_A/B=0 &PRE_A/B=1 &PRE_A/B=1
& PRE_SELA/ & PRE_SELA/
B=0 B=1
0 1x -3dB -4dB -6dB
1 0.5x -1.5dB -2dB -3dB
2 0.25x -0.75dB -1dB -1.5dB
3 0.125x -0.375dB -0.5dB -0.75dB
Table 6-112. PI2EQX8804 Swing Setting (SWING)

SWING Swing factor
0 0.8x
1 1.0x (1.1V Diff. V pk-pk)
Table 6-113. PI2EQX8804 Pre-shoot Setting (PRESHOT)

PRESHOOT Pre-shoot (when Byte 2 Pre-shoot (when Byte2
PRE_SELA/B=1) PRE_SELA/B=0)
0 0 dB 0dB
1 3.5dB 1.6dB
Order Code
286522 - proFPGA PCIe gen3 8-lane Kit for Stratix 10
Extension Boards

This topic is about PCIe gen3 8-lane Kit (EB-PDS-PCIs-Cable-R5)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
transceivers (MGTs)
Figure 6-58. proFPGA PCIe gen3 8-lane Kit (Host Interface Board, PCIe cable,
There are two different kits available. One kit is dedicated to XILINX FPGAs which identifies
itself as EB-PDS-PCIe-Cable-R5. The second kit is specific to all INTEL Arria-10 and Stratix-
10 FPGAs which identifies itself as EB-PDS-PCIe-Cable-R2.
Extension Boards
Note
For information on the PCIe Kit for INTEL FPGAs (EB-PDS-PCIe-Cable-R2) please refer
to PCIe gen3 8-lane Kit (EB-PDS-PCIe-Cable-R2/R3).
Figure 6-59 shows the pin assignment of the external PCIe connector. All sideband signals are
decoupled from the host system via optocouplers (Figure 6-60).
Extension Boards
Peripherals
• The LED D1 (silkscreen nCPERST) signals the reset signal of the PCIe port. On means,
the reset is active and the FPGA is an off-state. Off means, the reset is not active. The
signal is driven by the PCIe host.
• The LED D3 (silkscreen nCPRSNT) signals the present signal of the PCIe port. On
means, the present signal is on. Off means, the present signal is off. The signal is driven
by the FPGA and is therefore an output of the FPGA. It has to be driven low and then the
LED is on.



Extension Boards

V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU160-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU125-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU095-R1 √(*) √(*) √(*) √(*) √(*) √
FM-XCVU080-R1 √(*) √(*) √(*) √ √(*) √
FM-XCKU115-R1 √(*) √(*) √ √ √ √
FM-XCVU5P-R1 √(*) √(*) √ √ √ √
FM-XCVU7P-R1 √(*) √(*) √ √ √ √
FM-XCVU9P-R1 √(*) √(*) √ √ √ √
FM-XCVU13P-R1 √(*) √(*)
FM-XCZU19EG-R2 √ √ √(*)
FM-XCZU17EG-R2 √ √ √(*)
FM-XCZU11EG-R2 √ √ √(*)
Extension Boards

In the table below, (**) Arria 10 PCIe Hard IP is not supported

V1 V1
FM-1SG280<L,H>-R1 √
FM-1SG280<L,H>-R2 √
FM-10AX115-R1 √(**) √(**) √(**) √(**)
FM-1SG10M-R1 √ √ √ √

Module
FM-
1SG10M-
R1
Note
Express.

Note
Extension Boards
Table 6-119. EB-PDS-PCIE-Cable-R5 – FPGA Pin Constraints

Top connector Bottom connector / FPGA Intel FPGA
Module
(FPGA_)nCPERST IOSTANDARD =
LVCMOS18
(FPGA _)nCWAKE IOSTANDARD =
LVCMOS18
(FPGA _)nCPRSNT IOSTANDARD =
LVCMOS18
(FPGA _)CPWRON IOSTANDARD =
LVCMOS18

MGT Pins:
Pins
General Purpose pins:

Pins
IO_000 IO_004
IO_001 IO_005
Extension Boards
Related Work

Pins (cont.)
... ...
IO_143 IO_147
... ...
Related Work
profpga_run
<instance name>:
{
type = “BOARD”;
size = “A1A1”;
};
more information.

Extension Boards
Both redrivers are configured by a profpga plugin.
To load the plugin, the plugin_list entry before the system_configuration section must be added:
...
plugin_list = ( "pi3eqx16904 Siemens EB-PDS-PCIe-Cable-R5" );
{
...
Extension Boards
<instance name>:
{
type = "BOARD";
vendor = "Siemens";
size = "A1A1";
v_io_ba1 = "AUTO";
A0RX:
{
GAIN = <Flat Gain Setting>; # Expected values 0 - 3
SWING = <Amplitude Setting>; # Expected values 0 - 3
};
A0TX:
{
GAIN = <Flat Gain Setting>;
SWING = <Amplitude Setting>;
};
.
.
.
A7RX:
{
};
A7TX:
{
};
};
more information.
The redriver configuration plugin expects 8 channels with 3 parameters each. Each channel is
divided in two directions. A0RX - A7RX configures the equalization circuit between the host
system and the EB-PDS-PCIe-Cable-R5 extension board. A0TX - A7TX adjusts the
equalization circuit between the FPGA and the EB-PDS-PCIe-Cable-R5 extension board. Each
channel and equalization circuit is configured separately. All parameters of all channels must be
configured. If an entry is missing an error is raised during the systems’ power-up.
Extension Boards
Order Code
In case the pi3eqx16904 plugin is not present in the plugin_list the extension board still powers
up. This is not handled as a fault condition by the proFPGA software. All parameters for all
channels are then set to the redrivers built-in default which is maximum.
Table 6-122 to Table 6-124 show the adjustable configuration parameters of the PI3EQX16904
through the corresponding plugin.
Table 6-122. PI3EQX16904 Equalization Setting (EQ)
[dB]
0 0.2 1.0 2.3 5.6
1 0.2 1.1 2.6 6.2
2 1.8 2.7 3.9 7.0
3 2.1 3.3 4.8 8.5
4 3.0 4.2 5.8 9.4
5 3.2 4.6 6.5 10.4
6 4.3 5.8 7.8 11.7
7 4.5 6.5 8.8 13.0
Table 6-123. PI3EQX16904 Pre-emphasis Setting (GAIN)

GAIN Flat (DC) Gain [dB]
0 -3.5
1 -2
2 -0.5
3 1
Table 6-124. PI3EQX16904 Swing Setting (SWING)

SWING Output Amplitude
0 800
1 1000
2 1100
3 1200
Order Code
Extension Boards
Order Code
289439 Veloce PF PCIe G3 8l Brd Xlnx R2
289440 Veloce PF PCIe Gen3 8-lane Rev2
Extension Boards
PCIe gen2 dual-4-lane Kit (EB-PDS-PCIe-Cable-R6)
PCIe gen2 dual-4-lane Kit (EB-PDS-PCIe-

Cable-R6)
This topic is about PCIe gen2 dual-4-lane Kit (EB-PDS-PCIe-Cable-R6)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
proFPGA PCIe Kit provides up to two 4 lane gen2 PCIe communication interfaces between PC
and FPGA Module to implement two PCIe downstream systems at the proFPGA system. All
unused FPGA Module pins are routed to top side connector and are available for user
applications.
• proFPGA PCIe gen2 dual-4-lane daughter card, which will be plugged on a free
extension site of the proFPGA FPGA Module, which provides the required high speed
serial transceivers (MGTs)
• One PCIe gen2 4-lane host interface card
• One dedicated high performance cable
Note
If the use of 2 ports is required, one additional PCIe gen2 4-lane host interface card and one
additional dedicated high performance cable are required (order codes: Board: 286531 and
cable: 286530).
Extension Boards
Figure 6-61. proFPGA PCIe gen2 dual-4-lane Kit (Host Interface Board, PCIe
cable, EB-PDS-PCIe-Cable-R2 proFPGA Extension Board)
The beneath figure shows the pin assignment of the external PCIe connector. All sideband
signals are decoupled from the host system via optocouplers (EB-PDS-PCIe-Cable-R6 -
Sideband signals).
Extension Boards
Peripherals
• The LEDs D6 and D7 signal the reset signals of the two PCIe ports. On means, the reset
is active and the FPGA is an off-state. Off means, the reset is not active. The signal is
driven by the PCIe host.

This is about Extension Board Operating Conditions.


(**) only port 0 can be used
(***) Arria 10 PCIe Hard IP is only supported on port 1
Extension Boards

V1 V1
FM-XC7V2000T-R1 √ √
FM-XC7V2000T-R2 √ √
FM-XC7VX330T-R3 √(*) √(*) √(*)
FM-XC7VX485T-R3 √(*) √(*) √(*)
FM-XC7V585T-R3 √(*) √ √(*) √(*)
FM-XC7VX690T-R3 √(*) √ √(*) √(*)
FM-XC7Z100-R1 √(*) √
FM-XC7Z045-R1 √(*) √
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU160-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU125-R1 √(*) √(*) √(*) √(*) √ √
FM-XCVU095-R1 √(*) √(*) √(*) √(*) √(*) √
FM-XCVU080-R1 √(*) √(*) √(*) √ √(*) √
FM-XCKU115-R1 √(*) √(*) √ √ √ √
FM-XCVU5P-R1 √(*) √(*) √ √ √ √
FM-XCVU7P-R1 √(*) √(*) √ √ √ √
FM-XCVU9P-R1 √(*) √(*) √ √ √ √
FM-XCVU13P-R1 √(*) √(*)
FM-XCZU17EG-R2 √ √ √(*)
FM-XCZU11EG-R2 √ √ √(*)
Extension Boards

V1 V1
FM-10AX115-R1 √(** √(** √(** √(**
*) *) *) *)
FM-1SG10M-R1 √(** √(** √(** √(**

*) *) *) *)

FM-1SG10M-R1
Note
Express.

This topic is about FPGA Pin Constraint.
Note
Table 6-128. : EB-PDS-PCIE-Cable-R6 – FPGA Pin Constraints

(FPGA_)nCPERST_0 IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
(FPGA _)nCWAKE_0 IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
(FPGA _)nCPRSNT_0 IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
(FPGA _)CPWRON_0 IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
(FPGA_)nCPERST_1 IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
Extension Boards
Table 6-128. : EB-PDS-PCIE-Cable-R6 – FPGA Pin Constraints (cont.)

(FPGA _)nCWAKE_1 IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
(FPGA _)nCPRSNT_1 IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
(FPGA _)CPWRON_1 IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18

Table 6-129. EB-PDS-PCIE-Cable-R6 - Top Connector Pin Mapping Of Mgt

Pins
General purpose pins:

pins
IO_000 IO_008
IO_001 IO_009
... ...
IO_139 IO_147
... ...
Extension Boards
Related Work
Related Work
profpga_run
Please refer to “Redriver Configuration” on page 461.

Both redrivers are configured by a profpga plugin.
To load the plugin, the plugin_list entry before the system_configuration section must be added:
...
plugin_list = ( "pi3eqx16904 Siemens EB-PDS-PCIe-Cable-R6" );
{
...
Extension Boards
<instance name>:
{
type = "BOARD";
vendor = "Siemens";
size = "A1A1";
v_io_ba1 = "AUTO";
P0RX0:
{
GAIN = <Flat Gain Setting>; # Expected values 0 - 3
SWING = <Amplitude Setting>; # Expected values 0 - 3
};
P0TX0:
{
};
.
.
.
P1RX3:
{
};
P1TX3:
{
};
};
more information.
The redriver configuration plugin expects 8 channels (4 channels per port) with 3 parameters
each. Each channel is divided in two directions. P[0,1]RX0 – P[0,1]RX3 configures the
equalization circuit between the host system and the EB-PDS-PCIe-Cable-R6 extension board.
P[0,1]TX0 – P[0,1]TX3 adjusts the equalization circuit between the FPGA and the EB-PDS-
PCIe-Cable-R6 extension board. Each channel and equalization circuit is configured separately.
All parameters of all channels must be configured. If an entry is missing an error is raised
during the systems power-up.
Extension Boards
Note
It is recommended to use the maximum settings (EQ=7, GAIN=3, SWING=3) for use with
the EB-PDS-PCIe-Cable-R6. The DIP switches on the PCIeHostCableAdapter card should
be in the factory set position.
In case the pi3eqx16904 plug is not present in the plugin_list the extension board still powers
up. This is not handled as a fault condition by the proFPGA software. All parameters for all
channels are then set to the redrivers built-in default which is maximum.
Table 6-131 to Table 6-133 show the adjustable configuration parameters of the PI3EQX16904
through the corresponding plugin.
Table 6-131. : EB-PDS-PCIe-Cable-R6 - PI3EQX16904 Equalization Setting
(EQ)
[dB]
0 0.2 1.0 2.3 5.6
1 0.2 1.1 2.6 6.2
2 1.8 2.7 3.9 7.0
3 2.1 3.3 4.8 8.5
4 3.0 4.2 5.8 9.4
5 3.2 4.6 6.5 10.4
6 4.3 5.8 7.8 11.7
7 4.5 6.5 8.8 13.0
Table 6-132. EB-PDS-PCIe-Cable-R6 - PI3EQX16904 Pre-emphasis Setting

(GAIN)
GAIN Flat(DC) Gain[dB]
0 -3.5
1 -2
2 -0.5
3 1
Table 6-133. EB-PDS-PCIe-Cable-R6 - PI3EQX16904 Swing Setting (SWING)

0 800
1 1000
Extension Boards
Order Code
Table 6-133. EB-PDS-PCIe-Cable-R6 - PI3EQX16904 Swing Setting (SWING)

2 1100
3 1200
Order Code
289462 Veloce PF PCIe Gen2 4-lane Rev2
Extension Boards
PCIe Root Complex and M.2 Extension Board (EB-PDS-ROOT-COMPLEX-M.2-R1)
PCIe Root Complex and M.2 Extension Board

(EB-PDS-ROOT-COMPLEX-M.2-R1)
This topic is about PCIe Root Complex and M.2 Extension Board (EB-PDS-ROOT-
COMPLEX-M.2-R1)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
The proFPGA root complex and M.2 extension board has a PCIe x16 socket where 8 MGT
lanes are connected and an M.2 socket with Key M where 4 MGT lanes are connected.
The board provides:
• PCIe x16 socket, where 8 MGT lanes are connected

• M.2 connector with Key M, where 4 MGT lanes are connected
• An additional 12V power connector if the PCIe card draws too much current
• 3 LEDs
• 1 push button
Note
8 MGT lanes of the PCIe x16 socket can only be used if the FPGA module supports 12
MGTs on the extension board connector. If the FPGA module supports only 8 MGTs on the
extension board connector, only 4 MGTs are connected to the PCIe socket.
Extension Boards
Figure 6-64. EB-PDS-ROOT-COMPLEX-M.2-R1
Peripherals
• PCIe socket
o Connect your PCIe card here.
• PCIe bracket
o The PCIe card can be fixed here.
• Button
o Can be assigned for user usage. The signal has a pull-up and is low, when the button
is pressed.
• LEDs
o There are 3 user LEDs on the board. The signals have to be driven high if the LED
should glow.
• proFPGA TOP connector
o The proFPGA TOP connector makes unused Ios from the BOTTOM connector
available.
• M.2 socket
o Connect your M.2 card with Key M here.
• Holes for M.2 card mounting
o There are several holes available to support any kind of M.2 card which is specified
in the appropriate specification.
o To mount the M.2 card, please connect the screw and the nut at the right hole. Then
connect the M.2 card into the M.2 socket and fix it on the board with the washer and
the screw.
Extension Boards
• External P12V connector (optional)

o Connect the external 12 V power here if need. If the power from the bottom
connector is not sufficient to power the board plugged into the PCIe socket, an
additional 12 V power has to be attached here.
Figure 6-65. EB-PDS-ROOT-COMPLEX-M.2-R1 Components

Table 6-134. EB-PDS-ROOT-COMPLEX-M.2-R1 – Extension Board Operating

Conditions
Extension Boards

In the table below, (*) not officially supported by Xilinx Integrated Block for PCIe,
(**) only 4 Lanes

Table 6-135. EB-PDS-ROOT-COMPLEX-M.2-R1 – FPGA Extension Site
Compatibility and PCIe Blocks
FPGA Module Site PCIe block for PCIe block for
M.2 connector PCIe Edge
connector
FM-XC7V2000T-R1 TB2 X0Y1 X0Y0
BB2 X0Y0 X0Y0
FM-XC7V2000T-R2 TB1 X0Y1 X0Y1
TB2 X0Y0 X0Y0
FM-XC7VX330T-R3 TA1 X0Y1
TB1 X0Y1
TB2 X0Y0
FM-XC7V585T-R3 TA1 X0Y2
FM-XC7VX690T-R3 TA2 X0Y0 X0Y0
TB1 X0Y2
TB2 X0Y1
FM-XCVU440-R1 TA1 X0Y0 X0Y0
FM-XCVU440-R2 TA2 X0Y1 X0Y1
TB1 X0Y2 X0Y2
TB2 X0Y3 X0Y3
BB1 X0Y4 X0Y4
BB2 X0Y5 X0Y5
FM-XC7Z045-R1 TA1 X0Y0 X0Y1**
FM-XC7Z100-R1 TA2 X0Y3 X0Y2**
Extension Boards

Compatibility and PCIe Blocks (cont.)
connector
FM-XCVU190-R1 TB1 X0Y5
TB2 X0Y3
BB1 X0Y4 X0Y4
BB2 X0Y2 X0Y2
FM-XCVU160-R1 TB1
TB2
BB1 X0Y3 X0Y3
BB2 X0Y1 X0Y1
FM-XCVU125-R1 TB1 * X0Y3
TB2 * X0Y1
BB1 X0Y2 X0Y2
BB2 X0Y0 X0Y0
FM-XCVU095-R1 TB1 * *
FM-XCVU080-R1 TB2 * X0Y1

BB1 X0Y2 X0Y2
BB2 X0Y0 X0Y0
FM-XCKU115-R1 TB1 X0Y4 X0Y4
TB2 X0Y1 X0Y1
BB1 X0Y2 X0Y2
BB2 X0Y0 X0Y0
FM-XCZU-[11,17]EG- TA2 X1Y0 X1Y0
R1
TB2 X0Y1,X1Y1 X0Y1,X1Y1
BB1 via ARM via ARM
FM-XCZU-19EG-R1 TA2 X1Y0 X1Y0
TB2 X1Y0, X1Y1, X1Y0, X1Y1
X1Y2
BB1 via ARM via ARM
Extension Boards

connector
FM-XCVU5P-R1 TA1 X0Y3 X0Y3
TA2 X0Y1 X0Y1
TB1 X1Y2 X1Y2
TB2 X1Y0 X1Y0
BB1 X1Y2 *
BB2 X1Y0 *

TA2 X0Y1 X0Y1
TB1 X1Y2 X1Y2
TB2 X1Y0 X1Y0
BB1 X1Y2 *
BB2 X1Y0 *

TA2 X0Y1 X0Y1
TB1 X1Y4 X1Y4
TB2 X1Y2 X1Y2
BB1 X1Y4 (*)
BB2 X1Y2 (*)
FM-XCVU13P-R1 TA2 (*) (*)
TB2 (*) (*)
FM-XCVU19P-R1 TA0 X0Y6, X0Y7 X0Y6, X0Y7

TA1 X0Y4, X0Y5 X0Y4, X0Y5
TB0 X0Y0, X0Y1 X0Y0, X0Y1
TB1 X0Y2, X0Y3 X0Y2, X0Y3
Extension Boards

connector
FM-XCVU[37,47]P-R1 TA1 (*) (*)
TA2 PCIE4C_X0Y0, PCIE4C_X0Y0,

PCIE4C_X0Y1 PCIE4C_X0Y1
TB1 PCIE4_X0Y1 PCIE4_X0Y1
TB2 PCIE4_X0Y0 PCIE4_X0Y0
The table above summarizes the compatibility of the EB-PDS-ROOT-COMPLEX for each
FPGA module and on which FPGA site it could be placed.
Note
If Xilinx FPGAs are used and the integrated block for PCIe should be used: For each FPGA
site the integrated block for PCIe is listed which should be used for the PCIe design in
Vivado. It should be verified that the right PCIe lanes are connected to the according MGT
channels. The information for the according connector can be generated by proFPGA builder or
proFPGA brdgen. The information of the PCIe lanes is not given in the common xdc file in
Vivado. There is another xdc file in the project where this information is given and has to be
modified.

Note
Please refer “proFPGA Extension Board Design Guide” [UD003] for information about
Table 6-136. : EB-PDS-ROOT-COMPLEX-M.2-R1 – FPGA Pin Constraint

io[*] <any>
clk_io_n[*] <any>
clk_io_p[*]
Extension Boards
Top-side Extension Board Connector

MGT Pins:
Table 6-137. EB-PDS-ROOT-COMPLEX-M.2-R1 - Top Connector Pin Mapping
of MGT Pins
General Purpose pins:

Table 6-138. EB-PDS-ROOT-COMPLEX-M.2-R1- TOp Connector Pin Mapping
of GPIO pins
IO_000 IO_044
IO_001 IO_045
... ...
IO_103 IO_147
... ...
Related Work
Extension Boards
Related Work

Note
profpga_run
...
plugin_list = ( "si5338 ProDesign EB-PDS-ROOT-COMPLEX-M.2-R1" );
{
...
...
"si5338 ProDesign EB-PDS-ROOT-COMPLEX-M.2-R1" );
{
...
<instance name>:
{
type = "BOARD";
name = "EB-PDS-ROOT-COMPLEX-M.2-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.
Extension Boards
Order Code

information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-ROOT-COMPLEX-
M.2-R1”. The system configuration file can be created manually or with the profpga_builder
tool.
Order Code
286518
Extension Boards
PCIe Root Complex Extension Board (EB-PDS-ROOT-COMPLEX-R1)
PCIe Root Complex Extension Board (EB-PDS-

ROOT-COMPLEX-R1)
This section describes the PCIe Root Complex Extension Board EB-PDS-ROOT-COMPLEX-
R1.
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
The proFPGA root complex extension board has a PCIe x16 socket where 8 MGT lanes are
connected. In comparison to the EB-PDS-ROOT-COMPLEX-M.2-R1 board, the pinout of this
board is optimized for Stratix 10 FPGA modules.
The board provides:
• PCIe x16 socket, where 8 MGT lanes are connected

• 2 LEDs
• 1 push button
Extension Boards
Figure 6-66. EB-PDS-ROOT-COMPLEX-R1
Peripherals
• PCIe socket
Connect your PCIe card here.
• PCIe bracket
The PCIe card can be fixed here.
• Button
Can be assigned for user usage. The signal has a pull-up and is low, when the button is
pressed.
• LEDs
There are 2 user LEDs on the board. The signals have to be driven high if the LED
should glow.
The proFPGA TOP connector makes unused Ios from the BOTTOM connector
available
Extension Boards
Figure 6-67. EB-PDS-ROOT-COMPLEX-R1 Components

This topic describes the EB-PDS-ROOT-COMPLEX-R1 extension board operating conditions.
Table 6-139. EB-PDS-ROOT-COMPLEX-R1 — Extension Board Operating

Conditions

This topic describes the FPGA extension site compatibility of EB-PDS-ROOT-COMPLEX-R1.
Extension Boards
In the table below, (1) lanes are inversed connected, could lead to timing errors, not officially
supported by Xilinx Integrated Block for PCIe, it is recommended to use the EB-PDS-ROOT-
COMPLEX-M.2-R1 extension board instead - this may fit better
(2) only 6 lanes are connected

Table 6-140. EB-PDS-ROOT-COMPLEX-R1 — FPGA Extension Site
Compatibility
V1 V1
FM-XC7V2000T-R1 √(1) √(1)
FM-XC7V2000T-R2 √(1) √(1)
FM-XC7VX330T-R3 √(1) √(1) √(1)
FM-XC7VX485T-R3 √(1) √(1) √(1)
FM-XC7V585T-R3 √(1) √(1) √(1) √(1)
FM-XC7VX690T-R3 √(1) √(1) √(1) √(1)
FM-XC7Z100-R1 √(1) √(1)
FM-XC7Z045-R1 √(1) √(1)
FM-XCVU440-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU440-R2 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU190-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU160-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU125-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU095-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU080-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCKU115-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU5P-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU7P-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU9P-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU13P-R1 √(1) √(1)
FM-XCVU19P-R1 √(1) √(1)
Extension Boards

V1 V1
FM-XCVU37P-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU47P-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-1SG280<L,H>-R1 √ √(2)
FM-1SG280<L,H>-R2 √ √(2)
FM-XCZU19EG-R2 √(1) √(1)
FM-XCZU17EG-R2 √(1) √(1)
FM-XCZU11EG-R2 √(1) √(1)
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √

FM-1SG10M-R1
FM-XCVU19P-R1 √(1) √(1)

This topic describes the FPGA pin constraints of EB-PDS-ROOT-COMPLEX-R1.
Note
Please refer proFPGA Extension Board Design Guide [UD003] for information about MGT
placement constraints depending on FPGA module type and connector position.
Table 6-142. EB-PDS-ROOT-COMPLEX-R1 — FPGA Pin Constraint

io[*] <any>
clk_io_n[*] <any>
clk_io_p[*]
Extension Boards

Top side extension connector provides pin unused by daughter card with following mapping.
MGT Pins
Table 6-143. EB-PDS-ROOT-COMPLEX-R1 —Top Connector Pin Mapping of
MGT Pins
General purpose pins

Table 6-144. EB-PDS-ROOT-COMPLEX-R1 — Top Connector Pin Mapping of
GPIO Pins
IO_000 IO_028
IO_001 IO_029
… …
IO_119 IO_147
… …
Related Work
This topic describes EB-PDS-ROOT-COMPLEX-R1 related work.

Extension Boards
Related Work
Note
profpga_run
...
plugin_list = ( "si5338 ProDesign EB-PDS-ROOT-COMPLEX-R1" );
{
...
If there is already a plugin_list entry the plugin list must be extended.
Example:
...
"si5338 ProDesign EB-PDS-ROOT-COMPLEX-R1" );
{
...
<instance name>:
{
type = "BOARD";
name = "EB-PDS-ROOT-COMPLEX-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
system configuration. Please refer to the proFPGA Software Reference Manual [UD002] for
more information.
Extension Boards
Order Code

profpga_run. Please refer to the proFPGA Software Reference Manual [UD002] for more
information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-ROOT-COMPLEX-
R1”. The system configuration file can be created manually or with the profpga_builder tool.
Please refer to the proFPGA Software Reference Manual [SWRM] and the proFPGA Builder
User Manual [UD004] for more information.
Order Code
The order code for EB-PDS-ROOT-COMPLEX-R1 is 286523.
Extension Boards
PCIe 4-lane Host Interface Card (PCIex4_HostCableAdaptor-R2)
PCIe 4-lane Host Interface Card

This section describes the PCIe 4-lane host interface card PCIex4_HostCableAdaptor-R2.
DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
The proFPGA 4-lane host interface card provides 4-lane PCIe cable connection to a subsystem.
It is designed to fit in a standard PC’s 4-lane (or higher) slot.
Features of the board:
• One PCIe x4 connector for cable connection

• One 4-lane PCIe ReDriver
• PCIe Edge connector for installation in a PCIe x4 (or higher) slot
• One 100 MHz clock cleaner
• Standard PCIe slot bracket
Extension Boards
DIP Switch Settings
Figure 6-68. PCIex4_HostCableAdaptor-R2
DIP Switch Settings

This topic describes the DIP switch settings.
Table 6-145. PCIex4_HostCableAdaptor-R2 — Settings for DIP Switch SRD1

1 RD1_EQ2 ON 0
2 RD1_EQ1 ON 0
3 RD1_EQ0 ON 0
4 RD1_SW1 ON 0
5 RD1_FG1 ON 0
6 RD1_FG0 ON 0

1 RD2_EQ2 ON 0
Extension Boards
Order Code

2 RD2_EQ1 ON 0
3 RD2_EQ0 ON 0
4 RD2_SW1 ON 0
5 RD2_FG1 ON 0
6 RD2_FG0 ON 0
Order Code
This topic describes the order code for PCIex4_HostCableAdaptor-R2.
• Board: 289461 Veloce PF Host Brd PCIe 4l G3 Rev2
• Cable: 286530
Extension Boards
Mini PCIe Host Interface Card (MPCIe_HostCableAdapter-R1)
Mini PCIe Host Interface Card

(MPCIe_HostCableAdapter-R1)
This section describes the Mini PCIe host interface card MPCIe_HostCableAdapter-R1.
DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
The proFPGA mini PCIe host interface card provides 1-lane PCIe gen2 cable connection to a
subsystem. It is designed to fit into a mini PCIe slot. Because of the connector, the size is not
conforming to the PCIe specification.
It is used to build up a PCIe connection between a Mini PCIe subsystem and the proFPGA
system in combination with a PCIe extension board.
Caution
Due to the direction of the sideband signals, it is designed to work in a PCIe root complex
system. The direction of the sideband signals cannot be changed. So it will not work to
connect 2 root complex systems together.
Figure 6-69. MPCIe_HostCableAdapter-R1 — Typical Application Example
Features of the board:
• One PCIe x4 connector for cable connection

• One PCIe ReDriver
• Mini PCIe Edge connector for installation in a Mini PCIe Slot
• PCI Express™ Jitter Attenuator
Extension Boards
DIP Switch Settings
Figure 6-70. MPCIe_HostCableAdapter-R1
DIP Switch Settings

This topic describes the DIP switch settings of MPCIe_HostCableAdapter-R1.
Table 6-147. MPCIe_HostCableAdapter-R1 — Settings for DIP Switch S1

1 PLL_SEL OFF 1
2 MR ON 0
3 F_SEL0 ON 0
4 F_SEL1 ON 0

1 S0_A ON 0
2 [S1_A] OFF 1
3 [SEL0_A] OFF 1
Extension Boards
Order Code

4 SEL1_A OFF 1
5 [SEL2_A] OFF 1
6 [D0_A] OFF 1
7 P1_A__D1_A ON 0
8 nRDX_RES__D2_ OFF 1
A
9 VTH0__DE_A OFF 1
10 VTH1 OFF 1

1 S0_B ON 0
2 [S1_B] OFF 1
3 [SEL0_B] OFF 1
4 SEL1_B OFF 1
5 [SEL2_B] OFF 1
6 [D0_B] OFF 1
7 P1_B__D1_B ON 0
8 [D2_B] OFF 1
9 [DE_A] OFF 1
10 - - -
Order Code
This product is no longer available.
Extension Boards
M.2 Endpoint Extension Board (EB-PDS-M.2-EP-FLEX-R2)
M.2 Endpoint Extension Board (EB-PDS-M.2-

EP-FLEX-R2)
This section describes the M.2 Endpoint extension board EB-PDS-M.2-EP-FLEX-R2.
USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
SMBUS Interface and ID-PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
The proFPGA M.2 Endpoint extension board has an M.2 edge connector with Key M where 4
MGT lanes are connected.
The board provides:
• M.2 edge connector with Key M in 22110 formfactor, where 4 MGT lanes are connected
• proFPGA top connector for interconnection cables only
• A flexible connection between edge connector and proFPGA connector
• A button for individual use
• A 2.54mm Header for SMBus incl. #Alert signal
• Microchip Technology 24AA025E48-I/SN IDPROM on SMBUS with Adress 0xA6
• A JTAG connector with DIP-Switch for change between external JTAG or FPGA
• A 2.54mm Header for Manufacturing Data and Clock line
Extension Boards
Figure 6-71. EB-PDS-M.2-EP-FLEX-R2
Peripherals
• M.2 Edge Connector Key M
o Connects to a M.2 Key M slot.
• Holes for M.2 card mounting
o There are several holes available for best fitting option to the target system.
o To mount the M.2 connector, please connect the screw and the nut at the right hole.
Then connect the M.2 card into the M.2 socket and fix it on the target with the
washer and the screw.
• Button
o Can be assigned for custom usage. The signal has a pull-up and is driven low, when
the button is pressed.
• SMBUS Header
o Connector provides SMBUS with pull-ups for CLK and Data to PV_IO.
o Additional nAlert Pin.dedicated M.2 edge connector pins.
Extension Boards

o The proFPGA TOP connector makes unused IOs from the BOTTOM connector
available.
• JTAG Connector
o JTAG connector for debugging.
• JTAG Switch
o Switch to route the TDI and TDO of JTAG Chain to external connector or to FPGA.
• MFG Header
o Header to connect MFG Pins of target system
Figure 6-72. EB-PDS-M.2-EP-FLEX-R2 Components

This topic describes the extension board operating conditions of EB-PDS-M.2-EP-FLEX-R2.
Table 6-150. EB-PDS-M.2-EP-FLEX-R2 — Extension Board Operating

Conditions
Extension Boards

This topic describes the FPGA extension site compatibility of EB-PDS-M.2-EP-FLEX-R2.
Table 6-151. EB-PDS-M.2-EP-FLEX-R2 — Extension Site Compatibility

V1 V1
FM-XC7V2000T-R1 √ √
FM-XC7V2000T-R2 √ √
FM-XC7VX330T-R3 √ √ √ √
FM-XC7VX485T-R3 √ √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √
Extension Boards
Table 6-151. EB-PDS-M.2-EP-FLEX-R2 — Extension Site Compatibility (cont.)

V1 V1
FM-1SG280<L,H>-R2 √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √
Table 6-152. EB-PDS-M.2-EP-FLEX-R2 — FPGA Extension Site Compatibility,

FM-1SG10M-R1

This topic describes the FPGA pin constraints of EB-PDS-M.2-EP-FLEX-R2.
Note
Please refer to proFPGA Extension Board Design Guide [UD003] for information about
Table 6-153. EB-PDS-M.2-EP-FLEX-R2 — FPGA Pin Constraint

<all> <any>
USB Interface
This topic describes the USB interface of EB-PDS-M.2-EP-FLEX-R2.
Table 6-154.
Component Manufacturer Order Code Comment
IDPROM Microchip 24AA025E48-I/SN
Crystal Abracon ABM8-24.000MHZ-D2-T/24MHz 24 Mhz
Levelshifter Texas SN74AVCH8T245RHLR
Instruments
Extension Boards
SMBUS Interface and ID-PROM
Figure 6-73. EB-PDS-M.2-EP-FLEX-R2 USB Implementation
SMBUS Interface and ID-PROM

This topic describes the SMBUS interface and ID-PROM of EB-PDS-M.2-EP-FLEX-R2.
Component Manufacturer Order Code Comment

USB PHY Microchip USB3290-FH-TR Interface: UTMI
1X5 Header - - P=2.54mm
IDPROM Microchip 24AA025E48-I/SN 2Kbit with 0xA6
Address
Figure 6-74. EB-PDS-M.2-EP-FLEX-R2 SMBUS Implementation
Extension Boards

The top side extension connector provides pins unused by daughter card with the following
mapping.
General Purpose Pins

Table 6-155. EB-PDS-M.2-EP-FLEX-R2 — Top Connector Pin Mapping of GPIO
Pins
IO_000 IO_040
IO_001 IO_041
... ...
IO_107 IO_147
... ...
Related Work
This topic describes the EB-PDS-M.2-EP-FLEX-R2 related work.
profpga_run
<instance name>:
{
type = "BOARD";
name = "EB-PDS-M.2-EP-FLEX-R2";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.
Extension Boards
Order Code

plugged onto.
Please ensure that the system configuration file which is the input to the profpga_brdgen tool,
contains a valid x-board entry using the extension board name “EB-PDS-M.2-EP-FLEX-R2”.
The system configuration file can be created manually or with the profpga_builder tool.
Order Code
Use the order code 286543 for EB-PDS-M.2-EP-FLEX-R2.
Extension Boards
Debug Board (EB-PDS-DEBUG-R1)

This section describes the EB-PDS-DEBUG-R1 debug board.
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
The EB-PDS-DEBUG-R1 daughter board occupies one extension site of the proFPGA system
and offers various connectors and interfaces for debugging purpose.
Figure 6-75. EB-PDS-DEBUG-R1
The debug board provides:
• Three Mictor connectors to interface the proFPGA system to standard Logic Analyzers
or other measurement equipment (Figure 201)
• One 20x2 pin connector for general purpose IOs (Figure 202)
• One USB-UART debug interface over a micro USB connector (UART_TXD,
UART_RXD, UART_RTSn, UART_CTSn)
• One CPUARM JTAG interface (Figure 203)
• 16 LEDs (D1…D16 connected to IO_000…IO_015)
Extension Boards
• PV_IO power (X4) and GND (X5) connector

Figure 6-76. EB-PDS-DEBUG-R1 — Mictor Connector
Figure 6-77. EB-PDS-DEBUG-R1 — GPIO Pin Header
Extension Boards
Figure 6-78. EB-PDS-DEBUG-R1 — ARM JTAG Interface
Caution
SWDIO function is not available with this connector due to unidirectional levelshifters
used.
Caution
Some JTAG programmers need to be adjusted/ increased regarding drive strength to work
properly.
The UART pins are connected to the FTDI FT232R. The direction of each pin is shown in the
following table:
Table 6-156. EB-PDS-DEBUG-R1 — Pinout of UART Connector
Signal FT232R FPGA
Extension Boards

This topic describes the extension board operating conditions of EB-PDS-DEBUG-R1.
Table 6-157. EEB-PDS-DEBUG-R1 — Extension Board Operating Conditions


This topic describes the PGPGA extension site compatibility of EB-PDS-DEBUG-R1.
Caution
on EB-PDS-DEBUG-R1 may be unconnected.
In the table below, (1) LEDs, X2 (not all GPIOs), UART, JTAG (without JTAG_P1V8_NSRST)
can be used,
(2)
all but without Mictor CON #2 and #3,
(3)
using EB-FM-XCVU440-R1,
(4) MICTORs cannot be used

Table 6-158. EB-PDS-DEBUG-R1 — FPGA extension site compatibility
FPGA Module TA1 TA TB1 TB2 BA1 BA2 BB1 BB2 TA1V1 TA2V
2 1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √(1)
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √(1)
FM-XC7VX330T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7VX485T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7V585T-R3 √ √(2) √ √ √ √(1)
FM-XC7VX690T-R3 √ √(2) √ √ √ √(1)
FM-XC7Z100-R1 √(2) √
FM-XC7Z045-R1 √(2) √
Extension Boards
Table 6-158. EB-PDS-DEBUG-R1 — FPGA extension site compatibility (cont.)

FPGA Module TA1 TA TB1 TB2 BA1 BA2 BB1 BB2 TA1V1 TA2V
2 1
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(1)(3) √(1)(3)
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(1)(3) √(1)(3)
FM-XCVU190-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU160-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU125-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU095-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU080-R1 √ √ √ √(1) √(1) √(1)
FM-XCKU115-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU5P-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU7P-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU9P-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU13P-R1 √ √ √ √ √(4)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(1)(3) √(1)(3)
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-1SG280<L,H>- √ √ √ √ √ √(1) √ √
R1
FM-XCZU19EG-R2 √ √ √(1) √
FM-XCZU17EG-R2 √ √ √(1) √
FM-XCZU11EG-R2 √ √ √(1)
FM-1SG280<L,H>- √ √ √ √ √ √(1) √ √
R2
FM-10AX115-R1 √ √ √ √ √(1) √(1)
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(1)(3) √(1)(3)
Extension Boards
Table 6-159. EB-PDS-DEBUG-R1 — FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

This topic describes the FPGA pin constraints of EB-PDS-DEBUG-R1.
Table 6-160. EB-PDS-DEBUG-R1 — FPGA Pin Constraint

<all> LVCMOS18
Related Work
This topic describes the EB-PDS-DEBUG-R1 related work.
profpga_run
<instance name>:
{
type = "BOARD";
name = "EB-PDS-DEBUG-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
system configuration. Please refer to the proFPGA Software Reference Manual [SWRM] for
more information.

plugged onto.
Extension Boards
Order Code
contains a valid x-board entry using the extension board name “EB-PDS-DEBUG-R1”. The
Order Code
Use the order code 286513 for EB-PDS-DEBUG-R1.
Extension Boards

This section describes the EB-PDS-DEBUG-R2 debug board.
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
The board provides:
• Three SoftTouch Connectors to interface the proFPGA system to standard Logic

Analyzers or other measurement equipment (Figure 205)
• One 16x2 pin connector for general purpose IOs (Figure 206)
Extension Boards
• One CPUARM JTAG interface (Figure 207)

• 16 LEDs (D1…D16) with different colours
o 4 LEDs with blue colour
o 4 LEDs with red colour
o 4 LEDs with green colour
o 4 LEDs with yellow colour
Figure 6-80. EB-PDS-DEBUG-R2 — SoftTouch Connectors
It is possible to add external termination resistors for usage of SSTL IOSTANDARDs if

needed. Therefore, resistor pads (0603 size) and a termination voltage PSU which generates
PVIO/2 is available.
Figure 6-81. EB-PDS-DEBUG-R2 — GPIO Pin Header
Extension Boards
Figure 6-82. EB-PDS-DEBUG-R2 — ARM JTAG Interface
Caution
used.
Caution
properly.
following table:
Table 6-161. EB-PDS-DEBUG-R2 — Pinout of UART Connector
Signal FT232R FPGA

Table 6-162. EB-PDS-DEBUG-R2 — Extension Board Operating Conditions

Extension Boards


This topic describes the FPGA extension site compatibility of EB-PDS-DEBUG-R2.
Caution
Depending on the number of available I/Os on the FPGA module connectors some functions
In the table below, (1) without SoftTouch connector3, IO13, IO14 and IO15
(2)
without SoftTouch connectors 2 and 3, JTAG, UART, IO[0…15]
Table 6-163. EB-PDS-DEBUG-R2 — FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √(1) √
FM-XC7Z045-R1 √(1) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √
FM-XCVU125-R1 √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
Extension Boards
Table 6-163. EB-PDS-DEBUG-R2 — FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √(2) √
FM-XCVU47P-R1 √ √ √(2) √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √
The SoftTouch connectors are only fully compatible to the following sites:
X9
Table 6-165. EB-PDS-DEBUG-R2 — X9 SoftTouch FPGA Extension Site
Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √
FM-XC7VX330T-R3 √ √
Extension Boards

V1 V1
FM-XC7V585T-R3 √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √
FM-XCVU125-R1 √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-1SG280<L,H>- √ √ √ √ √ √ √
R1
FM-XCZU19EG-R2 √ √ √ √ √
FM-XCZU17EG-R2 √ √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-166. EB-PDS-DEBUG-R2 X9 SoftTouch — FPGA Extension Site

FM-1SG10M-R1 √ √ √ √ √ √
Extension Boards

Compatibility, [B,T][A,AB,B]0 Connectors (cont.)
FM-XCVU19P-R1 √ √ √ √
X10
Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √ √ √
FM-XCVU080-R1 √ √ √
FM-XCKU115-R1 √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
Extension Boards

V1 V1
FM-1SG280-R1 √ √ √ √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √
X11
Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
Extension Boards

V1 V1
FM-XCVU095-R1 √ √ √
FM-XCVU080-R1 √ √ √
FM-XCKU115-R1 √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>- √ √ √ √ √ √ √
R1
FM-1SG10M-R1 √ √ √ √ √ √ √ √

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √


<all> LVCMOS18
Extension Boards
Related Work
Related Work
This topic describes the EB-PDS-DEBUG-R2 related work.
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

plugged onto.
Order Code
Extension Boards
Debug Board (EB-PDS-DEBUG-SWDIO-R3)
Debug Board (EB-PDS-DEBUG-SWDIO-R3)

This section describes the EB-PDS-DEBUG-SWDIO-R3 debug board.
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
The EB-PDS-DEBUG-SWDIO-R3 daughter board occupies one extension site of the proFPGA
system and offers various connectors and interfaces for debugging purpose.
Extension Boards
Connectors
The board provides:
• 2 Mictor connectors to interface the proFPGA system to standard Logic Analyzers or

other measurement equipment
• One 20x2 pin connector for general purpose IOs
• One CPUARM JTAG interface
• Capability for Single Wire Debug via Pin JTAG-TMS and direction controlled by FPGA
Pin SWDIO.
• One Cortex Debug Connector 0,05” 10-Pin Header
• One Cortex Debug + ETM Connector 0,05” 20-Pin Header
• 16 LEDs (D1…D16 connected to IO_000…IO_015)
• A single push button
• A 8 position half pitch dip switch
• A Mini Sim Slot (2FF)
• A ìSD-Card slot
Connectors
This topic describes the EB-PDS-DEBUG-R3 connectors.
The available connectors are:
• JTAG Connectors
• µSD Interface
• SIM Interface
• µSD Interface, UART Over USB Interface
• MICTOR Connectors
• DEBUG Header
• DEBUG Button and DIP-Switch
Extension Boards
Connectors
JTAG Connectors
The board provides 3 Types of JTAG connectors.
Figure 6-84. EB-PDS-DEBUG-R3 — ARM JTAG Interface + CORTEX DEBUG

with and without ETM
The Jumper X8 could be used for enable or disable “VSUPPLY” functionality.
The direction of the TMS signal of the JTAG interface ca be controlled by the FPGA. This
allow the usage of the SWDIO functionality.
Table 6-172. Direction Settings for TMS Signal
Voltage Level of SWDIO_direction Signal Direction of JTAG_TMS / SWDIO Pin
LOW input
HIGH output
Caution
The direction signal of the Levelshifter (SWDIO_direction) has to be driven low, by the
FPGA for a stable JTAG connection.
Caution
properly.
Extension Boards
Connectors
Table 6-173 shows all relevant JTAG Signals on FPGA:

Table 6-173. JTAG Signals on proFPGA Connector
IO number Direction Signal Name Note
onConnetor
IO_033 input JTAG_NTRST
IO_034 input JTAG_TDI
IO_035 input JTAG_TMS SDIO Pin
IO_036 output JTAG_TDO
IO_037 bidirectional JTAG_NSRST
CLK_IO_P_6 input JTAG_TCK
CLK_IO_P_7 output JTAG_RTCK
CLK_IO_P_4 output TRACECLK
CLK_IO_N_5 output TRACEDATA_0
CLK_IO_P_5 output TRACEDATA_1
IO_018 output SWDIO_Direction Controls direction of SDIO
Pin
Extension Boards
Connectors
µSD Interface
Figure 6-85. EB-PDS-DEBUG-R3 - µSD-Interface
Table 6-174. SD Signals on proFPGA Connector

IO number on Direction Signal Name Note
Connector
CLK_IO_P_2 bidirectional TRC_CLK
IO_024 bidirectional TRC_EXT
CLK_IO_N_2 bidirectional TRC_DATA_0
CLK_IO_N_3 bidirectional TRC_DATA_1
CLK_IO_P_3 bidirectional TRC_DATA_2
CLK_IO_N4 bidirectional TRC_DATA_3
IO_127 input SD_CD Optional Chip Detect Signal
Extension Boards
Connectors
SIM Interface
Figure 6-86. EB-PDS-DEBUG-R3 Mini-SIM interface
The direction of the SIM_IO and SIM_SPU signals of the SIM interface ca be controlled by the
FPGA.
Table 6-175. Direction Settings for SIM-Signal
Voltage Level of Control-Signals Direction of SIM_*** Pin
LOW input
HIGH output
Table 6-176. SIM Holder Contacts on proFPGA Connetor

onConnetor
IO_025 output SIM_CLK
IO_026 output SIM_RST
IO_027 bidirectional SIM_IO
IO_028 bidirectional SIM_SPU
IO_110 output SIM_SPU_DIR Controls direction of SIM_SPU
IO_111 output SIM_IO_DIR Controls direction of SIM_IO
IO_112 output SIM_VCC Controls IO-Voltage and VCC-
Voltage of SIM Connector
Extension Boards
Connectors
µSD Interface, UART Over USB Interface

Figure 6-87. UART over USB Interface
The UART pins are connected to the FTDI FT232R.

Table 6-177. UART Signals
onConnetor
IO_029 Output UART_TXD
IO_030 Input UART_RXD
IO_031 Output UART_RTSn
IO_032 Input UART_CTSn
MICTOR Connectors
Figure 6-88. Mictor Connectors
Extension Boards
Connectors
Table 6-178. Signals on MICTOR Connectors

MICTOR Connector 1 MICTOR Connector2
IO MICTO MICTO Signal IO MICTO MICTO Signal
number R Pin R Pin Name number R Pin R Pin Name
Number Name Number Name
- 5 GND1 GND - 5 GND1 GND
CLK_IO 5 CLK1 CLK_IO CLK_IO 5 CLK1 CLK_IO
_N_0 _N_0 _N_0 _N_0
CLK_IO 6 CLK2 CLK_IO CLK_IO 6 CLK2 CLK_IO
_P_0 _P_0 _P_0 _P_0
IO_068 7 A15 IO_068 IO_068 7 A15 IO_068
IO_069 8 B15 IO_069 IO_069 8 B15 IO_069
IO_066 9 A14 IO_066 IO_066 9 A14 IO_066
IO_067 10 B14 IO_067 IO_067 10 B14 IO_067
IO_064 11 A13 IO_064 IO_064 11 A13 IO_064
IO_065 12 B13 IO_065 IO_065 12 B13 IO_065
IO_062 13 A12 IO_062 IO_062 13 A12 IO_062
IO_063 14 B12 IO_063 IO_063 14 B12 IO_063
IO_060 15 A11 IO_060 IO_060 15 A11 IO_060
IO_061 16 B11 IO_061 IO_061 16 B11 IO_061
IO_058 17 A10 IO_058 IO_058 17 A10 IO_058
IO_059 18 B10 IO_059 IO_059 18 B10 IO_059
IO_056 19 A9 IO_056 IO_056 19 A9 IO_056
IO_057 20 B9 IO_057 IO_057 20 B9 IO_057
IO_054 21 A8 IO_054 IO_054 21 A8 IO_054
IO_055 22 B8 IO_055 IO_055 22 B8 IO_055
IO_052 23 A7 IO_052 IO_052 23 A7 IO_052
IO_053 24 B7 IO_053 IO_053 24 B7 IO_053
Extension Boards
Connectors
Table 6-178. Signals on MICTOR Connectors (cont.)

MICTOR Connector 1 MICTOR Connector2
IO MICTO MICTO Signal IO MICTO MICTO Signal
number R Pin R Pin Name number R Pin R Pin Name
Number Name Number Name
IO_050 25 A6 IO_050 IO_050 25 A6 IO_050
IO_051 26 B6 IO_051 IO_051 26 B6 IO_051
IO_048 27 A5 IO_048 IO_048 27 A5 IO_048
IO_049 28 B5 IO_049 IO_049 28 B5 IO_049
IO_046 29 A4 IO_046 IO_046 29 A4 IO_046
IO_049 30 B4 IO_049 IO_049 30 B4 IO_049
IO_044 31 A3 IO_044 IO_044 31 A3 IO_044
IO_045 32 B3 IO_045 IO_045 32 B3 IO_045
IO_042 33 A2 IO_042 IO_042 33 A2 IO_042
IO_043 34 B2 IO_043 IO_043 34 B2 IO_043
IO_040 35 A1 IO_040 IO_040 35 A1 IO_040
IO_041 36 B1 IO_041 IO_041 36 B1 IO_041
IO_038 37 A0 IO_038 IO_038 37 A0 IO_038
IO_039 38 B0 IO_039 IO_039 38 B0 IO_039
DEBUG Header
Figure 6-89. DEBUG Header
Extension Boards
Connectors
Table 6-179. Signals on DEBUG Header

IO number Pin on Signal Name IO number Pin on Signal Name
Header Header
- 1 PV_IO IO_009 21 GPIO_9
- 2 GND IO_117 22 GPIO_27
IO_000 3 GPIO_0 IO_010 23 GPIO_10
IO_126 4 GPIO_36 IO_116 24 GPIO_26
IO_001 5 GPIO_1 IO_011 25 GPIO_11
IO_125 6 GPIO_35 IO_115 26 GPIO_25
IO_002 7 GPIO_2 IO_012 27 GPIO_12
IO_124 8 GPIO_34 IO_114 28 GPIO_24
IO_003 9 GPIO_3 IO_013 29 GPIO_13
IO_123 10 GPIO_33 IO_113 30 GPIO_23
IO_004 11 GPIO_4 IO_014 31 GPIO_14
IO_122 12 GPIO_32 IO_022 32 GPIO_22
IO_005 13 GPIO_5 IO_015 33 GPIO_15
IO_121 14 GPIO_31 IO_021 34 GPIO_21
IO_006 15 GPIO_6 IO_016 35 GPIO_16
IO_120 16 GPIO_30 IO_020 36 GPIO_20
IO_007 17 GPIO_7 IO_017 37 GPIO_17
IO_119 18 GPIO_29 IO_019 38 GPIO_19
IO_008 19 GPIO_8 IO_128 39 GPIO_18
IO_118 20 GPIO_28 - 40 GND
DEBUG Button and DIP-Switch

Button and DIP-Switch are pulled to PV_IO.
Table 6-180. Signals on DIP-Switch
Header Header
IO_102 1 SWITCH_1 IO_106 5 SWITCH_5
Extension Boards
Table 6-180. Signals on DIP-Switch (cont.)

Header Header
The Button is connected to IO_023 and the signal name is BUTTON.



This topic describes the FPGA extension site compatibility of EB-PDS-DEBUG-R3.
Caution
In the table below, (1) LEDs, X2 (not all GPIOs), Button and ìSD without CD pin
(2)
LEDs, X2 (not all GPIOs), Button, ìSD without CD pin, JTAG, CORTEX DEBUG include
ETM,UART, all but without Mictor CON #2 and #3
(3) using EB-FM-XCVU440-R1

Table 6-182. EB-PDS-DEBUG-R3 – FPGA extension site compatibility,
FPGA Module TA TA TB1 TB2 BA BA BB BB2 TA1V TA2V
1 2 1 2 1 1 1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √(1)
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √(1)
FM-XC7VX330T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7VX485T-R3 √ √(1) √ √(1) √ √(1)
Extension Boards
Table 6-182. EB-PDS-DEBUG-R3 – FPGA extension site compatibility, (cont.)

1 2 1 2 1 1 1
FM-XC7V585T-R3 √ √(2) √ √ √ √(1)
FM-XC7VX690T-R3 √ √(2) √ √ √ √(1)
FM-XC7Z100-R1 √(2) √
FM-XC7Z045-R1 √(2) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(1)(3) √(1)(3)
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(1)(3) √(1)(3)
FM-XCVU190-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU160-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU125-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU095-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU080-R1 √ √ √ √(1) √(1) √(1)
FM-XCKU115-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU5P-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU7P-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU9P-R1 √ √ √ √(1) √(1) √(1)
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(1)(3) √(1)(3)
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-1SG280<L,H>- √ √ √ √ √ √ √
R1
FM-1SG280<L,H>- √ √ √ √ √ √ √
R2
FM-10AX115-R1 √ √ √ √
Extension Boards
Table 6-182. EB-PDS-DEBUG-R3 – FPGA extension site compatibility, (cont.)

1 2 1 2 1 1 1
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(1)(3) √(1)(3)

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √


<all> LVCMOS18
Related Work
This topic describes EB-PDS-DEBUG-R3 related work.
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.
Extension Boards
Order Code

plugged onto.
Order Code
Extension Boards

This topic discusses Debug Board (EB-PDS-DEBUG-R4).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
The board provides
• Three SoftTouch Connectors to interface the proFPGA system to Tektronix Logic

Analyzers or other measurement equipment (Figure 6-91)
• One 16x2 pin connector for general purpose IOs (Figure 217Figure 6-92)
• One CPUARM JTAG interface (Figure 6-93)
Extension Boards
• 16 LEDs (D1…D16) with different colours

• 4 LEDs with blue colour
• 4 LEDs with red colour
• 4 LEDs with green colour
• 4 LEDs with yellow colour
Figure 6-91. EB-PDS-DEBUG-R4 – SoftTouch Connectors
It is possible to add external termination resistors for usage of SSTL IOSTANDARDs if

needed. Therefore, resistor pads (0603 size) and a termination voltage PSU which generates
PVIO/2 is available.
Figure 6-92. EB-PDS-DEBUG-R4 - GPIO Pin Header
Extension Boards
Figure 6-93. EB-PDS-DEBUG-R4 - ARM JTAG Interface
Note
used.
Note
properly.
following table:
Table 6-185. EB-PDS-DEBUG-R4 – Pinout of UART Connector
Signal FT232R FPGA

This topic discusses extension board operating conditions of Debug Board (EB-PDS-DEBUG-
R4).
Extension Boards
Table 6-186. EB-PDS-DEBUG-R4 – Extension Board Operating Conditions


This topic discusses FPGA extension site compatibility of Debug Board (EB-PDS-DEBUG-
R4).
Note
Depending on the number of available I/Os on the FPGA module connector some functions
In the table below, (1) without SoftTouch connector3, IO13, IO14 and IO15
Table 6-187. EB-PDS-DEBUG-R4 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √ (1) √
FM-XC7Z045-R1 √(1) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √
FM-XCVU125-R1 √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
Extension Boards
Table 6-187. EB-PDS-DEBUG-R4 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √(2) √
FM-XCVU47P-R1 √ √ √(2) √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √(1) √(1) √(1) √(1) √(1) √(1) √(1) √(1)
Table 6-188. EB-PDS-DEBUG-R4 – FPGA extension site compatibility,

[B,T][A,AB,B]0 connectors
FM-1SG10M-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU19P-R1 √ √ √ √
The SoftTouch connectors are only fully compatible to the following sites:
X9
Table 6-189. EB-PDS-DEBUG-R4 – X9 SoftTouch FPGA Extension Site
Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √
Extension Boards

V1 V1
FM-XC7V585T-R3 √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √
FM-XCVU125-R1 √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-XCZU17EG-R2 √ √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-190. EB-PDS-DEBUG-R4 – X9 SoftTouch – FPGA Extension Site

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √
Extension Boards
X10
Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √ √ √
FM-XCVU080-R1 √ √ √
FM-XCKU115-R1 √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
Extension Boards

V1 V1
FM-1SG10M-R1 √ √ √ √ √ √ √ √

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √
X11
Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √ √ √
FM-XCVU080-R1 √ √ √
FM-XCKU115-R1 √ √ √
Extension Boards

V1 V1
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-1SG10M-R1

FM-1SG10M-R1
FM-XCVU19P-R1 √ √ √ √

This topic discusses FPGA pin constraints of Debug Board (EB-PDS-DEBUG-R4).
Table 6-195. EB-PDS-DEBUG-R4 –FPGA Pin Constraint

<all> LVCMOS18
Related Work
This topic discusses related work of Debug Board (EB-PDS-DEBUG-R4).
Extension Boards
Order Code
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

plugged onto.
system configuration file can be created directly or with the profpga_builder tool.
Order Code
This topic discusses order code of Debug Board (EB-PDS-DEBUG-R4).
286516
Extension Boards
MGT Debug Board (EB-PDS-MGT-MMCX-R1)
MGT Debug Board (EB-PDS-MGT-MMCX-R1)

This topic discusses MGT Debug Board (EB-PDS-MGT-MMCX-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
This topic discusses functional description of MGT Debug Board (EB-PDS-MGT-MMCX-R1).
Figure 6-94. MGT Debug Board (EB-PDS-MGT-MMCX-R1)
The MGT Debug Board provides:
• Two proFPGA extension board connectors (1 at bottom-side, 1 at top side)

• Two 125 MHz differential (LVDS) clock outputs via MMCX connectors. Both clock
outputs are synchronous and based on the same 125 MHz clock generator.
• Four differential MGT REFCLK inputs via MMCX connectors
• 12 differential MGT TX outputs via MMCX connectors
• 12 differential MGT RX inputs via MMCX connectors
Extension Boards
• proFPGA top connector to make all unused IOs available for further connections or
extension boards
All MMCX MGT REFCLK inputs are AC-coupled via 100 nF capacitors.
All MMCX MGT TX and RX connections are AC-coupled via 10 nF capacitors.
Figure 6-95. EB-PDS-MGT-MMCX-R1 Components

This topic discusses extension board operating conditions for MGT Debug Board (EB-PDS-
MGT-MMCX-R1).
Table 6-196. EB-PDS-MGT-MMCX-R1 – Extension Board Operating Conditions

is used on top of this board the IO voltage requirements of this upper level hardware will be applied.

This topic discusses FPGA extension site compatibility of MGT Debug Board (EB-PDS-MGT-
MMCX-R1).
Extension Boards
Table 6-197. EB-PDS-MGT-MMCX-R1 – FPGA Extension Site Compatibility

V1 V1
FM-XC7V2000T-R1 √ √
FM-XC7V2000T-R2 √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √ √ √
FM-XCVU080-R1 √ √ √ √ √ √
FM-XCKU115-R1 √ √ √ √ √ √
FM-XCVU5P-R1 √ √ √ √ √ √
FM-XCVU7P-R1 √ √ √ √ √ √
FM-XCVU9P-R1 √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √ √ √ √
FM-XCVU47P-R1 √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √
FM-1SG280<L,H>-R2 √ √ √
FM-10AX115-R1 √ √ √ √
Extension Boards
Table 6-197. EB-PDS-MGT-MMCX-R1 – FPGA Extension Site Compatibility

V1 V1
FM-1SG10M-R1 √ √ √ √
Table 6-198. EB-PDS-MGT-MMCX-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1

This topic discusses FPGA pin constraints of MGT Debug Board (EB-PDS-MGT-MMCX-R1).
Note
Please refer “proFPGA Extension Board Design Guide” [UD003] for information about
Table 6-199. EB-PDS-MGT-MMCX-R1 – FPGA Pin Constraint

io[*] <any>
clk_io_n[*] <any>
clk_io_p[*]
Related Work
This topic discusses related work of MGT Debug Board (EB-PDS-MGT-MMCX-R1).
Extension Boards
Order Code
profpga_run
<instance name>:
{
type = "BOARD";
name = "EB-PDS-MGT-MMCX-R1";
size = "A1A1";
top_connectors = ("TA1");
v_io_ba1 = "AUTO";
};
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-MGT-MMCX-R1”.
The system configuration file can be created directly or with the profpga_builder tool.
Order Code
This topic discusses order code of MGT Debug Board (EB-PDS-MGT-MMCX-R1).
286517
Extension Boards
FMC Mezzanine Board Adapter (EB-PDS-FMC-R1/R2/R3)
FMC Mezzanine Board Adapter (EB-PDS-FMC-

R1/R2/R3)
This topic discusses FMC Mezzanine Board Adapter (EB-PDS-FMC-R1/R2/R3).

Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Differences between EB-PDS-FMC-R1 and EB-PDS-FMC-R2 . . . . . . . . . . . . . . . . . . . 549
Differences between EB-PDS-FMC-R2 and EB-PDS-FMC-R3 . . . . . . . . . . . . . . . . . . . 550
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
This topic discusses functional description of FMC Mezzanine Board Adapter (EB-PDS-FMC-
R1/R2/R3).
The FMC Mezzanine adapter board provides a HPC (high pin count) connector which is
compliant to the FMC standard [FMC] and supports FMC Mezzanine boards.
The main features of this board are:
• proFPGA A1A2 size extension board

• Two proFPGA extension board connectors (bottom-side)
• One FMC connector on top side
• 116 FMC bank A signals (58 differential signals)
• 44 FMC bank B signals (22 differential signals)
• Two differential unidirectional clk signals
• Two differential bidirectional clk signals
• Two differential REFCLK signals for MGTs
• 10 differential MGT signals (10 RX and 10 TX)
• on EB-PDS-FMC-R2: FMC I2C signals and GA signals
Extension Boards
Figure 6-96. EB-PDS-FMC-R1/R2/R3 - Top View (FMC Side)
Figure 6-97. EB-PDS-FMC-R1/R2/R3 - Bottom View (proFPGA Side)
Caution
The IO voltage and IO standard of the regular IOs must meet the capabilities of both
systems which need to be connected (the proFPGA system and the FMC mezzanine
module).
Especially for FMC_VIO_B_M2C which is generated by the mezzanine board the user needs to
take care about the correct IO voltage levels. For example the FM-XC7V2000T-R2 supports
PV_IO voltage levels up to 1.8V only.
Extension Boards
Figure 6-98. EB-PDS-FMC-R1/R2 Components
Unsupported FMC features are:
• FMC JTAG signals are ignored and left unconnected

• on EB-PDS-FMC-R1: FMC I2C signals are ignored and left unconnected
• on EB-PDS-FMC-R1: FMC GA signals are ignored and left unconnected

This topic discusses extension board operating conditions of FMC Mezzanine Board Adapter
(EB-PDS-FMC-R1/R2/R3).
Table 6-200. EB-PDS-FMC-R1/R2 – Extension Board Operating Conditions

IO voltage (min…recommended…max) <any>
IO voltage provider FPGA module for proFPGA connector A2
(FMC Bank A)
FMC Mezzanine Board for proFPGA
connector A1 (FMC Bank B)
Top-side extension board connector FMC Mezzanine Standard [FMC]
Extension Boards
Known Issues
Known Issues
This topic is about Known Issues in FMC Mezzanine Board Adapter (EB-PDS-FMC-R1/R2/
R3).
Caution
The signals LA01_N_CC and LA01_P_CC are swapped. This means if this signal pair is
used for a differential signal the signal value must be negated within the FPGA to correct
the phase.
This issue applies to EB-PDS-FMC-R1 and EB-PDS-FMC-R2. For signal standards other than
differential signals this issue has no impact.
Caution
The CLK_DIR signal is not supported by EB-PDS-FMC-R1/R2 and must not be driven
with 3.3V. Before plugging a FMC mezzanine board onto EB-PDS-FMC-R1/R2 please
double check if CLK_DIR is unconnected or not driven higher than the used FPGA IO voltage.
This issue applies to EB-PDS-FMC-R1 (all schematic revisions) and EB-PDS-FMC-R2

schematic revision < 2.0. For EB-PDS-FMC-R2 schematic revision 2.0 or higher the CLK_DIR
signal is unconnected.
With the proFPGA software 2015C or later the schematic revision can be obtained using the
following steps:
1. plug the EB-PDS-FMC-R2 onto the proFPGA system for example on connectors TA1/
TA2
2. power-on proFPGA
3. read out the IDPROM using the profpga_run tool (please refer [UD002] for more
information how to use the profpga_run tool):
$ profpga_run profpga.cfg --get-idprom MB1
TA1 1
...
Vendor: ProDesign
Name: EB-PDS-FMC-R2
Serial No: Bxxxxxx
Revision: 2.00
Size: A1A2
PROM version: 2
...
Caution
The level shifter for I2C and the GA signals are not connected to PV_IO. Due to this the I2C
and GA are not available.
Extension Boards
This issue applies to EB-PDS-FMC-R2 schematic revision < 3.0. For EB-PDS-FMC-R2
schematic revision 3.0 or higher I2C and GA are fully operative.
With the proFPGA software 2015C or later the schematic revision can be obtained using the
following steps:
1. plug the EB-PDS-FMC-R2 onto the proFPGA system for example on connectors TA1/
TA2
2. power-on proFPGA
3. read out the IDPROM using the profpga_run tool (please refer [UD002] for more
information how to use the profpga_run tool):
$ profpga_run profpga.cfg --get-idprom MB1
TA1 1
...
Vendor: ProDesign
Name: EB-PDS-FMC-R2
Serial No: Bxxxxxx
Revision: 3.00
Size: A1A2
PROM version: 2
...

This topic discusses FPGA extension site compatibility of FMC Mezzanine Board Adapter (EB-
PDS-FMC-R1/R2/R3).
In the table below, (MGT) MGT signals are available.
Table 6-201. EB-PDS-FMC-R1/R2/R3 – FPGA Extension Site Compatibility
FPGA Module TA1/TA2 TB1/TB2 BA1/BA2 BB1/BB2
FM-XC7V2000T-R1 HPC HPC(MGT) HPC
FM-XC7V2000T-R2 HPC HPC(MGT) HPC
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3 HPC(MGT)
FM-XC7VX690T-R3 HPC(MGT)
FM-XC7Z100-R1 HPC(MGT)
FM-XC7Z045-R1 HPC(MGT)
FM-XCVU440-R1 HPC(MGT) HPC(MGT) HPC HPC(MGT)
Extension Boards
Table 6-201. EB-PDS-FMC-R1/R2/R3 – FPGA Extension Site Compatibility

FPGA Module TA1/TA2 TB1/TB2 BA1/BA2 BB1/BB2
FM-XCVU440-R2 HPC(MGT)) HPC(MGT)) HPC HPC(MGT))
FM-XCVU190-R1 HPC(MGT))
FM-XCKU115-R1 HPC(MGT))
FM-XCVU5P-R1 HPC(MGT))
FM-XCVU13P-R1
FM-XCVU19P-R1 HPC HPC HPC HPC
FM-1SG280<L,H>-R1
FM-XCZU19EG-R2
FM-XCZU17EG-R2
FM-XCZU11EG-R2
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1
Table 6-202. EB-PDS-FMC-R1/R2/R3 – FPGA Extension Site Compatibility,

FPGA Module TA0/TA1 TB0/TB1
FM-1SG10M-R1
FM-XCVU19P-R1 HPC(MGT)) HPC(MGT))
Extension Boards

This topic discusses FPGA pin constraints of FMC Mezzanine Board Adapter (EB-PDS-FMC-
R1/R2/R3).
Table 6-203. EB-PDS-FMC-R1/R2/R3 –FPGA Pin Constraints

<all> <any>
Differences between EB-PDS-FMC-R1 and EB-PDS-

FMC-R2
This topic discusses the differences between EB-PDS-FMC-R1 and EB-PDS-FMC-R2.
The variants differ in the MGT signal assignment and in the connection of the FMC I2C and GA
signals:
Figure 6-99. MGT Pin Assignment on EB-PDS-FMC-R1
Figure 6-100. MGT Pin Assignment on EB-PDS-FMC-R2
Extension Boards
Differences between EB-PDS-FMC-R2 and EB-PDS-FMC-R3
Table 6-204. Connection of FMC I2C Signals on EB-PDS-FMC-R1/R2

FMC I2C Bus Signal EB-PDS-FMC-R1 EB-PDS-FMC-R2
FMC_I2C_SCL unconnected connected to FPGA module via level
shifter
FMC_I2C_SDA unconnected connected to FPGA module via level
shifter
FMC_I2C_GA0 unconnected connected to FPGA module via level
shifter
FMC_I2C_GA1 unconnected connected to FPGA module via level
shifter
Differences between EB-PDS-FMC-R2 and EB-PDS-

FMC-R3
This topic discusses the differences between EB-PDS-FMC-R2 and EB-PDS-FMC-R3.
The LA/HA/HB signals are connected to the proFPGA according to FMC specification
recommendations. The “_CC” signals and their associated I/O-Signals (Table 6-205) are
connected to the same I/O-Bank. For further Information about this recommendation refer to
FMC-Specification [FMC].
Table 6-205. FMC "_CC"-Signal Association to I/O Signals
“_CC” Signal(s) Associated I/Os
primary/secondary
LA00/LA01 LA01 – LA16
LA17/LA18 LA18 – LA33
HA00/HA01 HA01 – HA16
HA17/HA18 HA18 – HA23
HB00/HA06 HB01 – HB16
HB17 HB18 – HB21
Caution
The LA/HA/HB signal assignment of the EB-PDS-FMC-R3 is not compatible with the EB-
PDS-FMC-R1/R2 variants.
Extension Boards
Related Work
Related Work
This topic discusses related work of FMC Mezzanine Board Adapter (EB-PDS-FMC-R1/R2/
R3).
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A2";
name = "EB-PDS-FMC-R3";
positions = ("motherboard_1.TA1", "motherboard_1.TA2");
top_connectors = ("TA1", "TA2");
v_io_ba1 = "<value>"; # set this value to the IO voltage
# provided by the FMC mezzanine board
# on FMC bank B
# which should be provided to the FMC
# mezzanine board on FMC bank A
};
more information.
Caution
Special care must be taken to set the voltage values for connector BA1 and BA2. They must
match the capabilities of the proFPGA FPGA module and the FMC Mezzanine board and
must not exceed the maximum IO voltage values of both components. If the maximum IO
voltage values will be exceeded the FPGA module and/or FMC Mezzanine module will be
damaged.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-FMC-R1”, “EB-PDS-
FMC-R2”, “EB-PDS-FMC-R3”. The system configuration file can be created directly or with
the profpga_builder tool.
Please refer to the “proFPGA Software Reference Manual” [UD002] and the “proFPGA
Extension Boards
Order Code
Order Code
This topic discusses order code of FMC Mezzanine Board Adapter (EB-PDS-FMC-R1/R2/R3).
286534
Extension Boards
FMC Bank A Mezzanine Board Adapter (EB-PDS-FMC-BANK-A-R1)
FMC Bank A Mezzanine Board Adapter (EB-

PDS-FMC-BANK-A-R1)
This topic discusses FMC Bank A Mezzanine Board Adapter (EB-PDS-FMC-BANK-A-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
This topic discusses functional description of FMC Bank A Mezzanine Board Adapter (EB-
PDS-FMC-BANK-A-R1).
The FMC Bank A Mezzanine adapter board provides an HPC (high pin count) connector which
is compliant to the FMC standard [FMC] and supports FMC Mezzanine boards.

• One proFPGA extension board connectors (bottom-side)
• FMC I2C signals and GA signals
Extension Boards
Figure 6-101. EB-PDS-FMC-BANK-A-R1 - Top View (FMC Side)
Caution
module).
Figure 6-102. EB-PDS-FMC-BANK-A-R1 Components

• The CLK_DIR signal (to control the bidirectional clocks directions) is not connected to
FPGA
Extension Boards
• FMC Bank B is not available

This topic discusses extension board operating conditions of FMC Bank A Mezzanine Board
Adapter (EB-PDS-FMC-BANK-A-R1).
Table 6-206. EB-PDS-FMC-BANK-A-R1 – Extension Board Operating

Conditions
(FMC Bank A)

This topic discusses FPGA extension site compatibility of FMC Bank A Mezzanine Board
Adapter (EB-PDS-FMC-BANK-A-R1).
In the table below, (1) MGT signals only partially available
(2)
MGT signals not available
Table 6-207. EB-PDS-FMC-BANK-A-R1 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √(2) √(2) √(1) √(1) √(2) √(2) √(2)
FM-XC7V2000T-R2 √(2) √(2) √(1) √(1) √(2) √(2) √(2)
FM-XC7VX330T-R3 √(1) √(1) √(2)
FM-XC7VX485T-R3 √(1) √(1) √(2)
FM-XC7V585T-R3 √(1) √(1) √ √(2)
FM-XC7VX690T-R3 √(1) √(1) √ √(2)
FM-XC7Z100-R1 √(1)
FM-XC7Z045-R1 √(1)
FM-XCVU440-R1 √(1) √(1) √(1) √(1) √(2) √(2) √(1) √(1)
FM-XCVU440-R2 √(1) √(1) √(1) √(1) √(2) √(2) √(1) √(1)
Extension Boards

V1 V1
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √(1) √ √(1)
FM-XCVU080-R1 √(1) √ √(1)
FM-XCKU115-R1 √(1) √(1) √
FM-XCVU13P-R1 √ √ √(2 √(2)
FM-XCVU19P-R1 √ √(2) √ √(2) √(2) √(2) √(2) √(2)
FM-1SG280<L,H>-R1 √ √(1) √(1) √(2) √(2) √(2) √(2)
FM-1SG280<L,H>-R2 √ √(1) √(1) √(2) √(2) √(2) √(2)
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √(2) √(2) √(2) √(2)
Table 6-208. EB-PDS-FMC-BANK-A-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1 √(2) √(2) √(2) √(2) √(2) √(2)
FM-XCVU19P-R1 √ √ √(2) √(2)

This topic discusses FPGA pin constraints of FMC Bank A Mezzanine Board Adapter (EB-
PDS-FMC-BANK-A-R1).
Extension Boards
Related Work
Table 6-209. EB-PDS-FMC-BANK-A-R1 – FPGA Pin Constraints

<all> <any>
Related Work
This topic discusses FMC Bank A Mezzanine Board Adapter (EB-PDS-FMC-BANK-A-R1).
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A1";
name = "EB-PDS-FMC-BANK-A-R1";
positions = ("motherboard_1.TA1");
# on FMC bank A
};
system configuration. Please refer to the “proFPGA Software Reference Manual” [SWRM] for
more information.
Caution
Special care must be taken to set the voltage values for connector BA1. They must match
the capabilities of the proFPGA FPGA module and the FMC Mezzanine board and must not
exceed the maximum IO voltage values of both components. If the maximum IO voltage values
will be exceeded the FPGA module and/or FMC Mezzanine module will be damaged.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-FMC-BANK-A-R1”.
Extension Boards
Order Code
Order Code
This topic discusses order code of FMC Bank A Mezzanine Board Adapter (EB-PDS-FMC-
BANK-A-R1).
Extension Boards
FMC Reduced Mezzanine Board Adapter (EB-PDS-FMC-REDUCED-R1)
FMC Reduced Mezzanine Board Adapter (EB-

PDS-FMC-REDUCED-R1)
This topic discusses FMC Reduced Mezzanine Board Adapter (EB-PDS-FMC-REDUCED-
R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
This topic discusses functional description of FMC Reduced Mezzanine Board Adapter (EB-
PDS-FMC-REDUCED-R1).
The FMC Reduced Mezzanine adapter board provides an HPC (high pin count) connector
which is compliant to the FMC standard [FMC] and supports FMC Mezzanine boards.

• 24 FMC bank B signals (12 differential signals)
Extension Boards
Figure 6-103. EB-PDS-FMC-REDUCED-R1 - Top View (FMC Side)
Note
module).
Figure 6-104. EB-PDS-FMC-REDUCED-R1 Components
Extension Boards
• The CLK_DIR signal (to control the bidirectional clocks directions) is not connected to
FPGA
• FMC Bank B HB[12-21] is not available

This topic discusses extension board operating conditions of FMC Reduced Mezzanine Board
Adapter (EB-PDS-FMC-REDUCED-R1).
Table 6-210. EB-PDS-FMC-REDUCED-R1 – Extension Board Operating

Conditions
(FMC Bank A)

This topic discusses FPGA extension site compatibility of FMC Reduced Mezzanine Board
Adapter (EB-PDS-FMC-REDUCED-R1).
In the table below, (1) MGT signals only partially available
(2)
MGT signals not available
V1 V1
FM-XC7V2000T-R1 √(2) √(2) √(1) √(1) √(2) √(2) √(2)
FM-XC7V2000T-R2 √(2) √(2) √(1) √(1) √(2) √(2) √(2)
FM-XC7VX330T-R3 √(1) √(1) √(2)
FM-XC7VX485T-R3 √(1) √(1) √(2)
FM-XC7V585T-R3 √(1) √(1) √ √(2)
FM-XC7VX690T-R3 √(1) √(1) √ √(2)
FM-XC7Z100-R1 √(1)
FM-XC7Z045-R1 √(1)
Extension Boards

V1 V1
FM-XCVU440-R1 √(1) √(1) √(1) √(1) √(2) √(2) √(1) √(1)
FM-XCVU440-R2 √(1) √(1) √(1) √(1) √(2) √(2) √(1) √(1)
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √(1) √ √(1)
FM-XCVU080-R1 √(1) √ √(1)
FM-XCKU115-R1 √(1) √(1) √
FM-XCVU13P-R1 √ √ √(2 √(2)
FM-XCVU19P-R1 √ √(2) √ √(2) √(2) √(2) √(2) √(2)
FM-1SG280<L,H>-R1 √ √(1) √(1) √(2) √(2) √(2) √(2)
FM-1SG280<L,H>-R2 √ √(1) √(1) √(2) √(2) √(2) √(2)
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √(2) √(2) √(2) √(2)
Table 6-212. EB-PDS-FMC-REDUCED-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1 √(2) √(2) √(2) √(2) √(2) √(2)
FM-XCVU19P-R1 √ √ √(2) √(2)
Extension Boards

This topic discusses FPGA pin constraints of FMC Reduced Mezzanine Board Adapter (EB-
PDS-FMC-REDUCED-R1).
Table 6-213. EB-PDS-FMC-REDUCED-R1 – FPGA Pin Constraints

<all> <any>
Related Work
This topic discusses related work of FMC Reduced Mezzanine Board Adapter (EB-PDS-FMC-
REDUCED-R1).
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A1";
name = "EB-PDS-FMC-REDUCED-R1";
};
more information.
Caution

plugged onto.
Extension Boards
Order Code
contains a valid x-board entry using the extension board name “EB-PDS-FMC-REDUCED-
R1”. The system configuration file can be created directly or with the profpga_builder tool.
Order Code
This topic discusses order code of FMC Reduced Mezzanine Board Adapter (EB-PDS-FMC-
REDUCED-R1).
Extension Boards
FMC LPC Mezzanine Board Adapter (EB-PDS-FMC-LPC-R1)
FMC LPC Mezzanine Board Adapter (EB-PDS-

FMC-LPC-R1)
This topic discusses FMC LPC Mezzanine Board Adapter (EB-PDS-FMC-LPC-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
This topic discusses functional description of FMC LPC Mezzanine Board Adapter (EB-PDS-
FMC-LPC-R1).
The FMC LPC Mezzanine adapter board provides a LPC (low pin count) connector which is
compliant to the FMC standard [FMC] and supports FMC Mezzanine boards.

• One FMC LPC connector on top side
• One differential REFCLK signals for MGTs
• 1 differential MGT signal (1 RX and 1 TX)
Extension Boards
Figure 6-105. EB-PDS-FMC-LPC-R1 - Top View (FMC Side)
Caution
module).
Figure 6-106. EB-PDS-FMC-LPC-R1 Components
Extension Boards

This topic discusses extension board operating conditions of FMC LPC Mezzanine Board
Adapter (EB-PDS-FMC-LPC-R1).
Table 6-214. EB-PDS-FMC-LPC-R1 – Extension Board Operating Conditions


This topic discusses FPGA extension site compatibility of FMC LPC Mezzanine Board Adapter
(EB-PDS-FMC-LPC-R1).
In the table below, (1) MGT signal available
Table 6-215. EB-PDS-FMC-LPC-R1 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √(1) √(1) √ √ √
FM-XC7V2000T-R2 √ √ √(1) √(1) √ √ √
FM-XC7VX330T-R3 √(1) √(1) √
FM-XC7VX485T-R3 √(1) √(1) √
FM-XC7V585T-R3 √(1) √(1) √(1) √
FM-XC7VX690T-R3 √(1) √(1) √(1) √
FM-XC7Z100-R1 √(1) √(1)
FM-XC7Z045-R1 √(1) √(1)
FM-XCVU440-R1 √(1) √(1) √(1) √(1) √ √ √(1) √(1)
FM-XCVU440-R2 √(1) √(1) √(1) √(1) √ √ √(1) √(1)
FM-XCVU190-R1 √(1) √(1) √(1)
FM-XCVU160-R1 √(1) √(1) √(1)
FM-XCVU125-R1 √(1) √(1) √(1)
FM-XCVU095-R1 √(1) √(1) √(1)
Extension Boards
Table 6-215. EB-PDS-FMC-LPC-R1 – FPGA Extension Site Compatibility

V1 V1
FM-XCVU080-R1 √(1) √(1) √(1)
FM-XCKU115-R1 √(1) √(1) √(1)
FM-XCVU5P-R1 √(1) √(1) √(1)
FM-XCVU7P-R1 √(1) √(1) √(1)
FM-XCVU9P-R1 √(1) √(1) √(1)
FM-XCVU13P-R1 √(1) √(1) √ √
FM-XCVU19P-R1 √(1) √ √(1) √ √ √ √ √
FM-XCVU37P-R1 √(1) √(1) √(1)
FM-XCVU47P-R1 √(1) √(1) √(1)
FM-1SG280<L,H>-R1 √(1) √(1) √(1) √ √ √ √
FM-XCZU19EG-R2 √(1) √ √
FM-XCZU17EG-R2 √(1) √ √
FM-XCZU11EG-R2 √(1) √
FM-1SG280<L,H>-R2 √(1) √(1) √(1) √ √ √ √
FM-10AX115-R1 √(1) √(1) √(1) √(1)
FM-1SG10M-R1 √(1) √(1) √(1) √(1) √ √ √ √
Table 6-216. EB-PDS-FMC-LPC-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √(1) √(1) √(1) √(1)

This topic discusses FPGA pin constraints of FMC LPC Mezzanine Board Adapter (EB-PDS-
FMC-LPC-R1).
Extension Boards
Related Work
Table 6-217. EB-PDS-FMC-LPC-R1

<all> <any>
Related Work
This topic discusses related work of FMC LPC Mezzanine Board Adapter (EB-PDS-FMC-
LPC-R1).
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A1";
name = "EB-PDS-FMC-LPC-R1";
positions = ("motherboard_1.TA1” );
# which should be provided to the FMC
# mezzanine board
};
more information.
Caution

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-FMC-LPC-R1”. The
Extension Boards
Order Code
Order Code
This topic discusses order code of FMC LPC Mezzanine Board Adapter (EB-PDS-FMC-LPC-
R1).
286535
Extension Boards
FMC Carrier Board Adapter (FMC-PROFPGA-R1)
FMC Carrier Board Adapter (FMC-PROFPGA-

R1)
This topic discusses FMC Carrier Board Adapter (FMC-PROFPGA-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
This topic discusses functional description of FMC Carrier Board Adapter (FMC-PROFPGA-
R1).
The FMC Carrier Board Adapter provides a connection between an FMC carrier card and the
proFPGA system.
Main features of the adapter are:
• Two proFPGA cable connectors (top-side)

• One FMC HPC (high pin count) connector (bottom side)
• 40 MMCX connectors for MGT signals (10 MGT RX and TX pairs)
• Four MMCX connectors for MGT REFCLK signals (Two MGT Refclk pairs)
• One PSU for VIO voltage generation of Bank B signals (voltage can be set via jumper)
• Two proFPGA cables for connection are provided with the board
• The FMC DP[0-9]_C2M_[NP] signals are AC-coupled (100nF)
Extension Boards
Figure 6-107. FMC-PROFPGA-R1
In the figure below, each FMC bank requires a dedicated FMC cable (IC-PDS-FMC-CABLE-
A-R1 (40 cm), IC-PDS-FMC-CABLE-B-R1 (40 cm), IC-PDS-FMC-CABLE-A-R2 (80 cm),
IC-PDS-FMC-CABLE-B-R2 (80 cm))
Figure 6-108. FMC-PROFPGA-R1 - Two cables to connect to the proFPGA

system
If only the regular IOs should be connected with the proFPGA system, the system setup shown
in Figure 6-109 can be used. In this setup the IC-PDS-FMC-… cables are directly plugged on
the proFPGA FPGA module.
Extension Boards
If MGTs should be connected as well the system setup of Figure 6-110 can be used. In this case
an additional EB-PDS-MGT-MMCX-R1 board is used to make the MGT connections via
MMCX BNC cables.
Figure 6-109. FMC-PROFPGA-R1: Connection Example Schematic without MGT

Connections
Figure 6-110. FMC-PROFPGA-R1 - Connection Example Schematic with MGT

Connections
Table 6-218. Jumper Settings for VIO Voltage

Jumper pins VIO Voltage
1–2 1.2V
3–4 1.5V
5–6 1.8V
7–8 2.5V
9 – 10 3.3V
Extension Boards
Caution
systems which need to be connected (the proFPGA system and the FMC carrier card).
Especially for FMC_VIO_B_M2C which is generated by the mezzanine board and the VADJ
voltage which is generated by the FMC carrier card, the user needs to take care about the correct
IO voltage levels. For example, the FM-XC7V2000T-R2 supports PV_IO voltage levels up to
1.8V only.
For example, if a Zynq-7000 SoC ZC706 Evaluation Kit should be connected to an FM-
XC7V2000T-R2 FPGA module of a proFPGA system the I/O voltage FMC-VADJ of the
ZC706 must be changed to 1.8V (the default value is 2.5V) because the XC7V2000T FPGA
does not support I/O voltages higher than 1.8V. In the same regards the PV_IO voltage of the
used proFPGA connectors must be programmed to P1V8 as well.

• FMC I2C signals are ignored and left unconnected
• FMC GA signals are ignored and left unconnected
• CLK_DIR signal is not supported
Figure 6-111. Components of the FMC Carrier Board Adapter
Extension Boards

This topic discusses extension board operating conditions of FMC Carrier Board Adapter
(FMC-PROFPGA-R1).
Table 6-219. FMC-PROFPGA-R1 – Extension Board Operating Conditions

Top-side extension board connector two proFPGA connectors

This topic discusses FPGA extension site compatibility of FMC Carrier Board Adapter (FMC-
PROFPGA-R1).
In the table below, (M) MGT signals are available,
(1)
only 1 FPGA bank,
(2)only
2 FPGA banks,
(3)
(4)
only 3 HD banks available (72 IOs),
(5)
only 2 HD banks available (48 IOs).
Table 6-220. FMC-PROFPGA-R1 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √(M) √ √ √ √(M
,1)
FM-XC7V2000T-R2 √ √ √(M) √(M) √ √ √ √(1)
FM-XC7VX330T-R3 √(M) √(1) √(M √(M) √ √(1)
,1)
FM-XC7VX485T-R3 √(M) √(1) √(M √(M) √ √(1)
,1)
FM-XC7V585T-R3 √(M) √(M √(M) √(M) √ √(1)
,2)
Extension Boards
Table 6-220. FMC-PROFPGA-R1 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XC7VX690T-R3 √(M) √(M √(M) √(M) √ √(1)
,2)
FM-XC7Z100-R1 √(M √(M)
,2)
FM-XC7Z045-R1 √(M √(M)
,2)
FM-XCVU440-R1 √(M) √(M) √(M) √(M) √(M) √(M) √ √ √(1)( √(1)(
3) 3)
FM-XCVU440-R2 √(M) √(M) √(M) √(M) √(M) √(M) √ √ √(1)( √(1)(

3) 3)
FM-XCVU190-R1 √(M) √(M) √(M) √(M √(1) √(1)

,2)
FM-XCVU160-R1 √(M) √(M) √(M) √(M √(1) √(1)
,2)
FM-XCVU125-R1 √(M) √(M) √(M) √(M √(1) √(1)
,2)
FM-XCVU095-R1 √(M) √(M) √(M) √(M √(1) √(1)
,2)
FM-XCVU080-R1 √(M) √(M) √(M) √(M √(1) √(1)
,2)
FM-XCKU115-R1 √(M) √(M) √(M) √(M √(1) √(1)
,2)
FM-XCVU5P-R1 √(M) √(M) √(M) √(M √(1) √(1)
,2)
FM-XCVU7P-R1 √(M) √(M) √(M) √(M √(1) √(1)
,2)
FM-XCVU9P-R1 √(M) √(M) √(M) √(M √(1) √(1)
,2)
FM-XCVU13P-R1 √(M) √(M) √ √ √(1)
FM-XCVU19P-R1 √(M) √ √(M) √ √ √ √ √ √(5)( √(5)(
3) 3)
FM-XCVU37P-R1 √(M) √(M) √(M √(M)

,1)
Extension Boards
Table 6-220. FMC-PROFPGA-R1 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU47P-R1 √(M) √(M) √(M √(M)
,1)
FM-1SG280L-R1 √ √(M) √(M) √ √ √ √
(M)
FM-XCZU19EG-R2 √(M) √(M √

,4)
FM-XCZU17EG-R2 √(M) √(M √
,4)
FM-XCZU11EG-R2 √(M) √(M
,4)
FM-1SG280H-R<1,2> √ √(M) √(M) √ √ √ √
(M)
FM-1SG280<L,H>-R2 √ √(M) √(M) √ √ √ √

(M)
FM-10AX115-R1 √ √ √ √
(M) (M) (M) (M)
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(

(M) (M) (M) (M) 3) 3)
Table 6-221. EB-PDS-FMC-PROFPGA-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ (M) √ (M) √ √

This topic discusses FPGA pin constraints of FMC Carrier Board Adapter (FMC-PROFPGA-
R1).
Table 6-222. FMC-PROFPGA-R1 – FPGA Pin Constraint

<all> <any>
Extension Boards
Related Work
Related Work
This topic discusses related work of FMC Carrier Board Adapter (FMC-PROFPGA-R1).
profpga_run
<cable1>:
{
type = "BOARD";
size = "A1A1";
name = "IC-PDS-FMC-CABLE-B-R1";
positions = ( "<position1>" );
top_connectors = ( );
v_io_ba1 = "<voltage1>";
};
<cable2>:
{
type = "BOARD";
size = "A1A1";
name = "IC-PDS-FMC-CABLE-A-R1";
positions = ( "<position2>" );
v_io_ba1 = "<voltage2>";
};
Instance names <cable1> and <cable2> and position entries <position1> and <position2> must
be replaced with the correct value according to the system configuration. Please refer to the
„proFPGA Software Reference Manual” [UD002] for more information. The voltage entries
<voltage1> and <voltage2> must be set to the correct values. The name of the cable depends on
the selected cable length, IC-PDS-FMC-CABLE-<A,B>-R1 for 40 cm and IC-PDS-FMC-
CABLE-<A,B>-R2 for 80cm.
Caution
Special care must be taken to set the voltage values for both cable instances. They must
match the capabilities of the proFPGA FPGA module and the FMC carrier card and must
not exceed the maximum IO voltage values of both components. If the maximum IO voltage
values will be exceeded the FPGA module and/or FMC carrier card will be damaged.

plugged onto.
contains a valid x-board entry using the extension board name “FMC-PROFPGA-A-R1” and
Extension Boards
Order Code
“FMC-PROFPGA-B-R1”. The system configuration file can be created directly or with the
Order Code
This topic discusses order code of FMC Carrier Board Adapter (FMC-PROFPGA-R1).

FMC-PROFPGA-R1 286544
proFPGA Interconnection Cable for FMC 286532
Adapter A
proFPGA Interconnection Cable for FMC 286533
Adapter B
Extension Boards
USB 3.0 Board (EB-PDS-USB3-R1)
USB 3.0 Board (EB-PDS-USB3-R1)

This topic is about USB 3.0 Board (Eb-PDS-USB3-R1)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
proFPGA USB 3.0 Board provides two USB 3.0 A female connectors which can be used either
in host or in device mode. The USB 3.0 connection is provided with the TUSB1310A from
Texas Instruments. All IO and Clock IO pins of the extension board bottom connector are used.
The MGT ports are not used. So it’s preferred to put this board onto an FPGA connector without
MGT ports or to put in onto an extension board with top connector which uses the MGT ports
and only a short amount of IO pins.
• proFPGA USB 3.0 daughter card, which will be plugged on a free extension site of the
proFPGA FPGA Module
• Two AK669/3-3-R cables for use in host mode
• Two AK670/3-2-R cables for use in device mode
Figure 6-112. proFPGA USB 3.0 Kit (USB 3.0 Board, USB 3.0 A Male - A Female
Cable, USB 3.0 A Male - A Male Cable)
Extension Boards
The figure below shows the pin assignment of the USB 3.0 board bottom connector.
Figure 6-113. Signal Connections of the proFPGA USB 3.0 Board Bottom
Connector
The nets are named to their corresponding function of the TUSB1310A. The signals are divided
into several priority regions:
1. The first four IOs are connected to control the user LEDs.
2. USB port 1 high priority signals
3. USB port 2 high priority signals
4. USB port 1 low priority signals
5. USB port 2 low priority signals
All IO signals connected to Clock IO pins are high priority signals. All low priority signals are
also connected to DIP switches.
Note
If the low priority signals should be controlled by FPGA, the DIP switches have to be set to
“off” state
Extension Boards
Priority regions have been introduced to support a large range of IO signal count. The proFPGA
USB 3.0 board can be stacked on other extension board, which reduces the number of available
IO signal connections to the FPGA. The following use cases are supported:
• 2 USB ports, configuration pins driven by FPGA (all IO signals connected to FPGA)
• 2 USB ports, configuration pins driven by DIP switches (low-priority signals
unconnected)
• 1 USB port, configuration pins driven by DIP switches (low-priority signals and USB
port 2 high-priority signals unconnected)
The signals USB3_[1,2]_nEN_P5V0_OUT for activating the external 5 V for each port (used in
USB host mode) are active low.
Peripherals
• Four user LEDs

o USER_LED1- red - LED on means signal is high
o USER_LED2- yellow - LED on means signal is high
o USER_LED3- yellow- LED on means signal is high
o USER_LED4 - green- LED on means signal is high
• Three LEDs for each port which display the status of
o PWRPRESENT- green - LED on means signal is high
o POWERDOWN0 - yellow- LED on means signal is high
o POWERDOWN1 - yellow- LED on means signal is high
• Three DIP switches for each TUSB1310A USB chip are available. Each DIP switch
controls input signals of the TUSB1310. As described before, a large amount of the
signals can also be controlled by FPGA. In this case the DIP switches for these signals
have to be set to “off” state.
“off” means binary “0”
“on” means binary “1”
For S3 / S6 applies switch at pin 1 – on, switch at pin 3 – off
Table 6-223. DIP Switches of the USB 3.0 Board and the Connected Signals
USB PORT USB PORT # Signal off on
1 2
S1 S4 1 PHY_MODE 0k pull-down 225R pull-up
0
Extension Boards
Table 6-223. DIP Switches of the USB 3.0 Board and the Connected Signals
USB PORT USB PORT # Signal off on
1 2
2 PHY_MODE 0k pull-down 225R pull-up
1
3 OUT_ENAB 0k pull-down 225R pull-up
LE
4 TX_ONESZ 0k pull-down 225R pull-up
EROS
S2 S5 1 TX_DEEMP 10k pull- 225R pull-up
H1 down
2 TX_DEEMP 10k pull- 225R pull-up
H0 down
3 TX_MARGI 10k pull- 225R pull-up
N2 down
N1 down
N0 / down
SSC_DIS
6 TX_SWING 10k pull- 225R pull-up
down
7 RX_POLARI 10k pull- 225R pull-up
TY down
8 RX_TERMI 10k pull- 225R pull-up
NATION down
9 RATE 10k pull- 225R pull-up
down
10 ELAS_BUF_ 10k pull- 225R pull-up
MODE down
S3 S6 1 ULPI_DATA 10k pull- 10k pull-up
7/ down
ISO_START
• JTAG of the TUSB1310A is not connected.
• Preconfigured strap signals of the TUSB1310A:
o RX_ELECIDLE / XTAL_DIS - 10k pull-down
o TX_ELECIDLE - 10k pull-down
Extension Boards
o ULPI_DATA6 / ULPI_8BIT - 10k pull-down

o ULPI_DATA5 / REFCLK_SEL1 - 10k pull-up
o ULPI_DATA4 / REFCLK_SEL0 10k pull-up

Table 6-224. EB-PDS-USB3-R1 – Extension Board Operating Conditions

IO voltage provider FPGA module for FPGA Bank and USB 3.0
board for itself

In the table below, (a) Only Port 1 can be used
Table 6-225. EB-PDS-USB3-R1 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √(a) √ √ √
FM-XC7VX690T-R3 √ √(a) √ √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
Extension Boards
Table 6-225. EB-PDS-USB3-R1 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √ √ √
FM-XCVU080-R1 √ √ √
FM-XCKU115-R1 √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280L-R1 √(a) √(a) √(a) √(a) √(a) √(a) √(a)
FM-XCZU19EG-R2 √ √ √(a) √(a)
FM-XCZU17EG-R2 √ √ √(a) √(a)
FM-XCZU11EG-R2 √ √ √(a) √
FM-1SG280H-R<1,2> √(a) √(a) √(a) √(a) √(a) √(a) √(a)
FM-10AX115-R1 √(a) √(a) √(a) √(a)
FM-1SG10M-R1 √(a) √(a) √(a) √(a) √(a) √(a) √(a) √(a)
Table 6-226. EB-PDS-USB3-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1 √(a) √(a) √(a) √(a) √(a) √(a)
FM-XCVU19P-R1 √ √ √ √

Extension Boards
Related Work
Table 6-227. EB-PDS-USB3-R1 – FPGA Pin Constraints

LVCMOS18
Related Work
profpga_run
<instance name>:
{
type = "BOARD";
name = "EB-PDS-USB3-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-USB3-R1”. The
Please refer to the „proFPGA Software Reference Manual” [UD002] and the “proFPGA Builder
User Manual” [UD004] for more information.
Startup with USB3 Extension Board

The TUSB1310A Chip drives the IO pins of the FPGA before the PV_IO voltage of the FPGA
is applied. Therefore, the proFPGA Host software will bring an error at startup. To avoid this
error, the entry v_io_ta1_force = 1; has to be added to the cfg file for the according FPGA
Extension Boards
Order Code
module and voltage in respect to the connector where the board is plugged. The _ta1_ entry has
to be changed to the connector where the board is plugged onto. Possible options are [ta1, ta2,
tb1, tb2, ba1, ba2, bb1, bb2].
Order Code
286511
Extension Boards
USB 2.0(UTMI) & 3.0(ULPI) Interface Board (EB-PDS-USB2-3-R1/R2)
USB 2.0(UTMI) & 3.0(ULPI) Interface Board

(EB-PDS-USB2-3-R1/R2)
This topic is about USB 2.0(UTMI) & 3.0(ULPI) Interface Board (EB-PDS-USB2-3-R1/R2)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
This extension board has two USB ports. One USB port is available through a mini USB
connector and is connected to a USB3250 (Microchip). The USB3250 is a hi-speed USB device
transceiver with UTMI interface. This USB port can be used to implement a USB 2.0 device in
the FPGA with UTMI interface.
Caution
EB-PDS-USB2-3-R2/R3 is required if 12 Mbit/s Full Speed (USB 1.0) is needed!
Otherwise, the LINESTATE signals are not available if using EB-PDS-USB2-3-R1.
However, both devices support 480 Mbit/s High Speed (USB 2.0).
Conditions:
• USB3250 is used.
• Windows operating system is used.
• PC is booted before the design is loaded into the FPGA.
• The board is already connected via USB cable to the PC.
Extension Boards
Caution
If the board is used under these conditions, the device manager will identify the board as
“Unknown device”. This can only be reset by unplugging and then replugging the USB
cable.
• On the EB-PDS-USB2-3-R3 the USB2_TERMSELECT signal has a pull down. This

resolves the above-described issue so that the USB3250 will be detected only after the
design is loaded.
The second USB port is available through a USB A female connector and is connected to a
TUSB1310A (Texas Instruments). The TUSB1310A is a USB 3.0 Transceiver which can be
either used as an USB host or device. To avoid incompatibilities with the USB 3.0 connector in
host or device mode, two different USB 3.0 cables are delivered to fit both options. In host
mode the VUSB is generated on the extension board itself. Up to 1.5 A can be delivered to the
device. In device mode, the VUSB on the extension board can be disabled.
Twelve LEDs are on the extension board which can be programmed by user. There are blue,
green, red and yellow LEDs on the board. Each color is three times available.
One GPIO header is on the board where 18 FPGA pins are connected and can be used for debug
purposes. The GPIOs are directly connected to the FPGA so be careful by using these pins for
input into the FPGA that the voltage levels do not exceed 1.8 V. 1.8 V are connected to pin 1
and 2. On pin 21 and 22 GND is connected.
One 14-pin JTAG connector is on the board. The pins are connected to FPGA pins. The layout
of the JTAG connector is related to ARM JTAG.
All IO and Clock IO pins of the extension board bottom connector are used. The MGT ports are
not used. So it’s preferred to put this board onto an FPGA connector without MGT ports or to
put in onto an extension board with top connector which uses the MGT ports and only a short
amount of IO pins.
Features in short overview:
• Mini USB connector connected to USB3250 (USB 2.0 device mode)

• USB A female connector connected to TUSB1310A (USB 3.0 device and host mode)
• 12 user LEDs (3x blue, 3x green, 3x red, 3x yellow) connected to FPGA pins
• GPIO header with 18 FPGA signals, 2x 1.8 V, 2x GND
• 14-pin JTAG connector (ARM JTAG)
Extension Boards
Figure 6-114. proFPGA USB2-3-R1/R2/R3 Kit (USB2-3-R1/R2/R3 Board, USB 3.0

A Male - A Female Cable, USB 3.0 A Male - A Male Cable)
Peripherals
• Mini USB connector and USB3250

o The nets in the csv / xdc files correspond to the pin names of the USB3250. All
signals are connected with unidirectional level translators to the bottom connector of
the extension board. The direction of the USB2_DATA[0..7] and
USB2_DATA[8..15] can be controlled with FPGA pins. The signals for the
direction are USB2_DIR_DATA_0_7 and USB2_DIR_DATA_8_15. Logic 0 sets
the direction from the USB3250 to the FPGA. Logic 1 sets the direction from the
FPGA to the USB3250. When using the 8-bit unidirectional mode,
USB2_DATABUS16_8 and USB2_DIR_DATA_8_15 has to be driven low and
USB2_DIR_DATA_0_7 has to be driven high. In this case the data on
USB2_DATA[0..7] will be transmitted from the FPGA to the USB3250 and the data
on USB2_DATA[8..15] will be received by the FPGA.
o The USB3250 is connected to a 12 MHz crystal.
• USB A female connector and TUSB1310A
o The USB A female connector is connected to the TUSB1310A.
o The TUSB1310A is connected to a 40 MHz crystal.
o Switch S3 controls a 10k pull-up on ISO_START (switch in direction of pin 1) or a
10k pull-down on ISO_START (switch in direction of pin 3).
o JTAG of the TUSB1310A is not connected.
Extension Boards
o RX_ELECIDLE / XTAL_DIS 10k pull-down

o TX_ELECIDLE 10k pull-down
o ULPI_DATA6 / ULPI_8BIT 10k pull-down
o In host mode the 5 V output voltage to VBUS can be enabled by setting the signal
USB3_EN_P5V0_OUT high.
o The following points describes the silkscreen on the board, the function in respect to
the TUSB1310A, the color of the connected LED and the active level of the LED:
o PRESEN - PWRPRESENT- green - LED on means signal is high
o DOWN0 - POWER DOWN0 - yellow - LED on means signal is high
o DOWN1 - POWER DOWN1 - yellow - LED on means signal is high
• The 12 user LEDs are controlled by FPGA. A high signal at the output pin of the FPGA
means the LED is on.
• The pin assignment of the user GPIO header can be seen in the figure below.
Figure 6-115. Pin Assignment of User GPIO Header
• The pin assignment of the user JTAG connector can be seen in the figure below.
Extension Boards
Figure 6-116. Pin Assignment of User JTAG Connector

Table 6-228. EB-PDS-USB2-3-R1/R2/R3 – Extension Board Operating

Conditions

In the table below, (a) Only USB 3.0 Port can be used, (b) USER LEDs and USER GPIOs don’t
work, (c) USER GPIO 01 doesn’t work
Table 6-229. EB-PDS-USB2-3-R1/R2/R3 – FPGA Extension Site Compatibility
FPG TA1 TA2 TB1 TB2 BA1 BA2 BB1 BB2 TA1V TA2V
A 1 1
Modu
le
FM- √ √ √ √ √ √ √
XC7V
2000T
-R1
FM- √ √ √ √ √ √ √
XC7V
2000T
-R2
Extension Boards

A 1 1
Modu
le
FM- √ √ √
XC7V
X330
T-R3
FM- √ √ √
XC7V
X485
T-R3
FM- √ √(a) √ √ √
XC7V
585T-
R3
FM- √ √(a) √ √ √
XC7V
X690
T-R3
FM- √(a,b) √(c)
XC7Z
100-
R1
FM- √(a,b) √(c)
XC7Z
045-
R1
FM- √ √ √ √ √ √ √ √
XCV
U440-
R1
FM- √ √ √ √ √ √ √ √
XCV
U440-
R2
FM- √ √ √
XCV
U190-
R1
Extension Boards

A 1 1
Modu
le
FM- √ √ √
XCV
U160-
R1
FM- √ √ √
XCV
U125-
R1
FM- √ √ √
XCV
U095-
R1
FM- √ √ √
XCV
U080-
R1
FM- √ √ √
XCK
U115-
R1
FM- √ √ √
XCV
U5P-
R1
FM- √ √ √
XCV
U7P-
R1
FM- √ √ √
XCV
U9P-
R1
FM- √ √ √ √
XCV
U13P-
R1
Extension Boards

A 1 1
Modu
le
FM- √ √ √ √ √ √ √ √
XCV
U19P-
R1
FM- √ √ √
XCV
U37P-
R1
FM- √ √ √
XCV
U47P-
R1
FM- √ √ √ √ √ √ √
1SG2
80<L,
H>-
R1
FM- √ √ √ √
10AX
115-
R1
FM- √ √ √ √ √ √ √ √
1SG1
0M-
R1
Table 6-230. EB-PDS-USB2-3-R1/R2/R3 – FPGA Extension Site Compatibility,

Module
√ √ √ √ √ √
√ √ √ √

Extension Boards
Related Work
Table 6-231. EB-PDS-USB2-3-R1/R2/R3 –FPGA Pin Constraints

LVCMOS18
Related Work
profpga_run
<instance name>:
{
type = "BOARD";
name = "EB-PDS-USB2-3-R1"; # R2 or R3 for other revisions
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-USB2-3-R1” (R2 or
R3 for other revisions). The system configuration file can be created directly or with the
Startup with USB3 Extension Board

The TUSB1310A Chip drives the IO pins of the FPGA before the PV_IO voltage of the FPGA
is applied. Therefore, the proFPGA Host software will bring an error at startup. To avoid this
Extension Boards
Order Code
Order Code
EB-PDS-USB2-3-R2: 286510
EB-PDS-USB2-3-R3: Order Code missing
Extension Boards
GBit Ethernet Board (EB-PDS-GBITETHERNET-R1)
GBit Ethernet Board (EB-PDS-

GBITETHERNET-R1)
This topic is about GBit Ethernet Board (EB-PDS-GBITETHERNET-R1)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
proFPGA GBit Ethernet Board provides two GBit Ethernet RJ45 connectors. The GBit Ethernet
connection is provided with the DP83865DVH PHY from Texas Instruments.
• two GBit Ethernet PHYs (DP83865DVH) supporting 10m/100M/1G and MII/GMII/

RGMII
• all boot-strap signals are software programmable using the profpga_run tool
• five status LEDs per PHY (duplex, 1G, 100M, 10M, activity)
• proFPGA top connector to make unused FPGA signals available
Extension Boards
Figure 6-117. proFPGA GBit Ethernet Extension Board

Table 6-232. EB-EB-PDS-GBITETHERNET-R1 – Extension Board Operating

conditions
extension board for itself
Top-side extension board connector yes (to connect IC-PDS-CABLE-R1 only)

(a)
Only Port 1 can be used, (b) using EB-FM-XCVU440-R1
Extension Boards
Table 6-233. EB-PDS-GBITETHERNET-R1 – FPGA Extension Site

Compatibility.
A 1 1
Modu
le
FM- √ √ √ √ √ √ √
XC7V
2000T
-R1
FM- √ √ √ √ √ √ √
XC7V
2000T
-R2
FM- √ √(a) √ √
XC7V
X330
T-R3
FM- √ √(a) √ √
XC7V
X485
T-R3
FM- √ √ √ √ √
XC7V
585T-
R3
FM- √ √ √ √ √
XC7V
X690
T-R3
FM- √(a) √
XC7Z
100-
R1
FM- √(a) √
XC7Z
045-
R1
FM- √ √ √ √ √ √ √ √ √(a)(b) √(a)(b)
XCV
U440-
R1
Extension Boards

A 1 1
Modu
le
FM- √ √ √ √ √ √ √ √ √(a)(b) √(a)(b)
XCV
U440-
R2
FM- √ √ √ √
XCV
U190-
R1
FM- √ √ √ √
XCV
U160-
R1
FM- √ √ √ √
XCV
U125-
R1
FM- √ √ √ √
XCV
U095-
R1
FM- √ √ √ √
XCV
U080-
R1
FM- √ √ √ √
XCK
U115-
R1
FM- √ √ √ √
XCV
U5P-
R1
FM- √ √ √ √
XCV
U7P-
R1
Extension Boards

A 1 1
Modu
le
FM- √ √ √ √
XCV
U9P-
R1
FM- √ √ √ √
XCV
U13P-
R1
FM- √ √ √ √ √ √ √ √ √(a)(b) √(a)(b)
XCV
U19P-
R1
FM- √ √ √
XCV
U37P-
R1
FM- √ √ √
XCV
U47P-
R1
FM- √ √ √ √ √ √ √
1SG2
80<L,
H>-
R1
FM- √ √ √ √
10AX
115-
R1
FM- √ √ √ √ √ √ √ √
1SG1
0M-
R1
Extension Boards
Table 6-234. EB-PDS- GBITETHERNET-R1– FPGA Extension Site

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Table 6-235. EB-PDS-GBITETHERNET-R1 –FPGA Pin Constraints

LVCMOS18
Related Work
profpga_run
The boot-strap signals of both GBit Ethernet PHYs will be set with a profpga plugin. To load
the plugin the plugin_list entry before the system_configuration section must be added:
...
plugin_list = ( "dp83865dvh ProDesign EB-PDS-GBITETHERNET-R1" );
{
...
...
plugin_list = ("si5338 ProDesign EB-PDS-DVI-R1",
"dp83865dvh ProDesign EB-PDS-GBITETHERNET-R1" );
{
...
This will load the dp83865dvh plugin, which is part of the 2014A release. This plugin reads the
boot strap configuration parameter from the related section of the extension board instance and
Extension Boards
Related Work
apply thee to the PHY chip before FPGA configuration.For this board the following x-board
entry is required within the system configuration file:
<instance name>:
{
type = "BOARD";
name = "EB-PDS-GBITETHERNET-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
#--- Configuration options ----------------------
# CLK_MAC_FREQ
# 1 CLOCK TO MAC output is 125 MHz
# 0 CLOCK TO MAC output is 25 MHz
#------------------------------------------------
# MAN_MDIX
# 1 PHY is manually set to cross-over mode (MDIX)
# 0 PHY is manually set to straight mode (MDI)
#------------------------------------------------
# MAC_CLK_EN
# 1 CLK_TO_MAC clock output enabled
# 0 CLK_TO_MAC disabled
#------------------------------------------------
# MDIX_EN
# 1 enables pair swap mode
# 0 disables the Auto-MDIX and defaults the part into the
mode preset by the MAN_MDIX_STRAP pin.
#------------------------------------------------
# MULTI_EN
# 1 Selects multiple node priority (switch or hub)
# 0 Selects single node priority (NIC)
#--------------------------------------------
# | RGMII_SEL1| RGMII_SEL0| MAC Interface
# ---------------------------------------
# | 0 | 0 | GMII
# | 0 | 1 | GMII
# | 1 | 0 | RGMII - HP
# | 1 | 1 | RGMII - 3COM
#--------------------------------------------
# PHY ADDRESS [4:1]: The DP83865 provides five PHY address-
# sensing pins for multiple PHY applications.
# The setting on these five pins provides the base
# address of the PHY. The five PHYAD[4:0] bits are
# registered as inputs at reset with PHYADDR4 being
# the MSB of the 5-bit PHY address.BIT 0 is fixed
# to logic 1
#-------------------------------------------------------------
# ACT_SPEED0 and LNK10_SPEED1
#
# Auto-Neg disabled:
#
# | Speed[1] | Speed[0] | Speed enabled
# ---------------------------------------
# | 1 | 1 | Reserved
# | 1 | 0 | 1000BASE-T
Extension Boards
Related Work
# | 0 | 1 | 100BASE-TX
# | 0 | 0 | 10BASE-T
#
# Auto-Neg enabled:
#
# | Speed[1] | Speed[0] | Speed enabled
# ---------------------------------------
# | 1 | 1 | 1000BASE-T, 10BASE-T
# | 1 | 0 | 1000BASE-T
# | 0 | 1 | 1000BASE-T, 100BASE-TX
# | 0 | 0 | 1000BASE-T, 100BASE-TX, 10BASE-T
#-------------------------------------------------------------
# LNK1G_AUTO_NEG
# 1 Enables Auto-Neg
# 0 Disables Auto-Neg
#-------------------------------------------------------------
# LNK100_DUPLEX
# 1 Enables Full Duplex by default
# 0 Enables Half Duplex only
#-------------------------------------------------------------
eth_phy1:
{
CLK_MAC_FREQ = 0;
MAN_MDIX = 0;
MAC_CLK_EN = 0;
MDIX_EN = 0;
MULTI_EN = 0;
RGMII_SEL0 = 0;
RGMII_SEL1 = 0;
PHY_ADDR1 = 0;
PHY_ADDR2 = 0;
PHY_ADDR3 = 0;
PHY_ADDR4 = 0;
ACT_SPEED0 = 0;
LNK10_SPEED1 = 0;
LNK1G_AUTO_NEG = 1;
LNK100_DUPLEX = 1;
}
eth_phy2:
{
CLK_MAC_FREQ = 0;
MAN_MDIX = 0;
MAC_CLK_EN = 0;
MDIX_EN = 0;
MULTI_EN = 0;
RGMII_SEL0 = 0;
RGMII_SEL1 = 1;
PHY_ADDR1 = 0;
PHY_ADDR2 = 0;
PHY_ADDR3 = 0;
PHY_ADDR4 = 0;
ACT_SPEED0 = 0;
LNK10_SPEED1 = 0;
LNK1G_AUTO_NEG = 1;
LNK100_DUPLEX = 1;
}
};
Extension Boards
Order Code
more information.The eth_phy1 and eth_phy2 section must be adjusted according to the design
requirements (see also the DP83865DVH data sheet for more details).

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-GBITETHERNET-
R1”. The system configuration file can be created directly or with the profpga_builder tool.
Startup with GBit Ethernet Extension Board

The board drives the IO pins of the FPGA before the PV_IO voltage of the FPGA is applied.
Therefore, the proFPGA Host software will bring an error at startup.
To avoid this error, the entry v_io_ta1_force = 1; has to be added to the cfg file for the
according FPGA module and voltage in respect to the connector where the board is plugged.
The _ta1_ entry has to be changed to the connector where the board is plugged onto. Possible
options are [ta1, ta2, tb1, tb2, ba1, ba2, bb1, bb2].
Note
When using RGMII as protocol the clock has to be shifted 1.5-2ns in relation to the used
clock. This has either to be taken care of in the design itself by using delaying elements or
by using the 3COM mode where the PHY handles this by itself.
Note
Before using the Ethernet interface inside the logic, the nReset signal of the used PHY has
to be toggled once so that the strap pins are being read in by the PHY correctly. Otherwise,
it is not reliable if the settings which have been made in the configuration file will be applied
always.
Order Code
286512
Extension Boards
DVI Input and Output Board (EB-PDS-DVI-R1)
DVI Input and Output Board (EB-PDS-DVI-R1)

This topic is about DVI Input and Output Board (EB-PDS-DVI-R1)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
proFPGA DVI Board provides a DVI input and a DVI output with HDMI connectors.
• one Transmitter (TI TFP410)

• one Receiver (TI TFP403)
• two HDMI connectors
• DVI 1.0 compliant
• up to 165 MHz pixel rates (including 1080p and WUXGA @ 60Hz)
• EDID I2C at transmitter side, to read DVI receiver EEPROM
• 4Kbit EDID EEPROM at receiver side
• Hot plug detection
• over current protection
• one configurable clock generator (Silicon Labs SI5338C) provides up to 4 reference
clocks
• clock generator programmable by the profpga_run tool
• eight general purpose LEDs
• one Mictor-38 debug header
Extension Boards
• proFPGA DVI daughter card, which will be plugged on a free extension site of the
proFPGA FPGA Module
• Two HDMI cables (for use with DVI connectors an HDMI to DVI adapter is required,
not included)
Figure 6-118. EB-PDS-DVI-R1
The beneath image shows the structure of the board.
Extension Boards
Figure 6-119. EB-PDS-DVI-R1 Board Overview
Table 6-236. Signal Description (Bottom Connector)

Signal Signal Description
DVI output
DVI_OUT_nOC over current detection (active low), indicates an overcurrent (I
> 500mA) at 5V Pin of the DVI output HDMI connector
DVI_OUT_nHP hot plug detect (active low), indicates a connected DVI device
(e.g. Monitor)
DVI_OUT_EDID_SDA EDID I2C to read the EDID EEPROM of DVI devices
DVI_OUT_EDID_SCL
DVI_OUT_* the other signals are named to their corresponding function of
the DVI transmitter (TFP410), refer datasheet for detailed
information
DVI input
DVI_IN_EDID_SDA EDID I2C to configure the onboard EDID EEPROM
DVI_IN_EDID_SCL
Extension Boards
Table 6-236. Signal Description (Bottom Connector) (cont.)

DVI_IN_* the other signals are named to their corresponding function of
the DVI receiver (TFP403), refer datasheet for detailed
information
Reference clocks
REF_CLK* Reference clock provided by the Si5338
LEDs
LED* general purpose LEDs
Debug header
DBG_CLK bidirectional clock signal
DBG_DATA_A* bidirectional data signal connector’s A side
DBG_DATA_B* bidirectional data signal connector’s B side
Table 6-237. Pin Assignment Debug Header

Signal Pin Pin name Signal Pin Pin name
number number
nc 1 A1 nc 2 B1
GND 3 A2 nc 4 B2
DBG_CLK 5 A3 nc 6 B3
DBG_DATA_A0 7 A4 DBG_DA 8 B4
TA_B0
TA_B1
TA_B2
TA_B3
TA_B4
TA_B5
TA_B6
TA_B7
Extension Boards
Table 6-237. Pin Assignment Debug Header (cont.)

Signal Pin Pin name Signal Pin Pin name
number number
TA_B8
TA_B9
nc 27 A14 nc 28 B14
nc 29 A15 nc 30 B15
nc 31 A16 nc 32 B16
nc 33 A17 nc 34 B17
nc 35 A18 nc 36 B18
nc 37 A19 nc 38 B19

Table 6-238. EB-PDS-DVI-R1– Extension Board Operating Conditions


In the table below, (1) Only DVI Output (without EDID I2C) can be used.
Table 6-239. EB-PDS-DVI-R1– FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
Extension Boards
Table 6-239. EB-PDS-DVI-R1– FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √(1)
FM-XCVU160-R1 √ √ √ √(1)
FM-XCVU125-R1 √ √ √ √(1)
FM-XCVU095-R1 √ √ √ √(1)
FM-XCVU080-R1 √ √ √ √(1)
FM-XCKU115-R1 √ √ √ √(1)
FM-XCVU5P-R1 √ √ √ √(1)
FM-XCVU7P-R1 √ √ √ √(1)
FM-XCVU9P-R1 √ √ √ √(1)
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Extension Boards
Table 6-240. EB-PDS-DVI-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Table 6-241. EB-PDS-DVI-R1–FPGA Pin Constraints

LVCMOS18
Related Work
EDID EEPROM
The board provides a 4Kbit EDID EEPROM at the DVI receiver side. This EEPROM is not
programmed by Siemens. Some DVI sources (e.g. PC) need valid entries in the EEPROM for
proper operations. In these cases the EEPROM need to be programmed with timing and
resolution parameters supported by the FPGA design. The content of the EEPROM is specified
in the VESA Enhanced EDID Standard.
Caution
Disconnect the cable from the DVI input connector during the configuration of EEPROM.

The Si5338 is an optional clock source. Thus this section can be skipped, if the Si5338 will not
be used.The profpa_run tool requires a register map file to configure the output clocks of the
Si5338. This file can be generated by the ‘Clock Builder Desktop’ (old version) or ‘Clock
Builder Pro Software’ (new version) from SiLabs. It can be downloaded here:
http://www.silabs.com/products/clocksoscillators/Pages/Timing-Software-Development-
Tools.aspx
Extension Boards
Related Work
Using Clock Builder Desktop
Figure 6-120 on page 615 shows the Frequency Plan tab of the SiLabs Clock Builder. The
output frequencies in this picture are just examples and can be changed to the desired frequency.
Furthermore it is not necessary to use all outputs. Several steps are necessary to generate the
register map file for the Si5338.
1. Choose the Input Configuration Crystal (8-30MHz)

2. Enter the Frequency 25 MHz
3. Choose your Output Frequencies by adding respectively skipping
4. Press Create Plan
5. Press Apply Values to Register Map
After configuring the frequency plan select the Output Drivers tab (Figure 6-121 on
page 616).
6. set Output Type: Format and Voltage of each used output to 1.8V CMOS on A
Note
For other boards than the EB-PDS-DVI-R1 use the recommended voltage which is
mentioned in the section of the board.
7. Press Apply Values to Register Map
Extension Boards
Related Work
Figure 6-120. SiLabs Clock Builder Frequency Plan
Extension Boards
Related Work
Figure 6-121. SiLabs Clock Builder Output Drivers
After you have finished your clocking setup Save register map file (not for factory
programming).For the other tabs, refer to the SibLabs Clock Builder manual.Using Clock
Builder Pro SoftwareThe generation of the Register Map File in the Clock Builder Pro Software
is guided through a wizard.After ‘Create New Project’ > ‘Clock Generators’ > ‘Si5338’ you
have to do the following steps:
• Choose the ‘Universal Input Pin Configuration’ which is ‘CLKIN’ for Pin 3 and
‘I2C_LSB’ for Pin 4
• Select the I2C address of the device which is ‘0x70’ in hex
• The ‘I2C Bus Voltage’ value has to be set to ‘2.5/3.3V’
• Enter the ‘Input’ frequency ‘25 MHz’ and choose ‘XA/XB’ as ‘Type/Format’
• Choose your ‘Output Frequencies’ by writing the according value into each field
• set ‘Format’ of each used output to ‘CMOS Only A 1.8V’
Extension Boards
Related Work
Caution
For other boards than the EB-PDS-DVI-R1 use the recommended voltage which is
mentioned in the section of the board.
• After finishing the wizard click onto ‘Export’ to generate the register map file
• In the ‘Export’ menu select the tab ‘Register File’
• As ‘Export Type’ select ‘Comma Separated Values (CSV) File’
• To generate the file, click onto ‘Save To File …’ button and choose the location and the
name of the file
Figure 6-122. Clock Builder Pro Universal Pin Configuration
Extension Boards
Related Work
Figure 6-123. Clock Builder Pro Supply Voltages and Host Interface
Figure 6-124. Clock Builder Pro Input Clocks
Extension Boards
Related Work
Figure 6-125. Clock Builder Pro Output Frequencies
Figure 6-126. Clock Builder Pro Output Driver
Extension Boards
Related Work
Figure 6-127. Clock Builder Pro Frequency and Phase Offset
Figure 6-128. Clock Builder Pro Spread Spectrum
Extension Boards
Related Work
Figure 6-129. Clock Builder Pro Export
Extension Boards
Related Work
Figure 6-130. Clock Builder Pro Export Settings
profpga_run
...
plugin_list = ( "si5338 ProDesign EB-PDS-DVI-R1" );
{
...
...
"si5338 ProDesign EB-PDS-DVI-R1" );
{
...
Extension Boards
Related Work
<instance name>:
{
type = "BOARD";
name = " EB-PDS-DVI-R1";
size = "A1A1";
v_io_ba1 = "AUTO";

};
system configuration.
Please refer to the „proFPGA Software Reference Manual” [UD002] for more
information.<register map file> must be replaced with the path and the filename to the register
map file created with the Si5338 software.si5338_validate_input_clocks_1_2_3 and
si5338_validate_input_clocks_4_5_6 has to be set to yes or no in order which input clock will
be used. For the DVI board the input clocks 1 and 2 (IN1 and IN2) are used. Therefore, the input
clocks on these two inputs have to be valid before proceeding with the programming procedure
of the Si5338.
Refer to Si5338 manual for more information (figure 9 in Rev. 1.4 -> “Is input clock
valid?”).si5338_execute_plugin_async_event: A "yes" for this option enables the ability for
information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-DVI-R1”. The system
configuration file can be created directly or with the profpga_builder tool.
Please refer to the “proFPGA Software Reference Manual” [UD002] and the “proFPGA Builder
Extension Boards
Order Code
Order Code
This topic discusses order code of DVI Input and Output Board (EB-PDS-DVI-R1)
286500
Extension Boards
QSFP+ Extension Board (EB-PDS-QSFP+-R1)
QSFP+ Extension Board (EB-PDS-QSFP+-R1)

This topic discusses QSFP+ Extension Board (EB-PDS-QSFP+-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
This topic discusses functional description of QSFP+ Extension Board (EB-PDS-QSFP+-R1).
The proFPGA QSFP+ extension board provides two sockets for QSFP or QSFP+ modules and
supports the maximum transfer rate of the QSFP+ modules of 10 Gbit/s per Channel.

• One proFPGA top connector to make all unused regular IOs of the bottom connector
available for further use (e.g., to connect a cable for interconnections to other FPGAs).
• Programmable clock generator for MGT_REFCLK pins.
• Two QSFP+ connectors.
Extension Boards
Figure 6-131. EB-PDS-QSFP+-R1
Figure 6-132 shows the structure of the board.
Figure 6-132. EB-PDS-QSFP+-R1 Board Overview

I²C proFPGA I²C Bus
LPMODE Low Power Mode pull high for low power mode
Extension Boards

INTL Interrupt when low, it indicates a
possible module operational
fault or a status critical to the
host system
MODPRSL Module Present when low a QSFP module is
inserted
MODSELL Module Select need to be held low, that the
QSFP module responds to 2-
wire interface
RESETL Module Reset pull low for QSFP module
reset
MGT_REFCLK_0 Refclock from SI5338 CLK0
MGT_RX/TX_0..3 QSFP_RX/TX Port A
MGT_RX/TX_4..7 QSFP_RX/TX Port B
QSFP_SCL 2-wire serial interface clock
QSFP_SDA 2-wire serial interface data
QSFP_RX_[1..4] Receiver Data Outupt
QSFP_TX_[1..4] Transmitter Data Intupt

This topic discusses extension board operating conditions of QSFP+ Extension Board (EB-
PDS-QSFP+-R1).
Table 6-243. EB-PDS-QSFP+-R1– Extension Board Operating Conditions

Extension Boards

This topic discusses FPGA extension site compatibility of QSFP+ Extension Board (EB-PDS-
QSFP+-R1).
In the table below, (1) Only one QSFP+ connector can be used
Table 6-244. EB-PDS-QSFP+-R1– FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √
FM-XC7V2000T-R2 √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √ √ √
FM-XCVU080-R1 √ √ √ √ √ √
FM-XCKU115-R1 √ √ √ √ √ √
FM-XCVU5P-R1 √ √ √ √ √ √
FM-XCVU7P-R1 √ √ √ √ √ √
FM-XCVU9P-R1 √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √(1) √(1)
FM-XCZU19EG-R2 √ √ √(1)
Extension Boards
Table 6-244. EB-PDS-QSFP+-R1– FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCZU17EG-R2 √ √ √(1)
FM-XCZU11EG-R2 √ √ √(1)
FM-1SG280<L,H>-R2 √ √(1) √(1)
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √
Table 6-245. EB-PDS-QSFP+-R1– FPGA extension site compatibility,

FM-1SG10M-R1

This topic discusses FPGA pin constraints of QSFP+ Extension Board (EB-PDS-QSFP+-R1).
Table 6-246. EB-PDS-QSFP+-R1–FPGA Pin Constraints

LVCMOS18
Related Work
This topic discusses related work of QSFP+ Extension Board (EB-PDS-QSFP+-R1).

Tip
Extension Boards
Related Work
profpga_run
...
plugin_list = ( "si5338 ProDesign EB-PDS-QSFP+-R1" );
{
...
...
"si5338 ProDesign EB-PDS-QSFP+-R1" );
{
...
<instance name>:
{
type = "BOARD";
name = " EB-PDS-QSFP+-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

reconfiguration for the Si5338 clock generator during runtime. The reconfiguration, based on
the register map file, is triggered by the command line option --plugin-async-events for
information.
Extension Boards
Benchmark

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-QSFP+-R1”. The
Benchmark
This topic discusses benchmark for QSFP+ Extension Board (EB-PDS-QSFP+-R1).
Some measurements were done to validate the functionality of the EB-PDS-QSFP+-R1
extension board. For these measurements the following components were used:
• AFBR-79EQDZ: 40 Gigabit Ethernet & InfiniBand QSFP+ Pluggable, Parallel Fiber

Optics Module from Avago Technologies
• 1062831001: 1 meter OM3 cable from Molex
• proFPGA FM-XC7VX330T-R3 (speed grade 2)
An IBERT (integrated bit error test) was generated with Xilinx ise/14.6 for TB2 connector. The
analysis was done with the analyzer from Xilinx. Both MGT banks shared the same reference
clock of 100 MHz. The test was done with the complexest Data Pattern - PRBS 31-bit. Some
properties have to be set manually:
• TX Diff Output Swing: 600 mV

• TX Pre-Cursor: 3.41 dB
• Termination Voltage: AVTT
Extension Boards
Order Code
Figure 6-133. EB-PDS-QSFP+-R1 IBERT From Xilinx
The test was done for nearly half an hour with zero errors on each channel (RX Bit Error
Count).
The analyzer also allows creating an eye diagram. Please keep in mind, that this are not
optimized settings. With optimized settings, the eye could be much bigger.
Figure 6-134. EB-PDS-QSFP+-R1 Eye Diagram Generated with IBERT from

Xilinx
Order Code
This topic discusses order code of QSFP+ Extension Board (EB-PDS-QSFP+-R1).
Extension Boards
Order Code
286507
Extension Boards
QSFP28 Extension Board (EB-PDS-QSFP28-R1)
QSFP28 Extension Board (EB-PDS-QSFP28-

R1)
This topic discusses QSFP28 Extension Board (EB-PDS-QSFP28-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
This topic discusses functional description of QSFP28 Extension Board (EB-PDS-QSFP28-
R1).
The proFPGA QSFP28 extension board provides three sockets for QSFP28 modules and
supports the common transfer rate 25.78125 Gbit/s on each socket.

available for further use (e.g. to connect a cable for interconnections to other FPGAs).
• Two programmable clock generators for MGT_REFCLK pins (up to four individual
Reference clocks).
• Two QSFP28 connectors with three ports.
Extension Boards
Figure 6-135. EB-PDS-QSFP28-R1
Figure 6-136 shows the structure of the board.
Figure 6-136. EB-PDS-QSFP28-R1 Board Overview

I²C proFPGA I²C Bus
QSFP_*_LPMode Low Power Mode pull high for low power mode
Extension Boards

QSFP_*_ModInt_L Interrupt when low, it indicates a
host system
QSFP_*_ModPrsL Module Present when low a QSFP module is
inserted
QSFP_*_ModSelL Module Select need to be held low, that the
wire interface
QSFP_*_ResetL Module Reset pull low for QSFP module
reset
QSFP_*_SCL 2-wire serial interface clock
QSFP_*_SDA 2-wire serial interface data
QSFP_*_RX_[1..4] Receiver Data Outupt
QSFP_*_TX_[1..4] Transmitter Data Intupt
QSFP28_REFCLK Reference Clock Source for Alternative to SI5328B Cristal
MGT Reference Clock Clock Source
QSFP_MGT_REFCLK_ Reference Clock Input for
* MGTs
JITTER_RST_A nReset of Clock Generator Resets SI5328B Clock
JITTER_RST_B Generator
CA_A Active Clock Indicator Indicates Input Clock of Clock

CA_B Generator

This topic discusses extension board operating conditions of QSFP28 Extension Board (EB-
PDS-QSFP28-R1).
Table 6-248. EB-PDS-QSFP28-R1– Extension Board Operating Conditions

Extension Boards

This topic discusses FPGA extension site compatibility of QSFP28 Extension Board (EB-PDS-
QSFP28-R1).
Table 6-249. EB-PDS-QSFP28-R1– FPGA Extension Site Compatibility.

V1 V1
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1
FM-XCVU440-R2
FM-XCVU190-R1
FM-XCVU160-R1
FM-XCVU125-R1
FM-XCVU095-R1
FM-XCVU080-R1
FM-XCKU115-R1
FM-XCVU5P-R1
FM-XCVU7P-R1
FM-XCVU9P-R1
FM-XCVU19P-R1
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-1SG280<L,H>-R1
FM-XCZU19EG-R2
FM-XCZU17EG-R2
Extension Boards
Table 6-249. EB-PDS-QSFP28-R1– FPGA Extension Site Compatibility. (cont.)

V1 V1
FM-XCZU11EG-R2
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1
Table 6-250. EB-PDS-QSFP28-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1
FM-XCVU19P-R1

This topic discusses FPGA pin constraints of QSFP28 Extension Board (EB-PDS-QSFP28-R1).
Table 6-251. EB-PDS-QSFP28-R1–FPGA Pin Constraints

LVCMOS18
Related Work
This topic discusses related work of QSFP28 Extension Board (EB-PDS-QSFP28-R1).
Generating register map files for SI5328B

The SI5328B is a configurable clock source.
The profpa_run tool requires a register map file to configure the output clocks of the SI5328B.
This file can be generated by the ‘Precision Clock EVB Software V5.1’ from SiLabs. It can be
downloaded here: https://www.silabs.com/products/development-tools/software/clock
Using DSPLLsim
The software suite Precision Clock EVB Software 5.1 includes a variety of tools. For generating
a proper Registermap-file the tool DSPLLsim is used (see Figure 6-137).
Extension Boards
Related Work
Figure 6-137. DSPLLsim
After startup a dialog for the planed task is shown (see Figure 6-138). The task "Create a new
frequency plan with free run mode enabled" has to be chosen.
Figure 6-138. DSPLLsim Start-Up Dialog
After this dialog a dialog for choosing the device will open. The SI5328 has to be selected (see
Figure 6-139).
Extension Boards
Related Work
Figure 6-139. DSPLLsim Device Selector
In the next step the clock settings have to be done (see Figure 6-140). Using the crystal input is
recommended. This frequency is fixed to 114.285 MHz. So, the CKIN1 settings will be 114.285
MHz. The specified number of outputs depends on the implemented design. The output
frequency of 171.875MHz is recommended for QSFP28 use case.
Extension Boards
Related Work
Figure 6-140. DSPLLsim Frequency Planner
The software optimizes the PLL settings depending on the ppm requirements and the chosen
frequencies. The settings shown in Figure 6-141 are recommended for QSFP28 use case. The
values for CKIN1 and CKOUT1 have to be set and afterwards confirmed via pressing the
Calculate Ratio Button.
Extension Boards
Related Work
Figure 6-141. DSPLLsim Search Parameter Settings
The possible Frequency settings including error rate will show up in the next dialog (see
Figure 6-142). The appropriate setting has to be set in the field and confirmed via next button.
Extension Boards
Related Work
Figure 6-142. DSPLLsim Frequency Plan
The next dialogs summarize the settings and can be confirmed with the next Button (see
Figure 6-143 and Figure 6-144) and finally with the OK Button (see Figure 6-145).
Extension Boards
Related Work
Figure 6-143. DSPLLsim N3 Values
Extension Boards
Related Work
Figure 6-144. DSPLLsim NCn_LS Values
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Related Work
Figure 6-145. DPLLsim Overview Frequency Plan
Finally, in the last dialog (see Figure 6-146) additional settings can be made. There are
additional options for the software part of the SI5328B for example error LEDs and options for
adjusting the clock such as skew offsets, signal format and drive strength.
For QSFP28 use case following settings has to be set:
Tab Output Clocks:
SFOUT1_REG -> LVDS
SFOUT2_REG -> LVDS
QS_ICAL -> flagged
Extension Boards
Related Work
Figure 6-146. DPLLsim Setup
The Register Map File can be saved via options menu (see Figure 6-147).
Figure 6-147. Save Register Map File...
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Related Work
profpga_run
...
plugin_list = ( " si5328B ProDesign EB-PDS-QSFP28-R1" );
{
...
...
" si5328B ProDesign EB-PDS-QSFP28-R1" );
{
...
<instance name>:
{
type = "BOARD";
name = " EB-PDS-QSFP28-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
si5328B_1 :
{
registermap_file = "<register map file>";
};
si5328B_2 :
{
registermap_file = "<register map file>";
};
};
more information.
<register map file> must be replaced with the path and the filename to the register map file.
Extension Boards
Benchmark

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-QSFP28-R1”. The
Benchmark
This topic discusses benchmark of QSFP28 Extension Board (EB-PDS-QSFP28-R1).
Some measurements were done to validate the functionality of the EB-PDS-QSFP28-R1
extension board. For these measurements the following components were used:
• 1002971101 zQSFP+ Cable 1m from MOLEX

• proFPGA FM-XCVU13P-R1 (speed grade 3)
An IBERT (integrated bit error test) was generated with Xilinx Vivado 2018.3 for TB2
connector. The analysis was done with stock settings and the analyzer from Xilinx. The MGT
banks shared the same reference clock of 171.875000 MHz. The test was done with the
complexest Data Pattern - PRBS 31.
Order Code
This topic discusses order code of QSFP28 Extension Board (EB-PDS-QSFP28-R1).
286508
Extension Boards
EB-PDS-FIREFLY-R1
EB-PDS-FIREFLY-R1
This topic discusses EB-PDS-FIREFLY-R1.

System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
This topic discusses functional description of EB-PDS-FIREFLY-R1.
The proFPGA FireFly extension board is intended to be used in conjunction with Samtec's
exclusive optical cable product family of the type ECUO FireFly and provides individual
mounting sockets for R12 and T12 FireFly HOC (Half-Optical-Cable) modules.
Those FireFly cables can be used to exclusively connect different high-speed data lanes
between proFPGA FPGA modules over long distances, as required by server rack applications
or data center solutions. This feature allows the usage of the EB-PDS-FIREFLY-R1 extension
board as some kind of breakout board in terms of MGT connectivity.
Extension Boards
Figure 6-148. EB-PDS-FIREFLY-R1 - Veloce proFPGA FireFly Interface Kit
Extension Board - HOC Host

The EB-PDS-FIREFLY-R1 extension board provides:
• 1x proFPGA V0 top connector to make all unused regular IOs of the bottom connector
available for further use
• 1x IDPROM for board identification
• 1x FireFly HOC socket delivering 12x TxD lanes for an optical transmitter HOC of type
ECUO/ETUO (T12 or Y12 compatible, no hot-plug capability)
• 1x FireFly HOC socket delivering 12x RxD lanes for an optical receiver HOC of type
ECUO/ETUO (R12 or Y12 compatible, no hot-plug capability)
• Both FireFly HOC sockets can be used to interface a full-fledged HOC of type ECUO/
ETUO Y12-16G and Y12-25G
Extension Boards
• Both FireFly HOC sockets are powered by on-board power modules automatically
(switchable power supply capability via plugin)
• 2x fans for active cooling of each HOC socket, each fan is plug-able via a 4-pin header
and powered from 12V (up to 200mA current consumption)
Caution
The V0 top connector shall be utilized only with proFPGA cables for interconnections to
other FPGAs.
FireFly Cable Y12 - HOC Modules R12 + T12

The FireFly cables intended to be used with the EB-PDS-FIREFLY-R1 are primarily Y12
cables with an optical transmitter (T12) and optical receiver (R12) module.
Special care should be taken, when mounting the R12 and T12 modules on their desired socket
as there is no mechanical polarization present, but only corresponding labels in the PCB
silkscreen.
Caution
A wrong placement of the HOC modules could not be detected by the extension board and
could damage the FireFly HOC modules permanently, as well as the FPGA itself!
In case of need, each FireFly HOC module can be identified as an R12 or T12 module through a
corresponding copper-based marking underneath the HOC PCB and by the color of the
mounting tab:
• T12 Module: Marking 'T' with Orange tab

• R12 Module Marking 'R' with Cyan tab
Extension Boards
Figure 6-149. FireFly ECUO Y12 16G - T12/R12 Markings
For further instruction on how to mount the FireFly HOC modules properly, please refer to the
Samtec documentation.
Extension Boards
All 12x RxD and 12x TxD lanes are consolidated in a common MTP female connector with 24
fibers, with an up-counting signal mapping scheme as follows:
Figure 6-150. FireFly ECUO Y12 - Fiber Optic Mapping
Tip
It is recommended, to use a male-male MTP24 patch cable instead of directly connecting
two Y12 cables with their MTP24 female endings, as the male endings deliver guiding lugs
for increased contact alignment.
Optical Patch Cables - FOPC + Breakout Cables

The easiest way to achieve a 1:1 interconnection between two EB-PDS-FIREFLY-R1 extension
boards is to use a so called Full-Optical-Patch-Cable of type A (FOPC), which simply connects
the Tx0 output of one side with Rx0 input of the other in up-counting order and vice versa.
Extension Boards
Figure 6-151. Optical Setup - Full-Optical-Patch-Cable
If a more flexible signal mapping is required, it is recommended to use breakout cables (also
known as harness cables) converting the MTP24 connector interface into a bunch of single optic
fiber connectors.
Figure 6-152. Harness Cables
Utilizing this single fiber connectors (e.g LC/SC/FC), an interconnection setup equivalent to the
mapping scheme of a type A FOPC cable, as well as an individual scheme can be realized.
Note
Appropriate mechanical adapters are required to establish the connection between the
FireFly Y12 cables and the desired optical patch cable, as shown in the pictures above.
If breakout cables are used, an additional patch field or similar mechanical adapter interface for
the single fiber connectors is required as well.
Extension Boards
System Structure
Verified Optical Equipment

The EB-PDS-FIREFLY-R1 extension boards is verified with the following FireFly cables:
• OTP-224887-01-ECUO (included in FireFly Interface Kit 16G)

The following Full-Optical-Patch-Cables in conjunction with appropriate MTP adapters are
verified:
• FOPC-01-01-003-24-01 (+ MPO Adapter OPA-S-1-F)

The following LC breakout/harness cables in conjunction with appropriate MTP adapters and
mechanical LC adapter panels are verified:
• 24FMTPLCOM4 25884 + (MPO Adapter OPA-S-1-F + FHD Fiber Adapter Panel

41998)
System Structure
This topic discusses system structure of EB-PDS-FIREFLY-R1.
The extension board consists on the following main functional domains:
• Mechanical connectors forming a FireFly conformal socket for optical modules of the
type FireFly ECUO R12 and T12
• Power tree supplying each HOC socket individually from P12V directly
• Power up sequencing circuitry allowing to switch between 3.3V and 3.8V for FireFly
T12 modules
• I2C bus topology allowing to access all slave devices via the proFPGA system (SW/
HW)
• Programmable clock generator
• Thermal Monitoring circuitry consisting of a dedicated fan controller of the type
EMC2104
• Circuitry to supply up to 2 individual fans
Extension Boards
System Structure
Figure 6-153. EB-PS-FIREFLY-R1 - System Structure
Note
The proFPGA status command delivers an easy-to-use interface to read-back several critical
status signals via the common proFPGA I2C interface. For further usage, please refer to the
chapter proFPGA proFPGA Status Command!
Thermal Shutdown
In order to avoid damage to the FireFly modules in case of a thermal runaway condition of the
system, an automatic completely hardware based thermal shutdown mechanism is available.
This automatic control loop ensures a thermal safety feature intended as a fallback solution,
even when there is no specific system monitoring software present on the upper application
levels.
Extension Boards
System Structure
Figure 6-154. EB-PDS-FIREFLY-R1 - Thermal Shutdown Hardware

Implementation
Controlled by the EMC2104 fan controller, a low-active thermal shutdown signal is generated
which will be asserted by the EMC2104 if the temperature of its internal diode channel exceeds
a specific threshold value.
This thermal shutdown signal is connected to the enable inputs of all power modules and
deactivates them in case of need. This in turn powers down the FireFly modules in an instant,
yet the optional fans are not affected.
Due to the power down procedure of the power modules, all volatile configuration settings
written to FireFly T12 and R12 modules will be gone, when the thermal shutdown signal is
released again.
As long as the over-temperature condition is present, the thermal shutdown signal can be read-
back directly. If the over-temperature condition has vanished, the thermal shutdown signal will
be released.
Reading out a corresponding latching error flag, a previous thermal shutdown event can be
detected.
Active Cooling
The extension board delivers 2 individual 4-pin connectors allowing the optional usage of 12V
powered fans for both FireFly HOC sockets at will.
If an appropriate fan is connected, the supply voltage will be applied without any specific
restrictions and a current consumption up to 200mA is valid.
The following pinout should be taken into account, when other fans are used as shipped with the
Veloce FireFly Kit:
• GND
Extension Boards
• P12V (directly connected to proFPGA P12V supply)

• SENSE (open drain tachometer signal, not supported)
• CONTROL (PWM control signal, not supported)

This topic discusses extension board operating conditions of EB-PDS-FIREFLY-R1.
Table 6-252. EB-PDS-FIREFLY-R1 - Extension Board Operating Conditions

IO voltage (min ... recommended ... max) any, recommended 1800mV
IO voltage provider FPGA module for FPGA bank
Top-side extension board connector yes:
Type V0 TA1*X1
Type MGT_RX TA1*XMGT_RX[00:11]
Type MGT_TX TA1*XMGT_TX[00:11]

This topic discusses FPGA extension site compatibility of EB-PDS-FIREFLY-R1.
The following FPGA listing is focused on the exclusive usage of the extension board as an
MGT breakout board in terms of compatibility.
Table 6-253. EB-PDS-FIREFLY-R1 - Extension Site Compatibility
FPGA Module TA0 TA1 TA2 TB0 TB1 TB2 BA1 BA2 BB1 BB2
FM-XCVU19P-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √

This topic discusses FPGA pin constraints of EB-PDS-FIREFLY-R1.
Table 6-254. EB-PDS-FIREFLY-R1 - FPGA Pin Constraints

Signal Xilinx FPGA Altera FPGA
all IO signals any, any,
all IO and CLK_IO signals all IO and CLK_IO signals
routed from bottom to top routed from bottom to top
straight forward straight forward
Extension Boards
Related Work
Table 6-254. EB-PDS-FIREFLY-R1 - FPGA Pin Constraints (cont.)

Signal Xilinx FPGA Altera FPGA
O"
MGT/XCVR REFCLK IO_STANDARD "LVDS"
Related Work
This topic discusses related work of EB-PDS-FIREFLY-R1.
Extension Boards
Related Work
profpga_run
<instance_name>:
{
type = "BOARD";
vendor = "Siemens";
name = "EB-PDS-FIREFLY-R1";
size = "A1A1";
positions = ( "<position>" );
# Top Connector section
# Note: TA1*XMGT* entries needed for MGT Cable feature of proFPGA
Builder and Boardgen
top_connectors = ( "TA1*X1", "TA1*XMGT_RX00", "TA1*XMGT_RX01",
"TA1*XMGT_RX02", "TA1*XMGT_RX03", "TA1*XMGT_RX04", "TA1*XMGT_RX05",
"TA1*XMGT_RX06", "TA1*XMGT_RX07", "TA1*XMGT_RX08", "TA1*XMGT_RX09",
"TA1*XMGT_RX10", "TA1*XMGT_RX11", "TA1*XMGT_TX00", "TA1*XMGT_TX01",
"TA1*XMGT_TX02", "TA1*XMGT_TX03", "TA1*XMGT_TX04", "TA1*XMGT_TX05",
"TA1*XMGT_TX06", "TA1*XMGT_TX07", "TA1*XMGT_TX08", "TA1*XMGT_TX09",
"TA1*XMGT_TX10", "TA1*XMGT_TX11" );
v_io_ba1 = "AUTO";
# FireFly Y12 Plugin settings - R12 Module section
ff_r12 :
{
OUT_AMP_MODIFY = 0;
OUT_AMP_00 = 2;
OUT_AMP_01 = 2;
OUT_AMP_02 = 2;
OUT_AMP_03 = 2;
OUT_AMP_04 = 2;
OUT_AMP_05 = 2;
OUT_AMP_06 = 2;
OUT_AMP_07 = 2;
OUT_AMP_08 = 2;
OUT_AMP_09 = 2;
OUT_AMP_10 = 2;
OUT_AMP_11 = 2;
};
# FireFly Y12 Plugin settings - T12 Module section
ff_t12 :
{
INV_POL = 0;
};
# Si5332 V0 Plugin settings
si5332_registermap_file = "<register_map_file>";
};
<instance_name> and <position> must be replaced with the correct value according the system
configuration. Please refer to the “proFPGA Software Reference Manual” [UD002] for more
information.
<register_map_file> must be replaced with the path and the filename to the Si5332 conformal
register map file created with the Clock Builder Pro software.
Extension Boards
Related Work
If the Si5332 shall be used, it will be configured with a proFPGA plugin.
In order to power up the FireFly HOC modules properly and readout basic status and firmware
data, the FireFly Y12 plugin has to be called as well.
To load the plugins the plugin_list entry before the system_configuration section must be added
and/or modified as follows:
...
plugin_list = ( "firefly_y12 Siemens EB-PDS-FIREFLY-R1", "si5332_v0

Siemens EB-PDS-FIREFLY-R1");
system_configuration :
{
...
If there is already a plugin_list entry, the list must be simply extended.

The EB-PDS_FIREFLY-R1 extension boards features a programmable clock generator of the
type Si5332E-D-GM2 to create the reference clocks for all covered MGT banks. As is common
for proFPGA extension boards using MGT lanes, 4 individually programmable clock channels
are distributed on the V0 bottom connector.
The Si5332 needs to be programmed through a register map file. This file can be generated by
the ‘Clock Builder Pro Software’ from SiLabs.
The generation of the Register Map File in the Clock Builder Pro Software is guided through a
wizard.
Extension Boards
Related Work
After ‘Create New Project’ > ‘Clock Generators’ > ‘Si5332-GM2/AM2’
The following steps have to be performed:
• ‘Wizard Overview’: Nothing has to be done here.

• Step 1: An optional Design ID can be added
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Related Work
• Step 2: Choose the chip revision ‘D’:
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Related Work
• Step 3: In the package selection window select ‘Si5332-GM Embedded Crystal (Grades
E, F, G or H):
• Step 4: Multi Profile’ Selection can be left disabled.

• Step 5: Pin configuration of ‘INPUT1’ to ‘INPUT7’ has to be left to ‘None’.
• Step 6: The I2C Address Select pin has to be left at value ‘None’.
Extension Boards
Related Work
• Step 7: Input XA/XB should be set to 'Embedded Crystal' and CLKIN[2,3] to 'Unused'
for this extension board.
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Related Work
• Step 8: Next the outputs and their desired frequency values (in case of a PLL selection
previously) can be defined here:
Note
The EB-PDS-FIREFLY-R1 utilizes only 4/8 output channels in a specific pattern, as
shown below. Frequency values can be changed, the rest should be left untouched.
• Step 9: The spread spectrum can only be activated if the 'Divider SSC/FS' entry is not set
'Auto'. Normally nothing has to be done here.
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Related Work
• Step 10: The values have to be set to 'LVDS Fast 1.8V'! to use these clock outputs as
input lanes for the MGT reference clocks:
• Step 11: The output skew can be changed. Normally nothing has to be done here.
• Step 12: The output enable pins can be assigned here. Since INPUT[1...7] are not
connected, nothing can be done here.
• After finishing the wizard click onto 'Export' to generate the register map file.
• In the 'Export' menu select the tab 'Register File'
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Related Work
• As 'Export Type' select 'Comma Seperated Values (CSV) File'.
MGT-CABLE-R1
The MGT-CABLE-R1 is eventually only a virtual representation of a connected RxD and TxD
lane pair on the level of the system configuration file and can be used to emulate a single or an
aggregated physical connection like a full-patch-cable.
The EB-PDS-FIREFLY-R1 extension board can be used as a socket for the interconnection
cable MGT-CABLE-R1, allowing to define an application specific MGT lane mapping between
different extension boards or from the T12 to R12 sockets of the same board for loopback
purposes.
Extension Boards
Related Work
Figure 6-155. proFPGA Builder - EB-PDS-FIREFLY-R1 with Mounted MGT-

CABLE-R1
Following mapping schemes are supported by the proFPGA Builder and will be represented in
• MGT lane mapping from a single XMGT_TX to a single XMGT_RX (random access on
order of XMGT_TX[00:11] to XMGT_RX[00:11])
• MGT lane mapping<all> from a T12 socket to a R12 socket with patch cable mapping
scheme type B/C (up-counting order of XMGT_TX[00:11] to XMGT_RX[00:11] )
Extension Boards
Related Work
The x_board_list contains all MGT-CABLE-R1 instances as additional entries and

corresponding sections will be present in the system configuration file:
x_board_list = ("ta1_ta0_eb1", "ta1_tb0_eb1",

"mgtc_1", "mgtc_2", "mgtc_3", "mgtc_4", "mgtc_5", "mgtc_6", "mgtc_7",
"mgtc_8", "mgtc_9", "mgtc_10", "mgtc_11", "mgtc_12", "mgtc_13" );
...
# MGT lane mapping within the same extension board, according to scheme
<all>
mgtc_1 :
{
name = "MGT-CABLE-R1";
type = "MGT_CABLE";
positions = ( "ta1_ta0_eb1.TA1*XMGT_RX00", "ta1_ta0_eb1.TA1*XMGT_TX00"
);
};
...
mgtc_12 :
{
type = "MGT_CABLE";
positions = ( "ta1_ta0_eb1.TA1*XMGT_RX11", "ta1_ta0_eb1.TA1*XMGT_TX11"
);
};
# MGT lane mapping as interconnection between different extension boards,
according to scheme <all>
mgtc_1 :
{
type = "MGT_CABLE";
positions = ( "ta1_ta0_eb1.TA1*XMGT_RX00", "ta1_tb0_eb1.TA1*XMGT_TX00"
);
};
...
mgtc_12 :
{
type = "MGT_CABLE";
positions = ( "ta1_ta0_eb1.TA1*XMGT_RX11", "ta1_tb0_eb1.TA1*XMGT_TX11"
);
};
# MGT lane mapping as interconnection between different extension boards,
random access scheme
mgtc_13 :
{
type = "MGT_CABLE";
positions = ( "ta1_eb1.TA1*XMGT_RX01", "tb1_eb1.TA1*XMGT_TX00" );
};
Note
Due to the fact, that the physical FireFly cables are not accessible by the proFPGA system
directly, it is not possible to determine the amount of RxD/TxD pairs nor the mapping
scheme in respect to the R12 and T12 sockets by scanning a real system.
Extension Boards
Related Work
Plugin FireFly Y12

The EB-PDS-FIREFLY-R1 extension board must be used in conjunction with the FireFly Y12
plugin, if FireFly cables of the type ECUO Y12 shall be used.
Note
The FireFly Y12 plugin supports only FireFly cables which are part of the Verified Optical
Equipment listing. Using other types of cables will cause an error and the complete
proFPGA power up procedure will be aborted.
Calling the FireFly Y12 plugin, following steps will be performed to power up and initialize the
FireFly R12 and T12 modules according to the desired use-case:
• Configuring of power and system management circuitry

• Determining if FireFly T12 + R12 HOC sockets are populated
• Checking power good indication from power modules
• Determining if 16G or 25G HOC modules are present
• Configuring of power modules to set appropriate T12 supply voltage (pin 10: 16G with
3.3V, 25G with 3.8V)
• Releasing the reset signal on T12 + R12 HOC sockets for HOC micro-controller boot up
• Enabling I2C communication interfaces on T12 + R12 HOC sockets
• Reading out firmware revision for plausibility checking
• Reading out T12 and R12 module temperature sensors and checking against allowed
max operating temperature values (abort if exceeded)
Tip
Beside the default use-case of using the extension board with a fledged Y12 FireFly cable
(utilizing R12 + T12), it is allowed to leave both sockets R12 and T12 unpopulated as well.
The Plugin will detect this use-case and skip the power module configuration and I2C
initialization. Populating only one socket, the plugin will raise an error and the complete
proFPGA power up procedure will be aborted.
Extension Boards
Related Work
The following picture shows the plugin related output for both allowed use-cases in
combination with a FireFly Y12 16G cable assembly:
Figure 6-156. proFPGA Plugin FireFly Y12 - Console Output
In addition to these power up related steps, the following user configurable plugin parameters
can be modified by the customer, allowing to fine-tune the optical engines on the mounted
FireFly HOC modules:
Table 6-255. EB-PDS-FIREFLY-R1 - Plugin FireFly Y12
Plugin Parameter Default Value Allowed Values Description
OUT_AMP_MODIF 0b0 0b[0,1] 0 - ignores
IY OUT_AMP_XX
values, default values
from R12 module
will be applied
1 - writes
OUT_AMP_XX into
R12 module
Extension Boards
Related Work
Table 6-255. EB-PDS-FIREFLY-R1 - Plugin FireFly Y12 (cont.)

OUT_AMP_XX 0d2 0d[0:15] Output Amplitude
for optical channel
Rx-[00:11]
• Value: 0d0, 16G:
zero, 25G: 80 mV
• Value: 0d1, 16G:
zero, 25G:
156mV
• Value: 0d2, 16G:
low, 25G: 232
mV
• Value: 0d3, 16G:
low, 25G: 308
mV
• Value: 0d4, 16G:
medium, 25G:
384 mV
• Value: 0d5, 16G:
medium, 25G:
460 mV
• Value: 0d6, 16G:
high, 25G: 536
mV
• Value: 0d7:15,
16G: high, 25G:
612 mV
INV_POL 0b0 0b[0,1] 0 - transmit polarity
is default for Tx-
[00:11]
1 - transmit polarity
is inverted for Tx-
[00:11]

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-FIREFLY-R1”.
Extension Boards
Related Work
proFPGA Status Command

Calling the proFPGA status command, several status signals and temperature values related to
the system monitoring capabilities of the EB-PDS-FIREFLY-R1 extension board will be read
out.
profpga_run <config_file> --status
The additional system status parameters will be displayed as an extended section of the common
output-listing for every extension board of the type EB-PDS-FIREFLY-R1 which is present in
the actual system, including the path leading to the mounting position.
If there is no extension board of the type EB-PDS-FIREFLY-R1 in the system, no console

output will be generated at all (legacy behavior like older proFPGA releases).
Note
The EB-PDS-FIREFLY-R1 status parameters are only available with the proFPGA 2022A-
SP1 release or newer. Older version will simply ignore the presence of the extension board.
Figure 6-157. proFPGA status - Section Extension Board EB-PDS-FIREFLY-R1
This mechanism allows to get critical system parameters as listed below in the same manner as
used for the proFPGA FPGA modules. In addition, it allows to determine if specific critical
system conditions had occurred while the system is up and running.
Tip
If there is no FireFly module attached to the extension board, only some basic parameters
concerning the EMC2104 based monitoring are accessible.
Extension Boards
Related Work
Table 6-256. EB-PDS-FIREFLY-R1 - proFPGA Status Command

Status Parameter Description Values Remarks
EMC2104 internal actual temperature <val>=[-64:128]
temperature value of the internal deg.C
diode of EMC2104
fan controller
EMC2104 critical critical temperature <val>=100 deg.C • used as threshold
temperature limit for the internal for the thermal
diode of EMC2104 shutdown signal
fan controller • no configuration
supported, POR
default value
[T12,R12] module represents FireFly PRESENT • indicates the
[T12,R12] module NOT PRESENT physical presence
side band signal of a FireFly
PRESENT_N [T12,R12] HOC
module
• PRESENT
needed to display
additional status
parameters
Board PSU POWER represents the &- OK • parameter only
GODD wired status signal FAIL available when
covering the power T12+R12 are
good outputs of all present
power modules • FAIL indicates
abnormal
condition of
power supply
infrastructure
• FAIL can be
caused by
thermal
shutdown
condition as well
Extension Boards
Related Work
Table 6-256. EB-PDS-FIREFLY-R1 - proFPGA Status Command (cont.)

Status Parameter Description Values Remarks
Thermal shutdown represents the ACTIVE • parameter only
EMC2104 controlled INCATIVE available when
THERMAL_SHUT T12+R12 are
DOWN_N signal present
used for HW-based • becomes active if
thermal shutdown EMC2104
internal
temperature
exceeds critical
limit
• if asserted, all
power modules
will be
deactivated
automatically
[T12,R12] case actual temperature <val>=[-127:127] • parameter only
temperature value of the internal deg.C available when
thermal sensor of T12+R12 are
FireFly [T12,R12] present
FireFly module • temperature is
measured on the
HOC PCB by the
[T12,R12]
internal circuitry
• accuracy of
internal
measurement is
appr. +/- 3 deg.C
[T12,R12] case maximum <val>=70deg.C for • parameter only
temperature limit recommended ECUO available when
operating case T12+R12 are
temperature of present
mounted [T12,R12] • limit value is
FireFly module stored in FireFly
[T12,R12]
module directly
• value can't be
changed but
depends on used
FireFly product
series (ECUO,
ETUO etc.)
Extension Boards
Skew
Skew
This topic is about Skew.
The skew of the cables can be calculated with the following equations.
Cable Equation 3 m cables
25G x 12 CDR disabled 0.54 ns + 5.13 ns * (length/m) 15.93 ns
25G x 12 CDR enabled 0.64 ns + 5.13 ns * (length/m) 16.03 ns
16G x 12 1.16 ns + 5.13 ns * (length/m) 16.55 ns
The standard length of the FireFly cables are 3m (meters)
Order Code
This topic discusses order code of EB-PDS-FIREFLY-R1.
In general, the EB-PDS-FIREFLY-R1 extension board will be sold as a bundle/kit in
conjunction with appropriate FireFly cables.
FireFly Interface Kit 16G

Veloce PF Firefly Interface Kit 290692
FireFly Interface Kit 25G

not available, verification pending
Extension Boards
MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1)
MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1)

This topic discusses MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
This topic discusses functional description of MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1).
proFPGA MIPI DPHY Board provides two MIPI D-PHY Receiver Interfaces. To be compatible
with FPGA supported IO standards two Meticon MC20901 MIPI FPGA bridges convert the
MIPI signals into highspeed LVDS and low power LVCMOS level.
• compliant to MIPI D-PHY CSI-1, CSI-2 standard

• transfer rates up to 2.5Gbps (HS mode), 20MBps (LPDT mode)
• two camera interfaces
• each camera interface supports up to four data lanes
• eight GPIOs, a dedicated I²C interface, reset and reference clock available for each
camera interface
• two adjustable onboard PSU for camera
• LP Signals supports different I/O-Voltages
• Bus turn around for data lane 0 at each interface
• proFPGA MIPI DPHY daughter card, which will be plugged on a free extension site of
the proFPGA FPGA Module
Extension Boards
Figure 6-158. EB-PDS-MIPI-DPHY-RX-R1
Figure 6-159. EB-PDS-MIPI-DPHY-RX-R1 Board Overview
Table 6-257. MIPI DPHY Board Signal Description

MIPI DPHY Signls
DPHY_IF[12]_HS_DATA_[NP][0..3] MIPI Highspeed data lanes, Bus Turnaround
option at lane 0, must be supported by
camera and the FPGA design
Extension Boards
Table 6-257. MIPI DPHY Board Signal Description (cont.)

DPHY_IF[12]_LP_DATA_[NP][0..3] MIPI low power data lanes, Bus Turnaround
DPHY_IF[12]_HS_CLK_[NP] MIPI Highspeed clock lane
DPHY_IF[12]_LP_CLK_[NP] MIPI low power clock lane
MIPI Bridge control signals
DPHY_IF[12]_BTA Enables bus turnaround (active high), must
always be driven at a valid level by the
FPGA (e.g. low if not used)
Additional Camera signals
DPHY_IF[12]_CLK Reference clock I/O
DPHY_IF[12]_RST Reset I/O
DPHY_IF[12]_ I2C_SDA Camera control I²C interface
DPHY_IF[12]_ I2C_SCL
DPHY_IF[12]_GPIO[0..7] GPIOs
This board has no camera specific connector, thus a customer specific camera adapter board or
cable is required. To connect a specific board or cable a Samtec QSH-060-01-L-D-A is placed
on the board. This connector mates with Samtec QTE-060 Series (e.g. QTH-060-01-H-D-A)
and HQCD series cables.
Figure 6-160. Camera Adapter Board Connector Samtec QSH-060-01-L-D-A
Table 6-258. Camera Interface 1 Pin Assignment

Signal Name Direction Mapping to camera Description
(seen from EB side) adapter board
Connector
GND A1 (1)
Extension Boards
Table 6-258. Camera Interface 1 Pin Assignment (cont.)

Connector
DPHY_IF1_D_N0 IN/OUT A2 (3) MIPI CSI Data lane
DPHY_IF1_D_P0 IN/OUT A3 (5)
GND A4 (7)
DPHY_IF1_D_N1 IN A5 (9) MIPI CSI Data lane
DPHY_IF1_D_P1 IN A6 (11)
GND A7 (13)
GND A10 (19)
GND A13 (25)
DPHY_IF1_CLK_N IN A14 (27) MIPI CSI CLK
DPHY_IF1_CLK_P IN A15 (29)
GND A16 (31)
DPHY_IF1_REF_C IN/OUT A17 (33) Camera Reference
LK CLK
GND A18 (35)
DPHY_IF1_RST IN/OUT A19 (37) Camera Reset
GND A20 (39)
DPHY_IF1_I2C_SC IN/OUT A21 (41) I2C for Camera
L configuration
DPHY_IF1_I2C_SD IN/OUT A22 (43)
A
GND A23-A30 (45-59)
P12V B1 (2) 12V provided by
proFPGA System
P12V B2 (4)
GND B3 (6)
Extension Boards

Connector
P3V3 B4 (8) 3.3V provided by
proFPGA System
P3V3 B5 (10)
GND B6 (12)
P3V3_AUX B7 (14) 3.3V AUX provided
by proFPGA System
GND B8 (16)
PV_IO B9 (18) PV_IO provided by
proFPGA System
PV_IO B10 (20)
GND B11 (22)
I2C_SCL OUT B12 (24) proFPGA I2C
I2C_SDA IN/OUT B13 (26)
GND B14 (28)
PVADJ1 B15 (30) Camera voltage 1
max 0.5A
PVADJ1_EN IN B16 (32) PSU1 enable (10k
Pull down at
Extension board)
NC - B17 (34) Not Connected
GND B18 (36)
max 0.5A
Pull down at
Extension board)
NC - B21 (42) Not Connected
GND B22 (44)
Extension Boards

Connector
DPHY_IF1_GPIO0 IN/OUT B23 (46) Camera GIPO
(PV_IO level)
DPHY_IF1_GPIO1 IN/OUT B24 (48)

Connector
GND A31 (61)
DPHY_IF2_D_N0 IN/OUT A32 (63) MIPI CSI Data lane
GND A34 (67)
GND A37 (73)
GND A40 (79)
GND A43 (85)
GND A46 (91)
Extension Boards

Connector
DPHY_IF2_REF_C IN/OUT A47 (93) Camera Reference
LK CLK
GND A48 (95)
DPHY_IF2_RST IN/OUT A49 (97) Camera Reset
GND A50 (99)
DPHY_IF2_I2C_SC IN/OUT A51 (101) I2C for Camera
L configuration
A
GND A53-A60 (105-119)
GND B31 (62)
GND B32 (64)
proFPGA System
P12V B34 (66)
GND B35 (67)
proFPGA System
P3V3 B37 (69)
GND B38 (70)
by proFPGA System
GND B40 (72)
proFPGA System
PV_IO B42 (74)
GND B43 (75)
max 0.5A
GND B45 (77)
max 0.5A
GND B47 (79)
Extension Boards

Connector
NC B48-B51 (80-102) Not connected
GND B52 (104)
(PV_IO level)

This topic discusses extension board operating conditions of MIPI DPHY RX (EB-PDS-MIPI-
DPHY-RX-R1).
Table 6-260. EB-PDS-MIPI-DPHY-RX-R1 – Extension Board Operating

Conditions
IO voltage (min…recommended…max) 1.710V…1.8V… 2.625V

This topic discusses FPGA extension sit compatibility of MIPI DPHY RX (EB-PDS-MIPI-
DPHY-RX-R1).
Extension Boards
Table 6-261. EB-PDS-MIPI-DPHY-RX-R1 – FPGA Extension Site Compatibility

FPGA TA1 TA2 TB1 TB2 BA1 BA2 BB1 BB2 TA1 TA2
Module V1 V1
FM- √ √ √ √ √ √ √
XC7V2000T
-R1
FM- √ √ √ √ √ √ √
XC7V2000T
-R2
FM- √ √ √
XC7VX330
T-R3
FM- √ √ √
XC7VX485
T-R3
FM- √ √ √ √
XC7V585T-
R3
FM- √ √ √ √
XC7VX690
T-R3
FM- √ √
XC7Z100-
R1
FM- √ √
XC7Z045-
R1
FM- √ √ √ √ √ √ √ √
XCVU440-
R1
FM- √ √ √ √ √ √ √ √
XCVU440-
R2
FM- √ √ √ √
XCVU190-
R1
FM- √ √ √ √
XCVU160-
R1
Extension Boards

Module V1 V1
FM- √ √ √ √
XCVU125-
R1
FM- √ √ √ √
XCVU095-
R1
FM- √ √ √ √
XCVU080-
R1
FM- √ √ √ √
XCKU115-
R1
FM- √ √ √ √
XCVU5P-
R1
FM- √ √ √ √
XCVU7P-
R1
FM- √ √ √ √
XCVU9P-
R1
FM- √ √ √ √
XCVU13P-
R1
FM- √ √ √ √ √ √ √ √
XCVU19P-
R1
FM- √ √ √
XCVU37P-
R1
FM- √ √ √
XCVU47P-
R1
FM- √ √ √ √ √ √ √
1SG280<L,
H>-R1
Extension Boards

Module V1 V1
FM- √ √ √
XCZU19EG
-R2
FM- √ √ √
XCZU17EG
-R2
FM- √ √
XCZU11EG
-R2
FM- √ √ √ √ √ √ √
1SG280<L,
H>-R2
FM- √ √ √ √
10AX115-
R1
FM- √ √ √ √ √ √ √ √
1SG10M-R1
Table 6-262. EB-PDS-MIPI-DPHY-RX-R1 – FPGA Extension Site Compatibility,

Module
FM- √ √ √ √ √ √
1SG10M-R1
FM- √ √ √ √
XCVU19P-
R1

This topic discusses FPGA pin constraints of MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1).
Table 6-263. EB-PDS-MIPI-DPHY-RX-R1–FPGA Pin Constraints

DPHY_IF*_HS_ * IOSTANDARD = LVDS
Extension Boards
Related Work
Table 6-263. EB-PDS-MIPI-DPHY-RX-R1–FPGA Pin Constraints (cont.)

all other IO signals IOSTANDARD =
LVCMOS18
Related Work
This topic discusses related work of MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1).
profpga_run
<instance name>:
{
type = "BOARD";
name = "EB-PDS-MIPI-DPHY-RX-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-MIPI-DPHY-RX-R1”.
Please refer to the proFPGA Software Reference Manual” [UD002] and the “proFPGA Builder
Startup with MIPI DPHY Extension Board

The Meticon Chips drives the IO pins of the FPGA before the PV_IO voltage of the FPGA is
applied. Therefore, the proFPGA Host software will bring an error at startup. To avoid this
Extension Boards
Order Code
Order Code
This topic discusses order code of MIPI DPHY RX (EB-PDS-MIPI-DPHY-RX-R1).
286499
Extension Boards
MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1)
MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1)

This topic discusses MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
This topic discusses functional description of MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1).
The proFPGA MIPI DPHY TX board provides two MIPI D-PHY transmitter interfaces. To be
compatible with FPGA supported IO standards, two Meticon MC20902 MIPI to FPGA bridges
convert LVDS and low power LVCMOS signals to a MIPI conformal signal standard.
• compliant to MIPI D-PHY CSI-1, CSI-2 standard

• transfer rates up to 2.5Gbps (HS mode), 20MBps (LPDT mode)
• two camera interfaces
• each camera interface supports up to four data lanes
• eight GPIOs, a dedicated I²C interface, reset and reference clock available for each
camera interface
• two adjustable onboard PSUs for camera use
• LP Signals supports different I/O-Voltages
• Bus turn-around for data lane 0 at each interface
• proFPGA MIPI DPHY TX extension board, which will be plugged on a free extension
site of a proFPGA FPGA module
Extension Boards
Figure 6-161. EB-PDS-MIPI-DPHY-TX-R1
Extension Boards
Figure 6-162. EB-PDS-MIPI-DPHY-TX-R1 Board Overview
Table 6-264. MIPI DPHY TX Board Signal Description

MIPI DPHY Signls
DPHY_IF[12]_HS_DATA_[NP][0..3] MIPI highspeed data lanes, bus turnaround
DPHY_IF[12]_LP_DATA_[NP][0..3] MIPI low power data lanes, bus turnaround
DPHY_IF[12]_HS_CLK_[NP] MIPI highspeed clock lane
DPHY_IF[12]_LP_CLK_[NP] MIPI low power clock lane
MIPI bridge control signals
Extension Boards
Table 6-264. MIPI DPHY TX Board Signal Description (cont.)

DPHY_IF[12]_BTA Enables bus turnaround (active high), must
always be driven at a valid level by the
FPGA (e.g. low if not used)
Additional camera signals
DPHY_IF[12]_CLK Reference clock I/O
DPHY_IF[12]_RST Reset I/O
DPHY_IF[12]_ I2C_SDA Camera control I²C interface
DPHY_IF[12]_ I2C_SCL
DPHY_IF[12]_GPIO[0..7] GPIOs
This board has no camera specific connector; thus, a customer specific camera adapter board or
cable is required. To connect a specific board or cable a Samtec QSH-060-01-L-D-A is placed
on the board. This connector mates with Samtec QTE-060 Series (e.g. QTH-060-01-H-D-A)
and HQCD series cables.
Figure 6-163. Camera aAdapter Board Connector Samtec QSH-060-01-L-D-A

Signal name Direction Mapping to camera Description
connector
GND A1 (1)
DPHY_IF1_D_N0 IN/OUT A2 (3) MIPI CSI data lane
GND A4 (7)
DPHY_IF1_D_N1 IN A5 (9) MIPI CSI data lane
GND A7 (13)
Extension Boards

connector
GND A10 (19)
GND A13 (25)
GND A16 (31)
DPHY_IF1_REF_C IN/OUT A17 (33) Camera reference
LK CLK
GND A18 (35)
DPHY_IF1_RST IN/OUT A19 (37) Camera reset
GND A20 (39)
DPHY_IF1_I2C_SC IN/OUT A21 (41) I2C for camera
L configuration
A
GND A23-A30 (45-59)
proFPGA system
P12V B2 (4)
GND B3 (6)
proFPGA system
P3V3 B5 (10)
GND B6 (12)
by proFPGA system
GND B8 (16)
proFPGA System
PV_IO B10 (20)
Extension Boards

connector
GND B11 (22)
I2C_SCL OUT B12 (24) proFPGA I2C
I2C_SDA IN/OUT B13 (26)
GND B14 (28)
max 0.5A
Pull down at
extension board)
NC B17 (34) Not connected
GND B18 (36)
max 0.5A
Pull down at
extension board)
NC B21 (42) Not connected
GND B22 (44)
(PV_IO level)

connector
GND A31 (61)
Extension Boards

connector
DPHY_IF2_D_N0 IN/OUT A32 (63) MIPI CSI data lane
GND A34 (67)
GND A37 (73)
GND A40 (79)
GND A43 (85)
GND A46 (91)
DPHY_IF2_REF_C IN/OUT A47 (93) Camera reference
LK CLK
GND A48 (95)
DPHY_IF2_RST IN/OUT A49 (97) Camera reset
GND A50 (99)
DPHY_IF2_I2C_SC IN/OUT A51 (101) I2C for camera
L configuration
A
GND A53-A60 (105-119)
GND B31 (62)
NC B32-B51 (64-102) Not connected
GND B52 (104)
Extension Boards

connector
(PV_IO level)

This topic discusses extension board operating conditions of MIPI DPHY TX (EB-PDS-MIPI-
DPHY-TX-R1).
Table 6-267. EB-PDS-MIPI-DPHY-TX-R1 – Extension Board Operating

Conditions
IO voltage provider FPGA module for FPGA bank and extension
board for itself

This topic discusses FPGA extension site compatibility of MIPI DPHY TX (EB-PDS-MIPI-
DPHY-TX-R1).
Table 6-268. EB-PDS-MIPI-DPHY-TX-R1 – FPGA Extension Site Compatibility

V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
Extension Boards
Table 6-268. EB-PDS-MIPI-DPHY-TX-R1 – FPGA Extension Site Compatibility

V1 V1
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √
FM-XCVU125-R1 √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Extension Boards
Table 6-269. EB-PDS-MIPI-DPHY-TX-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

This topic discusses FPGA pin constraints of MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1).
Table 6-270. EB-PDS-MIPI-DPHY-TX-R1–FPGA Pin Constraints

DPHY_IF*_HS_ * IOSTANDARD = LVDS
all other IO signals IOSTANDARD =
LVCMOS18
Related Work
This topic discusses related work of MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1).
profpga_run
<instance name>:
{
type = "BOARD";
name = "EB-PDS-MIPI-DPHY-TX-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.
Extension Boards
Order Code

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-MIPI-DPHY-TX-R1”.
Order Code
This topic discusses order code of MIPI DPHY TX (EB-PDS-MIPI-DPHY-TX-R1).
286493
Extension Boards
DisplayPort Extension Board (EB-PDS-DP-R1)
DisplayPort Extension Board (EB-PDS-DP-R1)

This topic discusses DisplayPort extension board (EB-PDS-DP-R1).

I²C Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
DisplayPort – Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
This topic discusses functional description of DisplayPort extension board (EB-PDS-DP-R1).
The DisplayPort extension board provides 3 independent upstream and 3 independent
downstream channels, all accessible through full-size DisplayPort connectors.
• One proFPGA bottom connector for connection to the proFPGA system

• One proFPGA top connector make all unused regular IOs of the bottom connector
available for further use (e.g., to connect a cable for interconnections to other FPGA)
• One IDPROM for board identification
• 3 upstream channels HBR3 (8.1GT/s) with up to 4 Tx lanes (data rate qualification
pending)
• 3 downstream channels HBR3 (8.1GT/s) with up to 4 Rx lanes (data rate qualification
pending)
• DisplayPort 1.4 conformal Repeater on all upstream and downstream channels (I2C
programmable via proFPGA plugin, gain settings 0dB … 14dB)
• Bidirectional AUX channel on all upstreams and downstreams (Note: only native AUX
speed grade is supported - 1Mbit/s)
• HotPlug capability on all channels
• 6 DisplayPort connectors, all delivering DP_PWR with 3.3V up to 500mA
Extension Boards
• HDCP support (one EEPROM for HDCP key storage on all downstream channels)
Each of the 3 upstream, and downstream channels respectively, can be used by the HDL design
individually. The following tables show all FPGA accessible signals of the upstream and
downstream interface, as well as some global signals. Please note, that all 3 instances of up- and
downstream channels are identical, and the signal direction is FGPA/HDL referenced.
Figure 6-164. EB-PDS-DP-R1 - Front View
Table 6-271. proFPGA Connector - DisplayPort Downstream Signals

(Excluding MGT Lanes)
Signal Name Default Active Value Description
Value
DP[0:2]_RX_AUX_ O 0b0 0b[0,1] Output enable of AUX
OE channel LVDS transceiver
0 – LVDS transceiver in
receive mode
transmit mode
DP[0:2]_RX_AUX_ O 0b0 0b[0,1] SE bitdata transmitted on
DOUT AUX channel
DP[0:2]_RX_AUX_ I 0b1 0b[0,1] SE bitdata received from
DIN AUX channel
DP[0:2]_RX_AUX_ I 0b0 0b1 SE AUX_P signal (inverted)
SENS_P_INV 0 – no DP upstream device
detected
1 – DP upstream detected
Extension Boards

(Excluding MGT Lanes) (cont.)
Value
DP[0:2]_RX_AUX_ I 0b1 0b0 SE AUX_N signal
SENS_N_INV (inverted)
0 – DP upstream device
detected
1 – no DP upstream device
detected
DP[0:2]_RX_HPD O 0b0 0b1 Hot plug detection signal
0 – downstream device not
ready for AUX data
1 – downstream device
ready for AUX data
DP[0:2]_RX_DPPW O 0b0 0b1 Enable signal for
R_EN DisplayPort Power
0 – DPPWR on DP
connector Pin 20 disabled
1 – DPPWR on DP
connector Pin 20 enabled
DP[0:2]_RX_CAD_ O 0b1 0b0 CAD (cable adaptor
TEST detection) test probe
Note: not intended for
normal operation
DP[0:2]_RX_CAD_ I 0b1 0b0 CAD short circuit detection
SC_IN_INV (inverted)
Note: used in conjunction
with CEC_SC to detect
cable adaptors requesting
DPPWR
DP[0:2]_RX_CEC_ O 0b1 0b0 CEC short circuit detection?
SC 0 – apply probe voltage on
DP connector Pin 14
1 – leave DP connector Pin
14 unaffected
Extension Boards

(Excluding MGT Lanes) (cont.)
Value
DP[0:2]_RX_I2C_A I/O 0b1 0b[0,1] I2C bus signals used to
UX_[SCL,SDA] perform optional I2C onto
AUX feature
with voltage on DP
connector Pin 13
DP[0:2]_Rx_I2C_H I/O 0b1 0b[0,1] I2C bus to access the HDCP
CDP_[SCL,SDA] related EEPROM on
address 0x50
Table 6-272. proFPGA Connector - DisplayPort Upstream Signals (Excluding

MGT Lanes)
Value
DP[0:2]_TX_AUX_ O 0b0 0b[0,1] Output enable of AUX
OE channel LVDS transceiver
receive mode
transmit mode
DP[0:2]_TX_AUX_ O 0b0 0b[0,1] SE bitdata transmitted on
DOUT AUX channel
DP[0:2]_TX_AUX_ I 0b1 0b[0,1] SE bitdata received from
DIN AUX channel
DP[0:2]_TX_HPD_ I 0b1 0b0 Hot plug detection signal
SENS_INV (inverted)? 0 – downstream
device ready for AUX data
1 – downstream device not
ready for AUX data
DP[0:2]_TX_CAD_ O 0b1 0b0 CAD cable adaptor
SENS_INV detection signal (inverted)?
0 – cable adaptor device
detected
1 – no cable adaptor device
detected
Extension Boards
Table 6-272. proFPGA Connector - DisplayPort Upstream Signals (Excluding

MGT Lanes) (cont.)
Value
DP[0:2]_TX_CEC_I I 0b1 0b0 CEC receive signal
N_INV (inverted)
0 – high on DP connector
Pin 14
1 – low on DP connector Pin
14
DP[0:2]_TX_CEC_ O 0b0 0b1 CEC transmit signal? 0 –
OUT high on DP connector Pin
14
1 – low on DP connector Pin
14
DP[0:2]_TX_I2C_A I/O 0b1 0b[0,1] I2C bus signals used to
UX_[SCL,SDA] perform optional I2C onto
AUX feature
with voltage on DP
connector Pin 13
Table 6-273. proFPGA Connector - EB-PDS-DP-R1 Misc Signals

Value
DP_I2C_REP_CON I/O 0b1 0b[0,1] I2C bus signals allowing to
F_[SCL,SDA] configure the TDP142
DisplayPort repeater at
runtime
Note: all repeaters share the
same I2C bus
TP_DEBUG I/O 0b[0,1] FPGA controlled pin,
intended for debugging
purposes on HDL designs
Note: the signal can be
probed on TP13 of the EB-
PDS-DP-R1
Extension Boards

This topic discusses functional block diagram of DisplayPort extension board (EB-PDS-DP-
R1).
Figure 6-165. EB-PDS-DP-R1 - Functional Block Diagram
Extension Boards
I²C Topology
I²C Topology
This topic discusses I2C topology of DisplayPort extension board (EB-PDS-DP-R1).
The EB-PDS-DP-R1 accomodates several independent I2C bus interfaces on its proFPGA
XEBA1 connector, used for different functional domains of the extension board:
• XEBA_I2C: I2C bus used by proFPGA system to identify IDPROM and communicate
with top connector mounted extension boards (refer to UD003 for details); used by the
proFPGA plguins to program clock generator and DisplayPort repeaters
• DP[0:2]_TX_I2C_AUX: I2C bus used for the I2C onto AUX feature on the DisplayPort
upstream channels
• DP[0:2]_RX_I2C_AUX: I2C bus used for the I2C onto AUX feature on the DisplayPort
downstream channels
• DP[0:2]_RX_I2C_HDCP: I2C bus used for the HDCP EEPROM storage, related to the
DisplayPort downstream channels
• DP_I2C_REP_CONF: I2C bus intended for auxiliary access to the I2C based
DisplayPort repeaters; can be used to configure the repeaters while the system is running
Extension Boards
DisplayPort – Additional Features
Figure 6-166. EB-PDS-TP-R1 - I2C Bus Topology

This topic discusses additional features of DisplayPort extension board (EB-PDS-DP-R1).
Beside the main functions of the DisplayPort standard (AUX communication + MGT lanes), the
EB-PDS-DP-R1 supports a few additional features. This section only gives a short overview,
for further details please refer to the DisplayPort standard.
Extension Boards
Bidirectional AUX channel

The AUX communication channel itself is not an additional feature at all but one should note,
that the data transmission is achieved by using an LVDS transceiver, delivering single-ended
signals for data out and data in. In addition, there is a data direction signal present, which allows
to send or receive data on the differential AUX domain and has to be set accordingly.
Figure 6-167. EB-PDS-DP-R1 - LVDS Transceiver Circuitry
Table 6-274. EB-PDS-DP-R1 - LVDS Transceiver

Texas Instruments IC TRANSCVR M- 32-WQFN DS91M040TSQ/
LVDS QUAD NOPB
250MBPS
DisplayPort Power
All upstream and downstream channels deliver a 3.3V power supply on Pin 20 of their
respective DP connector, limited to 500mA current to power cable adaptor devices. According
to Figure 6-165, the 3.3V has to be enabled by the FPGA on all downstream channels, based on
a proper cable adaptor identification scheme (DisplayPort Power User Detection Method) on
the pins 13 and 14 of the DP connector.
Extension Boards
Figure 6-168. EB-PDS-DP-R1 - DisplayPort Power 3V3 Downstream
I2C onto AUX

According to the DisplayPort standard, it is possible to use the 3.3V terminated intermediate
AUX domain as an I2C sideband channel. This feature is primarly intended to allow the
implementation of an appropriate I2C transaction protocol which is beyond the scope of this
document and has to be achieved by the customer in case of need.
To activate the I2C mapping, the CAD signal (residing on Pin 13 of the PD connector of a
DisplayPort channel) has to be set to 3.3V, independent of the fact if it is an upstream or
downstream channel.
Figure 6-169. EB-PDS-DP-R1 - I2C onto AUX Mapping
CAD Sensing
Each upstream channel is capable of sensing a CAD signal (cable adaptor detection) present on
Pin 13 of its DP connector. This signal allows to detect an externally attached adaptor and
initiate CEC based communication.
Each downstream channel is capable of sensing the CAD signal on the same pin, as well, but the
use is restricted for the CAD/CEC short circuit detection procedure, which is part of the Display
Power User Detection Method.
Extension Boards
In addition, the CAD signal can be used by an external adaptor to enable the I2C onto AUX
feature on both, up- and downstream channels, as well, by driving 3.3V on CAD.
Tip
Please note, the CAD signal present on all downstream channels is intended to be used as an
input signal, only. In addition, it can be asserted by the FGPA logic for loopback tests, but
should not be used in normal operation mode (only for testing at Siemens).
CEC Communication
The EB-PDS-DP-R1 supports a minimal bidirectional CEC interface on all upstream channels,
allowing to communicate with external HDMI compliant devices, using the CEC signals for
configuration of multimedia features (e.g. remote access from multimedia players to TV
panels). The interface consists of a single open-drain signal, present on Pin 14 of the respective
DP connector. Implementation of an appropriate CEC transaction protocol is beyond the scope
of this document and has to be achieved by the customer in case of need.
Figure 6-170. EB-PDS-DP-R1 - Bidirectional CEC Circuitry
Note
Please note, there is an unidirectional CEC output signal present on all downstream
channels as well, which is intended to be used for cable adaptor detection only.

This topic discusses extension board operating conditions of DisplayPort extension board (EB-
PDS-DP-R1).
Extension Boards
Table 6-275. EB-PDS-DP-R1 - Extension Board Operating Conditions


This topic discusses FPGA extension site compatibility of DisplayPort extension board (EB-
PDS-DP-R1).
Each sink/source DisplayPort channel can be used with 1x/2x/4x lane configuration
individually. This allows for a reduced bandwith operation mode in case of insufficient MGT
lanes on a given proFPGA connector. In addition, it is suitable to use only one or two up-/
downstream channels at once and leave the others inactive.
Depending on the populated proFPGA connector in conjunction with the given FPGA module,
there could be restrictions to the number of HDL accessible channels, resulting in the following
compatibility list:
In the table below, (1) only 2 Rx/Tx channel pairs (4 lanes) due to insufficient MGT channels
(2)
only 2 Rx/Tx channel pairs (4 lanes) due to insufficient IO pins
(2a)
1 Rx/Tx channel pair (4 lanes) and 1 Rx/Tx channel pair (2 lanes) due to insufficient MGT
channels
(3) only 1 Rx/Tx channel pair (4 lanes) due to insufficient MGT channels
(4)
only 1 Rx/Tx channel pair (4 lanes) due to insufficient IO pins
Table 6-276. EB-PDS-DP-R1 - Extension Site Compatibility
FM-XC7VX330T-R3 √(1) √(1) √(4)
FM-XC7VX485T-R3 √(1) √(1) √(4)
FM-XC7V585T-R3 √(1) √(1) √(1) √
FM-XC7VX690T-R3 √(1) √(1) √(1) √
FM-XC7V2000T-R1 √(1) √(4)
FM-XC7V2000T-R2 √(1) √(1)
Extension Boards
Table 6-276. EB-PDS-DP-R1 - Extension Site Compatibility (cont.)

FM-XC7Z035-R1 √(1) √(1)
FM-XC7Z045-R1 √(1) √(1)
FM-XC7Z100-R1 √(1) √(1)
FM-XCKU115-R1 √(1) √(1) √(1) √(2) √(4) √(4)
FM-XCVU080-R1 √(1) √ √(3) √(2) √(4) √(4)
FM-XCVU095-R1 √(1) √ √(3) √(2) √(4) √(4)
FM-XCVU125-R1 √ √ √ √(2) √(4) √(4)
FM-XCVU160-R1 √ √ √ √(2) √(4) √(4)
FM-XCVU190-R1 √ √ √ √(2) √(4) √(4)
FM-XCVU440-HP-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU440-R1 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU440-R2 √(1) √(1) √(1) √(1) √(1) √(1)
FM-XCVU5P-R1 √ √ √ √(2) √(4) √(4)
FM-XCVU7P-R1 √ √ √ √(2) √(4) √(4)
FM-XCVU9P-R1 √ √ √ √(2) √(4) √(4)
FM-XCVU19P-R1 √ √ √ √
FM-XCVU37P-R1 √ √ √(4) √
FM-XCVU47P-R1 √ √ √(4) √
FM-XCZU11EG-R2 √(1) √(1)
FM-XCZU17EG-R2 √(1) √(1)
FM-XCZU19EG-R2 √(1) √(1)
FM-1SG280L-R1 √ √(2a) √(2a)
FM-1SG280L-R2 √ √(2a) √(2a)
FM-1SG280H-R1 √ √(2a) √(2a)
FM-1SG280H-R2 √ √(2a) √(2a)
Extension Boards
Table 6-276. EB-PDS-DP-R1 - Extension Site Compatibility (cont.)

FM-1SG10M-R1 √ √ √ √
FM-10AX115-R1 √ √ √ √

This topic discusses FPGA pin constraints of DisplayPort extension board (EB-PDS-DP-R1).
Table 6-277. EB-PDS-DP-R1 - FPGA Pin Constraints

all IO signals IOSTANDARD = IO_STANDARD "1.8 V"
LVCMOS18
O"
MGT/XCVR REFCLK IO_STANDARD “LVDS”
Related Work
This topic discusses related work of DisplayPort extension board (EB-PDS-DP-R1).
Extension Boards
Related Work
profpga_run
<instance name>:
{
type = "BOARD";
name = " EB-PDS-DP-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
# TDP142 Hex Plugin settings
# <tdp142_instance> = [dp_sink0, dp_sink1, dp_sink2,
# dp_source0, dp_source1, dp_source2]
<tdp142_instance> :
{
SWAP_HPDIN = 0;
EQ_OVERRIDE = 0;
HPDIN_OVRRIDE = 0;
CTLSEL0 = 1;
CTLSEL1 = 0;
AUX_SNOOP_DISABLE = 0;
DP0_DISABLE = 0;
DP1_DISABLE = 0;
DP2_DISABLE = 0;
DP3_DISABLE = 0;
DP0EQ_SEL = 0;
DP1EQ_SEL = 0;
DP2EQ_SEL = 0;
DP3EQ_SEL = 0;
};
};
more information.

information.
Extension Boards
Related Work
<tdp142_instance> has to be instantiated six times, one for each upstream (dp_source[0:2]) and
each downstream (dp_sink[0:2]) channel.
Plugin Si5338
...
plugin_list = ( "si5338 ProDesign EB-PDS-DP-R1" ,
"tdp142_hex ProDesign EB-PDS-DP-R1" );
{
...
If there is already a plugin_list entry, the plugin list must be extended. Example:
...
"si5338 ProDesign EB-PDS-DP-R1" ,
"tdp142_hex ProDesign EB-PDS-DP-R1" );
{
...
This will load the Si5338 and the TDP142 Hex plugins.

Plugin TDP142 Hex

The EB-PDS-DP-R1 features the TDP142 DisplayPort v1.4 compliant repeater on all upstream
and downstream channels, configured to be programmed via a dedicated I2C interface. In order
to perform a proper register configuration on power up, the tdp142_hex plugin can be used,
setting all register values according to the desired values, listed in the .CFG file.
The previously given tdp142_instance descriptors are corresponding to the silkscreen indication
on the extension board.
Table 6-278 gives an overview of the parameters, accessible by the tdp142_hex plugin.
Extension Boards
Related Work
Table 6-278. TDP142_hex Plugin Parameters

SWAP_HPDIN 0b0 0b[0,1] 0 – HPDIN is in
default location
1 – HPDIN location
is swapped (Pin 23 to
Pin 32)
EQ_OVERRIDE 0b0 0b[0,1] 0 – EQ settings based
on sampled state of
the EQ pins
(DPEQ[1:0])
1 – EQ settings based
on sampled state of
the EQ pins
HPDIN_OVRRIDE 0b0 0b[0,1] 0 – HPD based on
state HPDIN
1 – HPD high
CTLSEL[1:0] 0b01 0d[0:3] 0 – Shutdown. DP
disabled and lowest
power state
1 – DP disabled but
not in lowest power
state
2 – DP enabled
3 – Reserved
AUX_SNOOP_DIS 0b0 0b[0,1] 0 – AUX snoop
ABLE enabled
1 – AUX snoop
disabled
DP[0:3]_DISABLE 0b0 0b[0,1] 0 – DP Lane [0:3]
enabled
1 – DP Lane [0:3]
disabled
Extension Boards
Order Code
Table 6-278. TDP142_hex Plugin Parameters (cont.)

DP[0:3]EQ_SEL 0d0 0d[0:14] Field selects between
0 to 14dB of EQ for
DP lane [0:3]. When
EQ_OVERRIDE =
1’b1, software can
change the EQ
setting for DP lane
[0:3] based on the
value written to this
field.

With the profpga_brdgen tool, top level HDL files and pin location constraints files can be
plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-DP-R1”. The system
configuration file can be created directly or with the profpga_builder tool.
Order Code
This topic is about Order Code of DisplayPort extension board (EB-PDS-DP-R1).
286527
Extension Boards
Interface Board (EB-PDS-INTERFACE-R1/R8)
Interface Board (EB-PDS-INTERFACE-R1/R8)

This topic is about Interface Board (EB-PDS-INTERFACE-R1/R8)

Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
DIP Sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
FAN Control IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
I²C Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
PMBUS Power Supply Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
PMBUS Controller Isolated PSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
EJTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
SGPIO Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
GPIO Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
This topic discusses about the functional description of the extension board (EB-PDS-
INTERFACE-R1/R8).
The proFPGA Interface Board has a proFPGA Bottom and a proFPGA Top Connector. It
provides several interfaces and memories to the user.
This proFPGA extension board supports the following features:
• One proFPGA Bottom Connector

• One proFPGA Top Connector
• 1x SGPIO connector
• 2x MiniUSB UART connectors
• 1x EJTAG connector
• 8 GPIO pins available
Extension Boards
• 2x DIP sockets
• 1x I2C Connector
• I2C Fan Control Unit
• PMBus 6-channel Power-Supply Manager
• PMBus Isolated Power-Supply Controller
• 2x I2C EEPROM
• 2x 128M SPI Flash
• 8 RGB LEDs
Figure 6-171. EB-PDS-INTERFACE-R1/R8

This chapter is about Extension Boards.
Table 6-279. EB-PDS-INTERFACE-R1/R8 – Extension Board Operating

Conditions
IO voltage (min: recommended: max) 1.71V: 1.80V: 1.89V
Extension Boards
Note
The bottom connector of the EB-PDS-INTERFACE-R1/R8 board has a bigger stacking
height of 13mm instead of 10mm. Because of that, higher spacers are needed (M3x13
instead of M3x10).

In the table below, (1) I²C, DIP_SEEPROM, EEPROM, FAN, PMBUS Usable; (2)All But
Without GPIO, (3) Using EB-FM-XCVU440-R1, (4) I²C, DIP_SEEPROM, EEPROM, FAN,
(5) SGPIO, EJTAG
Table 6-280. EB-PDS-INTERFACE-R1/R8– FPGA Extension Site Compatibility
V1 V2
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √(1)
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √(1)
FM-XC7VX330T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7VX485T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7V585T-R3 √ √(2) √ √ √ √(1)
FM-XC7VX690T-R3 √ √(2) √ √ √ √(1)
FM-XC7Z100-R1 √(2) √
FM-XC7Z045-R1 √(2) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(
3) 3)
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(1)( √(1)(

3) 3)
FM-XCVU190-R1 √ √ √ √(1,5 √(4) √(4)

)
FM-XCVU160-R1 √ √ √ √(1,5 √(4) √(4)

)
Extension Boards

V1 V2
FM-XCVU125-R1 √ √ √ √(1,5 √(4) √(4)
)
FM-XCVU095-R1 √ √ √ √(1,5 √(4) √(4)

)
FM-XCVU080-R1 √ √ √ √(1,5 √(4) √(4)

)
FM-XCKU115-R1 √ √ √ √(1,5 √(4) √(4)

)
FM-XCVU5P-R1 √ √ √ √(1,5 √(4) √(4)

)
FM-XCVU7P-R1 √ √ √ √(1,5 √(4) √(4)

)
FM-XCVU9P-R1 √ √ √ √(1,5 √(4) √(4)

)
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(
3) 3)
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-XCZU19EG-R2 √ √ √(1,5 √(1) √
)
FM-XCZU17EG-R2 √ √ √(1,5 √(1) √

)
FM-XCZU11EG-R2 √ √ √(1,5 √(1)

)
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
Extension Boards

V1 V2
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(
3) 3)
EB-PDS-INTERFACE-R1/R8– FPGA extension site compatibility;
(1)
I²C, DIP_SEEPROM, EEPROM, FAN, PMBUS useable;
(2)all but without GPIO,
(3)
(4) I²C,
DIP_SEEPROM, EEPROM, FAN ,
(5) SGPIO,
EJTAG
Table 6-281. EB-PDS-INTERFACE-R1/R8 – FPGA Extension Site Compatibility,
[B,T][A,AB,B] 0 Connectors
FM-1SG10M-R1 √ √ √ √ √ √

Table 6-282. EB-PDS-INTERFACE-R1/R8–FPGA Pin Constraints

All IO signals LVCMOS18
The signals are named to the corresponding functional group they depend on.
Extension Boards
Figure 6-172. Signal Connections of the proFPGA Interface Board Bottom

Connector
Figure 6-173. Signal connections of the proFPGA Interface Board Bottom

Connector (Extended)
Extension Boards
Flash Memories
Flash Memories
The following memories are being assembled on the EB-PDS-INTERFACE-R1/R8 board:
Table 6-283. EB-PDS-INTERFACE-R1/R8–Flash Memories

Flash Type Manufacturer OrderCode Memory Bus
Capacity
SPI Flash(-R1) Micron N25Q128A11ESE 128 Mbit SPI_FLASH0,
40G SPI_FLASH1
SPI Flash(-R8) ISSI IS25WP128-JBLE
I2C Flash ON CAT24C08WI- 8 Kbit I2C_USER1
GT3
I2C Flash Microchip 24AA1026-I/SN 1 Mbit I2C_USER2
DIP Sockets
Two DIP sockets are available on the EB-PDS-INTERFACE-R1/R8 board.
Table 6-284. Pinout DIP Socket X3 for SPI Flash

Signal Name DIP socket pin Description
SPI_DIP_nCS 1 Chip Select with 2K PU
SPI_DIP_SDO 2 Serial Data Out
SPI_DIP_WP 3 Write Protect
GND 4 Ground
SPI_DIP_SDI 5 Serial Data In
SPI_DIP_SCK 6 Serial Clock
SPI_DIP_nHOLD 7 Hold Signal
PV_IO 8 VCC Voltage
Table 6-285. Pinout DIP Socket X4 for I2C Flash

DIP_A0_3V3 1 Address Bit 0
Extension Boards
FAN Control IC
Table 6-285. Pinout DIP Socket X4 for I2C Flash (cont.)

GND 4 Ground
I2C_USER3_SCL 5 I2C Serial Clock
I2C_USER3_SDA 6 I2C Serial Data
DIP_WP_3V3 7 Write Protect
P3V3 8 3.3V VCC Voltage
FAN Control IC
On the EB-PDS-INTERFACE-R1/R8, there is a FAN control IC available which can be
configured via I2C Bus and which can control a FAN which is connected to X2.
Table 6-286. Fan Control IC

Manufacturer Order Code Bus I2C Address
Maxim MAX6650EUB+T I2C_USER0 0x48
Extension Boards
I²C Connector
The pinout of the IC is as follows:
Figure 6-174. Pinout FAN Control IC on EB-PDS-INTERFACE-R1/R8
Pinout of the FAN connector X2:

Table 6-287. Pinout FAN Connector X2
Signal Name Connector Pin Description
FAN_CTRL_FB 1 Feedback Signal
P12B 2 12V
FAN_CTRL_TACHO 3 Tacho Signal
I²C Connector
The I2C Connector X1 provides direct access to the I2C Bus I2C_USER1 with the following
pinout:
Extension Boards
PMBUS Power Supply Manager
Table 6-288. Pinout I2C Connector X1

Signal Name Connector Pin Description
P3V3 1 3.3V
I2C_USER1_SCL_3V3 2 I2C Serial Clock
I2C_USER1_SDA_3V3 3 I2C Serial Data
GND 4 Ground
PMBUS Power Supply Manager

A Power Supply Manager with PMBUS Interface (IC6) is provided with the following pinout:
Extension Boards
PMBUS Controller Isolated PSU
Figure 6-175. Pinout of PMBUS Power Supply Manager on EB-PDS-

INTERFACE-R1/R8
PMBUS Controller Isolated PSU

A Controller Isolated PSU is available on the EB-PDS-INTERFACE-R1/R8 board (IC7).
Extension Boards
EJTAG Connector
Figure 6-176. Pinout PMBUS Controller Isolated PSU
EJTAG Connector
The EJTAG connector (X7) on the EB-PDS-INTERFACE-R1/R8 board has got the following
Pinout.
Figure 6-177. Pinout EJTAG Connector EB-PDS-INTERFACE-R1/R8
Extension Boards
SGPIO Connector
SGPIO Connector
The SGPIO Connector (X6) has got the following Pinout.
Figure 6-178. Pinout SGPIO Connector on EB-PDS-INTERFACE-R1/R8
GPIO Connector
The GPIO Connector (X5) has got the following Pinout.
Figure 6-179. GPIO Connector on EB-PDS-INTERFACE-R1/R8
Related Work
Extension Boards
Order Code
profpga_run
For this board, the following x-board entry is required within the system configuration file:
<instance name>:
{
type = "BOARD";
name = " EB-PDS-INTERFACE-R8";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

With the profpga_brdgen tool, top level HDL files and pin location constraints files can be
plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-INTERFACE-R1” or
“EB-PDS-INTERFACE-R8”, respectively. The system configuration file can be created
directly or with the profpga_builder tool.
Order Code
EB-PDS-INTERFACE-R1: Discontinued
EB-PDS-INTERFACE-R8: 288791
Extension Boards
Interface Board (EB-PDS-INTERFACE-R2)

This topic is about Interface Board (EB-PDS-INTERFACE-R2)

Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
LIN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
QSPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
I²S Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
I²C EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
SD Card Slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Lauterbach ARM JTAG/ETM Debugger Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . 748
TotalPhase Aardvark I²C/SPI Host Adapter Connector . . . . . . . . . . . . . . . . . . . . . . . . . 750
Spare I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Debug Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
The EB-PDS-INTERFACE-R2 Board has two proFPGA bottom and one proFPGA top
connector. It provides several interfaces and memories.
This proFPGA extension board supports the following features:

• Top Connector at site A1, all signals available
• CAN Controller (SPI Interface) and CAN Transceiver
Extension Boards
• LIN Transceiver
• QSPI Flash 500 Mb / 1 Gb
• I2S Audio CoDec (Analog Devices AD1938)
• Stereo Audio Input & Output via 3.5 mm Jack
• 2x I2C EEPROMs
• SD Card Slot, Full Size, UHS-I capable
• quad USB to UART converter
• Lauterbach ARM JTAG/ETM Debugger connection (2x10-pin Header and Mictor-38)
• TotalPhase Aardvark I2C/SPI Host Adapter connection (2x5-pin Header)
• Additional 2x10-pin JTAG Header ("Secondary JTAG")
Figure 6-180. EB-PDS-INTERFACE-R2
Extension Boards
Figure 6-181. EB-PDS-INTERFACE-R2 Connectivity

Table 6-289. EB-PDS-INTERFACE-R2 – Extension Board Operating

Conditions
IO voltage at BA1/TA1 Depends on stacked Extension Board
IO voltage at BA2 (min: recommended: 1.71V: 1.80V: 1.89V
max)
Top-side extension board connector Yes (TA1)
Known Issues
This topic is about Known Issues.
Extension Boards
Note
The signal LTB_ARM_PVIO_TCK connected to CLK_IO_N_2 is a single ended clock
signal which is connected to the ‘N’ pin of the FPGA. This leads into issues during
implementation process. To resolve this, an IBUF primitive has to be instantiated before the
BUFG instance of this clock.
Afterwards the clock has to be taken out of the clock network routing via adding the following
to the constraints:
set_property CLOCK_DEDICATED_ROUTE false [get_nets <LTB_ARM_PVIO_TCK

hierarchy>]
Note
The SD-Card interface which is advertised as UHS-I capable might not function correctly in
this mode. Running in UHS-I mode requires the hardware to switch the pull-up voltage of
the command and data lines from 3.3V to 1.8V. However, on this extension board also the VDD
of the SD-Card is changed to 1.8V which is not intended by the SPI specification.
Note
At the SD card socket (X4) pin 11 (DET_PROT) is floating. Because of that the Card Detect
and write protection detect signals are always pulled high regardless of the state of the
detection switches inside the SD card socket.
Do not rely on these signals when designing your interface controller.
This issue is fixed since revision C.
Note
The SD card interface is level translated by IC9, IC10 and IC11. These are unidirectional
components with direction control inputs available for IC10 (SD_CMD_DIR) and IC11
(SD_DAT_DIR). However, these signals must be driven by the user HDL design because there
are no pull-down resistors which would prevent floating.
This issue is fixed since revision C by adding pull-down resistors to aforementioned signals
which sets FPGA-to-SD-Card as the default direction.

In the table below, (1) CAN, LIN, SD-Card, (2) CAN, LIN, SD-Card, QSPI, USB2UART,
AADVARK Connector
Extension Boards
Table 6-290. EB-PDS-INTERFACE-R2– FPGA Extension Site Compatibility.

V1 V2
FM-XC7V2000T-R1 √ √ √
FM-XC7V2000T-R2 √ √ √
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3 √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √
FM-XCVU440-R2 √ √ √ √
FM-XCVU190-R1 √ √(1)
FM-XCVU160-R1 √ √(1)
FM-XCVU125-R1 √ √(1)
FM-XCVU095-R1 √ √(1)
FM-XCVU080-R1 √ √(1)
Extension Boards
Table 6-290. EB-PDS-INTERFACE-R2– FPGA Extension Site Compatibility.

V1 V2
FM-XCKU115-R1 √ √(1)
FM-XCVU5P-R1 √ √(1)
FM-XCVU13P-R1
FM-XCVU19P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √
FM-XCZU11EG-R2 √(2)
FM-1SG280<L,H>-R2 √ √ √
FM-10AX115-R1 √ √
FM-1SG10M-R1 √ √ √
√
Extension Boards
Table 6-291. EB-PDS-INTERFACE-R2 – FPGA Extension Site Compatibility,

FPGA Module TA0 TA1 TB0 TB1
FM-1SG10M-R1 √ √

Table 6-292. EB-PDS-INTERFACE-R2–FPGA Pin Constraints


This topic is about Functional Block Diagram.
Extension Boards
proFPGA Bottom Connector Signal Assignment
Figure 6-182. EB-PDS-INTERFACE-R2 Functional Block Diagram

This topic is about proFPGA Bottom Connector Signal Assignment.
Extension Boards
CAN Interface
Figure 6-183. EB-PDS-INTERFACE-R2 proFPGA Bottom Connector Signal

Assignment.jpg
CAN Interface
The CAN interface uses a CAN Controller IC to ease usage. This controller is accessed via SPI
and takes over the CAN related protocol generation in both directions. It implements the CAN
specification, version 2.0B.
Table 6-293.
Memory Type Manufacturer Order Code Interface
CAN Controller Microchip MCP2515-E/ML SPI
CAN Transceiver Microchip MCP2551-I/SN
Extension Boards
LIN Interface
Figure 6-184. CAN Bus Interface using Controller and Transceiver
LIN Interface
This topic is about LIN Interface.
Table 6-294. LIN Bus Transceiver Connection Scheme

LIN Transceiver Microchip MCP2003A-E/MD proprietary
Figure 6-185. LIN Bus Transceiver Connection Scheme
QSPI Flash
This topic discusses QSPI Flash of Interface Board (EB-PDS-INTERFACE-R2).
Extension Boards
I²S Audio Codec
Memory Type Manufacturer Order Code Memory Capacity

QSPI Flash Micron N25Q00AA11G124 1 Gbit
0
Figure 6-186. QSPI Flash Connection Scheme
I²S Audio Codec

This topic discusses I2S Audio Codec of Interface Board (EB-PDS-INTERFACE-R2).
This Extension Board features a Analog Devices AD1938 Audio Codec with I²S interface and
control SPI available on Bottom Connector XEBA2. Line Input and Output are available on one
standard 3.5 mm Audio Jacks each.
Audio Codec Analog Devices AD1938WBSTZ SPI & I²S
I²C EEPROMS
This topic discusses I2C EEPROMS of Interface Board (EB-PDS-INTERFACE-R2).
Memory Type Manufacturer Order Code Memory Capacity

I²C EEPROM Atmel AT24C32E-MAHM 32 kbit
Extension Boards
SD Card Slot
Figure 6-187. I²C EEPROMs Connection Scheme
SD Card Slot
This topic discusses SD card slot of Interface Board (EB-PDS-INTERFACE-R2).
The SD Card Interfaces features a full-size SD Card socket and is UHS-I capable. The signal
SD_UHS_EN (active high) must be driven high to switch the voltage of the sd card interface
from 3.3 V to 1.8 V. See Figure 6-189 and Figure 6-183 for details.
Since the SD card interface uses 3.3 V as a default, voltage level translators are used to adapt to
PV_IO. The circuit is shown in Figure 6-190. Note that the level translators used are
unidirectional and have direction control pins. With SD_CMD_DIR the direction of SD_CMD
can be changed. Driving this signal logic high results in transmission from FPGA to SD Card
while a logic low sets the transmission direction from SD Card to FPGA.
The signal SD_DAT_DIR controls SD_DAT[0:3]. Driving this signal logic high results in
transmission from FPGA to SD Card while a logic low sets the transmission direction from SD
Card to FPGA.
There is also an active low operation enable controlled by SD_DAT_nEN which forces the sd
card data group SD_DAT[0:3] into high impedance state.
Extension Boards
SD Card Slot
Figure 6-188. SD Card Socket Connection Scheme
Figure 6-189. Switchable Power Supply for SD Card UHS-I Mode
Extension Boards
Quad USB to UART Converter
Figure 6-190. SD Card Interface Level Translators

This topic discusses Quad USB to UART converter in Interface Board (EB-PDS-INTERFACE-
R2).
The FT4232HQ quadruple USB to UART converter is accessed from PC site via one Mini
USB-B receptacle. On the UART site there is TXD, RXD, RTS and CTS available for each of
the four UARTs. The FT4232HQ provides 4 separate Virtual COM Ports when connected to a
PC.
Lauterbach ARM JTAG/ETM Debugger Connectors

This topic discusses Lauterbach ARM JTAG/ETM Debugger Connectors in Interface Board
(EB-PDS-INTERFACE-R2).
Extension Boards
Figure 6-191. Lauterbach ARM JTAG / ETM Debugger Signal Assignment
Figure 6-192. Lauterbach ARM JTAG / ETM JTAG-only at Separate 2x10-Pin

Header
Extension Boards
TotalPhase Aardvark I²C/SPI Host Adapter Connector
TotalPhase Aardvark I²C/SPI Host Adapter

Connector
This topic discusses TotalPhase Aardvark I2C/SPI Host Adapter Connector in Interface Board
Figure 6-193. TotalPhase Aardvark I²C / SPI Host Adapter Connects to 5x2-pin
Standard Pin Header
Additional 2x10-pin JTAG Header

This topic discusses Additional 2x10-pin JTAG Header in Interface Board (EB-PDS-
INTERFACE-R2).
Extension Boards
Spare I/O Connector
Figure 6-194. Secondary Independent JTAG Header Connection Scheme
Spare I/O Connector

This topic discusses spare I/O connector in Interface Board (EB-PDS-INTERFACE-R2).
Unused I/Os on bottom connector XEBA2 are available for debugging and expansion purposes
on a 38-pin Mictor connector.
Extension Boards
Debug Header
Figure 6-195. EB-PDS-INTERFACE-R2 Spare I/Os on Mictor-38
Debug Header
This topic discusses debug header in Interface Board (EB-PDS-INTERFACE-R2).
Some interfaces are accessible for debugging purposes on a 38-pin Mictor connector. Available
interfaces are:
• Aardvark I²C
• Aardvark SPI
• All four UARTs from USB to UART converter
• Audio control SPI and I²S
Extension Boards
Related Work
Figure 6-196. EB-PDS-INTERFACE-R2 Debug Header Signal Assignment
Related Work
This topic discusses related work of Interface Board (EB-PDS-INTERFACE-R2).
profpga_run
For this board the following x-board entry is required within the system configuration file
<instance name>:
{
type = "BOARD";
size = "A1A2";
positions = ("<position>", "<position>");
v_io_ba1 = "AUTO";
v_io_ba2 = "AUTO";
};
Extension Boards
Order Code
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-INTERFACE-R2”.
Order Code
This topic discusses order code of Interface Board (EB-PDS-INTERFACE-R2).
This Extension Board has been discontinued. Please consider the latest version of this Interface
Board (EB-PDS-INTERFACE-R5) instead.
Extension Boards

The following subsections gives a detailed description of the EB-PDS-ADC250x16-R2 board.
Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
LIN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
QSPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
I²S Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
I²C EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
SD Card Slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
Debug Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

• LIN Transceiver
Extension Boards

• 2x I2C EEPROMs
Extension Boards

The following are the conditions under which the extension board operates.
Table 6-295. EB-PDS-INTERFACE-R3 – Extension Board Operating Conditions

IO voltage at BA2 1.71V…1.80V…1.89V
(min…recommended…max)
Known Issues
The following are the known issues in the board.
Extension Boards
Note
The signal LTB_ARM_PVIO_TCK connected to CLK_IO_N_2 is a single ended clock
signal which is connected to the ‘N’ pin of the FPGA. This leads to issues during HDL
implementation process. To resolve this, an IBUF primitive has to be instantiated before the
BUFG instance of this clock.
Afterwards the clock has to be taken out of the clock network routing by adding the following
constraint:
set_property CLOCK_DEDICATED_ROUTE false [get_nets
<LTB_ARM_PVIO_TCKhierarchy>]
This issue is fixed since revision D by changing the pin assignment of

LTB_ARM_PVIO_TCKto CLK_IO_P_1.
Note
At the SD card socket (X4) pin 11 (DET_PROT) is floating. Because of that the Card Detect
and write protection detect signals are always pulled high regardless of the state of the
detection switches inside the SD card socket.
Do not rely on these signals when designing your interface controller.

This issue is fixed since revision C.
Note
The SD card interface is level translated by IC9, IC10 and IC11. These are unidirectional
components with direction control inputs available for IC10 (SD_CMD_DIR) and IC11
(SD_DAT_DIR). However, these signals must be driven by the user HDL design because there
are no pull-down resistors which would prevent floating.
This issue is fixed since revision C by adding pull-down resistors to aforementioned signals
which sets FPGA-to-SD-Card as the default direction.

The following tables describe the extension site compatibility.
AADVARK Connector
Extension Boards
Table 6-296. EB-PDS-INTERFACE-R3– FPGA Extension Site Compatibility

Module V1 V1
FM- √ √ √
XC7V2000T
-R1
FM- √ √ √
XC7V2000T
-R2
FM-
XC7VX330
T-R3
FM-
XC7VX485
T-R3
FM- √
XC7V585T-
R3
FM- √ √
XC7VX690
T-R3
FM- √
XC7Z100-
R1
FM- √
XC7Z045-
R1
FM- √ √ √ √
XCVU440-
R1
FM- √ √ √ √
XCVU440-
R2
FM- √ √(1)
XCVU190-
R1
FM- √ √(1)
XCVU160-
R1
Extension Boards

Module V1 V1
FM- √ √(1)
XCVU125-
R1
FM- √ √(1)
XCVU095-
R1
FM- √ √(1)
XCVU080-
R1
FM- √ √(1)
XCKU115-
R1
FM- √ √(1)
XCVU5P-
R1
FM- √ √(1)
XCVU7P-
R1
FM- √ √(1)
XCVU9P-
R1
FM-
XCVU13P-
R1
FM- √ √ √ √
XCVU19P-
R1
FM- √ √
XCVU37P-
R1
FM- √ √
XCVU47P-
R1
FM- √ √ √
1SG280<L,
H>-R1
Extension Boards

Module V1 V1
FM- √(2) √
XCZU19EG
-R2
FM- √(2) √
XCZU17EG
-R2
FM- √(2)
XCZU11EG
-R2
FM- √ √ √
1SG280<L,
H>-R2
FM- √ √
10AX115-
R1
FM- √ √ √ √
1SG10M-R1
Table 6-297. EB-PDS-INTERFACE-R3 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √

The following are the pin constraints.
Table 6-298. EB-PDS-INTERFACE-R3–FPGA Pin Constraints


The following image shows the functional block diagram.
Extension Boards

The following image shows the bottom connector signal assignment.
Extension Boards
CAN Interface

Assignment
CAN Interface
Extension Boards
LIN Interface
Table 6-299. CAN Interface

Memory Type Memory Type Order Code Interface
LIN Interface
This topic describes the LIN interface of EB-PDS-INTERFACE-R3.
Table 6-300. EB-PDS-INTERFACE-R3 — LIN Transceiver

Extension Boards
QSPI Flash
QSPI Flash
This section describes the QSPI Flash.
Table 6-301. EB-PDS-INTERFACE-R3 — QSPI Flash

40
I²S Audio Codec

This Extension Board features a Analog Devices AD1938 Audio Codec with I²S interface and

Extension Boards
I²C EEPROMS
I²C EEPROMS
This section describes the I²C EEPROMS.
Table 6-303. I²C EEPROMS

I²C EEPROMS Atmel AT24C32E- 32 kbit
MAHM
SD Card Slot
This section describes the SD card interface.
from 3.3 V to 1.8 V. See Figure 6-206and Figure 6-200for details.
Since the SD card interface uses 3.3 V as a default, voltage level translators are used to adapt to
PV_IO. The circuit is shown in Figure 321. Note that the level translators used are
Extension Boards
SD Card Slot
unidirectional and have direction control pins. With SD_CMD_DIR the direction of SD_CMD
can be changed. Driving this signal logic high results in transmission from FPGA to SD Card
while a logic low sets the transmission direction from SD Card to FPGA.
Card to FPGA.
Extension Boards
SD Card Slot
Extension Boards

PC.
Extension Boards

This topic discusses Lauterbach ARM JTAG/ETM Debugger Connectors in Interface Board
Figure 6-208. Lauterbach ARM JTAG / ETM / ARM DSTREAM Debugger Signal
Assignment
Figure 6-209. Lauterbach ARM JTAG / ETM JTAG-Only at Separate 2x10-Pin

Header
Extension Boards

Connector
This topic discusses TotalPhase Aardvark I2C/SPI Host Adapter Connector in Interface Board
Standard Pin Header

This topic discusses Additional 2x10-pin JTAG Header in Interface Board (EB-PDS-
INTERFACE-R3).
This Extension Board provides a second independent JTAG connection on a standard 2x10-pin
2.54 mm pitch pin header.
Extension Boards
Spare I/O Connector
Spare I/O Connector

This topic discusses Spare I/O Connector in Interface Board (EB-PDS-INTERFACE-R3).
Unused I/Os on bottom connector XEBA2 are available for debugging and expansion purposes
Extension Boards
Debug Header
Debug Header
This topic discusses debug header in Interface Board (EB-PDS-INTERFACE-R3).
Some Interfaces are accessible for debugging purposes on a 38-pin Mictor connector. Available
interfaces are:
• Aardvark I²C
• Aardvark SPI
Extension Boards
Related Work
Related Work
This topic discusses related work of Interface Board (EB-PDS-INTERFACE-R3).
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A2";
v_io_ba1 = "AUTO";
v_io_ba2 = "AUTO";
};
more information.
Extension Boards
Order Code

plugged onto.
Order Code
This topic discusses order code of Interface Board (EB-PDS-INTERFACE-R3).
Extension Boards

This section discusses interface board EB-PDS-INTERFACE-R4.
Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
LIN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
QSPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
I²S Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
I²C EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
SD Card Slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Debug Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
The EB-PDS-INTERFACE-R4 board has two proFPGA bottom and one proFPGA top

• LIN Transceiver
Extension Boards

• 2x I2C EEPROMs
Extension Boards

This topic describes the extension board operating conditions.
Table 6-304. EB-PDS-INTERFACE-R4 — Extension Board Operating Conditions

IO voltage at BA2 (min…recommended…max) 1.71V…1.80V…1.89V
Known Issues
There are no issues known to the time this documentation was last updated.
Extension Boards

The following table describes the FPGA extension site compatibility.
AADVARK Connector
Table 6-305. EB-PDS-INTERFACE-R4 — FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √
FM-XC7V2000T-R2 √ √ √
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3 √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √
FM-XCVU440-R2 √ √ √ √
FM-XCVU190-R1 √ √(1)
FM-XCVU160-R1 √ √(1)
FM-XCVU125-R1 √ √(1)
FM-XCVU095-R1 √ √(1)
FM-XCVU080-R1 √ √(1)
FM-XCKU115-R1 √ √(1)
FM-XCVU13P-R1
FM-XCVU19P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √
Extension Boards

V1 V1
FM-1SG280<L,H>-R2 √ √ √
FM-10AX115-R1 √ √
FM-1SG10M-R1 √ √ √ √
Table 6-306. EB-PDS-INTERFACE-R4 — FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √

The following table describes the FPGA pin constraints.
Table 6-307. EB-PDS-INTERFACE-R4 — FPGA Pin Constraints


The following figure shows the functional block diagram of EB-PDS-INTERFACE-R4.
Extension Boards

The following figure shows the proFPGA bottom connector signal assignment of EB-PDS-
INTERFACE-R4.
Extension Boards
Figure 6-217. proFPGA Bottom Connector Signal Assignment
Extension Boards
CAN Interface
CAN Interface

LIN Interface
This section describes the LIN interface of EB-PDS-INTERFACE-R4.

Extension Boards
QSPI Flash
QSPI Flash
This section describes the QSPI Flash interface of EB-PDS-INTERFACE-R4.

40
Extension Boards
I²S Audio Codec
I²S Audio Codec

This Extension Board features an Analog Devices AD1938 Audio Codec with I²S interface and
Since this Revision (EB-PDS-INTERFACE-R4) the voltage level translators between FPGA
and the Audio Codec IC are unidirectional instead of bidirectional. However, the direction of
the clock signals AUDIO_DBCLK, AUDIO_DLRCLK, AUDIO_ABCLK and
AUDIO_ALRCLK can be either from FPGA to Audio Codec or vice versa – depending on the
mode the Audio Codec IC is configured to. To account for this fact two additional control
signals AUDIO_DAC_CLK_DIR and AUDIO_ADC_CLK_DIR where added.
See Figure 6-221 for details.

Figure 6-221. Audio Codec DAC Clock and ADC Clock Level Translator
Extension Boards
I²C EEPROMS
I²C EEPROMS
This topic describes the I²C EEPROMS for ED-PDS-INTERFACE-R4.

SD Card Slot
from 3.3 V to 1.8 V.
See Figure 6-224 and Figure 6-217 for details. Since the SD card interface uses 3.3 V as a
default, voltage level translators are used to adapt to PV_IO. The circuit is shown in
Figure 6-225. Note that the level translators used are unidirectional and have direction control
Extension Boards
SD Card Slot
pins. With SD_CMD_DIR the direction of SD_CMD can be changed. Driving this signal logic
high results in transmission from FPGA to SD Card while a logic low sets the transmission
direction from SD Card to FPGA.
Card to FPGA.
Caution
Due to the fact that there is a combined direction control signal (SD_DAT_DIR) for
SD_DAT[0:3] the SD Bus mode is not supported by this extension board. However, there
are no known issues with the SPI Bus mode.
Please contact Sales if you’re application requires the SD Bus mode.
Extension Boards
SD Card Slot
Extension Boards

PC.
Extension Boards

This section shows the Lauterbach ARM JTAG/ETM debugger connectors of EB-PDS-
INTERFACE-R4.
Assignment
Figure 6-227. Lauterbach ARM JTAG / ETM JTAG-Only at Separate 2x10-Pin

Header
Extension Boards

Connector
This topic shows the TotalPhase Aardvark I²C / SPI host adapter connector.
Standard Pin Header

This extension board provides a second independent JTAG connection on a standard 2x10-pin
Extension Boards
Spare I/O Connector
Spare I/O Connector

Unused I/O on Bottom Connector XEBA2 are available for debugging and expansion purposes
Extension Boards
Debug Header
Debug Header
Some Interfaces are accessible for debugging purposes on a 38-pin Mictor Connector.
Available interfaces are:
• Aardvark I²C
• Aardvark SPI
Extension Boards
Related Work
Related Work
This section describes the related work for EB-PDS-INTERFACE-R4.
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A2";
v_io_ba1 = "AUTO";
v_io_ba2 = "AUTO";
};
more information.
Extension Boards
Order Code

plugged onto.
Please refer to the proFPGA Software Reference Manual [UD002] and the proFPGA Builder
Order Code
Extension Boards

Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
LIN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
I²S Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
I²C EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
SD Card Slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
Debug Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

• LIN Transceiver
Extension Boards

• 2x I2C EEPROMs
• TotalPhase Aardvark I2C/SPI Host Adapter connection (2x5-pin Header)Additional
2x10-pin JTAG Header ("Secondary JTAG")
Extension Boards

This topic describes the extension board operating conditions for EB-PDS-INTERFACE-R5.

Known Issues
There are no issues known to the time this documentation was updated.

This topic describes the FPGA extension site compatibility of EB-PDS-INTERFACE-R5.
Extension Boards
AADVARK Connector
V1 V1
FM-XC7V2000T-R1 √ √ √
FM-XC7V2000T-R2 √ √ √
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3 √
FM-XC7Z100-R1 √
FM-XC7Z045-R1 √
FM-XCVU440-R1 √ √ √ √
FM-XCVU440-R2 √ √ √ √
FM-XCVU190-R1 √ √(1)
FM-XCVU160-R1 √ √(1)
FM-XCVU125-R1 √ √(1)
FM-XCVU095-R1 √ √(1)
FM-XCVU080-R1 √ √(1)
FM-XCKU115-R1 √ √(1)
FM-XCVU13P-R1
FM-XCVU19P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √
Extension Boards

V1 V1
FM-1SG280<L,H>-R2 √ √ √
FM-10AX115-R1 √ √
FM-1SG10M-R1 √ √ √ √

FM-1SG10M-R1 √ √

This topic describes the FPGA pin constraints for EB-PDS-INTERFACE-R5.


This topic describes the EB-PDS-INTERFACE-R5 functional block diagram.
Extension Boards

This topic describes the proFPGA bottom connector signal assignment of EB-PDS-
INTERFACE-R5.
Extension Boards
CAN Interface

Assignment
CAN Interface
specification, version 2.0B
Extension Boards
LIN Interface
Table 6-312. EB-PDS-INTERFACE-R5 — CAN Controllers

CAN Transceiver Microchip MCP2551-I/SN -
LIN Interface
This topic describes the LIN interface of EB-PDS-INTERFACE-R5.

Extension Boards
I²S Audio Codec
I²S Audio Codec

This Extension Board features an Analog Devices AD1938 Audio Codec with I²S interface and
Since Revision EB-PDS-INTERFACE-R4 the voltage level translators between FPGA and the
Audio Codec IC are unidirectional instead of bidirectional. However, the direction of the clock
signals AUDIO_DBCLK, AUDIO_DLRCLK, AUDIO_ABCLK and AUDIO_ALRCLK can
be either from FPGA to Audio Codec or vice versa – depending on the mode the Audio Codec
IC is configured to. To account for this fact two additional control signals
AUDIO_DAC_CLK_DIR and AUDIO_ADC_CLK_DIR where added.
See Figure 6-238 for details.

Table 6-314. EB-PDS-INTERFACE-R5 – Audio Codec
Figure 6-238. Audio Codec DAC Clock and ADC Clock Level Translator
I²C EEPROMS
This topic describes the I²C EEPROMS of EB-PDS-INTERFACE-R5.
Extension Boards
SD Card Slot
Table 6-315. EB-PDS-INTERFACE-R5 — EEPROM

SD Card Slot
from 3.3 V to 1.8 V.
See Figure 6-241 and Figure 6-235 for details. Since the SD card interface uses 3.3 V as a
default, voltage level translators are used to adapt to PV_IO. The circuit is shown in
Figure 6-242. Note that the level translators used are unidirectional and have direction control
pins. With SD_CMD_DIR the direction of SD_CMD can be changed. Driving this signal logic
high results in transmission from FPGA to SD Card while a logic low sets the transmission
direction from SD Card to FPGA.
Card to FPGA.
Extension Boards
SD Card Slot
Caution
Due to the fact that there is a combined direction control signal (SD_DAT_DIR) for
SD_DAT[0:3] the SPI Bus mode is not supported by this extension board. However, there
are no known issues with the SD Bus mode.
Please contact Sales if you’re application requires the SPI Bus mode.
Extension Boards
SD Card Slot
Extension Boards

PC.
Extension Boards

This topic shows the Lauterbach ARM JTAG / ETM / ARM DSTREAM debugger signal
assignment of EB-PDS-INTERFACE-R5.
Assignment
Figure 6-244. Lauterbach ARM JTAG / ETM JTAG-only at Separate 2x10-Pin

Header
Extension Boards

Connector
This topic describes the TotalPhase Aardvark I2C/SPI host adapter connector of EB-PDS-
INTERFACE-R5.
Standard Pin Header

This Extension Board provides a second independent JTAG connection on a standard 2x10-pin
Extension Boards
Spare I/O Connector
Spare I/O Connector

Unused I/O on Bottom Connector XEBA2 are available for debugging and expansion purposes
Debug Header
Some Interfaces are accessible for debugging purposes on a 38-pin Mictor Connector.
Available interfaces are:
• Aardvark I²C
• Aardvark SPI
Extension Boards
Related Work
Related Work
This topic describes the EB-PDS-INTERFACE-R5 related work.
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A2";
v_io_ba1 = "AUTO";
v_io_ba2 = "AUTO";
};
more information.
Extension Boards
Order Code

plugged onto.
Order Code
Use the order code 286504 for EB-PDS-INTERFACE-R5.
Extension Boards

Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Parallel NOR FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
Serial NAND FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
EJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
SPI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
IrDA UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
MICTOR Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
The EB-PDS-INTERFACE-R7 Board has one proFPGA bottom and one proFPGA top

available for further use (e.g., to connect a cable for interconnections to other FPGAs).
• 256 MB parallel NOR FLASH Memory
• 256 MB serial NAND FLASH Memory
• EJTAG interface (as slave)
• 3.3 V SPI bus (as Master)
• IrDA UART interface with configurable BAUD-rate (up to 115200 BAUD)
• Single GPIO for debugging
Extension Boards
Extension Boards

This topic describes the extension board operating conditions for PDS-INTERFACE-R7.

Known Issues
There are no issues known to the time this documentation was updated.
Extension Boards

This topic describes the FPGA extension site compatibility of EB-PDS-INTERFACE-R7.
In the table below, (1) Only NOR Parallel Memory available on this Connector
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √
FM-XCVU160-R1 √ √ √ √
FM-XCVU125-R1 √ √ √ √
FM-XCVU095-R1 √ √ √ √
FM-XCVU080-R1 √ √ √ √
FM-XCKU115-R1 √ √ √ √
FM-XCVU13P-R1
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-XCZU19EG-R2 √ √ √ √(1) √
Extension Boards

V1 V1
FM-XCZU17EG-R2 √ √ √ √(1) √
FM-XCZU11EG-R2 √ √ √ √(1)
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

This topic describes the FPGA pin constrains of EB-PDS-INTERFACE-R7.


This topic shows the functional block diagram of EB-PDS-INTERFACE-R7.
Extension Boards

This topic shows the proFPGA bottom connector signal assignment of EB-PDS-INTERFACE-
R7.
Extension Boards
Parallel NOR FLASH Memory

Assignment
Parallel NOR FLASH Memory

A NOR memory is assembled on the board and can be accessed via parallel interface. The
memory is directly connected to the FPGA.
Extension Boards
Serial NAND FLASH Memory
Table 6-320. EB-PDS-INTERFACE-R7 — NOR FLASH Memory Type

2GBIT - NOR CYPRESS S70GL02GT Parallel
FLASH
Serial NAND FLASH Memory

A NAND memory is assembled on the board and can be accessed via serial interface. The
memory is directly connected to the FPGA.
Table 6-321. EB-PDS-INTERFACE-R7 — NAND FLASH Memory Type

2GBIT - NAND winbond W25M02GWTCIG SPI/DualSPI/
FLASH QuadSPI
EJTAG
The EJTAG interface is designed as slave input to the FPGA. Level shifters allow an external
voltage level up to 5V.
The board allow a modification of the direction of the level shifters for transform the slave
interface to a master interface via resistor changing.
In the figure below, DNP is not mounted.
Extension Boards
EJTAG
Figure 6-253. EJTAG Interface Implementation
Transforming EJTAG Slave to Master

The transformation from slave to master is possible via resistor changing. Following table
shows the resistor setup:
Table 6-322. EJTAG Resistor Configuration for Slave or Master Mode
Resistor Designator Setup Setup Resistor Setup Setup
for for slave Designa for for slave
master mode tor master mode
mode mode
RJTAG1 0Ω not RJTAG1 1k Ω not
mounted 3 mounted
mounted 4 mounted
mounted 5 mounted
RJTAG4 not 0Ω RJTAG1 1k Ω not
mounted 6 mounted
mounted 7 mounted
Extension Boards
EJTAG
Table 6-322. EJTAG Resistor Configuration for Slave or Master Mode (cont.)
Resistor Designator Setup Setup Resistor Setup Setup
for for slave Designa for for slave
master mode tor master mode
mode mode
RJTAG6 not 0Ω RJTAG1 0 Ω 33.2 Ω
mounted 8
RJTAG7 not 0Ω RJTAG1 33.2 Ω 0Ω
mounted 9
RJTAG8 0Ω 0Ω RJTAG2 33.2 Ω 0Ω
0
RJTAG9 not 0Ω RJTAG2 33.2 Ω 0Ω
mounted 1
RJTAG10 0Ω not RJTAG2 33.2 Ω 0Ω
mounted 2
RJTAG11 1k Ω not RJTAG2 33.2 Ω 0Ω
mounted 3
RJTAG12 1k Ω not RJTAG2 33.2 Ω 0Ω
mounted 4
In the figure below, RJTAG Resistors are placed in the box with red frame.
Extension Boards
SPI Interface
Figure 6-254. Bottom Side of EB-PDS-INTERFACE-R7
Caution
Siemens assumes no responsibility / liability for damages on the board as a result of the
resistor change. The changes should only be done by professionals. The resistors are from
type 0402.
SPI Interface
The board provides a SPI Master bus with a voltage level of 3.3V.
In the figure below, the left represents a schematic diagram and the right depicts a header with
appropriate silkscreen.
Extension Boards
IrDA UART Interface
Figure 6-255. SPI Bus
IrDA UART Interface

An IrDA UART interface is provided by the EB-PDS-INTERFACE-R7. The UART signal is
level shifted from FPGA pins to 3.3V for an UART infrared de- and encoder. The de- and
encoder can be configured by UART signals via software mode or directly via DIP1 DIP-
switch.
Figure 6-256. UART Interface with DIP1 with Position Code
DIP 1 controls the de- and encoder IC. The supported modes can be find in the datasheet of the
de- and encoder IC or directly as silkscreen print on the board. The ON mark on the DIP switch
represents a "0".
Extension Boards
GPIO
Table 6-323. Parts of the UART Interface

Part Manufacturer Order Code Interface
Infrared De- and Microchip MCP2120 UART
Encoder
Infrared Transceiver VISHAY TFDU4101 directly
Module
GPIO
A single GPIO is directly connected to the FPGA. It can be used for debugging. The voltage
level is 1.8V.
MICTOR Connectors
All signals are routed to the both MICTOR connectors on the EB-PDS-INTERFACE-R7 board.
The voltage level is 1.8V.
Extension Boards
Related Work
Figure 6-257. MICTOR Pinout
Related Work
This topic describes the EB-PDS-INTERFACE-R7 related work.
Extension Boards
Order Code
profpga_run
<instance name>:
{
type = "BOARD";
size = "A1A1";
v_io_ba1 = "1V8";
};
<instance name> must be replaced with the correct value according to the system
configuration. Please refer to the proFPGA Software Reference Manual [UD002] for more
information.

INTERFACE-R7”. The system configuration file can be created manually or with the
profpga_builder tool.Please refer to the proFPGA Software Reference Manual [UD002] and the
proFPGA Builder User Manual [UD004] for more information.
Order Code
Use the order code 286505 for EB-PDS-INTERFACE-R7.
Extension Boards
Protocol Tester Board (EB-PDS-RnS-TESTER-R1)
Protocol Tester Board (EB-PDS-RnS-TESTER-

R1)
This topic is about Protocol Tester Board (EB-PDS-RnS-TESTER-R1).

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
ProFPGA protocol tester board provides two Interfaces for connecting protocol tester. One
interface is dedicated for R&S protocol tester.
• One R&S variable protocol tester interface (49 signal pins) with one auxiliary coaxial
port and one reference input coaxial port.
• A variable psu for the R&S protocol tester interface to adjust multiply cmos input and
ouput voltage levels (CMOS12, CMOS15, CMOS18, CMOS25 and CMOS33).
• One protocol tester interface with two DX20 Hirose Electric Co. connector and support
for cmos33 voltage level. Each connector has 32 directed signal pins. Additional four
mmcx coaxial connectors (Clk and Sync) with two ports for each direction.
• Both interfaces can also be used than an ordinary I/O interface with 100mbit/s.
Extension Boards
Figure 6-258. proFPGA RnS-TESTER-R1 Board

Table 6-324. EB-PDS-RnS-TESTER-R1 – Operating Conditions


In the table below:
(a) - Only RnS-Interface can be used
Extension Boards
Table 6-325. EB-PDS-RnS-TESTER-R1 – FPGA Extension Site Compatibility

V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √(a) √ √(a) √ √(a)
FM-XC7VX485T-R3 √ √(a) √ √(a) √ √(a)
FM-XC7V585T-R3 √ √(a) √ √ √ √(a)
FM-XC7VX690T-R3 √ √(a) √ √ √ √(a)
FM-XC7Z100-R1 √(a) √
FM-XC7Z045-R1 √(a) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √(a)
FM-XCVU160-R1 √ √ √ √(a)
FM-XCVU125-R1 √ √ √ √(a)
FM-XCVU080-R1 √ √ √ √(a)
FM-XCVU095-R1 √ √ √ √(a)
FM-XCKU115-R1 √ √ √ √(a)
FM-XCVU5P-R1 √ √ √ √(a)
FM-XCVU7P-R1 √ √ √ √(a)
FM-XCVU9P-R1 √ √ √ √(a)
FM-XCVU13P-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
Extension Boards
Table 6-325. EB-PDS-RnS-TESTER-R1 – FPGA Extension Site Compatibility

V1 V1
FM-XCZU11EG-R2 √ √ √(a)
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-326. EB-PDS-RnS-TESTER-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Table 6-327. EB-PDS-RnS-TESTER-R1 –FPGA Pin Constraints

LVCMOS18
Related Work
profpga_run
Using the protocol tester board requires a configuration via the plugin. To load the plugin the
...
plugin_list = ("rnstester ProDesign EB-PDS-RnS-TESTER-R1");
{
Extension Boards
Related Work
...
plugin_list = ("si5338 ProDesign EB-PDS-DVI-R1",
"rnstester ProDesign EB-PDS-RnS-TESTER-R1" );
{
...
This will load the rnstester-plugin, which is part of the 2016A- and subsequent-releases. The
plugin configures the direction and voltage level of the R & S protocol interface before FPGA
configuration.
Caution
Also, if no R&S interface is in usage, it is recommended that the plugin is used to configure
the R&S interface.
Extension Boards
Related Work
<instance name>:
{
type = "BOARD";
name = "EB-PDS-RnS-TESTER-R1";
size = "A1A1";
v_io_ba1 = "P1V8"; # for connector BA1
# Set voltage level standard
# Example: cmos18
# posible values:
# +---------------+---------------+
# | cmos_standard | voltage level |
# +---------------+---------------+
# | cmos12 | 1.2 V |
# | cmos15 | 1.5 V |
# | cmos18 | 1.8 V |
# | cmos25 | 2.5 V |
# | cmos33 | 3.3 V |
# +---------------+---------------+
RnS_voltage = "cmos18";
# Set value of direction
# Example: 1
# posible values:
# +---------------+---------------+
# | value | direction |
# +---------------+---------------+
# | 1 | OUT |
# | 0 | IN |
# +---------------+---------------+
rns_phy1:
{
RNS = 1;# R&S interface enable = 1, disable = 0
UI_I = 1;# Direction of Group UI_I
AUX_IO_0_1 = 1;# Direction of Group AUX_IO 0 and 1
GP0 = 1;# Direction of Pin GP0
Valid = 1;# Direction of Validationsignal
UI_Q = 0;# Direction of Group UI_Q
}
rns_phy2:
{
AUX_IO_2_3 = 0;# Direction of Group AUX_IO 2 and 3
RnS_AUX = 1;# Direction of auxilary signal
}
};
Extension Boards
Order Code
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-RnS-TESTER-R1”.
Startup with the protocol tester Board

The board enables the I/O pin directions and voltage levels of both interfaces after PV_IO is
applied. The board is immediately ready to use after plugin configuration. An error during
configuration stops startup routine of FPGA system.
Order Code
286506
Extension Boards
SATA Extension Board (EB-PDS-SATA-R2/R3)
SATA Extension Board (EB-PDS-SATA-R2/R3)

This topic is about SATA Extension Board (EB-PDS-SATA-R2/R3)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Erratum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
This extension board may be used to connect to SATA devices, SATA hosts as well as
additional extension boards of this type (FPGA interconnect). Since the high-speed serial
transceivers (MGTs) as well as the serial ATA interface have dedicated lanes for transmission
(TX) and reception (RX) there are two types of connectors (marked as "HOST" and "DEVICE"
in Figure 1). There is no mechanical difference in these two types. They differ electrically in the
arrangement of TX and RX pairs respectively.
• Use case 1: Attachments of SATA device(s). Because proFPGA acts as host use a
"HOST" connector
• Use case 2: Attachments to SATA host(s). Because proFPGA acts as device use a
"DEVICE" connector
• Use case 3: FPGA interconnect. Use a host and/or device connector. Make sure each
cable connects a host connector on one EB-PDS-SATA-R1 with a device connector on
another EB-PDS-SATA-R1 or vice versa. Do not interconnect two identically named
connectors to avoid shorting two TX drivers.
All three use cases can be combined.
• Up to 12.5 Gbps
• 8 SATA connectors (4x HOST, 4x DEVICE)
• Supports SATA Host and Device connections
• Supports FPGA interconnect
Extension Boards
• Pericom PI3EQX1204 SATA redrivers to enable flexible high speed connection using
SATA cables up to at least 1 m
• 4 outputs programmable reference clock generator
• 2 MMCX connector pairs for clock output
• 4 MMCX connector pairs for clock input
• 4 on-board multiplexers to select between local and remote clock
Figure 6-259. EB-PDS-SATA-R2 Top Side
Figure 6-260. EB-PDS-SATA-R2/R3 Clock Distribution Block Diagram
The clock distribution circuit is shown schematically in Figure 6-260. The MGT reference
clocks can be generated on-board with a Si5338A clock generation device or alternatively
Extension Boards
provided externally using the MMCX clock inputs. Reference clocks number 1 and 3 can also
be made available on MMCX output connector pairs.The following table lists the relationship
between SATA connectors and MGT signals:
Table 6-328. EB-PDS-SATA-R2/R3 Relationships of TX/RX Pairs
SATA Connector Type Direction MGT Diff Pair
X1 HOST TX MGT_TX_00
X1 HOST RX MGT_RX_00
X2 DEVICE TX MGT_TX_01
X2 DEVICE RX MGT_RX_01

Table 6-329. EB-PDS-SATA-R2/R3 Operating Conditions

IO voltage (min…recommended…max) Only MGTs are used

Extension Boards
In the table below:
(a) - X7 and X8 cannot be used

Table 6-330. EB-PDS-SATA-R2/R3 Extension site Compatibility.
V1 V1
FM-XC7V2000T-R1 √ √
FM-XC7V2000T-R2 √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU080-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √ √ √
FM-XCKU115-R1 √ √ √ √ √ √
FM-XCVU5P-R1 √ √ √ √ √ √
FM-XCVU7P-R1 √ √ √ √ √ √
FM-XCVU9P-R1 √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √ √ √ √
FM-XCVU47P-R1 √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √(a) √(a)
Extension Boards
Related Work
Table 6-330. EB-PDS-SATA-R2/R3 Extension site Compatibility. (cont.)

V1 V1
FM-1SG280<L,H>-R2 √ √(a) √(a)
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-331. EB-PDS-SATA-R2/R3 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
Related Work
Generating register map files for Si5338 Please refer to Related Work for details how to
generate register map files for the Si5338.
Note
profpga_run
The EB-PDS-SATA-R2/R3 uses three plugins to configure clock distribution, clock generation
as well as SATA redrivers. To load the plugins the plugin_list entry before the
system_configuration section must be added (example given for revision 2 but also valid for
R3):
plugin_list = ( "sata_eb_clkdist_r2 ProDesign EB-

PDS-SATA-R2",
"si5338 ProDesign EB-PDS-SATA-R2",
"pi3eqx1204 ProDesign EB-PDS-SATA-R2");
...
{
...
Extension Boards
Related Work
The following x-board entry is required within the system configuration file:
<instance name>:
{
type = "BOARD";
name = "EB-PDS-SATA-R2";
size = "A1A1";
v_io_ba1 = "AUTO";
...
};
Extension Boards
Related Work
more information.Settings used for the plugins have to be contained in the x-board entry for EB-
PDS-SATA-R2/R3:
<instance name>:
{
...
# Si5338(A) Plugin Settings
# Clock Distribution Settings
gpio_expander1:
{
IIC_CLK0_SEL = 0; # MGT_REFCLK0 clock source = CLKGEN_0
IIC_CLK2_SEL = 1; # MGT_REFCLK2 clock source = IN2
IIC_CLK1_PREA = 0; # PRE-AMP for buffer A disabled
IIC_CLK1_PREB = 0; # PRE-AMP for buffer B disabled
IIC_CLK1_PREL = 0; # PRE-AMP for buffer L (CLK1 MUX) disabled
IIC_CLK1_ENA = 1; # output to MMCX OUT0 enabled
IIC_CLK1_ENB = 1; # output to CLK1 MUX enabled
IIC_CLK1_ENL = 1; # output to MGT_REFCLK1 enabled
IIC_CLK3_ENA = 0; # output to MMCX OUT1 disabled
}
gpio_expander2:
{
SATA_NRESET = 0; # '0' = SATA active (must be '0'!)
NO_CONNECT_01 = 0; # set all NO_CONNECT bits to '0'
NO_CONNECT_02 = 0;
NO_CONNECT_03 = 0;
NO_CONNECT_04 = 0;
NO_CONNECT_05 = 0;
NO_CONNECT_06 = 0;
NO_CONNECT_07 = 0;
NO_CONNECT_08 = 0;
NO_CONNECT_09 = 0;
NO_CONNECT_10 = 0;
NO_CONNECT_11 = 0;
NO_CONNECT_12 = 0;
NO_CONNECT_13 = 0;
NO_CONNECT_14 = 0;
NO_CONNECT_15 = 0;
}
# SATA Redriver (PI3EQX1204) Settings per Connector
X1:
{
TX_BST = 0;
TX_DE = 0;
TX_PS = 0;
TX_VOD = 0;
Extension Boards
Order Code
TX_VTH = 0;
TX_ENABLE = 1;
TX_NODETECT = 1;
RX_BST = 0;
RX_DE = 0;
RX_PS = 0;
RX_VOD = 0;
RX_VTH = 0;
RX_ENABLE = 1;
RX_NODETECT = 1;
}
# see PI3EQX1204 datasheet for detailed description of these settings
# there must be a section for each connector (X1 .. X8)
# only one section is shown here for simplicity
};

information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-SATA-R2”. The
Order Code
The board is obsolete and not available anymore. Refer to “SATA Extension Board (EB-PDS-
SATA-R4)” on page 847 for replacement.
Benchmark
This topic is about Benchmark.
Extension Boards
Benchmark
The EB-PDS-SATA-R2/R3 extension board has been tested with the following equipment:
• proFPGA FM-XC7V2000T-R2 (speed grade 1) and FM-XC7VX330T-R3 (speed grade

2)
• 3M SATA cables with 0.5 m and 1.0 m length
Tests were performed with IBERT (Integrated Bit Error Rate Test) generated with Xilinx
Vivado 2014.2 for FPGA module connector TB2. Connection speed was 8.0 Gbps for FM-
XC7V2000T-R2 and 10 Gbps for FM-XC7VX330T-R3.
MGTs were connected according to the following scheme.

Table 6-332. EB-PDS-SATA-R2/R3 MGT Connections for Performance Tests
FM- FM-XC7VX330T-R3
XC7V2000T-
R2
X1 <-> X8 X1 <-> X2
X2 <-> X7 X3 <-> X4
X3 <-> X6 X5 <-> X6
X4 <-> X5 X7 <-> X8
Vivado settings for all tests:

Table 6-333. EB-PDS-SATA-R2/R3 Vivado Settings Performance Tests
Parameter Setting
TX Pattern PRBS-31 bit
TX Diff Swing 866 mV
DFE Enabled Yes
Termination Voltage 800 mV
RX Common Mode Floating
SATA Redriver settings for up to 8 Gbps:

Table 6-334. EB-PDS-SATA-R2/R3 Redriver Settings for 8 Gbps
Parameter X1 X2 X3 X4 X5 X6 X7 X8
TX_BST 0 0 0 0 0 0 0 0
TX_DE 0 0 0 0 0 0 0 0
TX_PS 0 0 0 0 0 0 0 0
TX_VOD 0 0 0 0 0 0 0 0
TX_VTH 0 0 0 0 0 0 0 0
Extension Boards
Benchmark
Table 6-334. EB-PDS-SATA-R2/R3 Redriver Settings for 8 Gbps (cont.)

TX_ENABLE 1 1 1 1 1 1 1 1
TX_NODETECT 1 1 1 1 1 1 1 1
RX_BST 0 0 0 0 0 0 0 0
RX_DE 0 0 0 0 0 0 0 0
RX_PS 0 0 0 0 0 0 0 0
RX_VOD 0 0 0 0 0 0 0 0
RX_VTH 0 0 0 0 0 0 0 0
RX_ENABLE 1 1 1 1 1 1 1 1
RX_NODETECT 1 1 1 1 1 1 1 1
SATA Redriver settings for 10 Gbps:
Table 6-335. EB-PDS-SATA-R2/R3 Redriver Settings for 10 Gbps
TX_BST 3 3 3 3 3 3 3 3
TX_DE 0 0 0 0 0 0 0 0
TX_PS 2 2 2 2 2 2 2 2
TX_VOD 0 0 0 0 0 0 0 0
TX_VTH 0 0 0 0 0 0 0 0
TX_ENABLE 1 1 1 1 1 1 1 1
TX_NODETECT 1 1 1 1 1 1 1 1
RX_BST 3 3 3 3 3 3 3 3
RX_DE 0 0 0 0 0 0 0 0
RX_PS 2 2 2 2 2 2 2 2
RX_VOD 0 0 0 0 0 0 0 0
RX_VTH 0 0 0 0 0 0 0 0
RX_ENABLE 1 1 1 1 1 1 1 1
RX_NODETECT 1 1 1 1 1 1 1 1
Extension Boards
Erratum
Figure 6-261. Eye Diagram and IBERT Results for 10 Gbps with FM-XC7VX330T-
R3
The above figure shows an eye diagram of one channel running at 10 Gbps through 1 m SATA
cable without errors. This test was performed on quad 113 of FM-XC7VX330T-R3.
Erratum
This topic is about Erratum
There is a pin assignment error on the SATA connectors (X1-X8) regarding pins (S)5 and (S)6.
For the HOST connectors (X1, X3, X5, X7) this is the RX differential pair and for the DEVICE
connectors (X2, X4, X6, X8) this is the TX differential pair.
Workaround:
If a SATA device is connected to a SATA EB HOST port the data on the RX pair has to be
negated.
In case a SATA host connects to a SATA EB DEVICE port the TX pair data has to be negated.
If this workaround is not sufficient in solving issues provoked by this Erratum please contact
proFPGA Support.
Note
Please note that this issue has been fixed in Revision 3 (EB-PDS-SATA-R3) of the SATA
Extension board.
Extension Boards
SATA Extension Board (EB-PDS-SATA-R4)
SATA Extension Board (EB-PDS-SATA-R4)

This topic is about SATA Extension Board (EB-PDS-SATA-R4)

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
This extension board may be used to connect to SATA devices, SATA hosts as well as
additional extension boards of this type (FPGA interconnect). Since the high-speed serial
transceivers (MGTs) as well as the serial ATA interface have dedicated lanes for transmission
(TX) and reception (RX) there are two types of connectors (marked as "HOST" and "DEVICE"
in Figure 1). There is no mechanical difference in these two types. They differ electrically in the
arrangement of TX and RX pairs respectively.
• Use case 1: Attachments of SATA device(s). Because proFPGA acts as host use a
"HOST" connector
• Use case 2: Attachments to SATA host(s). Because proFPGA acts as device use a
"DEVICE" connector
• Use case 3: FPGA interconnect. Use a host and/or device connector. Make sure each
cable connects a host connector on one EB-PDS-SATA-R4 with a device connector on
another EB-PDS-SATA-R4 or vice versa. Do not interconnect two identically named
connectors to avoid shorting two TX drivers.
All three use cases can be combined.
• up to 12.5 Gbps
• 8 SATA connectors (4x HOST, 4x DEVICE)
• Supports SATA Host and Device connections
• Supports FPGA interconnect
• TI DS125BR820 SATA redrivers to enable flexible high speed connection using SATA
cables up to at least 1 m
Extension Boards
• 4 outputs programmable reference clock generator

• 2 MMCX connector pairs for clock output
• 4 MMCX connector pairs for clock input
• 4 on-board multiplexers to select between local and remote clock
Figure 6-262. EB-PDS-SATA-R4 Top Side
Figure 6-263. EB-PDS-SATA-R4 Clock Distribution Block Diagram
The clock distribution circuit is shown schematically in the above figure. The MGT reference
clocks can be generated on-board with a Si5338A clock generation device or alternatively
Extension Boards
provided externally using the MMCX clock inputs. Reference clocks number 1 and 3 can also
be made available on MMCX output connector pairs.The following table lists the relationship
between SATA connectors and MGT signals:
Table 6-336. EB-PDS-SATA-R4 Relationships of TX/RX Pairs
SATA Connector Type Direction MGT Diff Pair

Table 6-337. EB-PDS-SATA-R4 Operating Conditions

IO voltage (min…recommended…max) Only MGTs are used

Extension Boards
In the table below:
(a) - X7 and X8 cannot be used

Table 6-338. EB-PDS-SATA-R4 Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √
FM-XC7V2000T-R2 √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √
FM-XC7VX690T-R3 √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU080-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √ √ √
FM-XCKU115-R1 √ √ √ √ √ √
FM-XCVU5P-R1 √ √ √ √ √ √
FM-XCVU7P-R1 √ √ √ √ √ √
FM-XCVU9P-R1 √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √ √ √ √
FM-XCVU47P-R1 √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √(a) √(a)
Extension Boards
Related Work
Table 6-338. EB-PDS-SATA-R4 Extension Site Compatibility (cont.)

V1 V1
FM-1SG280<L,H>-R2 √ √(a) √(a)
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-339. EB-PDS-SATA-R2/R3 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
Related Work
Generating register map files for Si5338 Please refer to Related Work for details how to
generate register map files for the Si5338.
Note
profpga_run
The EB-PDS-SATA-R4 uses three plugins to configure clock distribution, clock generation as
well as SATA redrivers. To load the plugins the plugin_list entry before the
system_configuration section must be added:
plugin_list = ( "sata_eb_clkdist_r4 ProDesign EB-

PDS-SATA-R4",
"si5338 ProDesign EB-PDS-SATA-R4",
"ds125br820 ProDesign EB-PDS-SATA-R4");
...
{
...
Extension Boards
Related Work
<instance name>:
{
type = "BOARD";
name = "EB-PDS-SATA-R4";
size = "A1A1";
v_io_ba1 = "AUTO";
...
};
Extension Boards
Related Work
more information.Settings used for the plugins have to be contained in the x-board entry for EB-
PDS-SATA-R4:
<instance name>:
{
...
# Si5338(A) Plugin Settings
# Clock Distribution Settings
gpio_expander1:
{
IIC_CLK1_ENA = 1; # output to MMCX OUT0 enabled
IIC_CLK3_ENA = 0; # output to MMCX OUT1 disabled
}
# SATA Redriver (DS125BR820) Settings per Connector
X1:
{
TX_PWDN = 0; # 0 = channel enabled, 1 = channel disabled
TX_RXDET = 1;
TX_EQ = 1;
TX_VOD = 6;
TX_VOD_DB = 0;
TX_VTH = 0;
TX_VTH_DA = 0;
RX_PWDN = 0; # 0 = channel enabled, 1 = channel disabled
RX_RXDET = 1;
RX_EQ = 1;
RX_VOD = 6;
RX_VOD_DB = 0;
RX_VTH = 0;
RX_VTH_DA = 0; }
# see DS125BR820 datasheet for detailed description of these settings
# there must be a section for each connector (X1 .. X8)
# only one section is shown here for simplicity
};

Extension Boards
Order Code
profpga_run.
Please refer to the „proFPGA Software Reference Manual” [UD002] for more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-SATA-R4”. The
Order Code
286498
Extension Boards
ADC Board (EB-PDS-ADC250x16-R2)
ADC Board (EB-PDS-ADC250x16-R2)

Refer to the following subsections for a detailed description of the EB-PDS-ADC250x16-R2
board.
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
This extension board has two 16-bit 250MSPS ADCs (ISLA216P25, Intersil). Each ADC has
one channel. The two input channels of the ADCs are connected with an input filtering stage to
MMCX connectors. Both ADCs are directly connected to the bottom connector. Each ADC
channel has its own analog ground and a shielding. The shielding is removable for customizing
the filtering circuit.
A clock generator is on the board which sources the ADCs and 2 clock outputs. It is possible to
work with the same clock for both ADCs or with different clocks. An external clock input is
also connected to the clock generator which allows that one or both ADCs are working with the
external clock source.
An external trigger input is on the board. This port is connected to the proFPGA bottom
connector and may be used for event management.
The board has a proFPGA top connector which makes unused FPGA connections available to
another extension board or a cable.
Features in short overview:
• 2 differential ADC input channels (MMCX connectors), which are connected to

• 2 separated filtering circuits with removable shielding, which are connected to
• 2 ADCs (ISLA216P25, Intersil)
• 1 clock generator which sources both ADCs with the identical or different clocks
• 2 clock outputs
• 1 external clock input connected to the clock generator, this clock can be used to source
one or both ADCs (through the clock generator)
• 1 external trigger input connected to the proFPGA bottom connector
Extension Boards
• 1 proFPGA top connector to make unused FPGA connections available to another

extension board or a cable
Figure 6-264. EB-PDS-ADC250x16 Overview
Peripherals
• Differential ADC input channels
o Both ADC channels are connected to MMCX connectors.
o Between the ADC input connectors and the ADC, a filtering circuit is used. The
filtering circuit is located below the shielding. This filtering circuit is dimensioned
like a bandpass and has a lower frequency limit of 10 kHz and an upper frequency
limit of 100 MHz.
Extension Boards
Figure 6-265. ADC Input Channel Filtering Circuit
The filtering circuit can be easily changed by reassembling the corresponding

components after the dimension of the new filtering circuit is finished. All capacitive
and inductive components are in form factor 0603, excluding C56, C57, C65, C66
(form factor 0402). The transformers have a pitch of 2.54 mm. The land pattern can
be seen in following figure.
Figure 6-266. Land Pattern of Transformer
• Clock Generator
o One Si5338 (Silicon Labs) clock generator is on the board. The output clock
frequency can be changed easily by configuring the Si5338. The Clock Builder
Software from Silicon Labs is used to generate a register map file for this purpose.
Refer to Related Work for detailed explanation. The following figure shows the
connection of the input and output ports of the Si5338.
Extension Boards
Figure 6-267. Connection of Input and Output Ports of the Si5338
o One 25 MHz crystal is connected to the CLKIN1 of the Si5338.

o CLKIN2 is tied to ground.
o The external clock input is connected to the feedback (FDBK) input of the Si5338.
o CLK0 is connected to the ADC input clock of ADC A.
o CLK1 is connected to the ADC input clock of ADC B.
o CLK2 is connected to clock out 1 (CLKO1).
o CLK3 is connected to clock out 2 (CLKO2).
• External Trigger Input
o The external trigger input is connected directly to the FPGA. It can be used to trigger
external events inside the design.
• Clock inputs and outputs
o Please refer to clock generator explanation.
Note
The reset of both ADCs has to be released for proper communication on the 3-
wire interface.

The following table describes the conditions under which the extension board operates.
Table 6-340. EB-PDS-ADC250x16-R2 – Extension Board Operating Conditions

IO voltage 1.710V...1.8V...1.890V
(min...recommended...max)
Extension Boards
Table 6-340. EB-PDS-ADC250x16-R2 – Extension Board Operating Conditions

IO voltage 1.710V...1.8V...1.890V

In the table below:
(1) - only ADC A can be used

Table 6-341. EB-PDS-ADC250x16-R2 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √
FM-XC7VX485T-R3 √ √ √
FM-XC7V585T-R3 √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √ √(1)
FM-XCVU160-R1 √ √ √ √(1)
FM-XCVU125-R1 √ √ √ √(1)
FM-XCVU095-R1 √ √ √ √(1)
FM-XCVU080-R1 √ √ √ √(1)
FM-XCKU115-R1 √ √ √ √(1)
FM-XCVU5P-R1 √ √ √ √(1)
FM-XCVU7P-R1 √ √ √ √(1)
Extension Boards
Table 6-341. EB-PDS-ADC250x16-R2 – FPGA Extension Site Compatibility

V1 V1
FM-XCVU9P-R1 √ √ √ √(1)
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-XCZU19EG-R2 √ √ √(1) √
FM-XCZU17EG-R2 √ √ √(1) √
FM-XCZU11EG-R2 √ √ √(1)
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-342. EB-PDS-ADC250x16-R2 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

The following table describes the pin constraints.
Table 6-343. EB-PDS-ADC250x16 –R2 –FPGA Pin Constraints

LVCMOS18
Extension Boards
Related Work
Related Work
Following is the related work.

Note
Please use 1.8 V LVDS as output type for CLK0 and CLK1 because the output driver is
connected to 1.8 V.
Please use 3.3 V as output type for CLK2 and CLK3 and the IO standard which fits your
application because the output driver is connected to 3.3 V.
profpga_run
...
plugin_list = ( "si5338 ProDesign EB-PDS-ADC250x16-R2" );
{
...
...
"si5338 ProDesign EB-PDS-ADC250x16-R2" );
{
...
Extension Boards
Order Code
<instance name>:
{
type = "BOARD";
name = "EB-PDS-ADC250X16-R2";
size = "A1A1";
v_io_ba1 = "AUTO";
si5338_execute_plugin_async_event = "no";
};
more information.

information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-ADC250x16-R2”. The
Order Code
286496
Extension Boards
Dual DAC Extension Board (EB-PDS-DAC1600x16-R2)
Dual DAC Extension Board (EB-PDS-

DAC1600x16-R2)
Refer to the following subsections for a detailed description of the EB-PDS-DAC1600x16-R2
board.
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
The DAC board provides a dual, 16bit digital-to-analog converter (AD9142A, Analog Devices)
that supports sample rates up to 1600MSPS. Both DAC outputs are connected via analog filter
stages to MMCX connectors.
A programmable clock generator is available to provide clocks to the DAC and optionally to the
FPGA and MMCX connectors. There are also MMCX connectors as a alternative clock input of
the clock generator at the board.
• 1 Analog Devices AD9142A TxDAC+ DAC

• provides proFPGA extension board top connector to make unused connections available
to another extension boards and cable
• EMI Shielding
• a programmable clock generator (configuration via proFPGA plugin)
• optional clock output
• optional clock input
• optional clock connected to FPGAs clock capable inputs
Extension Boards
Figure 6-268. EB-PDS-DAC1600x16-R2 Overview
Each DAC has its own filter stage shown in the following figure which is directly connected to
DAC outputs. These stages are identically for each DAC output. The implemented Low pass
filter (LFCN-800+, Mini-Circuits) passes frequencies between DC and 800MHz with a
maximum insertion loss of 1.3dB through. Its cut-off frequency is 990Mhz.
Figure 6-269. Filter Stage

Extension Boards
Table 6-344. EB-PDS-DAC1600x16-R2– Operating Conditions

IO voltage 1.710V...1.8V...1.890V
Top-side extension board connector available

Table 6-345. EB-PDS-DAC1600x16-R2– FPGA Extension Site Compatibility

V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √
FM-XC7V585T-R3 √ √ √
FM-XC7VX690T-R3 √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU190-R1 √ √ √
FM-XCVU160-R1 √ √ √
FM-XCVU125-R1 √ √ √
FM-XCVU095-R1 √ √ √
FM-XCVU080-R1 √ √ √
FM-XCKU115-R1 √ √ √
FM-XCVU13P-R1 √ √ √ √ √
Extension Boards
Table 6-345. EB-PDS-DAC1600x16-R2– FPGA Extension Site Compatibility

V1 V1
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 6-346. EB-PDS-DAC1600x16-R2 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Table 6-347. EB-PDS-DAC1600X16-R2 FPGA Pin Constraints

DAC_D[*]_P IOSTANDARD = LVDS
DAC_D[*]_N
DAC_DCI_P
DAC_DCI_N
DAC_FRAME_P
DAC_FRAME_N
CLK_FPGA_P
CLK_FPGA _N
Extension Boards
Related Work
Table 6-347. EB-PDS-DAC1600X16-R2 FPGA Pin Constraints (cont.)

all other DAC- Signales IOSTANDARD =
LVCMOS18
Related Work

Note
The following figure shows how the clock outputs and inputs of the Si5338 are connected at the
board.
Figure 6-270. Si5338 Overview
The recommended output type settings of each output are listed in the following table.
Extension Boards
Related Work
Table 6-348. Recommended Output Type Settings for the Si5338

Si5338 Output Type
Output
CLK0A/B Depends on the clock sink and where the clock sink is connected
Single ended clock sinks:
• 1.8V CMOS on A
• 1.8V CMOS on B
• 1.8V CMOS on A and B
Differential clock sinks:
• 1.8V LVDS
CLK1A/B 1.8V LVDS
CLK2A/B 1.8V LVDS
CLK3A/B depends on the FPGA design
Single ended clock:
• 1.8V CMOS on A
Differential clock:
• 1.8V LVDS
profpga_run
...
plugin_list = ( "si5338 ProDesign EB-PDS-ADC250x16-R2" );
{
...
...
"si5338 ProDesign EB-PDS-ADC250x16-R2" );
{
...
Extension Boards
Order Code
<instance name>:
{
type = "BOARD";
name = "EB-PDS-ADC250X16-R2";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-ADC250x16-R2”. The
Order Code
This topic is about the order code of Dual DAC Extension Board EB-PDS-DAC1600x16-R2
board.
Extension Boards
Order Code
286497
Extension Boards
Riser Board (EB-PDS-RISER-R1)
Riser Board (EB-PDS-RISER-R1)

Refer to the following subsections for a detailed description of the EB-PDS-RISER-R1 board.

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
proFPGA Riser Board provides a proFPGA Bottom and a proFPGA Top Connector. It is used
wherever due to height incompatibility two different extension boards cannot be plugged on-top
of each other.
• One proFPGA Bottom Connector

• One proFPGA Top Connector
• I²C subsystem including I²C IDPROM, I²C multiplexer and I²C GPIO expander
Figure 6-271. EB-PDS-RISER-R1!

Extension Boards
Table 6-349. EB-PDS-RISER-R1 – Extension Board Operating Conditions

IO voltage (min...recommended...max) any1
1. Since all regular IO and CLK_IO signals are simply routed through from bottom to top connector this board
does not have any specific requirements regarding the IO voltage. If an extension board or cable is used on
top of this board the IO voltage requirements of this upper-level hardware will be applied.

In the table below:
(1) - using EB-FM-XCVU440-R1

Table 6-350. EB-PDS-RISER-R1– FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √ √ √ √ √ √
FM-XC7VX485T-R3 √ √ √ √ √ √ √ √
FM-XC7V585T-R3 √ √ √ √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(1) √(1)
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(1) √(1)
FM-XCVU190-R1 √ √ √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √ √ √
FM-XCVU080-R1 √ √ √ √ √ √
FM-XCKU115-R1 √ √ √ √ √ √
Extension Boards
Table 6-350. EB-PDS-RISER-R1– FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU5P-R1 √ √ √ √ √ √
FM-XCVU7P-R1 √ √ √ √ √ √
FM-XCVU9P-R1 √ √ √ √ √ √
FM-XCVU13P-R1 √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(1) √(1)
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √ √
FM-XCZU19EG-R2 √ √ √ √ √
FM-XCZU17EG-R2 √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √ √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(1) √(1)
Table 6-351. EB-PDS-RISER-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

Table 6-352. EB-PHS-RISER-R1–FPGA Pin Constraints

all IO signals <any>
Extension Boards
Related Work
Related Work
profpga_run
<instance name>:
{
type = "BOARD";
name = " EB-PDS-RISER-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-RISER-R1”. The
Order Code
286463
Extension Boards
V2 Riser Board (EB-PHS-RISER-R1)
V2 Riser Board (EB-PHS-RISER-R1)

Refer to the following subsections for a detailed description of the EB-PHS-RISER-R1 board.
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
The proFPGA V2 riser board provides a proFPGA V2 bottom and a proFPGA top connector. It
is used wherever due to height incompatibility two different extension boards cannot be plugged
on-top of each other.
Features of the extension board are as follows:
• One proFPGA V2 bottom connector

• One proFPGA V2 top connector
Figure 6-272. EB-PHS-RISER-R1
Note
In comparison to the EB-PDS-RISER-R1 extension board, all signals including the I²C
subsystem is routed from the bottom to the top connector. Therefore, the board is not
present in the configuration file and in the system structure of the software.
Extension Boards

Table 6-353. EB-PHS-RISER-R1 – extension board operating conditions

IO voltage any1
(min…recommended…max)
1. Since all regular IO and CLK_IO signals are simply routed through from bottom to top connector this board
does not have any specific requirements regarding the IO voltage. If an extension board or cable is used on
top of this board the IO voltage requirements of this upper-level hardware will be applied.

Table 6-354. EB-PDS-RISER-R1– FPGA Extension Site Compatibility

FPGA Module TA1 TB1V TC1 TD1 TE1V TF1V TG1 TH1
V2 2 V2 V2 2 2 V2 V2
FM-XCVU13P-R1 √ √ √ √
Note
The extension board is also compatible with the V2 Breakout Board (EB-PDS-
BREAKOUT-R3).

Table 6-355. EB-PHS-RISER-R1–FPGA Pin Constraints

All IO signals any
Related Work
The following is the related work.
Extension Boards
Order Code
profpga_run
For this board, no x-board entry is required within the system configuration file since the I²C
subsystem is routed from the bottom to the top connector of the board and not otherwise
connected.
Order Code
286464
Extension Boards
V2 QSFP28 Extension Board (EB-PHS-QSFP28-R1)
V2 QSFP28 Extension Board (EB-PHS-

QSFP28-R1)
Refer to the following subsections for a detailed description of the EB-PHS-QSFP28-R1 board.
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
The proFPGA V2 QSFP28 extension board provides two sockets for QSFP28 modules and
supports the common transfer rate 25.78125 Gbit/s on each socket.
• One proFPGA V2 bottom connector for connection to the proFPGA system.

• Two QSFP28 ports.
Extension Boards
Figure 6-273. EB-PHS-QSFP28-R1
The following figure shows the structure of the board.
Extension Boards
Figure 6-274. EB-PHS-QSFP28-R1 Board Overview
The following table provides the signal description the broad.

Table 6-356. Signal Description
Signal Signal Description Remarks
I2C proFPGA I²C bus Configuration of the GPIO
expander via plugin
I2C_IP IP I²C bus Configuration of the GPIO
expander via HDL
I2C_A I²C IDPROM connection
port A
I2C_B I²C IDPROM connection
port B
LPMode Low Power Mode pull high for low power
mode
ModInt_L Interrupt when low, it indicates a
host system
ModPrsL Module Present when low a QSFP module is
inserted
Extension Boards
Table 6-356. Signal Description (cont.)

Signal Signal Description Remarks
ModSelL Module Select need to be held low, that the
wire interface
ResetL Module Reset pull low for QSFP module
reset
QSFP_*_RX_[1..4] Receiver Data Output
QSFP_*_TX_[1..4] Transmitter Data Input

Table 6-357. EB-PHS-QSFP28-R1– Operating Conditions

IO voltage 1.200V...1.8V...3.600V

The following table describes the extension site compatibility.
Table 6-358. EB-PHS-QSFP28-R1– FPGA Extension Site Compatibility

FPGA Module TA1 TB1V TC1 TD1 TE1V TF1V TG1 TH1
V2 2 V2 V@ 2 2 V2 V2
FM-XCVU13P-R1 √ √ √ √

Table 6-359. EB-PHS-QSFP28-R1–FPGA Pin Constraints

LVCMOS18
Extension Boards
Related Work
Related Work
The following is the related work.
profpga_run
The EB-PHS-QSFP28-R1 uses one plugin to configure the QSFP modules. To load the plugin
the plugin_list entry before the system_configuration section must be added.
plugin_list = ( "phs_qsfp28 ProDesign EB-PHS-QSFP28-R1" );

...
{
...
<instance name>:
{
type = "BOARD";
name = " EB-PHS-QSFP28-R1";
size = "A1A1V2";
v_io_ba1 = "AUTO";
#Plugin settings
gpio_expander1 :
{
qsfp_a_mod_sel_n = 0;
qsfp_a_reset_n = 0;
qsfp_a_lp_mode = 1;
qsfp_b_mod_sel_n = 0;
qsfp_b_reset_n = 0;
qsfp_b_lp_mode = 1;
};
};
more information.
<register map file> must be replaced with the path and the filename to the register map file.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PHS-QSFP28-R1”. The
Extension Boards
Order Code
Tip
As shown in Figure 6-274, the sideband signals of the QSFP connectors are connected to a
GPIO expander. The GPIO expander will be configured as explained before by a plug-in (if
needed). The GPIO expander is also reachable from the USER FPGA design. Therefore, an IP
is available to read the input signals & write output signals of the GPIO expander. For more
information about HDL IP please refer to “proFPGA HDL Design Library” [UD006].
Order Code
286509
Extension Boards
ARM Express Adapter Board (EB-PDS-EXPRESS-ADAPTER-R1)
ARM Express Adapter Board (EB-PDS-

EXPRESS-ADAPTER-R1)
Refer to the following subsections for a detailed description of the EB-PDS-EXPRESS-
ADAPTER-R1 board.
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Workaround for Error during Verilog Top Level generation . . . . . . . . . . . . . . . . . . . . 887
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
The ARM Express Adapter Board allows using the proFPGA system together with the ARM
Juno platform.
The ARM Express Adapter contains the following features:
• Extension of ARM Juno platform with proFPGA

• Clock generator with two configurable clocks and one fixed clock
• Identification Chips for correct detection of Juno and proFPGA system
• Control of Juno’s nPBRESET(Reboot function) and nPBON (Start function) signals
(optional via cables)
• Support of proFPGA Uno, Duo and Quad Motherboards
• proFPGA is seen from Juno as Logic or Core Tile
The following image shows the ARM Express Adapter Board.
Extension Boards
Figure 6-275. EB-PDS-EXPRESS-ADAPTER-R1

Table 6-360. EB-PDS-EXPRESS-ADAPTER-R1 – Operating conditions

IO voltage 1.710V...1.8V...1.890V
Connected sites 1

Table 6-361. EB-PDS-EXPRESS-ADAPTER-R1 – FPGA Extension Site

Compatibility
V1 V1
FM-XC7V2000T-R1 √
FM-XC7V2000T-R2 √
FM-XC7VX330T-R3 √
FM-XC7VX485T-R3 √
FM-XC7V585T-R3 √
FM-XC7VX690T-R3 √
Extension Boards
Table 6-361. EB-PDS-EXPRESS-ADAPTER-R1 – FPGA Extension Site

V1 V1
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1 √
FM-XCVU440-R2 √
FM-XCVU190-R1
FM-XCVU160-R1
FM-XCVU125-R1
FM-XCVU095-R1
FM-XCVU080-R1
FM-XCKU115-R1
FM-XCVU5P-R1
FM-XCVU7P-R1
FM-XCVU9P-R1
FM-XCVU13P-R1
FM-XCVU19P-R1 √
FM-XCVU37P-R1
FM-XCVU47P-R1
FM-1SG280<L,H>-R1
FM-XCZU19EG-R2
FM-XCZU17EG-R2
FM-XCZU11EG-R2
FM-1SG10M-R1
Table 6-362. : EB-PDS-EXPRESS-ADAPTER-R1 – FPGA Extension Site

FM-1SG10M-R1
FM-XCVU19P-R1
Extension Boards
Related Work
Related Work
For further information about the EB-PDS-EXPRESS-ADAPTER-R1 board please have a look
into [UD011].
Workaround for Error during Verilog Top Level

generation
During the generation of Verilog Top-level files an error can occurs. This error is triggered
through the xml file (board description for proFPGA Builder).
The error can be avoided by selecting the Skip XML Files option in the Generate Board Files
window.
In the figure below, the proFPGA builder opens to “Tools > Generate Code for FPGA
Synthesis...” and the option of “Skip XML Files” is marked.
Figure 6-276. Generate Board Files Window
Order Code
286495
Extension Boards
Flexible Riser Board (EB-PDS-FLEXRISER-R1)
Flexible Riser Board (EB-PDS-FLEXRISER-R1)

The following subsections gives a detailed description of the EB-PDS-FLEXRISER-R1 board.
Speed Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
The proFPGA Flexible Riser Board provides a proFPGA Bottom and a proFPGA Top
Connector. It is used wherever two extension boards cannot be plugged directly on top of each
other. With the Flexible Riser Board an extension board doesn’t need to be located directly on
the proFPGA system but can be angled. This can improve usability and ease bring-up.
• One proFPGA Bottom Connector (Figure 6-277, on the right)

• One proFPGA Top Connector (Figure 6-277, on the left)
• All Power Rails (P12V, P3V3, P3V3_AUX and PV_IO) fully rated
Figure 6-277. EB-PDS-FLEXRISER-R1
Note
There are no MGT connections are available with the Flexible Riser board.
Extension Boards

The following table described the conditions under which the extension board operates.
Table 6-363. EB-PDS-FLEXRISER-R1– Operating Conditions

IO voltage any8
8Since all regular IO and CLK_IO signals are simply routed through from bottom to top
level hardware applies.

The following tables describes the extension site compatibility.
In the table below:
(1)-using
EB-FM-XCVU440-R1
Table 6-364. EB-PDS-FLEXRISER-R1– FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √
FM-XC7VX330T-R3 √ √ √ √ √ √ √ √
FM-XC7VX485T-R3 √ √ √ √ √ √ √ √
FM-XC7V585T-R3 √ √ √ √ √ √ √ √
FM-XC7VX690T-R3 √ √ √ √ √ √ √ √
FM-XC7Z100-R1 √ √
FM-XC7Z045-R1 √ √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(1) √(1)
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(1) √(1)
FM-XCVU190-R1 √ √ √ √ √ √
FM-XCVU160-R1 √ √ √ √ √ √
Extension Boards
Table 6-364. EB-PDS-FLEXRISER-R1– FPGA Extension Site Compatibility

V1 V1
FM-XCVU125-R1 √ √ √ √ √ √
FM-XCVU095-R1 √ √ √ √ √ √
FM-XCVU080-R1 √ √ √ √ √ √
FM-XCKU115-R1 √ √ √ √ √ √
FM-XCVU5P-R1 √ √ √ √ √ √
FM-XCVU7P-R1 √ √ √ √ √ √
FM-XCVU9P-R1 √ √ √ √ √ √
FM-XCVU13P-R1 √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(1) √(1)
FM-XCVU37P-R1 √ √ √ √
FM-XCVU47P-R1 √ √ √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √ √ √
FM-XCZU19EG-R2 √ √ √ √ √
FM-XCZU17EG-R2 √ √ √ √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √ √ √
FM-10AX115-R1 √ √ √ √ √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(1) √(1)
Table 6-365. EB-PDS-FLEXRISER-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

The following table describes the pin constraints.
Extension Boards
Speed Tests
Table 6-366. EB-PDS-FLEXRISER-R1–FPGA Pin Constraints

all IO signals any
Speed Tests
The following values represent minimum values according to measurements done with the first
production lot. All tests were performed on a FM-XC7V2000T-R2 FPGA Module with speed
grade 1.
Table 6-367. EB-PDS-FLEXRISER-R1 - Speed Test Results

IO Standard Speed (in Mb/s) Minimum Value Measured
at
LVCMOS18 340 TB1, BA1, BA2, BB2
HSTL18_I_DCI 408 BB2
HSTL18_II_DCI 495 BA1
SSTL18_I_DCI 415 BA1, BB2
SSTL18_II_DCI 536 BB2
LVDS 1000 BA2
Related Work
This section describes the related work.
profpga_run
<instance name>:
{
type = "BOARD";
name = " EB-PDS-FLEXRISER-R1";
size = "A1A1";
v_io_ba1 = "AUTO";
};
more information.
Extension Boards
Order Code

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-FLEXRISER-R1”.
Order Code
This product is no longer available.
Extension Boards
Zynq US+ Interface Board (EB-FM-XCZUxxEG-R2/R3)
Zynq US+ Interface Board (EB-FM-XCZUxxEG-

R2/R3)
The following subsections gives detailed description of the EB-FM-XCZUxxEG-R2/R3 board.
MIO Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
ProFPGA Connector Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
SATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
CAN Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Display Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
I²C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
GPIO Pin Header, Buttons and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
The Zynq US+ interface board provides interfaces connected to the PS part of the Zynq
Ultrascale+ FPGA module. In addition, this board can also be used on general FPGA modules.
• One proFPGA bottom connector

• CAN interface
• Display port TX interface
• Gbit ethernet interface
• GPIO interface
• I2C interface
• PMU access
• SATA interface
Extension Boards
• USB 3.0 Interface

The following image shows the EB-FM-XCZUxxEG-R2 board.
Figure 6-278. EB-FM-XCZUxxEG-R2 Board
The following image shows the EB-FM-XCZUxxEG-R3 board.
Extension Boards
Figure 6-279. EB-FM-XCZUxxEG-R3 Board

The following table describes the conditions under which the extension board operates.
Table 6-368. EB-FM-XCZUxxEG-R2/R3 – Operating Conditions

IO voltage 1.710V...1.8V...1.890V

The following tables describes the extension site compatibility.
Extension Boards
In the table below:
(1)-Connecting to PS part of the module
(2)-Ethernetcannot be used
Table 6-369. EB-FM-XCZUxxEG-R2/R3-FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √(2) √(2)
FM-XC7V2000T-R2 √(2) √(2)
FM-XC7VX330T-R3 √(2) √(2) √(2)
FM-XC7VX485T-R3 √(2) √(2) √(2)
FM-XC7V585T-R3 √(2) √(2) √(2) √(2)
FM-XC7VX690T-R3 √(2) √(2) √(2) √(2)
FM-XC7Z100-R1 √(2) √(2)
FM-XC7Z045-R1 √(2) √(2)
FM-XCZU11EG-R2 √(2) √(2) √(1)
FM-XCZU17EG-R2 √(2) √(2) √(1)
FM-XCZU19EG-R2 √(2) √(2) √(1)
FM-XCVU440-R1 √(2) √(2) √(2) √(2) √(2) √(2)
FM-XCVU440-R2 √(2) √(2) √(2) √(2) √(2) √(2)
FM-XCVU190-R1 √(2) √(2) √(2) √(2)
FM-XCVU160-R1 √(2) √(2) √(2) √(2)
FM-XCVU125-R1 √(2) √(2) √(2) √(2)
FM-XCVU095-R1 √(2) √(2) √(2) √(2)
FM-XCVU080-R1 √(2) √(2) √(2) √(2)
FM-XCKU115-R1 √(2) √(2) √(2) √(2)
FM-XCVU5P-R1 √(2) √(2) √(2) √(2)
FM-XCVU7P-R1 √(2) √(2) √(2) √(2)
FM-XCVU9P-R1 √(2) √(2) √(2) √(2)
Extension Boards
MIO Pin Connections
Table 6-369. EB-FM-XCZUxxEG-R2/R3-FPGA Extension Site Compatibility

V1 V1
FM-XCVU13P-R1 √(2) √(2) √(2) √(2)
FM-XCVU19P-R1 √(2) √(2) √(2) √(2) √(2) √(2) √(2) √(2)
FM-XCVU37P-R1 √(2) √(2) √(2)
FM-XCVU47P-R1 √(2) √(2) √(2)
FM-1SG280<L,H>-R1 √(2) √(2) √(2)
FM-1SG280<L,H>-R2 √(2) √(2) √(2)
FM-10AX115-R1 √(2) √(2) √(2)
FM-1SG10M-R1 √(2) √(2) √(2) √(2) √(2) √(2) √(2) √(2)
Note
Please refer to Gigabit Ethernet,if Ethernet is needed at the PL part of the FPGA
Table 6-370. EB-FM-XCZUxxEG-R2/R3 - FPGA Extension Site Compatibility,

FM-1SG10M-R1 √(2) √(2) √(2) √(2) √(2) √(2)
FM-XCVU19P-R1 √(2) √(2) √(2) √(2)
MIO Pin Connections

In the case the board has been plugged onto the BB1 connector of the FM-XCZUxxEG-R2
FPGA which connects to the PS part of the FPGA, the interfaces are connected to the MIOs.
Extension Boards
MIO Pin Connections
Table 6-371. EB-FM-XCZUxxEG-R2/R3 MIO Pin Connections

Bank Pin FM-XCZUxx- Bank Pin FM- Bank Pin FM-
R1 XCZUx XCZUx
x-R1 x-R1
501 MIO26 GPIO / CSU / 502 MIO52 USB 3.0 505 Lane 0 DP
PMU
MIO27 DP MIO53 Lane 1
MIO28 MIO54 Lane 2 USB 3.0
MIO29 MIO55 Lane 3 SATA
MIO30 MIO56
MIO31 GPIO / PMU MIO57
MIO32 MIO58
MIO33 MIO59
MIO34 MIO60
MIO35 MIO61
MIO36 MIO62
MIO37 MIO63
MIO38 GPIO / PJTAG MIO64 Gbit
ETH
MIO39 MIO65
MIO40 MIO66
MIO41 MIO67
MIO42 GPIO MIO68
MIO43 MIO69
MIO44 MIO70
MIO45 MIO71
MIO46 CAN 0 MIO72
MIO47 MIO73
MIO48 I2C 1 MIO74
MIO49 MIO75
MIO50 GPIO / VIDEO MIO76
REF CLK
MIO51 GPIO / PSS ALT MIO77
REF CLK
Extension Boards
ProFPGA Connector Signals
ProFPGA Connector Signals

The following table describes the connector signals.
Table 6-372. EB-FM-XCZUxxEG-R2/R3–Signals

MIO26_GPIO_01, MIO31_GPIO_02, Pushbuttons and LEDs connected to GPIO
MIO32_GPIO_03, MIO33_GPIO_04
MIO27_DP_AUX_OUT, Display Port signals
MIO28_DP_HPD, MIO29_DP_OE,
MIO30_DP_AUX_IN
MIO26_GPIO_01, GPIO signals and clocks connected to XGPIO1 pin
MIO[31..45]_GPIO_[02..16] header
MIO50_VIDEO_REF_CLK,
MIO51_PSS_ALT_REF_CLK
MIO46_CAN_PS_RX_1V8, CAN Interface signals
MIO47_CAN_PS_TX_1V8
MIO48_I2C_SCL_1V8, I2C signals
MIO49_I2C_SDA_1V8
MIO52_USB_ULPI_CLK, USB3 signals
MIO53_USB_ULPI_DIR,
MIO54_USB_ULPI_TX_DATA_2,
MIO55_USB_ULPI_NXT,
MIO58_USB_ULPI_STP,
MIO[59..63]_USB_ULPI_TX_DATA
_[3..7]
MIO64_ENET_TX_CLK, GBit Ethernet signals
MIO[65..68]_ENET_TXD_[0..3],
MIO69_ENET_TX_CTL,
MIO70_ENET_RX_CLK,
MIO[71..74]_ENET_RXD_[0..3],
MIO75_ENET_RX_CTL,
IO76_ENET_GEM3_MDC,
MIO77_ENET_GEM3_MDC_IO
PS_MODE[0..3] PS MODE pins
PS_nPOR, PS_nSRST PS Power On Reset and System Reset
Extension Boards
SATA Interface
SATA Interface
A SATA interface is on the board for connection to a common SATA device (for example a
hard disk drive).
The following diagram shows the SATA interface.
Figure 6-280. SATA Interface
Note
For hardware maintenance reasons the XSATA1 connector is flipped by 180° on some
boards. The functionality on both boards is the same.
For powering the SATA device, a SATA power cable is delivered. It can be plugged in between
the SATA device and the power supply for the proFPGA system.
USB Interface
A USB ULPI PHY (USB3320) is on the board and is connected in between the ZYNQ
Ultrascale+ FPGA and the USB-C port.
The USB-C port was implemented to be used as a host as well as a device. Please refer to the
plugin section to get information about the configuration as a host or a device.
The USB-C port is not implemented according to the USB specification. Therefore, the
connector on the board, the cable and the adapter are marked. Please connect the cable or
adapter so that both marks are on the same side.
The following figure explains the connection of the USB C adapter and USB C cable with
marks.
Extension Boards
Ethernet Interface
Figure 6-281. USB C Adapter and USB C Cable
Host:
• uses the USB adapter and connects a device to the USB-A socket
Device:
• uses the USB cable and connects the side with the USB-A cable to a USB host
The USB PHY can be reset by using the button S6.
Ethernet Interface
A Gigabit Ethernet PHY (DP83867IRPAPT) is on the board.
Please refer to the “profpga_run” on page 907 to get information about the configuration of the
Ethernet interface.
The Ethernet PHY can be reset by using button S5.
Note
From R2 to R3 version the orientation of the Ethernet connector has changed by 180° for
better compatibility of the board on the proFPGA system.
CAN Bus Interface

The CAN bus interface on the board can be terminated by using jumpers.
Using a jumper between the pin 3 and 4 of XCAN1 the termination on CANH will be added.
Using a jumper between the pin 5 and 6 of XCAN1 the termination on CANL will be added.
Extension Boards
Display Port Interface
Figure 6-282. CAN Bus Connector and Termination
Figure 6-283. CAN Bus Transceiver

The following diagram describes the display port connector and LVDS driver.
Extension Boards
Figure 6-284. Display Port LVDS Driver
Extension Boards
I²C Interface
Figure 6-285. Display Port Connector
I²C Interface
An I²C interface is on the board. The operating voltage is 3.3 V.
Extension Boards
GPIO Pin Header, Buttons and LEDs
Figure 6-286. I2C Header
GPIO Pin Header, Buttons and LEDs

A GPIO pin header is on the board.
Figure 6-287. GPIO Pin Header EB-FM-XCZUxxEG-R2
Figure 6-288. GPIO Pin Header EB-FM-XCZUxxEG-R3
Extension Boards
Clock Generator
Caution
The operating voltage of the GPIO pins on the header is 1.8 V!
Note
The connector has changed from R2 to R3. On the R3 there is one pin missing which can be
used to develop polarized extension boards for the GPIO pin header.
LEDs and buttons are connected to GPIO pins GPIO_[01..04]. The 4 signals have 10 k pull
down resistors. So normally a logically low signal is present at the pins. By pressing a button,
the signal is additionally connected to a 1 k pull up resistor. In this case a logically high signal is
present at the pin. The pull resistors prevent the pins from damage when using them as outputs
and pressing the buttons.
Clock Generator
A clock generator (Si5338) is on the board which generates the MGT clocks of the ARM. The 4
outputs [0..3] are connected with 100 n AC-capacitors to the
PS_MGTREFCLK[3..0][N,P]_505.
The following figure depicts the clocks generated by the Si5338 and their connection to
PS_MGTREFCLK.
Figure 6-289. Clock Connections - PS_MGTREFCLK
If the extension board is used on another connector of the FM-XCZUxxEG or on another

proFPGA FPGA module, the clocks are connected straight to the MGT banks. The following
figure depicts the clock generated by Si5338 and their connection to MGT_REFCLK.
Extension Boards
Figure 6-290. Clock Connections - MGT_REFCLK

The following table describes the FPGA pin constraints.
Table 6-373. EB-FM-XCZUxxEG-R2/R3-FPGA Pin Constraints

Related Work
The following sections describe the related work.

Note
profpga_run
...
plugin_list = ( "si5338 ProDesign EB-FM-XCZUxxEG-R2" );
{
...
Extension Boards
Related Work
Respectively:
...
plugin_list = ( "si5338 ProDesign EB-FM-XCZUxxEG-R3" );
{
...
If there is already a plugin_list entry the plugin list must be extended.
Example:
...
plugin_list = ("dp83865dvh ProDesign EB-PDS-GBITETHERNET-R1", "si5338
ProDesign EB-FM-XCZUxxEG-R2" );
{
...
Respectively:
...
plugin_list = ("dp83865dvh ProDesign EB-PDS-GBITETHERNET-R1", "si5338
ProDesign EB-FM-XCZUxxEG-R3" );
{
...
<instance name>:
type = "BOARD";
name = "EB-FM-XCZU19EG-R2";
size = ""A1A1";
v_io_ba1 = "AUTO";

};
Extension Boards
Related Work
Respectively:
<instance name>:
{
type = "BOARD";
name = "EB-FM-XCZU19EG-R3";
size = "A1A1";
v_io_ba1 = "AUTO";

};
system configuration. Please refer to the “proFPGA Software Reference Manual" [UD002] for
more information.

profpga_run. Please refer to the „proFPGA Software Reference Manual" [UD002] for more
information.
If the GPIO Expander is used, it will be configured with a profpga plugin. To load the plugin the
...
plugin_list = ( "xczuxxeg_eb_config ProDesign EB-FM-XCZUxxEG-R2" );
{
...
Respectively:
...
plugin_list = ( "xczuxxeg_eb_config ProDesign EB-FM-XCZUxxEG-R3" );
{
...
Extension Boards
Related Work
...
"xczuxxeg_eb_config ProDesign EB-FM-XCZUxxEG-R2" );
{
...
Respectively:
...
"xczuxxeg_eb_config ProDesign EB-FM-XCZUxxEG-R3" );
{
...
This will load the GPIO Expander plugin.
profpga_run
<instance name>:
{
type = "BOARD";
vendor = "ProDesign"
name = "EB-FM-XCZUxxEG-R2";
size = "A1A1";
positions = ("motherboard_1.BB1");
v_io_ba1 = "AUTO";
# Settings of Components on the board
gpio_expander1:
{
USB_ID_SEL = 0; # 0 -> A/B Cable Detect | 1 -> ID not used
USB_CVBUS_SEL = 1; # 0 -> Device or OTG | 1 -> Hos
USB_HD_MODE_SEL0 = 1; # 0 -> Device or OTG | 1 -> Host
USB_HD_MODE_SEL1 = 1; # 0 -> OTG | 1 -> Host/Device
PS-POR_RESET_N = 1; # 0 -> USB and Ethernet is in reset | 1 -> USB
and Ehternet not in reset (in dependence of PS-MODE1 and GEM3_EXP_RESET_N)
PS-MODE1 = 1; # 0 -> Ethernet is in reset | 1 -> USB is not in reset
(in dependence of PS-MODE1 and PS-POR_RESET_N)
GEM3_EXP_RESET_N = 1; # 0 -> USB is in reset | 1 -> Ehternet is
not in reset (in dependence of PS-MODE1 and PS-POR_RESET_N)
}
};
Extension Boards
Related Work
Respectively:
<instance name>:
{
type = "BOARD";
name = "EB-FM-XCZUxxEG-R2";
size = "A1A1";
positions = ("motherboard_1.BB1");
v_io_ba1 = "AUTO";
# Settings of Components on the board
gpio_expander1:
{
USB_ID_SEL = 0; # 0 -> A/B Cable Detect | 1 -> ID not used
USB_CVBUS_SEL = 1; # 0 -> Device or OTG | 1 -> Host
USB_HD_MODE_SEL0 = 1; # 0 -> Device or OTG | 1 -> Host
USB_HD_MODE_SEL1 = 1; # 0 -> OTG | 1 -> Host/Device
PS-POR_RESET_N = 1; # 0 -> USB and Ethernet is in reset | 1 -> USB
and Ehternet not in reset (in dependence of PS-MODE1 and GEM3_EXP_RESET_N)
PS-MODE1 = 1; # 0 -> Ethernet is in reset | 1 -> USB is not in reset
(in dependence of PS-MODE1 and PS-POR_RESET_N)
GEM3_EXP_RESET_N = 1; # 0 -> USB is in reset | 1 -> Ehternet is
not in reset (in dependence of PS-MODE1 and PS-POR_RESET_N)
}
};
system configuration. Please refer to the „proFPGA Software Reference Manual" [UD002] for
more information.

profpga_run. Please refer to the „proFPGA Software Reference Manual" [UD002] for more
information.

plugged onto.
contains a valid x-board entry using the extension board name "EB-PDS-DDR4-R2" or "EB-
PDS-DDR4-R3". The system configuration file can be created manually or with the
Extension Boards
Order Code
Please refer to the “proFPGA Software Reference Manual" [SWRM] and the "proFPGA
Builder User Manual" [UD004] for more information.
Order Code
286525
Extension Boards
Multi-Cluster Clock Synchronization Boards
Multi-Cluster Clock Synchronization Boards

The following subsections provides detailed description of the Multi-Cluster Clock
Synchronization board.
Three boards belong in this category:
• EB-MB-CLK-SYNC-R3: Master clock synchronization board

• EB-MB-CLK-SYNC-R4: Slave clock synchronization board
• EB-BP-CLK-SYNC-R1: Back panel clock and sync signal distribution board
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Power Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Clock and Sync Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
The clock synchronization boards were developed for multi cluster clock synchronization.
The master board has one clock and one sync signal output. In addition, the board has one clock
and one sync signal input.
The slave board has one clock and one sync signal input.
Two cables are connected from the master board’s outputs to the back panel clock and sync
signal distribution board’s inputs. The back panel distribution board has 6 outputs for clock and
for sync signals, each. So up-to 6 clusters can be synchronized with the boards. The outputs of
the clock and sync signals are connected to the inputs of the master and slave clock
synchronization boards.
A full setup would consist of one master clock synchronization board, one back panel clock and
sync signal distribution board and up-to 5 slave clock synchronization boards.
Extension Boards
Figure 6-291. Clock Synchronization Concept
Each of the clock and the sync signal outputs of the back panel distribution board are equal. It
would be no problem if output number 4 is connected to the clock input of one slave clock
synchronization board and sync output number 3 is connected to the sync input of the same
slave clock synchronization board. For better traceability it is recommended to connect the
outputs of the back panel distribution board as it is intended.
Caution
Do not mix up clock and sync inputs and outputs with each other! This will lead to
unpredictable behavior of the system and may damage it.
Figure 6-292. EB-MB-CLK-SYNC-R3 Board and EB-BP-CLK-SYNC-R1 Board
Extension Boards
Compatibility
Compatibility
The master and the slave clock synchronization boards are compatible with the generation 2
motherboard (MB-4M-R3). They must be plugged onto the XEXT1 extension board connector.
The back panel clock and sync signal distribution board is compatible with the master and slave
clock synchronization boards.
Power Cable
The back panel clock and sync signal distribution board needs to be powered by 12V.
Therefore, a 6-pin connector as used on the proFPGA motherboard is present. Connect a cable
from the PSU to the power connector of the back panel clock and sync signal distribution board.
Clock and Sync Cables

The section describes the cable used for connections.
The boards can be connected with the following cable:
• IC-CJT-CABLE-R1: Clock and synchronization cable, 3 m length.
Extension Boards
Order Code
Figure 6-293. IC-CJT-CABLE-R1
Order Code
The following section describes the order code for this board.
Table 6-374. Order Code

EB-MB-CLK-SYNC-R3 No order code available.
EB-MB-CLK-SYNC-R4 No order code available.
EB-BP-CLK-SYNC-R1 No order code available.
Extension Boards
Order Code
Table 6-374. Order Code (cont.)

IC-CJT-CABLE-R1 No order code available.
Extension Boards
Order Code
Chapter 7
Interconnect Boards and Cables
This chapter discusses interconnect boards and cables.
Interconnect Cable (IC-PDS-CABLE-R1/R6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

FPGA Extension Site Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
1:1 Interconnect Cable (IC-PDS-CABLE-R4/R5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
Interconnect Cable (IC-PDS-CABLE-R2/R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Interconnect Cable (IC-PHS-CABLE-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
East-West Interconnect (IC-PDS-EW-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
North-South Interconnect (IC-PDS-NS-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
4-way Interconnect (IC-PDS-4WAY-R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Breakout Board (EB-PDS-BREAKOUT-R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
V2 Breakout Board (EB-PDS-BREAKOUT-R3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Firmware Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
TA1V1/TA2V1 Adapter Board (EB-FM-XCVU440-R1) . . . . . . . . . . . . . . . . . . . . . . . . . 983
Signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Interconnect Cable (IC-PDS-CABLE-R1/R6)

This topic discusses interconnect cable (IC-PDS-CABLE-R1/R6).
Figure 7-1. Interconnect Cable IC-PDS-CABLE-R1/R6

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
This topic discusses functional description of interconnect cable (IC-PDS-CABLE-R1/R6).
The interconnect cable connects two FPGA extension sites.

This topic discusses extension board operating conditions for interconnect cable (IC-PDS-
CABLE-R1/R6).
Table 7-1. IC-PDS-CABLE-R1/R6 – Extension Board Operating conditions

IO voltage (min…recommended…max) No limitations
Connected sites 2

This topic discusses FPGA extension site compatibility interconnect cable (IC-PDS-CABLE-
R1/R6).
In the table below, (1) only 1 IO bank,
(2)
only 2 IO banks,
(3)
(4) only 3 HD banks (72 pins),
(5)
only 2 HD banks (48 pins)
Table 7-2. IC-PDS-CABLE-R1/R6 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √(1)
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √(1)
FM-XC7VX330T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7VX485T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7V585T-R3 √ √(2) √ √ √ √(1)
FM-XC7VX690T-R3 √ √(2) √ √ √ √(1)
FM-XC7Z100-R1 √(2) √
FM-XC7Z045-R1 √(2) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(
3) 3)
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(1)( √(1)(

3) 3)
FM-XCVU190-R1 √ √ √ √(2) √(1) √(1)

FM-XCVU160-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU125-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU095-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU080-R1 √ √ √ √(2) √(1) √(1)
Table 7-2. IC-PDS-CABLE-R1/R6 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCKU115-R1 √ √ √ √(2) √(1) √(1)
FM-1SG280<L,H>-R1 √ √ √ √ √ √(1) √ √
FM-XCVU5P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU7P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU9P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(3)( √(3)(
5) 5)
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-XCZU11EG-R2 √ √ √(4)
FM-XCZU17EG-R2 √ √ √(4) √
FM-XCZU19EG-R2 √ √ √(4) √
FM-1SG280<L,H>-R2 √ √ √ √ √ √(1) √ √
FM-10AX115-R1 √ √ √ √ √(1) √(1)
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(
3) 3)
Table 7-3. IC-PDS-CABLE-R1/R6 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √
Table 7-4. IC-PDS-CABLE-R1/R6 – Available Connections

3 IO banks (148 2 IO banks (98 1 IO bank (48
pins) pins) pins)
3 IO banks (148 pins) 140 94 44
Table 7-4. IC-PDS-CABLE-R1/R6 – Available Connections (cont.)

3 IO banks (148 2 IO banks (98 1 IO bank (48
pins) pins) pins)
2 IO banks (98 pins) 94 90 44
1 IO bank (48 pins) 44 44 40
In the figure below, populated pins: A = 148pins-to-148pins, B=98pins-to-98pins, C=48pins-to-
48pins, D=148pins-to-98pins, E=148/98pins-to-48pins
Figure 7-2. IC-PDS-Cable-R1/R6 – Interconnect Scheme
The Figure 7-2 above shows the IOs of two proFPGA connectors and how they are
interconnected when an IC-PDS-CABLE-R1/R6 is plugged. The cables are not connecting
straight the same pins on every cable, but they are connecting different IOs e.g. IO146 is
connected to IO138 and IO147 is connected to IO139.
The colored bars on the right are visualizing what happens when proFPGA connectors with
different available IOs are interconnected (also see descriptions below the figure). If there is
only one green bar the connections are valid in both directions for the IOs where the bar is
shown. When a lower IO count connector connects to one with more IOs just some of the IOs
will be interconnected. Then there are two bars showing which IOs from the connector on the
left side are connected (yellow bar) and which IOs from the connector on the right side are
connected (blue bar). As an example, when a 148pin connector is interconnected with a 98pin
connector, IO072 and IO073 on the left side connector are connected but IO072 and IO073 on
the right side connector not because they are not available there (not connected to an FPGA
bank).

This topic discusses FPGA pin constraints of interconnect cable (IC-PDS-CABLE-R1/R6).
Table 7-5. IC-PDS-CABLE-R1/R6 –FPGA Pin Constraints

All signals According to FPGA IO
limitations
Related Work
This topic discusses related work of interconnect cable (IC-PDS-CABLE-R1/R6).
profpga_run
For this cable the following x-board entry is required within the system configuration file:
<instance name>:
{
type = "CABLE";
name = "IC-PDS-CABLE-R1";
positions = ("<position1>", "<position2>");
v_io = "AUTO";
};
<instance name>, <position1> and <position2> must be replaced with the correct value
according to the system configuration. Please refer to the „proFPGA Software Reference
Manual” [UD002] for more information.
Order Code

plugged onto.
contains a valid x-board entry using the extension board name “IC-PDS-CABLE-R1”. The
Order Code
This topic discusses order code of interconnect cable (IC-PDS-CABLE-R1/R6).
Length Order Code

40 cm 286461
80 cm 286462
120 cm 286467
160 cm 286468
200 cm 286469
1:1 Interconnect Cable (IC-PDS-CABLE-R4/R5)
1:1 Interconnect Cable (IC-PDS-CABLE-R4/R5)

This topic discusses 1:1 interconnect cable (IC-PDS-CABLE-R4/R5).
Figure 7-3. 1:1 Interconnect Cable IC-PDS-CABLE-R4

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
This topic discusses functional description of 1:1 interconnect cable (IC-PDS-CABLE-R4/R5).
The interconnect cable connects two FPGA extension sites without signal crossings.

This topic discusses extension board operating conditions for 1:1 interconnect cable (IC-PDS-
CABLE-R4/R5).
Table 7-6. IC-PDS-CABLE-R1– Extension Board Operating Conditions

Connected sites 2

This topic discusses FPGA extension site compatibility of 1:1 interconnect cable (IC-PDS-
CABLE-R4/R5).
In the table below,
(1) only 1 IO bank,
(2) only 2 IO banks,
(3) using EB-FM-XCVU440-R1,
(4) only 3 HD banks (72 pins),
(5)
Table 7-7. IC-PDS-CABLE-R1 – FPGA Extension Site Compatibility
V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √(1)
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √(1)
FM-XC7VX330T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7VX485T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7V585T-R3 √ √(2) √ √ √ √(1)
FM-XC7VX690T-R3 √ √(2) √ √ √ √(1)
FM-XC7Z100-R1 √(2) √
FM-XC7Z045-R1 √(2) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(
3) 3)
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(1)( √(1)(

3) 3)
FM-XCVU190-R1 √ √ √ √(2) √(1) √(1)

FM-XCVU160-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU125-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU095-R1 √ √ √ √(2) √(1) √(1)
Table 7-7. IC-PDS-CABLE-R1 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU080-R1 √ √ √ √(2) √(1) √(1)
FM-XCKU115-R1 √ √ √ √(2) √(1) √(1)
FM-1SG280<L,H>-R1 √ √ √ √ √ √(1) √ √
FM-XCVU5P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU7P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU9P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(3)( √(3)(
5) 5)
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-XCZU11EG-R2 √ √ √(4)
FM-XCZU17EG-R2 √ √ √(4) √
FM-XCZU19EG-R2 √ √ √(4) √
FM-1SG280<L,H>-R2 √ √ √ √ √ √(1) √ √
FM-10AX115-R1 √ √ √ √ √(1) √(1)
FM-1SG10M-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(
3) 3)
Table 7-8. IC-PDS-CABLE-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √
Table 7-9. IC-PDS-CABLE-R1 – Available Connections

3 IO banks (148 2 IO banks (98 pins) 1 IO bank (48 pins)
pins)
3 IO banks (148 140 94 44
pins)
2 IO banks (98 pins) 94 90 44
1 IO bank (48 pins) 44 44 40
In the image below, populated pins: A = 148pins-to-148pins, B=98pins-to-98pins, C=48pins-to-

48pin
Figure 7-4. IC-PDS-Cable-R1 – Interconnect Scheme
The Figure 7-4 above shows the IOs of two proFPGA connectors and how they are
interconnected when an IC-PDS-CABLE-R4/R5 is plugged. The cables are connecting straight
the same pins on every cable.
The colored bars on the right are visualizing which IOs are available when interconnecting two
proFPGA connectors depending on how many banks are available.

This topic discusses FPGA pin constraints in 1:1 interconnect cable (IC-PDS-CABLE-R4/R5).

limitations
Related Work
This topic discusses related work of 1:1 interconnect cable (IC-PDS-CABLE-R4/R5).
profpga_run
<instance name>:
{
type = "CABLE";
name = "IC-PDS-CABLE-R4";
v_io = "AUTO";
};
according to the system configuration. Please refer to the “proFPGA Software Reference

plugged onto.
contains a valid x-board entry using the extension board name “IC-PDS-CABLE-R4”. The
Order Code
Order Code
This topic discusses order code of 1:1 interconnect cable (IC-PDS-CABLE-R4/R5).
Length Order Code

40 cm 287251
80 cm 287252

This topic discusses interconnect cable (IC-PDS-CABLE-R2/R3).
Figure 7-5. Interconnect Cable IC-PDS-CABLE-R2/R3

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
This topic discusses functional description of interconnect cable (IC-PDS-CABLE-R2/R3).
The interconnect cable connects two FPGA extension sites using small pin count connectors.
This cable can be plugged directly on the TA1V1 and TA2V1 sites of the FM-XCVU440R-R1/
R2 FPGA modules and can be used in conjunction with the EB-PDS-BREAKOUT-R1 breakout
board to connect one proFPGA V0 connector with multiple FPGAs.
The cable is compatible to the proFPGA V1 connector type. All signals are connected using a
1:1 interconnection scheme.

This topic discusses etension board operating conditions of interconnect cable (IC-PDS-
CABLE-R2/R3).
Table 7-11. IC-PDS-CABLE-R2/R3– Extension Board Operating Conditions

Connected sites 2

This topic discusses FPGA extension site compatibility interconnect cable (IC-PDS-CABLE-
R2/R3).
(2)
only 2 IO banks,
(3)
using EB-PDS-BREAKOUT-R1,
(4)
only 3 HD banks (72 pins),
(5)
V1 V1
FM-XC7V2000T-R1 √(3) √(3) √(3) √(3) √(3) √(3) √(3) √(1)(
3)
FM-XC7V2000T-R2 √(3) √(3) √(3) √(3) √(3) √(3) √(3) √(1)(

3)
FM-XC7VX330T-R3 √(3) √(1)( √(3) √(1)( √(3) √(1)(

3) 3) 3)
FM-XC7VX485T-R3 √(3) √(1)( √(3) √(1)( √(3) √(1)(

3) 3) 3)
FM-XC7V585T-R3 √(3) √(2)( √(3) √(3) √(3) √(1)(

3) 3)
FM-XC7VX690T-R3 √(3) √(2)( √(3) √(3) √(3) √(1)(

3) 3)
FM-XC7Z100-R1 √(2)( √(3)

3)

V1 V1
FM-XC7Z045-R1 √(2)( √(3)
3)
FM-XCVU440-R1 √(3) √(3) √(3) √(3) √(3) √(3) √(3) √(3) √(1) √(1)
FM-XCVU440-R2 √(3) √(3) √(3) √(3) √(3) √(3) √(3) √(3) √(1) √(1)
FM-XCVU190-R1 √(3) √(3) √(3) √(2) √(3) √(3)
FM-XCVU160-R1 √(3) √(3) √(3) √(2) √(3) √(3)
FM-XCVU125-R1 √(3) √(3) √(3) √(2) √(3) √(3)
FM-XCVU095-R1 √(3) √(3) √(3) √(2) √(3) √(3)
FM-XCVU080-R1 √(3) √(3) √(3) √(2) √(3) √(3)
FM-XCKU115-R1 √(3) √(3) √(3) √(2) √(3) √(3)
FM-1SG280<LH>-R1 √(3) √(3) √(3) √(3) √(3) √(1)( √(3) √(3)
3)
FM-XCVU5P-R1 √ √ √ √(2) √(1) √(1)

FM-XCVU7P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU9P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-XCZU11EG-R2 √ √ √(4)
FM-XCZU17EG-R2 √ √ √(4) √
FM-XCZU19EG-R2 √ √ √(4) √
FM-1SG280<L,H>-R2 √(3) √(3) √(3) √(3) √(3) √(1)( √(3) √(3)
3)
FM-10AX115-R1 √(3) √(3) √(3) √(3) √(3) √(3)

FM-1SG10M-R1 √(3) √(3) √(3) √(3) √(3) √(3) √(3) √(3) √(1) √(1)
Table 7-13. IC-PDS-CABLE-R2/R3 – FPGA Extension Site Compatibility,

FM-1SG10M-R1 √ √ √ √ √ √
FM-XCVU19P-R1 √ √ √ √

This topic discusses FPGA pin constraints in interconnect cable (IC-PDS-CABLE-R2/R3).

limitations
Related Work
This topic discusses related work of interconnect cable (IC-PDS-CABLE-R2/R3).
profpga_run
<instance name>:
{
type = "CABLE";
name = "IC-PDS-CABLE-R2"; # or R3
v_io = "AUTO";
};

plugged onto.
Order Code
contains a valid x-board entry using the extension board name “IC-PDS-CABLE-R2/R3”. The
Order Code
This topic discusses order code of interconnect cable (IC-PDS-CABLE-R2/R3).
Length Order Code

40 cm 286465
80 cm 286466
Interconnect Cable (IC-PHS-CABLE-R1)
Interconnect Cable (IC-PHS-CABLE-R1)

This topic discusses interconnect cable (IC-PHS-CABLE-R1).
Figure 7-6. Interconnect Cable IC-PHS-CABLE-R1

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
This topic discusses functional description of interconnect cable (IC-PHS-CABLE-R1).
The IC-PHS-CABLE-R1 was developed for connecting high speed serial IO transceivers of 2
FPGAs together.
The cable is compatible to the proFPGA V2 connector type. All signals are connected using a
1:1 interconnection scheme.
Note
There are IOs available on the connector. These IOs are also connected due to the cable.
Since the cable is developed for high-speed serial IO transceiver signals, the IOs in the cable
should be used in differential mode (LVDS for example). This additional information is only for
the IOs in the cable!
Note
Due to the design, it cannot be differentiated if no cable is plugged or if a cable with only
one end is plugged onto the PHS connector.

This topic discusses extension board operating conditions of interconnect cable (IC-PHS-
CABLE-R1).
Table 7-15. IC-PHS-CABLE-R1– Extension Board Operating Conditions

IO voltage (min…recommended…max) 1710...1800...1890 mV
Connected sites 2

This topic discusses FPGA compatibility of interconnect cable (IC-PHS-CABLE-R1).
FM-XCVU13P-R1

This topic discusses FPGA pin constraints of interconnect cable (IC-PHS-CABLE-R1).
Table 7-16. IC-PHS-CABLE-R1 –FPGA pin constraints

all IO signals LVDS
Related Work
This topic discusses related work of interconnect cable (IC-PHS-CABLE-R1).
Skew
profpga_run
<instance name>:
{
type = "CABLE";
name = "IC-PHS-CABLE-R1";
v_io = "AUTO";
};

plugged onto.
contains a valid x-board entry using the extension board name “IC-PHS-CABLE-R1”. The
Skew
This topic discusses skew of interconnect cable (IC-PHS-CABLE-R1).
By using the (80 cm) cable, a delay of 3.84 to 3.85 ns has to be taken into account.
Order Code
This topic discusses order code of interconnect cable (IC-PHS-CABLE-R1).
Length Order Code

80 cm Order Code missing
East-West Interconnect (IC-PDS-EW-R2)
East-West Interconnect (IC-PDS-EW-R2)

This topic discusses East-West interconnect (IC-PDS-EW-R2).
Figure 7-7. (IC-PDS-EW-R2)

Signal mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
This topic discusses functional description of East-West interconnect (IC-PDS-EW-R2).
The proFPGA East-West Interconnect board provides connection between two horizontally
adjacent FPGA modules on the same motherboard.
Signal mapping
Figure 7-8. East-West Interconnect Board (view from top)
Signal mapping
This topic discusses signal mapping in East-West interconnect (IC-PDS-EW-R2).
Table 7-17. IC-PDS-EW-R2 – Signal Mapping

GND all GND pins are connected
to the GND net
P3V3_AUX 1 power supply for IDPROM
I2C 2 IDPROM
IO 148 connect matching pins of
XEBC1 and XEBB1? Note:
The wire length within each
group must match (+/- 10ps).
CLK_IO 16 connect matching pins of
XEBC1 and XEBB1 (1:1
mapping)? Note: The wire
length within each group
must match (+/- 10ps).

This topic discusses extension board operating conditions of East-West interconnect (IC-PDS-
EW-R2).
Table 7-18. IC-PDS-EW-R2 – Extension Board Operating Conditions

Connected sites 2

This topic discusses FPGA extension site compatibility of East-West interconnect (IC-PDS-
EW-R2).
(2)
only 2 IO banks,
(3)
Table 7-19. IC-PDS-EW-R2 – FPGA Extension Site Compatibility
V1 V1
Extension site of peer TB1 TB2 TA1 TA2 BB1 BB2 BA1 BA2
FPGA
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √(1)
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √(1)
FM-XC7VX330T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7VX485T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7V585T-R3 √ √(2) √ √ √ √(1)
FM-XC7VX690T-R3 √ √(2) √ √ √ √(1)
FM-XC7Z100-R1 √(2) √
FM-XC7Z045-R1 √(2) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
Table 7-19. IC-PDS-EW-R2 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU190-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU160-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU125-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU095-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU080-R1 √ √ √ √(2) √(1) √(1)
FM-XCKU115-R1 √ √ √ √(2) √(1) √(1)
FM-1SG280<L,H>-R1 √ √ √ √ √ √(1) √ √
FM-XCVU5P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU7P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU9P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCZU11EG-R2 √ √ √(3)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-XCZU17EG-R2 √ √ √(3) √
FM-XCZU19EG-R2 √ √ √(3) √
FM-1SG280<L,H>-R2 √ √ √ √ √ √(1) √ √
FM-10AX115-R1 √ √ √ √ √ √
FM-1SG10M-R1 √ √ √ √ √ √ √ √
Table 7-20. IC-PDS-EW-R2 – FPGA Extension Site Compatibility,

Extension site of peer TB0 TA0 BB0 BA0
FPGA
FM-1SG10M-R1 √ √ √ √
FM-XCVU19P-R1 √ √ √ √

This topic discusses FPGA pin constraints of East-West interconnect (IC-PDS-EW-R2).
Table 7-21. IC-PDS-EW-R2 –FPGA Pin Constraints

limitations
Related Work
This topic discusses related work of East-West interconnect (IC-PDS-EW-R2).
profpga_run
<instance name>:
{
type = "BOARD";
name = "IC-PDS-EW-R2";
size = "B1C1";
v_io_bb1 = "AUTO";
v_io_bc1 = "AUTO";
};

plugged onto.
contains a valid x-board entry using the extension board name “IC-PDS-EW-R2”. The system
configuration file can be created manually or with the profpga_builder tool.
Order Code
Order Code
This topic discusses order code of East-West interconnect (IC-PDS-EW-R2).
286458
North-South Interconnect (IC-PDS-NS-R2)
North-South Interconnect (IC-PDS-NS-R2)

This topic discusses North-South interconnect (IC-PDS-NS-R2).
Figure 7-9. North-South Interconnect board

Signal mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
This topic discusses functional description of North-South interconnect (IC-PDS-NS-R2).
The proFPGA North-South Interconnect board provides connection between two vertically
adjacent FPGA modules on the same motherboard or on two motherboards.
Signal mapping
Figure 7-10. North-South Interconnect Board (view from top)
Signal mapping
This topic discusses signal mapping of North-South interconnect (IC-PDS-NS-R2).
Table 7-22. IC-PDS-NS-R2 – Signal Mapping

to the GND net
V3P3_AUX 1 power supply for IDPROM
I2C 2 IDPROM
IO 148 connect matching pins of
XEBA2 and XEBA3 (1:1
matching)? Note: The wire
CLK_IO 8 pairs connect matching pins of
XEBA2 and XEBA3 (1:1
mapping)? Note: The wire

This topic discusses extension board operating conditions of North-South interconnect (IC-
PDS-NS-R2).
Table 7-23. IC-PDS-NS-R2 – Extension Board Operating Conditions

Connected sites 2

This topic discusses FPGA extension site compatibility of North-South interconnect (IC-PDS-
NS-R2).
(2)
only 2 IO banks,
(3)
(4)
only 3 HD banks (72 pins),
(5)
only 2 HD banks (48 pins).
Table 7-24. IC-PDS-NS-R2 – FPGA Extension Site Compatibility
V1 V1
Extension site of peer TA2 TA1 TB2 TB1 BA2 BA1 BB2 BB1 TA2 TA1
FPGA V1 V1
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √(1)
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √(1)
FM-XC7VX330T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7VX485T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7V585T-R3 √ √(2) √ √ √ √(1)
FM-XC7VX690T-R3 √ √(2) √ √ √ √(1)
FM-XC7Z100-R1 √(2) √
Table 7-24. IC-PDS-NS-R2 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XC7Z045-R1 √(2) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √ √(1)( √(1)(
3) 3)
FM-XCVU440-R2 √ √ √ √ √ √ √ √ √(1)( √(1)(

3) 3)
FM-XCVU190-R1 √ √ √ √(2) √(1) √(1)

FM-XCVU160-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU125-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU095-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU080-R1 √ √ √ √(2) √(1) √(1)
FM-XCKU115-R1 √ √ √ √(2) √(1) √(1)
FM-1SG280<L,H>-R1 √ √ √ √ √ √(1) √ √
FM-XCVU5P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU7P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU9P-R1 √ √ √ √(2) √(1) √(1)
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √ √(3)( √(3)(
5) 5)
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
FM-XCZU11EG-R2 √ √ √(4)
FM-XCZU17EG-R2 √ √ √(4) √
FM-XCZU19EG-R2 √ √ √(4) √
FM-1SG280<L,H>-R2 √ √ √ √ √ √(1) √ √
FM-10AX115-R1 √ √ √ √ √ √
FM-1SG10M-R1
Table 7-25. IC-PDS-NS-R2 – FPGA Extension Site Compatibility,

FM-1SG10M-R1
FM-XCVU19P-R1

This topic discusses FPGA pin constraints of North-South interconnect (IC-PDS-NS-R2).
Table 7-26. IC-PDS-NS-R2 –FPGA Pin Constraints

limitations
Related Work
This topic discusses related work of North-South interconnect (IC-PDS-NS-R2).
profpga_run
<instance name>:
{
type = "BOARD";
name = "IC-PDS-NS-R2";
size = "A2A3";
v_io_ba2 = "AUTO";
v_io_ba3 = "AUTO";
};
Order Code

plugged onto.
contains a valid x-board entry using the extension board name “IC-PDS_NS-R2”. The system
configuration file can be created manually or with the profpga_builder tool.
Order Code
This topic discusses order code of North-South interconnect (IC-PDS-NS-R2).
286459
4-way Interconnect (IC-PDS-4WAY-R1)
4-way Interconnect (IC-PDS-4WAY-R1)

This topic discusses 4-way interconnect (IC-PDS-4WAY-R1).
Figure 7-11. 4-way interconnect board

Signal mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
This topic discusses functional description of 4-way interconnect (IC-PDS-4WAY-R1).
The proFPGA 4-way interconnect board provides connection between four adjacent FPGA
modules on the same motherboard.
Signal mapping
Figure 7-12. 4-way Interconnect Board (view from top)
Caution
The 4-way interconnect board can not be used on generation 2 motherboards.
Signal mapping
This topic discusses signal mapping of 4-way interconnect (IC-PDS-4WAY-R1).
Table 7-27. IC-PDS-4WAY-R1 – Signal Mapping

P3V3_AUX 1 power supply for IDPROMs;
GPIO expander (XEBB2)
P3V3 2 XEBB2: power supply for
LDO
PV_IO 5 XEBB2: power supply for
CPLD input and output
I2C 2 IDPROM; GPIO expander
(XEBB2)
Signal mapping
Table 7-27. IC-PDS-4WAY-R1 – Signal Mapping (cont.)

IO 148 connect each IOx-Pins from
each connector? e.g.
XEBB2.IO0 - XEBB3.IO0 -
XEBC2.IO0 - XEBC3.IO0
CLK_IO 16 All CLK_IO_N_x pins of all
connectors are connected as
inputs to the three CLPDs.
All CLK_IO_P_x pins of all
connectors are connected as
outputs from the three
CLPDs. The clocks are
routed in that way inside the
CLPD that one
CLK_IO_N_x, e.g.
XEBB3_CLK_IO_N_3, is
connected to all
CLK_IO_P_x pins, e.g.
XEB[B,C][2,3], except for
the sending FPGA. The
master CLK_IO_N_x can be
chosen for each x with the
GPIO expander.
JTAG 4 XEBB2: connect JTAG
interface to all 3 CPLDs
Figure 7-13. Connection of CLK_IO Singals to CPLD
Figure 7-14. Example of CLK_IO Signal Switching
Caution
The CLK_IOs should be used as IO signals. Since they are not routed as T-signals like the
normal IOs on this board, the signal integrity is better.
Tip
If the same clock has to be used in multiple FPGAs, it is recommended to use the
motherboard clock distribution network. These clocks are length matched and routed
differentially to the FPGAs. With the help of the SYNC signals, the designs in multiple FPGAs
also can be synchronized.
Caution
Due to the T-connection of the signals all signals on the board should be used as low speed
synchronous signals.
Caution
The facts below have to be kept in mind for configuration of the plugin. The plugin is
referenced to the extension board - not to the motherboard connectors. If the board is used
on bottom side, please be aware, that:
• XEBB2 of the extension board is plugged onto BB3 of motherboard extension board con
• XEBB3 of the extension board is plugged onto BB2 of motherboard extension board con
• XEBC2 of the extension board is plugged onto BC3 of motherboard extension board con
• XEBC3 of the extension board is plugged onto BC2 of motherboard extension board con

This topic discusses extension board operating conditions of 4-way interconnect (IC-PDS-
4WAY-R1).
Table 7-28. IC-PDS-4WAY-R1– Extension Board Operating Conditions

Connected sites 4

This topic discusses 4-way interconnect (IC-PDS-4WAY-R1).
(2) only 2 IO banks

Table 7-29. IC-PDS-4WAY-R1 – FPGA Extension Site Compatibility
V1 V1
FM-10AX115-R1 √ √ √ √ √ √
FM-1SG10M-R1 √ √
FM-1SG280<L,H>-R1 √ √ √ √ √ √(1) √ √
FM-1SG280<L,H>-R2 √ √ √ √ √ √(1) √ √
FM-XC7V2000T-R1 √ √ √ √ √ √ √ √(1)
FM-XC7V2000T-R2 √ √ √ √ √ √ √ √(1)
FM-XC7VX330T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7VX485T-R3 √ √(1) √ √(1) √ √(1)
FM-XC7V585T-R3 √ √(2) √ √ √ √(1)
FM-XC7VX690T-R3 √ √(2) √ √ √ √(1)
FM-XC7Z045-R1 √(2) √
FM-XC7Z100-R1 √(2) √
FM-XCKU115-R1 √ √ √(2) √
FM-XCVU080-R1 √ √ √(2) √
FM-XCVU095-R1 √ √ √(2) √
FM-XCVU125-R1 √ √ √(2) √
Table 7-29. IC-PDS-4WAY-R1 – FPGA Extension Site Compatibility (cont.)

V1 V1
FM-XCVU160-R1 √ √ √(2) √
FM-XCVU190-R1 √ √ √(2) √
FM-XCVU440-R1 √ √ √ √ √ √ √ √
FM-XCVU440-R2 √ √ √ √ √ √ √ √
FM-XCVU5P-R1 √ √ √(2) √
FM-XCVU7P-R1 √ √ √(2) √
FM-XCVU9P-R1 √ √ √(2) √
FM-XCVU13P-R1 √ √ √ √ √(1)
FM-XCVU19P-R1 √ √ √ √ √ √ √ √
FM-XCVU37P-R1 √ √ √(1) √
FM-XCVU47P-R1 √ √ √(1) √
Table 7-30. IC-PDS-4WAY-R1 – FPGA Extension Site Compatibility,

FM-1SG10M-R1
FM-XCVU19P-R1

This topic discusses FPGA pin constraints of 4-way interconnect (IC-PDS-4WAY-R1).
Table 7-31. IC-PDS-4WAY-R1 – FPGA Pin Constraint

All signals According to FPGA IO limitations, regarding IO voltage
range
Related Work
Related Work
This topic discusses related work of 4-way interconnect (IC-PDS-4WAY-R1).
profpga_run
The IC-PDS-4WAY-R1 uses one plugin to configure the distribution of the clk_io signals. To
load the plugin, the plugin_list entry before the system_configuration section must be added:
plugin_list = ( "pds_4way ProDesign IC-PDS-4WAY-

R1");
...
{
...
<instance name>:
{
type = "BOARD";
name = "IC-PDS-4WAY-R1";
size = "B2C3";
positions = ("<position1>", "<position2>", "<position3>",
"<position4>");
v_io_bb2 = "AUTO";
v_io_bb3 = "AUTO";
v_io_bc2 = "AUTO";
v_io_bc3 = "AUTO";
gpio_expander1:
{
clk_io_0 = "<setting>";
# Expecteced values for <setting> are:
# XEBB2
# XEBB3
# XEBC2
# XEBC3
};
};
<instance name>, <position1>, < position2>, <position3> and <position4> must be replaced
with the correct value according to the system configuration. Please refer to the „proFPGA
Software Reference Manual” [UD002] for more information.
Order Code
<setting> must be replaced with the correct value of the source for the appropriate channel.

plugged onto.
contains a valid x-board entry using the extension board name “IC-PDS-4WAY-R1”. The
Order Code
This topic discusses order code of 4-way interconnect (IC-PDS-4WAY-R1).
286460
Breakout Board (EB-PDS-BREAKOUT-R2)
Breakout Board (EB-PDS-BREAKOUT-R2)

This topic discusses Breakout Board (EB-PDS-BREAKOUT-R2).

Signal mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
This topic discusses functional description of Breakout Board (EB-PDS-BREAKOUT-R2).
The proFPGA breakout board provides the ability to spread a single proFPGA connector in up
to three proFPGA V1 connectors. Features of the extension board:
• One proFPGA bottom connector

• Three proFPGA V1 top connectors (X1, X2, X3)
• Each proFPGA V1 top connector provides P12, P3V3, P3V3_AUX, PV_REF and
PV_IO
• Each proFPGA V1 top connector provides an individual FPGA I2C control bus
• The proFPGA V1 top connectors provide a different number of I/Os:
o X1: 47 I/Os and 8 Clock-I/Os
Signal mapping
Figure 7-15. EB-PDS-BREAKOUT-R2
Signal mapping
This topic discusses signal mapping of Breakout Board (EB-PDS-BREAKOUT-R2).
Table 7-32. EB-PDS-BREAKOUT-R2– Signal Mapping

to the GND net
V3P3_AUX 1 power supply for I2C sub
system
PV_IO 3x5 connected to top connectors
P12V 3x5 connected to top connectors
P3V3 3x2 connected to top connectors
I2C 2 IDPROM and I2C sub
system
IO 2 x 47 X1: DQ02 / DQ05 / DQ03* /
1 x 46 DQ04* / 7 unique I/Os
= 141 X2: DQ00 / DQ01 / DQ06* /
DQ07* / 7 unique I/Os
X3: DQ08 / DQ09 / DQ10* /
DQ11* / 6 unique I/Os
* 8 I/Os -> rest as
CLK__IOs
Table 7-32. EB-PDS-BREAKOUT-R2– Signal Mapping (cont.)

CLK_IO 3 x 4 pair X1: DQ03 / DQ04 each 4
CLK I/Os
X2: DQ06 / DQ07 each 4
CLK I/Os
X2: DQ10 / DQ11 each 4
CLK I/Os
MGT not connected

This topic discusses extension board operating conditions of Breakout Board (EB-PDS-
BREAKOUT-R2).
Table 7-33. EB-PDS-BREAKOUT-R2– Extension Board Operating Conditions

1. Since all regular IO and CLK_IO signals are simply routed from bottom to top connector this board
does not have any specific requirements regarding the IO voltage. If an extension board or cable is used
on top of this board the IO voltage requirements of this upper-level hardware will be applied.

This topic discusses FPGA extension site compatibility of Breakout Board (EB-PDS-
BREAKOUT-R2).
Table 7-34 (top connectors) and Table 7-35(bottom connectors) show the compatibility of the
EB-PDS-BREAKOUT-R2 with the different proFPGA FPGA modules
Top Connectors:
Table 7-34. EB-PDS-BREAKOUT-R2– FPGA Extension Site Compatibility (Top
Connectors)
FM-XC7V2000T-R1 X1 X2 X3 X1 X2 X3 X1 X2 X3 X1 X2 X3
I/ 43 40 43 43 40 43 43 40 43 43 40 43
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XC7V2000T-R2 I/ 43 40 41 43 40 41 43 40 41 43 40 41
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XC7VX330T-R3 I/ 43 40 41 8 24 - 43 40 41 8 24 -
Os
Cl 8 8 8 0 8 8 8 8 8 0 8 8
k I/
Os
FM-XC7VX485T-R3 I/ 43 40 41 8 24 - 43 40 41 8 24 -
Os
Cl 8 8 8 0 8 8 8 8 8 0 8 8
k I/
Os
FM-XC7V585T-R3 I/ 43 40 41 40 30 4 43 40 41 43 40 41
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XC7VX690T-R3 I/ 43 40 41 40 30 4 43 40 41 43 40 41
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os

Connectors) (cont.)
FM-XC7Z100-R1 I/ 40 40 8 43 40 41 - - - - - -
Os
Cl 8 8 8 8 8 8 - - - - - -
k I/
Os
FM-XC7Z045-R1 I/ 40 40 8 43 40 41 - - - - - -
Os
Cl 8 8 8 8 8 8 - - - - - -
k I/
Os
FM-XCVU440-R1 I/ 43 43 43 43 43 41 43 43 43 43 43 43
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XCVU440-R2 I/ 43 43 43 43 43 41 43 43 43 43 43 43
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XCVU190-R1 I/ 43 43 43 43 43 41 43 43 43 36 24 -
Os
Cl 8 8 8 8 8 8 8 8 8 - 4 4
k I/
Os
FM-XCVU160-R1 I/ 43 43 43 43 43 41 43 43 43 36 24 -
Os
Cl 8 8 8 8 8 8 8 8 8 - 4 4
k I/
Os
FM-XCVU125-R1 I/ 43 43 43 43 43 41 43 43 43 36 24 -
Os
Cl 8 8 8 8 8 8 8 8 8 - 4 4
k I/
Os

Connectors) (cont.)
FM-XCVU095-R1 I/ 43 43 43 43 43 41 43 43 43 36 24 -
Os
Cl 8 8 8 8 8 8 8 8 8 - 4 4
k I/
Os
FM-XCVU080-R1 I/ 43 43 43 43 43 41 43 43 43 36 24 -
Os
Cl 8 8 8 8 8 8 8 8 8 - 4 4
k I/
Os
FM-XCKU115-R1 I/ 43 43 43 43 43 41 43 43 43 36 24 -
Os
Cl 8 8 8 8 8 8 8 8 8 - 4 4
k I/
Os
FM-1SG280<L,H>-R1 I/ 40 40 37 40 40 37 40 40 37 40 40 37
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XCVU13P-R1 I/ - - - - - - 43 43 43 43 43 43
Os
Cl - - - - - - 8 8 8 8 8 8
k I/
Os
FM-XCVU19P-R1 I/ 43 43 43 43 43 41 43 43 43 43 43 43
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XCVU37P-R1 I/ 43 43 43 43 43 41 11 24 - 43 43 43
Os
Cl 8 8 8 8 8 8 - 8 8 8 8 8
k I/
Os

Connectors) (cont.)
FM-XCVU47P-R1 I/ 43 43 43 43 43 41 11 24 - 43 43 43
Os
Cl 8 8 8 8 8 8 - 8 8 8 8 8
k I/
Os
FM-1SG280<L,H>-R2 I/ 40 40 37 40 40 37 40 40 37 40 40 37
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-10AX115-R1 I/ 40 40 37 40 40 37 40 40 37 40 40 37
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-1SG10M-R1 I/ 40 40 37 40 40 37 40 40 37 40 40 37
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
Bottom Connectors:
Table 7-35. EB-PDS-BREAKOUT-R2– FPGA Extension Site Compatibility
(Bottom Connectors)
FM-XC7V2000T-R1 X1 X2 X3 X1 X2 X3 X1 X2 X3 X1 X2 X3
I/ 43 40 43 43 40 43 43 40 43 8 26 -
Os
Cl 8 8 8 8 8 8 8 8 8 0 8 8
k I/
Os
FM-XC7V2000T-R2 I/ 43 40 41 43 40 41 43 40 41 8 24 -
Os
Cl 8 8 8 8 8 8 8 8 8 0 8 8
k I/
Os

(Bottom Connectors) (cont.)
FM-XC7VX330T-R3 I/ 43 40 41 8 24 - - - - - - -
Os
Cl 8 8 8 0 8 8 - - - - - -
k I/
Os
FM-XC7VX485T-R3 I/ 43 40 41 8 24 - - - - - - -
Os
Cl 8 8 8 0 8 8 - - - - - -
k I/
Os
FM-XC7V585T-R3 I/ 43 40 41 8 24 - - - - - - -
Os
Cl 8 8 8 0 8 8 - - - - - -
k I/
Os
FM-XC7VX690T-R3 I/ 43 40 41 8 24 - - - - - - -
Os
Cl 8 8 8 0 8 8 - - - - - -
k I/
Os
FM-XC7Z100-R1 I/ - - - - - - - - - - - -
Os
Cl - - - - - - - - - - - -
k I/
Os
FM-XC7Z045-R1 I/ - - - - - - - - - - - -
Os
Cl - - - - - - - - - - - -
k I/
Os
FM-XCVU440-R1 I/ 43 43 43 43 43 41 43 43 43 43 43 43
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os

FM-XCVU440-R2 I/ 43 43 43 43 43 41 43 43 43 43 43 43
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XCVU190-R1 I/ - - - - - - - 21 - - 21 -
Os
Cl - - - - - - - 4 - - 4 -
k I/
Os
FM-XCVU160-R1 I/ - - - - - - - 21 - - 21 -
Os
Cl - - - - - - - 4 - - 4 -
k I/
Os
FM-XCVU125-R1 I/ - - - - - - - 21 - - 21 -
Os
Cl - - - - - - - 4 - - 4 -
k I/
Os
FM-XCVU095-R1 I/ - - - - - - - 21 - - 21 -
Os
Cl - - - - - - - 4 - - 4 -
k I/
Os
FM-XCVU080-R1 I/ - - - - - - - 21 - - 21 -
Os
Cl - - - - - - - 4 - - 4 -
k I/
Os
FM-XCKU115-R1 I/ - - - - - - - 21 - - 21 -
Os
Cl - - - - - - - 4 - - 4 -
k I/
Os

FM-1SG280<L,H>-R1 I/ 40 40 37 - 23 - 40 40 37 40 40 37
Os
Cl 8 8 8 - 8 8 8 8 8 8 8 8
k I/
Os
FM-XCVU13P-R1 I/ 43 43 43 - - - 43 43 43 22 24 -
Os
Cl 8 8 8 - - - 8 8 8 8 8 8
k I/
Os
FM-XCVU19P-R1 I/ 43 43 43 43 43 41 43 43 43 43 43 43
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
FM-XCVU37P-R1 I/ - - - - - - - - - - - -
Os
Cl - - - - - - - - - - - -
k I/
Os
FM-XCVU47P-R1 I/ - - - - - - - - - - - -
Os
Cl - - - - - - - - - - - -
k I/
Os
FM-1SG280<L,H>-R2 I/ 40 40 37 - 23 - 40 40 37 40 40 37
Os
Cl 8 8 8 - 8 8 8 8 8 8 8 8
k I/
Os
FM-10AX115-R1 I/ 40 40 37 - 23 - - 39 - - 40 -
Os
Cl 8 8 8 - 8 8 - 8 8 - 8 8
k I/
Os

FM-1SG10M-R1 I/ 40 40 37 40 40 37 40 40 37 40 40 37
Os
Cl 8 8 8 8 8 8 8 8 8 8 8 8
k I/
Os
Table 7-36. EB-PDS-BREAKOUT-R2 – FPGA Extension Site Compatibility (“0”

Top Connectors)
FPGA Module TA0 TAB0 TB0
FM-1SG10M-R1 I/Os 40 40 37 40 40 37 40 40 37
Clk 8 8 8 8 8 8 8 8 8
I/Os
FM-XCVU19P-R1 I/Os 43 43 43 - - - 43 43 43
Clk 8 8 8 - - - 8 8 8
I/Os
Table 7-37. EB-PDS-BREAKOUT-R2 – FPGA Extension Site Compatibility (“0”

Bottom Connectors)
FPGA Module BA0 BAB0 BB0
FM-1SG10M-R1 I/Os 40 40 37 40 40 37 40 40 37
Clk 8 8 8 8 8 8 8 8 8
I/Os
FM-XCVU19P-R1 I/Os 43 43 43 - - - 43 43 43
Clk 8 8 8 - - - 8 8 8
I/Os

This topic discusses FPGA pin constraints of Breakout Board (EB-PDS-BREAKOUT-R2).
Table 7-38. EB-PDS-BREAKOUT-R2–FPGA Pin Constraints

Related Work
Related Work
This topic discusses related work of Breakout Board (EB-PDS-BREAKOUT-R2).
profpga_run
<instance name>:
{
type = "BOARD";
name = " EB-PDS-BREAKOUT-R2";
size = "A1A1";
positions = ("<position.pos>");
top_connectors = ( "<pos>*X1", "<pos>*X2", "<pos>*X3" );
v_io_ba1 = "AUTO";
};
<instance name>, <position.pos> and <pos> must be replaced with the correct value according
to the system configuration. Please refer to the “proFPGA Software Reference Manual”
[UD002] for more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-BREAKOUT-R2”.
Order Code
This topic discusses order code of Breakout Board (EB-PDS-BREAKOUT-R2).
286470
V2 Breakout Board (EB-PDS-BREAKOUT-R3)
V2 Breakout Board (EB-PDS-BREAKOUT-R3)

This topic discusses V2 Breakout Board (EB-PDS-BREAKOUT-R3).

Signal mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Firmware Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
This topic discusses functional description of V2 Breakout Board (EB-PDS-BREAKOUT-R3).
The proFPGA V2 breakout board provides the ability to spread a single proFPGA-connector
into one proFPGA (V0) top connector and two proFPGA V2 top connectors. Features of the
extension board:
• One proFPGA-bottom connector

• One proFPGA (V0) top connector (X1)
• Two proFPGA V2 top connectors (X2, X3)
• The proFPGA (V0) top connector provides P12, P3V3, P3V3_AUX, PV_REF and
PV_IO
• Each proFPGA V2 top connector provides P12, P3V3_AUX and PV_IO
• Each top connector provides an individual I2C control bus
• X2 provides upto 8 differential MGTs [serial IO channels] (depending on the FPGA
module connector) and 10 single ended or 5 differential IOs
• X3 provides upto 4 differential MGTs [serial IO channels] (depending on the FPGA
module connector) and 10 single ended or 5 differential IOs
• X1 provides all remaining IOs of the FPGA module connected to the corresponding
connector. Since all serial IOs are connected to X2 and X3, no serial IOs are available at
X1.
Signal mapping
Figure 7-16. EB-PDS-BREAKOUT-R3
Signal mapping
This topic discusses signal mapping of V2 Breakout Board (EB-PDS-BREAKOUT-R3).
Table 7-39. EB-PDS-BREAKOUT-R3 @X1 – Signal Mapping

to the GND net
P3V3_AUX 1 power supply for I2C sub
system
P3V3 2 connected to top connectors
system
IO All remaining IOs from the
bottom connecto
CLK_IO 8 pair
MGT not connected
Signal mapping
Table 7-40. EB-PDS-BREAKOUT-R3 @X2 & X3 – Signal Mapping

to the GND net
P3V3_AUX 1 power supply for I2C sub
system
system
IO 10 10 IOs are connected to each
connector
MGT X2: 8? X3: 4 8 serial IOs channels
([R,T]X_[N,P]) are
connected? 4 serial IOs
channels ([R,T]X_[N,P]) are
connected
2 clock generators (Si5332E-D-GM2) are on the board providing clocks for the MGTs.
Signal mapping
Figure 7-17. EB-PDS-BREAKOUT-R3: Functional Description
According to the clock connection scheme, 2 incoming clocks from X2 and one incoming clock
coming from X3 (MGT_REFCLK_[N,P]_0) are connected to the clock generators. With the
help of the ‘Clock Builder Pro Software’ a register map file can be created for configuring the
clocks. The incoming clocks from connectors X2 and X3 can be used as well as a self generated
clock from the clock generator or a mix of both. Please refer to Reference Clocks at V2
Connectors for more information about configuring the Si5332-E-D-GM2.
X2: 3 output clocks of the clock generator (OUT0, OUT1, OUT2) are connected to the
proFPGA bottom connector of the extension board.
X3: 1 output clock of the clock generator (OUT0) is connected to the proFPGA bottom
connector of the extension board.
Caution
The clocks are inputs for the connectors X2 and X3 on the extension board. If 2 connectors
are interconnected with a cable, no clock will be transferred in the cable because there is no
driver. In this case, an asynchronous clock must be generated on each side of the connector
using the clock generator.

This topic discusses extension board operating conditions of V2 Breakout Board (EB-PDS-
BREAKOUT-R3).
Table 7-41. EB-PDS-BREAKOUT-R3– Extension Board Operating Conditions

IO voltage (min…recommended…max) 1710...1800...1890 mV

This topic discusses FPGA extension site compatibility of V2 Breakout Board (EB-PDS-
BREAKOUT-R3).
The proFPGA V2 top connectors are mainly connectors for MGTs [serial IOs]. Therefore, the
compatibility list considers only connectors with MGTs [serioal IOs].
In the table below, (1) 4 MGTs are available at X2, no MGTs are available at X3
(2)
8 MGTs are available at X2, no MGTs are available at X3
(3)
8 MGTs are available at X2, no MGTs are available at X3, no IOs are connected, IOs may be
needed for extension boards
(4)
6 MGTs are available at X2, no MGTs are available at X3
Table 7-42. EB-PDS-BREAKOUT-R3 – FPGA Extension Site Compatibility
FPGA Module TA1 TA2 TB1 TB2 BA1 BA2 BB1 BB2
FM-XC7V2000T-R1 √(2) √(2)
FM-XC7V2000T-R2 √(2) √(2)
FM-XC7VX330T-R3 √(2) √(2) √
FM-XC7VX485T-R3 √(2) √(2) √
Table 7-42. EB-PDS-BREAKOUT-R3 – FPGA Extension Site Compatibility

FM-XC7V585T-R3 √(2) √(2) √(2) √
FM-XC7VX690T-R3 √(2) √(2) √(2) √
FM-XC7Z100-R1 √(2) √(2)
FM-XC7Z045-R1 √(2) √(2)
FM-XCVU440-R1 √(2) √(2) √(2) √(2) √(2) √(2)
FM-XCVU440-R2 √(2) √(2) √(2) √(2) √(2) √(2)
FM-XCVU190-R1 √ √ √ √ √(2) √(2)
FM-XCVU160-R1 √ √ √ √ √(2) √(2)
FM-XCVU125-R1 √ √ √ √ √(2) √(2)
FM-XCVU095-R1 √(2) √ √(1) √ √(2) √(2)
FM-XCVU080-R1 √(2) √ √(1) √ √(2) √(2)
FM-XCKU115-R1 √(2) √(2) √ √ √(2) √(2)
FM-XCVU5P-R1 √ √ √ √ √(2) √(2)
FM-XCVU7P-R1 √ √ √ √ √(2) √(2)
FM-XCVU9P-R1 √ √ √ √ √(2) √(2)
FM-XCVU37P-R1 √ √ √ √ √(3) √(3)
FM-XCVU47P-R1 √ √ √ √ √(3) √(3)
FM-XCZU11EG-R2 √(2) √(2)
FM-XCZU17EG-R2 √(2) √(2)
FM-XCZU19EG-R2 √(2) √(2)
FM-1SG280<L,H>-R1 √ √(4)
FM-1SG280<L,H>-R2 √ √(4)
FM-10AX115-R1 √ √ √ √
FM-1SG10M-R1 √ √ √ √
Table 7-43. EB-PDS-BREAKOUT-R3 – FPGA Extension Site Compatibility,

FM-1SG10M-R1
Caution
The maximum transfer rate depends on the chosen proFPGA FPGA module and speedgrade
of the FPGA. The board was tested with the FM-XCVU13P-R1. To achieve a datarate of 25
Gbit / s with a BER value < 10-14 on all links, a speedgrade 3 XCVU13P was used. It is not
guaranteed to achieve this BER value with a speedgrade 2 XCVU13P.

This topic discusses FPGA pin constraints of V2 Breakout Board (EB-PDS-BREAKOUT-R3).
Table 7-44. EB-PDS-BREAKOUT-R3 – FPGA Pin Constraints

Related Work
This topic discusses related work of V2 Breakout Board (EB-PDS-BREAKOUT-R3).
profpga_run
<instance name>:
{
type = "BOARD";
name = " EB-PDS-BREAKOUT-R3";
size = "A1A1";
positions = ("<position.pos>");
top_connectors = ( "<pos>*X1", "<pos>*X2", "<pos>*X3" );
v_io_ba1 = "AUTO";
x2_si5332_registermap_file = "<register map file>";
x3_si5332_registermap_file = "<register map file>";
};
Firmware Requirement
<instance name>, <position.pos>, <pos> and <register map file> must be replaced with the
correct value according to the system configuration. Please refer to the „proFPGA Software
If no clock is needed at the output of the clock generators, it can be set to "OFF". In this case the
clock generator will not be configured on power up.

plugged onto.
contains a valid x-board entry using the extension board name “EB-PDS-BREAKOUT-R3”.
Firmware Requirement
This topic discusses firmware requirement of V2 Breakout Board (EB-PDS-BREAKOUT-R3).
Caution
This board can only be used with a firmware version of 2020C or newer. Otherwise, the
board cannot be identified in the right way and will not work es expected.
Order Code
This topic discusses order code of V2 Breakout Board (EB-PDS-BREAKOUT-R3).
286742
TA1V1/TA2V1 Adapter Board (EB-FM-XCVU440-R1)
TA1V1/TA2V1 Adapter Board (EB-FM-

XCVU440-R1)
This topic discusses TA1V1/TA2V1 Adapter Board (EB-FM-XCVU440-R1).

Signal mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
This topic discusses functional description of TA1V1/TA2V1 Adapter Board (EB-FM-
XCVU440-R1).
The EB-FM-XCVU440-R1 consists of two boards which allow to convert the proFPGA V1
connectors on modules to regular proFPGA V0 connectors. One of the two boards is dedicated
to the TA1V1 connector and the second board is dedicated to the TA2V1 connector.
Figure 7-18. EB-FM-XCVU440-R1
Signal mapping
This topic discusses signal mapping of TA1V1/TA2V1 Adapter Board (EB-FM-XCVU440-
R1).
Table 7-45. EB-PDS-BREAKOUT-R3 @X1 – Signal Mapping

P3V3_AUX 1 power supply for IDPROM,
connected to top connector
P3V3 2 connected to top connector
P12V 5 connected to top connector
PV_IO 5 connected to top connector
I2C 2 IDPROM, connected to top
connector
IO 70 IO_[0-7] connected to
CLK_IO_[NP]_[4-7] on top
connector
IO_[8-61] connected to
IO_[0-53] on top connector
CLK_IO 8 connected to
CLK_IO_[NP]_[0-3] on top
connector
JTAG 4 connected to top connector
MGT not applicable

This topic discusses extension board operating conditions of TA1V1/TA2V1 Adapter Board
(EB-FM-XCVU440-R1).
Table 7-46. EB-FM-XCVU440-R1 – Extension Board Operating Conditions


This topic discusses FPGA extension site compatibility of TA1V1/TA2V1 Adapter Board (EB-
FM-XCVU440-R1).
In the table below, (1) in total 51 IOs and CLK_IOs are connected,
(2) in total 52 IOs and CLK_IOs are connected,
(3)
only 2 HD banks available (48 IOs).
Table 7-47. EB-FM-XCVU440-R1– FPGA Extension Site Compatibility
FM-XC7V2000T-R1
FM-XC7V2000T-R2
FM-XC7VX330T-R3
FM-XC7VX485T-R3
FM-XC7V585T-R3
FM-XC7VX690T-R3
FM-XC7Z100-R1
FM-XC7Z045-R1
FM-XCVU440-R1 √(1) √(2)
FM-XCVU440-R2 √(1) √(2)
FM-XCVU190-R1
FM-XCVU160-R1
FM-XCVU125-R1
FM-XCVU095-R1
FM-XCVU080-R1
FM-XCKU115-R1
FM-1SG280<L,H>-R1
FM-XCVU19P-R1 √(3) √(3)
FM-XCVU37P-R1
FM-XCVU47P-R1
FM-1SG280<L,H>-R2
FM-10AX115-R1
FM-1SG10M-R1 √(1) √(1)
Table 7-48. EB-FM-XCVU440-R1– FPGA Extension Site Compatibility,

FM-1SG10M-R1
FM-XCVU19P-R1

This topic discusses FPGA pin constraints of TA1V1/TA2V1 Adapter Board (EB-FM-
XCVU440-R1).
Table 7-49. EB-FM-XCVU440-R1–FPGA Pin Constraints

Related Work
This topic discusses related work of TA1V1/TA2V1 Adapter Board (EB-FM-XCVU440-R1).
profpga_run
For this board the following x-board entry is required within the system configuration file for
the adapter board plugged onto TA1V1:
<instance name>:
{
type = "BOARD";
name = "EB-FM-XCVU440-TA1V1-R1";
size = "A1A1V1";
positions = ("<motherboard>.TA1V1");
v_io_ba1 = "AUTO";
};
Order Code
For the adapter at TA2V1 the following x-board entry is required:
<instance name>:
{
type = "BOARD";
name = "EB-FM-XCVU440-TA2V1-R1";
size = "A1A1V1";
positions = ("<motherboard>.TA2V1");
v_io_ba1 = "AUTO";
};
more information.

plugged onto.
contains a valid x-board entry using the extension board name “EB-FM-XCVU440-TA1V1-
R1” and “EB-FM-XCVU440-TA2V1-R1”. The system configuration file can be created
manually or with the profpga_builder tool.
Order Code
This topic discusses order code of TA1V1/TA2V1 Adapter Board (EB-FM-XCVU440-R1).
286471
Order Code
Chapter 8
Board Assembly Checklist
This chapter discusses board assembly checklist.

• any connector:
o Only connect boards which are provided by Siemens, or which comply with the
proFPGA extension board design guides.
o Do not connect FMC boards. This may irreversibly damage the FMC board, the
proFPGA prototyping system or both.
o Ensure that no obstacles block the assembly path (e.g., cables, screws, other boards).
o Always use standoffs to fix the board. The standard length for standoffs is 10 mm.
Use 5 mm standoffs for connections to the motherboard when board stiffeners are
present.
o Check if Board connector ends with single and double notch point to the same
direction.
o Check if connectors are collocated before applying pressure to join them (e.g., screw
holes match).
• FM:
o FM only fits to topside of motherboard. Do not assemble FM anywhere else.
o FPGA faces downward, i.e., heat sink enters hole in motherboard, “this side up”
appears on top side.
• EB/IC:
o Do not connect to bottom side of FM.
o Do not connect top side of stackable EB to top side of MB.
• Power Supply:
o Connect all 6-pin power connectors on the motherboard to power supplies.
o The proFPGA prototyping system supports the use of different power supplies for
each of the power connectors.
Board Assembly Checklist

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SIEMENS EDA

proFPGA Hardware User

About Siemens Digital Industries Software

Support Center: support.sw.siemens.com

Revision Date Author Comments

proFPGA Hardware User Guide, v2022A-SP2

4 proFPGA Hardware User Guide, v2022A-SP2

proFPGA Hardware User Guide, v2022A-SP2 5

6 proFPGA Hardware User Guide, v2022A-SP2

proFPGA Hardware User Guide, v2022A-SP2 7

8 proFPGA Hardware User Guide, v2022A-SP2

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10 proFPGA Hardware User Guide, v2022A-SP2

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12 proFPGA Hardware User Guide, v2022A-SP2

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14 proFPGA Hardware User Guide, v2022A-SP2

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16 proFPGA Hardware User Guide, v2022A-SP2

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18 proFPGA Hardware User Guide, v2022A-SP2

proFPGA Hardware User Guide, v2022A-SP2 19

20 proFPGA Hardware User Guide, v2022A-SP2

proFPGA Hardware User Guide, v2022A-SP2 21

22 proFPGA Hardware User Guide, v2022A-SP2

proFPGA Hardware User Guide, v2022A-SP2 23

24 proFPGA Hardware User Guide, v2022A-SP2

proFPGA Hardware User Guide, v2022A-SP2 25

26 proFPGA Hardware User Guide, v2022A-SP2

proFPGA Hardware User Guide, v2022A-SP2 27

28 proFPGA Hardware User Guide, v2022A-SP2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

proFPGA Hardware User Guide, v2022A-SP2 29

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

30 proFPGA Hardware User Guide, v2022A-SP2

FPGA Extension Site Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

proFPGA Hardware User Guide, v2022A-SP2 31

FPGA Extension Site Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

32 proFPGA Hardware User Guide, v2022A-SP2

FPGA Extension Site Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

proFPGA Hardware User Guide, v2022A-SP2 33

FPGA Pin Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

34 proFPGA Hardware User Guide, v2022A-SP2

Extension Board Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

proFPGA Hardware User Guide, v2022A-SP2 35

FPGA Pin Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

36 proFPGA Hardware User Guide, v2022A-SP2

Extension Board Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

proFPGA Hardware User Guide, v2022A-SP2 37

Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

38 proFPGA Hardware User Guide, v2022A-SP2

Order Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754

proFPGA Hardware User Guide, v2022A-SP2 39

FPGA Extension Site Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

40 proFPGA Hardware User Guide, v2022A-SP2

SATA Extension Board (EB-PDS-SATA-R4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

proFPGA Hardware User Guide, v2022A-SP2 41

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888