ANNA UNIVERSITY: CHENNAI – 600 025

B.E. / B. Tech Degree Practical Examinations NOV/ DEC – 2022

COLLEGE CODE & NAME : 9112 & MAHATH AMMA INSTITUTE OF ENGINEERING AND
TECHNOLOGY
SUB. CODE & NAME : EC8361 ANALOG AND DIGITAL CIRCUITS LABORATORY

BRANCH CODE & NAME : 106 - B.E. ELECTRONICS AND COMMUNICATION ENGINEERING

YEAR & SEM. : II / III

DATE & SESSION : 23-01-2023 & FN ,11:30:00
SYLLABUS

LIST OF ANALOG EXPERIMENTS

1. Design of Regulated Power supplies
2. Frequency Response of CE, CB, CC and CS amplifiers
3. Darlington Amplifier
4. Differential Amplifiers - Transfer characteristics, CMRR Measurement
5. Cascode and Cascade amplifiers
6. Determination of bandwidth of single stage and multistage amplifiers
7. Analysis of BJT with Fixed bias and Voltage divider bias using Spice
8. Analysis of FET, MOSFET with fixed bias, self-bias and voltage divider bias using simulation software like
Spice
9. Analysis of Cascode and Cascade amplifiers using Spice
10. Analysis of Frequency Response of BJT and FET using Spice
LIST OF DIGITAL EXPERIMENTS

1. Design and implementation of code converters using logic gates(i) BCD to excess-3 code and vice versa (ii)
Binary to gray and vice-versa
2. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
3. Design and implementation of Multiplexer and De-multiplexer using logic gates
4. Design and implementation of encoder and decoder using logic gates
5. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
6. Design and implementation of 3-bit synchronous up/down counter
 ANNA UNIVERSITY: CHENNAI – 600 025

B.E. / B. Tech Degree Practical Examinations NOV/ DEC – 2022

COLLEGE CODE & NAME : 9112 & MAHATH AMMA INSTITUTE OF ENGINEERING AND
TECHNOLOGY
SUB. CODE & NAME : EC8361 ANALOG AND DIGITAL CIRCUITS LABORATORY

BRANCH CODE & NAME : 106 - B.E. ELECTRONICS AND COMMUNICATION ENGINEERING

YEAR & SEM. : II / III

DATE & SESSION : 23-01-2023 & FN ,11:30:00
MARK ALLOCATION

1. Aim/Principle/Apparatus 25
required/Procedure

2. Tabulation/Circuit/Program/Drawing 30

3. Calculation & Results 25

4. Viva-Voce 10

5. Record 10

TOTAL 100

Internal Examiner External Examiner

 ANNA UNIVERSITY: CHENNAI – 600 025

B.E. / B. Tech Degree Practical Examinations NOV/ DEC – 2022

COLLEGE CODE & NAME : 9112 & MAHATH AMMA INSTITUTE OF ENGINEERING AND
TECHNOLOGY
SUB. CODE & NAME : EC8361 ANALOG AND DIGITAL CIRCUITS LABORATORY

BRANCH CODE & NAME : 106 - B.E. ELECTRONICS AND COMMUNICATION ENGINEERING

YEAR & SEM. : II / III

DATE & SESSION : 23-01-2023 & FN ,11:30:00
QUESTION SET

Internal Examiner External Examiner

 ANNA UNIVERSITY: CHENNAI – 600 025
B.E. / B. Tech Degree Practical Examinations NOV/ DEC – 2022
COLLEGE CODE & NAME : 9112 & MAHATH AMMA INSTITUTE OF ENGINEERING AND
TECHNOLOGY
SUB. CODE & NAME : EC8361 ANALOG AND DIGITAL CIRCUITS LABORATORY
BRANCH CODE & NAME : 106 - B.E. ELECTRONICS AND COMMUNICATION ENGINEERING
YEAR & SEM. : II / III
DATE & SESSION : 23-01-2023 & FN ,11:30:00
MARK STATEMENT
VIVA TOTAL
S.NO REG.NUMBER NAME OF THE STUDENT MARKS MARKS
1 911220106001 KANNAN K

2 911220106302 ASHOK KUMAR A

3 911220106303 DEEPAKALEX J

4 911220106305 KALAIVANI P

5 911220106306 KESAVARTHINI P

6 911220106307 KUMARESAN P

7 911220106308 MAHABOOB HUSSAIN S

8 911220106312 MURALI K

9 911220106314 NITHISHKUMAR S

10 911220106315 PRABAKARAN N

11 911220106317 PREMCHANDAR SP

12 911220106318 RAJESH S

13 911220106319 RAMESHKANNAN R

14 911220106323 SHANMUGAPRIYA M

15 911220106325 STALIN S

16 911220106328 THAMARAIPRIYA K

17 911220106331 VIGNESHRAJA S

18 911219106301 DANIEL S

19 911219106302 GOMATHI PL

20 911219106303 JANSI P

21 911219106305 SELVARAJ S

Internal Examiner External Examiner

 ANNA UNIVERSITY: CHENNAI – 600 025
B.E. / B. Tech Degree Practical Examinations NOV/ DEC – 2022
COLLEGE CODE & NAME : 9112 & MAHATH AMMA INSTITUTE OF ENGINEERING AND
TECHNOLOGY
SUB. CODE & NAME : EC8361 ANALOG AND DIGITAL CIRCUITS LABORATORY
BRANCH CODE & NAME : 106 - B.E. ELECTRONICS AND COMMUNICATION ENGINEERING
YEAR & SEM. : II / III
DATE & SESSION : 23-01-2023 & FN ,11:30:00
LAB SCHEDULE

NAME OF THE DATE &

S.NO DEPARTMENT CANDIDATES
LAB SESSION
911220106001,911220106302
911220106303,
911220106305 TO 911220106308,
911220106312, 911220106314,
106 - B.E.
EC8361 ANALOG
ELECTRONICS 23-01-2023 911220106315, 911220106317 TO
AND DIGITAL
1 AND &FN
CIRCUITS 911220106319,
COMMUNICATION 11:30:00
LABORATORY
ENGINEERING 911220106323 ,911220106325
911220106328,911220106331
911219106301 TO 911219106303
911219106305

Internal Examiner External Examiner

 ANNA UNIVERSITY: CHENNAI – 600 025
B.E. / B. Tech Degree Practical Examinations NOV/ DEC – 2022
COLLEGE CODE & NAME : 9112 & MAHATH AMMA INSTITUTE OF ENGINEERING AND
TECHNOLOGY
SUB. CODE & NAME : EC8361 ANALOG AND DIGITAL CIRCUITS LABORATORY
BRANCH CODE & NAME : 106 - B.E. ELECTRONICS AND COMMUNICATION ENGINEERING
YEAR & SEM. : II / III
DATE & SESSION : 23-01-2023 & FN ,11:30:00
LAB SCHEDULE

S.N NAME OF DATE &

DEPARTMENT CANDIDATES
O THE LAB SESSION
911220106001,911220106302
911220106303,
911220106305 TO 911220106308,

106 - B.E. EC8361 911220106312, 911220106314,

ELECTRONICS ANALOG AND 23-06-2022 911220106315,
1 AND DIGITAL &FN
COMMUNICATION CIRCUITS 11:30:00 911220106317 TO 911220106319,
ENGINEERING LABORATORY
911220106323 ,911220106325
911220106328,911220106331
911219106301 TO 911219106303
911219106305

Internal Examiner HOD

1. Construct a Common Emitter BJT amplifier using voltage divider bias and determine the
frequency response. Calculate the bandwidth from the obtained frequency response.
(100)

2. Construct a Common Collector BJT amplifier using voltage divider bias and determine the
frequency response. Calculate the bandwidth from the obtained frequency response.
(100)

3. Construct a Common Source FET amplifier and determine the frequency response. Calculate
the bandwidth from the obtained frequency response.
(100)

4. Construct a Darlington amplifier using BJT and determine the frequency response. Calculate
the bandwidth from the obtained frequency response. (100)

5. Construct a Differential amplifier using BJT and determine the common mode gain, differential
mode gain and CMRR. (100)

6. Construct a Cascode amplifier and determine the frequency response. Calculate the bandwidth
from the obtained frequency response. (100)

7. Construct a Cascade amplifier and determine the frequency response. Calculate the bandwidth
from the obtained frequency response. (100)

8. Construct a Single stage amplifier and determine the frequency response. Calculate the
bandwidth from the obtained frequency response. (100)

9. Construct a multistage amplifier and determine the frequency response. Calculate the
bandwidth from the obtained frequency response. (100)

10. Design and implement BCD to Excess-3 code converter using logic gates and verify its truth
table. (100)

11. Design and implement Excess-3 to BCD code converter using logic gates and verify its truth
table. (100)
12. Design and implement binary to gray code converter and gray to binary code converter using
logic gates and verify its truth table. (100)

13. Design and implement 4-bit binary Adder / Subtractor using IC 7483. (100)

14. Design and implement BCD adder using IC 7483. (100)

15. Design and implement 4x2 encoder and 2x4 decoder using logic gates and verify its truth table.

(100)

16. Design and implement 4x1 multiplexer and 1x4 de-multiplexer using logic gates and verify its
truth table. (100)

17. Design and construct a 4 – bit mod-12 ripple counter and verify its truth table. (100)

18. Design and construct a 4 – bit mod-10 ripple counter and verify its truth table. (100)

19. Construct a 3-bit synchronous up / down counter and verify its truth table. (100)

20. Design and implement binary to gray code converter and vice versa using logic gates and verify
its truth table. (100)

21. Construct regulated power supply for the DC voltage of 12V. (100)

Simulate BJT amplifier with the following biasing using spice. (100)
22.
a. Fixed bias

b. Voltage divider bias

c. Self -bias

Simulate Common source-FET amplifier with the following biasing using spice. (100)
23.
a. Fixed bias

b. Voltage divider bias

c. Self -bias.
 Simulate Common source MOSFET amplifier with the following biasing using spice. (100)
24.

a. Fixed bias

b. Voltage divider bias

c. Self -bias.

Simulate Cascode and Cascade BJT amplifier using spice. (100)

25.