Lecture 16

Prof. Eros Pasero

HC00 data sheet

 ESD Protection? Human Body Model? Machine

Model? Charge Device Model?
 Latch Up?

2023 Electronic System Engineering™ - Prof. Eros Pasero 2

 Electro Static Discharge (ESD)
 Static Energy
 Triboelectric effect
 ESD definition
 ESD Failures
 ESD Studies
 Standard Models:
 Human Body Model
 Machine Model
 Charged Device Model

2023 Electronic System Engineering™ - Prof. Eros Pasero 3

Static energy
 It’s an electric charge coming from
an electrons imbalance on the
surface of an object
 When 2 objects have different
electrical potentials you have a fast
charge transfer when the 2 objects
are in contact
 Static electricity creation =>
triboelectric effect

2023 Electronic System Engineering™ - Prof. Eros Pasero 4

Parameters influencing electrical
discharge
 Environment conditions: humidity…
 Scrub speed
 Contact area
 Material:
 Positive charge: nylon, hairs, fur….
 Negative charge: teflon, silicon, gold….

2023 Electronic System Engineering™ - Prof. Eros Pasero 5

Humidity

2023 Electronic System Engineering™ - Prof. Eros Pasero 6

 ESD in Ics: definition
 ESD is a transient discharge of static charge
that arises from either human handling or a
machine contact.
 Although ESD is the result of a static
potential in a charged object, the energy
dissipated and damages made are mainly
due to the current flowing through ICs
during discharge.
2023 Electronic System Engineering™ - Prof. Eros Pasero 7
ESD
Becomes a problem when current densities closely
approach or exceed 500,000 A/cm2
For sub-micron width leads, this translates to
currents of only a few milliamps
Slow wearout of metallization caused by excessive
current densities
=>Electromigration

2023 Electronic System Engineering™ - Prof. Eros Pasero 8

Difficult to recognize
 IC sometime don’t work: transient stress? No, ESD
 Random problems, infant mortality, production
defects? NO, ESD
 Different problems not immediately after the
discharge
 You don’t have the right instrumentation to check the
problem
 It’s economically profitable to replace the part!

2023 Electronic System Engineering™ - Prof. Eros Pasero 9

Failures

2023 Electronic System Engineering™ - Prof. Eros Pasero 10

 ESD damages
 pn-junction may melt.
 Gate oxide may have void formation.
 Metal interconnects & Vias may melt or
vaporization, leading to shorts or opens.
 Gate-oxide breakdown is another form of
ESD damage.

2023 Electronic System Engineering™ - Prof. Eros Pasero 11

 ESD failures in Ics
Gate oxide damage Junction breakdown

Metal/via damage

2023 Electronic System Engineering™ - Prof. Eros Pasero 12

 ESD studies

2023 Electronic System Engineering™ - Prof. Eros Pasero 13

 Why is ESD Critical ?
gate oxide thickness junction depth

The level of ESD stress, however, does not scale down

with the technology!

2023 Electronic System Engineering™ - Prof. Eros Pasero 14

Device: protection circuits

2023 Electronic System Engineering™ - Prof. Eros Pasero 15

 Input:

Ci ≤ 5 pF and Ri = 1012 Ω High Zi

Electro static charges

Clamp diodes: Vi > Vcc + Vth CLAMP

Vi < GND + Vth CLAMP

Rs ≈250 Ω Current limit when high Vi is applied to inputs

2023 Electronic System Engineering™ - Prof. Eros Pasero 16

 Xoxyde < 500 Å (1 Å = 10-10 m => Xox = 50 nm)
Dielectric strenght = 107 V/cm => 1 V/nm
=> Break down when Vgs>50V

22 nm technology
 Gate length: 22 nm
 Oxide Thickness: 0.8 nm (SiO2)=> higher leakage I:
 High K dielectrics larger thickness with small Cox
 Junction depth: 20 nm

2023 Electronic System Engineering™ - Prof. Eros Pasero 17

Principle Sources of ESD in ICs
Human Handling
 A person walking on a synthetic floor can accumulate
up to 20 kV. (Icharge = 1-10 A @ ∆t =10-100 ns).This
voltage is discharged when the person touches an
object that is sufficiently at ground.
Test and Handling Systems
 Equipment can accumulate static charge due to
improper grounding. The charge is transmitted
through ICs when it is picked up for placement in test
sockets.
2023 Electronic System Engineering™ - Prof. Eros Pasero 18
Principle Sources of ESD in ICs
IC Itself is Charged During Transport / Contact
With Charged Objects:
 ICs remain charged until they come into contact
with a grounded surface (large metal plates /test
sockets). Charge is discharged through the pins of
ICs. Large currents in the internal interconnects
can result in high voltage inside the devices which
can cause damage to thin dielectrics and
insulators.

2023 Electronic System Engineering™ - Prof. Eros Pasero 19

Modelling: 3 Standard models
 HBM: Human Body Model
 MM: machine Model
 CDM: Charged Device Model

2023 Electronic System Engineering™ - Prof. Eros Pasero 20

 MIL-STD-883 Method 3015 - ESD STM5.1: Electrostatic Discharge
Sensitivity Testing -- Human Body Model

2023 Electronic System Engineering™ - Prof. Eros Pasero 21

2023 Electronic System Engineering™ - Prof. Eros Pasero 22
 Resistance in a Wrist Strap System

2023 Electronic System Engineering™ - Prof. Eros Pasero 23

 Anti-Static Products

2023 Electronic System Engineering™ - Prof. Eros Pasero 24

 Real Model

2023 Electronic System Engineering™ - Prof. Eros Pasero 25

 Destruction mechanisms
1. Short transition time: tr < 1 ns. The protection
circuit is not still active and the discharge
power can’t be dissipated.
2. High peak currents Ipeak > 1.5 A
3. High discharge energy

2023 Electronic System Engineering™ - Prof. Eros Pasero 26

How much energy is at stake?
 You must dissipate:

E ≈ ½ V2 C
V = 2000V e C = 100 pF
=> E= 20 mJ

2023 Electronic System Engineering™ - Prof. Eros Pasero 27

 ESD STM5.2: Electrostatic Discharge Sensitivity Testing -- Machine
Model
2023 Electronic System Engineering™ - Prof. Eros Pasero 28
 Integrated circuit packaging

2023 Electronic System Engineering™ - Prof. Eros Pasero 29

 Discharge Energy
E = ½ V2 C = ½ 5002 200 10-12 = 25 µJ
L = 500 nH depends on the length of
wire and series inductance of the wires
utilized

2023 Electronic System Engineering™ - Prof. Eros Pasero 30

 V = .5 – 2 kV

ESD STM5.3.1: Electrostatic Discharge

Sensitivity Testing - Charged Device Model Metal Plate

2023 Electronic System Engineering™ - Prof. Eros Pasero 31

 Pick place machine
Surface mount component feeder

2023 Electronic System Engineering™ - Prof. Eros Pasero 32

CDM test

2023 Electronic System Engineering™ - Prof. Eros Pasero 33

Test wave forms

2023 Electronic System Engineering™ - Prof. Eros Pasero 34

 E= ½ V2 C =0.5 10002 1000 10-12 = 0.5 mWs (or mJ)

2023 Electronic System Engineering™ - Prof. Eros Pasero 35

 Temperature growth

CS = 1.631 Ws/Kcm3 silicon thermal capacity

Si fusion temperature = 1600 °C; Al fusion temperature << 1600 °C
>> Al melts and spreads into Si => the protection circuit becomes a
short circuit
2023 Electronic System Engineering™ - Prof. Eros Pasero 36
JEDEC STANDARD
 JESD22-A115C (Revision of JESD22-A115B, March 2010)
 Electrostatic Discharge (ESD) Sensitivity Testing,
Machine Model (MM)
About JEDEC
JEDEC brings manufacturers and suppliers together to
participate in more than 50 committees and
subcommittees, with the mission to create standards to
meet the diverse technical and developmental needs of
the industry.

2023 Electronic System Engineering™ - Prof. Eros Pasero 37

2023 Electronic System Engineering™ - Prof. Eros Pasero 38
2023 Electronic System Engineering™ - Prof. Eros Pasero 39
2023 Electronic System Engineering™ - Prof. Eros Pasero 40
Reference regulations

2023 Electronic System Engineering™ - Prof. Eros Pasero 41

ECE – R10 Rev. 5
6.10.4
• Electrostatic discharge
– For vehicles fitted with tyres, the vehicle body/chassis
can be considered to be an electrically isolated structure.
Significant electrostatic forces in relation to the vehicle's
external environment only occur at the moment of
occupant entry into or exit from the vehicle. As the
vehicle is stationary at these moments, no type approval
test for electrostatic discharge is deemed necessary.

2023 Electronic System Engineering™ - Prof. Eros Pasero 42

 IEC 61000-4-2 (EN 61000-4-2)
 The EUT is subjected to three types of discharge.
Direct contact discharge is preferred either directly to
the EUT or indirectly through vertical or horizontal
coupling planes. Air discharge is used where direct
contact cannot be applied.

2023 Electronic System Engineering™ - Prof. Eros Pasero 43

Environmental conditions

2023 Electronic System Engineering™ - Prof. Eros Pasero 44

Generator

2023 Electronic System Engineering™ - Prof. Eros Pasero 45

Discharge
AD CD

2023 Electronic System Engineering™ - Prof. Eros Pasero 46

Discharge Networks

2023 Electronic System Engineering™ - Prof. Eros Pasero 47

Evaluation
 No change, according to manufacturer specifications
 Temporary loss of function, ending after the test
 Temporary loss of function requiring operator
 loss of function not recoverable

2023 Electronic System Engineering™ - Prof. Eros Pasero 48

How to protect your inputs?
 DVIULC6-4SC6Y: Automotive ultralow capacitance
ESD protection
 4-line ESD protection (IEC 61000-4-2)
DVI ports up to 1.65 Gb/s
HDMI ports up to 1.65 Gb/s
IDB 1394
USB 2.0 ports up to 480 Mb/s (high speed),
backwards compatible with USB1.1 low and full
speed
Ethernet port: 10/100/1000 Mb/s
SIM card protection
Video line protection

2023 Electronic System Engineering™ - Prof. Eros Pasero 49

 Silicon Controlled Rectifier
pnpn

A
A

K IG → Ic2 → Ic1 → Ib2 → Self

Distruction
2023 Electronic System Engineering™ - Prof. Eros Pasero 50
Thyristor
 100 A 1200 V SCR
 four-layered, three terminal semiconducting device,
with each layer consisting of alternately N-type or P-
type material, for example P-N-P-N.
 arc welding machines

2023 Electronic System Engineering™ - Prof. Eros Pasero 51

TRIAC
 Triode for Alternating Current
 bidirectional triode thyristor
 The bidirectionality makes TRIACs very
convenient switches for alternating
current circuits,
 Light dimmers

2023 Electronic System Engineering™ - Prof. Eros Pasero 52

Latchup in Bulk CMOS
Electrostatic Discharge stress can cause
latch-up by injecting minority carriers from the
clamping device in the protection circuit into
either the substrate or the well.

β1β2 >1 =latchup

2023 Electronic System Engineering™ - Prof. Eros Pasero 53

2023 Electronic System Engineering™ - Prof. Eros Pasero 54
 Shunted Rs and Rw

2023 Electronic System Engineering™ - Prof. Eros Pasero 55

2023 Electronic System Engineering™ - Prof. Eros Pasero 56
2023 Electronic System Engineering™ - Prof. Eros Pasero 57
2023 Electronic System Engineering™ - Prof. Eros Pasero 58
2023 Electronic System Engineering™ - Prof. Eros Pasero 59
2023 Electronic System Engineering™ - Prof. Eros Pasero 60
Buried contacts
 The buried contact is a
method to make direct
ohmic contact between
the polysilicon gate
material and the
junctions, in silicon-gate
integrated circuits.

2023 Electronic System Engineering™ - Prof. Eros Pasero 61

  The gate and source of a
depletion device can be
connected by a method
Butting contact known as butting contact.
 Here metal makes contact
to both the diffusion
forming the source of the
depletion transistor and to
the poly silicon forming
this device’s gate.
 Its advantage is that no
buried contact mask is
required and it avoids
associated processing.

2023 Electronic System Engineering™ - Prof. Eros Pasero 62

Preventing latchup: System approach
 Make sure power supplies are off before plugging a board:
signal pins can see surge voltages greater than 0.7 V
higher than Vdd
 Carefully protect electrostatic protection devices
associated with I/O pads with guard rings: Electrostatic
discharge can trigger latchup by means of the clamping
diodes which can inject minority carriers in the substrate
or well, potentially triggering latchup
 Radiations can generate electron-hole pairs which can
contribute to well or substrate currents
 Sudden transients on the power or ground bus (i.e. when
large numbers of transistors switch simultaneously)

2023 Electronic System Engineering™ - Prof. Eros Pasero 63

2023 Electronic System Engineering™ - Prof. Eros Pasero 64
2023 Electronic System Engineering™ - Prof. Eros Pasero 65