Synopsys Design Flow Tutorial

Lab 3: Physical Design. IC Compiler II

Objective
Learn how to compile the design with IC Compiler II and what kind of commands are needed for it.

Introduction
IC Compiler II is a single, convergent netlist-to-GDSII synthesis design tool for chip designers
developing very deep submicron designs. It takes as input a gate-level netlist, a detailed floorplan,
timing constraints, physical and timing libraries, and foundry-process data, and it generates as output
either a GDSII-format file of the layout.

IC Compiler II provides two user interfaces:

- Shell interface (icc2_shell)
The IC Compiler II command-line interface is used for scripts, batch mode, and push-button
operations.
- Graphical user interface (GUI)
The IC Compiler II graphical user interface is an advanced analysis and physical editing tool.

IC Compiler II

NDM .ndm
Fig.1.Input and output files of IC compiler II

The logic, timing, and power information of the cell is typically contained in a set of Synopsys database
(.db).

Tech file
A technology file provides technology-specific information, such as names and physical and electrical
characteristics of each metal layer and routing design rules. IC Compiler II uses the Milkyway design
library to access the technology information.

TluPlus
The parasitic attributes define the metal layer parasitics. In general, IC Compiler II gets the parasitic
information from the TLUPlus files rather than from the technology file.

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Simplified ICC II Design Flow

Invoke ICC II

IC Compiler II

Fig.2. Simplified IC Compiler II Design Flow

1. Start IC Compiler II graphical user interface (GUI) from work directory. To start the IC Compiler II
command-line interface, enter the following command at the UNIX or Linux prompt:

%icc2_shell -gui

This opens the IC Compiler II top-level GUI window. (Fig. 1)

Fig.3. IC Compiler II Top-level GUI window

2. When IC Compiler II starts, it automatically reads “.synopsys_dc.setup” file from the current
directory. In this lab this file is located in the work directory. Start IC Compiler II from that
directory to automatically read the file and set up the libraries. To check whether the libraries
were set, open File> Setup > Application Setup menu (Fig. 4).

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 Fig.4. Application setup window

If these values are not set, either exit and start IC Compiler II from “work” directory or fill in the files
manually.

In IC Compiler II, specify the .db files to use for the design by setting target_library, and link_library
variables.
target_library variable specifies the .db library files containing the logic cells that can be used for
optimization, for example, different NAND gates having various areas, drive strengths, delays, and
power usage.
link_library variable specifies the .db libraries containing all the logic cells that can be used to resolve
hierarchical references in the design during execution of the link command.

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Design flow
3.1 Create New Design Model library

To create the NDM design library, choose File > Create Library. The Create Library dialog box
appears. (Fig.5)

Fig.5. Create library window

The create_mw_lib command and the Create Library dialog box have options to specify the name
of the new NDM library, the name of the associated technology file, the names of the associated NDM
reference libraries, and the bus naming style.

3.2 Set TLU+ files

Set TLUPlus file paths. TLUPlus is a binary table that stores RC coefficients. The TLUPlus models
enable accurate RC extraction results by including the effects of width, space, density, and
temperature on the resistance coefficients. Set it using View > Map > Rail Parasitics (Fig.6).

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 Fig.6. Set TLU+ window

Type or browse for the map file in the “Map file” text box. Type or browse for the maximum and
minimum TLUPlus model files.

3.3 Import Design

Read the Verilog file for the design by choosing Task > Create Block > Create Design Library and
specifying the Verilog netlist file, which is a gate-level design in one or more files (Fig.7 and Fig .8).

Fig.7. Import design window

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 Fig.8. Design view after importing

3.4 Read constraints

To read constraints, go to Task > Timing > Mode.

Setup is completed.

After setting up design in IC Compiler II, do the following steps:

4.1. Initialize floorplan,

4.2. Create rectangular rings
4.3. Create power straps, Route standard cells
4.4. Placement
4.5. CTS (Clock Tree Synthesis)
4.6. Routing
4.7. Finishing.

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4.1. Initialize floorplan

Floorplan information includes the core area, top-level ports, and placement sites. To floorplan the
design, choose Floorplan>Initialize Floorplan (Fig.8 and Fig.9).

Specify the control parameters.

Indicate the method which specifies the size of the core area:
1. Aspect ratio – A ratio of height divided by width (the default)
2. Width & height – The exact width and height
3. Row number – A number of rows
4. Boundary – A fixed size according to the boundary defined in design planning

Fig.9. Initialize floorplan window

Fig.10. Design view after initialize_floorplanning

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4.2. Create power straps

After creation rectangular rings the straps are automatically connected to the closest power and
ground ring at, or beyond, both ends of the straps.

The create_pg_strap command creates power straps in a design. Use a few wide straps rather
than many thin straps to improve the placement quality and decrease the placement runtime.

The same as from Menu bar choose Task > Design Planning > Ring/Hard Macro/ Std cell Pattern
(Fig.13 and Fig.14).

Fig.13. Create object tool window

Fig.14. Design view after creation power straps

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4.3. Placement

place_opt - command performs simulation placement, routing, and optimization on the current
design. During the placement phase this design's standard cells have been automatically placed in
horizontal placement rows.

To run placement, choose Placement > Core Placement and Optimization Task > Placement >
Placement > Create Placement(Fig.15 and Fig 16).
The Core Placement and Optimization dialog box appears. Select “Power optimization.”

Fig.15. Core placement and optimization window

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 Fig.16. Design view after Core Placement and Optimization

4.4. Clock tree synthesis

During clock tree synthesis, IC Compiler II builds clock trees that meet the clock tree design rule
constraints while balancing the loads and minimizing the clock skew. IC Compiler II fixes the
placement of the clock sinks, performs incremental logic and placement optimization, and fixes the
placement of both the buffers and registers on the clock tree. The clock_opt command performs
clock tree synthesis, routing of clock nets, extraction, optimization, and optionally hold-time violation
fixing on the current design. If clock tree synthesis fails, or the routing of clock nets fail, the command
returns with a value of 0.

To perform clock tree synthesis and optimization, use the clock_opt command or choose CTS >
Core CTS and Optimization in the GUI. (Fig.17 and Fig.18). The Core CTS and Optimization dialog
box appears and select route clock cells. To perform clock tree synthesis choose Task > Clock tree >
Chack Clock Trees

Fig.17. Core CTS and optimization window

Fig.18. Design view after Core CTS and Optimization

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4.5. Pre-route standard cells

Connect power and ground pins in standard cells to the straps and rings and connect power and
ground rails in the standard cells. To make sure the global router can recognize the routing
obstruction, Route the standard cells before performing global routing.

The route_auto command connects power and ground pins in the standard cells to the power and
ground rings or straps, and connects power and ground rails in the standard cells.

The same as from Menu bar choose Task > Routing> Create Routing Blockage (Fig. 19 and
Fig.20).

Fig.19. Route standard cells window

Fig.20. Design view after Routing Standard Cells

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4.6. Routing

The route_opt this command performs simultaneous routing and postroute optimization on the
current design. The output of this command is a postroute optimized design.
Finally, for routing the design choose Route >Core Routing and Optimization. The core routing and
optimization dialog box appears (Fig.21 and Fig. 22).

Fig.21. Core routing and optimization window

ICC have route_eco command. This command performs routing for the broken nets. It runs global
route, track assignment and detail route.

Fig.22. Design view after core routing and optimization

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4.7. Finishing

create_stdcell_filler this command fills empty spaces in standard cell rows with instances of
master filler cells in the library (Fig.23).

Fig.23. Design view after insert fillers

4.9. Design Rule Check

To check DRC in IC Compiler II external tools are used such as IC Validator.

To do this first Physical Signoff Options should be set. To do this go to Signoff > Set Physical
Signoff Options menu, the setup window will open (Fig. 24). It should be set up with tool name,
runset and map file. To check DRC choose Verification > Signoff DRC.

Fig.24. Signoff DRC setup window

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4.9. Layout versus Schematic (LVS) Check

For check LVS errors choose Verification > LVS (Fig.25).

Fig.25. Check LVS window

Other features.

IC Compiler II can different data in form of overlay maps. For example, choose View> Map mode,
then in the opened sidebar select Cell Density. Then click Reload ( Fig.26).

Fig.26.Check Leakage Power Density window

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4.10. Writing results

Write the design in gate-level Verilog: Task > Design Planning > Write Floorplan & Verilog >
Verilog (Fig. 27).

Fig.27. Write verilog format box

4.11. Export parasitics

Extract parasitics using File > Export > Write Parasitics menu, in the opened dialog press OK. To
write the design with Standard Parasitic Exchange Format (SPEF) from Menu bar choose File >
Export > Write Parasitics (Fig. 28).

Fig.28. Write .spef format box

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4.12. Export Stream (GDSII)

To write the data in specified library to a file in GDS format choose File > Export > Write Stream (Fig.
26).

Fig.29. Write .gds format box

In this design output results stored in ../results/ directory.

To exit ICC II select File > Close Design, then File > Close Library then File > Exit.

Use script created carry out all of these operations using commands. There is a flow.tcl script in
scripts directory. To source the script write in newly opened ICC window. Explore script to learn
commands

Icc2_shell> source ../scripts/flow.tcl

Report

Report must include:

1. Gate level Verilog
2. Stream
3. SPEF file
4. Screenshots of placed, routed designs as well as DRC/LVS results.

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