Riverside TR MB LA-J261PR10 A00 20200327

5 4 3 2 1
COMPAL CONFIDENTIAL Riverside 13"14" UMA(TR)

MODEL NAME :FDX40
Comet Lake U42 V1
PCB NO :LA-J261P
2020-03-27
D D
BOM P/N :431AJS31LXX

REV : 1.0 (A00)
@ : Nopop Component AC@ : Intel 9560 WLAN Solder Down Component
EMI@ : EMI Component AX@ : Intel AX201 WLAN Solder Down Component
@EMI@ : EMI Nopop Component AXN@ : Intel AX201(N) WLAN Solder Down
ESD@ : ESDComponent SDP@ : Single-Die Package DRAM Component
@ESD@ : ESD Nopop Component DDP@ : Dual-Die Package DRAM Component
C
RF@ : RF Component S4G@ : Samsung 4GB DRAM Component C
@RF@ : RF Nopop Component S8G@ : Samsung 8GB DRAM Component

DS3@ : Deep sleep support S16G@ : Samsung 16GB DRAM Component
NDS3@ : NDS3 support S32G@ : Samsung 32GB DRAM Component
@NDS3@ : NDS3 Nopop Component H4G@ : Hynix 4GB DRAM Component
CXDP@ : XDP Component H8G@ : Hynix 8GB DRAM Component
RTD3@ : RTD3 Component H16G@ : Hynix 16GB DRAM Component
B
@RTD3@ : RTD3 Nopop Component H32G@ : Hynix 32GB DRAM Component B
NRTD3@ : RTD3 Component M4G@ : Micron 4GB DRAM Component

VPRO@ : vPro Component M4GN@ : Micron New 4GB DRAM Component
NVPRO@ : Non-vPro Component M8G@ : Micron 8GB DRAM Component
JUMP@ : Jump solder and short M8GN@ : Micron New 8GB DRAM Component
Layout Dell logo
@JUMP@ : Jump no solder M16G@ : Micron 16GB DRAM Component
5107ES@ : 5107 ES Component M16GN@ : Micron New 16GB DRAM Component
A 5107NES@ : 5107 non-ES Component M32G@ : Micron 32GB DRAM Component A
CONN@ : Connector Component

MB PCB
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Part Number Description
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
COPYRIGHT 2019
ALL RIGHT RESERVED DAB0005M010 PCB 2UW LA-J261P REV1 MB TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Cover Sheet
REV:A00 Size Document Number Rev
PWB:CP2JJ Power CKT :RIVERSIDE_PVT_POWER_200305 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
GPIO map : X11_CML_U_CSLP GPIO map Rev0.7_20190919
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-J261p
Date: Friday, March 27, 2020 Sheet 1 of 106
5 4 3 2 1
5 4 3 2 1
Riverside TR Block Diagram Memory Down
Memory BUS (DDR4)

DDR4 on Board
P23, P24
DDR4 2667MHz for CML-U v1
D
2Gx16 8//1Gx16 8//512Mx16 8//512Mx16 4 LCD Touch
D
I2C[0] P38
4-Lane eDP1.4 EDP
EDP CONN USB2.0[6]
P38 Camera
P38 Trough eDP Cable
HDMI 2.0 HDMI LSPCON DP
CONN P40 PS186 P40 PCIE[5][6][7][8]
USB2.0[3] SLGC55544BVTR USB2.0[3]_PS
USB POWER SHARE
Left side rear TBT
TR-DP
DDI[1] INTEL
TypeC P45 DDI[2]
USB USB3.0 Conn
USB3.0[2]
PS(Ext Port 1) Right side rear
TBT USB3 Repeater
Left side front P42-43 PS8719B
TypeC P46 CML-U v1 MCP USB2.0[4]
USB3.0 Conn
USB3.0[3] (Ext Port 2) Right side front
USB3 Repeater
USB2.0/SMBus PD Solution PS8719B Only Riverside 14" IO board
TPS65988P44 USB2.0/SMBus
IO/B, trough Beam CONN
I2C Accelerometer
C
PCIE[9] PCIE[12] PCIE[10] (MB) P66 LED/B C
Micro SIM CNVi Magnetometer/

Card reader
M.2,3042 Key B WLAN Module Down
PAGE 6~19
E-Compass Battery LED
RTS5242 P70
WWAN/LTE WLAN+BT/CNVi
eSIM P52 Place on Sensor/B
Accelerometer &
SD4.0 USB2.0[7] USB2.0[10] Gyroscope Breath LED
P70
USB3.0[4]
IO/B, trough Beam CONN GMR Sensor
SAR Sensor
Semtech SX9324
POWER ON/OFF SW
TOP
USB2.0[1]/[2] from PCH IO/B, trough Beam CONN
Left side rear DEMUX INT.Speaker
ESPI
SPI
TypeC TS3DS10224 SMBus from EC
SATA[2]/PCIE[16][15][14][13] USH CONN
BOT P66
HD Audio I/F HDA Codec Universal Jack

SPI(G3 shared Mode)
ALC3254 CPU&PCH XDP Port
TOP P79
B B
Left side front DEMUX AUTOMATIC POWER

GD25B256DYIG
TypeC TS3DS10224 P8 SWITCH(APS) P79
BOT Dig. MIC
256Mb 4K sector WSON8 M.2 2280 P38
SSD Conn P68
TPM2.0 Trough eDP Cable DC/DC Interface
DEMUX for DOCK FW update support ST-ST33HTPH2032AHC1 P78
P66
Place on 6mm IR camera module
BC link
KB/TP CONN
P63
Smart Card TDA8034HN SMSC KBC ALS Sensor
USH TPM1.2 USB2.0[8] MEC5107
BCM58202 PWM FAN CONN
P58-59
RFID/NFC SPI P77 P-Sensor
Fingerprint SPI
CONN V-Tree for Service
USH board P58
A Fingerprint FP-USB2.0 A
MOCV P66
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block Diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
POWER STATES USB3.0 Gbe PCIE SATA DESTINATION USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS USB3.0-1 PCIE-1 N/A 1 Type-C Port1
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State
USB3.0-2 PCIE-2 JUSB1-->Right Rear 2 Type-C Port2
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON USB3.0-3 PCIE-3 JUSB2-->Right Front 3 JUSB1-->Right Rear
D
S0ix/Moff LOW HIGH HIGH HIGH ON ON ON OFF OFF
USB3.0-4 PCIE-4 M.2 3042(LTE) 4 JUSB2-->Right Front D
USB3.0-5 PCIE-5 5 NA
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
USB3.0-6 PCIE-6 6 Camera
Titan Ridge - DP
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF PCIE-7 7 M.2 3042(WWAN)
S0ix (Suspend to RAM) / M-OFF HIGH HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-8 8 USH
PCIE-9 Card Reader 9 Reserved for FPR in PB
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCIE-10 Solder Down 1216(WLAN) 10 Solder Down 1216(BT)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF PCIE-11 SATA-0 N/A
PCIE-12 SATA-1 M.2 3042(LTE)
PCIE-13
C C
PCIE-14 M.2 2280 SSD

PCIE-15
PCIE-16 SATA-2
PM TABLE
+5V_ALW
+3.3V_ALW +3.3V_CV2 +5V_RUN
+3.3V_ALW_DSW +1.2V_MEM +3.3V_RUN
power
plane +3.3V_ALW_PCH +2.5V_MEM +0.6V_DDR_VTT
+RTC_CELL +1.05V_VCCSTG +1.8V_RUN
B B
+1.8V_PRIM +1.2V_RUN
+5V_ALW2
+3.3V_ALW2
State
+3.3V_RTC_LDO
+1.05V_PRIM
S0 ON ON ON
S0ix ON ON OFF
S5 S4/AC ON OFF OFF
S5 S4/AC doesn't exist ON OFF OFF
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Port assignment
Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
Converter Single Load switch@SIO_SLP_S3#

@SIO_SLP_S0# CPU PWR
SIO_SLP_S4# VCCSTG_EN
EM5201V PCH PWR
+1.2V_MEM (UZ27) +VCCPLL_OC
Peripheral Device PWR
SY8310 Single Load switch
(PU200) RUN_ON TYPE-C Power
0.6V_DDR_VTT_ON CPU_C10_GATE#
EM5201V GPU PWR
Type-C Type-C +0.6V_DDR_VTT (UZ19) +1.05V_VCCSTG
ADAPTER ADAPTER
Single Load switch@SIO_SLP_S3#
@SIO_SLP_S4#
RUN ON
EM5201V
(UZ21) +1.05V_VCCST
D D
PCH_PRIM_EN
(SIO_SLP_SUS#)
SY8386
(PU301) +1.05V_PRIM
Dual Load switch Dual Load switch
@PCH_3.3V_TS_EN
RUN_ON 3.3V_TS_EN
CHARGER EM5209VF LP2301
ISL9538C +PWR_SRC +5V_ALW (UZ47) +5V_RUN (QV8) TS_PWR_SRC
ALW ON
(PU700) SY8288C Dual Load switch
(PU102) AUD_PWR_EN
EM5209VF
+5V_ALW2 (@UZ5) +5V_RUN_AUDIO
USB charging port power switch
ALW ON
SY8288B USB_POWERSHARE_VBUS_EN
(PU100) +3.3V_RTC_LDO SLGC55544C
(UI3) +5V_USB_CHG_PWR
BATTERY Power switch
USB_PWR_EN1#
+3.3V_ALW2 SY6288D
(UI1) +USB_EX2_PWR
Power switch
USB_PWR_EN2#
+3.3V_ALW SY6288D
(UI2) +USB_EX3_PWR
C C
Converter
PCH_PRIM_EN
(SIO_SLP_SUS#)
SY8057C
(PU402) +1.05V_PRIM_CORE
Dual Load switch
PCH_PRIM_EN
RT8097A RUN_ON
(PU501) +1.8V_PRIM +1.8V_RUN

EM5209VF
(UZ43) WLAN_PWR_EN
+3.3V_WLAN
Converter
RUN_ON
SY8057D
(PU401) +0.95VS_VCCIO
DR.MOS DR.MOS P-MOSFET
ISL95880 FDMF3035 Dual Load switch

(PU602) FDMF3035 (PU610) PCH_PRIM_EN
(PU612) AO6405
FDMF3035 (QV1) +3.3V_ALW_PCH
EM5209VF
ISL95808 (PU613) (UZ3) P-MOSFET
(PU614) RUN_ON
LP2301A 3.3V_CAM_EN#
B
+3.3V_RUN (QZ1) +3.3V_CAM B
IMVP_VR_ON
IMVP_VR_ON
IMVP_VR_ON
EN_INVPWR
Dual Load switch

Dual Load switch
AUD_PWR_EN
EM5209VF
EM5209VF SIO_SLP_LAN#
(@UZ5) +3.3V_RUN_AUDIO
(UZ47) +3.3V_LAN
LDO
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC Power switch LCD_VCC_TEST_EN RUN_ON
ENVDD_PCH EM1109V
G524B1T11U (PU502) +1.2V_RUN
(UV24) +LCDVDD
TYPE-C
LDO
SIO_SLP_S4#
+5V_ALW +3.3V_VDD_PIC
EM1109BV +2.5V_MEM
TPS65987DDJ (PU503) for DDR4
(UT5)
+20V_TBTA_VBUS_1(5V~20V)
A A
Power rails
Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
+1.05V_PRIM
Timing Diagram for S5 to S0 mode VCCPRIM_1P0
VCCPRIM_CORE
PCH PWRBTN#
SIO_PWRBTN# 8
DCPDSW_1P0
Non-Deep VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~6
RSMRST#
PCH_RSMRST#
SIO_SLP_SUS#
7
VCCMPHYGT_1P0
VCCSRAM_1P0
SLP_SUS#
9
SIO_SLP_S5#
+1.0V_MPHYGT VCCAMPHYPLL_1P0 SLP_S5#
VCCAPLLEBB
SIO_SLP_S4#
9
SLP_S4# 10
SIO_SLP_S3#
+3.3V_ALW +3.3V_ALW_DSW SLP_S3#
4 VCCDSW_3P3
SLP_A#
SIO_SLP_A#
D
CPU
+3.3V_SPI 4 +3.3V_ALW_PCH SIO_SLP_LAN#
11 D
+VCC_CORE VCCHDA SLP_LAN#

VCCST_PWRGD VCCSPI
12 VCCST_PWRGD VCC VCCPRIM_3P3
VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+0.95VS_VCCIO VCCRTCPRIM RESET_OUT#
H_CPUPWRGD
VCCIO
5 +1.8V_PRIM SYS_PWROK
16
15 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK
PCH_PLTRST#
VCCGT
+RTC_CELL 14
+1.2V_MEM
17 PLTRST#
VDDQ
VCCRTC
VCCST_PWRGD
VCCST_PWRGD
12
0.6V_DDR_VTT_ON
VDDQC
VCCPLL_OC +1.05V_PRIM 5 +1.05V_PRIM_CORE
VCCPRIM_CORE
12 DDR_VTT_CNTL +1.05V_VCCST 11 SIO_SLP_S4# PROCPWRGD
H_CPUPWRGD
15
VCCST TPS22961 PCH_PLTRST#
VCCSTG
VCCPLL 17 PLTRST#
+VCC_SA
VCCSA
PCH_DPWROK
4 DSW_PWROK
+3.3V_ALW
ENVDD_PCH
+LCDVDD G524B1T11 EDP_VDDEN
+PWR_SRC
3
+1.05V_PRIM_CORE PCH_PRIM_EN +3.3V_ALW
5 SY8057C
SIO_SLP_LAN#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LAN#
C
5 +1.8V_PRIM
RT8097
+5V_RUN
C
@PCH_3.3V_TS_EN
+5V_TSP LP2301ALT1G GPP_B21

+PWR_SRC
5 3.3V_TS_EN (EC)
+3.3V_RUN
+1.05V_PRIM SY8386
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7
8
Power Button
EC 5107 1BAT 2AC

POWER_SW_IN#
11 SIO_SLP_WLAN#
11 ADAPTER
+PWR_SRC
+5V_ALW ALWON
+5V_ALW2
RUN_ON
EC 5107 SYV828C
+5V_ALW
+5V_RUN 1BAT
EM5209VF
+PWR_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SY8288B
+3.3V_ALW2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD_M2 +3.3V_ALW
+1.8V_PRIM
SIO_SLP_WLAN# SIO_PWRBTN#
B
EM5209VF +1.8V_RUN
8 B
PCH_RSMRST#
+PWR_SRC 7 +3.3V_ALW
SLP_WLAN#_GATE
NMOS PCH_DPWROK
+3.3V_ALW TLV62130 +0.95VS_VCCIO 6 3
EM5209VF
OR 11 +3.3V_ALW 9 SIO_SLP_SUS# PCH_PRIM_EN +3.3V_ALW_PCH 4
11 +3.3V_WLAN EM5209VF Gate
AUX_EN_WOWL
3.3V_WWAN_EN RESET_OUT#
EM5209VF +3.3V_WWAN 16
10 SIO_SLP_S4#
SIO_SLP_S5#
9
SIO_SLP_LAN#
11 SIO_SLP_S3# +PWR_SRC
SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
+PWR_SRC
12
+VCC_SA IMVP_VR_ON 10 +PWR_SRC
13 +VCC_CORE ISL95880 SIO_SLP_S4#
+VCC_GT +1.2V_MEM VDDQ
SY8310 VTT
DDR
+0.6V_DDR_VTT
PCH_PWROK
0.6V_DDR_VTT_ON
12
A
14 A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Sequence
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
1.0
Date : Friday, March 27, 2020 Sheet 5 of 106
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
CPU_DP2_HPD RC8771 2 100K_0201_5%
2 1 CPU_DP1_CTRL_CLK
@ RC503 2.2K_0201_5% CPU_DP1_HPD RC8631 2 100K_0201_5%
2 1 CPU_DP1_CTRL_DATA
RC178 2.2K_0201_5% EDP_HPD RC2 1 2 100K_0201_5%
2 1 CPU_DP2_CTRL_CLK
@ RC176
2
RC502
2.2K_0201_5%
1 CPU_DP2_CTRL_DATA
2.2K_0201_5%
CPU@
UC1A
For 4LANE EDP
AL5 AG4
D <42> CPU_DP1_N0 AL6 DDI1_TXN_0 EDP_TXN_0 AG3 EDP_TXN0 <38> D
<42> CPU_DP1_P0 AJ5 DDI1_TXP_0 EDP_TXP_0 AG2 EDP_TXP0 <38>
<42> CPU_DP1_N1 AJ6 DDI1_TXN_1 EDP_TXN_1 AG1 EDP_TXN1 <38>
<42> CPU_DP1_P1 AF6 DDI1_TXP_1 EDP_TXP_1 AJ4 EDP_TXP1 <38>
<42> CPU_DP1_N2 DDI1_TXN_2 EDP_TXN_2 EDP_TXN2 <38> +3.3V_ALW_PCH
AF5 EDP AJ3
<42> CPU_DP1_P2 AE5 DDI1_TXP_2 EDP_TXP_2 AJ2 EDP_TXP2 <38>
DDI1_TXN_3 EDP_TXN_3
2
<42> CPU_DP1_N3 AE6 AJ1 EDP_TXN3 <38>
<42> CPU_DP1_P3 DDI1_TXP_3 EDP_TXP_3 EDP_TXP3 <38> RC95
TR AC4 DDI 100K_0201_5%
<42> CPU_DP2_N0 AC3 DDI2_TXN_0 AH4
<42> CPU_DP2_P0 AC1 DDI2_TXP_0 EDP_AUX_N AH3 EDP_AUXN <38>
COMPENSATION PU FOR eDP
1
<42> CPU_DP2_N1 AC2 DDI2_TXN_1 EDP_AUX_P EDP_AUXP <38>
All VREF traces should CAD Note: <42> CPU_DP2_P1 DDI2_TXP_1
AE4 AM7 GPD7
have 10 mil trace width Trace width=5 mils <42> CPU_DP2_N2 AE3 DDI2_TXN_2 DISP_UTILS
<42> CPU_DP2_P2 AE1 DDI2_TXP_2 AC7
Isolation Spacing=25mil, <42> CPU_DP2_N3 DDI2_TXN_3 DDI1_AUX_N CPU_DP1_AUXN <42>
Reserved,External pull-up is required. Recommend 100 kohm.
This strap should sample HIGH. There should NOT be
AE2 AC6
Max length=100 mils. <42> CPU_DP2_P3 DDI2_TXP_3 DDI1_AUX_P AD4 CPU_DP1_AUXP <42> any on-board device driving it to opposite direction
CPU_DP2_AUXN <42> during strap sampling
DDI2_AUX_N AD3
GPP_E19 DDI2_AUX_P
DDI3_AUX_N
AG7 CPU_DP2_AUXP <42>
AG6
Display Port B Detected DISPLAY DDI3_AUX_P
SIDEBANDS
HIGH detected CN6 CPU_DP1_HPD +3.3V_ALW_PCH
LOW(DEFAULT) not detected GPP_E13/DDPB_HPD0/DISP_MISC0 CM6 CPU_DP2_HPD CPU_DP1_HPD <42>
WEAK INTERNAL PD 20K GPP_E14/DDPC_HPD1/DISP_MISC1 CP7 CPU_DP2_HPD <42>
GPP_E15/DPPD_HPD2/DISP_MISC2
2
CP6 HDMI_PD# <40>
GPP_E21 GPP_E16/DPPE_HPD3/DISP_MISC3
GPP_E17/EDP_HPD/DISP_MISC4
CM7 EDP_HPD
EDP_HPD <38>
RC443
Display Port C Detected 4.7K_0201_5%
CK11
EDP_BKLTEN CG11 PANEL_BKEN_PCH <38>
HIGH detected
1
EDP_VDDEN CH11 ENVDD_PCH <38>
LOW(DEFAULT) not detected EDP_BKLTCTL BIA_PWM_PCH <38> GPP_H21
WEAK INTERNAL PD 20K
RC8 1 2 24.9_0201_1% EDP_COMP AM6 An external pull-up is required on this strap since 38.4 MHz
+0.95VS_VCCIO DISP_RCOMP XTAL is not supported on the PCH.
CPU_DP1_CTRL_CLK CC8
CPU_DP1_CTRL_DATA Strap Pin CC9 GPP_E18/DPPB_CTRLCLK/CNVI_BT_HOST_WAKE# XTAL Frequency Select
GPP_E19/DPPB_CTRLDATA
C
CPU_DP2_CTRL_CLK CH4
HIGH 24MHz C
CPU_DP2_CTRL_DATA Strap Pin CH3 GPP_E20/DPPC_CTRLCLK LOW(DEFAULT) 38.4MHz

GPP_E21/DPPC_CTRLDATA WEAK INTERNAL PD
CP4
CN4 GPP_E22/DPPD_CTRLCLK
GPP_E23/DPPD_CTRLDATA
CR26 +3.3V_ALW_PCH
GPP_H17 Strap Pin CP26 GPP_H16/DDPF_CTRLCLK
GPP_H17/DDPF_CTRLDATA
2
CML-U_BGA1528 1 of 20
@ RC537
4.7K_0201_5%
+3.3V_ALW_PCH
1
1 2 GPP_H17 GPP_H23
@ RC101 20K_0201_5%
This strap should sample HIGH.
Reserved, This signal has a weak internal pull-down. There should NOT be any on-board device Warning: This strap must be configured to "0"(SAFS is disabled)
This strap should sample LOW. CPU@ driving it to opposite direction during strap sampling. if the eSPI or LPC strap is configured to "0"(eSPI is disabled)
UC1I eSPI Flash Sharing Mode
CR30
<52> CNV_PRX_DTX_N0 CP30 CNVI_WR_D0N CN27
<52> CNV_PRX_DTX_P0 CNVI_WR_D0P CNVi GPP_H18/CPU_C10_GATE# CPU_C10_GATE# <17,87> HIGH Slave Attached Flash Sharing (SAFS) enabled
CM30 CM27 LOW(DEFAULT) Master Attached Flash Sharing (MAFS) enabled
<52> CNV_PRX_DTX_N1 CN30 CNVI_WR_D1N GPP_H19/TIMESYNC_0 WEAK INTERNAL PD
+1.8V_RUN <52> CNV_PRX_DTX_P1 CNVI_WR_D1P CF25 Strap Pin GPP_H21
CN32 GPP_H21/XTAL_FREQ_SELECT CN26
<52> CNV_PTX_DRX_N0 CM32 CNVI_WT_D0N GPP_H22 CM26Strap Pin GPP_H23
1 2 DDR_CHA_EN_1P8 <52> CNV_PTX_DRX_P0 CNVI_WT_D0P GPP_H23 CK17
RC878 100K_0201_5% CP33 GPP_F10
1 2 DDR_CHB_EN_1P8 <52> CNV_PTX_DRX_N1 CN33 CNVI_WT_D1N
<52> CNV_PTX_DRX_P1 CNVI_WT_D1P BV35 Strap Pin GPD7
RC879 100K_0201_5%
CN31 GPD7 CN20
<52> CLK_CNV_PRX_DTX_N CP31 CNVI_WR_CLKN GPP_F3
<52> CLK_CNV_PRX_DTX_P
CP34
CNVI_WR_CLKP
GPP_D4/IMGCLKOUT0/BK4/SBK4
CG25
CH25 TBT_FORCE_PWR <42> DRAM Option Detail at Page 103
<52> CLK_CNV_PTX_DRX_N CN34 CNVI_WT_CLKN GPP_H20/IMGCLKOUT1
B
1 2 DDR_CHA_EN_1P8 <52> CLK_CNV_PTX_DRX_P CNVI_WT_CLKP CR201.8V MEM_CONFIG0_1P8 +1.8V_PRIM +1.8V_PRIM +1.8V_PRIM +1.8V_PRIM +1.8V_PRIM B
@ RC880 0_0201_5% 150_0201_1% 2 1 RC448 CNV_WT_RCOMP CP32 GPP_F12/EMMC_DATA0 CM201.8V MEM_CONFIG1_1P8

1 2 DDR_CHB_EN_1P8 CR32 CNVI_WT_RCOMP_1 EMMC GPP_F13/EMMC_DATA1 CN191.8V MEM_CONFIG2_1P8
CNVI_WT_RCOMP_2 GPP_F14/EMMC_DATA2
1
@ RC881 0_0201_5% <52> CNV_COEX3_1P8 1.8V CP20 CM191.8V MEM_CONFIG3_1P8
DDR_CHA_EN_1P8 1.8V CK19 GPP_F0/CNVI_PA_BLANKING GPP_F15/EMMC_DATA3 CN181.8V MEM_CONFIG4_1P8 RC388 @ RC389 @ RC390 @ RC391 @ RC392 @
DDR_CHB_EN_1P8 1.8VCG17 GPP_F1 GPP_F16/EMMC_DATA4 CR18
GPP_F2 GPP_F17/EMMC_DATA5 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
CP18
CR14 GPP_F18/EMMC_DATA6 CM18
<74> WWAN_FULL_PWR_EN
2
CP14 GPP_C8/UART0_RXD GPP_F19/EMMC_DATA7 MEM_CONFIG0_1P8 MEM_CONFIG1_1P8 MEM_CONFIG2_1P8 MEM_CONFIG3_1P8 MEM_CONFIG4_1P8
<79> SBIOS_TX CN14 GPP_C9/UART0_TXD CM16
GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK
1
CM14 CP16
GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16 RC393 @ RC394 @ RC395 @ RC396 @ RC871 @
1.8V CJ17 GPP_F11/EMMC_CMD CN16
<52> CNV_COEX2_1P8 GPP_F8/CNVI_MFUART2_RXD GPP_F22/EMMC_RESET# 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
1.8VCH17
<52> CNV_COEX1_1P8 GPP_F9/CNVI_MFUART2_TXD CK15 EMMC_RCOMP 1 2
2
607109_CML_U_PDG_Rev0p7 P.456(602383-cml-mow-ww03-2019) 2 1 A4WP_PRESENT_1P8 1.8V CF17 EMMC_RCOMP RC10 200_0201_1%
Although not used, it is Recommended to not use this GPIO for other needs, RC88 75K_0201_5% GPP_F23/A4WP_PRESENT
to nottoggle it, and to add a PD at the platform
level to avoid a floating signal (with a non-deterministic value)
A A
CPU(1/14)DDI,EDP,CSI2,EMMC
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
5 4 3 2 1
5 4 3 2 1
DDR4, Ballout for side by side(Non-Interleave)
D <24> DDR_B_DQS#[0..7] D
<23> DDR_A_DQS#[0..7]
<24> DDR_B_D[0..63]
<23> DDR_A_D[0..63]
<24> DDR_B_DQS[0..7]
<23> DDR_A_DQS[0..7]
<24> DDR_B_MA[0..16]
<23> DDR_A_MA[0..16]
CPU@ CPU@
UC1B UC1C
LP4x(V2) / DDR4 (IL) / LP3(V1)-DDR4 (NIL) LP4x(V2) / LP3(V1) / DDR4 LP4x(V2) / DDR4 (IL) / LP3(V1)-DDR4 (NIL) LP4x(V2) / LP3(V1) / DDR4
DDR_A_D0 A26 V32 DDR_A_CLK#0 DDR_A_D16 J22 AF28 DDR_B_CLK#0
DDR_A_D1 DDRA_DQ0_0/DDR0_DQ_0/DDR0_DQ_0 DDRB_CLK_N/DDR0_CKN_0/DDR0_CKN_0 DDR_A_CLK0 DDR_A_CLK#0 <23> DDR_A_D17 DDRA_DQ2_0/DDR1_DQ_0/DDR0_DQ_16 DDRD_CLK_N/DDR1_CKN_0/DDR1_CKN_0 DDR_B_CLK0 DDR_B_CLK#0 <24>
D26 V31 H25 AF29
DDR_A_D2 DDRA_DQ0_1/DDR0_DQ_1/DDR0_DQ_1 DDRB_CLK_P/DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK0 <23> DDR_A_D18 DDRA_DQ2_1/DDR1_DQ_1/DDR0_DQ_17 DDRD_CLK_P/DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK0 <24>
D28 T32 G22 AE28
DDR_A_D3 C28 DDRA_DQ0_2/DDR0_DQ_2/DDR0_DQ_2 DDRA_CLK_N/DDR0_CKN_1/DDR0_CKN_1 T31 DDR_A_D19 H22 DDRA_DQ2_2/DDR1_DQ_2/DDR0_DQ_18 DDRC_CLK_N/DDR1_CKN_1/DDR1_CKN_1 AE29
DDR_A_D4 B26 DDRA_DQ0_3/DDR0_DQ_3/DDR0_DQ_3 DDRA_CLK_P/DDR0_CKP_1/DDR0_CKP_1 DDR_A_D20 F25 DDRA_DQ2_3/DDR1_DQ_3/DDR0_DQ_19 DDRC_CLK_P/DDR1_CKP_1/DDR1_CKP_1
DDR_A_D5 DDRA_DQ0_4/DDR0_DQ_4/DDR0_DQ_4 LP4x(V2) / LP3(V1) / DDR4 DDR_A_CKE0 DDR_A_D21 DDRA_DQ2_4/DDR1_DQ_4/DDR0_DQ_20 LP4x(V2) / LP3(V1) / DDR4
C26 U36 J25 T28
DDR_A_D6 DDRA_DQ0_5/DDR0_DQ_5/DDR0_DQ_5 DDRA_CKE0/DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE0 <23> DDR_A_D22 DDRA_DQ2_5/DDR1_DQ_5/DDR0_DQ_21 DDRC_CKE0/DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE0 <24>
B28 U37 G25 T29
DDR_A_D7 A28 DDRA_DQ0_6/DDR0_DQ_6/DDR0_DQ_6 DDRA_CKE1/DDR0_CKE_1/DDR0_CKE_1 U34 DDR_A_D23 F22 DDRA_DQ2_6/DDR1_DQ_6/DDR0_DQ_22 DDRC_CKE1/DDR1_CKE_1/DDR1_CKE_1 V28
DDR_A_D8 B30 DDRA_DQ0_7/DDR0_DQ_7/DDR0_DQ_7 DDRB_CKE0/DDR0_CKE_2/NC U35 DDR_A_D24 D22 DDRA_DQ2_7/DDR1_DQ_7/DDR0_DQ_23 DDRD_CKE0/DDR1_CKE_2/NC V29
DDR_A_D9 D30 DDRA_DQ1_0/DDR0_DQ_8/DDR0_DQ_8 DDRB_CKE1/DDR0_CKE_3/NC DDR_A_D25 C22 DDRA_DQ3_0/DDR1_DQ_8/DDR0_DQ_24 DDRD_CKE1/DDR1_CKE_3/NC
DDR_A_D10 DDRA_DQ1_1/DDR0_DQ_9/DDR0_DQ_9 LP4x(V2) / LP3(V1) / DDR4 DDR_A_CS#0 DDR_A_D26 DDRA_DQ3_1/DDR1_DQ_9/DDR0_DQ_25 LP4x(V2) / LP3(V1) / DDR4 DDR_B_CS#0
B33 AE32 C24 AL37
DDR_A_D11 DDRA_DQ1_2/DDR0_DQ_10/DDR0_DQ_10 DDRA_CS#_0/DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#0 <23> DDR_A_D27 DDRA_DQ3_2/DDR1_DQ_10/DDR0_DQ_26 DDRC_CS#_0/DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#0 <24>
D32 AF32 D24 AL35
DDR_A_D12 A30 DDRA_DQ1_3/DDR0_DQ_11/DDR0_DQ_11 DDRA_CS#_1/DDR0_CS#_1/DDR0_CS#_1 AE31 DDR_A_ODT0 DDR_A_D28 A22 DDRA_DQ3_3/DDR1_DQ_11/DDR0_DQ_27 DDRC_CS#_1/DDR1_CS#_1/DDR1_CS#_1 AL36 DDR_B_ODT0
DDR_A_D13 DDRA_DQ1_4/DDR0_DQ_12/DDR0_DQ_12 DDRB_CS#_0/DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT0 <23> DDR_A_D29 DDRA_DQ3_4/DDR1_DQ_12/DDR0_DQ_28 DDRD_CS#_0/DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT0 <24>
C30 AF31 B22 AL34
DDR_A_D14 B32 DDRA_DQ1_5/DDR0_DQ_13/DDR0_DQ_13 DDRB_CS#_1/NC/DDR0_ODT_1 DDR_A_D30 A24 DDRA_DQ3_5/DDR1_DQ_13/DDR0_DQ_29 DDRD_CS#_1/NC/DDR1_ODT_1 AG36
DDR_A_D15 DDRA_DQ1_6/DDR0_DQ_14/DDR0_DQ_14 LP4x(V2) / LP3(V1) / DDR4 DDR_A_D31 DDRA_DQ3_6/DDR1_DQ_14/DDR0_DQ_30 NC/DDR1_CAB_9/DDR1_MA_0 DDR_B_MA0 <24>
C32 AC37 B24 AG35
DDR_A_D32 DDRA_DQ1_7/DDR0_DQ_15/DDR0_DQ_15 NC//DDR0_CAB_9/DDR0_MA_0 DDR_A_MA0 <23> DDR_A_D48 DDRA_DQ3_7/DDR1_DQ_15/DDR0_DQ_31 NC/DDR1_CAB_8/DDR1_MA_1 DDR_B_MA1 <24>
H37 AC36 G31 AF34
DDR_A_D33 DDRB_DQ0_0/DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CAB_8/DDR0_MA_1 DDR_A_MA1 <23> DDR_A_D49 DDRB_DQ2_0/DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CAB_5/DDR1_MA_2 DDR_B_MA2 <24>
H34 AC34 G32 AG37
DDR_A_D34 DDRB_DQ0_1/DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CAB_5/DDR0_MA_2 DDR_A_MA2 <23> DDR_A_D50 DDRB_DQ2_1/DDR1_DQ_17/DDR0_DQ_49 NC/NC/DDR1_MA_3 DDR_B_MA3 <24>
K34 AC35 H29 AE35
DDR_A_D35 DDRB_DQ0_2/DDR0_DQ_18/DDR0_DQ_34 NC/NC/DDR0_MA_3 DDR_A_MA3 <23> DDR_A_D51 DDRB_DQ2_2/DDR1_DQ_18/DDR0_DQ_50 DDRC_CA5/NC/DDR1_MA_4 DDR_B_MA4 <24>
K35 AA35 H28 AF35
DDR_A_D36 DDRB_DQ0_3/DDR0_DQ_19/DDR0_DQ_35 DDRA_CA5/NC/DDR0_MA_4 DDR_A_MA4 <23> DDR_A_D52 DDRB_DQ2_3/DDR1_DQ_19/DDR0_DQ_51 DDRC_CA0/DDR1_CAA_0/DDR1_MA_5 DDR_B_MA5 <24>
H36 AB35 G28 AE37
DDR_A_D37 DDRB_DQ0_4/DDR0_DQ_20/DDR0_DQ_36 DDRA_CA0/DDR0_CAA_0/DDR0_MA_5 DDR_A_MA5 <23> DDR_A_D53 DDRB_DQ2_4/DDR1_DQ_20/DDR0_DQ_52 DDRC_CA2/DDR1_CAA_2/DDR1_MA_6 DDR_B_MA6 <24>
H35 AA37 G29 AC29
K36 AA36 H31 AE36
K37 AB34 H32 AB29
N36 W36 L31 AG34
DDR_A_D41 DDRB_DQ1_0/DDR0_DQ_24/DDR0_DQ_40 DDRA_CA1/DDR0_CAA_1/DDR0_MA_9 DDR_A_MA9 <23> DDR_A_D57 DDRB_DQ3_0/DDR1_DQ_24/DDR0_DQ_56 NC/DDR1_CAB_7/DDR1_MA_10 DDR_B_MA10 <24>
N34 Y31 L32 AC28
C DDR_A_D42 DDRB_DQ1_1/DDR0_DQ_25/DDR0_DQ_41 NC/DDR0_CAB_7/DDR0_MA_10 DDR_A_MA10 <23> DDR_A_D58 DDRB_DQ3_1/DDR1_DQ_25/DDR0_DQ_57 NC/DDR1_CAA_7/DDR1_MA_11 DDR_B_MA11 <24> C
R37 W34 N29 AB28
DDR_A_D43 DDRB_DQ1_2/DDR0_DQ_26/DDR0_DQ_42 NC/DDR0_CAA_7/DDR0_MA_11 DDR_A_MA11 <23> DDR_A_D59 DDRB_DQ3_2/DDR1_DQ_26/DDR0_DQ_58 NC/DDR1_CAA_6/DDR1_MA_12 DDR_B_MA12 <24>
R34 AA34 N28 AK35
DDR_A_D44 DDRB_DQ1_3/DDR0_DQ_27/DDR0_DQ_43 NC/DDR0_CAA_6/DDR0_MA_12 DDR_A_MA12 <23> DDR_A_D60 DDRB_DQ3_3/DDR1_DQ_27/DDR0_DQ_59 DDRD_CA0/DDR1_CAB_0/DDR1_MA_13 DDR_B_MA13 <24>
N37 AC32 L28
DDR_A_D45 DDRB_DQ1_4/DDR0_DQ_28/DDR0_DQ_44 DDRB_CA0/DDR0_CAB_0/DDR0_MA_13 DDR_A_MA13 <23> DDR_A_D61 DDRB_DQ3_4/DDR1_DQ_28/DDR0_DQ_60 LP4x(V2) / LP3(V1) / DDR4
N35 L29 AJ35
DDR_A_D46 DDRB_DQ1_5/DDR0_DQ_29/DDR0_DQ_45 LP4x(V2) / LP3(V1) / DDR4 DDR_A_D62 DDRB_DQ3_5/DDR1_DQ_29/DDR0_DQ_61 DDRD_CA2/DDR1_CAB_2/DDR1_MA_14 DDR_B_MA14 <24>
R36 AC31 N31 AK34
DDR_A_D47 DDRB_DQ1_6/DDR0_DQ_30/DDR0_DQ_46 DDRB_CA2/DDR0_CAB_2/DDR0_MA_14 DDR_A_MA14 <23> DDR_A_D63 DDRB_DQ3_6/DDR1_DQ_30/DDR0_DQ_62 DDRD_CA1/DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15 <24>
R35 AB32 N32 AJ34
DDR_B_D0 DDRB_DQ1_7/DDR0_DQ_31/DDR0_DQ_47 DDRB_CA1/DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15 <23> DDR_B_D16 DDRB_DQ3_7/DDR1_DQ_31/DDR0_DQ_63 DDRD_CA3/DDR1_CAB_3/DDR1_MA_16 DDR_B_MA16 <24>
AN35 Y32 AJ29
DDR_B_D1 DDRC_DQ0_0/DDR0_DQ_32/DDR1_DQ_0 DDRB_CA3/DDR0_CAB_3/DDR0_MA_16 DDR_A_MA16 <23> DDR_B_D17 DDRC_DQ2_0/DDR1_DQ_32/DDR1_DQ_16 LP4x(V2) / LP3(V1) / DDR4
AN34 AJ30 AJ37
DDR_B_D2 DDRC_DQ0_1/DDR0_DQ_33/DDR1_DQ_1 LP4x(V2) / LP3(V1) / DDR4 DDR_B_D18 DDRC_DQ2_1/DDR1_DQ_33/DDR1_DQ_17 DDRD_CA4/DDR1_CAB_4/DDR1_BA_0 DDR_B_BA0 <24>
AR35 W32 AM32 AJ36
DDR_B_D3 DDRC_DQ0_2/DDR0_DQ_34/DDR1_DQ_2 DDRB_CA4/DDR0_CAB_4/DDR0_BA_0 DDR_A_BA0 <23> DDR_B_D19 DDRC_DQ2_2/DDR1_DQ_34/DDR1_DQ_18 DDRD_CA5/DDR1_CAB_6/DDR1_BA_1 DDR_B_BA1 <24>
AR34 AB31 AM31 W29
DDR_B_D4 DDRC_DQ0_3/DDR0_DQ_35/DDR1_DQ_3 DDRB_CA5/DDR0_CAB_6/DDR0_BA_1 DDR_A_BA1 <23> DDR_B_D20 DDRC_DQ2_3/DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
AN37 V34 AM30
DDR_B_D5 DDRC_DQ0_4/DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23> DDR_B_D21 DDRC_DQ2_4/DDR1_DQ_36/DDR1_DQ_20 LP4x(V2) / LP3(V1) / DDR4
AN36 AM29 Y28
DDR_B_D6 DDRC_DQ0_5/DDR0_DQ_37/DDR1_DQ_5 LP4x(V2) / LP3(V1) / DDR4 DDR_B_D22 DDRC_DQ2_5/DDR1_DQ_37/DDR1_DQ_21 NC/DDR1_CAA_9/DDR1_BG_1 DDR_B_BG1 <24>
AR36 V35 AJ31 W28
DDR_B_D7 DDRC_DQ0_6/DDR0_DQ_38/DDR1_DQ_6 NC/DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <23> DDR_B_D23 DDRC_DQ2_6/DDR1_DQ_38/DDR1_DQ_22 NC/DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <24>
AR37 W35 AJ32
DDR_B_D8 DDRC_DQ0_7/DDR0_DQ_39/DDR1_DQ_7 NC/DDR0_CAA_9/DDR0_BG_1 DDR_A_BG1 <23> DDR_B_D24 DDRC_DQ2_7/DDR1_DQ_39/DDR1_DQ_23 LP4x(V2) / DDR4 (IL) / LP3(V1)-DDR4 (NIL)
AU35 AR31 H24
DDR_B_D9 DDRC_DQ1_0/DDR0_DQ_40/DDR1_DQ_8 LP4x(V2) / DDR4 (IL) / LP3(V1)-DDR4 (NIL) DDR_B_D25 DDRC_DQ3_0/DDR1_DQ_40/DDR1_DQ_24 DDRA_DQSN_2/DDR1_DQSN_0/DDR0_DQSN_2 DDR_A_DQS#2 <23>
AU34 C27 AR32 G24
DDR_B_D10 DDRC_DQ1_1/DDR0_DQ_41/DDR1_DQ_9 DDRA_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#0 <23> DDR_B_D26 DDRC_DQ3_1/DDR1_DQ_41/DDR1_DQ_25 DDRA_DQSP_2/DDR1_DQSP_0/DDR0_DQSP_2 DDR_A_DQS2 <23>
AW35 D27 AV30 C23
DDR_B_D11 DDRC_DQ1_2/DDR0_DQ_42/DDR1_DQ_10 DDRA_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS0 <23> DDR_B_D27 DDRC_DQ3_2/DDR1_DQ_42/DDR1_DQ_26 DDRA_DQSN_3/DDR1_DQSN_1/DDR0_DQSN_3 DDR_A_DQS#3 <23>
AW34 D31 AV29 D23
DDR_B_D12 DDRC_DQ1_3/DDR0_DQ_43/DDR1_DQ_11 DDRA_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DDR_A_DQS#1 <23> DDR_B_D28 DDRC_DQ3_3/DDR1_DQ_43/DDR1_DQ_27 DDRA_DQSP_3/DDR1_DQSP_1/DDR0_DQSP_3 DDR_A_DQS3 <23>
AU37 C31 AR30 G30
DDR_B_D13 DDRC_DQ1_4/DDR0_DQ_44/DDR1_DQ_12 DDRA_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS1 <23> DDR_B_D29 DDRC_DQ3_4/DDR1_DQ_44/DDR1_DQ_28 DDRB_DQSN_2/DDR1_DQSN_2/DDR0_DQSN_6 DDR_A_DQS#6 <23>
AU36 J35 AR29 H30
DDR_B_D14 DDRC_DQ1_5/DDR0_DQ_45/DDR1_DQ_13 DDRB_DQSN_0/DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#4 <23> DDR_B_D30 DDRC_DQ3_5/DDR1_DQ_45/DDR1_DQ_29 DDRB_DQSP_2/DDR1_DQSP_2/DDR0_DQSP_6 DDR_A_DQS6 <23>
AW36 J34 AV32 L30
DDR_B_D15 DDRC_DQ1_6/DDR0_DQ_46/DDR1_DQ_14 DDRB_DQSP_0/DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS4 <23> DDR_B_D31 DDRC_DQ3_6/DDR1_DQ_46/DDR1_DQ_30 DDRB_DQSN_3/DDR1_DQSN_3/DDR0_DQSN_7 DDR_A_DQS#7 <23>
AW37 P34 AV31 N30
DDR_B_D32 DDRC_DQ1_7/DDR0_DQ_47/DDR1_DQ_15 DDRB_DQSN_1/DDR0_DQSN_3/DDR0_DQSN_5 DDR_A_DQS#5 <23> DDR_B_D48 DDRC_DQ3_7/DDR1_DQ_47/DDR1_DQ_31 DDRB_DQSP_3/DDR1_DQSP_3/DDR0_DQSP_7 DDR_A_DQS7 <23>
BA35 P35 BA32 AL31
DDR_B_D33 DDRD_DQ0_0/DDR0_DQ_48/DDR1_DQ_32 DDRB_DQSP_1/DDR0_DQSP_3/DDR0_DQSP_5 DDR_A_DQS5 <23> DDR_B_D49 DDRD_DQ2_0/DDR1_DQ_48/DDR1_DQ_48 DDRC_DDSN_2/DDR1_DQSN_4/DDR1_DQSN_2 DDR_B_DQS#2 <24>
BA34 AP35 BA31 AL30
DDR_B_D34 DDRD_DQ0_1/DDR0_DQ_49/DDR1_DQ_33 DDRC_DQSN_0/DDR0_DQSN_4/DDR1_DQSN_0 DDR_B_DQS#0 <24> DDR_B_D50 DDRD_DQ2_1/DDR1_DQ_49/DDR1_DQ_49 DDRC_DDSP_2/DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS2 <24>
BC35 AP34 BD31 AU31
DDR_B_D35 DDRD_DQ0_2/DDR0_DQ_50/DDR1_DQ_34 DDRC_DQSP_0/DDR0_DQSP_4/DDR1_DQSP_0 DDR_B_DQS0 <24> DDR_B_D51 DDRD_DQ2_2/DDR1_DQ_50/DDR1_DQ_50 DDRC_DQSN_3/DDR1_DQSN_5/DDR1_DQSN_3 DDR_B_DQS#3 <24>
BC34 AV34 BD32 AU30
DDR_B_D36 DDRD_DQ0_3/DDR0_DQ_51/DDR1_DQ_35 DDRC_DQSN_1/DDR0_DQSN_5/DDR1_DQSN_1 DDR_B_DQS#1 <24> DDR_B_D52 DDRD_DQ2_3/DDR1_DQ_51/DDR1_DQ_51 DDRC_DQSP_3/DDR1_DQSP_5/DDR1_DQSP_3 DDR_B_DQS3 <24>
BA37 AV35 BA30 BC31
DDR_B_D37 DDRD_DQ0_4/DDR0_DQ_52/DDR1_DQ_36 DDRC_DQSP_1/DDR0_DQSP_5/DDR1_DQSP_1 DDR_B_DQS1 <24> DDR_B_D53 DDRD_DQ2_4/DDR1_DQ_52/DDR1_DQ_52 DDRD_DQSN_2/DDR1_DQSN_6/DDR1_DQSN_6 DDR_B_DQS#6 <24>
BA36 BB35 BA29 BC30
DDR_B_D38 DDRD_DQ0_5/DDR0_DQ_53/DDR1_DQ_37 DDRD_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_4 DDR_B_DQS#4 <24> DDR_B_D54 DDRD_DQ2_5/DDR1_DQ_53/DDR1_DQ_53 DDRD_DQSP_2/DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS6 <24>
BC36 BB34 BD29 BH31
DDR_B_D39 DDRD_DQ0_6/DDR0_DQ_54/DDR1_DQ_38 DDRD_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_4 DDR_B_DQS4 <24> DDR_B_D55 DDRD_DQ2_6/DDR1_DQ_54/DDR1_DQ_54 DDRD_DQSN_3/DDR1_DQSN_7/DDR1_DQSN_7 DDR_B_DQS#7 <24>
BC37 BF34 BD30 BH30
DDR_B_D40 DDRD_DQ0_7/DDR0_DQ_55/DDR1_DQ_39 DDRD_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_DQS#5 <24> DDR_B_D56 DDRD_DQ2_7/DDR1_DQ_55/DDR1_DQ_55 DDRD_DQSP_3/DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 <24>
BE35 BF35 BG31
DDR_B_D41 DDRD_DQ1_0/DDR0_DQ_56/DDR1_DQ_40 DDRD_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_5 DDR_B_DQS5 <24> DDR_B_D57 DDRD_DQ3_0/DDR1_DQ_56/DDR1_DQ_56 LP4x(V2) / LP3(V1) / DDR4 DDR_B_ALERT#
BE34 BG32 Y29
DDR_B_D42 DDRD_DQ1_1/DDR0_DQ_57/DDR1_DQ_41 LP4x(V2) / LP3(V1) / DDR4 DDR_B_D58 DDRD_DQ3_1/DDR1_DQ_57/DDR1_DQ_57 NC/NC/DDR1_ALERT# DDR_B_PARITY DDR_B_ALERT# <24>
BG35 W37 BK32 AE34
DDR_B_D43 DDRD_DQ1_2/DDR0_DQ_58/DDR1_DQ_42 NC/NC/DDR0_ALERT# DDR_A_ALERT# <23> DDR_B_D59 DDRD_DQ3_2/DDR1_DQ_58/DDR1_DQ_58 NC/NC/DDR1_PAR DDR_DRAMRST# DDR_B_PARITY <24>
BG34 W31 BK31 BU31
DDR_B_D44 DDRD_DQ1_3/DDR0_DQ_59/DDR1_DQ_43 NC/NC/DDR0_PAR DDR_A_PARITY <23> DDR_B_D60 DDRD_DQ3_3/DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET# DDR_DRAMRST# <23>
BE37 F36 BG29
DDR_B_D45 DDRD_DQ1_4/DDR0_DQ_60/DDR1_DQ_44 NC/DDR0_VREF_CA/DDR0_VREF_CA +DDR_VREF_CA DDR_B_D61 DDRD_DQ3_4/DDR1_DQ_60/DDR1_DQ_60 SM_RCOMP0
BE36 D35 BG30 BN28
DDR_B_D46 BG36 DDRD_DQ1_5/DDR0_DQ_61/DDR1_DQ_45 NC/DDR0_VREF_DQ_1/NC_1 D37 DDR_B_D62 BK30 DDRD_DQ3_5/DDR1_DQ_61/DDR1_DQ_61 DDR_RCOMP_0 BN27 SM_RCOMP1
DDR_B_D47 BG37 DDRD_DQ1_6/DDR0_DQ_62/DDR1_DQ_46 NC/DDR0_VREF_DQ_2/NC_2 E36 DDR_B_D63 BK29 DDRD_DQ3_6/DDR1_DQ_62/DDR1_DQ_62 DDR_RCOMP_1 BN29 SM_RCOMP2
DDRD_DQ1_7/DDR0_DQ_63/DDR1_DQ_47 NC/DDR1_VREF_DQ/DDR1_VREF_CA +DDR_VREF_B_DQ DDRD_DQ3_7/DDR1_DQ_63/DDR1_DQ_63 DDR_RCOMP_2
C35
DDR_VTT_CTL DDR_VTT_CTRL <23>
B CML-U_BGA1528 2 of 20 B
DDR4 COMPENSATION SIGNALS

SM_RCOMP0 RC5 1 2 121_0201_1%
SM_RCOMP1 RC504 1 2 80.6_0201_1%
SM_RCOMP2 RC7 1 2 100_0201_1%
A A
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU(2/14)DDR4
5 4 3 2 1
5 4 3 2 1
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
606576-cml-pch-lp-eds-vol1-rev1p0 P.263
CPU@
UC1E
PCH_SPI_CLK_PCH CH37 CK14 MEM_SMBCLK
RC11 need pop when use XDP PCH_SPI_D1_PCH CF37 SPI0_CLK GPP_C0/SMBCLK CH15 MEM_SMBDATA
PCH_SPI_D0_PCH Strap Pin CF36 SPI0_MISO GPP_C1/SMBDATA CJ15 Strap Pin GPP_C2
@CXDP@ RC11 2 1 1K_0201_5% PCH_SPI_D2_PCH Strap Pin CF34 SPI0_MOSI GPP_C2/SMBALERT#
<79> PCH_SPI_DO2_XDP PCH_SPI_D3_PCH Strap Pin CG34 SPI0_IO2 SPI - FLASH CH14 SML0_SMBCLK
PCH_SPI_CS#0 SPI0_IO3 GPP_C3/SML0CLK SML0_SMBDATA SML0_SMBCLK <42>
CG36 SMBUS , SMLINK CF15
SPI0_CS0# GPP_C4/SML0DATA SML0_ALERT# SML0_SMBDATA <42>
CG35 CG15Strap Pin
SPI0_CS1# GPP_C5/SML0ALERT# SML0_ALERT# <42>
CH34
<66> PCH_SPI_CS#2 SPI0_CS2# SML1_SMBCLK
CN15 SML1_SMBCLK <58>
GPP_C6/SML1CLK CM15 SML1_SMBDATA
GPP_C7/SML1DATA SML1_SMBDATA <58>
D CC34Strap Pin GPP_B23 D
+3.3V_ALW _PCH VPRO_DET# CF20 GPP_B23/SML1ALERT#/PCHHOT#
CG22 GPP_D1/SPI1_CLK/BK1/SBK1
RTC_DET# CF22 GPP_D2/SPI1_MISO_IO1/BK2/SBK2
<83> RTC_DET# GPP_D3/SPI1_MOSI_IO0/BK3/SBK3SPI - TOUCH ESPI_IO0_1P8_R RC366
CG23 CA291.8V 1 2 15_0201_5%
GPP_D21/SPI1_IO2 GPP_A1/LAD0/ESPI_IO0 ESPI_IO0_1P8 <58,79>
1
CH23 BY29 1.8V ESPI_IO1_1P8_R RC367 1 2 15_0201_5%

GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1 ESPI_IO2_1P8_R RC368 ESPI_IO1_1P8 <58,79>
CG20 BY27 1.8V 1 2 15_0201_5%
100K_0201_5% <70> MEDIACARD_IRQ# GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2 ESPI_IO3_1P8_R RC369 ESPI_IO2_1P8 <58,79>
BV27 1.8V 1 2 15_0201_5%
RC882 NVPRO@ GPP_A4/LAD3/ESPI_IO3 ESPI_IO3_1P8 <58,79>
LPC , ESPI CA281.8V
GPP_A5/LFRAME#/ESPI_CS# CA271.8V ESPI_CS#_1P8 <58,79> RVP 15 ohm
ESPI_RESET#_1P8 <58,79>
2
CH7 GPP_A14/SUS_STAT#/ESPI_RESET# 607554_CML-U_v1_AEP_SCH_Rev0p9

VPRO_DET# <52> PCH_CL_CLK1 CH8 CL_CLK BV32 1.8V ESPI_CLK EMI@ RC19 1 2 33_0201_5%
<52> PCH_CL_DATA1 CL_DATA GPP_A9/CLKOUT_LPC0/ESPI_CLK ESPI_CLK_1P8 <58,79>
CH9 C LINK BV30
<52> PCH_CL_RST1# CL_RST# GPP_A10/CLKOUT_LPC1 BY30
GPP_A8/CLKRUN#
1
BV29
100K_0201_5% VPRO_DET# BV28 GPP_A0/RCIN#/TIME_SYNC1
RC883 VPRO@ GPP_A6/SERIRQ
2
HIG H NVPRO
606576-cml-pch-lp-eds-vol1-rev1p0
LOW VPRO External pull-up is required. Recommend 100 kohm if
pulled up to 3.3V or 75 kohm if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
2 1 ESPI_RESET#_1P8 any on-board device driving it to opposite direction
@ RC833 100K_0201_5% during strap sampling.
2 1 PCH_SPI_CLK_PCH
RC96 100K_0201_5%
Reserved Straps pin Reserved Straps pin Reserved Straps pin +3.3V_ALW_PCH
RF Request
Reference to 607109_CML_U_PDG_Rev2p0 P.172 +3.3V_ALW _PCH +3.3V_ALW _PCH +3.3V_ALW _PCH
ESPI_CLK_1P8 1 2 MEM_SMBCLK 1 2
+3.3V_ALW _PCH @RF@ CC316 33P_0201_50V8J RC12 1K_0201_5%
1
1
MEM_SMBDATA 1 2
RC94 RC61 RC62 SML0_SMBCLK 1 2 RC14 1K_0201_5%
1
@RF@ CC318 33P_0201_50V8J SML1_SMBCLK 1 2
100K_0201_5% 100K_0201_5% 100K_0201_5%
RC305 RC15 1K_0201_5%
SML1_SMBCLK 1 2 SML1_SMBDATA 1 2
100K_0201_5%
2
2
PCH_SPI_D0_PCH PCH_SPI_D2_PCH PCH_SPI_D3_PCH @RF@ CC319 33P_0201_50V8J RC507 1K_0201_5%
SML0_SMBCLK 1 2
2
C C
1
1
PCH_SPI_D1_PCH MEM_SMBCLK 1 2 RC347 1K_0201_5%
@ RC518 @ RC519 @ RC515 @RF@ CC320 33P_0201_50V8J SML0_SMBDATA 1 2
4.7K_0201_5% 4.7K_0201_5% 4.7K_0201_5% RC348 1K_0201_5%
RTC_DET# 1 2
@ RC866 100K_0201_5%
2
2
Add according to Microchip 0621 feedback
PLACE RC61 AND RC519 CLOSE PLACE RC62 AND RC515 CLOSE Place close CPU side 0418 Follow Dorest intel recommend change pull up to 100K from 10K.
TO THE SPI SIGNAL TO AVOID STUB TO THE SPI SIGNAL TO AVOID STUB
EC G3 SPI Flash Sharing with Wire-OR(1 Flash and 1TPM)

Reference 607109_CML_U_PDG_Rev1p2 P.333
QC9,VGS(th)Max=2.5V,Typ=1.6V,Min=1.0V
Topology R1 loaction
G3 sharing WDT circuit @ QC9 Need to use the same specifications
NX7002BKW _SOT323-3
PCH_SPI_CLK_PCH
@ RC27
1 2
0_0201_5%
PCH_SPI_CLK
PCH_SPI_CLK <66>
PCH_SPI_D0_PCH 1 2 PCH_SPI_D0
1 3 @ RC25 0_0201_5% PCH_SPI_D0 <66> --->To TPM
D
<11> VCCDSW _EN_Q PCH_RSMRST# <58,63,79> PCH_SPI_D1_PCH PCH_SPI_D1

1 2
From PCH ---> @ RC26 0_0201_5%
PCH_SPI_D1 <66>
PCH_SPI_D2_PCH 1 2 PCH_SPI_D2
G
2
1 2 @ RC29 0_0201_5%
@ RC303 200K_0201_1% PCH_SPI_D3_PCH 1 2 PCH_SPI_D3
1 @ RC30 0_0201_5%
@ CC341
Topology R3 loaction
0.33U_0201_25V6K 1 2 1 2 PCH_SPI_CLK_0_R
2 <58> SHD_CLK
RC581 33_0201_1% RC571 33_0201_1%
1 2 1 2 PCH_SPI_D0_0_R
<58> SHD_IO0
RC577 33_0201_1% RC570 33_0201_1%
1 2 1 2 PCH_SPI_D1_0_R +3.3V_ALW_PCH
<58> SHD_IO1 RC578 33_0201_1% RC734 33_0201_1% --->To UC5 ROM
1 2 1 2 PCH_SPI_D2_0_R
<58> SHD_IO2
RC579 75_0201_1% RC33 22_0201_1%
System ROM choice need follow ARD 2.01 approved list From EC ---> <58> SHD_IO3
1 2 1 2 PCH_SPI_D3_0_R GPP_C2 1 2
RC580 75_0201_1% RC572 22_0201_1% RC266 4.7K_0201_5%

B Topology R2 loaction B
PCH_SPI_CS#0 TLS CONFIDENTIALITY
1 2
<58> SHD_CS#0
@ RC582 0_0201_5% HIGH ENABLE
JSPI1 CONN@ LOW(DEFAULT) DISABLE
22
21 GND2
20 GND1
19 20 +3.3V_ALW_PCH
PCH_SPI_CLK 1 PCH_SPI_D0_PCH 18 19
PCH_SPI_D0 PAD~D @ VIA1 18
1 @ VIA2 17
PCH_SPI_D1 PAD~D PCH_SPI_D1_PCH 17
1 @ VIA3 16
PCH_SPI_D2 PAD~D 16 SML0_ALERT# RC277
1 @ VIA4 15 1 2 4.7K_0201_5%
PCH_SPI_D3 PAD~D PCH_SPI_CLK_PCH 15
1 @ VIA5 14 WEAK INTERNAL PD 20K
PAD~D 14
13
PCH_SPI_CS#0 12 13 eSPI or LPC Select(for EC)
VIA for Auto TLCT Footprint:TP_18D8 11 12
PCH_SPI_D2_PCH 10 11 HIGH eSPI
9 10 LOW (DEFAULT) LPC
PCH_SPI_D3_PCH 8 9
7 8 Warning: If this strap is configured to "0"(eSPI is disabled),
6 7 the eSPI Flash Sharing Mode
+3.3V_SPI 6 strap must be configured to "0" as well (SAFS is disabled)
5
+3.3V_ALW _PCH 5
4
<63> PROM_BIOS_R 3 4
PCH_SPI_CLK_0_R 2 3
+3.3V_SPI 1 2 1 2
256Mb WSON8 Flash ROM @ RC31 0_0201_5% 1 +3.3V_ALW_PCH
1
@EMI@ +3.3V_SPI CC9 JXT_FP243A-020G1BM

RC299 1 2 1 2
33_0201_5% 1 2 PCH_SPI_CS#0
RC206 4.7K_0201_5% 0.1U_0201_10V6K DC4 GPP_B23 1 2
UC5 RB521CM-30T2R_SOD923-2 @ RC317 4.7K_0201_5%
2
Add according to Microchip 0410 review results PCH_SPI_CS#0 1 2 SPI_CS#0_R 1 8

@ RC32 0_0201_5% PCH_SPI_D1_0_R 2 CS# VCC 7 PCH_SPI_D3_0_R 1. The internal pull-down is disabled after RSMRST# deasserts.
PCH_SPI_D2_0_R 3 SO(IO1) IO3 6 PCH_SPI_CLK_0_R 2. When used as PCHHOT# and strap low, a 150
1 IO2 SCLK PCH_SPI_D0_0_R kohm pull-up is needed to ensure it does not
@EMI@ 4 5 override the internal pull-down strap sampling.
CC1453 VSS SI(IO0) 9
ThemalPad
2
33P_0201_50V8J
GD25B256DYIG_W SON8_8X6
Intel DCI-OOB
HIGH ENABLE
A A
LOW(DEFAULT) DISABLE
WEAK INTERNAL PD
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU(3/14)SPI,ESPI,SMB,LPC
5 4 3 2 1
5 4 3 2 1
CPU@
UC1F
PRIM_CORE_OPT_DIS CC27
TPM_PIRQ#_A7 CC32 GPP_B15/GSPI0_CS0#
ONE_DIMM# CE28 GPP_A7/PIRQA#/GSPI0_CS1# CN22 IR_CAM_DET# TBT_DET#
CE27 GPP_B16/GSPI0_CLK GPP_D9/ISH_SPI_CS#/GSPI2_CS0# CR22 IR_CAM_DET# <38>
NRB_BIT Strap Pin CE29 GPP_B17/GSPI0_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK CM22 TBT_RTD3_WAKE#
GPP_B18/GSPI0_MOSI GPP_D11/ISH_SPI_MISO/GSPI2_MISO TBT_RTD3_WAKE# <42>
CP22 Strap PinGPP_D12
CA31 GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
GPP_B19/GSPI1_CS0#
1
CA32 CK22 ISH_I2C0_SDA
TPM_PIRQ#_B20 GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D5/ISH_I2C0_SDA ISH_I2C0_SCL ISH_I2C0_SDA <66>
CC29 CH20 RC401
PCH_3.3V_TS_EN CC30 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL ISH_I2C0_SCL <66>
<38> PCH_3.3V_TS_EN GPP_B21/GSPI1_MISO 100K_0201_5%
GPP_B22 Strap Pin CA30 CH22 ISH_I2C1_SDA
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA CJ22 ISH_I2C1_SCL ISH_I2C1_SDA <38>
RC710,RC711 placed closer to PCH.CNV_BRI_PRX_DTX_1P8 ISH_I2C1_SCL <38>
2
1.8V CK20 GPP_D8/ISH_I2C1_SCL
D <52> CNV_BRI_PRX_DTX_1P8 1 2 33_0201_5% CNV_RGI_PTX_DRX_1P8 Strap Pin 1.8V CG19 GPP_F5/CNVI_BRI_RSP ISH CJ27 ISH_I2C2_SDA D
<52> CNV_RGI_PTX_DRX_1P8_R AC@RC710
1 2 33_0201_5% CNV_BRI_PTX_DRX_1P8 1.8V CJ20 GPP_F6/CNVI_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA CJ29 ISH_I2C2_SCL ISH_I2C2_SDA <74>
<52> CNV_BRI_PTX_DRX_1P8_R AC@RC711
CNV_RGI_PRX_DTX_1P8 GPP_F4/CNVI_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <74>
1.8V CH19
<52> CNV_RGI_PRX_DTX_1P8 GPP_F7/CNVI_RGI_RSP CM24
GPP_D13/ISH_UART0_RXD TS_RST# <38>
CN23
CR12 GPP_D14/ISH_UART0_TXD CM23 RTD3_CIO_PWR_EN TOUCH_SCREEN_DET# <38>
<38> 3MM_CAM_DET# CP12 GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# CR24 TBT_DET# RTD3_CIO_PWR_EN <42>
<38> P_SENSOR_PWR_SAVE# SMART_SPK_DET1# CN12 GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT#
<74> SMART_SPK_DET1# TS_INT# CM12 GPP_C22/UART2_RTS# CG12 SC_CAGE_DET#
<38> TS_INT# GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD SC_CAGE_DET# <66>
CH12 TBT_DET#
CM11 GPP_C13/UART1_TXD/ISH_UART1_TXD CF12 LCD_CBL_DET#
TS <38> I2C0_SDA_TS CN11 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# CG14 PCH_TBT_PERST# LCD_CBL_DET# <38>
<38> I2C0_SCL_TS GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS# PCH_TBT_PERST# <42> HIGH NON TR
CK12 BW35 ISH_ACC1_INT
TP <63> I2C1_SDA_TP GPP_C18/I2C1_SDA GPP_A18/ISH_GP0 ISH_ACC1_INT <66>
CJ12 I2C , UART BW34
<63> I2C1_SCL_TP GPP_C19/I2C1_SCL GPP_A19/ISH_GP1 CA37 ISH_TABLE_MODE# ISH_ACC2_INT <66>
LOW TR
CF27 GPP_A20/ISH_GP2 CA36 ISH_TABLE_MODE# <58>
GPP_H4/I2C2_SDA GPP_A21/ISH_GP3 ISH_NB_MODE# ISH_ALS_INT# <38>
CF29 CA35
<58,66> 360_SENSOR_DET# GPP_H5/I2C2_SCL GPP_A22/ISH_GP4 ISH_NB_MODE# <58,74>
CA34
GPP_A23/ISH_GP5 ISH_LID_CL#_NB <74>
CH27 BW37
CH28 GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF# ISH_LID_CL#_TAB <74>
GPP_H7/I2C3_SCL
CJ30
CJ31 GPP_H8/I2C4_SDA
GPP_H9/I2C4_SCL
PU OPTION TO AVOID RSP SIGNALS
+1.8V_PRIM FROM FLOATING IN CASE INTERNAL PUS NOT ENABLED IN A0
20K_0201_5% 2 1 @ RC724 CNV_BRI_PRX_DTX_1P8
20K_0201_5% 2 1 @ RC733 CNV_RGI_PRX_DTX_1P8
C C
+3.3V_ALW_PCH
TPM_PIRQ# option circuit PRIM_CORE_OPT_DIS 1 2
606576-cml-pch-lp-eds-vol1-rev1p0 @ RC862 10K_0201_5%
1 2 TPM_PIRQ#_A7 TBT_RTD3_WAKE# 1 2
<66> TPM_PIRQ#
@ RC455 0_0201_5% External pull-up is required. Recommend 100 kohm if RC21 10K_0201_5%
pulled up to 3.3V or 75 kohm if pulled up to 1.8V. GPP_D12 1 2
This strap should sample HIGH. There should NOT be RC847 100K_0201_5%
1 2 TPM_PIRQ#_B20 ISH_TABLE_MODE# 1 2
@ RC456 0_0201_5%
any on-board device driving it to opposite direction @ RC551 10K_0201_5%
during strap sampling. ISH_LID_CL#_NB 1 2
RC884 10K_0201_5%
ISH_LID_CL#_TAB 1 2
RC885 10K_0201_5%
RTD3_CIO_PWR_EN 1 2
@ RC753 10K_0201_5%
+3.3V_RUN
LCD_CBL_DET# 1 2
RC749 100K_0201_5%
IR_CAM_DET# 1 2
RC345 100K_0201_5%
+1.8V_PRIM SC_CAGE_DET# 1 2
RC886 100K_0201_5%
2
+3.3V_RUN
RC842
20K_0201_5% ISH_I2C0_SDA 1 2
RC306 2.2K_0201_5%
ISH_I2C0_SCL 1 2
1
RC307 2.2K_0201_5%
CNV_RGI_PTX_DRX_1P8_R ISH_I2C2_SDA 1 2
B @ RC363 1K_0201_5% B
1
ISH_I2C2_SCL 1 2
@ RC832
4.7K_0201_5%
Reserved for wake on voice +3.3V_ALW_PCH
@ RC362 1K_0201_5%
2
PCH_TBT_PERST# pull up power rail

change to +3.3V_RUN from +3.3V_ALW_PCH +3.3V_RUN
follow 604311_CML_U_DDR4_TDK_SCH_Rev1p0
@ UC9
5
MC74VHC1G32DFT2G_SC70-5
A weak external pull-up is required. PRIM_CORE_OPT_DIS 1 PCH_TBT_PERST# 1 2
P
+3.3V_ALW_PCH When a RF companion chip is connected to the INB 4 RTD3@ RC557 10K_0201_5%
PCH CNVi interface, the device internal pull down SIO_SLP_S0# O VR_LPM_R# <87>
resistor will pull the strap load to enable CNVi interface. 2
<11,17,66,79,87> SIO_SLP_S0# INA
G PCH_TBT_PERST# 1 2
1 2 NRB_BIT M.2 CNV Mode Select @ RC754 10K_0201_5%
3
RC831 4.7K_0201_5%

HIGH Integrated CNVi disable.
LOW Integrated CNVi enable. ISH_NB_MODE# 1 2
No Reboot RC549 10K_0201_5%
ISH_TABLE_MODE# 1 2
HIGH No REBOOT RC550 10K_0201_5%
LOW(DEFAULT) REBOOT ENABLE* 1 2
*PCH will disable the @ RC867 0_0201_5%
TCO Timer system reboot feature. This function is 1 2
useful when running ITP/XDP.
@ RC660 0_0201_5%
+3.3V_ALW_PCH
1
@ RC52
10K_0201_5%
+3.3V_ALW_PCH
2
ONE_DIMM#
A A
1
1
RC53
@ RC46 10K_0201_5%
4.7K_0201_5%
2
2
GPP_B22

Boot BIOS Strap Bit BBS DIMM Detect
HIGH LPC HIGH 1 DIMM
CPU(4/14)GSPI,I2C,UART,ISH
LOW(DEFAULT) SPI LOW 2 DIMM NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
CPU@
UC1H
PCIE / USB3.1 / SATA
BW9 CB5
D <42> PCIE_PRX_DTX_N5 BW8 PCIE5_RXN/USB31_5_RXN PCIE1_RXN/USB31_1_RXN CB6 D
<42> PCIE_PRX_DTX_P5 BW4 PCIE5_RXP/USB31_5_RXP PCIE1_RXP/USB31_1_RXP CA4
<42> PCIE_PTX_DRX_N5 BW3 PCIE5_TXN/USB31_5_TXN PCIE1_TXN/USB31_1_TXN CA3
<42> PCIE_PTX_DRX_P5 PCIE5_TXP/USB31_5_TXP PCIE1_TXP/USB31_1_TXP
BU6 BY8
<42> PCIE_PRX_DTX_N6 BU5 PCIE6_RXN/USB31_6_RXN PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN BY9 USB3_PRX_RD_DTX_N2 <74>
<42> PCIE_PRX_DTX_P6 BU4 PCIE6_RXP/USB31_6_RXP PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP CA2 USB3_PRX_RD_DTX_P2 <74>
<42> PCIE_PTX_DRX_N6 BU3 PCIE6_TXN/USB31_6_TXN PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN CA1 USB3_PTX_DRX_N2 <74> -----> Ext USB3 Port 1 charge
<42> PCIE_PTX_DRX_P6 PCIE6_TXP/USB31_6_TXP PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB3_PTX_DRX_P2 <74>
TR ---> BT7 BY7
<42> PCIE_PRX_DTX_N7 BT6 PCIE7_RXN PCIE3_RXN/USB31_3_RXN BY6 USB3_PRX_RD_DTX_N3 <74>
<42> PCIE_PRX_DTX_P7 BU2 PCIE7_RXP PCIE3_RXP/USB31_3_RXP BY4 USB3_PRX_RD_DTX_P3 <74>
<42> PCIE_PTX_DRX_N7 BU1 PCIE7_TXN PCIE3_TXN/USB31_3_TXN BY3 USB3_PTX_DRX_N3 <74> -----> Ext USB3 Port 2
<42> PCIE_PTX_DRX_P7 PCIE7_TXP PCIE3_TXP/USB31_3_TXP USB3_PTX_DRX_P3 <74>
BU9 BW6
<42> PCIE_PRX_DTX_N8 BU8 PCIE8_RXN PCIE4_RXN/USB31_4_RXN BW5 USB3_PRX_DTX_N4 <74>
<42> PCIE_PRX_DTX_P8 BT4 PCIE8_RXP PCIE4_RXP/USB31_4_RXP BW2 USB3_PRX_DTX_P4 <74>
<42> PCIE_PTX_DRX_N8 BT3 PCIE8_TXN PCIE4_TXN/USB31_4_TXN BW1 USB3_PTX_DRX_N4 <74> -----> M.2 3042(LTE)
<42> PCIE_PTX_DRX_P8 PCIE8_TXP PCIE4_TXP/USB31_4_TXP USB3_PTX_DRX_P4 <74>
BP5 CE3
<70> PCIE_PRX_DTX_N9 BP6 PCIE9_RXN USB2N_1 CE4 USB20_N1 <44>
<70> PCIE_PRX_DTX_P9 BR2 PCIE9_RXP USB2P_1 USB20_P1 <44> -----> Type C (PD)
Card Reader RTS5242-----> <70> PCIE_PTX_DRX_N9 BR1 PCIE9_TXN CE1
<70> PCIE_PTX_DRX_P9 PCIE9_TXP USB2N_2 CE2 USB20_N2 <44>
<52> PCIE_PRX_DTX_N10
BN6 USB2P_2 USB20_P2 <44> -----> Type C (PD)
BN5 PCIE10_RXN CG3
<52> PCIE_PRX_DTX_P10 BR4 PCIE10_RXP USB2N_3 CG4 USB20_N3 <74>
Solder Down 1216 WLAN ---> <52> PCIE_PTX_DRX_N10 BR3 PCIE10_TXN USB2P_3 USB20_P3 <74> -----> Ext USB2 Port 1
<52> PCIE_PTX_DRX_P10 PCIE10_TXP CD3
BN10 USB2N_4 CD4 USB20_N4 <74>
BN8 PCIE11_RXN/SATA0_RXN USB2P_4 USB20_P4 <74> -----> Ext USB2 Port 2
BN4 PCIE11_RXP/SATA0_RXP CG5
C BN3 PCIE11_TXN/SATA0_TXN USB2N_5 CG6 C
PCIE11_TXP/SATA0_TXP USB2P_5
BL6 CC1
<74> PCIE_PRX_DTX_N12 BL5 PCIE12_RXN/SATA1A_RXN USB2N_6 CC2 USB20_N6 <38>
<74> PCIE_PRX_DTX_P12 BN2 PCIE12_RXP/SATA1A_RXP USB2P_6 USB20_P6 <38> -----> Camera
M.2 3042(WWAN)---> <74> PCIE_PTX_DRX_N12 BN1 PCIE12_TXN/SATA1A_TXN USB2.0
CG8
<74> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP USB2N_7 CG9 USB20_N7 <74>
BK6 USB2P_7 USB20_P7 <74> -----> M2 3042(WWAN)
<68> PCIE_PRX_DTX_N13 BK5 PCIE13_RXN CB8
<68> PCIE_PRX_DTX_P13 BM4 PCIE13_RXP USB2N_8 CB9 USB20_N8 <66>
<68> PCIE_PTX_DRX_N13 BM3 PCIE13_TXN USB2P_8 USB20_P8 <66> -----> USH
<68> PCIE_PTX_DRX_P13 PCIE13_TXP CH5
BJ6 USB2N_9 CH6 USB20_N9 <66>
<68>
<68>
PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14
BJ5 PCIE14_RXN
PCIE14_RXP
USB2P_9 USB20_P9 <66> ----> Reserved FPR in PB
BL2 CC3
<68> PCIE_PTX_DRX_N14 BL1 PCIE14_TXN USB2N_10 CC4 USB20_N10 <52>
<68> PCIE_PTX_DRX_P14 PCIE14_TXP USB2P_10 USB20_P10 <52>-----> M.2 2230(BT)
M2 2280 SSD (4 Lane) ---> BG5 CC5 USBCOMP RC47 1 2 113_0201_1%
<68> PCIE_PRX_DTX_N15 PCIE15_RXN/SATA1B_RXN USB2_COMP USB2_ID
PCIe Gen3 x 4 <68> PCIE_PRX_DTX_P15
BG6
BL4 PCIE15_RXP/SATA1B_RXP USB_ID
CE8
CC6
@ RC3371
VBUSSENSE RC49 1
2 0_0201_5%
2 1K_0201_5%
<68> PCIE_PTX_DRX_N15 BL3 PCIE15_TXN/SATA1B_TXN USB_VBUSSENSE
<68> PCIE_PTX_DRX_P15 PCIE15_TXP/SATA1B_TXP CK6 USB_OC0#
BE5 GPP_E9/USB2_OC0#/GP_BSSB_CLK CK5 USB_OC1# USB_OC0# <74>
<68> PCIE_PRX_DTX_N16 BE6 PCIE16_RXN/SATA2_RXN GPP_E10/USB2_OC1#/GP_BSSB_DI CK8 USB_OC2# USB_OC1# <74>
Reserve
<68> PCIE_PRX_DTX_P16 BJ4 PCIE16_RXP/SATA2_RXP GPP_E11/USB2_OC2# CK9 USB_OC3# Reserve
<68> PCIE_PTX_DRX_N16 BJ3 PCIE16_TXN/SATA2_TXN GPP_E12/USB2_OC3#
<68> PCIE_PTX_DRX_P16 PCIE16_TXP/SATA2_TXP CP8
GPP_E4/DEVSLP0 CR8
PCIE_RCOMPN CE6 GPP_E5/DEVSLP1 CM8 M3042_DEVSLP <74>
RC50 1 2 100_0201_1% PCIE_RCOMPP CE5 PCIE_RCOMP_N GPP_E6/DEVSLP2 M2280_DEVSLP <68>
PCIE_RCOMP_P CN8 HDD_DET#
CR28 GPP_E0/SATAXPCIE0/SATAGP0 CM10 M3042_PCIE#_SATA
B CP28 GPP_H12/M2_SKT2_CFG0 GPP_E1/SATAXPCIE1/SATAGP1 CP10 M2280_PCIE_SATA# M3042_PCIE#_SATA <58> B
CN28 GPP_H13/M2_SKT2_CFG1 GPP_E2/SATAXPCIE2/SATAGP2 M2280_PCIE_SATA# <68>
CM28 GPP_H14/M2_SKT2_CFG2 CN7
GPP_H15/M2_SKT2_CFG3 GPP_E8/SATALED#/SPI1_CS1# SECURE_BIO <38>
AR3
RSVD_BSCAN
+3.3V_RUN
M2280_PCIE_SATA# 2 1
RC764 10K_0201_5%
HDD_DET# 2 1
RC765 100K_0201_5%
M3042_PCIE#_SATA 2 1
RC766 10K_0201_5%
M3042_PCIE#_SATA @ RC521 1 2 1K_0201_5%
M2280_PCIE_SATA# @ RC730 1 2 1K_0201_5% +3.3V_ALW_PCH
USB_OC3# RC836 2 1 10K_0201_5%

USB_OC0# RC837 2 1 10K_0201_5%
USB_OC1# RC839 2 1 10K_0201_5%
USB_OC2# RC838 2 1 10K_0201_5%
A A
CPU(5/14)PCIE,USB,SATA
1.0
5 4 3 2 1
5 4 3 2 1
Refer RVP is 200K ohm +-1% CC21

604311_CML_U_DDR4_RVP_TDK_SCH_Rev0p9
1 2
15P_0201_50V8J
3
4
RC59 YC1
CPU@ 200K_0201_1% 24MHZ_12PF_8Y24000034-X
UC1J XTAL24_IN_CPU 1 2 XTAL24_IN
1
2
0418 Follow Dorest intel recommend change CLKREQ pull up to 20K from 10K. CLOCK SINGNALS EMI@ RC728 33_0201_1%
1
AW2 AU1 CLK_ITPXDP_N 1
<74> CLK_PCIE_N0 CLKOUT_PCIE_N0 CLKOUT_ITPXDP_N CLK_ITPXDP_P PAD~D @ T473
AY3 AU2 1
<74> CLK_PCIE_P0 CLKOUT_PCIE_P0 CLKOUT_ITPXDP_P PAD~D @ T472
CF32 CC22
M.2 3042 WWAN---> <74> CLKREQ_PCIE#0
RC189 2 1 20K_0201_5% GPP_B5/SRCCLKREQ0# BT32 SUSCLK XTAL24_OUT_CPU 1 2 XTAL24_OUT 1 2
+3.3V_RUN GPD8/SUSCLK SUSCLK <52,68>
BC1 EMI@ RC729 33_0201_1%
D <52> CLK_PCIE_N1 CLKOUT_PCIE_N1 XTAL24_IN_CPU D
BC2 CK3 @ CC93 2 1 0.1U 16V K X5R 0201 15P_0201_50V8J
<52> CLK_PCIE_P1 CLKOUT_PCIE_P1 XTAL_IN XTAL24_OUT_CPU
CE32 CK2
Solder Down 1216 WLAN---> <52> CLKREQ_PCIE#1
RC522 2 1 20K_0201_5% GPP_B6/SRCCLKREQ1# XTAL_OUT
+3.3V_RUN XCLK_BIASREF
BD3 CJ1 RC402 1 2 60.4_0201_1%
<68> CLK_PCIE_N2 CLKOUT_PCIE_N2 XCLK_BIASREF REFCLK_CNV
BC3 CM3 1 2
<68> CLK_PCIE_P2 CLKOUT_PCIE_P2 CLKIN_XTAL REFCLK_CNV_L <52>
CF30 @ESD@ LC5 BLM15BD121SN1D_2P~D
M.2 2280 SSD---> <68> CLKREQ_PCIE#2
RC525 2 1 20K_0201_5% GPP_B7/SRCCLKREQ2# BN31 PCH_RTCX1 LC5 place near CPU side Refer RVP is 10M ohm +-5% CC23
+3.3V_RUN Intel Timdaway feedback190718: 604311_CML_U_DDR4_RVP_TDK_SCH_Rev0p9
BH3 RTCX1 BN32 PCH_RTCX2 PCH_RTCX1 1 2
Quasar base PCH, so 38.4MHz is no longer needed
BH4 CLKOUT_PCIE_N3 RTCX2 PCH_RTCX2
RC523 2 1 20K_0201_5% CLKREQ_PCIE#3 CE31 CLKOUT_PCIE_P3 BR37 SRTCRST# RC56 1 2 20K_0201_5% 12P_0201_50V8J
+3.3V_RUN GPP_B8/SRCCLKREQ3# SRTCRST# +RTC_CELL_PCH
BR34
1
BA1 RTCRST# CC24 1 2 1U_0201_6.3V6M
<70> CLK_PCIE_N4 CLKOUT_PCIE_N4
BA2 RC66 YC2
<70> CLK_PCIE_P4 CLKOUT_PCIE_P4 PCH_RTCRST# <58,79> 10M_0201_5%
Card Reader ---> CE30 32.768KHZ_12.5PF_9H03200042-X
<70> CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4# PCH_RTCRST#
+3.3V_RUN RC51 2 1 20K_0201_5% RC57 1 2 20K_0201_5% ESD Request ESR MAX=50k ohm
2
BE1 0419 ESD YuHeng: follow Intel recommendation
1
<42> CLK_PCIE_N5 BE2 CLKOUT_PCIE_N5 CC25 1 2 1U_0201_6.3V6M CC26
<42> CLK_PCIE_P5 CF31 CLKOUT_PCIE_P5 REFCLK_CNV 1 2 PCH_RTCX2_R 1 2
TR---> <42> CLKREQ_PCIE#5
2 1 20K_0201_5% GPP_B10/SRCCLKREQ5#
+3.3V_RUN RC190 @ RC532 0_0201_5%
12P_0201_50V8J
CML-U_BGA1528 10 of 20 1 2 1
1 2 @ESD@
CC1477
@ CMOS1 SHORT PADS~D 4.7P_0201_50V8B
2
CMOS1 footprint change to SHORTPADS-NPM
CMOS1 must take care short & touch risk on layout placement REFCLK_CNV 2 1
RC751 10K_0201_5%
ESD Request:place near CPU side SUSCLK 1 2
@ RC48 1K_0201_5%
+3.3V_ALW_DSW
2 1 LAN_W AKE# PCH_PLTRST# 1 2

PLTRST_TPM# <66>
RC323 10K_0201_5% @ RC60 0_0201_5%
2 1 PCH_PCIE_W AKE# PCH_PLTRST#_AND 1 2 1 2 SIO_SLP_SUS# 1 2

+3.3V_ALW_PCH <18> VCCDSW_EN_GPIO PCH_PRIM_EN <78,87>
RC67 1K_0201_5% @ RC738 0_0201_5% DS3@ RC445 0_0201_5% DS3@ RC441 0_0201_5%
C C
@NDS3@ DC1
+1.05V_VCCST 2 1 VCCDSW _EN_Q 1 2
<58> VCCDSW_EN
UC7
5
2 1 VCCST_PW RGD RB751S-40_SOD523-2 0_0201_5%

RC71 1K_0201_5% PCH_PLTRST# 1 2 1 @NDS3@ RC442
P
B 4 PCH_PLTRST#_AND @NDS3@ RC329 0_0603_5%

O PCH_PLTRST#_AND <38,42,52,68,70,74>
2 RC329 Co-lay with DC1;RC330 Co-lay with DC2
A
G
2 1 PCH_PW ROK
RC439RC440RE536RC215RC441RC442
@ RC536 10K_0201_5% MC74VHC1G08EDFT2G_SC70-5 @ RC65 @NDS3@ RC330 1 2 0_0603_5%
3
100K_0201_5%
Support DS3 V X V X V X @NDS3@ DC2
1 2
<63,85> ALW_PWRGD_3V_5V VCCDSW_EN_Q <8>
2
No Support DS3 X V X V X V RB751S-40_SOD523-2
'V' mean POP, 'X' mean DE-POP

+3.3V_ALW_PCH
3.3V_CAM_EN# 1 2
PCH Signal Glitch Free Implementation Requirements RC834 100K_0201_5%
(607109_CML_U_PDG_Rev1p0 P.170)
2 1 SIO_SLP_SUS#
100K_0201_5% RC229 +3.3V_ALW_DSW
2 1 Refer checklist BATLOW# use 8.2K to 10K pull up
0.33U_0201_25V6K @ CC1465 607109_CML_U_SchChecklist_Rev1p0
PCH_BATLOW # 1 2
2 1 SIO_SLP_S4#
S4 power side PD need @,need check AC_PRESENT
RC72 10K_0201_5%
100K_0201_5% RC232 1 2
2 1 RC555 10K_0201_5%
0.33U_0201_25V6K @ CC1467 CPU@ AC_PRESENT is setting OD on EC side, so need pull up.
UC1K +RTC_CELL_PCH
2 1 SIO_SLP_S3# SYSTEM POWER MANAGEMENT
100K_0201_5% RC231 PCH_PLTRST# BJ35 BJ37 SIO_SLP_S0#
SYS_RESET# GPP_B13/PLTRST# GPP_B12/SLP_S0# SIO_SLP_S0# <9,17,66,79,87>
2 1 CN10 BU36 INTRUDER# 1 2
<79> SYS_RESET# PCH_RSMRST#_AND SYS_RESET# GPD4/SLP_S3# SIO_SLP_S3# <17,42,59,79>
0.33U_0201_25V6K @ CC1468 BR36 BU27 RC69 1M_0201_5%
<63,79> PCH_RSMRST#_AND RSMRST# GPD5/SLP_S4# SIO_SLP_S5# SIO_SLP_S4# <17,79,86,87>
BT29
2 1 SIO_SLP_A# @ RC77 2 1 1K_0201_5% H_CPUPW RGD AR2 GPD10/SLP_S5# SIO_SLP_S5# <79>
100K_0201_5% RC233 RC78 1 2 62_0201_5% VCCST_PW RGD_CPU BJ2 PROCPWRGD BU29 +3.3V_ALW_PCH
<59,79> VCCST_PWRGD VCCST_PWRGOOD SLP_SUS# SIO_SLP_SUS# <58>
B 2 1 BT31 B
0.33U_0201_25V6K @ CC1469 CR10 SLP_LAN# BT30
<58> SYS_PW ROK SYS_PWROK GPD9/SLP_WLAN# SIO_SLP_A# SIO_SLP_WLAN# <78>
BP31 BU37 VRALERT# 1 2
SIO_SLP_W LAN# <88,96> PCH_PWROK PCH_PWROK GPD6/SLP_A# SIO_SLP_A# <79>
2 1 BP30 RC73 10K_0201_5%
<58> PCH_DPWROK DSW_PWROK
100K_0201_5% RC234 BU28
GPD3/PWRBTN# SIO_PWRBTN# <58>
2 1 BV34 BU35
GPP_A13/SUSWARN#/SUSPWRDACK GPD1/ACPRESENT PCH_BATLOW # AC_PRESENT <58>
0.33U_0201_25V6K @ CC1470 BY32 BV36
GPP_A15/SUSACK# GPD0/BATLOW#
2 1 SIO_SLP_S5# BU30
<42,58,59> PCH_PCIE_WAKE# LAN_W AKE# WAKE#
100K_0201_5% @ RC230 BU32 BR35 INTRUDER#
2 1 PCH_PLTRST# BU34 GPD2/LAN_WAKE# INTRUDER#
100K_0201_5% @ RC237 GPD11/LANPHYPC CC37 3.3V_CAM_EN# INPUT3VSEL
GPP_B11/EXT_PWR_GATE# CC36 VRALERT# 3.3V_CAM_EN# <38>
2
GPP_B2/VRALERT#
BT27 Strap PinINPUT3VSEL RC452
INPUT3VSEL 4.7K_0201_5%
1
External pull-up or pull-down is required.

This strap should only be used for
+3.3V_ALW_PCH specific targeted 1S battery systems.
2 1 SIO_SLP_S0# 3.0V Select

100K_0201_5% RC763 HIGH 3.3V supply is 3.0V +/- 5%
LOW 3.3V supply is 3.3V +/- 5%
1 2 SYS_RESET#
<79> XDP_DBRESET#
@ RC243 0_0201_5%
SYS_RESET#
A
RC215 A
POP NO Support Deep sleep

DE-POP Support Deep sleep 1
@ESD@
CC302
PCH_DPW ROK 1 2 PCH_RSMRST#_AND 0.1U_0201_25V6K
H_CPUPW RGD VCCST_PW RGD PCH_PLTRST#_AND 2
0_0201_5%
1
1 @NDS3@ RC215
100P_0201_50V8J
100P_0201_50V8J
0.01U_0201_25V7K
@ CC266
100K_0201_5%
DS3@ RC220
100K_0201_5%
RC75
1 1 1
ESD@ DELL CONFIDENTIAL/PROPRIETARY
CC300
ESD@
CC301
ESD@
CC196 ESD Request:place near CPU side

2 0.047U_0201_10V6K
2
2 2 2
For ESD solution TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
CPU(6/14)CLK,PM,RTC
ESD Request:place near CPU side
5 4 3 2 1
5 4 3 2 1
CPU@
UC1G
RC92 1 2 33_0201_5% HDA_SYNC BN34 CH36
D <74> HDA_SYNC_R 1 2 HDA_BIT_CLK BN37 HDA_SYNC/I2S0_SFRM GPP_G0/SD_CMD CL35 CAM_MIC_CBL_DET# <38> D
EMI@ RC93 33_0201_5%
<74> HDA_BIT_CLK_R 1 2 HDA_SDOUT BN36 HDA_BCLK/I2S0_SCLK GPP_G1/SD_DATA0 CL36 TBT_CIO_PLUG_EVENT#
RC561 33_0201_5%
<74> HDA_SDOUT_R 1 2 BN35 HDA_SDO/I2S0_TXD GPP_G2/SD_DATA1 CM35 TBT_CIO_PLUG_EVENT# <42>
RC562 1K_0201_5%
<79> ME_FWP_PCH <74> HDA_SDIN0 BL36 HDA_SDI0/I2S0_RXD AUDIO SDIO / SDXC GPP_G3/SD_DATA2 CN35 CONTACTLESS_DET#
1 2 33_0201_5% HDA_RST# BL35 HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G4/SD_DATA3 CH35 HOST_SD_WP# CONTACTLESS_DET# <66>
RC560
<74> HDA_RST#_R CK23 HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G5/SD_CD# CK36 AUD_PWR_EN HOST_SD_WP# <70>
GPP_D23/I2S_MCLK GPP_G6/SD_CLK CK34 SMART_SPK_DET0#
BL37 GPP_G7/SD_WP SMART_SPK_DET0# <74>
HDA_BIT_CLK_R BL34 I2S1_SFRM/SNDW2_CLK
I2S1_TXD/SNDW2_DATA
1 CNV_RF_RESET#_1P81.8V CJ32
RF@
<52> CNV_RF_RESET#_1P8 CH32 GPP_H1/I2S2_SFRM/CNVI_BT_I2S_BCLK/CNVI_RF_RESET#
CC27
47P_0201_50V8J CLKREQ_CNV_1P8 1.8VCH29 GPP_H0/I2S2_SCLK/CNVI_BT_I2S_SCLK
2 <52> CLKREQ_CNV_1P8 CNVI_EN# CH30 GPP_H2/I2S2_TXD/CNVI_BT_I2S_SDI/MODEM_CLKREQ
<52> CNVI_EN# GPP_H3/I2S2_RXD/CNVI_BT_I2S_SDO BW36
Close to RC93
CP24 GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 BY31 2.7MM_CAM_DET# ISH_P_SENSOR_INT# <38>
CN24 GPP_D19/DMIC_CLK0/SNDW4_CLK GPP_A16/SD_1P8_SEL 2.7MM_CAM_DET# <38>
GPP_D20/DMIC_DATA0/SNDW4_DATA CK33
KB_DET# CK25 SD_1P8_RCOMP CM34 SD_RCOMP RC116 1 2 200_0201_1%
<63> KB_DET# CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
GPP_D18/DMIC_DATA1/SNDW3_DATA
SPKR Strap Pin CF35
<74> SPKR GPP_B14/SPKR
1 2
<58> SIO_SLP_SUS#_R
@ RC926 0_0402_5%
Reserved for support TOP SWAP feature
C C
+3.3V_ALW_PCH
2 1 CAM_MIC_CBL_DET#
RC725 100K_0201_5%
0418 Follow Dorest intel recommend change pull up to 100K from 10K.
+3.3V_ALW_PCH RF Request. Place near CPU side (Intel MOW)

2 1 SPKR
@ RC183 8.2K_0201_5% HDA_RST# HDA_SDOUT
+3.3V_RUN

2 1 CONTACTLESS_DET#
RC278 100K_0201_5%
TOP SWAP STRAP
AUD_PWR_EN 1 1
2 1 ENABLE @RF@ @RF@
B RC279 100K_0201_5%
HIGH CC331 CC333 B
2 1 HOST_SD_WP# LOW(DEFAULT) DISABLE 2.2P_0201_50V8C 2.2P_0201_50V8C
RC292 10K_0201_5% 2 2
+3.3V_ALW_PCH
2 1 KB_DET#
RC288 100K_0201_5%
Intel Timdaway feedback190718:
For CLKREQ, CML RVP kept PD resistor footprint but
didn't pop in BOM
1 2 CLKREQ_CNV_1P8
@ RC752 71.5K_0201_1%
1 2 CNV_RF_RESET#_1P8
RC640 75K_0201_5%
1 2 CNVI_EN#
RC868 75K_0201_5%
A A
CPU(7/14)MISC,JTAG,HDA,SDIO
1.0
5 4 3 2 1
5 4 3 2 1
1 2 CFG0 1 2 CFG7
@ RC120 1K_0201_5% @ RC411 1K_0201_5%
EAR-STALL/NOT STALL RESET PEG DEFER TRAINING

SEQUENCE AFTER PCU PLL IS LOCKED
1: (DEFAULT) PEG TRAIN IMMEDIATELY
CFG0 1:(DEFAULT)NORMAL OPERATION; NO STALL CFG7 FOLLOWING XXRESETB DE ASSERTION
0:STALL 0: PEG WAIT FOR BIOS FOR TRAINING
D D
1 2 CFG1 1 2 CFG8
@ RC405 1K_0201_1% @ RC412 1K_0201_1%
UC1Q
ALLOW THE USE OF CFG ON LOCKED UNITS RESERVED SIGNALS
PCH/ PCH LESS MODE SELECTION
1: DISABLED(DEFAULT); IN THIS CASE, CFG WILL BE
CFG0 T4 F37 1 @ T16
CFG_0 RSVD_TP_1 F34 1 PAD~D
1: (DEFAULT) NORMAL OPERATION DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS AND @ T17
CFG1 0: PCH-LESS MODE
CFG8 0: EENABLED; CFG WILL BE CFG1 R4 RSVD_TP_2 CP36 1 PAD~D
AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT CFG_1 IST_TRIG PAD~D @ T18
CFG2 T3 CN36 1 @ T19
R3 CFG_2 RSVD_TP_3 PAD~D
<79> CFG3 CFG_3
CFG4 J4
CFG5 M4 CFG_4 BJ36
1 2 CFG2 1 2 CFG9 CFG6 J3 CFG_5 RSVD_12 BJ34
@ RC406 1K_0201_1% @ RC413 1K_0201_1% CFG7 M3 CFG_6 RSVD_13
CFG8 R2 CFG_7 BK34 1
CFG9 N2 CFG_8 TP_1 BR18 1 PAD~D @ T20
CFG10 R1 CFG_9 TP_2 PAD~D @ T21
CFG11 N1 CFG_10
CFG12 J2 CFG_11
PCI EXPRESS STATIC LANE REVERSAL NO SVID PROTOCOL CAPABLE VR CONNECTED CFG13 L2 CFG_12 BT9
FOR ALL PEG PORTS CFG14 J1 CFG_13 RSVD_14 BT8
1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT CFG15 L1 CFG_14 RSVD_15
CFG2 1: (DEFAULT)NORMAL OPERATION CFG9 0: NO VR SUPPORTING SVID IS PRESENT. CFG_15 BP8
0: LANE REVERSAL THE CHIP WILL NOT GENERATE (OR RESPOND TO) SVID ACTIVITY 1 CFG16 L3 RSVD_16 BP9
T467 @ PAD~D CFG_16 RSVD_17
1 CFG18 N3
T471 @ PAD~D CFG_18
1 CFG17 L4 CR4 1
C T466 @ PAD~D CFG_17 RSVD_18 PAD~D @ T360 C
1 CFG19 N4
1 2 CFG10 T469 @ PAD~D CFG_19
1 2 CFG3 Refer RVP CFG_RCOMP Keep 49.9 ohm to GND CP3
@ RC407 1K_0201_1% @ RC414 1K_0201_1% 604311_CML_U_DDR4_RVP_TDK_SCH_Rev0p9 RSVD_19 CR3
2 1 CFG_RCOMP AB5 RSVD_20
RC624 49.9_0201_1% CFG_RCOMP
2 1 ITP_PMODEStrap Pin W4
+1.05V_PRIM_XDP ITP_PMODE
RC125 1.5K_0201_5%
WEAK INTERNAL PU CG2
CG1 RSVD_1
SAFE MODE BOOT <79> ITP_PMODE RSVD_2
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
0 : ENABLED 1: POWER FEATURES ACTIVATED DURING RESET Refer RVP CFG_RCOMP Keep 1.5K ohm to 1.05V_XDP AT3
CFG3 SET DFX ENABLED BIT IN DEBUG INTERFACE MSR CFG10 0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT 604311_CML_U_DDR4_RVP_TDK_SCH_Rev0p9 RSVD_21 AU3
1 : DISABLED ACTIVATED) RSVD_22
H4
H3 RSVD_3
RSVD_4 AN1
BV24 RSVD_23 AN2
1 2 CFG4 1 2 CFG11 RSVD_5 RSVD_24
BV25
RC723 1K_0201_1% @ RC415 1K_0201_1% RSVD_6 AN4
RSVD_25 AN3
RSVD_26
0: AN EXTERNAL DISPLAY PORT DEVICE PORT IS CONNECTED TO THE EMBEDDED PORT AL2
1: NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT RSVD_27 AL1
RSVD_28
DMI AC COUPLING - JUST A PLACE HOLDER.
DISPLAY PORT PRESENCE STRAP NOT APPLICABLE FOR ULX-ULT
AL4
1:(DEFULT) RSVD_29 AL3
CFG4 0: ENABLED CFG11 DMI WILL BE CONFIGURED AS HALF SWING DC COUPLED
1: DISABLED; RSVD_30
0:DMI WILL BE CONFIGURED AS FULL SWING AC COUPLED
BK36 BP34 1
BK35 RSVD_7 TP_3 BP36 PAD~D @ T361
RSVD_8 VSS_434 BP35 1
W3 TP_4 PAD~D @ T363
1 2 CFG5 1 2 CFG12 RSVD_9
B AM4 B
@ RC409 1K_0201_1% @ RC416 1K_0201_1% RSVD_10
AM3
RSVD_11
CR35 1
1 2 CFG6 RSVD_31 PAD~D @ T423
@ RC410 1K_0201_1% PM SYNC LEGACY
CFG12 1: (DEFAULT) PMSYNC 2.0

0 : LEGACY
E1 SKTOCC# @ RC5651 2 0_0201_5%
SKTOCC#
PCIE PORT BIFURCATION STRAPS 1 2 CFG13
CPU@
@ RC417 1K_0201_1%
11: DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED
10: DEVICE1 FUNTION 1, ENABLED DEVICE 1 FUNCTION2 DISABLED
CFG[6:5]
PCH/ PCH LESS MODE SELECTION PMSYNC AYNC MODE- PM SYNC
01: DEVICE1 FUNTION 1, DISABLED, DEVICE 1 FUNCTION2 ENABLED 1: (DEFAULT)SYNCHCRONOUS (1 24 MHZ CYCLE PER BIT)
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED
CFG13 0: ASYNC - 4-24MHZ CYCLES PER BIT
1 2 CFG14 1 2 CFG15
@ RC418 1K_0201_1% @ RC419 1K_0201_1%
A A
CFG14 CFG15 Compal Electronics, Inc.
CPU(8/14)CFG,RSVD
1.0
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCST
RC2181 2 1K_0201_1% H_THERMTRIP#_R
RC2191 2 49.9_0201_1% H_CATERR# CPU@

UC1D
CPU MISC JTAG
H_CATERR# AA4 T6
CATERR# PROC_TCK CPU_XDP_TCLK <79>
AR1 U6
+1.05V_VCCSTG <58> PECI_EC PROCHOT#_R PECI PROC_TDI CPU_XDP_TDI <79>
<44,58,84,88> PROCHOT# PROCHOT# RC84 1 2 499_0201_1% Y4 Y5
H_THERMTRIP#_R PROCHOT# PROC_TDO CPU_XDP_TDO <79>
@ RC5591 2 0_0201_5% BJ1 T5
<59> H_THERMTRIP# THRMTRIP# PROC_TMS CPU_XDP_TRST# CPU_XDP_TMS <79>
AB6
RC5581 2 1K_0201_1% PROCHOT# 1 XDP_OBS0_R U1 PROC_TRST# 1 2
T468 @ PAD~D XDP_OBS1_R BPM#_0
1 U2 W6 @ RC86 51_0201_5%
T470 @ PAD~D XDP_OBS2_R BPM#_1 PCH_TCK PCH_JTAG_TCK <79>
T366 @ PAD~D 1 U3 U5
XDP_OBS3_R BPM#_2 PCH_TDI PCH_JTAG_TDI <79>
D 1 U4 W5 D
T367 @ PAD~D BPM#_3 PCH_TDO PCH_JTAG_TDO <79>
P5
PCH_TMS Y6 PCH_JTAG_TMS <79>
+3.3V_RUN PCH_TRST# XDP_JTAGX CPU_XDP_TRST# <79>
P6
PCH_JTAGX XDP_JTAGX <79>
1 2
MEM_INTERLEAVED +1.05V_VCCSTG
CE9 W2 @ RC87 1K_0201_5%
TOUCH_SCREEN_PD# GPP_E3/CPU_GP0 PROC_PREQ# CPU_XDP_PREQ# <79>
@ RC82 1 2 10K_0201_5% CN3 W1
<38> TOUCH_SCREEN_PD# TOUCHPAD_INTR# CB34 GPP_E7/CPU_GP1 PROC_PRDY# CPU_XDP_PRDY# <79>
TOUCHPAD_INTR# <58,63> TOUCHPAD_INTR# PCH_BT_RADIO_DIS# GPP_B3/CPU_GP2
2 1 CC35
<52> PCH_BT_RADIO_DIS# GPP_B4/CPU_GP3
RC567 100K_0201_5%
CPU_POPIRCOMP BP27
PCH_POPIRCOMP BW25 PROC_POPIRCOMP
PCH_OPIRCOMP
+3.3V_ALW_PCH
1
49.9_0201_1%
49.9_0201_1%
1 2 PCH_BT_RADIO_DIS#
RC106
RC107
RC510 100K_0201_5%
2
MEM_INTERLEAVED
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX
@ESD@ CC303
@ESD@ CC304
@ESD@ CC305
1
C C
0.1U_0201_25V6K
0.1U_0201_25V6K
0.1U_0201_25V6K
1 1 1
RC844
100K_0201_5%
2 2 2
2
DIMM TYPE
HIGH Interleave
ESD request,Place near CPU side.

LOW Non-Interleave
B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(9/14)XDP
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
PSC(Primary side cap) : Place as close to the package as possible

BSC(Backside cap) : Place on secondary side, underneath the package
+VCC_CORE +VCC_CORE
CPU@
Component placement order: UC1L
CPU POWER 1 OF 4
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source AN9 AW24
AN10 VCCCORE_28 VCCCORE_67 AW25
AN24 VCCCORE_29 VCCCORE_68 AW26
+VCC_CORE: 0.55~1.5V, 29A AN26
AN27
VCCCORE_30
VCCCORE_31
VCCCORE_69
VCCCORE_70
AW27
AY24
+VCC_EDRAM: 1V, 2.5A AP2
AP9
VCCCORE_32
VCCCORE_33
VCCCORE_71
VCCCORE_72
AY26
BA5
D AP24 VCCCORE_34 VCCCORE_73 BA7 D
+V1.8S_EDRAM: 1.8V, 50mA - REMOVE AP26 VCCCORE_35
VCCCORE_36
VCCCORE_74
VCCCORE_75
BA8
AR5 BA25
+VCC_EOPIO: 0.8~1V, 2A - REMOVE AR6 VCCCORE_37
VCCCORE_38
VCCCORE_76
VCCCORE_77
BA27
AR7 BB2
CPU@ AR8 VCCCORE_39 VCCCORE_78 BB26
UC1O AR10 VCCCORE_40 VCCCORE_79 BC5
RESERVED SIGNALS AR25 VCCCORE_41 VCCCORE_80 BC6
K12 AA24 AR27 VCCCORE_42 VCCCORE_81 BC7
K14 RSVD_32 RSVD_60 AA26 AT9 VCCCORE_43 VCCCORE_82 BC9
K15 RSVD_33 RSVD_61 AB25 AT24 VCCCORE_44 VCCCORE_83 BC10
K17 RSVD_34 RSVD_62 AC24 AT26 VCCCORE_45 VCCCORE_84 BC26
K18 RSVD_35 RSVD_63 AC25 AU5 VCCCORE_46 VCCCORE_85 BC27
K20 RSVD_36 RSVD_64 AC26 AU6 VCCCORE_47 VCCCORE_86 BD5
L25 RSVD_37 RSVD_65 AD24 AU7 VCCCORE_48 VCCCORE_87 BD8
M24 RSVD_38 RSVD_66 AD26 AU8 VCCCORE_49 VCCCORE_88 BD10
M26 RSVD_39 RSVD_67 V25 VCCEOPIO_SENSE 1 AU9 VCCCORE_50 VCCCORE_89 BD25
P24 RSVD_40 RSVD_68 T25 VSSEOPIO_SENSE 1 PAD~D @ T368 AU24 VCCCORE_51 VCCCORE_90 BD27
P26 RSVD_41 RSVD_69 A35 PAD~D @ T369 AU25 VCCCORE_52 VCCCORE_91 BE9
R24 RSVD_42 RSVD_70 D34 AU26 VCCCORE_53 VCCCORE_92 BE24
R25 RSVD_43 RSVD_71 N5 AU27 VCCCORE_54 VCCCORE_93 BE25
R26 RSVD_44 RSVD_72 AV2 VCCCORE_55 VCCCORE_94 BE26 +VCC_CORE
V24 RSVD_45 AV5 VCCCORE_56 VCCCORE_95 BE27
W25 RSVD_46 AV7 VCCCORE_57 VCCCORE_96 BF2
RSVD_47 VCCCORE_58 VCCCORE_97
Close CPU
1
Y24 AV10 BF9
+1.05V_VCCSTG Y25 RSVD_48 AV27 VCCCORE_59 VCCCORE_98 BF24 RC150
G2 RSVD_49 AW5 VCCCORE_60 VCCCORE_99 BF26 100_0201_1%
G1 RSVD_50 AW6 VCCCORE_61 VCCCORE_100 BG27 0_0201_5%
RSVD_51 VCCCORE_62 VCCCORE_101
1
1 2 C34 AW7 @ RC430
2
@ RC436 0_0201_5% @ RC420 G3 RSVD_52 AW8 VCCCORE_63 AN6 VCCSENSE_R 1 2
100_0201_1% G4 RSVD_53 AW9 VCCCORE_64 VCC_SENSE AN5 VSSSENSE_R 1 2 VCC_SENSE_IA <88>
1 A34 RSVD_54 AW10 VCCCORE_65 VSS_SENSE VSS_SENSE_IA <88>
T364 @ PAD~D RSVD_55 VCCCORE_66
1
C 1 B35 AA3 H_CPU_SVIDALRT# 0_0201_5% C
T365 @ PAD~D
2
2 1 AJ27 RSVD_56 1 +VCC_CORE_G0 BB9 VIDALERT# @ RC429 RC151

RSVD_57 T371 @ PAD~D +VCC_CORE_G1 RSVD_74 VIDSCLK_R
1@ RC564 0_0201_5%AH26 1 BC24 AA1 100_0201_1%
T465 @ PAD~D RSVD_58 T372 @ PAD~D +VCC_CORE_G2 RSVD_75 VIDSCK
L5 1 AY9
RSVD_59 T373 @ PAD~D +VCC_CORE_G3 RSVD_76 VIDSOUT_R
1 BB24 AA2
T374 @ PAD~D
2
RSVD_77 VIDSOUT
CML-U_BGA1528 15 of 20 Y3
RSVD_78
BG3 +1.05V_VCCSTG_R @ RC153 2 1 0_0201_5%
VCCSTG_3 +1.05V_VCCSTG
1V@0.05A
+1.05V_VCCST
SVID ALERT
1
RC154 CAD Note: Place the PU resistors close to CPU
56_0201_1% RC154 close to CPU 1000 - 1500mils
B B
2
2 1 H_CPU_SVIDALRT#
<88> VIDALERT_N
220_0201_5% RC155
+1.05V_VCCST
SVID DATA
1
CAD Note: Place the PU resistors close to CPU
RC156 RC156close to CPU 1000 - 1500mils
100_0201_1%
2
0_0201_5% 2 1 @ RC157 VIDSOUT_R
<88> VIDSOUT
+1.05V_VCCST
SVID CLK
1
@ CAD Note: Place the PU resistors close to CPU
RC158 RC158close to CPU 1000 - 1500mils
43_0201_5%
2
0_0201_5% 2 1 @ RC159 VIDSCLK_R
<88> VIDSCLK
A A
CPU(10/14)PWR-VCC CORE
1.0
5 4 3 2 1
5 4 3 2 1
D D
+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A
+VCC_GT +VCC_GT
1.5V@54A
CPU@
UC1M
CPU POWER 2 OF 4
A5 H12
A6 VCCGT_1 VCCGT_61 H14
A15 VCCGT_6 VCCGT_66 J7
B3 VCCGT_10 VCCGT_70 J17
B4 VCCGT_11 VCCGT_71 J20
B6 VCCGT_12 VCCGT_72 K2
B8 VCCGT_13 VCCGT_73 K11
B11 VCCGT_14 VCCGT_74 L7
B14 VCCGT_15 VCCGT_75 L8
B17 VCCGT_16 VCCGT_76 L10 +VCC_CORE
B20 VCCGT_17 VCCGT_77 M9
C2 VCCGT_18 VCCGT_78 N7
C C6 VCCGT_20 VCCGT_80 N9 C
C8 VCCGT_22 VCCGT_82 P2
C11 VCCGT_23 VCCGT_83 P8
C12 VCCGT_24 VCCGT_84 R9
C14 VCCGT_25 VCCGT_85 T8
C18 VCCGT_28 VCCGT_88 U8
C20 VCCGT_29 VCCGT_89 U10
D4 VCCGT_30 VCCGT_90 V9
D7 VCCGT_31 VCCGT_91 W8
D11 VCCGT_32 VCCGT_92 W9
D12 VCCGT_33 VCCGT_93 AA9
D14 VCCGT_34 VCCCORE_1 AB2
D20 VCCGT_38 VCCCORE_5 AC8
E4 VCCGT_39 VCCCORE_6 AD9
F5 VCCGT_40 VCCCORE_7 AE8
F8 VCCGT_43 VCCCORE_10 AF2
F17 VCCGT_46 VCCCORE_13 AG8
F20 VCCGT_47 VCCCORE_14 AG9
G11 VCCGT_48 VCCCORE_15 AH9
G12 VCCGT_49 VCCCORE_16 AJ8
G14 VCCGT_50 VCCCORE_17 AJ10
G15 VCCGT_51 VCCCORE_18 AK2 +VCC_GT
B G17 VCCGT_52 VCCCORE_19 AK9 B
G18 VCCGT_53 VCCCORE_20 AL8
G20 VCCGT_54 VCCCORE_21 AL9
VCCGT_55 VCCCORE_22
Close CPU
1
H5 AL10
H6 VCCGT_56 VCCCORE_23 AM8 RC160
H7 VCCGT_57 VCCCORE_24 V2 100_0201_1%
H8 VCCGT_58 VCCCORE_25 Y8
H11 VCCGT_59 VCCCORE_26 Y10
2
VCCGT_60 VCCCORE_27
E3 VCCGT_SENSE_R@ RC632 1 2 0_0201_5%
VCCGT_SENSE D2 VSSGT_SENSE_R@ RC631 1 2 0_0201_5% VCC_SENSE_GT <88>
VSSGT_SENSE VSS_SENSE_GT <88>
1
RC161
100_0201_1%
2
A A
CPU(11/14)PWR-VCCGT
1.0
5 4 3 2 1
5 4 3 2 1
+1.2V_DDR: 1.2V, 3.5A

+1.05V_VCCST: 1.5V, 120mA
+1.05V_VCCSTG: 1.5V, 40mA RF Request
+VCCPLL_OC: 1.2V, 260mA +1.2V_MEM
+0.95VS_VCCIO: 0.85~0.95V, 3.1A
+VCC_SA: 1.15V, 5.1A
RF@ CC1478
1200P_0402_50V7K
680P_0201_50V7K
RF@ CC1479
1 1
D D
2 2
CPU@ +0.95VS_VCCIO
+1.2V_MEM UC1N
+1.05V_VCCST CPU POWER 3 OF 4
AK24 0.95V@3.1A
1.2V@3.5AAD36 VCCIO_1 AK26
PSC AH32 VDDQ_1 VCCIO_2 AL24
1V@0.12A
close to package AH36 VDDQ_2 VCCIO_3 AL25
AM36 VDDQ_3 VCCIO_4 AL26
1U_0201_6.3V6M
place as close as CPU VDDQ_4 VCCIO_5
1 AN32 AL27
AW32 VDDQ_5 VCCIO_6 AM25
PDG0.7 P.495 0402/0201 AY36 VDDQ_6 VCCIO_7 AM27
CC28
BE32 VDDQ_7 VCCIO_8 BH24
+1.2V_MEM +VCCPLL_OC 2 BH36 VDDQ_8 VCCIO_9 BH25
+VCCPLL_OC source 1 2
R32
Y36
VDDQ_9
VDDQ_10
VDDQ_11
VCCIO_10
VCCIO_11
VCCIO_12
BH26
BH27
BJ24
@ RZ119 0_0402_5% VCCIO_13 BJ26
VCCIO_14 BP16 +VCC_SA
BC28 VCCIO_15 BP18
UZ27 RSVD_73 VCCIO_16
1 BP11 BG8 1.15V@5.1A
2 1 2 VIN1 +1.05V_VCCSTG BP2 VCCST_1 VCCSA_1 BG10
CZ102 1U_0201_6.3V6M VIN2 VCCST_2 VCCSA_2 BH9
7 6 VCCSA_3 BJ8
VIN thermal VOUT BG1 VCCSA_4 BJ9
2 VCCSTG_1 VCCSA_5
3 BG2 BJ10
+5V_ALW VBIAS VCCSTG_2 VCCSA_6 +0.95VS_VCCIO
CZ303 BK8
VCCSTG_EN 1 2 VCCPLL_EN 4 5 BL27 VCCSA_7 BK25
0.1U_0201_10V6K
@ RZ120 0_0201_5% ON GND 1 BM26 VCCPLL_OC_1 VCCSA_8 BK27
+1.05V_VCCSTG VCCPLL_OC_2 VCCSA_9 BL8 Close CPU
VCCSA_10
1
EM5201V_DFN3X3-8 BR11 BL9
1 2 BT11 VCCPLL_1 VCCSA_11 BL10 RC163
<11,17,42,59,79> SIO_SLP_S3# VCCPLL_2 VCCSA_12
@ RZ1418 0_0201_5% 1V@0.04A BL24 100_0201_1%
close to package VCCSA_13 BL26
VCCSA_14 BM24
1U_0201_6.3V6M
2
1 2 VCCSA_15 BN25
<9,11,66,79,87> SIO_SLP_S0# 1 VCCSA_16
@ RZ1419 0_0201_5%
CC29
PDG0.7 P.495 0402/0201 BP28 VCCIO_SENSE
VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE <87>
BP29
C 2 VSSIO_SENSE VSSIO_SENSE <87> C
BE7 @ RC425 1 2 0_0201_5%

VSSSA_SENSE BG7 @ RC426 1 2 0_0201_5%
VCCSA_SENSE
1
100_0201_1%
RC164
CML-U_BGA1528 14 of 20 RC165
100_0201_1%
+VCCPLL_OC 1 2
+VCC_SA
2
RC166 100_0201_1%
PSC 1.2V@0.26A +1.05V_VCCST
close to package
PSC
1V@0.12A
1U_0201_6.3V6M
close to package
VSS_SENSE_SA <88>
1
+1.05V_VCCSTG source VCC_SENSE_SA <88>
CC430
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
+1.05V_VCCSTG +1.05V_VCCST
CC96
1 1 1
2
CC31
CC1462
1 2
+1.05V_PRIM @ RZ151 0_0402_5%
pop option with UZ19 2 2 2
1
+3.3V_RUN 2 1 JUMP@ PDG0.7 P.495 0402/0201

CZ105 1U_0201_6.3V6M UZ19 PJP2
1 PAD-OPEN1x1m
2 VIN1
VIN2
2
RZ1422 +5V_ALW 7 6 +1.05V_VCCSTG_C1 2

100K_0201_5% VIN thermal VOUT CZ106
3 0.1U_0201_10V6K
VBIAS
1
+3.3V_ALW 4 5
1 2 ON GND
<6,87> CPU_C10_GATE#
0_0201_5% EM5201V_DFN3X3-8
@ RZ1420 CML_U PDG rev1.0 P.537
4.4mohm/6A
5
TR=12.5us@Vin=1.05V VCCIO:
1
Primary Side cap
P
B 4 VCCSTG_EN
O
<17,58,59,78,87> RUN_ON
2
A CML_U PDG rev1.0 P.537 4x 1uF 0201
G
B B
UZ35 VDDQ:
3
MC74VHC1G08EDFT2G_SC70-5
Primary Side cap Primary or Secondary Side
1x 22uF 0603 + 6x 10uF 0402 +0.95VS_VCCIO
6x 10uF 0402
@ RZ320 1 2 0_0201_5%
Secondary Side cap Placeholder Only
4x 1uF 0402/0201 + 3x 10uF 0402 Primary Side PDG0.7 P.495 0201 4x 0402
+1.2V_MEM
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1
PDG0.7 P.495 22U 0603,10U 0402
CC1458
CC1459
CC1460
CC1461
Primary Side
2 2 2 2
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
+1.05V_VCCST source 1 1 1 1 1 1 1
CC32
CC33
CC34
CC35
CC36
CC37
CC38
@ RC864
0_0603_5% PDG0.7 P.495 0402
2 1
RC864 Co-lay 2 2 2 2 2 2 2 Primary or Secondary Side
JUMP@ with PJP1
+1.05V_PRIM PJP1
UZ21 2 1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
+1.05V_VCCST 1 1 1 1 1 1
2 1 1
CC51
CC52
CC234
CC235
CC236
CC237
CZ100 1U_0201_6.3V6M 2 VIN1
VIN2 PAD-OPEN1x1m PDG0.7 P.495 1U 0402/0201,10U 0402
+5V_ALW 7 6 +1.05V_VCCST_C 1 2
Secondary Side 2 2 2 2 2 2
VIN thermal VOUT CZ101 0.1U_0201_10V6K
3
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
VBIAS
VCCST_EN 1 1 1 1 1 1 1
1 2 4 5 PDG0.7 P.495 0402
CC45
CC46
CC195
CC1454
CC1455
CC1456
CC1457
<11,17,42,59,79> SIO_SLP_S3#
@ RZ1416 0_0201_5% ON GND Placeholder
1 2 EM5201V_DFN3X3-8 2 2 2 2 2 2 2
<11,79,86,87> SIO_SLP_S4#
@ RZ1417 0_0201_5%
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1
CC39
CC40
CC41
CC42
1 2
4.4mohm/6A
<17,58,59,78,87> RUN_ON
@ RZ1423 0_0201_5% TR=12.5us@Vin=1.05V
2@ 2@ 2@ 2@
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU(12/14)PWR-VCCIO,MEM
5 4 3 2 1
5 4 3 2 1
close UC1 <100mil

+1.05V_PRIM +1.05V_APLL
@ LC1 1 2 MIP1608P2R2MBP_2P
+1.05V_PRIM +3.3V_ALW_PCH
22U_0402_6.3V6M
22U_0402_6.3V6M
1 1
@ CC85
@ CC86
1 2
@ RC422 0_0603_5% +1.8V_PRIM 1.05V@1.625A 3.3V@0.199A
2 2 1.8V@0.696A CC67/CC68 close to BP20
1
1U_0201_6.3V6M
CC98 close to CP17 1 1 CPU@ CC75 close to CP29
1U_0201_6.3V6M
1U_0201_6.3V6M
PDG0.7 P.531 0201 UC1P PDG0.7 P.531 0201 reserve
@ CC75
1
1U_0201_6.3V6M
D D
BP20 CPU POWER 4 OF 4
CC68
CC67
BW16 VCCPRIM_1P05_1 CB16 2
CC98
2 2 BW18 VCCPRIM_1P05_2 VCCPRIM_3P3_8
2 BW19 VCCPRIM_1P05_3 +RTC_CELL_PCH
BY16 VCCPRIM_1P05_4
LC1, LC2, LC3 CIS no symbol(SHI0000X800) PDG0.7 P.531 0201 CA14
CC15
VCCPRIM_1P05_5
VCCPRIM_1P05_6 VCCRTC
BR23
BY20
3.0V@0.002A
1 1 CC72/CC73 close to BR23
1U_0201_6.3V6M
+1.05V_PRIM
0.1U_0201_6.3V6K
CD15 VCCPRIM_1P8_1 VCCPRIM_1P05_14 BP24 DCPRTC PDG0.7 P.531 0201
CD16 VCCPRIM_1P8_2 DCPRTC
CC72
CC73
1U_0201_6.3V6M
0809 BSOD +3.3V_ALW_PCH CP17 VCCPRIM_1P8_3 PDG0.7 P.531 0201 reserve
VCCPRIM_1P8_4 1
+1.05V_PRIM Pop LC2 INDUCTOR,CC100 22U_0603 +1.05V_CLK BR20 2 2
@ CC76
depop RC175 VCCPRIM_1P05_15 +1.05V_PRIM
Add CC103 22U_0603 3.3V@0.199A CB22
CB23 VCCPRIM_3P3_1 BT12
VCCPRIM_3P3_2 VCCAPLL_1P05_2 +1.05V_APLL 2
LC2 1 2 MIP1608P2R2MBP_2P CC22
CC23 VCCPRIM_3P3_3 BP14
VCCPRIM_3P3_4 VCCA_BCLK_1P05
1.05V@0.009A +1.05V_PRIM
@ RC175 CD22
0.01_0603_1% CD23 VCCPRIM_3P3_5 BR14
1 1 1 1 1.05V@0.102A PCH Internal VRM
1U_0201_6.3V6M
1U_0201_6.3V6M
+1.05V_APLL
22U_0603_6.3V6M
22U_0603_6.3V6M
1 2 +1.05V_PRIM_CORE CP29 VCCPRIM_3P3_6 VCCAPLL_1P05_3
VCCPRIM_3P3_7 close to BP24 +VCCDPHY_1P24
BU12 1.05V@0.034A
CC83
CC70
CC103
CC100
VCCA_SRC_1P05 +1.05V_PRIM
1.05V@4.26A BU15
4.7U_0402_6.3V6M
2 2 2 2 BU22 VCCPRIM_CORE_1 CP5
CC66 close to BV18 VCCPRIM_CORE_2 VCCA_XTAL_1P05
1.05V@0.034A +1.05V_CLK PCH Internal VRM
PDG0.7 P.531 0201 reserve BV15 1 close to CP25
BV16 VCCPRIM_CORE_3 BY24 1.24V@0.61A
CC84
1
1U_0201_6.3V6M
VCCPRIM_CORE_4 VCCDPHY_1P24_1 +VCCLDOSRAM_1P24
BV18 CA24 PDG0.7 P.531 0402
@ CC66
BV19 VCCPRIM_CORE_5 VCCDPHY_1P24_2
CC103/CC83/CC70 close to CP5 VCCPRIM_CORE_6 PCH Internal VRM
PDG0.7 P.531 0201 BV20 BY23 2
2 BV22 VCCPRIM_CORE_7 VCCDPHY_1P24_3 CA23
CC100/CC103 one is close to the VCCPRIM_CORE_8 VCCDPHY_1P24_4
BW20 CP25 +3.3V_ALW_DSW
CPU and the other is far from the CPU. +VCCPDSW_1P05 VCCPRIM_CORE_9 VCCDPHY_EC_1P24
BW22
CA12 VCCPRIM_CORE_10 BT23
VCCPRIM_CORE_11 VCCDSW_3P3_2
3.3V@0.199A
1.05V@0.024A CA16
CA18 VCCPRIM_CORE_12 BR12 1.05V@0.027A
PCH Internal VRM 1
1U_0201_6.3V6M
VCCPRIM_CORE_13 VCCA_19P2_1P05 +1.05V_PRIM
close to BT24 CA19
@ CC1463
1
1U_0201_6.3V6M
PDG0.7 P.531 0201 CA20 VCCPRIM_CORE_14
VCCPRIM_CORE_15
CC1463 close to BR24
CB12 +1.8V_PRIM
CC65
CB14 VCCPRIM_CORE_16 2 PDG0.7 P.531 0201 reserve
2 CB15 VCCPRIM_CORE_17 CC18
C PDG rev0.7 P.539,CC71 close to BV12 1.8V@0.696A C
+1.05V_APLL VCCPRIM_CORE_18 VCCPRIM_1P8_5 CC19
Place an 22uF edge cap not more than VCCPRIM_1P8_6
12 mm away measuring from package edge. BT24 CD18 1
1U_0201_6.3V6M
VCCDSW_1P05 VCCPRIM_1P8_7 CD19
@ CC1464
+1.05V_MPHYGT BU14 VCCPRIM_1P8_8 CP23
1.05V@0.102A VCCPRIM_1P05_7 VCCPRIM_1P8_9 CC1464 close to CP23
PDG0.7 P.531 0201 reserve
1.05V@2.878A BV12 BW23 3.3V@0.199A 2
+1.05V_PRIM +1.05V_MPHYGT VCCPRIM_MPHY_1P05_1 VCCPRIM_3P3_9 +3.3V_ALW_PCH
JUMP@ BW12
22U_0603_6.3V6M
PJP3 PDG0.7 P.531 0603 1 BW14 VCCPRIM_MPHY_1P05_2
1 2 BY12 VCCPRIM_MPHY_1P05_3
CC71
BY14 VCCPRIM_MPHY_1P05_4
PAD-OPEN1x3m VCCPRIM_MPHY_1P05_5 BP23
VCCPRIM_3P3_10
3.3V@0.199A +3.3V_ALW_PCH
2 1.05V@0.152A BV2
+1.05V_AMPHYPLL
+1.05V_MPHYGT source +1.05V_APLL 1.05V@0.102A BR15
VCCAMPHYPLL_1P05
VCCAPLL_1P05_1
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
CB36
CB35
CORE_VID0
CORE_VID1
<87>
<87>
+1.05V_PRIM
1.05V@0.129A CC12
VCCDUSB_1P05
+3.3V_ALW_PCH LC4 3.3V@0.001A BR24
+3.3V_ALW_DSW VCCDSW_3P3_1
close UC1 <120mil BLM18EG221TN1D_2P~D
0809 BSOD 1 2 VCCHDA 3.3V@0.006A BT20
+1.05V_MPHYGT Pop LC3 INDUCTOR,CC102 22U_0603 +1.05V_AMPHYPLL VCCHDA
depop RC173
Add CC104 22U_0603 2 +3.3V_ALW_PCH 3.3V@0.002A BV23
VCCSPI
1
LC3 1 2 MIP1608P2R2MBP_2P RC845 @RF@ RF@ CC95 BT18

+1.05V_PRIM VCCPRIM_1P05_8
0_0201_5% 2.2P_0201_25V BT19
@ RC173 1 BU18 VCCPRIM_1P05_9
1 1 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.01_0603_1% BU19 VCCPRIM_1P05_10

+1.05V_MPHYGT
2
1 2 BT22 VCCPRIM_1P05_11
CC80
CC69
CC104
CC102
+1.05V_PRIM VCCPRIM_1P05_12
1 BP22
2 2 2 2 RF@ CC77 VCCPRIM_1P05_13
2.2P_0201_25V BV14
VCCPRIM_MPHY_1P05_6
2 CML-U_BGA1528 16 of 20
CC104/CC80/CC69 close to BV2
PDG0.7 P.531 0201
CC102/CC104 one is close to the
B CPU and the other is far from the CPU. B
+3.3V_ALW_DSW +3.3V_ALW_PCH
1 2
@NDS3@ RC440 0_0402_5% +3.3V_ALW
1 2
@ RC214 0_0201_5%
DS3@ QC7
NTK3139PT1G_SOT723-3
1 2 +3.3V_ALW_DSW_R 1 3
D
DS3@ RC439 0_0402_5%

1
22U_0402_6.3V6M
22U_0402_6.3V6M
499K_0201_1%
DS3@ RC432
1 1
G
2
@ CC279
@ CC280
2 2
2
2
0.1U_0201_25V6K
100K_0201_5%
DS3@ RC431
49.9K_0201_1%
DS3@ RC433
1
1
@ CC340
2
RC439RC440RE536RC215RC441RC442
2
A Support DS3 V X V X V X A
1
D
NX7002BKW_SOT323-3
DS3@ QC6
No Support DS3 X V X V X V 2
VCCDSW_EN_GPIO <11>
G
'V' mean POP, 'X' mean DE-POP S
3
If support NDS3,depop the part PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
QC6 QC7 RC432 RC433 RC439 RC431 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU(13/14)PCH PWR
1.0
5 4 3 2 1
5 4 3 2 1
CPU@ CPU@
UC1R UC1S CPU@
D GND 1 OF 3 GND 2 OF 3 UC1T D
CR34 BL7 BT35 BY25 GND 3 OF 3
BT5 VSS_290 VSS_362 AE25 D6 VSS_145 VSS_217 J18 N6 CF23
BY5 VSS_291 VSS_363 BM33 AL32 VSS_146 VSS_218 AU32 B37 VSS_1 VSS_73 V4
CP35 VSS_292 VSS_364 CM5 BT36 VSS_147 VSS_219 BY28 CB3 VSS_2 VSS_74 BE30
CM37 VSS_293 VSS_365 AE27 D8 VSS_148 VSS_220 J21 P10 VSS_3 VSS_75 CF28
CK37 VSS_294 VSS_366 BM35 AL7 VSS_149 VSS_221 AV25 B5 VSS_4 VSS_76 W10
AW1 VSS_295 VSS_367 CM9 D9 VSS_150 VSS_222 BY33 CB33 VSS_5 VSS_77 BE31
CM1 VSS_296 VSS_368 AE30 AM10 VSS_151 VSS_223 J24 P3 VSS_6 VSS_78 CF3
BD6 VSS_297 VSS_369 BM36 BU11 VSS_152 VSS_224 AV28 B7 VSS_7 VSS_79 W27
AY4 VSS_298 VSS_370 CN13 E23 VSS_153 VSS_225 BY35 CB4 VSS_8 VSS_80 CF4
B34 VSS_299 VSS_371 AE7 AM28 VSS_154 VSS_226 J33 P33 VSS_9 VSS_81 W30
E35 VSS_300 VSS_372 BM9 E27 VSS_155 VSS_227 AV3 B9 VSS_10 VSS_82 BF3
A4 VSS_301 VSS_373 CN17 AM33 VSS_156 VSS_228 BY36 CB7 VSS_11 VSS_83 CG33
AE24 VSS_302 VSS_374 AF27 BU23 VSS_157 VSS_229 J36 P36 VSS_12 VSS_84 W7
AE26 VSS_303 VSS_375 BN30 E29 VSS_158 VSS_230 AV33 BA10 VSS_13 VSS_85 BF33
AF25 VSS_304 VSS_376 CN21 AM35 VSS_159 VSS_231 J6 CC11 VSS_14 VSS_86 CG7
AG24 VSS_305 VSS_377 AF3 BU24 VSS_160 VSS_232 AV36 P4 VSS_15 VSS_87 BF36
AG26 VSS_306 VSS_378 BN7 E31 VSS_161 VSS_233 C1 BA28 VSS_16 VSS_88 Y26
AH24 VSS_307 VSS_379 CN25 BU25 VSS_162 VSS_234 K21 P7 VSS_17 VSS_89 BF4
AH25 VSS_308 VSS_380 AF30 E33 VSS_163 VSS_235 AV4 BA3 VSS_18 VSS_90 CH31
B2 VSS_309 VSS_381 CN29 AN25 VSS_164 VSS_236 C21 CC20 VSS_19 VSS_91 Y27
B36 VSS_310 VSS_382 AF33 BU7 VSS_165 VSS_237 K22 R27 VSS_20 VSS_92 BG25
C36 VSS_311 VSS_383 BP15 E9 VSS_166 VSS_238 AV6 BB3 VSS_21 VSS_93 Y30
C37 VSS_312 VSS_384 AF36 AN28 VSS_167 VSS_239 C25 CC25 VSS_22 VSS_94 BG28
CN1 VSS_313 VSS_385 AF4 BV11 VSS_168 VSS_240 K24 R28 VSS_23 VSS_95 CJ11
CN2 VSS_314 VSS_386 CN5 F12 VSS_169 VSS_241 AV8 BB33 VSS_24 VSS_96 Y33
CN37 VSS_315 VSS_387 AF7 AN29 VSS_170 VSS_242 C29 CC28 VSS_25 VSS_97 CJ14
CP2 VSS_316 VSS_388 BP25 F15 VSS_171 VSS_243 K25 R29 VSS_26 VSS_98 Y35
C D1 VSS_317 VSS_389 CN9 AN30 VSS_172 VSS_244 AW28 BB36 VSS_27 VSS_99 BH28 C
A32 VSS_318 VSS_390 AG10 F18 VSS_173 VSS_245 C33 CC31 VSS_28 VSS_100 CJ19
F33 VSS_319 VSS_391 BP3 AN31 VSS_174 VSS_246 K27 R30 VSS_29 VSS_101 Y7
A3 VSS_320 VSS_392 CP1 BV3 VSS_175 VSS_247 AW29 BB4 VSS_30 VSS_102 BH29
BJ7 VSS_321 VSS_393 BP32 F2 VSS_176 VSS_248 C4 CC7 VSS_31 VSS_103 CJ23
CJ36 VSS_322 VSS_394 CP11 AN7 VSS_177 VSS_249 K28 R31 VSS_32 VSS_104 BH32
A36 VSS_323 VSS_395 AH27 BV31 VSS_178 VSS_250 AW3 BC25 VSS_33 VSS_105 CJ28
BK10 VSS_324 VSS_396 BP33 F21 VSS_179 VSS_251 C9 CD11 VSS_34 VSS_106 BH33
CJ4 VSS_325 VSS_397 CP13 AN8 VSS_180 VSS_252 K29 T27 VSS_35 VSS_107 CJ33
AB27 VSS_326 VSS_398 AH28 BV33 VSS_181 VSS_253 AW30 CD12 VSS_36 VSS_108 BH35
BK2 VSS_327 VSS_399 BP4 F24 VSS_182 VSS_254 CA11 T30 VSS_37 VSS_109 CJ35
CK1 VSS_328 VSS_400 CP15 BV4 VSS_183 VSS_255 K3 BC29 VSS_38 VSS_110 BP19
AB3 VSS_329 VSS_401 AH29 F3 VSS_184 VSS_256 AW31 CD14 VSS_39 VSS_111 BR16
BK28 VSS_330 VSS_402 BP7 AP3 VSS_185 VSS_257 CA15 T33 VSS_40 VSS_112 BY18
AB30 VSS_331 VSS_403 CP19 BW11 VSS_186 VSS_258 K30 T35 VSS_41 VSS_113 BY19
BK3 VSS_332 VSS_404 AH30 F4 VSS_187 VSS_259 AY33 BC32 VSS_42 VSS_114 CC16
CK4 VSS_333 VSS_405 CP21 AP33 VSS_188 VSS_260 CA22 CD24 VSS_43 VSS_115 BU16
AB33 VSS_334 VSS_406 AH31 BW15 VSS_189 VSS_261 K31 T36 VSS_44 VSS_116 CC14
BK33 VSS_335 VSS_407 BR19 G21 VSS_190 VSS_262 AY35 CD25 VSS_45 VSS_117 BR22
CK7 VSS_336 VSS_408 CP27 AP36 VSS_191 VSS_263 K32 T7 VSS_46 VSS_118 BU20
AB36 VSS_337 VSS_409 AH33 G27 VSS_192 VSS_264 B12 BC8 VSS_47 VSS_119 CD20
BK4 VSS_338 VSS_410 BR25 AP4 VSS_193 VSS_265 K4 CE33 VSS_48 VSS_120 BT14
CL2 VSS_339 VSS_411 AH35 G33 VSS_194 VSS_266 B15 U26 VSS_49 VSS_121 BP12
AB4 VSS_340 VSS_412 CP37 AR28 VSS_195 VSS_267 CA25 BD28 VSS_50 VSS_122 CB24
BK7 VSS_341 VSS_413 AJ25 G35 VSS_196 VSS_268 K9 CE35 VSS_51 VSS_123 CC24
CM13 VSS_342 VSS_414 BT15 G36 VSS_197 VSS_269 B18 U7 VSS_52 VSS_124 J5
AB7 VSS_343 VSS_415 AJ28 AT33 VSS_198 VSS_270 CB11 BD33 VSS_53 VSS_125 U24
BL25 VSS_344 VSS_416 BT16 BW24 VSS_199 VSS_271 L27 CE36 VSS_54 VSS_126 BD7
CM17 VSS_345 VSS_417 CP9 G9 VSS_200 VSS_272 B21 V26 VSS_55 VSS_127 AR4
B AC10 VSS_346 VSS_418 AJ7 AT35 VSS_201 VSS_273 L33 BD35 VSS_56 VSS_128 AU4 B
BL28 VSS_347 VSS_419 CR2 H21 VSS_202 VSS_274 B23 CE7 VSS_57 VSS_129 AW4
CM21 VSS_348 VSS_420 AK3 AT36 VSS_203 VSS_275 L35 V27 VSS_58 VSS_130 BA6
AC27 VSS_349 VSS_421 CR36 BW7 VSS_204 VSS_276 B25 BD36 VSS_59 VSS_131 BC4
BL29 VSS_350 VSS_422 AK33 H27 VSS_205 VSS_277 CB18 CF11 VSS_60 VSS_132 BE4
CM25 VSS_351 VSS_423 D21 AT4 VSS_206 VSS_278 L36 V3 VSS_61 VSS_133 BE8
AC30 VSS_352 VSS_424 AK36 BY11 VSS_207 VSS_279 B27 BE10 VSS_62 VSS_134 BA4
BL30 VSS_353 VSS_425 BT25 AU10 VSS_208 VSS_280 CB19 CF14 VSS_63 VSS_135 BD4
CM29 VSS_354 VSS_426 D25 BY15 VSS_209 VSS_281 L6 V30 VSS_64 VSS_136 BG4
BL31 VSS_355 VSS_427 AK4 H9 VSS_210 VSS_282 B29 BE28 VSS_65 VSS_137 CJ2
CM31 VSS_356 VSS_428 BT28 AU28 VSS_211 VSS_283 CB2 CF19 VSS_66 VSS_138 CJ3
AD33 VSS_357 VSS_429 AL28 BY22 VSS_212 VSS_284 N25 V33 VSS_67 VSS_139 AM5
BL32 VSS_358 VSS_430 BT33 J12 VSS_213 VSS_285 B31 BE29 VSS_68 VSS_140 CM4
CM33 VSS_359 VSS_431 D5 AU29 VSS_214 VSS_286 CB20 CF2 VSS_69 VSS_141 AC5
AD35 VSS_360 VSS_432 AL29 J15 VSS_215 VSS_287 N27 V36 VSS_70 VSS_142 AG5
VSS_361 VSS_433 VSS_216 VSS_288 CB25 BE3 VSS_71 VSS_143 CR6
VSS_289 VSS_72 VSS_144
CML-U_BGA1528 CML-U_BGA1528
18 of 20 19 of 20 CML-U_BGA1528
20 of 20
A A
MCP(14/14)VSS
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
SOC or PCH / FCH
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
SOC or PCH / FCH
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
SOC or PCH / FCH
5 4 3 2 1
5 4 3 2 1
<7> DDR_A_DQS#[0..7]
<7>
<7>
DDR_A_D[0..63]
DDR_A_DQS[0..7]
For DDR4
+1.2V_MEM
<7> DDR_A_MA[0..16]
0.01U_0201_16V7
1
CD143
@ @ DDR_A_CLK#0 1 2DDR_A_CLK0_R 2
+VREFCA UD1 +VREFCA UD2 @ @ DDR_A_CLK0 RD18 1 2 33_0201_5%
+VREFCA UD3 +VREFCA UD4 RD19 33_0201_5%
+VREFCA M1 G2 DDR_A_D0 +VREFCA M1 G2 DDR_A_D16
VREFCA DQL0 F7 DDR_A_D3 VREFCA DQL0 F7 DDR_A_D20 +VREFCA M1 G2 DDR_A_D32 +VREFCA M1 G2 DDR_A_D61 +0.6V_DDR_VTT
DQL1 H3 DDR_A_D5 DQL1 H3 DDR_A_D23 VREFCA DQL0 F7 DDR_A_D34 VREFCA DQL0 F7 DDR_A_D58
DDR_A_MA0 P3 DQL2 H7 DDR_A_D6 DDR_A_MA0 P3 DQL2 H7 DDR_A_D17 DQL1 H3 DDR_A_D35 DQL1 H3 DDR_A_D56 DDR_A_MA0 RD1 1 2 36_0201_1%
DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D1 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D21 DDR_A_MA0 P3 DQL2 H7 DDR_A_D39 DDR_A_MA0 P3 DQL2 H7 DDR_A_D62 DDR_A_MA1 RD2 1 2 36_0201_1%
D DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D2 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D18 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D37 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D60 DDR_A_MA2 RD3 1 2 36_0201_1% D
DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D4 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D19 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D33 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D59 DDR_A_MA3 RD4 1 2 36_0201_1%
DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D7 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D22 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D36 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D57 DDR_A_MA4 RD5 1 2 36_0201_1%
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D38 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D63 DDR_A_MA5 RD6 1 2 36_0201_1%
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA6 RD7 1 2 36_0201_1%
DDR_A_MA7 R8 A6 A3 DDR_A_D24 DDR_A_MA7 R8 A6 A3 DDR_A_D12 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA7 RD8 1 2 36_0201_1%
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D29 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D15 DDR_A_MA7 R8 A6 A3 DDR_A_D48 DDR_A_MA7 R8 A6 A3 DDR_A_D41 DDR_A_MA8 RD9 1 2 36_0201_1%
DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D28 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D13 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D50 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D46 DDR_A_MA9 RD10 1 2 36_0201_1%
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D30 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D14 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D53 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D40 DDR_A_MA10 RD11 1 2 36_0201_1%
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D25 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D9 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D54 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D47 DDR_A_MA11 RD12 1 2 36_0201_1%
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D27 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D11 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D52 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D45 DDR_A_MA12 RD13 1 2 36_0201_1%
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D31 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D8 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D51 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D43 DDR_A_MA13 RD14 1 2 36_0201_1%
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D26 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D10 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D49 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D44 DDR_A_MA14 RD15 1 2 36_0201_1%
A14/WE DQU7 A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D55 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D42 DDR_A_MA15 RD16 1 2 36_0201_1%
DDR_A_BA0 N2 DDR_A_BA0 N2 A14/WE DQU7 A14/WE DQU7 DDR_A_MA16 RD17 1 2 36_0201_1%
<7,23> DDR_A_BA0 DDR_A_BA1 N8 BA0 <7,23> DDR_A_BA0 DDR_A_BA1 N8 BA0 DDR_A_BA0 N2 DDR_A_BA0 N2 DDR_A_CS#0
B3 +1.2V_MEM<7,23> B3 +1.2V_MEM
<7,23> DDR_A_BA0 <7,23> DDR_A_BA0 RD20 1 2 36_0201_1%
<7,23> DDR_A_BA1 BA1 VDD1 DDR_A_BA1 BA1 VDD1 DDR_A_BA1 N8 BA0 DDR_A_BA1 N8 BA0 DDR_A_ODT0
B9 B9 B3 B3 RD21 1 2 36_0201_1%
VDD2 VDD2 <7,23> DDR_A_BA1 BA1 VDD1 +1.2V_MEM
<7,23> DDR_A_BA1 BA1 VDD1 +1.2V_MEM DDR_A_CKE0
E2 D1 E2 D1 B9 B9 RD22 1 2 36_0201_1%
+1.2V_MEM DMU/DBIU VDD3 +1.2V_MEM DMU/DBIU VDD3 VDD2 VDD2 DDR_A_BA0
E7 G7 E7 G7 +1.2V_MEM
E2 D1 +1.2V_MEM
E2 D1 RD23 1 2 36_0201_1%
DML/DBIL VDD4 J1 DML/DBIL VDD4 J1 E7 DMU/DBIU VDD3 G7 E7 DMU/DBIU VDD3 G7 DDR_A_BA1 RD24 1 2 36_0201_1%
VDD5 J9 VDD5 J9 DML/DBIL VDD4 J1 DML/DBIL VDD4 J1 DDR_A_PARITY RD25 1 2 36_0201_1%
VDD6 L1 VDD6 L1 VDD5 J9 VDD5 J9 DDR_A_BG0 RD26 1 2 36_0201_1%
DDR_A_CLK0 K7 VDD7 L9 DDR_A_CLK0 K7 VDD7 L9 VDD6 L1 VDD6 L1 DDR_A_BG1_R RD27 1 2 36_0201_1%
<7,23> DDR_A_CLK0 DDR_A_CLK#0K8 CK_t VDD8 <7,23> DDR_A_CLK0 DDR_A_CLK#0K8 CK_t VDD8 DDR_A_CLK0 K7 VDD7 DDR_A_CLK0 K7 VDD7 DDR_A_ACT#
R1 R1 L9 L9 RD30 1 2 36_0201_1%
<7,23> DDR_A_CLK#0 DDR_A_CKE0 K2 CK_c VDD9 <7,23> DDR_A_CLK#0 DDR_A_CKE0 K2 CK_c VDD9 <7,23> DDR_A_CLK0 DDR_A_CLK#0K8 CK_t VDD8 <7,23> DDR_A_CLK0 DDR_A_CLK#0K8 CK_t VDD8
T9 T9 R1 R1
<7,23> DDR_A_CKE0 CKE VDD10 <7,23> DDR_A_CKE0 CKE VDD10 <7,23> DDR_A_CLK#0 DDR_A_CKE0 K2 CK_c VDD9 <7,23> DDR_A_CLK#0 DDR_A_CKE0 K2 CK_c VDD9
T9 T9
<7,23> DDR_A_CKE0 CKE VDD10 <7,23> DDR_A_CKE0 CKE VDD10 +1.2V_MEM
A1 A1
VDDQ1 A9 VDDQ1 A9 A1 A1
VDDQ2 C1 VDDQ2 C1 VDDQ1 A9 VDDQ1 A9 DDR_A_ALERT# RD33 1 2 49.9_0201_1%
VDDQ3 D9 VDDQ3 D9 VDDQ2 C1 VDDQ2 C1
VDDQ4 F2 VDDQ4 F2 VDDQ3 D9 VDDQ3 D9
VDDQ5 F8 VDDQ5 F8 VDDQ4 F2 VDDQ4 F2 DDP@
DDR_A_ODT0 K3 VDDQ6 G1 DDR_A_ODT0 K3 VDDQ6 G1 VDDQ5 F8 VDDQ5 F8 DDR_A_BG1_R RD79 1 2 0_0201_5%
<7,23> DDR_A_ODT0 DDR_A_CS#0 L7 ODT VDDQ7 <7,23> DDR_A_ODT0 DDR_A_CS#0 L7 ODT VDDQ7 DDR_A_ODT0 K3 VDDQ6 DDR_A_ODT0 K3 VDDQ6 DDR_A_BG1 <7>
G9 G9 G1 G1
<7,23> DDR_A_CS#0 DDR_A_MA16 L8 CS VDDQ8 <7,23> DDR_A_CS#0 DDR_A_MA16 L8 CS VDDQ8 <7,23> DDR_A_ODT0 DDR_A_CS#0 L7 ODT VDDQ7 <7,23> DDR_A_ODT0 DDR_A_CS#0 L7 ODT VDDQ7
J2 J2 G9 G9 SDP@
DDR_A_MA15 M8 RAS VDDQ9 DDR_A_MA15 M8 RAS VDDQ9 <7,23> DDR_A_CS#0 DDR_A_MA16 L8 CS VDDQ8 <7,23> DDR_A_CS#0 DDR_A_MA16 L8 CS VDDQ8
J8 J8 J2 J2 RD80 1 2 0_0201_5%
CAS VDDQ10 CAS VDDQ10 DDR_A_MA15 M8 RAS VDDQ9 J8 DDR_A_MA15 M8 RAS VDDQ9 J8 SDP@
B2 DDP@ B2 DDP@ CAS VDDQ10 CAS VDDQ10 RD96 1 2 0_0201_5%
VSS1 E1 RD88 VSS1 E1 RD89 B2 DDP@ B2 DDP@
DDR4 mapping SDP DDP SDP@
VSS2 E9 UD1_E9 2 1 VSS2 E9 UD2_E9 2 1 VSS1 E1 RD90 VSS1 E1 RD91 RD97 1 2 0_0201_5%
VSS3 G8 VSS3 G8 VSS2 E9 UD3_E9 2 1 VSS2 E9 UD4_E9 2 1
E9 VSS UZQ SDP@
C DDR_A_DQS#3 VSS4 DDR_A_DQS#1 VSS4 VSS3 VSS3 C
A7 K1 240_0201_1% A7 K1 240_0201_1% G8 G8 VSS RD98 1 2 0_0201_5%
DDR_A_DQS3 B7 DQSU_c VSS5 K9 DDR_A_DQS1 B7 DQSU_c VSS5 K9 DDR_A_DQS#6 A7 VSS4 K1 240_0201_1% DDR_A_DQS#5 A7 VSS4 K1 240_0201_1%
M9 BG1
DDR_A_DQS#0 F3 DQSU_t VSS6 M9 DDR_A_BG1_R DDR_A_DQS#2 F3 DQSU_t VSS6 M9 DDR_A_BG1_R DDR_A_DQS6 B7 DQSU_c VSS5 K9 DDR_A_DQS5 B7 DQSU_c VSS5 K9
DDR_A_DQS0 G3 DQSL_c VSS7 N1 DDR_A_DQS2 G3 DQSL_c VSS7 N1 DDR_A_DQS#4 F3 DQSU_t VSS6 M9 DDR_A_BG1_R DDR_A_DQS#7 F3 DQSU_t VSS6 M9 DDR_A_BG1_R T7 NC VSS
DQSL_t VSS8 T1 DQSL_t VSS8 T1 DDR_A_DQS4 G3 DQSL_c VSS7 N1 DDR_A_DQS7 G3 DQSL_c VSS7 N1
DDR_DRAMRST#_R P1 VSS9 DDR_DRAMRST#_R P1 VSS9 DQSL_t VSS8 T1 DQSL_t VSS8 T1
RD28 RESET RD29 RESET DDR_DRAMRST#_R P1 VSS9 DDR_DRAMRST#_R P1 VSS9 Total
1 2UD1_ZQ F9 1 2UD2_ZQ F9 RD84 RESET RD85 RESET VDDQ & VDD :32x1uF, 10x10uF
ZQ ZQ 1 2UD3_ZQ F9 1 2UD4_ZQ F9 VPP : 16x1uF, 5x10uF
ZQ ZQ
240_0201_1%
DDR_A_ACT# L3
240_0201_1%
DDR_A_ACT# L3 VTT : 16x1uF, 4x10uF
A2 A2 240_0201_1% 240_0201_1%
<7,23> DDR_A_ACT# DDR_A_BG0 M2 ACT VSSQ1 <7,23> DDR_A_ACT# DDR_A_BG0 M2 ACT VSSQ1 DDR_A_ACT# L3 DDR_A_ACT# L3 +2.5V_MEM
A8 A8 A2 A2
<7,23> DDR_A_BG0 BG0 VSSQ2 <7,23> DDR_A_BG0 BG0 VSSQ2 <7,23> DDR_A_ACT# DDR_A_BG0 M2 ACT VSSQ1 <7,23> DDR_A_ACT# DDR_A_BG0 M2 ACT VSSQ1
N9 C9 N9 C9 A8 A8
DDR_A_ALERT# P9 TEN VSSQ3 D2 DDR_A_ALERT# P9 TEN VSSQ3 D2
<7,23> DDR_A_BG0
N9 BG0 VSSQ2 C9
<7,23> DDR_A_BG0
N9 BG0 VSSQ2 C9
For VPP
<7,23> DDR_A_ALERT# DDR_A_PARITY T3 ALERT VSSQ4 <7,23> DDR_A_ALERT# DDR_A_PARITY T3 ALERT VSSQ4 DDR_A_ALERT# P9 TEN VSSQ3 DDR_A_ALERT# P9 TEN VSSQ3
D8 D8 D2 D2
<7,23> DDR_A_PARITY PAR VSSQ5 <7,23> DDR_A_PARITY PAR VSSQ5 <7,23> DDR_A_ALERT# DDR_A_PARITY T3 ALERT VSSQ4 <7,23> DDR_A_ALERT# DDR_A_PARITY T3 ALERT VSSQ4
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
E3 E3 D8 D8
VSSQ6 VSSQ6 <7,23> DDR_A_PARITY PAR VSSQ5 <7,23> DDR_A_PARITY PAR VSSQ5
T7 E8 T7 E8 E3 E3 1 1 1 1 1 1 1 1
B1 NC VSSQ7 F1 B1 NC VSSQ7 F1 T7 VSSQ6 E8 T7 VSSQ6 E8
+2.5V_MEM VPP1 VSSQ8 +2.5V_MEM VPP1 VSSQ8 NC VSSQ7 NC VSSQ7
CD52
CD74
CD75
CD76
CD118
CD117
CD120
CD119
R9 H1 R9 H1 +2.5V_MEM B1 F1 +2.5V_MEM B1 F1
VPP2 VSSQ9 H9 VPP2 VSSQ9 H9 R9 VPP1 VSSQ8 H1 R9 VPP1 VSSQ8 H1
96-BALL VSSQ10 96-BALL VSSQ10 VPP2 VSSQ9 H9 VPP2 VSSQ9 H9 2 2 2 2 2 2 2 2
SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ10 96-BALL VSSQ10
K4A8G165W B-BCPB_FBGA96-X K4A8G165W B-BCPB_FBGA96-X SDRAM DDR4 SDRAM DDR4
K4A8G165W B-BCPB_FBGA96-X K4A8G165W B-BCPB_FBGA96-X
+1.2V_MEM +2.5V_MEM
For VDDQ & VDD
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
1 1 1 1 1 1
1
CD30
CD68
CD69
CD70
CD71
CD72
CD41
CD42
CD43
2
2
2 2 2 2 2 2
B B
+1.2V_MEM +1.2V_MEM +VREFCA
0.047U_0201_6.3V6K
0.047U_0201_6.3V6K
0.047U_0201_6.3V6K
0.047U_0201_6.3V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
1 1 1 1 1 1 1 1
CD135
CD136
CD137
CD138
CD1
CD2
CD3
CD4
CD31
CD32
CD33
2
2
2 2 2 2 2 2 2 2
+1.2V_MEM +1.2V_MEM
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
10U_0603_10V6M
+1.2V_MEM +1.2V_MEM
1 1 1 1 1 1
1
+DDR_VREF_CA +1.2V_MEM +VREFCA
CD22
CD23
CD24
CD25
CD26
CD27
CD5
CD6
1 2
2
1
@ CD115 0.1U_0201_10V6K 2 2 2 2 2 2
1
RD86
RD34 470_0201_1%
1.8K_0201_1%
5
UD9
2
RD36
2
Vcc
DDR_DRAMRST# +0.6V_DDR_VTT
NC
1 2 @ RD87 1 2 0_0201_5% 2 4 +0.6V_DDR_VTT

<24> DDR_DRAMRST#_R DDR_DRAMRST# <7> <7> DDR_VTT_CTRL A Y 0.6V_DDR_VTT_ON <86>
1 1 For VTT
G
CD39 2.7_0201_1% @ 1 2
+3.3V_RUN
CD116 RD83 100K_0201_5%
1
0.022U_0201_16V6K 0.1U_0201_10V6K 74AUP1G07SE-7_SOT353-5

3
2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
10U_0603_10V6M
RD38
1
1.8K_0201_1% 1 1 1 1 1 1 1 1
1
RD40
CD60
CD61
CD62
CD66
CD124
CD122
CD125
CD123
CD55
CD121
A 24.9_0201_1% A
2
2
2 2 2 2 2 2 2 2
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4 DIMMA
5 4 3 2 1
5 4 3 2 1
For DDR4
<7> DDR_B_DQS#[0..7]
<7> DDR_B_D[0..63]
+1.2V_MEM
<7> DDR_B_DQS[0..7]
0.01U_0201_16V7
<7> DDR_B_MA[0..16] 1
CD144
DDR_B_CLK#0 1 2DDR_B_CLK0_R 2
DDR_B_CLK0 RD67 1 2 33_0201_5%
RD68 33_0201_5%
+0.6V_DDR_VTT
DDR_B_MA0 RD42 1 2 36_0201_1%
DDR_B_MA1 RD43 1 2 36_0201_1%
DDR_B_MA2 RD44 1 2 36_0201_1%
DDR_B_MA3 RD45 1 2 36_0201_1%
D DDR_B_MA4 RD46 1 2 36_0201_1% D
@ @ @ @ DDR_B_MA5 RD47 1 2 36_0201_1%
+VREFDQ_B UD5 +VREFDQ_B UD6 +VREFDQ_B UD7 +VREFDQ_B UD8 DDR_B_MA6 RD48 1 2 36_0201_1%
DDR_B_MA7 RD49 1 2 36_0201_1%
+VREFDQ_B M1 G2 DDR_B_D12 +VREFDQ_B M1 G2 DDR_B_D23 +VREFDQ_B M1 G2 DDR_B_D24 +VREFDQ_B M1 G2 DDR_B_D57 DDR_B_MA8 RD50 1 2 36_0201_1%
VREFCA DQL0 F7 DDR_B_D14 VREFCA DQL0 F7 DDR_B_D21 VREFCA DQL0 F7 DDR_B_D26 VREFCA DQL0 F7 DDR_B_D63 DDR_B_MA9 RD51 1 2 36_0201_1%
DQL1 H3 DDR_B_D9 DQL1 H3 DDR_B_D16 DQL1 H3 DDR_B_D25 DQL1 H3 DDR_B_D56 DDR_B_MA10 RD52 1 2 36_0201_1%
DDR_B_MA0 P3 DQL2 H7 DDR_B_D11 DDR_B_MA0 P3 DQL2 H7 DDR_B_D19 DDR_B_MA0 P3 DQL2 H7 DDR_B_D31 DDR_B_MA0 P3 DQL2 H7 DDR_B_D59 DDR_B_MA11 RD53 1 2 36_0201_1%
DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D13 DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D17 DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D28 DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D61 DDR_B_MA12 RD54 1 2 36_0201_1%
DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D15 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D20 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D27 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D62 DDR_B_MA13 RD55 1 2 36_0201_1%
DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D8 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D22 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D29 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D60 DDR_B_MA14 RD56 1 2 36_0201_1%
DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D10 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D18 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D30 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D58 DDR_B_MA15 RD57 1 2 36_0201_1%
DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA16 RD58 1 2 36_0201_1%
DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5 DDR_B_CS#0 RD62 1 2 36_0201_1%
DDR_B_MA7 R8 A6 A3 DDR_B_D2 DDR_B_MA7 R8 A6 A3 DDR_B_D32 DDR_B_MA7 R8 A6 A3 DDR_B_D45 DDR_B_MA7 R8 A6 A3 DDR_B_D49 DDR_B_ODT0 RD64 1 2 36_0201_1%
DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D6 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D34 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D47 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D50 DDR_B_CKE0 RD65 1 2 36_0201_1%
DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D0 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D37 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D40 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D48 DDR_B_BA0 RD59 1 2 36_0201_1%
DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D3 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D38 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D42 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D55 DDR_B_BA1 RD60 1 2 36_0201_1%
DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D4 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D36 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D41 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D53 DDR_B_PARITY RD61 1 2 36_0201_1%
DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D1 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D39 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D46 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D54 DDR_B_BG0 RD63 1 2 36_0201_1%
DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D5 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D35 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D44 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D52 DDR_B_BG1_R RD66 1 2 36_0201_1%
DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D7 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D33 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D43 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D51 DDR_B_ACT# RD81 1 2 36_0201_1%
A14/WE DQU7 A14/WE DQU7 A14/WE DQU7 A14/WE DQU7
DDR_B_BA0 N2 DDR_B_BA0 N2 DDR_B_BA0 N2 DDR_B_BA0 N2 +1.2V_MEM
<7,24> DDR_B_BA0 DDR_B_BA1 N8 BA0 <7,24> DDR_B_BA0 DDR_B_BA1 N8 BA0 <7,24> DDR_B_BA0 DDR_B_BA1 N8 BA0 <7,24> DDR_B_BA0 DDR_B_BA1 N8 BA0
B3 B3 B3 B3
<7,24> DDR_B_BA1 BA1 VDD1 +1.2V_MEM
B9 B9 B9 B9
E2 VDD2 D1 E2 VDD2 D1 E2 VDD2 D1 E2 VDD2 D1 DDR_B_ALERT# RD82 1 2 49.9_0201_1%
+1.2V_MEM DMU/DBIU VDD3 +1.2V_MEM DMU/DBIU VDD3 +1.2V_MEM DMU/DBIU VDD3 +1.2V_MEM DMU/DBIU VDD3
E7 G7 E7 G7 E7 G7 E7 G7
DML/DBIL VDD4 J1 DML/DBIL VDD4 J1 DML/DBIL VDD4 J1 DML/DBIL VDD4 J1
VDD5 J9 VDD5 J9 VDD5 J9 VDD5 J9 DDP@
VDD6 L1 VDD6 L1 VDD6 L1 VDD6 L1 DDR_B_BG1_R RD69 1 2 0_0201_5%
DDR_B_CLK0 K7 VDD7 DDR_B_CLK0 K7 VDD7 DDR_B_CLK0 K7 VDD7 DDR_B_CLK0 K7 VDD7 DDR_B_BG1 <7>
L9 L9 L9 L9
<7,24> DDR_B_CLK0 DDR_B_CLK#0K8 CK_t VDD8 <7,24> DDR_B_CLK0 DDR_B_CLK#0K8 CK_t VDD8 <7,24> DDR_B_CLK0 DDR_B_CLK#0K8 CK_t VDD8 <7,24> DDR_B_CLK0 DDR_B_CLK#0K8 CK_t VDD8
R1 R1 R1 R1 SDP@
<7,24> DDR_B_CLK#0 DDR_B_CKE0 K2 CK_c VDD9 <7,24> DDR_B_CLK#0 DDR_B_CKE0 K2 CK_c VDD9 <7,24> DDR_B_CLK#0 DDR_B_CKE0 K2 CK_c VDD9 <7,24> DDR_B_CLK#0 DDR_B_CKE0 K2 CK_c VDD9
T9 T9 T9 T9 RD74 1 2 0_0201_5%
<7,24> DDR_B_CKE0 CKE VDD10 <7,24> DDR_B_CKE0 CKE VDD10 <7,24> DDR_B_CKE0 CKE VDD10 <7,24> DDR_B_CKE0 CKE VDD10 SDP@
RD99 1 2 0_0201_5%
A1 A1 A1 A1 SDP@
VDDQ1 A9 VDDQ1 A9 VDDQ1 A9 VDDQ1 A9
DDR4 mapping SDP DDP RD100 1 2 0_0201_5%
VDDQ2 C1 VDDQ2 C1 VDDQ2 C1 VDDQ2 C1 SDP@
VDDQ3 D9 VDDQ3 D9 VDDQ3 D9 VDDQ3 D9
E9 VSS UZQ RD101 1 2 0_0201_5%
VDDQ4 F2 VDDQ4 F2 VDDQ4 F2 VDDQ4 F2
VDDQ5 F8 VDDQ5 F8 VDDQ5 F8 VDDQ5 F8
M9 VSS BG1
C DDR_B_ODT0 K3 VDDQ6 DDR_B_ODT0 K3 VDDQ6 DDR_B_ODT0 K3 VDDQ6 DDR_B_ODT0 K3 VDDQ6 C
G1 G1 G1 G1 NC VSS
<7,24> DDR_B_ODT0 DDR_B_CS#0 L7 ODT VDDQ7 G9 <7,24> DDR_B_ODT0 DDR_B_CS#0 L7 ODT VDDQ7 G9 <7,24> DDR_B_ODT0 DDR_B_CS#0 L7 ODT VDDQ7 G9 <7,24> DDR_B_ODT0 DDR_B_CS#0 L7 ODT VDDQ7 G9
T7
<7,24> DDR_B_CS#0 DDR_B_MA16 L8 CS VDDQ8 <7,24> DDR_B_CS#0 DDR_B_MA16 L8 CS VDDQ8 <7,24> DDR_B_CS#0 DDR_B_MA16 L8 CS VDDQ8 <7,24> DDR_B_CS#0 DDR_B_MA16 L8 CS VDDQ8
J2 J2 J2 J2
DDR_B_MA15 M8 RAS VDDQ9 J8 DDR_B_MA15 M8 RAS VDDQ9 J8 DDR_B_MA15 M8 RAS VDDQ9 J8 DDR_B_MA15 M8 RAS VDDQ9 J8
CAS VDDQ10 CAS VDDQ10 CAS VDDQ10 CAS VDDQ10 Total
B2 DDP@ B2 DDP@ B2 DDP@ B2 DDP@ VDDQ & VDD :32x1uF, 10x10uF
VSS1 E1 RD92 VSS1 E1 RD93 VSS1 E1 RD94 VSS1 E1 RD95 VPP : 16x1uF, 5x10uF
VSS2 E9 UD5_E9 2 1 VSS2 E9 UD6_E9 2 1 VSS2 E9 UD7_E9 2 1 VSS2 E9 UD8_E9 2 1
VSS3 VSS3 VSS3 VSS3 VTT : 16x1uF, 4x10uF
G8 G8 G8 G8
DDR_B_DQS#0 A7 VSS4 K1 240_0201_1% DDR_B_DQS#4 A7 VSS4 K1 240_0201_1% DDR_B_DQS#5 A7 VSS4 K1 240_0201_1% DDR_B_DQS#6 A7 VSS4 K1 240_0201_1%
DDR_B_DQS0 B7 DQSU_c VSS5 K9 DDR_B_DQS4 B7 DQSU_c VSS5 K9 DDR_B_DQS5 B7 DQSU_c VSS5 K9 DDR_B_DQS6 B7 DQSU_c VSS5 K9
DDR_B_DQS#1 F3 DQSU_t VSS6 M9 DDR_B_BG1_R DDR_B_DQS#2 F3 DQSU_t VSS6 M9 DDR_B_BG1_R DDR_B_DQS#3 F3 DQSU_t VSS6 M9 DDR_B_BG1_R DDR_B_DQS#7 F3 DQSU_t VSS6 M9 DDR_B_BG1_R +2.5V_MEM +2.5V_MEM
DDR_B_DQS1 G3 DQSL_c VSS7 N1 DDR_B_DQS2 G3 DQSL_c VSS7 N1 DDR_B_DQS3 G3 DQSL_c VSS7 N1 DDR_B_DQS7 G3 DQSL_c VSS7 N1
DQSL_t VSS8 T1 DQSL_t VSS8 T1 DQSL_t VSS8 T1 DQSL_t VSS8 T1
For VPP
DDR_DRAMRST#_R P1 VSS9 DDR_DRAMRST#_R P1 VSS9 DDR_DRAMRST#_R P1 VSS9 DDR_DRAMRST#_R P1 VSS9
23> DDR_DRAMRST#_R RESET RESET RESET RESET
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
RD70 RD71 RD72 RD73
1 2UD5_ZQ F9 1 2UD6_ZQ F9 1 2UD7_ZQ F9 1 2UD8_ZQ F9 1 1 1 1 1 1 1 1
ZQ ZQ ZQ ZQ
1
CD103
CD104
CD106
CD107
CD127
CD126
CD129
CD128
CD110
CD111
CD145
240_0201_1% 240_0201_1% 240_0201_1% 240_0201_1%
DDR_B_ACT# L3 A2 DDR_B_ACT# L3 A2 DDR_B_ACT# L3 A2 DDR_B_ACT# L3 A2
<7,24> DDR_B_ACT# <7,24> DDR_B_ACT# <7,24> DDR_B_ACT# <7,24> DDR_B_ACT#
2
DDR_B_BG0 M2 ACT VSSQ1 A8 DDR_B_BG0 M2 ACT VSSQ1 A8 DDR_B_BG0 M2 ACT VSSQ1 A8 DDR_B_BG0 M2 ACT VSSQ1 A8 2 2 2 2 2 2 2 2
<7,24> DDR_B_BG0 BG0 VSSQ2 <7,24> DDR_B_BG0 BG0 VSSQ2 <7,24> DDR_B_BG0 BG0 VSSQ2 <7,24> DDR_B_BG0 BG0 VSSQ2
N9 C9 N9 C9 N9 C9 N9 C9
DDR_B_ALERT# P9 TEN VSSQ3 D2 DDR_B_ALERT# P9 TEN VSSQ3 D2 DDR_B_ALERT# P9 TEN VSSQ3 D2 DDR_B_ALERT# P9 TEN VSSQ3 D2
<7,24> DDR_B_ALERT# DDR_B_PARITY T3 ALERT VSSQ4 <7,24> DDR_B_ALERT# DDR_B_PARITY T3 ALERT VSSQ4 <7,24> DDR_B_ALERT# DDR_B_PARITY T3 ALERT VSSQ4 <7,24> DDR_B_ALERT# DDR_B_PARITY T3 ALERT VSSQ4
D8 D8 D8 D8
<7,24> DDR_B_PARITY PAR VSSQ5 <7,24> DDR_B_PARITY PAR VSSQ5 <7,24> DDR_B_PARITY PAR VSSQ5 <7,24> DDR_B_PARITY PAR VSSQ5
E3 E3 E3 E3
T7 VSSQ6 E8 T7 VSSQ6 E8 T7 VSSQ6 E8 T7 VSSQ6 E8
B1 NC VSSQ7 F1 B1 NC VSSQ7 F1 B1 NC VSSQ7 F1 B1 NC VSSQ7 F1
+2.5V_MEM VPP1 VSSQ8 +2.5V_MEM VPP1 VSSQ8 +2.5V_MEM VPP1 VSSQ8 +2.5V_MEM VPP1 VSSQ8 +1.2V_MEM +1.2V_MEM
R9 H1 R9 H1 R9 H1 R9 H1
VPP2 VSSQ9 H9 VPP2 VSSQ9 H9 VPP2 VSSQ9 H9 VPP2 VSSQ9 H9
96-BALL VSSQ10 96-BALL VSSQ10 96-BALL VSSQ10 96-BALL VSSQ10 For VDD & VDDQ
SDRAM DDR4 SDRAM DDR4 SDRAM DDR4 SDRAM DDR4
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
10U_0603_10V6M
K4A8G165W B-BCPB_FBGA96-X K4A8G165W B-BCPB_FBGA96-X K4A8G165W B-BCPB_FBGA96-X K4A8G165W B-BCPB_FBGA96-X
1 1 1 1 1 1
1
CD98
CD105
CD108
CD109
CD113
CD114
CD100
CD101
2
2
2 2 2 2 2 2
B B
+1.2V_MEM +1.2V_MEM +VREFDQ_B
0.047U_0201_6.3V6K
0.047U_0201_6.3V6K
0.047U_0201_6.3V6K
0.047U_0201_6.3V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
1 1 1 1 1 1 1 1
CD139
CD141
CD140
CD142
CD79
CD80
CD81
CD82
CD83
2
2 2 2 2 2 2 2 2
+1.2V_MEM +1.2V_MEM
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
10U_0603_10V6M
1 1 1 1 1 1
1
CD85
CD86
CD89
CD91
CD92
CD95
CD90
CD93
2
2
+DDR_VREF_B_DQ +1.2V_MEM +VREFDQ_B 2 2 2 2 2 2
1
RD75
1.8K_0201_1%
+0.6V_DDR_VTT +0.6V_DDR_VTT
2
RD76
1 2
For VTT
1
CD67 2.7_0201_1%
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
10U_0603_10V6M
1
0.022U_0201_16V6K 1 1 1 1 1 1 1 1
1
2 RD77
1
CD56
CD57
CD58
CD64
CD132
CD131
CD134
CD133
CD63
CD130
A 1.8K_0201_1% A
RD78
2
24.9_0201_1% 2 2 2 2 2 2 2 2
2
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4 DIMMB
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DDR_2
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DDR_3
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
VRAM
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
VRAM
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DGPU_DC/DC Interface
5 4 3 2 1
5 4 3 2 1
CONN@
41
JEDP1
GND_1 1
1
+BL_PWR_SRC TOUCH SCREEN & IR CAMERA connector For 3mm IR CAM ALS & P-Sensor
42 2
43 GND_2 2 3 +LCDVDD CONN@JIR1 1 2 TOUCH_SCREEN_PD#_R +1.8V_RUN
GND_3 3 +TS_PWR <14> TOUCH_SCREEN_PD#
44 4 1
GND_4 4 EDP_HPD 1 IR_CAM_DET# <9> ISH_I2C1_SDA
45 5 1 2 2 DV20 2 1
46 GND_5 5 6 @ RV7 100K_0201_5% 2 3 RB751S-40_SOD523-2 RV740 2.2K_0201_5%
GND_6 6 EPRIVACY_EN <58> 3 ISH_I2C1_SCL
47 7 4 2 1
GND_7 7 2.7MM_CAM_DET# <12> 4 ISH_I2C1_SDA 3MM_CAM_DET# <9>
48 8 Reserve for EA 5 RV741 2.2K_0201_5%
GND_8 8 5 ISH_I2C1_SCL ISH_I2C1_SDA <9> +TS_PWR ISH_ALS_INT#
49 9 6 2 1
GND_9 9 DMIC0 <74> 6 ISH_ALS_INT# ISH_I2C1_SCL <9>
50 10 7 RV742 2.2K_0201_5%
GND_10 10 7 P_SENSOR_PW R_SAVE# ISH_ALS_INT# <9> P_SENSOR_PW R_SAVE# 2
51 11 8 1
GND_11 11 DMIC_CLK0 <74> 8 P_SENSOR_PWR_SAVE# <9>
1
52 12 9 ISH_P_SENSOR_INT# RV743 10K_0201_5%
GND_12 12 +3.3V_RUN_F 9 ISH_P_SENSOR_INT# <12> ISH_P_SENSOR_INT#
53 13 10 RV1000 2 1
GND_13 13 USB20_N6_R +3.3V_CAM 10
100P_0201_50V8J
82P_0201_50V8J
54 14 11 100K_0201_5% RV755 10K_0201_5%
GND_14 14 USB20_P6_R 11 SECURE_BIO_R @ RZ1498 1 TOUCH_SCREEN_PD#_R P_SENSOR_DET#
RF@
RF@ CA6
55 15 1 1 12 2 0_0201_5% 2 1
GND_15 15 12 P_SENSOR_DET# SECURE_BIO <10>
56 16 13 @ RZ1497 100K_0201_5%
CAM_MIC_CBL_DET# <12>
2
57 GND_16 16 17 Pin17: LOOP_BACK 13 14 +TS_PW R_QV101
GND_17 17 BIA_PWM 14 +1.8V_ALS_PWR
58 18 @EMI@ LV1 BLM15PX221SN1D_2P 1 2 15
PJX138K_SOT563-6
PJX138K_SOT563-6
GND_18 18 15 +3.3V_P_SENSOR_PWR
6
D DISP_ON 2 2 +3.3V_RUN D
CA5
59 19 1 2 16
60 GND_19 19 20 @EMI@ RV999 0_0402_5% 16 17 FZ1
61 GND_20 20 21 17 18 +13.5VB_IR 2 1 +1.8V_ALS_PWR +1.8V_RUN Touch pull up at the panel side RF Request
QV101B
QV101A
62 GND_21 21 22
LV1 Co-lay with RV999 18 +13.5VB
FZ4 5 2 DISP_ON
63 GND_22 22 23 19 1A_65V_T0603FF1000TM 1 2 I2C0_SDA_TS 2 1
GND_23 23 EDP_HPD <6> G1 +13.5VB
64 24 20 @ RV98 2.2K_0201_5%
65 GND_24 24 25
RF Request G2 0.5A_65V_T0603FF0500TM I2C0_SCL_TS 2 1
66 GND_25 25 26 ACES_50208-01801-P03 +3.3V_P_SENSOR_PWR +3.3V_RUN @ RV99 2.2K_0201_5%
GND_26 26 LCD_TST <58>
1
67 27 FZ5 TS_INT# 2 1
GND_27 27 +LCDVDD
68 28 1 2 @ RV311 100K_0201_5%
69 GND_28 28 29 TOUCH_SCREEN_DET# CONN@ JTS1 SECURE_BIO 2 1
GND_29 29 EDP_AUXN_R TOUCH_SCREEN_DET# <9>
100P_0201_50V8J
RF@ CZ3
70 30 8 @ RZ311 1 2 0_0201_5% 0.5A_65V_T0603FF0500TM @ RZ1496 100K_0201_5% 1
GND_30 30 EDP_AUXP_R GND2 TS_RST# <9>
71 31 7
72 GND_31 31 32 EDP_TXP0_R EDP_AUXN_C CV1 2 1 0.1U_0201_25V6K GND1 6 TS_RST#_R @ RZ310 1 2 0_0201_5%
73 GND_32 32 33 EDP_TXN0_R EDP_AUXP_C CV2 2 1 0.1U_0201_25V6K
EDP_AUXN <6> 6 5
PCH_PLTRST#_AND <11,42,52,68,70,74> RF Request
GND_33 33 EDP_TXP1_R EDP_TXP0_C EDP_AUXP <6> 5 I2C0_SDA_TS TS_INT# <9> 2
74 34 CV3 2 1 0.1U_0201_25V6K 4 I2C0_SDA_TS <9>
GND_34 34 EDP_TXN1_R EDP_TXN0_C EDP_TXP0 <6> 4 I2C0_SCL_TS I2C0_SDA_TS
35 CV4 2 1 0.1U_0201_25V6K 3 1 2
35 EDP_TXP2_R EDP_TXP1_C EDP_TXN0 <6> 3 TOUCH_SCREEN_PD#_R I2C0_SCL_TS <9>
36 CV5 2 1 0.1U_0201_25V6K 2 @RF@ CV54 33P_0201_50V8J
36 EDP_TXN2_R EDP_TXN1_C EDP_TXP1 <6> 2 TS_5V_DET#
37 CV6 2 1 0.1U_0201_25V6K 1
37 EDP_TXP3_R EDP_TXP2_C EDP_TXN1 <6> 1 I2C0_SCL_TS
38 CV761 2 1 0.1U_0201_25V6K 1 2
38 EDP_TXN3_R EDP_TXN2_C EDP_TXP2 <6>
39 CV762 2 1 0.1U_0201_25V6K ACES_50208-0060N-P01 @RF@ CV55 33P_0201_50V8J
39 EDP_TXP3_C EDP_TXN2 <6>
40 CV759 2 1 0.1U_0201_25V6K
40 LCD_CBL_DET# <9> EDP_TXN3_C EDP_TXP3 <6>
CV760 2 1 0.1U_0201_25V6K
EDP_TXN3 <6>
I-PEX_20879-040E-01
RF Request LV13, LV14, LV15, LV16, LV17 need to Co-lay with resistor
Relink I-PEX_20879-040E-01 done 0827 @RF@ RV757 1 2 0_0201_5% @RF@ RV763 1 2 0_0201_5% LCDVDD POWER
DLM0NSN900HY2D_4P DLM0NSN900HY2D_4P
EDP_AUXN_R 4 3 EDP_AUXN_C EDP_TXP2_R 4 3 EDP_TXP2_C
4 3 4 3
RF Request place as close as JEDP1 EDP_AUXP_R 1 2 EDP_AUXP_C EDP_TXN2_R 1 2 EDP_TXN2_C +3.3V_ALW
+LCDVDD +3.3V_CAM +BL_PW R_SRC 1 2 1 2 @ CV17
LV13 @RF@ @RF@ RV761 1 2 0_0201_5% LV16 @RF@ +LCDVDD +EDP_VDD 1 2
@RF@ RV756 1 2 0_0201_5% @RF@ RV762 1 2 0_0201_5% JUMP@ UV24
DLM0NSN900HY2D_4P PJP12
EDP_TXP1_R 4 3 EDP_TXP1_C 1 2 1 6 0.01U_0201_25V7K DV3
4 3 OUT IN
PAD-OPEN1x1m 2 5 UV24_SET 1 2 3
C EDP_TXN1_R EDP_TXN1_C GND SET LCD_VCC_TEST_EN <58> C
1 2 RV102 20K_0201_5%
1 2 LCD_PW R_EN_R 2 1LCD_PW R_EN 1
12P_0201_50V8J
RF@ CV20
82P_0201_50V8J
RF@ CV21
100P_0201_50V8J
RF@ CV751
100P_0201_50V8J
RF@ CV752
27P_0201_25V8
RF@CV757
12P_0201_50V8J
RF@ CV22
82P_0201_50V8J
RF@ CV23
120P_0402_50V8
RF@ CV750
12P_0201_50V8J
RF@ CV24
82P_0201_50V8J
RF@ CV25
120P_0402_50V8
RF@ CV753
27P_0201_25V8
RF@ CV758
1 1 1 1 1 1 1 1 1 1 1 1 3 4
@RF@ RV759 1 2 0_0201_5% LV15 @RF@ @RF@ RV764 1 2 0_0201_5% 1 2 FLAG EN(/EN) @ RV180 2
ENVDD_PCH <6>
1
100K_0201_5%
1U_0402_6.3V6K
@RF@ RV760 1 2 0_0201_5% @ RV101 0.01_1206_1% 1 0_0402_5%
DLM0NSN900HY2D_4P DLM0NSN900HY2D_4P
@ CV80
1 G527ATP1U_TSOT23-6
2 2 2 2 2 2 2 2 2 2 2 2 EDP_TXP0_R EDP_TXP0_C EDP_TXP3_R EDP_TXP3_C
RV3
4 3 4 3 BAT54CTB_SOT-523-3
4 3 4 3 @ CV16
10U_0402_10V6M
2
2
EDP_TXN0_R 1 2 EDP_TXN0_C EDP_TXN3_R 1 2 EDP_TXN3_C 2
1 2 1 2
LV14 @RF@ LV17 @RF@
@RF@ RV758 1 2 0_0201_5% @RF@ RV765 1 2 0_0201_5%
+BL_PWR_SRC
+BL_PWR_SRC +LCDVDD +3.3V_CAM +TS_PW R +3.3V_RUN_F
Backlight POWER
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1A_65V_T0603FF1000TM
0.1U_0201_25V6K
1 1 1 1 1
2
@ CV11
@ @ @ @
CV12
CZ202
CZ2
CA7
FZ2
2 2 2 2 2 QV1 change from SB000008S80 to SB000010C00
For Layout limit height WebCAM +3.3V_CAM +3.3V_RUN_F +3.3V_RUN
1
QV1
+13.5VB DMP3050LVT-7_TSOT26-6 QZ1
Close to JEDP1.1~3 Close to JEDP1.27~28 Close to JEDP1.13 Close to JEDP1.5 Close to JEDP1.12
D
6 +BL_PW R_SRC_P FZ3
S
4 5 1 3 1 2
S
2
1 0.5A_65V_T0603FF0500TM
0.1U_0201_25V6K
G
2
1
1U_0402_25V6K
1 1
CV15
RF Request RV4
3.3V_CAM_EN#_R
CV13
270K_0201_1% 1 2
+TS_PW R <11> 3.3V_CAM_EN#
@ RZ388 0_0201_5%
2 2
1
2
@
B CZ220 B
BL_PWR_SRC_ON 0.1U_0201_25V6K EMI@
2 LZ1
QV2 1 2 USB20_N6_R
<10> USB20_N6 1 2
0.01U_0201_25V7K
PJE138K_SOT-523-3
12P_0201_50V8J
RF@ CV18
82P_0201_50V8J
RF@ CV19
120P_0402_50V8
RF@ CV754
DV1 1 1 1 1 USB20_P6_R
1 2 1 3 4 3
D
S
BIA_PWM_PCH <10> USB20_P6 4 3
CV14
3 RV5 47K_0201_5%
BIA_PWM_PCH <6>
DLM0NSN900HY2D_4P
BIA_PWM 1 2 2 2 2
2 G
2 BIA_PWM_EC
BIA_PWM_EC <58>
1
RV1
4.7K_0201_5% BAT54CW _SOT323-3 +TS_PWR +5V_RUN
<58> EN_INVPW R
For Touchscreen
2
1
100_0402_5%
place as close as JEDP1 2
@ RV775
RV733 0.1U_0201_25V6K
0.5A_65V_T0603FF0500TM
DV2 DMIC_CLK0 I2C0_SCL_TS CV764
47K_0201_5%
1
3 @
PANEL_BKEN_PCH <6> I2C0_SDA_TS 1
DMIC0
2
DISP_ON 1 TS_5V_DET#
2
2
+TS_PW R_DIS
CEST523NC5VB_SOT-523-3
FV1
2
ESD@ DV13
ESD@ DZ10
G
PANEL_BKEN_EC <58> QV8
2
1
0418 Follow Dorest intel recommend change NTK3139PT1G_SOT723-3 1 3

BAT54CW _SOT323-3 +5V_RUN
1
RV2 pull up to 100K from 10K.
S
D +TS_PW R_QV8 1 3+3.3V_5V_RUN_QV8
S
2.2K_0201_5%
0.1U_0201_25V6K
1
2
+3.3V_RUN +3.3V_RUN +3.3V_RUN G 2
47K_0201_5%
1 QV22
2
@ CV635
@ QV100
G
2
RV6
PJE138K_SOT-523-3 S QV23
1
3
RV734 RV325 RV8 +3.3V_RUN 2
1
3 1
D
10K_0201_5% 10K_0201_5% 100K_0201_5% +3.3V_RUN
TS_PW R_EN# 2 1 TS_PW R_EN#_R
100K_0201_5%
1
1
RV400 0_0201_5%
2
2.7MM_CAM_DET# 3MM_CAM_DET# TOUCH_SCREEN_DET#
RV326
D
G
2
USB20_P6_R ISH_I2C1_SCL TS_5V_DET
1
G 2
2
USB20_N6_R ISH_I2C1_SDA D QV24
If touch panel, GPIO Low-> Touch Mic. EQ ; 1
2
A @ PJE138K_SOT-523-3 S A
others the GPIO is High -> Non-Touch Mic. EQ
2
3.3V_TS_EN_R 47K_0201_5%
1 2 2 G CV763
<58> 3.3V_TS_EN
3
ESD@ DV14
ESD@ DZ21
@ RV323 0_0201_5% QV7 RV732 0.1U_0201_25V6K

1 2 S PJE138K_SOT-523-3 2
<9> PCH_3.3V_TS_EN
1
@ RV324 0_0201_5%
3
+5V_RUN
1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT eDP CONN & Touch screen
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
DP
5 4 3 2 1
5 4 3 2 1
+1.2V_RUN +1.2V_LSPCON_VDD +1.2V_RUN +1.2V_LSPCON_VDDTX

LV602 LV604
1 2 1 2 Note:
10U_0402_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0201_10V6K
0.01U_0201_10V6K
10U_0402_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0201_10V6K
0.01U_0201_10V6K
*The decoupling caps shall be close to
BLM18KG331SN1D_2P BLM18KG331SN1D_2P the power pins as possible
1 1 1 1 1 1 1 1 1 1 1 1 *1.2V power ripple requirement: <30mV
CV625
CV643
CV644
CV48
CV610
CV627
CV42
CV611
CV612
CV613
CV621 CV624
0.47U_0201_6.3V6K 0.47U_0201_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2
+3.3V_RUN +3.3V_LSPCON_VDD
LV601
1 2
10U_0402_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
BLM18KG331SN1D_2P
+1.2V_RUN +1.2V_LSPCON_VDDA +1.2V_RUN +1.2V_LSPCON_VDDRX 1 1 1 1
LV603 LV605
CV629
CV608
CV609
EMI@ RV56 1 2 5.6_0402_5%
D HDMI_L_TX_P2 D
1 2 1 2 CV620
@EMI@ LV3
10U_0402_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0201_10V6K
0.01U_0201_10V6K
0.47U_0201_6.3V6K
2
BLM18KG331SN1D_2P BLM18KG331SN1D_2P 2 2 2 2 HDMI_TX_P2 1 4 @EMI@
1 4 RV26
1 1 1 1 1 1 1 1 1 1
CV626
CV45
CV46
CV628
CV614
CV617
CV616
CV615
130_0402_5%
CV622 CV623 HDMI_TX_N2 2 3
0.47U_0201_6.3V6K 0.47U_0201_6.3V6K 2 3
1
2 2 2 2 2 2 2 2 2 2 HCM1012GH900BP_4P HDMI_L_TX_N2
EMI@ RV57 1 2 5.6_0402_5%
UV19 EMI@ RV58 1 2 5.6_0402_5%

+1.2V_LSPCON_VDD +3.3V_LSPCON_VDD HDMI_L_TX_P1
@EMI@ LV6
2
+1.2V_LSPCON_VDDA 27 26 HDMI_TX_P1 1 4 @EMI@
42 VDD12 VDD33 49 1 4 RV29
+1.2V_LSPCON_VDDTX 29 VDD12 VDD33 130_0402_5%
VDDA12 HDMI_TX_N1 2 3
+1.2V_LSPCON_VDDRX 28 2 3
1
41 VDDTX12 HCM1012GH900BP_4P HDMI_L_TX_N1
2 VDDTX12 EMI@ RV59 1 2 5.6_0402_5%
14 VDDRX12
VDDRX12
EMI@ RV60 1 2 5.6_0402_5%
HDMI_L_TX_P0
@ RV748 1 2 0_0201_5% TR_DP1_R_P0 3 34 HDMI_TX_P0 @EMI@ LV9
<42> TR_DP1_C_P0 DRX0P HDMID0P
2
@ RV749 1 2 0_0201_5% TR_DP1_R_N0 4 33 HDMI_TX_N0 HDMI_TX_P0 1 4 @EMI@
<42> TR_DP1_C_N0 DRX0N HDMID0N 1 4 RV32
@ RV750 1 2 0_0201_5% TR_DP1_R_P1 6 37 HDMI_TX_P1 130_0402_5%
<42> TR_DP1_C_P1 TR_DP1_R_N1 DRX1P HDMID1P HDMI_TX_N1 HDMI_TX_N0
@ RV751 1 2 0_0201_5% 7 36 2 3
<42> TR_DP1_C_N1 DRX1N HDMID1N 2 3
1
@ RV632 1 2 0_0201_5% TR_DP1_R_P2 9 40 HDMI_TX_P2 HCM1012GH900BP_4P HDMI_L_TX_N0
<42> TR_DP1_C_P2 TR_DP1_R_N2 DRX2P HDMID2P HDMI_TX_N2
@ RV633 1 2 0_0201_5% 10 39 EMI@ RV61 1 2 5.6_0402_5%
<42> TR_DP1_C_N2 DRX2N HDMID2N
@ RV634 1 2 0_0201_5% TR_DP1_R_P3 12 31 HDMI_CLKP
C <42> TR_DP1_C_P3 TR_DP1_R_N3 DRX3P HDMICKP HDMI_CLKN C
@ RV635 1 2 0_0201_5% 13 30 EMI@ RV62 1 2 5.6_0402_5%
<42> TR_DP1_C_N3 DRX3N HDMICKN HDMI_L_CLKP
+VHDMI_VCC
56 1 HDMI_CEC_R @ RV19 1 2 0_0201_5% HDMI_CEC HDMI_CLKP @EMI@ LV12
<42> TR_DP1_C_AUXP AUXP HDMI_CEC
2
55 1 1 4 @EMI@
<42> TR_DP1_C_AUXN AUXN HDMI_CTRL_CLK 1 4
+3.3V_RUN RV610 1 2 100K_0201_5% AUXDCP 54 52 RV22 1 2 2.2K_0201_5% @ CV778 RV35
RV611 1 2 100K_0201_5% AUXDCN 53 AUXDCP DDC_SCL 51 HDMI_CTRL_DATA RV23 1 2 2.2K_0201_5% 3.3P_0402_50V8B 130_0402_5%
AUXDCN DDC_SDA 2 3
HDMI_CLKN 2 2 3
1
LSPCON_CS# 21 32 HDMI_HPD HCM1012GH900BP_4P HDMI_L_CLKN
LSPCON_DO 22 IROMS HDMI_HPD 46 TR_DP1_HPD_R RV21 1 2 1K_0201_5%
LSPCON_CLK 23 IROMQ DP_HPD TR_DP1_HPD <42> EMI@ RV63 1 2 5.6_0402_5%
LSPCON_DI IROMC 1
24
I2C_ADDR +3.3V_RUN LSPCON_WP# 25 IROMD 20 LSPCON_REXT RV38 1 2 4.99K_0201_1% CV777
IROMW REXT 11 HDMI_PD#_R
‘ 0’ : 10 h – 2 Fh (defaul t) PDB RV38 should be placed 0.22U_0201_6.3V6K
@ RV612 1 2 4.7K_0201_5% LSPCON_I2C_ADDR 45 2
‘ 1’ : 90h – 9Fh, D0h – DF h I2C_ADDR LSPCON_EQ0 close to REXT pin.
5
17 EQ0 8 LSPCON_EQ1
+3.3V_RUN 18 GPIO1 EQ1
19 GPIO2 35 TMDS_CFG0 EMI Request
GPIO4
@ RV613 1 2 4.7K_0201_5% LSPCON_GPIO4 43 GPIO3 TMDS_CFG0 50 TMDS_CFG1
DP Rx lane count capability selection GPIO4 TMDS_CFG1
TMDS_CFG1 @ RV614 1 2 0_0201_5% LSPCON_GPIO5 44 +3.3V_RUN +3.3V_RUN
‘ 0’ : 4lan e (default ) GPIO5
‘ 1’ : 2lane T474 @ PAD~D
1 38
TESTMODEB
0.1U_0201_25V6K
EMI@ CV779
+3.3V_RUN
1
RV605 1 2 4.7K_0201_5% LSPCON_CSCL 48 1
RV606 1 2 4.7K_0201_5% LSPCON_CSDA 47 CSCL RV607 +5V_RUN
1 CSDA
T475 @ PAD~D 20K_0201_5%
HDMI_CLK_27M_IN 15 57
HDMI_CLK_27M_OUT 16 XTLI GND 2
2
XTLO HDMI_PD#_R
0.1U_0201_10V6K
1 2 Power down; ACTIVE LOW
<6> HDMI_PD#
@ RV766 1K_0201_5% 1 1
PS185HDMQFN56GTR2-A1_QFN56_7X7-X
@
CV605
1
CV39
1U_0201_6.3V6K +VHDMI_VCC
2 2
IN
AP2330W-7_SC59-3
B B
UV2
0.1U_0201_10V6K
10U_0603_10V6M
+3.3V_RUN +3.3V_RUN 1 1
GND
OUT
@
YV2
1
CV40
CV41
TMDS swing configuration pin.
1
3-state input. 3.3V I/O 2 2
3
HDMI_CLK_27M_IN 1 3 HDMI_CLK_27M_OUT_R 1 2 HDMI_CLK_27M_OUT @ RV753 RV746 TMDS_CFG0=
1
1
NC1 NC2
3
1 RV609 1K_0201_5% 4.7K_0201_5% 4.7K_0201_5% L: Default TMDS output swing
M:Decrease TMDS swing by10%
HDMI connector
2
CV607 CV606
H: Increase TMDS swing by 10%
2
18P_0201_50V8J 2 4 18P_0201_50V8J TMDS_CFG0

2 2 Link HMRBL-A41L0F done 0123
27MHZ_10PF_XRCGB27M000F2P18R0-X TMDS_CFG1 JHDMI1 CONN@
TMDS output configuration for its output pre-emphasis level. HDMI_HPD 19
Add ground shielding HP_DET
1
3-state input. 3.3V I/O 18

+5V
between REXT and XTLO/XTLI @ RV745 @ RV747 TMDS_CFG1= HDMI_CTRL_DATA
17
DDC/CEC_GND
4.7K_0201_5% 4.7K_0201_5% L: No pre-emphasis 16
+3.3V_RUN +3.3V_RUN HDMI_CTRL_CLK 15 SDA
M:1.5dB pre-emphasis SCL
14
H: 3dB pre-emphasis
2
HDMI_CEC 13 Reserved
CEC
1
HDMI_L_CLKN 12 20
CK- GND4
1
[EQ1,EQ0]= 11 21
@ RV620 @ RV622 HDMI_L_CLKP 10 CK_shield GND3 22
LL: Compensate channel loss up to 5dB@HBR3 CK+ GND2
4.7K_0201_5% HDMI_L_TX_N0 9 23
4.7K_0201_5% LM: Compensate channel loss up to 8dB@HBR3 D0- GND1
LH: Compensate channel loss up to 14dB@HBR3 8
2
HDMI_L_TX_P0 7 D0_shield
LSPCON_EQ0 ML: Compensate channel loss up to 16dB@HBR3
2
HDMI_L_TX_N1 6 D0+
MM: Compensate channel loss up to17dB@HBR3 5 D1-
MH: Compensate channel loss up to18dB@HBR3 HDMI_L_TX_P1 4 D1_shield
LSPCON_EQ1 HL: Compensate channel loss up to19dB@HBR3 HDMI_L_TX_N2 3 D1+
+3.3V_RUN +3.3V_RUN +3.3V_RUN HM: Compensate channel loss up to 20dB@HBR3 2 D2-
D2_shield
1
HH: Compensate channel loss up to 21dB @HBR3 HDMI_L_TX_P2

0.1U_0201_10V6K
1
@ RV621 @ RV752 Please note that this is only an optional method of setting D2+
A A
1
1 4.7K_0201_5% 4.7K_0201_5% input DP EQ via these two pins. By default, PS186 uses ACON_HMRBL-A41L0F-X
CV630
RV616 RV617 adaptive EQ by firmware.

4.7K_0201_5% 4.7K_0201_5%
2
UV32 2
2
LSPCON_CS# 1 8
LSPCON_DO
LSPCON_WP#
2
3
CS#
DO
VCC
HOLD#
7
6
LSPCON_HOLD#
LSPCON_CLK
4 WP# CLK 5 LSPCON_DI
GND DI Compal Electronics, Inc.
1
RV619 W25X20CLSNIG_SO8 RV618 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
4.7K_0201_5% 4.7K_0201_5% TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
HDMI CONN
2
1.0
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
CRT
5 4 3 2 1
5 4 3 2 1
TR ROM choice need follow Intel approved list

+3.3V_TBT_LC +3.3V_TBT_LC
+3.3V_TBT_LC Reference Titan Ridge DP 1.41 Datasheet
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
3.3K_0201_5%
2.2K_0201_5%
2.2K_0201_5%
3.3K_0201_5%
1
1
CT1
RT5
RT6
RT7
RT8
0.1U_0201_10V6K
2
RT1
RT2
RT3
RT4
1
2
UT2 TBT_JTAG_TDI
8 1 TBT_ROM_CS# TBT_JTAG_TMS
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO TBT_JTAG_TCK
D TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_W P# TBT_JTAG_TDO D
TBT_ROM_DI 5 CLK WP#(IO2) 4
DI(IO0) GND
W 25Q80DVSSIG_SO8-X TBT_ROM_DI
TBT_ROM_DO TBT_ROM_DI <42,44>
TBT_ROM_CS# TBT_ROM_DO <42,44>
TBT_ROM_CLK TBT_ROM_CS# <42,44>
TBT_ROM_CLK <42,44>
UT1A
CT2 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P5 Y23 V23 PCIE_PRX_C_DTX_P5 CT6 1 2 0.22U_0201_6.3V6K

<10> PCIE_PTX_DRX_P5 PCIE_PTX_C_DRX_N5 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_C_DTX_N5 PCIE_PRX_DTX_P5 <10>
CT3 1 2 0.22U_0201_6.3V6K Y22 V22 CT7 1 2 0.22U_0201_6.3V6K
<10> PCIE_PTX_DRX_N5 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N5 <10>
CT4 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P6 T23 P23 PCIE_PRX_C_DTX_P6 CT8 1 2 0.22U_0201_6.3V6K
CT5 1 2 0.22U_0201_6.3V6K T22 P22 CT9 1 2 0.22U_0201_6.3V6K
PCIe GEN3
CT123 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P7 M23 K23 PCIE_PRX_C_DTX_P7 CT127 1 2 0.22U_0201_6.3V6K
CT124 1 2 0.22U_0201_6.3V6K M22 K22 CT128 1 2 0.22U_0201_6.3V6K
CT125 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P8 H23 F23 PCIE_PRX_C_DTX_P8 CT129 1 2 0.22U_0201_6.3V6K +3.3V_ALW _PCH
CT126 1 2 0.22U_0201_6.3V6K H22 F22 CT130 1 2 0.22U_0201_6.3V6K
T4 TBT_PERST#
V19 PERST#
<11> CLK_PCIE_P5 REFCLK_100_IN_P TBT_PCIE_RBIAS TBT_CIO_PLUG_EVENT#
T19 N16 1 2 RT391 1 2 10K_0201_5%
<11> CLK_PCIE_N5
Y6 REFCLK_100_IN_N PCIE_RBIAS Y2 PCIE_W AKE#_TR RT34 3.01K_0201_1% For backdrive issue
<11> CLKREQ_PCIE#5 PCIE_CLKREQ# PEWAKE#
CT176 1 2 0.22U_0201_6.3V6K CPU_DP1_N0_C AB7 AB21 TR_DP1_P0 0.22U_0201_6.3V6K 2 1 CT136
<6> CPU_DP1_N0 CPU_DP1_P0_C DPSNK1_ML0_N DPSRC_ML0_P TR_DP1_N0 TR_DP1_C_P0 <40> +3.3V_TBT_SX
CT177 1 2 0.22U_0201_6.3V6K AC7 AC21 0.22U_0201_6.3V6K 2 1 CT137
<6> CPU_DP1_P0 DPSNK1_ML0_P DPSRC_ML0_N TR_DP1_C_N0 <40>
CT172 1 2 0.22U_0201_6.3V6K CPU_DP1_P1_C AB9 AC19 TR_DP1_P1 0.22U_0201_6.3V6K 2 1 CT138 PCIE_W AKE#_TR RTD3@ RT455 1 2 10K_0201_5%
<6> CPU_DP1_P1 CPU_DP1_N1_C DPSNK1_ML1_P DPSRC_ML1_P TR_DP1_N1 TR_DP1_C_P1 <40> DG_GPIO8
CT171 1 2 0.22U_0201_6.3V6K AC9 AB19 0.22U_0201_6.3V6K 2 1 CT139 RT338 1 2 10K_0201_5%
<6> CPU_DP1_N1 DPSNK1_ML1_N DPSRC_ML1_N TR_DP1_C_N1 <40>
SOURCE PORT 0
TDOCK_BATLOW # RT20 1 2 10K_0201_5%
CPU
SINK PORT 1
CT174 1 2 0.22U_0201_6.3V6K CPU_DP1_P2_C AC11 AB17 TR_DP1_P2 0.22U_0201_6.3V6K 2 1 CT140 TBT_I2C_SDA RT18 1 2 2.2K_0201_5%
<6> CPU_DP1_P2 CPU_DP1_N2_C DPSNK1_ML2_P DPSRC_ML2_P TR_DP1_N2 TR_DP1_C_P2 <40> TBT_I2C_SCL
DDI1 <6> CPU_DP1_N2
CT168 1 2 0.22U_0201_6.3V6K AB11
DPSNK1_ML2_N DPSRC_ML2_N
AC17 0.22U_0201_6.3V6K 2 1 CT141
TR_DP1_C_N2 <40> TBT_I2C_INT
RT19 1
RT16 1
2
2
2.2K_0201_5%
10K_0201_5%
CT173 1 2 0.22U_0201_6.3V6K CPU_DP1_P3_C AB13 AC15 TR_DP1_P3 0.22U_0201_6.3V6K 2 1 CT142
<6> CPU_DP1_P3 CPU_DP1_N3_C DPSNK1_ML3_P DPSRC_ML3_P TR_DP1_N3 TR_DP1_C_P3 <40>
CT170 1 2 0.22U_0201_6.3V6K AC13 AB15 0.22U_0201_6.3V6K 2 1 CT143
<6> CPU_DP1_N3 DPSNK1_ML3_N DPSRC_ML3_N TR_DP1_C_N3 <40> +3.3V_TBT_S0
CT169 1 2 0.22U_0201_6.3V6K CPU_DP1_AUXP_C N1 N4 TR_DP1_AUXP 0.22U_0201_6.3V6K 2 1 CT144
C <6> CPU_DP1_AUXP CPU_DP1_AUXN_C DPSNK1_AUX_P DPSRC_AUX_P TR_DP1_AUXN TR_DP1_C_AUXP <40> SIO_SLP_S3# C
<6> CPU_DP1_AUXN CT175 1 2 0.22U_0201_6.3V6K N2 N5 0.22U_0201_6.3V6K 2 1 CT145 @ RT22 1 2 10K_0201_5%
DPSNK1_AUX_N DPSRC_AUX_N TR_DP1_C_AUXN <40> RTD3_CIO_PW R_EN RTD3@RT372 1 2 10K_0201_5%
AA2 TBT_FORCE_PW R @ RT21 1 2 10K_0201_5%
<6> CPU_DP1_HPD DPSNK1_HPD R5 TR_DP1_HPD
DPSRC_HPD TR_DP1_HPD <40> TR_DP1_HPD RT184 1 2 100K_0201_5%
CT186 1 2 0.22U_0201_6.3V6K CPU_DP2_P0_C A5 TBTA_HPD_SCL RT23 1 2 100K_0201_5%
<6> CPU_DP2_P0 CPU_DP2_N0_C DPSNK2_ML0_P TBTB_HPD_SDA
CT187 1 2 0.22U_0201_6.3V6K B5 RT28 1 2 100K_0201_5%
<6> CPU_DP2_N0 DPSNK2_ML0_N RTD3_USB_PW R_EN RT26 1 2 100K_0201_5%
CT183 1 2 0.22U_0201_6.3V6K CPU_DP2_P1_C B3 W1 DG_GPIO0 Reference 607109_CML_U_PDG_Rev1p2 P.261 TBT_FORCE_PW R RT27 1 2 100K_0201_5%
<6> CPU_DP2_P1 DPSNK2_ML1_P
LC GPIO
CT180 1 2 0.22U_0201_6.3V6K CPU_DP2_N1_C A3 GPIO_0 W2 DG_GPIO1 and Intel comment no need to use SML0_ALERT#. RTD3_CIO_PW R_EN NRTD3@ RT25 1 2 100K_0201_5%
<6> CPU_DP2_N1 DPSNK2_ML1_N GPIO_1
SINK PORT 2
Y1 SML0_ALERT#_TR @ RT200 1 2 0_0201_5% SML0_ALERT#_TR RT33 1 2 100K_0201_5%
CPU CT185 1 2 0.22U_0201_6.3V6K CPU_DP2_P2_C C2 TMU_CLKOUT AA1 TBT_CIO_PLUG_EVENT# SML0_ALERT# <8> DG_GPIO8 @ RT124 1 2 100K_0201_5%
<6> CPU_DP2_P2 CPU_DP2_N2_C DPSNK2_ML2_P CIO_PLUG_EVENT# DG_GPIO8 TBT_CIO_PLUG_EVENT# <12> DG_PA_USB2_MXCTL
DDI2 <6> CPU_DP2_N2
CT179 1 2 0.22U_0201_6.3V6K C1
DPSNK2_ML2_N TMU_CLKIN
W6
DG_PB_USB2_MXCTL
RT128 1
RT129 1
2
2
100K_0201_5%
100K_0201_5%
CT182 1 2 0.22U_0201_6.3V6K CPU_DP2_P3_C E2 DG_GPIO0 RT31 1 2 100K_0201_5%
<6> CPU_DP2_P3 CPU_DP2_N3_C DPSNK2_ML3_P TBT_I2C_SDA DG_GPIO1
CT181 1 2 0.22U_0201_6.3V6K E1 V1 RT32 1 2 100K_0201_5%
<6> CPU_DP2_N3 DPSNK2_ML3_N I2C_SDA TBT_I2C_SCL TBT_I2C_SDA <44>
V2
CPU_DP2_AUXP_C POC GPIO I2C_SCL RTD3_USB_PW R_EN TBT_I2C_SCL <44>
<6> CPU_DP2_AUXP CT178 1 2 0.22U_0201_6.3V6K P1 V5
CT184 1 2 0.22U_0201_6.3V6K CPU_DP2_AUXN_C P2 DPSNK2_AUX_P USB_FORCE_PWR V4 TBT_FORCE_PW R
<6> CPU_DP2_AUXN DPSNK2_AUX_N FORCE_PWR TDOCK_BATLOW # TBT_FORCE_PW R <6>
U2
Y4 BATLOW# U1
<6> CPU_DP2_HPD DPSNK2_HPD SLP_S3# RTD3_CIO_PW R_EN SIO_SLP_S3# <11,17,59,79>
T5
RTD3_PWR_EN RTD3_CIO_PW R_EN <9> For vPRO docking support vHPD
AC3 E5 TBT_RESET#_AND
AB3 U0_SSRXp1 RESET# 1 2
U0_SSRXn1 SML0_SMBCLK <8>
Misc
D22 XTAL_25_IN 1 2 XTAL_25_IN_R TBTA_HPD_SCL @ RT96 0_0201_5%

USB
AB5 XTAL_25_IN D23 XTAL_25_OUT @ RT394 1 2 0_0201_5% XTAL_25_OUT_R 1 2 TBTA_HPD

U0_SSTXn1 XTAL_25_OUT TBTA_HPD <44>
AC5 @ RT40 0_0201_5% @ RT97 0_0201_5%
U0_SSTXp1 YT1
TBT_JTAG_TDI W20 3 1
TBT_JTAG_TMS Y20 TDI Y18 TBT_ROM_DI OUT IN
TBT_JTAG_TCK W19 TMS EE_DI W16 TBT_ROM_DO TBT_ROM_DI <42,44> 4 2 1 2
TBT_JTAG_TDO TCK EE_DO TBT_ROM_CS# TBT_ROM_DO <42,44> GND2 GND1 TBTB_HPD_SDA SML0_SMBDATA <8>
27P_0201_25V8
27P_0201_25V8
Y19 MISC W18 1 1 @ RT98 0_0201_5%
TDO EE_CS# TBT_ROM_CLK TBT_ROM_CS# <42,44> TBTB_HPD
Y16 25MHZ_20PF_FL2500123Z-X 1 2
TBTA_RBIAS EE_CLK TBT_ROM_W P# TBT_ROM_CLK <42,44> TBTB_HPD <44>
CT20
CT21
1 2 J6 W4 @ RT99 0_0201_5%
RT39 4.75K_0201_0.5% TBTA_RSENSE J5 RBIAS EE_WP#
RSENSE 2 2 Reference TR_DP_TI88_HOST_REF_DESIGN_R1V2
B21 A13
<45> TBT_A_TRX_DTX_P1 ASSRXp1 BSSRXp1 TBT_B_TRX_DTX_P1 <46>
A21 B13
<45> TBT_A_TRX_DTX_N1 ASSRXn1 BSSRXn1 TBT_B_TRX_DTX_N1 <46>
B A19 A11 1 2 B
<45> TBT_A_TTX_DRX_P1 B19 ASSTXp1 BSSTXp1 B11 TBT_B_TTX_DRX_P1 <46> NRTD3@ RT502 0_0201_5%
<45> TBT_A_TTX_DRX_N1 ASSTXn1 BSSTXn1 TBT_B_TTX_DRX_N1 <46>
<45> TBT_A_TRX_DTX_P2
A15 B7
TBT_B_TRX_DTX_P2 <46>
TBT RTD3 Support +3.3V_ALW
B15 ASSRXp2 BSSRXp2 A7 0.1U_0201_10V6K
<45> TBT_A_TRX_DTX_N2 ASSRXn2 BSSRXn2 TBT_B_TRX_DTX_N2 <46>
TBT PORTS
1 2
A17 A9
Type C ASSTXp2 Type C
Port A
PORT B
<45> TBT_A_TTX_DRX_P2 B17 BSSTXp2 B9 TBT_B_TTX_DRX_P2 <46> RTD3@

<45> TBT_A_TTX_DRX_N2 ASSTXn2 BSSTXn2 TBT_B_TTX_DRX_N2 <46>
Port A H4 L4
Port B CT360
<45> TBTA_SBU1 ASBU1 BSBU1 TBTB_SBU1 <46>
5
J4 L5
<45> TBTA_SBU2 ASBU2 BSBU2 TBTB_SBU2 <46>
1
P
<11,38,52,68,70,74> PCH_PLTRST#_AND B TBT_PERST#
E20 E19 4
<44> TBTA_USB20_P PA_USB2_D_P PB_USB2_D_P TBTB_USB20_P <44> O
D20 D19 2
<44> TBTA_USB20_N PA_USB2_D_N PB_USB2_D_N TBTB_USB20_N <44> <9> PCH_TBT_PERST# A
100K_0201_5%
2
TBTA_HPD_SCL T2 T1 TBTB_HPD_SDA
RTD3@ RT503
RTD3@ UT34
3
TBT_I2C_INT M4 PA_HPD PB_HPD M5 TBT_I2C_INT MC74VHC1G08EDFT2G_SC70-5
<44> TBT_I2C_INT DG_PA_USB2_MXCTL PA_I2C_INT PB_I2C_INT DG_PB_USB2_MXCTL
R2 R1
1 2 TBTA_USB2_RBIAS H19 PA_USB2_MXCTL PB_USB2_MXCTL F19 TBTB_USB2_RBIAS 2 1
RT41 200_0201_1% PA_USB2_RBIAS PB_USB2_RBIAS RT42 200_0201_1%
1
V8 W5 TEST_PW RGD 1 2
THERMDA TEST_PWR_GOOD R4 RT37 200_0201_1% 1 2
D4 TEST_EN B23 @ RT504 0_0201_5%
L8 TEST_EDM USB2_ATEST AB23 1 2
FUSE_VQPS_64 PCIE_ATEST J9
DEBUG ATEST_P
@ RT505 0_0201_5%
A23 J11 RTD3@
A1 PA_MONDC ATEST_N H5 @RTD3@ RT456 +3.3V_ALW CT237
AC23 PB_MONDC VGA_RES 0_0201_5% 0.1U_0201_10V6K
AC1 PC_MONDC TBT_RTD3_W AKE# 1 2 1 2
D5 USB_MONDC <9> TBT_RTD3_W AKE# UT32 RTD3@
MONDC_SVR PCH_PCIE_W AKE# 1 2 1 5
<11,58,59> PCH_PCIE_W AKE# @RTD3@ RT445 0_0201_5% NO V+
JHL7540-SLMHS_BGA337-X PCIE_W AKE# 3 4 PCIE_W AKE#_TR
TR-DP <52,59,68,74> PCIE_W AKE# NC COM
6 2
<58> RTD3_SELECT IN GND
2
@RTD3@
TBT Reset AND gate
2
RTD3@ TS5A3159ADCKR_SC70-6 RT440
RT447 1M_0201_5%
1 2 10K_0201_5%
@ RT105 0_0201_5%
IN NC NO
1
1
A +3.3V_TBT_SX A
L COM X
5
H X COM
VCC
1 TBT_RESET_N_EC_R 1 2
TBT_RESET#_AND IN1 TBT_RESET_N_EC <58>
4 @ RT102 0_0201_5%
OUT 2 TBT_RESET_N_PD_R 1 2
GND
IN2 TBT_RESET_N_PD <44>

@ RT103 0_0201_5%
1
RT104 @UT35
3
100K_0201_5% MC74VHC1G08EDFT2G_SC70-5
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, TBT-AR-SP(1/2) DP,PCIE
1.0
5 4 3 2 1
5 4 3 2 1
TBT Power circuit

D D
+3.3V_RUN +3.3V_TBT
JUMP@
PJP5
2 1
2 1
JUMP_43X79
UT1B
+0.9V_TBT_SVR +3.3V_TBT_S0
H9 G1
+3.3V_TBT_S0 +3.3V_TBT H11 VCC0P9_SVR_PAB_ANA1 VCC3P3_SVR1 G2
LT2 H12 VCC0P9_SVR_PAB_ANA2 VCC3P3_SVR2 H2
1 2 H13 VCC0P9_SVR_PAB_ANA3 VCC3P3_SVR3 E6
H15 VCC0P9_SVR_PAB_ANA4 VCC3P3A
1UH_LQM18PN1R0MFHD_20% H16 VCC0P9_SVR_PAB_ANA5 L6 +3.3V_TBT_SX
1U_0201_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
+3.3V_TBT_ANA VCC0P9_SVR_PAB_ANA6 VCC3P3_S0

1 1 1
CT67
CT68
CT69
T12 F18
T13 VCC0P9_SVR_PC_ANA1 VCC3P3_SX1 R6 +0.9V_TBT_SVR
1U_0201_6.3V6M
T15 VCC0P9_SVR_PC_ANA2 VCC3P3_SX2
2 2 2 VCC0P9_SVR_PC_ANA3 J13
1 VCC0P9_SVR1
CT32
T9 L11
Pin E16
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
T11 VCC0P9_SVR_USB_ANA1 VCC0P9_SVR2 L13
VCC0P9_SVR_USB_ANA2 VCC0P9_SVR3 1 1 1 1 1 1 1
M8
Pin H11
Pin H13
Pin H16
Pin J13
Pin L11
Pin M11
Pin E8
2 +0.9V_TBT_PCIE VCC0P9_SVR4
CT48
CT49
CT50
CT51
CT52
CT53
CT54
N6 M11
VCC0P9_SVR_DPAUX_ANA VCC0P9_SVR5 M13
+3.3V_TBT_SX +3.3V_ALW J18 VCC0P9_SVR6 N8 2 2 2 2 2 2 2
L19 VCC0P9_PCIE VCC0P9_SVR7 N11
VCC0P9_ANA_PCIE_11 VCC0P9_SVR8 VCC0P9_SVR:0.9V @ 1.8A max
1 2 M19 N13
@ RT508 0_0603_5% L18 VCC0P9_ANA_PCIE_12 VCC0P9_SVR9 R8
Minimum of 4 vias must be used
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
M16 VCC0P9_ANA_PCIE_21 VCC0P9_SVR10 R11
VCC0P9_ANA_PCIE_22 VCC0P9_SVR11 2 2 2 2 2 2 2
M18 R13
Pin N6
Pin R8
Pin N11
Pin R16
Pin T8
Pin T13
Pin T16
1 1 VCC0P9_ANA_PCIE_23 VCC0P9_SVR12
CT39
CT40
CT370
CT375
CT372
CT371
CT373
CT376
CT374
R16
Pin F18
Pin R6
VCC0P9_SVR13 T8
J8 VCC0P9_SVR14 T16 1 1 1 1 1 1 1 +0.9V_TBT_SVR
2 2 +0.9V_TBT_LC VCC0P9_LC VCC0P9_SVR15 E8
VCC0P9_SVR_BRD_SENSE
VCC
+0.9V_TBT_LVR_OUT H8
H6 VCC0P9_LVR K1 +TBT_SVR_IND LT1 1 2
VCC0P9_LVR_SENSE SVR_IND1 K2 0.6UH_MND-04ABIR60M-XGL_20%
47U_0603_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
C SVR_IND2 L1 C
+VCC3V3_ANA_USB2 SVR_IND3 1 1 1
H18 L2
+VCC3V3_ANA_PCIE VCC3P3_ANA_USB2 SVR_IND4
CT55
CT56
CT57
L16
E16 VCC3P3_ANA_PCIE H1
1U_0201_6.3V6M
1U_0201_6.3V6M
+3.3V_TBT_ANA VCC3P3_ANA SVR_VSS1 2 2 2
J1
10K_0201_5%
SVR_VSS2
1
1 1 +3.3V_TBT_LC V6 J2
VCC3P3_LC SVR_VSS3
CT64
CT63
@ RT498
Pin L16
Pin H18
1U_0201_6.3V6M
+0.9V_TBT_LVR_OUT +0.9V_TBT_LC
2 2 1 SVR_VSS:Minimum of 4 vias must be used.
CT363
A6 AB18
Pin V6
2
A8 VSS_ANA1 VSS_ANA2 AB20

1U_0201_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
2 A12 VSS_ANA5 VSS_ANA6 AC6

1 1 1 1 1 VSS_ANA7 VSS_ANA8
CT59
CT60
CT61
CT62
CT33
A14 AC8
Pin H6
Pin H8
VSS_ANA9 VSS_ANA10 Share Same GND plane

A16 AC10 +3.3V_TBT_S0
Pin J8
VSS_ANA11 VSS_ANA12 VCC3P3_SVR:3.3V @ 0.6A max with SVR_VSS of TR

A18 AC12
2 2 2 2 2 A20 VSS_ANA13 VSS_ANA14 AC14
A22 VSS_ANA15 VSS_ANA16 AC16
B6 VSS_ANA17 VSS_ANA18 AC18
1U_0201_6.3V6M
1U_0201_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
B8 VSS_ANA19 VSS_ANA20 AC20
VSS_ANA21 VSS_ANA22 1 1 1 1
CT38
CT366
CT365
CT364
B10 AC22
Pin E6
Pin L6
B12 VSS_ANA23 VSS_ANA24 E4
B14 VSS_ANA25 VSS_ANA26 F5
+0.9V_TBT_PCIE B16 VSS_ANA27 VSS_ANA28 J12 2 2 2 2
B18 VSS_ANA29 VSS_ANA30 F6
B20 VSS_ANA31 VSS_ANA32 J15
B22 VSS_ANA33 VSS_ANA34 B2
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
D8 VSS_ANA35 VSS_ANA36 B1
D9 VSS_ANA37 VSS_ANA38 D1
1 1 1 1 1 VSS_ANA39 VSS_ANA40
CT34
CT35
CT36
CT37
CT377
D11 A2
Pin L19
Pin L18
Pin M19
Pin M16
D12 VSS_ANA41 VSS_ANA42 J16

D13 VSS_ANA43 VSS_ANA44 V13
2 2 2 2 2 D15 VSS_ANA45 VSS_ANA46 V12
D16 VSS_ANA47 VSS_ANA48 V11
VSS_ANA49 VSS_ANA50
GND
D18 M6
E9 VSS_ANA51 VSS_ANA52 U23
E11 VSS_ANA53 VSS_ANA54 U22
E15 VSS_ANA55 VSS_ANA56 T20
H20 VSS_ANA57 VSS_ANA58 R23
B B
E22 VSS_ANA59 VSS_ANA60 R22
E23 VSS_ANA61 VSS_ANA62 R20
F9 VSS_ANA63 VSS_ANA64 R19
F16 VSS_ANA65 VSS_ANA66 R18
F20 VSS_ANA67 VSS_ANA68 W11
G22 VSS_ANA69 VSS_ANA70 Y11
G23 VSS_ANA71 VSS_ANA72 C23
L20 VSS_ANA73 VSS_ANA74 F15
L22 VSS_ANA75 VSS_ANA76 V9
L23 VSS_ANA77 VSS_ANA78 V15
J19 VSS_ANA79 VSS_ANA80 V20
J20 VSS_ANA81 VSS_ANA82 W8
M20 VSS_ANA87 VSS_ANA88 W23
N20 VSS_ANA89 VSS_ANA90 Y9
N22 VSS_ANA91 VSS_ANA92 Y13
N23 VSS_ANA93 VSS_ANA94 AA22
C22 VSS_ANA95 VSS_ANA96 AA23
E18 VSS_ANA97 VSS_ANA98 AB6
W13 VSS_ANA99 VSS_ANA100 AB8
AB2 VSS_ANA101 VSS_ANA102 AB10
B4 VSS_ANA105 VSS_ANA106 AB14
Y8 VSS_ANA107 VSS_ANA108 AB16
F2 VSS_ANA109 VSS_ANA110 N19
D2 VSS_ANA111 VSS_ANA112 N18
F1 VSS_ANA113 VSS_ANA114 F8
AC4 VSS_ANA115 VSS_ANA116 F13
AB4 VSS_ANA117 VSS_ANA118 F12
Y5 VSS_ANA119 VSS_ANA120 F11
Y12 VSS_ANA121 VSS_ANA122 E13
W12 VSS_ANA123 VSS_ANA124 E12
D6 VSS_ANA125 VSS_ANA126 W15
AB1 VSS_ANA127 VSS_ANA128 Y15
AC2 VSS_ANA129 VSS_ANA130
VSS_ANA131
A A
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
M15
V16
L12
R15
R9
R12
L9
M9
F4
V18
L15
N15
M1
M2
N12
T6
T18
N9
M12
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, TBT-AR-SP(2/2) VCC/VSS
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
5 4 3 2 1
JHL7540-SLMHS_BGA337-X
5 4 3 2 1
+3.3V_TBT_FLASH +3.3V_TBT_FLASH
2
3.3K_0201_5%
3.3K_0201_5%
3.3K_0201_5%
3.3K_0201_5%
1
CT330
RT495
RT494
RT493
RT492
0.1U_0201_10V6K
2
1
UT6 TBT_ROM_DO_PD @ RT544 1 2 0_0201_5%
8 1 TBT_ROM_CS#_PD TBT_ROM_DI_PD @ RT545 1 2 0_0201_5% TBT_ROM_DO <42>
TBT_ROM_HOLD#_PD VCC CS# TBT_ROM_DO_PD TBT_ROM_CLK_PD@ RT546 1 TBT_ROM_DI <42>
7 2 2 0_0201_5%
TBT_ROM_CLK_PD HOLD#(IO3) DO(IO1) TBT_ROM_W P#_PD TBT_ROM_CS#_PD@ RT547 1 TBT_ROM_CLK <42>
6 3 2 0_0201_5%
TBT_ROM_DI_PD CLK WP#(IO2) TBT_ROM_CS# <42>
5 4
DI(IO0) GND
D GD25Q80CSIGR_SO8 D
TR & PD Share ROM
+3.3V_VDD +3.3V_TBT_FLASH
@ RT399 1 2 0_0603_5% +5V_ALW RF request

+5V_ALW
2.2U_0402_10V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
Pin11
Pin12
Pin25
1 1 1
CT75
1
CT76
CT77
RF@
CT22
2 2 2 100P_0201_50V8J
2
+3.3V_ALW
+20V_TBTB_VBUS_1
RT90 1 2 100K_0201_5%MUX1_USB2_FLIP
@ RT91 1 2 100K_0201_5%MUX1_I2C_EN +20V_TBTA_VBUS_1
2.2U_0402_10V6M
10U_0402_6.3V6M
RT92 1 2 100K_0201_5%MUX1_USB2_EN 1 1
RT552 1 2 100K_0201_5%MUX2_USB2_FLIP
CT392
Pin1
Pin2
100K_0201_5%MUX2_I2C_EN
2.2U_0402_25V6M
2.2U_0402_25V6M
@ RT553 1 2
CT393
UT5 1 1
RT554 1 2 100K_0201_5%MUX2_USB2_EN
100K_0201_5%PD_MUX1_EN 2 2
CT83
CT82
RT80 1 2 11 3
RT551 1 2 100K_0201_5%PD_MUX2_EN 12 PP_HV1_1 VBUS2_1 4
+3.3V_ALW PP_HV1_2 VBUS2_2 2 2
1 13
2 PP_HV2_1 VBUS1_1 14
@ RT93 1 2 100K_0201_5%MUX1_USB2_FLIP PP_HV2_2 VBUS1_2
1
RT94 1 2 100K_0201_5%MUX1_I2C_EN +3.3V_TBT_FLASH 25
10U_0402_6.3V6M
Pin5
PP1_CABLE TBTA_CC1 <45>
2 100K_0201_5%MUX2_USB2_FLIP
CT74
@ RT556 1 24
RT555 1 2 100K_0201_5%MUX2_I2C_EN 5 C1_CC1 26
10U_0402_6.3V6M
2 VIN_3V3 C1_CC2
220P_0201_50V7K
220P_0201_50V7K
1 TBTA_CC2 <45>
+1.8V_TBT_LDO 9
CT84
LDO_3V3 1 1
35 50
4.7U_0402_6.3V6M
Pin9
LDO_1V8 C1_USB_P(GPIO18)
CT85
CT86
53
2 C1_USB_N(GPIO19)
1 PD_ADCIN1 6 2 2
CT72
Pin35
C PD_ADCIN2 10 ADCIN1 UPD1_SMBCLK C
27
ADCIN2 I2C1_SCL UPD1_SMBDAT UPD1_SMBCLK <58>
28
2 I2C1_SDA UPD1_SMBINT# UPD1_SMBDAT <58>
29
I2C1_IRQ UPD1_SMBINT# <58>
@ RT110 1 2 0_0201_5% RESET_N 16 32
<42> TBT_RESET_N_PD TBT_I2C_SCL <42> USB only on TBTA_TOP_P/N;TBTB_TOP_P/N
MUX1_USB2_FLIP @ RT77 1 2 0_0201_5% DDM_MUX1_FLIP 17 GPIO0 I2C2_SCL 33
MUX1_I2C_EN GPIO1 I2C2_SDA TBT_I2C_SDA <42>
@ RT78 1 2 0_0201_5% DDM_MUX1_EN 18 34 USB on TBTA_TOP_P/N;TBTB_TOP_P/N
GPIO2 I2C2_IRQ TBT_I2C_INT <42>
30 DDM on TBTA_BOT_P/N;TBTB_BOT_P/N
<42> TBTA_HPD HPD1(GPIO3)
31
<42> TBTB_HPD PD_GPIO5 HPD2(GPIO4) TBT_ROM_DO_PD
@ T219 PAD~D
1 21 36
@ 1 PD_GPIO6 22 GPIO5 SPI_MISO(GPIO8) 37 TBT_ROM_DI_PD
T220 PAD~D GPIO6 SPI_MOSI(GPIO9) TBT_ROM_CLK_PD
23 38
@ RT85 1 2 0_0201_5% PROCHOT#_PD 40 GPIO7 SPI_CLK(GPIO10) 39 TBT_ROM_CS#_PD
<14,58,84,88> PROCHOT# MUX2_USB2_EN @ RT548 1 GPIO12 SPI_SS(GPIO11)
2 0_0201_5% USB2_MUX2_EN 41
MUX2_USB2_FLIP @ RT510 1 2 0_0201_5% DDM_MUX2_FLIP 42 GPIO13
MUX2_I2C_EN @ RT511 1 2 0_0201_5% DDM_MUX2_EN 43 GPIO14(PWM) 44 TBT_HRESET 1 2
48 GPIO15(PWM) HRESET RT101 100K_0201_5%
<82,84> EN_PD_HV_1 GPIO16(PEXT1)
49
<82,84> EN_PD_HV_2 GPIO17(PEXT2) PD_DRAIN1
8 USB only on TBTA_BOT_P/N;TBTB_BOT_P/N
54 DRAIN1_1 15
MUX1_USB2_EN @ RT79 1 2 0_0201_5% USB2_MUX1_EN 55 C2_USB_P(GPIO20) DRAIN1_2 19 USB on TBTA_BOT_P/N;TBTB_BOT_P/N
C2_USB_N(GPIO21) DRAIN1_3 58 PD_DRAIN1,PD_DRAIN2 are thermal pad DDM on TBTA_TOP_P/N;TBTB_TOP_P/N
20 DRAIN1_4
<46> TBTB_CC1 Can't conection to GND
45 GND_1 7 PD_DRAIN2
46 C2_CC1 DRAIN2_1 52 +3.3V_ALW
+5V_ALW PP2_CABLE DRAIN2_2
47 56
C2_CC2 DRAIN2_3
220P_0201_50V7K
220P_0201_50V7K
51 57
<46> TBTB_CC2 GND_2 DRAIN2_4
59
0.1U_0201_10V6K
1 1 GND_3
10U_0402_6.3V6M
1
CT73
CT71
CT80
1 SA0000CM61L
Pin46
SN1702027RSHR_VQFN56_7X7~D
2 2
CT383
Dell PN:SN1702027RSHR 2
2 TI PN:TPS65988DJRSHR UT13
Need CHECK <45> TBTA_TOP_P

13
1
VCC A1_OUTp
A1_OUTn
20
19
UPD1_SMBCLK
UPD1_SMBDAT
2 A_INp 18
<45> TBTA_TOP_N A_INn A0_OUTp 17
BUSPOWER Config MUX1_USB2_FLIP
PD_MUX1_EN
14
16 SAI
A0_OUTn
15 MUX1_I2C_EN
B BP_NoWait value 0.7~0.78 EN_A SAO 0_0201_5%
0_0201_5%
2
2
1 RT400 @
1 RT401 @ TBTA_USB20_P <42> B
TBT_A_USB20_P_R TBTA_USB20_N <42>
3 6 0_0201_5% 2 1 RT402 @
<45> TBTA_BOT_P B_INp B1_OUTp TBT_A_USB20_N_R USB20_P1 <10>
4 7 0_0201_5% 2 1 RT403 @
<45> TBTA_BOT_N B_INn B1_OUTn USB20_N1 <10>
MUX1_USB2_FLIP 12 8
+3.3V_TBT_FLASH PD_MUX1_EN 10 SBI B0_OUTp 9
EN_B B0_OUTn
5 11 MUX1_USB2_EN
100K_0201_1%
GND SBO
1
21
Thermal pad
RT86
R1 TS3DS10224RUKR_W QFN20_3X3-X
2
PD_ADCIN1
1
300K_0201_1%
RT87
R2 +3.3V_ALW
2
0.1U_0201_10V6K
1
CT368
2
UT14
13 20 UPD1_SMBCLK
VCC A1_OUTp 19 UPD1_SMBDAT
Need CHECK <46>

<46>
TBTB_TOP_P
TBTB_TOP_N
1
2 A_INp
A_INn
A1_OUTn
A0_OUTp
18
17
MUX2_USB2_FLIP 14 A0_OUTn
I2C Address Divider:010b PD_MUX2_EN 16 SAI
EN_A SAO
15 MUX2_I2C_EN
0_0201_5% 2 1 RT519 @
TBTB_USB20_P <42>
0_0201_5% 2 1 RT518 @
TBT_B_USB20_P_R TBTB_USB20_N <42>
3 6 0_0201_5% 2 1 RT521 @
<46> TBTB_BOT_P B_INp B1_OUTp TBT_B_USB20_N_R USB20_P2 <10>
4 7 0_0201_5% 2 1 RT520 @
+3.3V_TBT_FLASH <46> TBTB_BOT_N B_INn B1_OUTn USB20_N2 <10>
MUX2_USB2_FLIP 12 8
PD_MUX2_EN 10 SBI B0_OUTp 9
100K_0201_1%
A A
1
EN_B B0_OUTn
5 11 MUX2_USB2_EN
RT88
R1 21 GND
Thermal pad
SBO
TS3DS10224RUKR_W QFN20_3X3-X
2
PD_ADCIN2
1
100K_0201_1%
RT89
R2 DELL CONFIDENTIAL/PROPRIETARY
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT [Type C]PD Controller TI
5 4 3 2 1
5 4 3 2 1
+20V_TBTA_VBUS +20V_TBTA_VBUS RF Request

JUSBC1 CONN@
A1 B12 +20V_TBTA_VBUS
GND_1 GND_4 +20V_TBTA_VBUS
TBT_A_TTX_C_DRX_P2 A2 B11 TBT_A_TRX_C_DTX_P2
TBT_A_TTX_C_DRX_N2 A3 SSTXP1 SSRXP1 B10 TBT_A_TRX_C_DTX_N2
SSTXN1 SSRXN1
2 1 A4 B9 2 1
VBUS_1 VBUS_4
1
CT99 0.47U_0201_25V CT100 0.47U_0201_25V
TBTA_CC2 A5 B8 TBTA_SBU1 ESD@
<44> TBTA_CC2 CC1 SUB2 TBTA_SBU1 <42>
12P_0201_50V8J
RF@ CT189
82P_0201_50V8J
RF@ CT190
1 1 DT4
0_0201_5% 2 1 RT123 @EMI@TBTA_BOT_P_R A6 B7 TBTA_TOP_N_R 0_0201_5% 2 1 RT121 @EMI@ AZ4A24-01F.R7G_DFN0603P2Y2
<44> TBTA_BOT_P DP1 DN2 TBTA_TOP_N <44>
0_0201_5% 2 1 RT122 @EMI@TBTA_BOT_N_R A7 B6 TBTA_TOP_P_R 0_0201_5% 2 1 RT120 @EMI@
<44> TBTA_BOT_N DN1 DP2 TBTA_TOP_P <44>
Bottom
D D
2
TBTA_SBU2 A8 B5 TBTA_CC1 2 2
<42> TBTA_SBU2 SUB1 CC2 TBTA_CC1 <44>
TOP
2 1 A9 B4 2 1
0.47U_0201_25V CT101 VBUS_2 VBUS_3 CT102 0.47U_0201_25V
TBT_A_TRX_C_DTX_N1 A10 B3 TBT_A_TTX_C_DRX_N1
TBT_A_TRX_C_DTX_P1 A11 SSRXN2 SSTXN2 B2 TBT_A_TTX_C_DRX_P1
SSRXP2 SSTXP2
A12 B1
GND_2 GND_3
1 4
GND_5 GND_8
2 3
5 GND_6 GND_7 6
7 GND_9 GND_10 8
EMI Request
NPTH_1 NPTH_2
JAE_DX07SD24JJ4-X +20V_TBTA_VBUS
0.1U_0201_25V6K
EMI@ CT394
0.1U_0201_25V6K
EMI@ CT395
1 1
2 2
C C
AC coupling is recommended for

Place holder for future VBUS-short VBUS-short protection on SSRX lines. If not
fix (reduce current surge) needed, place 0 Ohm resistor instead.
TBT_A_TRX_DTX_P1 RT190 1 2 2.2_0201_1% TBT_A_TRX_R_DTX_P1 CT326 1 2 0.33U_0201_25V6K TBT_A_TRX_C_DTX_P1
<42> TBT_A_TRX_DTX_P1 TBT_A_TRX_DTX_N1 RT191 1 2 2.2_0201_1% TBT_A_TRX_R_DTX_N1 CT327 1 2 0.33U_0201_25V6K TBT_A_TRX_C_DTX_N1
<42> TBT_A_TRX_DTX_N1
TBT_A_TTX_DRX_P1 RT192 1 2 2.2_0201_1% TBT_A_TTX_R_DRX_P1 CT95 1 2 0.22U_0201_25V6K TBT_A_TTX_C_DRX_P1
<42> TBT_A_TTX_DRX_P1 TBT_A_TTX_DRX_N1 TBT_A_TTX_R_DRX_N1 TBT_A_TTX_C_DRX_N1
RT193 1 2 2.2_0201_1% CT96 1 2 0.22U_0201_25V6K
<42> TBT_A_TTX_DRX_N1
ESD@ DT5 ESD@ DT13
TBT_A_TRX_DTX_P2 RT194 1 2 2.2_0201_1% TBT_A_TRX_R_DTX_P2 CT328 1 2 0.33U_0201_25V6K TBT_A_TRX_C_DTX_P2
<42> TBT_A_TRX_DTX_P2 TBT_A_TRX_DTX_N2 RT195 1 2 2.2_0201_1% TBT_A_TRX_R_DTX_N2 CT329 1 2 0.33U_0201_25V6K TBT_A_TRX_C_DTX_N2 TBT_A_TTX_R_DRX_P1 1 2 TBT_A_TRX_R_DTX_P1 1 2
<42> TBT_A_TRX_DTX_N2
TBT_A_TTX_DRX_P2 RT196 1 2 2.2_0201_1% TBT_A_TTX_R_DRX_P2 CT97 1 2 0.22U_0201_25V6K TBT_A_TTX_C_DRX_P2 AZ5B8S-01F.R7G_DFN0603P2Y2 AZ5B8S-01F.R7G_DFN0603P2Y2
<42> TBT_A_TTX_DRX_P2 TBT_A_TTX_DRX_N2 1 2 2.2_0201_1% TBT_A_TTX_R_DRX_N2 TBT_A_TTX_C_DRX_N2
RT197 CT98 1 2 0.22U_0201_25V6K
<42> TBT_A_TTX_DRX_N2
ESD@ DT6 ESD@ DT14
TBT_A_TTX_R_DRX_N1 1 2 TBT_A_TRX_R_DTX_N1 1 2
AZ5B8S-01F.R7G_DFN0603P2Y2 AZ5B8S-01F.R7G_DFN0603P2Y2
Discharge SSTX/SSRX resistors - must be ESD@ DT9 ESD@ DT17
B
placed if 330nF cap is being used. TBT_A_TRX_R_DTX_P2 1 2 TBT_A_TTX_R_DRX_P2 1 2 B
TBT_A_TTX_C_DRX_P2 1 2 TBT_A_TRX_C_DTX_P2 1 2 AZ5B8S-01F.R7G_DFN0603P2Y2 AZ5B8S-01F.R7G_DFN0603P2Y2

RT491 221K_0201_1% RT221 221K_0201_1%
TBT_A_TTX_C_DRX_N2 1 2 TBT_A_TRX_C_DTX_N2 1 2 ESD@ DT10 ESD@ DT18
RT490 221K_0201_1% RT222 221K_0201_1%
TBT_A_TTX_C_DRX_P1 1 2 TBT_A_TRX_C_DTX_P1 1 2 TBT_A_TRX_R_DTX_N2 1 2 TBT_A_TTX_R_DRX_N2 1 2
RT488 221K_0201_1% RT219 221K_0201_1%
TBT_A_TTX_C_DRX_N1 1 2 TBT_A_TRX_C_DTX_N1 1 2 AZ5B8S-01F.R7G_DFN0603P2Y2 AZ5B8S-01F.R7G_DFN0603P2Y2
RT489 221K_0201_1% RT220 221K_0201_1%
DT39 ESD@ DT40 ESD@

TBTA_SBU1 1 1 TBTA_SBU1 TBTA_SBU2 TBTA_SBU2
10 9 1 1 10 9
TBTA_TOP_N_R 2 2 9 8 TBTA_TOP_N_R TBTA_BOT_N_R 2 9 8 TBTA_BOT_N_R
2
TBTA_TOP_P_R 4 4 7 7 TBTA_TOP_P_R TBTA_BOT_P_R 4 7 7 TBTA_BOT_P_R
4
TBTA_CC1 5 5 6 6 TBTA_CC1 TBTA_CC2 5 5 6 6 TBTA_CC2
3 3 3 3
8 8
A A
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
USB 3.0 CONN TYPE C
5 4 3 2 1
5 4 3 2 1
+20V_TBTB_VBUS +20V_TBTB_VBUS RF Request

JUSBC2 CONN@
A1 B12 +20V_TBTB_VBUS
GND_1 GND_4 +20V_TBTB_VBUS
TBT_B_TTX_C_DRX_P2 A2 B11 TBT_B_TRX_C_DTX_P2
TBT_B_TTX_C_DRX_N2 A3 SSTXP1 SSRXP1 B10 TBT_B_TRX_C_DTX_N2
SSTXN1 SSRXN1
2 1 A4 B9 2 1
VBUS_1 VBUS_4
1
CT385 0.47U_0201_25V CT386 0.47U_0201_25V
TBTB_CC2 A5 B8 TBTB_SBU1 ESD@
<44> TBTB_CC2 CC1 SUB2 TBTB_SBU1 <42>
12P_0201_50V8J
RF@ CT382
82P_0201_50V8J
RF@ CT381
1 1 DT47
0_0201_5% 2 1 RT533 @EMI@TBTB_BOT_P_R A6 B7 TBTB_TOP_N_R 0_0201_5% 2 1 RT532 @EMI@ AZ4A24-01F.R7G_DFN0603P2Y2
<44> TBTB_BOT_P DP1 DN2 TBTB_TOP_N <44>
0_0201_5% 2 1 RT535 @EMI@TBTB_BOT_N_R A7 B6 TBTB_TOP_P_R 0_0201_5% 2 1 RT534 @EMI@
<44> TBTB_BOT_N DN1 DP2 TBTB_TOP_P <44>
Bottom
D D
2
TBTB_SBU2 A8 B5 TBTB_CC1 2 2
<42> TBTB_SBU2 SUB1 CC2 TBTB_CC1 <44>
TOP
2 1 A9 B4 2 1
0.47U_0201_25V CT369 VBUS_2 VBUS_3 CT387 0.47U_0201_25V
TBT_B_TRX_C_DTX_N1 A10 B3 TBT_B_TTX_C_DRX_N1
TBT_B_TRX_C_DTX_P1 A11 SSRXN2 SSTXN2 B2 TBT_B_TTX_C_DRX_P1
SSRXP2 SSTXP2
A12 B1
GND_2 GND_3
1 4
GND_5 GND_8
2 3
5 GND_6 GND_7 6
7 GND_9 GND_10 8
NPTH_1 NPTH_2
JAE_DX07SD24JJ4-X
C C
AC coupling is recommended for

Place holder for future VBUS-short VBUS-short protection on SSRX lines. If not
fix (reduce current surge) needed, place 0 Ohm resistor instead.
TBT_B_TRX_DTX_P1 RT536 1 2 2.2_0201_1% TBT_B_TRX_R_DTX_P1 CT391 1 2 0.33U_0201_25V6K TBT_B_TRX_C_DTX_P1
<42> TBT_B_TRX_DTX_P1 TBT_B_TRX_DTX_N1 RT538 1 2 2.2_0201_1% TBT_B_TRX_R_DTX_N1 CT379 1 2 0.33U_0201_25V6K TBT_B_TRX_C_DTX_N1
<42> TBT_B_TRX_DTX_N1
TBT_B_TTX_DRX_P1 RT537 1 2 2.2_0201_1% TBT_B_TTX_R_DRX_P1 CT388 1 2 0.22U_0201_25V6K TBT_B_TTX_C_DRX_P1
<42> TBT_B_TTX_DRX_P1 TBT_B_TTX_DRX_N1 TBT_B_TTX_R_DRX_N1 TBT_B_TTX_C_DRX_N1
RT539 1 2 2.2_0201_1% CT390 1 2 0.22U_0201_25V6K
<42> TBT_B_TTX_DRX_N1
ESD@ DT55 ESD@ DT50
TBT_B_TRX_DTX_P2 RT540 1 2 2.2_0201_1% TBT_B_TRX_R_DTX_P2 CT378 1 2 0.33U_0201_25V6K TBT_B_TRX_C_DTX_P2
<42> TBT_B_TRX_DTX_P2 TBT_B_TRX_DTX_N2 RT541 1 2 2.2_0201_1% TBT_B_TRX_R_DTX_N2 CT380 1 2 0.33U_0201_25V6K TBT_B_TRX_C_DTX_N2 TBT_B_TTX_R_DRX_P1 1 2 TBT_B_TRX_R_DTX_P1 1 2
<42> TBT_B_TRX_DTX_N2
TBT_B_TTX_DRX_P2 RT542 1 2 2.2_0201_1% TBT_B_TTX_R_DRX_P2 CT389 1 2 0.22U_0201_25V6K TBT_B_TTX_C_DRX_P2 AZ5B8S-01F.R7G_DFN0603P2Y2 AZ5B8S-01F.R7G_DFN0603P2Y2
<42> TBT_B_TTX_DRX_P2 TBT_B_TTX_DRX_N2 1 2 2.2_0201_1% TBT_B_TTX_R_DRX_N2 TBT_B_TTX_C_DRX_N2
RT543 CT384 1 2 0.22U_0201_25V6K
<42> TBT_B_TTX_DRX_N2
ESD@ DT48 ESD@ DT53
TBT_B_TTX_R_DRX_N1 1 2 TBT_B_TRX_R_DTX_N1 1 2
AZ5B8S-01F.R7G_DFN0603P2Y2 AZ5B8S-01F.R7G_DFN0603P2Y2
Discharge SSTX/SSRX resistors - must be ESD@ DT51 ESD@ DT54
B
placed if 330nF cap is being used. TBT_B_TRX_R_DTX_P2 1 2 TBT_B_TTX_R_DRX_P2 1 2 B
TBT_B_TTX_C_DRX_P2 1 2 TBT_B_TRX_C_DTX_P2 1 2 AZ5B8S-01F.R7G_DFN0603P2Y2 AZ5B8S-01F.R7G_DFN0603P2Y2

RT524 221K_0201_1% RT527 221K_0201_1%
TBT_B_TTX_C_DRX_N2 1 2 TBT_B_TRX_C_DTX_N2 1 2 ESD@ DT49 ESD@ DT52
RT526 221K_0201_1% RT530 221K_0201_1%
TBT_B_TTX_C_DRX_P1 1 2 TBT_B_TRX_C_DTX_P1 1 2 TBT_B_TRX_R_DTX_N2 1 2 TBT_B_TTX_R_DRX_N2 1 2
RT528 221K_0201_1% RT529 221K_0201_1%
TBT_B_TTX_C_DRX_N1 1 2 TBT_B_TRX_C_DTX_N1 1 2 AZ5B8S-01F.R7G_DFN0603P2Y2 AZ5B8S-01F.R7G_DFN0603P2Y2
RT525 221K_0201_1% RT531 221K_0201_1%
DT45 ESD@ DT46 ESD@

TBTB_SBU1 1 1 TBTB_SBU1 TBTB_SBU2 TBTB_SBU2
10 9 1 1 10 9
TBTB_TOP_N_R 2 2 9 8 TBTB_TOP_N_R TBTB_BOT_N_R 2 9 8 TBTB_BOT_N_R
2
TBTB_TOP_P_R 4 4 7 7 TBTB_TOP_P_R TBTB_BOT_P_R 4 7 7 TBTB_BOT_P_R
4
TBTB_CC1 5 5 6 6 TBTB_CC1 TBTB_CC2 5 5 6 6 TBTB_CC2
3 3 3 3
8 8
A A
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
USB 3.0 CONN TYPE C
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
TYPE-C_Port2 (2/2)
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
TYPE-C_Port3 (1/2)
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
TYPE-C_Port3 (2/2)
5 4 3 2 1
5 4 3 2 1
D D
C Reserve for external PD power C
B B
A A
[Type C]PD Power
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
LAN
5 4 3 2 1
5 4 3 2 1
+3.3V_WLAN
+1.8V_PRIM
+3.3V_WLAN
W L1 AC@
4
5 3.3V 0
3.3V 1 PCIE_W AKE#
0.01U_0201_25V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
0.01U_0201_25V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
72 29
73 3.3V 2 PEWAKE# 30 PCIE_W AKE# <42,59,68,74>
1 1 1 1 1 1 3.3V 3 CLKREQ# PCH_PLTRST#_AND CLKREQ_PCIE#1 <11> CNV_BRI_PTX_DRX_1P8_R
A48 31 @ RZ603 1 2 10K_0201_5%
3.3V 4 PERST# PCH_PLTRST#_AND <11,38,42,68,70,74>
CZ28
CZ30
CZ27
CZ29
CZ31
CZ32
A49
3.3V 5
2 2 2 2 2 2 27 W IGIG_32KHZ 0_0201_5% 2 1 @ RZ56
SUSCLK(32KHZ)(3.3V) SUSCLK <11,68>
1
2 UIM_POWER_SRC/GPIO1 14
3 UIM_POWER_SNK SYSCLK/GNSS0 15
UIM_SWP TX_BLANKING/GNSS1
Place near JNGFF1.72/JNGFF1.73 Place near JNGFF1.4/JNGFF1.5 W LAN_COEX1 11 7

D W LAN_COEX2 12 COEX_TXD RESERVED 0 D
W LAN_COEX3 13 COEX_RXD
COEX3
6
@RF@ RZ128 1 2 0_0201_5% W LAN_COEX3 16 GND 0 17
<74> W W AN_COEX3 W LAN_COEX2 RESERVED 1 GND 1
@RF@ RZ129 1 2 0_0201_5% 18 20
<74> W W AN_COEX2 W LAN_COEX1 RESERVED 2 GND 2
@RF@ RZ130 1 2 0_0201_5% 19 23
<74> W W AN_COEX1 RESERVED 3 GND 3
21 26
22 RESERVED 4 GND 4 32
@RF@ RZ373 1 2 0_0201_5% 24 RESERVED 5 GND 5 35
CNV_COEX1_1P8 <6> RESERVED 6 GND 6
@RF@ RZ372 1 2 0_0201_5% 25 38
@RF@ RZ374 1 2 0_0201_5% 66 41
67 62
RESERVED 9 GND 9 68
GND 10 71
33 GND 11 74
<11> CLK_PCIE_N1 REFCLKN0 GND 12
34 75
<11> CLK_PCIE_P1 REFCLKP0 GND 13 76
CZ13 1 2 0.1U_0201_25V6K PCIE_PTX_C_DRX_N10 39 GND 14 77
<10> PCIE_PTX_DRX_N10 PETN0 GND 15
CZ12 1 2 0.1U_0201_25V6K PCIE_PTX_C_DRX_P10 40 78
<10> PCIE_PTX_DRX_P10 PETP0 GND 16 79
36 GND 17 80
<10> PCIE_PRX_DTX_N10 37 PERN0 GND 18 81
<10> PCIE_PRX_DTX_P10 PERP0 GND 19 82
GND 20 83
42 GND 21 84
<8> PCH_CL_CLK1 CLINK_CLK GND 22
43 85
<8> PCH_CL_DATA1 CLINK_DATA GND 23
44 86
<8> PCH_CL_RST1# CLINK_RESET GND 24 87
GND 25 88 +3.3V_ALW
45 GND 26 89
46 SDIO_RESET# GND 27 90
47 SDIO_WAKE# GND 28 91
SDIO_DATA3 GND 29
1
48 92
49 SDIO_DATA2 GND 30 93 @ RZ377
50 SDIO_DATA1 GND 31 94 100K_0201_5%
51 SDIO_DATA0 GND 32 95
52 SDIO_CMD GND 33 96
2
SDIO_CLK GND 34 G1 0_0201_5% 2 1 @ RZ827
GND 35 <58> CNV_DET#_EC CNVI_EN# <12>
G2
53 GND 36 G3
CNV_BRI_PTX_DRX_1P8_R 1.8V 54 UART_WAKE#(3.3V) GND 37 G4
C CNV_BRI_PRX_DTX_1P8_R LPSS_UART_RTS/BRI_DT GND 38 C
1.8V 55 G5
LPSS_UART_RXD/BRI_RSP GND 39
1
CNV_RGI_PTX_DRX_1P8_R 1.8V 56 G6
CNV_RGI_PRX_DTX_1P8_R 1.8V 57 LPSS_UART_TXD/RGI_DT GND 40 G7 D
LPSS_UART_CTS/RGI_RSP GND 41 G8
GND 42 G9 2 G @ QZ17
CNV_RF_RESET#_1P8 GND 43 <12> CNV_RF_RESET#_1P8
1.8V 58 G10 PJE138K_SOT-523-3
1 2 CLKREQ_CNV_1P8_R 1.8V 59 PCM_SYNC/I2S_WS GND 44 G11 75K PD at PCH side S
<12> CLKREQ_CNV_1P8 PCM_OUT/I2S_SD_OUT GND 45
@ RZ1385 0_0201_5% 60 G12 VGS(th)Max=1.5V
3
61 PCM_IN/I2S_SD_IN GND 46 A07
PCM_CLK/I2S_SCK GND 47 A26
GND 48 A31 1 2 WLAN_WIGIG60GHZ_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R GND 49 <58> W LAN_W IGIG60GHZ_DIS#
28 A50
BT_RADIO_DIS# 63 W_DISABLE1# GND 50 DZ1
W_DISABLE2# RB751S-40_SOD523-2
A11
65 RESERVED 10 A12
64 LED1# RESERVED 11 A13
LED2# RESERVED 12 A14
RESERVED 13 A16
USB20_N10_R 69 RESERVED 14 A17
USB20_P10_R 70 USB_D- RESERVED 15 A18 DZ16
USB_D+ RESERVED 16 A27 RB751S-40_SOD523-2
RESERVED 17 A28 1 2
@ 1 ISH_UART0_CTS#_R 8 RESERVED 18 A29
T455 PAD~D ISH_UART0_TXD_R ALERT# RESERVED 19 BT_RADIO_DIS#
@ 1 9 A30 1 2
T456 PAD~D ISH_UART0_RXD_R I2C_CLK RESERVED 20 <58> EC_BT_RADIO_DIS#
@ 1 10 A46 @ RZ300 0_0201_5%
T457 PAD~D I2C_DATA RESERVED 21 A47 1 2
RESERVED 22 <14> PCH_BT_RADIO_DIS#
CNV_RF_RESET#_1P8 1.8V A42 DZ2
RF_RESET_B A08 RB751S-40_SOD523-2
CLKREQ_CNV_1P8_R 1.8V A43 A4WP_IRQ# A09
A44 CLKREQ0 A4WP_CLK A10
<11> REFCLK_CNV_L REFCLK0 A4WP_DATA A15
LNA_EN A25 W IGIG_32KHZ
1
@ A45 C_P32K
RZ752 NC
10K_0201_5% A19 CLK_CNV_PTX_DRX_P
WT_CLKP CLK_CNV_PTX_DRX_N CLK_CNV_PTX_DRX_P <6>
A20
WT_CLKN CNV_PTX_DRX_P0 CLK_CNV_PTX_DRX_N <6>
A21
CNV_PTX_DRX_P0 <6>
2
WT_D0P A22 CNV_PTX_DRX_N0

WT_D0N CNV_PTX_DRX_P1 CNV_PTX_DRX_N0 <6>
A23
WT_D1P CNV_PTX_DRX_N1 CNV_PTX_DRX_P1 <6>
B A24 B
WT_D1N CNV_PTX_DRX_N1 <6>
A32 CLK_CNV_PRX_DTX_P RF Request Place near WL1
WGR_CLKP A33 CLK_CNV_PRX_DTX_N CLK_CNV_PRX_DTX_P <6>
+3.3V_WLAN
WGR_CLKN A34 CNV_PRX_DTX_P0 CLK_CNV_PRX_DTX_N <6>
WGR_D0P A35 CNV_PRX_DTX_N0 CNV_PRX_DTX_P0 <6>
WGR_D0N A36 CNV_PRX_DTX_P1 CNV_PRX_DTX_N0 <6>
WGR_D1P A37 CNV_PRX_DTX_N1 CNV_PRX_DTX_P1 <6>
WGR_D1N CNV_PRX_DTX_N1 <6>
15P_0201_50V8J
15P_0201_50V8J
15P_0201_50V8J
15P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
CNV_BRI_PTX_DRX_1P8_R
RF@ CZ33
RF@ CZ34
RF@ CZ35
RF@ CZ36
RF@ CZ204
RF@ CZ205
27P_0201_25V8
RF@ CZ206
27P_0201_25V8
RF@ CZ207
A38 1.8V
BRI_DT CNV_BRI_PRX_DTX_1P8_R RZ1381 1 CNV_BRI_PTX_DRX_1P8_R <9>
A39 1.8V 2 22_0201_5% 1 1 1 1 1 1 1 1
BRI_RSP CNV_RGI_PTX_DRX_1P8_R CNV_BRI_PRX_DTX_1P8 <9>
A40 1.8V
RGI_DT CNV_RGI_PRX_DTX_1P8_R RZ1383 1 CNV_RGI_PTX_DRX_1P8_R <9>
A41 1.8V 2 22_0201_5%
RGI_RSP CNV_RGI_PRX_DTX_1P8 <9>
2 2 2 2 2 2 2 2
9560.D2W D.NV
RF Request
MCM1012B900F06BP_4P
4 3 USB20_N10_R
<10> USB20_N10
1 2 USB20_P10_R
<10> USB20_P10
LI9 RF@
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NGFF Card
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
WIGIG / WIDI
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
USB/PCIE MUX HD3SS3212
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
Reserve for PCIE device
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Codec ALC3204
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
Audio Ampfilper
5 4 3 2 1
5 4 3 2 1
+1.8V_PRIM
@ RE32 1 2 0_0402_5% +RTC_CELL_VBAT SAR_DPR1#_1P8 1 2

+RTC_CELL
RE521 10K_0201_5%
SAR_DPR2#_1P8
0.1U_0201_10V6K
1 1 2
CE11
RE832 10K_0201_5%
+3.3V_ALW
+3.3V_ALW_UE1
JUMP@
1U_0201_6.3V6M
2 UPD1_SMBDAT
0.1U_0201_10V6K
0.1U_0201_10V6K
PJP22 1 2
+3.3V_ALW 1 2 1 1 1 RE302 2.2K_0201_5%
+3.3V_ALW_UE1_VTR1 UPD1_SMBCLK
10U_0402_6.3V6M
1 2
CE14
CE13
CE23
PAD-OPEN1x1m RE303 2.2K_0201_5%
1 SA0000CQ730 : ES, non-signed (Similar X10 MEC5105) UPD1_SMBINT#
0.1U_0201_10V6K
1 2
2 2 2
SA0000CQ740 : Non-ES, signed (SimilarX10 MEC5106)
CE16
1 RE91 100K_0201_5%
EPRIVACY_EN
CE19
1 2
2 UE1 5107ES@ @ RE92 100K_0201_5%
D3 TYPEC_ID PBAT_CHARGER_SMBDAT 1 2
2 GPIO033/RC_ID0 SYSTEM_ID TYPEC_ID <59>
F5 K14 SYSTEM_ID <74> RE37 2.2K_0201_5%
VBAT GPIO034/RC_ID1/SPI0_CLK J12 BOARD_ID PBAT_CHARGER_SMBCLK 1 2
D GPIO036/RC_ID2/SPI0_MISO BOARD_ID <59> D
F9 C4 RE43 2.2K_0201_5%
close to pin F6 2 1 VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# B3 SIO_SLP_SUS#_R 1 2
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI
0.1U_0201_10V6K
0_0402_5% @ RE314 J3 @NDS3@ RE561 100K_0201_5%
VREF_ADC C1 RUNPW ROK NGFF_CONFIG_1 1 2
1 +3.3V_EC_PLL GPIO057/VCC_PWRGD GPS_DISABLE#
CE18
D1 E2 RE723 100K_0201_5%
+3.3V_ALW_UE1_VTR2 VTR_PLL GPIO060/KBRST/48MHZ_OUT GPS_DISABLE# <74> NGFF_CONFIG_2
C13 1 2
GPIO104/UART0_TX HOST_DEBUG_TX <79>
H5 G14 RE724 100K_0201_5%
2 VTR_REG GPIO105/UART0_RX RTCRST_ON_POW ER ME_FWP <79> NGFF_CONFIG_0
0.1U_0201_10V6K
C12 1 2
1 2 +3.3V_ALW _UE1_VTR1 F6 GPIO127/A20M/UART0_CTS# E10 UPD1_SMBINT# RE725 100K_0201_5%
1 +3.3V_ALW_UE1 VTR1 GPIO225/UART0_RTS# UPD1_SMBINT# <44> NGFF_CONFIG_3
2 0_0402_5% +3.3V_ALW _UE1_VTR2
CE20
@ RE315 1 J8 1 2
close to pin J8 @ RE316 0_0402_5% 1.8V J6 VTR2 L10 PCIE_W AKE#_R RE726 100K_0201_5%
+3.3V_ALW_UE1 +1.8V_PRIM_VTR3 VTR3 GPIO025/TIN0/nEM_INT/UART_CLK PCIE_WAKE#_R <59> USB_PW R_EN2#
P14 1 2
2 PCH_DPW ROK_EC GPIO026/TIN1 PTP_DIS# <63>
0.1U_0201_10V6K
1 1 2 P1 N14 @ RE727 100K_0201_5%
<11> PCH_DPWROK RUN_ON_EC GPIO020 GPIO027/TIN2 FPR_PWR_EN# <74> USB_POW ERSHARE_EN#
DS3@ RE536 0_0201_5% A8 L12 1 2
<59> RUN_ON_EC SSD_SCP# GPIO045 GPIO030/TIN3 FPR_SSO_EN# <74>
CE15
M12 RE728 100K_0201_5%
<68> SSD_SCP# EC_BT_RADIO_DIS# GPIO120 VGA_IDENTIFY USB_PW R_EN1#
close to pin J8 A1 N10 1 2
2 <52> EC_BT_RADIO_DIS# PBAT_PRES# GPIO166 GPIO017/GPTP-IN5
F10 M10 RE729 100K_0201_5%
<83> PBAT_PRES# SIO_SLP_SUS#_R GPIO175 GPIO151/ICT4 NGFF_CONFIG_1 <74> USB_POW ERSHARE_VBUS_EN
1 2 M8 N11 1 2
<11> SIO_SLP_SUS# PANEL_MONITOR GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 <74>
DS3@ RE349 43K_0201_1% <79> PANEL_MONITOR
K9 RE730 100K_0201_5%
P7 GPIO231 E11 AC_DIS 1 2
<11> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <74>
Close to pin H5 D10 @ RE83 100K_0201_5%
<12> SIO_SLP_SUS#_R GPIO157/LED1 BAT1_LED# <64> GPS_DISABLE#
<8>
SML1_SMBDATA C10 D11 1 2
GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <64>
RF Request Reserved for support TOP SWAP feature <8> SML1_SMBCLK
E8 B1 RE106 100K_0201_5%
GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <38> W LAN_W IGIG60GHZ_DIS#
L14 1 2
+3.3V_ALW <52> CNV_DET#_EC FPR_LOW _PW R_MODE# M13 GPIO110/PS2_CLK2 A3 RE8 100K_0201_5%
<74> FPR_LOW_PWR_MODE# W LAN_W IGIG60GHZ_DIS# K11 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_EXPANDER_SMBDAT <66,74> LED_MASK#
B4 1 2
<52> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 VCCDSW _EN USH_EXPANDER_SMBCLK <66,74>
M14 L1 @ RE21 100K_0201_5%
<11> SIO_PWRBTN# SLP_W LAN#_GATE_R GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 360_SENSOR_DET#_R VCCDSW_EN <11> @ RE838 1
@ RE552 1 2 0_0201_5% K10 K7 2 0_0201_5% THERMTRIP1# 1 2
<78> SLP_WLAN#_GATE GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 PBAT_CHARGER_SMBDAT 360_SENSOR_DET# <9,66>
M11 N1 RE301 10K_0201_5%
<59,74> LID_CL_SIO# GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <83,84> PCIE_W AKE#_R
E9 M1 1 2
<63> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <83,84>
C9 P13 NGFF_CONFIG_2 <74> RE35 10K_0201_5%
<63> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA LED_MASK# FPR_PW R_EN#
12P_0201_50V8J
RF@ CE59
68P_0201_50V8J
RF@ CE60
P11 1 2
GPIO140/SMB06_CLK/ICT5 LED_MASK# <74>
1 1 B6 A5 RE704 100K_0201_5%
<79> JTAG_TDI E7 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD#/TRACEDAT0 B5 FPR_SCAN_INT#_EC 1 2
<79> JTAG_TDO B8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR#/TRACEDAT1 C5 UPD1_SMBDAT RE826 100K_0201_5%
<79> JTAG_CLK GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#/TRACEDAT2 UPD1_SMBCLK UPD1_SMBDAT <44> BC_DAT_ECE1117
C7 C6 1 2
2 2 <79> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI#/TRACEDAT3 UPD1_SMBCLK <44>
H9 RE365 100K_0201_5%
JTAG_RST# G5 I_BATT_R RE64 1 2 300_0201_5% SSD_SCP# 1 2
GPIO200/ADC00 I_SYS_R <84> I_BATT
F1 J5 RE312 1 2 300_0201_5% @ RE821 100K_0201_5%
<77> TACH_FAN1 EPRIVACY_EN GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 <84,88,96> I_SYS VCCDSW _EN EC_BT_RADIO_DIS#
F2 G3 1 2
<38> EPRIVACY_EN LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 TOUCHPAD_INTR#_R ISH_NB_MODE# <9,74>
K8 J1 @ RE318 1 2 0_0201_5% RE11 100K_0201_5%
<38> LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 USH_PW R_STATE#_R TOUCHPAD_INTR# <14,63> FPR_DET#
0.1U_0201_10V6K
N13 K2 @ RE608 2 1 0_0201_5% 1 2
C <77> PWM_FAN1 W W AN_DET# GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_POW ERSHARE_VBUS_EN USH_PWR_STATE# <66> C
@ CE66
L11 K4 RE606 100K_0201_5%
<74> W W AN_DET# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_POWERSHARE_VBUS_EN <74>
1
P5 L3 USB_POW ERSHARE_EN# PTP_DIS# 1 2
<8> SHD_CS#0 SHD_CLK GPIO055/PWM2/SHD_CS# GPIO206/ADC06 USB_PW R_EN1# USB_POWERSHARE_EN# <74>
N7 L4 RE605 100K_0201_5%
<8> SHD_CLK GPIO056/PWM3/SHD_CLK GPIO207/ADC07 AUX_EN_W OW L USB_PWR_EN1# <74> W W AN_RADIO_DIS#
<38> BIA_PWM_EC N9 H3 1 2
AUX_EN_WOWL <78>
2
FPR_SCAN_INT#_EC P8 GPIO001/PWM4 GPIO210/ADC08 G2 LOM_CABLE_DETECT# RE10 100K_0201_5%
<66,74> FPR_SCAN_INT#_EC GPIO002/PWM5 GPIO211/ADC09 BC_INT#_ECE1117 LID_CL_SIO_TAB#
P9 J2 1 2
JUMP@ M9 GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 H2 USB_PW R_EN2# BC_INT#_ECE1117 <63> @ RE828 10K_0201_5%
PJP20 <38> PANEL_BKEN_EC D14 GPIO015/PWM7 GPIO213/ADC11 H1 SPI_SHARE_BOOT_SELECT 1 2
1 2 +3.3V_ALW <74> BEEP FPR_DET# C11 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K1 DCIN2_EN @ RE601 1 2 0_0201_5% RE12 10K_0201_5%
+1.8V_PRIM +1.8V_PRIM_VTR3 <74> FPR_DET# AC_DIS C14 GPIO133/PWM9 GPIO215/ADC13 L2 DCIN2_EN_R <82> PRIM_PW RGD
Boot Source Select
1 <84> AC_DIS GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 PCH_PCIE_WAKE# <11,42,59>
PAD-OPEN1x1m H10 K5 1=Use the Shared SPI pins for Boot
<66> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 TBT_RESET_N_EC <42>
1
0.1U_0201_10V6K
CE22 J9 0=Use the eSPI Flash Channel for Boot
<79> MSCLK GPIO170/TFDP_CLK/UART1_TX CV3_ON_R
@ CE68
0.1U_0201_10V6K RE362 H13 M6 RE539 1 2 100_0201_5% Warning: can not support DSW(DS3) mode for G3 sharing mode.
<79> MSDATA GPIO171/TFDP_DATA/UART1_RX/(JTAG_STRAP) GPIO222/SER_IRQ CV3_ON <66>
1
2 100K_0201_5% P6 Boot ROM will not drive GPIO020 (DSW_PWROK) high in G3 sharing mode.
GPIO223/SHD_IO0 SHD_IO0 <8> +RTC_CELL
1 CE21 E3 M7
<74> NB_MUTE# EN_INVPW R GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 SHD_IO1 <8>
0.1U_0201_10V6K C2 N6
<38> EN_INVPWR SHD_IO2 <8>
2
2
RESET_IN# F3 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 N5 VCI_IN1# 1 2
<63> RESET_IN# IMVP_VR_ON_EC GPIO024(RESETI#)/GPTP-IN2 GPIO016/GPTP-IN7/SHD_IO3/ICT3 SHD_IO3 <8>
N12 RE507 100K_0201_5%
2 Close to pin J6 <59> IMVP_VR_ON_EC P10 GPIO031/GPTP-OUT1 D5 BGPO0 1 LID_POW ER_ON# 1 2
<74> FPR_UEFI_MGMT# GPIO032/GPTP-OUT0 BGPO0 PAD~D @ T476
P12 B7 RE508 100K_0201_5%
<79> M_BIST GPIO040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <79,84> ACAV_IN VCI_IN3#
E6 1 2
VCI_OUT ALWON <83,85>
H12 A6 RE822 100K_0201_5%
<42> RTD3_SELECT GPIO121/PVT_IO0 GPIO163/VCI_IN0# VCI_IN1# POWER_SW_IN# <59,79,83> +PECI_VREF
0.1U_0201_10V6K
G12 A7 2 1
<82,84> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# LID_POW ER_ON# +1.05V_VCCST I_BATT_R
@ CE67
+3.3V_ALW E12 E4 LID_POWER_ON# <59,83> @ RE59 0_0201_5% CE3 1 2 2200P_0201_25V7K
<66> USH_DET#
1
LID_CL_SIO_TAB# GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# VCI_IN3#
0.1U_0201_10V6K
E13 E5
<59,74> LID_CL_SIO_TAB# GPIO126/PVT_IO3 GPIO000/VCI_IN3# I_SYS_R CE4 1 2 2200P_0201_25V7K
1
LOM_CABLE_DETECT# RTCRST_ON
CE25
2 1 F12
2
@ RE505 100K_0201_5% W W AN_RADIO_DIS# G13 GPIO122/BCM0_DAT/PVT_IO1 C8
USH_DET# <74> WWAN_RADIO_DIS# GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0/TRACECLK 3.3V_WWAN_EN <74> RE59 close to UE1 at least 250mils
2 1 G10
<63> BC_DAT_ECE1117
2
@ RE526 10K_0201_5% D12 GPIO046/BCM1_DAT D2 32KHZ_OUT @ CE54 1 2 10P_0201_50V8J
BCM5882_ALERT# +3.3V_ALW2 <63> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT EPRIVACY_EN
2 1 1 2
RE532 4.7K_0201_5% E1 RE802 1M_0201_5%
W W AN_DET# <74> NGFF_CONFIG_3 SYSPW R_PRES GPIO041/SYS_SHDN# +PECI_VREF PCH_RSMRST#
2 1 @ RE57 2 1 1K_0201_5% D4 H14 1 2
RE900 100K_0201_5% 1.8V K6 SYSPWR_PRES GPIO044/VREF_VTT K12 PECI_EC_R RE60 1 2 43_0201_5% RE342 100K_0201_5%
<74> SAR_ACT#_1P8 PECI_EC <14>
1
1 2 CV3_ON_R @ RE602 1 2 0_0201_5% VBUS1_ECOK N8 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT K13 M3042_PCIE#_SATA SYS_PW ROK 1 2
RE716 100K_0201_5% RE58 <82> VBUS1_ECOK_R 1.8V M4 GPIO021/LPCPD# GPIO043/SB-TSI_CLK B9 REM_DIODE1_N CE24 1 2 2200P_0201_25V7K M3042_PCIE#_SATA <10> RE56 100K_0201_5%
1 2 IMVP_VR_ON_EC 100K_0201_5% <8,79> ESPI_RESET#_1P8 M5 GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A A9 REM_DIODE1_P REM_DIODE1_N I_SYS_R 1 2
GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE1_P REM_DIODE1_N <59>
RE717 100K_0201_5% M2 B12 CE26 1 2 2200P_0201_25V7K @ RE313 10K_0201_5%
RUN_ON_EC GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_N REM_DIODE1_P <59> LCD_TST
1 2 1.8V P2 A12 1 2
REM_DIODE2_N <59>
2
RE718 100K_0201_5% <8,79> ESPI_CLK_1P8 1.8V N2 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B11 REM_DIODE3_N @ CE80 1 2 2200P_0201_25V7K REM_DIODE2_P RE20 100K_0201_5%
TBT_RESET_N_EC <8,79> ESPI_CS#_1P8 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A REM_DIODE3_P REM_DIODE3_N REM_DIODE2_P <59> EN_INVPWR
1 2 1.8V N3 A11 1 2
<8,79> ESPI_IO0_1P8 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N REM_DIODE3_P REM_DIODE3_N <59>
B @ RE95 100K_0201_5% 1.8V P3 B10 CE27 1 2 2200P_0201_25V7K RE55 100K_0201_5% B
<8,79> ESPI_IO1_1P8 1.8V N4 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P REM_DIODE4_N REM_DIODE3_P <59> SPI_SHARE_BOOT_SELECT 1
A10 2
<8,79> ESPI_IO2_1P8 1.8V P4 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP REM_DIODE4_P REM_DIODE4_N <59>
A14 @ RE18 100K_0201_5%
<8,79> ESPI_IO3_1P8 SAR_DPR1#_1P8 1.8V M3 GPIO073/LAD3/ESPI_IO3 VIN VSET_5107 REM_DIODE4_P <59>
A13 VSET_5107 <59>
<74> SAR_DPR1#_1P8 SAR_DPR2#_1P8 1.8V L5 GPIO067/CLKRUN# VSET B14
<74> SAR_DPR2#_1P8 RESET_OUT# GPIO100/nEC_SCI VCP I_ADP <84>
@ RE548 1 2 0_0201_5% B2 G9 THERMTRIP2# THERMTRIP2# <59>
<11> SYS_PWROK @ RE600 1 2 0_0201_5% DCIN1_EN L13 GPIO106/PWROK GPIO103/THERMTRIP2# B13 THERMTRIP1#
+3.3V_ALW <82> DCIN1_EN_R GPIO107/nSMI THERMTRIP1# D13 PROCHOT#_R1 1 2
MEC_XTAL1 A4 GPIO160/PWM11/PROCHOT# RE288 100_0201_5% PROCHOT# <14,44,84,88> +3.3V_RUN
MEC_XTAL2_R A2 XTAL1 C3
XTAL2 GPIO062(RESETO#)
1
E14 PRIM_PW RGD @ RE361 1 2 0_0201_5% RUNPWROK 1 2

GPIO076(PRIM_PWRGD) SPI_SHARE_BOOT_SELECT 1.05V_PRIM_PWRGD <87>
RE63 F13 RE67 10K_0201_5%
GPIO074(BSS_STRAP) J14 PCH_RSMRST# +3.3V_ALW
VSS_ANALOG
100K_0201_5% PCH_RSMRST# <8,63,79>
GPIO075(RSMRST#) F14 VBUS2_ECOK 1 2
GPIO117 J10 3.3V_TS_EN@ RE603 VBUS2_ECOK_R <82> VGA_IDENTIFY 1 2
VSS_ADC
0_0201_5%
3.3V_TS_EN <38>
2
VR_CAP
GPIO240 J13 RE84 100K_0201_5%

GPIO116 ISH_TABLE_MODE# <9>
VSS1
VSS2
VSS3
VSS
JTAG_RST#
VGA_IDENTIFY
MEC5107KD4LJTR_W FBGA176-NH-X QE15 CIS no symbol(SB00001SN00) Discrete 0
G6
H6
J7
K3
+VR_CAP G1
F8
F7
1
1U_0201_6.3V6M
UMA 1
1
+RTC_CELL_PCH +RTC_CELL
@SHORT PADS~D
JTAG1 @
1 @
RE65 QE15
CE30
100_0201_5% PJA3415AE_SOT-23-3
1U_0201_6.3V6M
1
2 1 3
S
2
CE31
+RTC_CELL_PCH +RTC_CELL
1U_0201_6.3V6M
2
1
2
1
G
2
2
RE546 1 2
CE63
10K_0201_5% @RE551 0_0402_5%
2 DE2 RE94
2
2 1 1 2
75_0201_5% PCH_RTCRST# <11,79>
X11 New diagnostic circuit (V-Tree) for Service
1
+3.3V_ALW D
RB751S-40_SOD523-2
RTCRST_ON 2 QE12
For EMI request
1
D
RE543 G NX7002BKW _SOT323-3
1
1
MEC_XTAL2_R ESPI_CLK_1P8 QE17 2 RTCRST_ON_POW ER_R1 1 2 RTCRST_ON_POW ER_R 1 2 RTCRST_ON_POW ER
S
3
RE68 NX7002BKW _SOT323-3 G @ RE565 0_0201_5% RE93
100K_0201_5% S 1M_0201_5% 100K_0201_5%
3
1
A @EMI@ A
1
1
22P_0201_50V8J
RE350 1 1
2
2
1
@ RE290 33_0201_5% QE2 RE541 @

32 KHz Clock
CE65
S1
0_0201_5% 2 100K_0201_5% CE64
<17,59,78,87> RUN_ON RUN_ON# RUN_PWRGD@ RE102 1 0.1U_0201_25V6K
G1
D1 6 2 0_0201_5%
2
4 2 2
2
2
RUN_ON# 5 S2
@ RE103 1 2 0_0201_5%
G2 <87> 2.5V_MEM_PW RGD
YE1 1 D2
MEC_XTAL1 1 2 MEC_XTAL2 @EMI@ PJX138K_SOT-563-6 @ RE104 1 2 0_0201_5% RUNPWROK
3
<86> 1.2V_MEM_PW RGD

CE57
32.768KHZ_9PF_X1A000141000200 2
33P_0201_50V8J
<87> 0.95VS_VCCIO_PW RGD
@ RE105 1 2 0_0201_5% DELL CONFIDENTIAL/PROPRIETARY
1 1 RUN_PWRGD
CE28 CE29 Compal Electronics, Inc.
10P_0201_50V8J 10P_0201_50V8J PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2 2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EC MEC5107
5 4 3 2 1
5 4 3 2 1
For Riverside UMA

+RTC_CELL
+3.3V_ALW +RTC_CELL
+3.3V_ALW
1
@ CE10
1
RE31
RE25 RE88 100K_0201_5% 1 2
PCIE_WAKE# <42,52,68,74>
100K_0201_5% 2M_0201_5%
2
G
0.1U_0201_10V6K
2
2
2
LID_CL_SIO# 3 1 LID_CL#_R 2 1 1 2
<58,74> LID_CL_SIO# LID_CL# <74> <58,79,83> POWER_SW_IN# POWER_SW#_MB <74,77,79>
RE26 10_0402_5% RE33 1K_0201_5% 1 2 1 2
D
<58> PCIE_WAKE#_R PCH_PCIE_WAKE# <11,42,58>
.047U_0402_16V7K
0.22U_0402_16V7K
1 @ RE275 0_0201_5% @ RE274 0_0201_5%
QE10
1
D D
CE12
NX7002BKW _SOT323-3
CE8
Stuff RE275 and no stuff RE274 keep E5 design
1 2 2 Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
2
@ RE89 0_0201_5%
+3.3V_ALW
@ CE53
1 2
Fixed 360 casue auto power on 0.1U_0201_10V6K

UE4
+3.3V_ALW
5
+RTC_CELL 1 6
IMVP_VR_ON_EC 1 NC1 VCC
P
<58> IMVP_VR_ON_EC B IMVP_VR_ON
4 2 5
O A NC2
1
SIO_SLP_S3# 2
<11,17,42,59,79> SIO_SLP_S3# A
G
RE904 3 4
1 2 LID_CL_SIO_TAB#_D1 2M_0201_5% UE3 GND Y VCCST_PWRGD <11,79>
3
MC74VHC1G08EDFT2G_SC70-5 74AUP1G07FZ4-7_X2-DFN1410-6
DZ109
2
RB751S-40_SOD523-2
1 2 LID_CL#_D IMVP_VR_ON <88,96>

@ CE400 1U_0201_6.3V6M
1 2 1 2
PJX138K_SOT563-6
PJX138K_SOT563-6
6
3
RE903 49.9K_0201_1%
DZ110
QE32A
QE32B
RB751S-40_SOD523-2
1 2 LID_CL#_QE32 2 5
<58,74> LID_CL_SIO_TAB#
RE902 10M_0201_1% +3.3V_ALW
RF Request
@ CE52 +3.3V_ALW
1 1 2
CE401
4
2.2U_0402_10V6M 0.1U_0201_10V6K 1
5
2 RF@CE61
1 68P_0201_50V8J
P
C B 2 C
4
RUN_ON_EC O RUN_ON <17,58,78,87>
2
<58> RUN_ON_EC A
G
UE5
3
+3.3V_ALW +3.3V_ALW
1
RE343 RE79
S5 LID OPEN POWER ON 33K_0201_5% 4.3K_0402_1%
2
<58> TYPEC_ID <58> BOARD_ID
1 1
+RTC_CELL
CE62 CE40
4700P_0201_6.3V7K 4700P_0201_6.3V7K
1
2 2
RE836
1 2 2M_0201_5%
RE343 CE62 REV RE79 CE40 REV
DZ106
2
RB751S-40_SOD523-2 Single Port ACE w/o TR

LID_CL#_D
240K 4700p 240K 4700p X00
1 2
CE71 1U_0201_6.3V6M LID_POWER_ON# <58,83> 130K 4700p Single Port ACE w/TR 130K 4700p X01
62K 4700p Dual Port ACE w/o TR 62K 4700p X02
1 2 1 2
PJX138K_SOT563-6
PJX138K_SOT563-6
Dual Port ACE w/TR

* 33K 4700p 33K 4700p X03
6
RE835 220K_0201_5%
DZ107 Dual Port ACE (w/TR +w/o TR)
8.2K 4700p 8.2K 4700p reserved
QE18A
QE18B
RB751S-40_SOD523-2 1
LID_CL#_R 1 2 LID_CL#_QE18 2 5
RE837 10M_0201_1%
1
CE402 CE72 4.3K 4700p * 4.3K 4700p A00
1U_0402_25V6K
1
2
2
0.22U_0201_6.3V6K
2K 4700p 2K 4700p
CE73
B
1K 4700p 1K 4700p B
1
1U_0402_25V6K
2
TYPEC_ID rise time is measured from 0%~63.2%. BOARD_ID rise time is measured from 0%~63.2%.
VSET_5107
VSET_5107 <58>
1
1.58K_0402_1%
1
RE77
CE38
0.1U_0201_25V6K
2
2
Thermal diode mapping Rest=1.58K , Tp=96 degree
Place on PL701 charger choke Rest=1.33K , Tp=93 degree
5107 Channel Location Place CE81 close to the QE30 as possible
Place under CPU
Place CE35 close to the QE3 as possible REM_DIODE3_P <58>
DP1/DN1 CPU (QE3)
REM_DIODE1_P <58>
100P_0201_50V8J
100P_0201_50V8J
DP2/DN2 2280 SSD (QE5) 1 1

1
@ CE35
@ CE81
C
1
C 2
DN2a/DP2a DDR (QE7) 2 B
2
2
B
E @ QE30
3
E QE3 LMBT3904W T1G_SC70-3

Charger Choke
3
DP3/DN3 LMBT3904W T1G_SC70-3

(QE30)
REM_DIODE1_N <58> REM_DIODE3_N <58>
DP4/DN4 CPU VR (QE6) RE69
DP2/DN2 for M2 2280 on QE5, place QE5 close 1 2
to JNGFF3 and CE37 close to QE5 +0.95VS_VCCIO +3.3V_ALW THERMTRIP2# <58>
A
DP4/DN4 for Skin on SIO_SLP_S3# <11,17,42,59,79> 8.2K_0201_5% 1 A
LMBT3904WT1G_SC70-3
QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
2
CE36
G
to DDR and CE46 close to QE7

1
Vcore VR choke. C 0.1U_0201_10V6K

2
QE4
1 3 1 2 2
REM_DIODE4_P <58> REM_DIODE2_P <58> B
RE70 2.2K_0201_5%
D
+1.05V_VCCST E
LMBT3904WT1G_SC70-3
3
100P_0201_50V8J
@ QE11
100P_0201_50V8J
100P_0201_50V8J
1 NX7002BKW _SOT323-3
1
1
@ CE39
C E C 1 2
1 1
@ CE46
@ CE37
2 2 2
B
@ RE90 0_0201_5%
B B
2 <14> H_THERMTRIP#
E C E
QE6 QE7 QE5
3
LMBT3904W T1G_SC70-3 2 2 LMBT3904W T1G_SC70-3

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5107 support
REM_DIODE4_N <58> REM_DIODE2_N <58> BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
Secure & Reset IC
5 4 3 2 1
5 4 3 2 1
1K
1K
+3.3V_ALW_PCH 14 Accelerometer
CH14 SML0_SMBCLK 13 and
T2 TR Gyro
SML 0 CF15 SML0_SMBDATA For vPro docking
T1
2.2K
2.2K
+3.3V_RUN
D CH20 ISH_I2C0_SCL D
1 1 Magnetometer
ISH_I2C0 ISH_I2C0_SDA Accelerometer
CK22 4 4 and
2.2K E-Compass
PCH
2.2K
+1.8V_RUN
Place on M/B Place on Sensor/B
CJ22 ISH_I2C1_SCL
6
ISH_I2C1 CH22 ISH_I2C1_SDA JIR1 Magnetometer/E-Compass Only 360 SKU
5
ALS Sensor
SML 1
CM15 CN15
1K
SML1_SMBDATA
+3.3V_ALW_PCH P Sensor
SML1_SMBCLK 1K
C C
C10 E8 2.2K
+3.3V_TP Place on Camera
03 03 2.2K
DAT_TP_SIO_I2C_CLK
ALS/P-Sensor Only On 3mm/6mm IR Camera
02 C9 5
02 E9 CLK_TP_SIO_I2C_DAT 7 TP
2.2K
+3.3V_ALW IO/B, Trough Beam CONN

2.2K
Place on IO/B, Only Support WWAN SKU
B4 USH_EXPANDER_SMBCLK
2.2K
01 16
A3 USH_EXPANDER_SMBDAT USH/B
01 15 +1.8V_RUN
2.2K
2.2K
00 B3 PJX138K
00 C4
2.2K PJX138K
KBC +3.3V_ALW
C6 UPD1_SMBCLK 27 PD &
04
C5 UPD1_SMBDAT 28 Dock FW reflash
B 04 B
A1
SAR Sensor
B1
MEC 5107
05 B5
05 A5
06 P11
06 P13
07 K7
07 L1
08 C7
08 B8
0 ohm 21
2.2K
09 F7
0 ohm 22 Charger
09 B6
+3.3V_ALW
2.2K
A
PBAT_CHARGER_SMBCLK
100 ohm A
10 M1 7
BATTERY
10 N1 PBAT_CHARGER_SMBDAT 100 ohm 6 CONN
Security Classification Compal Secret Data
Title
Issued Date 2017/01/01 Deciphered Date 2018/01/01
SMbus Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-J261p
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
LEDs (Controller)
5 4 3 2 1
5 4 3 2 1
RF Request
Touch Pad +3.3V_TP
KB_DET#
RF@ CZ84
1 2
68P_0201_50V8J
BC_INT#_ECE1117 1 2
1 @RF@ CZ85 68P_0201_50V8J
+3.3V_RUN +3.3V_TP RF@
CZ83 BC_DAT_ECE1117 1 2
JUMP@ 68P_0201_50V8J @RF@ CZ86 68P_0201_50V8J
PJP35 2
1 2 BC_CLK_ECE1117 1 2
D @RF@ CZ87 68P_0201_50V8J D
PAD-OPEN1x1m
2 1 I2C1_SCL_TP_R
<58> DAT_TP_SIO_I2C_CLK
@ RZ347 0_0201_5%
2 1 I2C1_SDA_TP_R
<58> CLK_TP_SIO_I2C_DAT
@ RZ346 0_0201_5%
10P_0201_50V8J
10P_0201_50V8J
1 1 I2C From EC
CZ80
CZ81
2 2
Keyboard 1
CONN@
JKBTP1
+3.3V_TP 1
2
<66> NFC_ACTIVITY_STATUS# KB_DET# 3 2
<12> KB_DET# 4 3
<58> PTP_DIS# I2C1_SCL_TP_R 4
5
6 5
+3.3V_TP I2C1_SDA_TP_R 7 6
+3.3V_TP 8 7
<14,58> TOUCHPAD_INTR# 9 8
+5V_RUN KSI_03_R 9
10
C 11 10 +3.3V_TP +3.3V_ALW +5V_RUN C
+3.3V_ALW 11
1
BC_DAT_ECE1117
10K_0201_5%
10K_0201_5%
@ @ 12
<58> BC_DAT_ECE1117 12
1
1
2.2K_0201_5% BC_CLK_ECE1117
2.2K_0201_5%
RZ116
RZ117
13
<58> BC_CLK_ECE1117 13
14
BC_INT#_ECE1117 14
RZ20
RZ21
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
15 1 1 1
<58> BC_INT#_ECE1117 15
@
16
2
KSO_02_R 16
CZ90
CZ91
CZ92
17
2
18 17
1 2 I2C1_SDA_TP_R EC_KSI_03_R 19 18 2 2 2
<9> I2C1_SDA_TP EC_KSO_02_R 19
@ RZ26 0_0201_5% 20
1 2 I2C1_SCL_TP_R 20
<9> I2C1_SCL_TP
@ RZ29 0_0201_5%
+3.3V_TP 21
I2C From CPU 22 GND1 Place close to JKBTP1
GND2
1
RZ1499 HRS_TF31-20S-0P5SH-800
100K_0201_1%
Link HRS_TF31-20S-0P5SH-800 done 0313
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
2
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues NFC_ACTIVITY_STATUS#
EC_KSI_03_R @ RCH99 1 2 0_0201_5% KSI_03_R
B EC_KSO_02_R @ RCH95 1 2 0_0201_5% KSO_02_R B
RSMRST circuit
1 2 PROM_BIOS_R <8>
<58> RESET_IN#
RZ200 1K_0201_5%
1
@ RZ401 +3.3V_ALW
1K_0201_5% @ CZ82
1 2
2
0.1U_0201_10V6K
5
1 2 PROM_BIOS 1
P
<8,58,79> PCH_RSMRST# B
@ RZ400 0_0201_5% 4 PCH_RSMRST#_AND <11,79>
2 O
<11,85> ALW_PWRGD_3V_5V A
G
3
UZ41
A A
Keyboard
5 4 3 2 1
5 4 3 2 1
Battery LED
1 2 BATT_WHITE#
<58> BAT2_LED#
RZ361 1K_0402_1%
1 2 BATT_YELLOW#
<58> BAT1_LED#
RZ28 1K_0402_1%
D D
LED board CONN

HRS_TF31-4S-0P5SH-800
6
5 GND2
GND1
+5V_ALW
4
BATT_YELLOW # 3 4
<79> BATT_YELLOW# BATT_W HITE# 3
2
2
0.1U_0201_10V6K
1 1
1
ESD@ CZ380
C C
JLED1
2 CONN@
B B
A A
LED & LID
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
Reserve for KB/TP/LED/LID
5 4 3 2 1
5 4 3 2 1
For ST TPM <74> FPR_RST#

2
DZ17
1 FPR_RST#_USH
+3.3V_ALW
1 2 USH_EXPANDER_SMBCLK
RZ8 2.2K_0201_5%
RB751S-40_SOD523-2 1 2 USH_EXPANDER_SMBDAT
RZ9 2.2K_0201_5%
@ RZ1411 1 2 0_0603_5%
+3.3V_ALW_PCH 1 2 USH_PWR_STATE#
DZ17 Co-lay with RZ1411 RZ10 100K_0201_5%
1 2 TPM_PIRQ# 1 2
+3.3V_ALW _PCH +3.3V_VPS_UZ12 <74> USB20_P9_FP USB20_P9 <10>
RZ69 10K_0201_5% @ RZ1408 1 2 0_0402_5% @ RZ1389 0_0201_5%
+1.8V_PRIM
<74> USB20_N9_FP
@ RZ1388
1 2
0_0201_5%
USB20_N9
USB20_P9_USH
<10> USH CONN
1 2
@ RZ351 0_0201_5%
D 1 2 USB20_N9_USH CONN@ D
+3.3V_RUN
1 2 @ RZ350 0_0201_5% JUSH1
1 2 TPM_PIRQ# @ RZ362 10K_0201_5% 28
@ RZ1600 10K_0201_5% 27 GND2
1 2 TPM_GPIO0 GND1
<9,11,17,79,87> SIO_SLP_S0#
@ RZ112 0_0201_5% 26
<9> SC_CAGE_DET# FPR_RST#_USH 25 26
24 25
<58> CV3_ON USB20_N9_USH 24
23
USB20_P9_USH 22 23
UZ12 21 22
20 21
22 +3.3V_VPS_UZ12 Fixed USBP/N for X11 Rialto/Riverside <10> USB20_P8
19 20
VPS 19
8
NiC_5 USH/B, Don't change!!! <10> USB20_N8
18
18
0.1U_0201_10V6K
10U_0402_10V6M
1 17
NiC_1 16 17
1 1 <58,74> USH_EXPANDER_SMBCLK 16
31 15
NiC_21 <58,74> USH_EXPANDER_SMBDAT 15
CZ54
CZ55
16 14
20 NiC_13 27 <58> BCM5882_ALERT# 13 14
<8> PCH_SPI_CS#2 SPI_CS# NiC_17 2 2 13
18 26 12
<9> TPM_PIRQ# SPI_PIRQ# NiC_16 25 11 12
PCH_SPI_D0_2_R NiC_15 +3.3V_ALW 11
RZ59 1 2 33_0201_1% 21 30 10
<8> PCH_SPI_D0 PCH_SPI_D1_2_R MOSI NiC_20 10
RZ58 1 2 33_0201_1% 24 29 +5V_ALW
9
<8> PCH_SPI_D1 MISO NiC_19 28 8 9
TPM_GPIO0 NiC_18 +3.3V_RUN 8
6 14 7
GPIO NiC_11 +5V_RUN FPR_SCAN_INT#_EC_R 7
15 place CZ54,CZ55 as close as UZ12.22 @ RZ114 1 2 0_0201_5% 6
NiC_12 <58,74> FPR_SCAN_INT#_EC USH_PW R_STATE# 6
13 5
NiC_10 12 <58> USH_PWR_STATE# 2 1 CONTACTLESS_DET#_R 4 5
PCH_SPI_CLK_2_R NiC_9 <12> CONTACTLESS_DET# 4
RZ60 1 2 33_0201_1% 19 11 DZ8 RB751S-40_SOD523-2 3
<8> PCH_SPI_CLK SPI_CLK NiC_8 3
10 2
NiC_7 <63> NFC_ACTIVITY_STATUS# 2
5 1
Topology R4 loaction NiC_4 4 <58> USH_DET# 1
7 NiC_3 3 HRS_TF31C-26S-0P5SH-800
PP NiC_2
32
PCH_SPI_CLK_2_R NiC_22 23 Link HRS_TF31C-26S-0P5SH-800 done 0313
17 NiC_14 9
<11> PLTRST_TPM# SPI_RST# NC_6 2
GND0
1
@EMI@ 33
RZ63 THPAD
33_0201_5%
ST33HTPH2X32AHD4_VQFN32_5X5-X
C C
2
1
@EMI@
CZ56
0.1U_0201_25V6K
2
Close to JUSH1 RF Request

+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW +5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
RF Request
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
68P_0201_50V8J
RF@ CZ69
68P_0201_50V8J
RF@ CZ71
68P_0201_50V8J
RF@ CZ72
68P_0201_50V8J
RF@ CZ73
USH_EXPANDER_SMBCLK 1 1 1 1 1 1 1 1
@
1 2
CZ64
CZ66
CZ67
CZ68
@RF@ CZ62 68P_0201_50V8J
USH_EXPANDER_SMBDAT 1 2 2 2 2 2 2 2 2 2
@RF@ CZ63 68P_0201_50V8J
Accelerometer
B B
+3.3V_RUN
+3.3V_RUN
@ RZ150
RZ155
1
1
2 10K_0201_5%
2 10K_0201_5%
ACC2_ADD_SEL
ACC2_ADD_SEL
Sensor/B +3.3V_RUN
1
FZ6
2 +3.3V_RUN_FZ6
JSEN1 +3.3V_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
0.5A_65V_T0603FF0500TM 1
360_SENSOR_DET# 2 1 ISH_ACC1_INT 1 2
1 1 <9,58> 360_SENSOR_DET# ISH_ACC1_INT 2
3 RZ505 10K_0201_5%
<9> ISH_ACC1_INT 3 ISH_ACC2_INT
CZ199
CZ201
4 1 2
ISH_I2C0_SDA 5 4 RZ506 10K_0201_5%
2 2 <9,66> ISH_I2C0_SDA ISH_I2C0_SCL 5 360_SENSOR_DET# 1
UZ1 6 2
<9,66> ISH_I2C0_SCL 6 RZ1495 100K_0201_5%
LNG2DM
10 5 7
9 VDD_IO RES 8 GND1
VDD GND2
2
ISH_ACC2_INT
12
ACC2_ADD_SEL INT 1 ISH_ACC2_INT <9>
ESD@ DZ108
3 11 ACES 50208-00601-P01
@ RZ152 1 2 0_0201_5% ISH_I2C0_SDA_R 4 SDO/SA0 INT 2
<9,66> ISH_I2C0_SDA ISH_I2C0_SCL_R SDA/SDI/SDO CONN@
@ RZ153 1 2 0_0201_5% 1 6
<9,66> ISH_I2C0_SCL SCL/SPC GND_1 7
RZ154 1 2 100K_0201_5% 2 GND_2 8
+3.3V_RUN CS GND_3 EMI Request
1
LNG2DMTR_LGA12_2X2-X +3.3V_RUN
0.1U_0201_25V6K
EMI@ CZ337
1
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USH & TPM
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
HDD/ODD/FFS Connector
5 4 3 2 1
5 4 3 2 1
Add Power Decoupling for support Intel Teton Glacier

RF Request
Place close JNGFF3 pin 12,14,16,18 Place close JNGFF3 pin 2,4 Place close JNGFF3 pin 70,72,74
+3.3V_HDD_M2
+3.3V_HDD_M2 +3.3V_HDD_M2 +3.3V_HDD_M2
68P_0201_50V8J
@RF@ CN60
27P_0201_25V8
RF@ CN87
100P_0201_50V8J
RF@ CN78
0.01U_0201_16V7
0.1U_0201_10V6K
22U_0402_6.3V6M
0.01U_0201_16V7
0.01U_0201_16V7
0.1U_0201_10V6K
22U_0402_6.3V6M
0.01U_0201_16V7
0.01U_0201_16V7
0.1U_0201_10V6K
22U_0402_6.3V6M
1 1 1
1 1 1 1 1 1 1 1 1 1 1
D D
CN79
CN61
CN77
CN80
CN81
CN86
CN64
CN84
CN82
CN62
CN63
2 2 2
2 2 2 2 2 2 2 2 2 2 2
Place near JNGFF3
2280 SSD
NGFF slot C Key M
JUMP@ PJP31
+3.3V_HDD_M2 2 1
JNGFF3 CONN@ PAD-OPEN1x3m

1 2 2.8A 1 2 +3.3V_RUN
3 GND1 3.3VAUX1 4 @ RN130 0.01_0805_1%
5 GND2 3.3VAUX2 6
<10> PCIE_PRX_DTX_N13 7 PERn3 N/C1 8 SSD_SCP#_R 1 2
<10> PCIE_PRX_DTX_P13 PERp3 N/C2 NVME_LED# @ RN129 SSD_SCP# <58>
9 10 0_0201_5% 1 @
PCIE_PTX_C_DRX_N13 GND3 DAS/DSS# PAD~D T459
CN65 1 2 0.22U_0201_10V6K 11 12
<10> PCIE_PTX_DRX_N13 PCIE_PTX_C_DRX_P13 PETn3 3.3VAUX3
CN66 1 2 0.22U_0201_10V6K 13 14
<10> PCIE_PTX_DRX_P13 PETp3 3.3VAUX4
15 16
17 GND4 3.3VAUX5 18
C <10> PCIE_PRX_DTX_N14 19 PERn2 3.3VAUX6 20 C
<10> PCIE_PRX_DTX_P14 21 PERp2 N/C3 22
CN67 1 2 0.22U_0201_10V6K PCIE_PTX_C_DRX_N14 23 GND5 N/C4 24
<10> PCIE_PTX_DRX_N14 PCIE_PTX_C_DRX_P14 PETn2 N/C5
CN68 1 2 0.22U_0201_10V6K 25 26
<10> PCIE_PTX_DRX_P14 PETp2 N/C6
27 28
29 GND6 N/C7 30
<10> PCIE_PRX_DTX_N15 31 PERn1 N/C8 32
<10> PCIE_PRX_DTX_P15 33 PERp1 N/C9 34
<10> PCIE_PTX_DRX_N15 PCIE_PTX_C_DRX_P15 PETn1 N/C11
CN70 1 2 0.22U_0201_10V6K 37 38
<10> PCIE_PTX_DRX_P15 PETp1 DEVSLP M2280_DEVSLP <10>
39 40
41 GND8 N/C12 42
<10> PCIE_PRX_DTX_P16 43 PERn0/SATA B+ N/C13 44
<10> PCIE_PRX_DTX_N16 45 PERp0/SATA B- N/C14 46
<10> PCIE_PTX_DRX_N16 PCIE_PTX_C_DRX_P16 PETn0/SATA A- N/C16
CN72 1 2 0.22U_0201_10V6K 49 50
<10> PCIE_PTX_DRX_P16 PETp0/SATA A+ PERST# PCH_PLTRST#_AND <11,38,42,52,70,74>
+3.3V_HDD_M2 51 52
GND10 CLKREQ# PCIE_W AKE# CLKREQ_PCIE#2 <11>
53 54
<11> CLK_PCIE_N2 REFCLKn PEWake# PCIE_WAKE# <42,52,59,74>
55 56
<11> CLK_PCIE_P2 REFCLKp N/C17
1 2 M2280_DEVSLP 57 58
@ RN37 10K_0201_5% GND11 N/C18
67 68 SUSCLK_R 1 2
if signal is PCIE GEN3/SATA GEN3 maybe change C value N/C19 SUSCLK SUSCLK <11,52>
or no need for DG0.9 SATA EXPRESS HDD 69 70 @ RN99 0_0201_5%
<10> M2280_PCIE_SATA# 71 PEDET 3.3VAUX7 72
73 GND12 3.3VAUX8 74
75 GND13 3.3VAUX9
GND14
77 76
B MTG77 MTG76 B
79 78
NPTH2 MTG78
LOTES_APCI0146-P008A
A A
M2 2280 Socket
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
eMMC / UFS
5 4 3 2 1
5 4 3 2 1
RF Request
+3.3V_RUN
1
JUMP@
PJP14
2
+3.3V_MMI_IN
For PCIE Interface
+3.3V_MMI_AUX +3.3V_MMI_IN PAD-OPEN1x2m
+3.3V_MMI_IN +3.3V_MMI_AUX
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/off 3V3AUX)
2 1
D @ RR20 0_0402_5% D
+3.3V_MMI_AUX +3.3V_MMI_IN
12P_0201_50V8J
@RF@ CR27
82P_0201_50V8J
@RF@ CR28
12P_0201_50V8J
@RF@ CR25
82P_0201_50V8J
@RF@ CR26
1 1 1 1
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_6.3V6M
+3.3V_MMI_AUX
2 2 2 2
1 1 1 1
CR4
CR3
1 MEDIACARD_IRQ#
CR1
CR2
2 7/18 Vender suggest.
RR19 10K_0201_5%
2 2 2 2
27
11
UR1
EMI Request
3V3aux
3V3_IN
1 12 +3.3V_RUN_CARD
+3.3V_RUN <11,38,42,52,68,74> PCH_PLTRST#_AND PERST# CARD_3V3
2 18 1 2
<11> CLKREQ_PCIE#4 CLK_REQ# DV33_18 CR22 1U_0201_6.3V6M
0.1U_0201_25V6K
EMI@ CR29
5
<11> CLK_PCIE_P4 REFCLKP SD/MMCDAT1/RCLK-_R
1 6 15 SD/MMCDAT1/RCLK- 1 2
<11> CLK_PCIE_N4 REFCLKN SP1 SD/MMCDAT0/RCLK+_R
16 SD/MMCDAT0/RCLK+ @ RR9 1 2 0_0201_5%
C CR11 1 2 0.1U_0201_25V6K PCIE_PTX_C_DRX_P9 3 RTS5242 SP2 17 SD/MMCCLK @ RR10 1 2 0_0201_5% SD/MMCCLK_R C
<10> PCIE_PTX_DRX_P9 PCIE_PTX_C_DRX_N9 HSIP SP3 SD/MMCCMD_R
@EMI@ CR21
CR12 1 2 0.1U_0201_25V6K 4 19 SD/MMCCMD @EMI@ RR5 1 2 0_0201_5%
2 <10> PCIE_PTX_DRX_N9 PCIE_PRX_C_DTX_P9 HSIN SP4 SD/MMCDAT3_R
5P_0402_50V8C
CR13 1 2 0.1U_0201_25V6K 7 20 SD/MMCDAT3 @ RR6 1 2 0_0201_5%
<10> PCIE_PRX_DTX_P9 CR14 1 2 0.1U_0201_25V6K PCIE_PRX_C_DTX_N9 8 HSOP SP5 21 SD/MMCDAT2 @ RR7 1 2 0_0201_5% SD/MMCDAT2_R
<10> PCIE_PRX_DTX_N9 HSON SP6
1
29 SDWP @ RR8 0_0201_5%
SP7
32
2
<8> MEDIACARD_IRQ# 31 WAKE#
SD/MMCCD# 30 MS_INS#
+1.2V_LDO SD_CD#
7/18 Vender suggest
SD_UHS2_D1P
SD_LN1_P
22 EMI depop location
23 SD_UHS2_D1N
10 SD_LN1_M
14 AV12 26 SD_UHS2_D0P
DV12S SD_LN0_P 25 SD_UHS2_D0N
SD_LN0_M
4.7U_0402_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K +1.8V_RUN_CARD 13
SD_VDD2 24 +SDREG2 CR15 1 2
1 1 1
E-PAD
+RREF 9 SDREG2 28 1U_0201_6.3V6M
CR5
CR6
CR7
RREF GPIO SD_GPIO 2 1 +3.3V_MMI_AUX
100K_0201_5% RR3
2 2 2 RTS5242-GR_QFN32_4X4-X
33
1
RR4 JSD1 CONN@
6.2K_0402_1% SD/MMCDAT2_R 1
SD/MMCDAT3_R 2 DAT2
SD/MMCCMD_R 3 CD/DAT3
2
4 CMD
+3.3V_RUN_CARD SD/MMCCLK_R VDD1
5
6 CLK
B SD/MMCDAT0/RCLK+_R 7 VSS1 B
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
SD/MMCCD# 9 DAT1/RCLK-
CD
+1.8V_RUN_CARD 15
16 VDD2
17 SWIO 24
SD_UHS2_D0P 18 VSS2 NPTH1 25
SD_UHS2_D0N 19 D0+ NPTH2
20 D0- 10
QR1 SD_UHS2_D1N 21 VSS3 GND1 11
NX7002BKW _SOT323-3 SD_UHS2_D1P 22 D1- GND2 12
+3.3V_RUN_CARD +1.8V_RUN_CARD 23 D1+ GND3 13
HOST_SD_W P# SDW P STATUS SDWP 1 3 VSS4 GND4 14
D
GND5
T-SOL_158-1090902601
High Low Write Enable
4.7U_0402_10V6M
4.7U_0402_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
G
2
2 1 2 1
CR17
CR19
<12> HOST_SD_WP#
CR18
CR20
Low High Write Protect(FW LOCK)
1 2 1 2
CR17,CR18 near JSD1.4 CR19,CR20 near JSD1.14

A A
Card Reader RTS5242
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
JUSB1+PS
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
JUSB2
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
USB2/USB3 DB
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +AUD_STB
JIO1 CONN@
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
D 1 2 D
1 2
@RF@ CZ307
RF@ CZ305
27P_0201_25V8
RF@ CZ306
@RF@ CZ311
RF@ CZ313
27P_0201_25V8
RF@ CZ312
A1 A14
B1 A1 A14 B14
1 1 1 1 1 1 <58> SYSTEM_ID B1 B14 PCIE_PTX_DRX_N12 <10>
BREATH_LED#_Q C1 C14
C1 C14 PCIE_PTX_DRX_P12 <10>
PD# D1 D14
AUD_PC_BEEP E1 D1 D14 E14
2 2 2 2 2 2 F1 E1 E14 F14 PCIE_PRX_DTX_P12 <10>
<12> SMART_SPK_DET0# G1 F1 F14 G14 PCIE_PRX_DTX_N12 <10>
<9> SMART_SPK_DET1# LID_CL# H1 G1 G14 H14
<59> LID_CL# LID_CL_SIO_TAB# H1 H14 CLK_PCIE_N0 <11>
J1 J14 ANT_CONFIG Antenna Configuration
<58,59> LID_CL_SIO_TAB# J1 J14 CLK_PCIE_P0 <11> RZ1450
K1 K14
+3.3V_RUN +1.8V_RUN <58> FPR_SSO_EN# K1 K14 W W AN_ANT_CONFIG
L1 L14 1 2
<58,66> FPR_SCAN_INT#_EC L1 L14
3 4 RZ1450 470_0201_1% Pop 4x4 Antenna
A2 3 4 A13
<59,77,79>
POWER_SW#_MB A2 A13
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J B2 B13 Depop 2x2 Antenna

<58>
FPR_UEFI_MGMT# B2 B13 USB3_PTX_DRX_P4 <10>
@RF@ CZ308
RF@ CZ309
27P_0201_25V8
RF@ CZ310
@RF@ CZ314
RF@ CZ316
27P_0201_25V8
RF@ CZ315
C2 C13
<66> FPR_RST# C2 C13 USB3_PTX_DRX_N4 <10>
1 1 1 1 1 1 D2 D13
<58> FPR_LOW_PWR_MODE# D2 D13
E2 E13 @ QZ7
<58> FPR_DET# E2 E13 USB20_P7 <10>
F2 F13 NX7002BKW _SOT323-3
<58> USB_POWERSHARE_VBUS_EN F2 F13 USB20_N7 <10>
G2 G13
2 2 2 2 2 2 <58> USB_POWERSHARE_EN# G2 G13 BREATH_LED#_Q
D
H2 H13 3 1
<10> USB_OC0# H2 H13 USB3_PRX_DTX_N4 <10> <58> BREATH_LED#
J2 J13
<58> USB_PWR_EN1# J2 J13 USB3_PRX_DTX_P4 <10> +3.3V_ALW
K2 K13
<58> FPR_PWR_EN# K2 K13
L2 L13 @ CZ93
G
SAR_DPR1#_1P8 <58>
2
<10> USB_OC1# 5 L2 L13 6 1 2
+5V_ALW +5V_RUN +3.3V_ALW A3 5 6 A12
+3.3V_RUN A3 A12 W W AN_COEX1 <52>
B3 B12 0.1U_0201_10V6K
+AUD_STB B3 B12 W W AN_COEX2 <52>
C3 C12
C3 C12 W W AN_COEX3 <52>
5
+1.8V_RUN
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
D3 D12
D3 D12 PCIE_W AKE# <42,52,59,68>
@RF@ CZ317
RF@ CZ319
27P_0201_25V8
RF@ CZ318
@RF@ CZ320
RF@ CZ322
27P_0201_25V8
RF@ CZ321
C E3 E12 1 C
P
E3 E12 CLKREQ_PCIE#0 <11> <58> LED_MASK# B MASK_BASE_LEDS#
1 1 1 1 1 1 F3 F12 4
+5V_RUN F3 F12 SAR_DPR2#_1P8 <58> O
G3 G12 2
G3 G12 ISH_I2C2_SDA <9> <58,59> LID_CL_SIO# A
G
H3 H12
H3 H12 ISH_I2C2_SCL <9>
J3 J12 @ UZ10
3
2 2 2 2 2 2 +5V_ALW K3 J3 J12 K12 MC74VHC1G08EDFT2G_SC70-5
K3 K12 USH_EXPANDER_SMBDAT <58,66>
L3 L12
L3 L12 USH_EXPANDER_SMBCLK <58,66>
7
DMIC0 A4 7 A11
<38> DMIC0 DMIC_CLK0 A4 A11 PCH_PLTRST#_AND <11,38,42,52,68,70>
B4 B11
LID_CL# <38> DMIC_CLK0 B4 B11 M3042_DEVSLP <10>
1 2 K4 K11
ISH_LID_CL#_NB <9> K4 K11 NGFF_CONFIG_2 <58>
L4 L11
L4 L11 NGFF_CONFIG_1 <58>
DZ104
RB751S-40_SOD523-2 HDA_SDOUT_R A5 A10
LID_CL_SIO_TAB# <12> HDA_SDOUT_R HDA_SDIN0 A5 A10 GPS_DISABLE# <58>
1 2 B5 B10
ISH_LID_CL#_TAB <9> <12> HDA_SDIN0 B5 B10 W W AN_DET# <58>
K5 K10
K5 K10 NGFF_CONFIG_0 <58>
DZ105 L5 L10
L5 L10 WWAN_RADIO_DIS# <58>
RB751S-40_SOD523-2
A6 A9
+AUD_STB HDA_SYNC_R A6 A9 WWAN_FULL_PWR_EN <6>
B6 B9
<12> HDA_SYNC_R HDA_BIT_CLK_R B6 B9 NGFF_CONFIG_3 <58>
C6 C9
<12> HDA_BIT_CLK_R C6 C9 ISH_NB_MODE# <9,58>
@ RA54 1 2 0_0201_5% +RTC_CELL D6 D9
D6 D9 SAR_ACT#_1P8 <58>
E6 E9
F6 E6 E9 F9
DMIC_CLK0 F6 F9 3.3V_W W AN_EN <58>
DMIC0 G6 G9
G6 G9 +3.3V_ALW
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
100P_0201_50V8J
H6 H9
<10> USB3_PTX_DRX_P3 H6 H9
@RF@ CZ323
RF@ CZ325
@RF@ CZ326
RF@ CZ327
J6 J9
<10> USB3_PTX_DRX_N3 J6 J9
1 1 1 1 K6 K9
L6 K6 K9 L9
B L6 L9 B
A7 A8
2 2 2 2 B7 A7 A8 B8
<10> USB3_PTX_DRX_N2 B7 B8 USB3_PRX_RD_DTX_P2 <10>
C7 C8
<10> USB3_PTX_DRX_P2 C7 C8 USB3_PRX_RD_DTX_N2 <10>
D7 D8 CLASS-D POWER DOWN CONTROL CIRCUIT
E7 D7 D8 E8
<10> USB20_N4 E7 E8 USB3_PRX_RD_DTX_P3 <10>
F7 F8
HDA_SDOUT_R HDA_SDIN0 <10> USB20_P4 F7 F8 USB3_PRX_RD_DTX_N3 <10>
G7 G8
G7 G8
100P_0201_50V8J
100P_0201_50V8J
H7 H8
<10> USB20_P3 H7 H8 USB20_P9_FP <66>
@RF@ CZ328
47P_0201_50V8J
@RF@ CZ330
@RF@ CZ331
47P_0201_50V8J
@RF@ CZ332
J7 J8
<10> USB20_N3 J7 J8 USB20_N9_FP <66>
1 1 1 1 K7 K8
L7 K7 K8 L8
L7 L8 @ RA48 1 2 0_0201_5%
2 2 2 2 UNIMI_FBGCBE058-B-X
@ DA8 1 2
<58> NB_MUTE#
RB751S-40_SOD523-2 PD#
AUD_PC_BEEP 2 1 SPKR_R 1 2 HDA_SYNC_R HDA_BIT_CLK_R
SPKR <12>
1 0.1U_0201_25V6K BEEP_R
100P_0201_50V8J
100P_0201_50V8J
CA27 2 RA12 1 2 1K_0201_5% 1 2

BEEP <58> <12> HDA_RST#_R
@RF@ CZ333
47P_0201_50V8J
@RF@ CZ334
@RF@ CZ336
47P_0201_50V8J
@RF@ CZ335
CA28 0.1U_0201_25V6K RA13 1K_0201_5% @ RA50 0_0201_5%
1 1 1 1 HDA_Link is 3.3V,no need level shift circuit
2 2 2 2
SPKR_R
A BEEP_R A
100P_0201_50V8J
100P_0201_50V8J
1
1
@ CA72
10K_0201_5%
1
1
RA51
@ CA62
10K_0201_5%
RA45
2
2 Compal Electronics, Inc.
2
2
Dock
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
Reserve for USB
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
Reserve for USB
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 PWM_FAN1
RE48 10K_0201_5%
1 2 TACH_FAN1
RE51 10K_0201_5%
D D
Link 50271-0040N-001 done 0123
CONN@ JFAN1
6
GND2 5
GND1
4
4 3 PW M_FAN1
3 TACH_FAN1 PWM_FAN1 <58>
2
2 TACH_FAN1 <58>
1 +5V_RUN
1
10U_0402_6.3V6M
CVILU_CI1104M2HR1-NH
1
1
@ DE1
CE32
BZV55-B5V6_SOD80C2
2
2
C C
POWER & INSTANT ON SWITCH

TOP @ SW 3
1 2
<59,74,79> POWER_SW#_MB 1 2
@SHORT PADS~D
BOT CLIPS
CLIP1 CONN@ CLIP2 CONN@ CLIP3 CONN@ CLIP4 CONN@
B 1 1 1 1 B
P1 P1 P1 P1
EMIST_SUL-15A3M EMIST_SUL-15A3M EMIST_SUL-15A3M EMIST_SUL-15A3M

1 1 1 1
P1 P1 P1 P1
CPU
Fiducial Mark @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10
DDR CLIPS EMIST_SUL-15A3M EMIST_SUL-15A3M EMIST_SUL-25M EMIST_SUL-25M
@ FD1 H_3P7 H_3P7 H_3P7 H_3P7 H_4P0 H_4P0 H_2P5 H_2P5 H_2P5 H_3P4 CLIP20 CONN@ CLIP22 CONN@ CLIP23 CONN@ CLIP9 CONN@ CLIP10 CONN@ CLIP11 CONN@ CLIP12 CONN@
1 1 1 1 1 1 1 1
P1 P1 P1 P1 P1 P1 P1
FIDUCIAL MARK~D
1
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-25M EMIST_SUL-25M EMIST_SUL-15A3M EMIST_SUL-25M

@ FD2
1 CLIP24 CONN@ CLIP25 CONN@ CLIP26 CONN@ CLIP27 CONN@ CLIP13 CONN@ CLIP15 CONN@
1 1 1 1 1 1
P1 P1 P1 P1 P1 P1
FIDUCIAL MARK~D FBEA M
@ H11 @ H12 @ H13 @ H14
@ FD3 H_2P8X2P3N H_2P3N H_2P8N H_2P8N Gasket EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-15A3M EMIST_SUL-25M
1
FIDUCIAL MARK~D CLIP31 CONN@ 1 1 1 1
1
1 P1 P1 P1 P1
@ FD4 P1
1 EDP SSD EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-15A3M
A
SMR-TS-2-2P5-13 A
FIDUCIAL MARK~D @ ST1 @ ST2 @ ST3
CLIP_C7 CLIP_C7 CLIP_C7 CLIP32 CONN@
1
P1 DELL CONFIDENTIAL/PROPRIETARY
1
SHDCAN CONN@
1
SMR-TS-2-2P5-21P5
P1 Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
SION_C7521R_1P-T
PWRBTN, PAD, ME, FAN
5 4 3 2 1
5 4 3 2 1
+1.8V_RUN source
JUMP@
PJP42 0.013A
1 2 +1.8V_RUN
+1.8V_PRIM UZ8
PAD-OPEN1x1m
1 7
2 VIN1 VOUT1 8 +1.8V_RUN_UZ8 1 2
VIN2 VOUT2 CZ120 0.1U_0201_10V6K
@ RZ345 1 2 0_0201_5% RUN_ON_1.8V 3 6 1 2
<17,58,59,78,87> RUN_ON ON CT CZ121 470P_0201_50V7K
D D
+5V_ALW
4
VBIAS 5
GND1 9
1 GND2
@ CZ197
470P_0201_50V7K AOZ1336DI_DFN8_2X2
2
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
EC request to reserve OR gate for WLAN power enable

+3.3V_ALW_PCH/+3.3V_RUN source 3.435A +3.3V_ALW
JUMP@
PJP39 +3.3V_ALW_PCH
1
1 2
+3.3V_RUN +3.3V_ALW
RZ518
+3.3V_ALW PAD-OPEN1x3m 100K_0201_5%
UZ3
1
20K_0201_5%
@ RZ379
20K_0201_5%
1 14 1 2
2
VIN1_1 VOUT1_1 +3.3V_RUN_UZ3
RZ1483
2 13 CZ115 0.1U_0201_10V6K
VIN1_2 VOUT1_2 <58> SLP_WLAN#_GATE
RUN_ON 3 12 1 2
<17,58,59,78,87> RUN_ON ON1 CT1 CZ113 1000P_0201_50V7K
2
+5V_ALW 4 11
VBIAS GND
5 10 1 2 1 2
<11,87> PCH_PRIM_EN ON2 CT2 CZ114 100P_0201_50V8J @ RZ71 0_0201_5%
2
C 6 9 +3.3V_ALW_PCH_UZ3 C
7 VIN2_1 VOUT2_1 8 1 2 DZ9
G
VIN2_2 VOUT2_2 CZ112 0.1U_0201_10V6K
15 3
GPAD JUMP@ 1 3 SLP_WLAN#_M
<11> SIO_SLP_WLAN# 1 WLAN_PWR_EN
EM5209VF_DFN14_3X2 PJP38
S
1 2 2
+3.3V_ALW_PCH
QZ15
PAD-OPEN1x1m PJE138K_SOT-523-3
0.63A <58> AUX_EN_WOWL BAT54CTB_SOT-523-3
1 2
@ RZ70 0_0201_5%
+5V_RUN/+3.3V_WLAN source
+1.8V_PRIM discharge circuit
+1.8V_PRIM
Need to be close to the source(PJP502)
JUMP@
3.076A
1
100_0603_5%
PJP40
RZ122
1 2
+5V_RUN
+5V_ALW
UZ47 PAD-OPEN1x2m
2
1 14 +5V_RUN_UZ47 1 2
+1.8V_PRIM_DIS
2 VIN1_1 VOUT1_1 13 CZ116 0.1U_0201_10V6K
VIN1_2 VOUT1_2 +5V_ALW
B 3 12 1 2 B
<17,58,59,78,87> RUN_ON ON1 CT1 CZ110 470P_0201_50V7K
1
1M_0402_5%
4 11
VBIAS GND
RZ121
3
WLAN_PWR_EN 5 10 1 2
PJX138K_SOT563-6
ON2 CT2 CZ118 470P_0201_50V7K
6 9 +3.3V_WLAN_UZ47 1 2
+3.3V_ALW
2
7 VIN2_1 VOUT2_1 8 CZ122 0.1U_0201_10V6K PCH_PRIM_EN# 5
QZ10B
VIN2_2 VOUT2_2 JUMP@
6
15 PJP36
PJX138K_SOT563-6
GPAD 1 2 +3.3V_WLAN
EM5209VF_DFN14_3X2
4
PAD-OPEN1x2m PCH_PRIM_EN 2
QZ10A
2A
1 2 WLAN_PWR_EN
RZ38 100K_0201_5%
1
A A
Power control
5 4 3 2 1
5 4 3 2 1
CONN@ +3.3V_RUN +13.5VB
1
JAPS1 JESPI
1
For BL_PWR_SRC & LCDVDD monitor
+3.3V_ALW_PCH 1 1
3
2 2 +LCDVDD
<11,17,42,59> SIO_SLP_S3# 2 2
3 3 ESPI_IO0_1P8 <8,58>
+3.3V_ALW 3 3
4 4 ESPI_IO1_1P8 <8,58>
<11> SIO_SLP_S5# 4 4
5 5 ESPI_IO2_1P8 <8,58> 2
<11,17,86,87> SIO_SLP_S4# 5 5
6 6
<11> SIO_SLP_A# 6 6 ESPI_IO3_1P8 <8,58>
7 7
+3.3V_ALW 7 7 ESPI_CS#_1P8 <8,58>
1
8 8
8 8 ESPI_RESET#_1P8 <8,58>
1
9 11 9 +BL_PWR_SRC RV623
<11,58> PCH_RTCRST# 9 GND1 9 QV18
10 12 10 RV627 100K_0201_5%
ESPI_CLK_1P8 <8,58>
1
11 10 GND2 10 10K_0201_5% MMBT3906H_SOT23-3
<59,74,77> POWER_SW#_MB 11
12 MOD_FP241AH-010GAAM_10P-X
2
13 12
<11> SYS_RESET# CONN@
2
13
1
D 14 D
15 14 2 1 RV625 PANEL_PW RGD 1 2
<9,11,17,66,87> SIO_SLP_S0# 15 PANEL_MONITOR <58>
16 47K_0201_5% @ RV628 0_0201_5%
17 16
J
X
T
_
F
P
2
4
1
A
H
-
0
1
0
G
A
A
M
L
I
N
K
D
O
N
E
DV11
0.1U_0201_25V6K
17 1
200K_0201_5%
2200P_0201_25V7K
18 RB751S-40_SOD523-2
2
18
1
1M_0201_5%
CV634
1 1
1
RV626
RV624
19 C
GND1 BL_PW R_MONITOR
CV633
20 2 2 CV632
GND2 B 0.1U_0201_25V6K
2 QV19 E 2
2
VM_FPC0510-18RP-TAGHL-X LMBT3904W T1G_SC70-3
+3.3V_ALW +3.3V_RUN
3
1
10_0402_1%
1
RE71
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
RF Request
2
1
100K_0201_5%
RE715
RE714
RE713
RE712
+13.5VB
10K_0201_5%
10K_0201_5%
10K_0201_5%
@ RE75
2
1
2 RE72
2 RE73
2 RE74
JDEG1
2
1 +EC_DEBUG_VCC +LCDVDD RV631

1 JTAG_TDI QV20
47P_0201_50V8J
RF@
100P_0201_50V8J
RF@
2 10K_0201_5%
JTAG_TDI <58>
2
2 JTAG_TMS
1
3 MMBT3906H_SOT23-3
3 JTAG_CLK JTAG_TMS <58> 1 1
4
JTAG_CLK <58>
2
4 5 JTAG_TDO RE86
JTAG_TDO <58>
1
5
CV755
CV756
6 MSCLK 10K_0201_5%
6 7 MSDATA 1 2 2 1 RV630 2 2
7 8 HOST_DEBUG_TX 47K_0201_5%
8 DEBUG_TX
200K_0201_5%
2200P_0201_25V7K
11 9 DV12
0.1U_0201_25V6K
GND1 9
1
12 10 1 RB751S-40_SOD523-2 1
2
GND2 10
RV629
1 2
CV652
<6> SBIOS_TX
CV651
MOD_FP241AH-010GAAM_10P-X @ RE306 0_0201_5%
1
2 C place as close as QV18
CONN@ LCDVDD_MONITOR
2 2
HOST_DEBUG_TX <58>
2
B
MSDATA <58>
QV21 E
MSCLK <58>
3
C C
1 2
J
X
T
_
F
P
2
4
1
A
H
-
0
1
0
G
A
A
M
L
I
N
K
D
O
N
E
LMBT3904W T1G_SC70-3
@ RE30 0_0201_5%
+1.05V_PRIM +1.05V_PRIM_XDP
@ RC216
1 2
0_0402_5%
M-BIST
RC328, RC850, RC851, RC852, RC853, RC735,
RC736, RC737 need pop when use XDP BATT_YELLOW# <64>
+1.05V_PRIM_XDP 1 2
+1.05V_PRIM_XDP CFG3 <13> CPU_XDP_TCLK XDP_JTAGX
RC121 1.5K_0201_5% 1 2
CPU XDP XDP_PRSNT_PIN1 @ RC328 0_0201_5%
XDP_JTAGX <14>
TDO_XDP 1 0_0201_5% CPU_XDP_TDO

0.1U_0201_10V6K
0.1U_0201_10V6K
1 2 @ RC850 2
CPU_XDP_TDO <14>
@ CC288
@ CC299
1 1 @ RC122 0_0201_5% @ DZ12

JXDP1 CONN@ TDI_XDP @ RC851 2 1 0_0201_5% CPU_XDP_TDI 1 2
CPU_XDP_TDI <14> <58,84> ACAV_IN
3
1 2
3 1 2 4 XDP_TMS @ RC852 2 1 0_0201_5% CPU_XDP_TMS RB751S-40_SOD523-2
2 2 <14> CPU_XDP_PREQ# 3 4 CPU_XDP_TMS <14> M_BIST_R
5 6 2 1
R2
R1=10K;R2=10K
<14> CPU_XDP_PRDY# 5 6 TRST#_XDP @ RC853 <58> M_BIST
7 8 2 1 0_0201_5% CPU_XDP_TRST# @ RZ1415 0_0201_5% BAT1_LED#_R 2 QZ3
7 8 CPU_XDP_TRST# <14>
9 10 +3.3V_ALW 1 2 LMUN5111T1G_SC70-3
11 9 10 12 RZ1482 330K_0201_5%
R1
13 11 12 14 XDP_TMS 1 2 PCH_JTAG_TMS 1 2
13 14 PCH_JTAG_TMS <14> <8,58,63> PCH_RSMRST#
15 16 @ RC735 0_0201_5% @ RZ1413 330K_0201_5%
Place near 15 16
1
17 18 TDI_XDP 1 2 PCH_JTAG_TDI C
JXDP1 PCH_JTAG_TDI <14>
1
19 17 18 20 @ RC736 0_0201_5% 2 1 2
21 19 20 22 TDO_XDP 1 2 PCH_JTAG_TDO CZ218 2.2U_0402_10V6M B
21 22 PCH_JTAG_TDO <14>
23 24 @ RC737 0_0201_5% QZ21 E
3
25 23 24 26 LMBT3904W T1G_SC70-3
27 25 26 28 1 2
29 27 28 30 Depop RC328, RC850, RC851, RC852, RC853, RC735, RZ25 150_0201_1%
29 30
31
33 31 32
32
34
RC736, RC737 according ESD team request +1.05V_VCCSTG
@ RC123 1 33 34 <58,59,83> POWER_SW_IN#

B 2 1K_0201_5% 35 36 B
<11,59> VCCST_PWRGD 35 36
37 38
CXDP@ RC124 1 2 1K_0201_5% H_VCCST_PWRGD_XDP 39 37 38 40 PCH_JTAG_TDI 1 2
<11,63> PCH_RSMRST#_AND 39 40
41 42 RC569 51_0201_5%
43 41 42 44 PCH_JTAG_TDO 1 2
45 43 44 46 ITP_PMODE RC568 100_0201_5%
45 46 XDP_DBRESET# ITP_PMODE <13> PCH_JTAG_TMS
47 48 XDP_DBRESET# <11> 1 2
49 47 48 50 RC130 51_0201_5%
51 49 50 52 TDO_XDP
53 51 52 54 TRST#_XDP
55 53 54 56 TDI_XDP
<14> PCH_JTAG_TCK CPU_XDP_TCLK 55 56 XDP_TMS +1.05V_VCCSTG
57 58
<14> CPU_XDP_TCLK 57 58
59 60
59 60 PCH_SPI_DO2_XDP <8>
61
61 CPU_XDP_TMS 1 2
@ RC131
CPU_XDP_TDI
51_0201_5% Service Mode Switch:
62 63 1 2
GND GND @ RC134 51_0201_5% Add a switch to ME_FWP signal to unlock the ME region and
CPU_XDP_TDO 1 2 allow the entire region of the SPI flash to be updated using FPT.
JXT_FP270H-061G1AM RC135 100_0201_5%
+3.3V_ALW_PCH
Link FP270H-061G1AM done 0131 CPU_XDP_TRST# 1 2
@ RC136 51_0201_5% ME_FW P 1 2 ME_FWP_PCH
+3.3V_RUN CPU_XDP_TCLK 1 2 @ RC221 0_0201_5%
1
RC139 51_0201_5% PT,ST pop RC222 and SW1; MP pop RC221
SYS_PRES# 1 2 SYS_PRES_SHIP# +3.3V_TBAT_LDO +3.3V_TBAT_LDO +13.5VB @ RC222
@ RZ6 0_0201_5% 2 1 XDP_DBRESET# 1K_0201_5%
If no need Battery switch circuit pop RZ6 depop SW4, RZ1, RC137 3K_0201_1%
RZ2, RZ3, RZ4, RZ5, LED3, QZ2, QZ19 +1.05V_PRIM_XDP
2
1
@ SW ME1
+3.3V_TBAT_LDO @ RZ3 1
@ RZ2 1 2 CPU_XDP_PREQ# ME_FWP_PCH 2 1
100_0201_5% <12> ME_FWP_PCH
2M_0201_5% @ RC138 51_0201_5% ME_FW P 3 C
<58> ME_FWP 2
4
2
2 2
G1
1
5
TDO_XDP H_VCCST_PW RGD_XDP G2
2.2K_0201_5%
2.2K_0201_5%
1
@ RZ1 SSAJ120100_3P-X
6
@ESD@ CC306
@ESD@ CC307
100K_0201_5% @ LED3 ME_FWP PCH has internal 20K PD. Link SSAJ120100 done 0514
0.1U_0201_25V6K
HT-191UD5_AMBER 0.1U_0201_25V6K
@ RZ4
@ RZ5
PJX138K_SOT-563-6
Place near JXDP1.48 1 1 (suspend power rail)

2
@ QZ2A
2 XDP_DBRESET#
FLASH DESCRIPTOR SECURITY OVERRIDE
2
A A
3 1
2 2
@ SW 4
LOW = ENABLE (DEFAULT) -->Pin2 & Pin3 short
PJX138K_SOT-563-6
HIGH = DISABLE (ME can update) -->Pin1 & Pin2 short

0.1U_0201_25V6K
1 1
1
1
2
@ QZ2B
<83> SYS_PRES_SHIP# C
3 5
<83> SYS_PRES#
1
2
CC326
4
5 G1 D 2 ESD request,Place near JXDP1 side.
G2
SSAJ120100_3P-X 2 G
4
@ QZ19
S PJE138K_SOT-523-3

3
Battery Switch
LOW = BATTERY ON (DEFAULT) -->Pin2 & Pin3 short TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT XDP/CMC/APS...debug
HIGH = BATTERY OFF -->Pin1 & Pin2 short BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Google Debug & INAs
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D PWR-Block Diagram
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
EMI Part
EMI@ PL806
5A_Z80_20M_0805_2P +20V_TBTA_VBUS_1 +20V_VBUSA_DC_SS S2
1 2 S1
PQ9 PQ4
+20V_TBTA_VBUS EMI@ PL805 EMZB08P03V_EDFN3X3-8-5 EMZB08P03V_EDFN3X3-8-5 place on BOT side close to S2
5A_Z80_20M_0805_2P 1 1
1 2 +20V_TBTA_VBUS_1 place on BOT side 2 2 +19.5V_SDC_IN
10U_0603_25V6M
10U_0603_25V6M
AOSS21311C 1P SOT23-3
1
3 5 5 3
0.022U_0402
1
300K_0201_5%
EMI@ PC711
EMI@ PC712
PR10
100P_0402_50V8J
100P_0402_50V8J
PQ5
@ PC4
100K_0201_5%
499K_0201_1%
300K_0201_5%
0.47U_0402_25V6K
1
1
PR31
PR11
499K_0201_1%
1000P_0402_50V7K
0.1U_0402_25V6
2
1
3
S
PQ11
PC19
PC20
PC14
@ PR57
PC15
PC6
2
1
G
PR12
2
2
3
S
100K_0201_5%
2
2
1
1
G
D 2 D D
1
EMI@
EMI@
@EMI@
@EMI@
short pad PR15 +3.3V_VDD
PR14
PR47 +3.3V_VDD D 100K_0201_5%
1
1
0_0201_5%
1 2 PR32
+3.3V_VDD
2
1
1
100K_0201_5%
100K_0201_5% @
PR16 PR17
6
PR33
PC13 49.9K_0201_1% 100K_0201_5%
PJX138K_SOT563-6
0.1U_0402_10V7K
S1_OVP <82>
PQ1A
1 2 PR18
2
3
49.9K_0201_1% 2
PQ10B
PJX138K_SOT563-6
2
5
1
PJX138K_SOT563-6
5
PQ10A
1 short pad
P
B
6
PJX138K_SOT563-6
4 2
O
3
<44,82,84> EN_PD_HV_1 2 short pad
A
PQ7A
PJX138K_SOT563-6
PR25
PQ1B
PR51 2 1 2
3
0_0201_5% EN_PD_HV_1 <44,82,84> 5 1 2
1
1
EN_PD_HV_1 <44,82,84>
100K_0201_5%
PU3 @ PR50
2
PR45
MC74VHC1G08DFT2G_SC70-5 0_0201_5% 0_0201_5%
1
6
4
PJX138K_SOT563-6
2
PQ6A
3
PJX138K_SOT563-6
2 short pad
PQ7B
PR20
PQ6B 5 1 2
PJX138K_SOT563-6 VBUS1_ECOK_R <58,82>
1
0_0201_5%
4 3 PR24
<58> DCIN1_EN_R
1M_0201_1%
2
1
100K_0201_5%
1
PR28
5
1
100K_0201_5%
PR27
0.1U_0402_25V6
2
1
100K_0201_5%
PC21
PR21
2
2
2
+3.3V_VDD
+3.3V_ALW
C C
EMI Part
EMI@ PL801
5A_Z80_20M_0805_2P +20V_TBTB_VBUS_1 S4 S5
1 2
PQ800 +20V_VBUSB_DC_SS PQ801
+20V_TBTB_VBUS EMI@ PL800
5A_Z80_20M_0805_2P 1
EMZB08P03V_EDFN3X3-8-5 EMZB08P03V_EDFN3X3-8-5
1 close to S5
1 2 +20V_TBTB_VBUS_1 place on BOT side 2 2 place on BOT side
3 5 5 3 +19.5V_SDC_IN
300K_0201_5%
10U_0603_25V6M
10U_0603_25V6M
0.47U_0402_25V6K
1
1
100P_0402_50V8J
100P_0402_50V8J
1500P_0402_50V7K
1
PQ805
100K_0201_5%
PR801
EMI@ PC713
EMI@ PC714
PR802
0.1U_0402_25V6
1
1
PQ803
PC803
499K_0201_1%
300K_0201_5%
1000P_0402_50V7K
4
1
1
@EMI@ PC806
EMI@ PC807
EMI@ PC809
@ PR823
EMI@ PC816
499K_0201_1%
2
3
3
S S
PR803
@ PC802
2 PR804
2
2
G G
2 2
100K_0201_5%
2
2
1
+3.3V_VDD
2
2
1
@ PR862
short pad
100K_0201_5%
D D
+3.3V_VDD
1
PR807
PR808
PR859 100K_0201_5%
2
0_0201_5%
2
1
1
1 2
+3.3V_VDD
2
1
49.9K_0201_1%
PR810 PR812 PR813
PJX138K_SOT563-6
PR811
100K_0201_5% 49.9K_0201_1% 100K_0201_5%
3
PQ802A
PJX138K_SOT563-6
PQ806B
1 2
EN_PD_HV_1#
2
2
2
PC814 5
0.1U_0402_10V7K
1
5
4
6
PQ802B
PJX138K_SOT563-6
1 short pad
P
<44,82,84> EN_PD_HV_2 B
6
PJX138K_SOT563-6
4 5
O
1
PQ807A
PJX138K_SOT563-6
2
A
G
6
PQ804A
2 short pad
1
PJX138K_SOT563-6
1 2 2
100K_0201_5%
<82> S4_OVP <44,82,84> EN_PD_HV_2 PR868 PR820

3
PQ806A
PR855
PU801 0_0201_5% 0_0201_5%

4
MC74VHC1G08DFT2G_SC70-5 @ PR867 2 1 2
EN_PD_HV_2 <44,82,84>
2
0_0201_5%
1
2
1
short pad
PJX138K_SOT563-6
PQ804B
@ PD810 PR861
PQ807B 0_0201_5%
1 2 PJX138K_SOT563-6 1 2 5
+13.5VB <58,82> VBUS2_ECOK_R
4 3
RB520SM-30T2R_EMD2-2 <58> DCIN2_EN_R
1
1
100K_0201_5%
4
PR821
PR892 PR819
PD803
+3.3V_VDD +3.3V_VDD_DCIN 22_0805_5% 1M_0201_1%
2 1 2
+20V_TBTA_VBUS_1
5
2
1
+20V_LDO_input
2
1
100K_0201_5%
100K_0201_5%
PR13 short pad PR893
PU2
1
1000P_0402_50V7K
B 0_0603_5% 22_0805_5% B
0.1U_0402_25V6
1
1
PC11
1 2 1 3 1 2
PR815
PC815
PR822
VCC +20V_TBTB_VBUS_1
2
3
2
VOUT 2 BAT54CW_SOT323-3
2
GND
82P_0402_50V8J
PC12
AP2204R-3.3TRG1_SOT89-3
1
PC10 +3.3V_VDD
4.7U_0402_6.3V6M +3.3V_ALW
2
2
RF@
+3.3V_ALW +3.3V_ALW
1
short pad
@ PR824 @ PR825
PR826 100K_0201_5% 100K_0201_5% +3.3V_ALW
0_0201_5%
2
1 2
<58,82> VBUS1_ECOK_R
1
<58,82> VBUS2_ECOK_R 1 2
PR828 CMOUT <84>
PR827 100K_0201_5%
0_0201_5%
AC_DISC# <58,84>
2
PR829 short pad
+3.3V_ALW 0_0201_5%
1 2
6
+20V_TBTA_VBUS_1
3
+20V_TBTB_VBUS_1 +3.3V_ALW
+3.3V_VDD PR830
+3.3V_VDD 100K_0201_5% 2
PJX138K_SOT563-6
5 2 5
PQ810A
PJX138K_SOT563-6
PQ810B
+3.3V_VDD PR833
S4 OVP<44,82,84> +3.3V_VDD
499K_0201_1%
100K_0201_5%
S1 OVP<44,82,84>
1
1
EN_PD_HV_2
PQ811A
PJX138K_SOT563-6
PJX138K_SOT563-6
PQ811B
115K_0201_1%
499K_0201_1%
short pad
2
1
4
EN_PD_HV_1 +3.3V_ALW
PR58
115K_0201_1%
PD4 PR834
PR53
PR831
SDMK0340L-7-F_SOD323-2 PD802 0_0201_5%

1 2 1 2 +3.3V_ALW
PR832
SDMK0340L-7-F_SOD323-2 <44,82,84> EN_PD_HV_2
1
1 2 2
47K_0201_1%
47K_0201_1%
PQ808A
2
47K_0201_1%
PC810
1500P_0402_50V7K
PJX138K_SOT563-6
2
2
1
1
@ PR55
47K_0201_1%
+3.3V_VDD S4_OVP
PR838
2
1
1
PR85
S4_OVP <82>
+3.3V_VDD S1_OVP
100K_0201_5%
@ PR835
PR869
PR839 @ PROCHOT#_CHG <84>
2
S1_OVP <82>
1
5 PQ808B 100K_0201_5%
3
PJX138K_SOT563-6
2
2
8
6
PU800A 1
2
2
8
3 AS393MMTR-G1_MSOP8 PU800B
P
+ 1 5 5 AS393MMTR-G1_MSOP8 PQ812
P
O +
4
2 PQ13B 7 5 @0@ PR841 2 PQ809A

10U_0402_6.3V6M
2.2U_0402_25V6M
PJE138K 1N SOT-523-3 MOSFET

- O
1
1M_0201_1%
6 2
97.6K_0201_1%
PJX138K_SOT563-6 PQ813B 0_0201_5% PJX138K_SOT563-6

100P_0402_50V8J
10U_0402_6.3V6M
2.2U_0402_25V6M
-
1
3
1M_0201_1%
1 2
PR86
PJX138K_SOT563-6
42.2K_0201_1%
97.6K_0201_1%
100P_0402_50V8J
4
1
1
PR52
PC16
PC17
PC18
PR870
42.2K_0201_1%
4
4
1
PR54
PR842
PC811
PC812
PC813
1
3
PR843
<44,82,84> EN_PD_HV_1 1 2 5
2
A PR844 PQ809B A
2
0_0201_5% PJX138K_SOT563-6
2
4
6
short pad
6
PJX138K_SOT563-6
@0@ PR845
OVP setting:5.4V
PQ13A
PJX138K_SOT563-6
0_0201_5%
OVP setting:5.4V
PQ813A
2 1 2
EN_PD_HV_1 <44,82,84>
2 EN_PD_HV_2 <44,82,84>
1
1
PR56
1
100K_0201_5% PR846
100K_0201_5%
2
2

Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 2TypeC PD_Selector
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PD1 ESD@ PD2 ESD@
D CEST523NC5VB 3P C/A SOT-523 AU CEST523NC5VB 3P C/A SOT-523 AU PR2 RTC_DET# <8> D
1
1K_0201_5%
+3.3V_RTC_LDO
1
1
2
EMI@ PL1 +3.3V_TBAT_LDO @ PQ14
FBMJ4516HS720NT_2P PJE138K 1N SOT-523-3 MOSFET
+Z4012
2
3
1 2
1
2
2
@ PR9
EMI@ PL2 PD5 100K_0201_5% 3
2
Primary Battery Connector +13.2VB_PBATT_C
FBMJ4516HS720NT_2P
1 2 +13.2VB_BATT LBAT54HT1G_SOD323-2-X
2
PBATT1 CONN@
1
12
+RTC_CELL
GND2 11 PD3
1
GND1
10 1 2 BAS40CW_SOT323-3
10 9
9
1
8 PR38
8 PBAT_SMBCLK_C PBAT_CHARGER_SMBCLK <58,84>
7 100_0201_5% PC3
2200P_0402_50V7K
7 6 PBAT_SMBDAT_C 1 2 @ PR3
1U_0402_25V6K
27P_0402_50V8J
PBAT_CHARGER_SMBDAT <58,84>
2
6 5 PBAT_LDO 1.2K_0402_5%
PC2
5
1
4 PR39 1 2
EMI@ PC1
4 3
SYS_PRES# <79>
100_0201_5% +RTC_CELL +COINCELL
3 2 1 2
+3.3V_TBAT_LDO
2
2 1 CONN@ JRTC1
RF@
1 PR40 short pad 1

0_0201_5% +COINCELL 2 1
CVILU_CI8710M2VR0-NH 1 2 2 3
PBAT_PRES# <58,83> G1 4
@ PR41 G2
100_0402_5% CVILU_CI4202M2HR0-NH
GND
+3.3V_ALW
C C
Note: new ASM support circuit
1
PR4
100K_0201_5%
Location pop depop
2
PBAT_PRES# <58,83>
+3.3V_TBAT_LDO
RE853 V X 1
PQ15
PD4005 V X 2 PJE138K 1N SOT-523-3 MOSFET
1
CE399 V X
PR5 3
2M_0201_5%
QE31 V X POWER_SW_IN# <58,59,79>
2
PC4001 V 2.2U V 1U
1
@ QE31
Storage mode wake up circuit <79,83> SYS_PRES_SHIP# 1 2 SYS_PRES_SHIP#_QE31 2
@ RE853
1U_0402_25V6K
1M_0201_5% 1
RB520SM-30T2R_EMD2-2
3
@ CE399
2
@ PD4005
Add for selection

1
<58,59> LID_POWER_ON#
@0@ PR4020 @0@ PR4015

0_0402_5% 0_0402_5%
1 2 1 2
+RTC_CELL SYS_PRES_SHIP# <79,83>
1
B PR4019 B
10M_0402_5%
0_0402_5%
@ PR4017
6
1 2 @ PD4002
+RTC_CELL
PJX138K_SOT563-6
2 @ PR4008
+3.3V_TBAT_LDO 499K_0402_1%
@ PQ4002A
2
1 1 2 2
@ PD4001
2 3
+3.3V_TBAT_LDO +3.3V_ALW
1
1
BAT54CW_SOT323-3
1
@ PR4009
3 499K_0402_1% @ PR4010
+3.3V_ALW 100K_0402_5%
PJX138K_SOT563-6
BAT54CW_SOT323-3
2
@ PD4003 @ PR4023
1M_0201_1%
@ PQ4002B
1 2 1 2 5
1M_0402_1%
+13.5VB
1
@ PD4004
PR4006
1
2 1
1U_0402_6.3V6K
@ PC4004
@ PR4012
1
4
short pad RB520SM-30T2R_EMD2-2 100K_0402_5%
2
PR4004 PU4000 @ PR4011
PJX138K_SOT563-6
PR4003
0_0402_5% SN74LVC1G123DCUR_VSSOP8 3M_0402_1%
499K_0402_1%
2
1
1 2 1 8 1 2 2
@ PQ4003A
1U_0402_6.3V6K
<58,83,85> ALWON
PC4001
A# VCC
PR4001 PR4005
2
100K_0402_5% 1 2 2 7
2
B R/CEXT
3
1U_0402_6.3V6K
@ PC4002
1U_0402_6.3V6K
@ PC4003
0_0402_5% 3 6 @ PR4014
PJX138K_SOT563-6
2
CLR# CEXT
1
short pad 100K_0402_5%
@ PQ4003B
1
4 5 PR4016 5 1 2
PQ4001 GND Q 0_0402_5% +13.5VB
2
PJE138K 1N SOT-523-3 MOSFET 1 2 SYS_PRES_SHIP# <79,83>
2
1
1
4
@ PR4013
1M_0402_1%
PR4002 100K_0402_5%
PR4007
100K_0402_5% 3
2
2
<58,83,85> ALWON
A A
Title
Battery Connector/ RTC
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-J261P
5 4 3 2 1
A B C D
EMI@ PL702
+19.5V_AC 5A_Z80_20M_0805_2P
1 2
+19.5V_SDC_IN +19.5V_CHARGER
PR700
0.01_1206_1% EMI@ PL700
5A_Z80_20M_0805_2P
1 4 1 2
+13.5VB
2 3
10U_0805_25VAK
10U_0805_25VAK
SMF4L22A_SOD123FL2
1
0.1U_0402_25V6
2200P_0402_50V7K
15U_B2_25VM_R100M
1
1
PC702
PC703
+
@ PD701
EMI@ PC700
EMI@ PC701
PC706
1
2
2
2
1 1
CSIN_CHG_R
CSIP_CHG_R
10U_0603_16VAM
10U_0603_16VAM
10U_0603_16VAM
10U_0603_16VAM
1
15U_B2_25VM_R100M
1
1
PC707
PC708
PC709
PC710
+
PC715
2
2
2
1
PR701 PR702
1_0603_1% 1_0603_1%
+13.5VB
2200P_0402_50V7K
2
0.1U_0402_25V6
1
1
EMI@ PC720
EMI@ PC721
PC719
4.7U_0402_6.3V6M
2
1 2
1U_0402_25V6K
1U_0402_25V6K
2200P_0201_25V
2200P_0201_25V
1U_0402_25V6K
82P_0201_50V8J
82P_0201_50V8J
82P_0201_50V8J
0.1U_0201_25V6K
0.1U_0201_25V6K
0.1U_0201_25V6K
0.1U_0201_25V6K
1
1
PC725
PC726
1
PC728
PC729
PC730
PC731
PC732
PC733
PC734
PC735
PC722
PC723
1
2
2
PC727
2
0.47U_0402_25V6K
1BST1_CHG_R2
Not to change short pad
RF@
RF@
RF@
RF@
RF@
RF@
RF@
RF@
RF@
RF@
+19.5V_SDC_IN PR703
0_0603_5%
1 2 ADP_CHG
1
PD702
+13.5VB 2 1 PR705
PR704
22P_0201_25V8
22P_0201_25V8
432K_0201_1%
47P_0201_25V8J
47P_0201_25V8J
100P_0201_25V8J
100P_0201_25V8J
SDMK0340L-7-F_SOD323-2~D 4.7_0603_1% 1 1
1
2 2
PC756
PC757
PC758
PC759
PC760
PC761
DCIN_CHG_R
PD704
2
2
ACIN_CHG
2 1
CSIP_CHG
CSIN_CHG
BOOT1_CHG
UG1_CHG
LX1_CHG
LG1_CHG
2
+19.5V_SDC_IN 2 2
1
1
RF@
RF@
RF@
RF@
RF@
RF@
RB520SM-30T2R_EMD2-2 PC736 PR706
PR707
0.1U_0402_25V6 97.6K_0201_1% 4.7_0603_5%
1 2 VDD_CHG
1
@ PC790
2
2.2U_0402_25V6M PR708
1 2 PU700
16
15
14
13
12
11
10
33
2_0805_5%
9
ISL9538CHRTZ-T_TQFN32_4X4-X
PC737
BOOT1
UGATE1
PHASE1
LGATE1
CSIN
PAD
ADP
CSIP
ASGATE
2
2.2U_0402_25V6M EVT use SA0000CUG10 sample

+13.5VB_VCHGR
9
1 2 DCIN_CHG
17 8 VDDP_CHG 1 2 UG1_CHG 1 8 LG1_CHG LG2_CHG 8 1 UG2_CHG PQ702
D1_3
D1_3
1 2 DCIN VDDP G1 G2 G2 G1 PR711 EMZB08P03V_EDFN3X3-8-5
@0@ PR746 0_0201_5% VDD_CHG 18 7 LG2_CHG PC738 LX1_CHG 2 7 1UH_MMD-10BDN1R0M-R2L__12.5A_20% 7 2 LX2_CHG 0.005_1206_1% 1
VDD LGATE2 S1/D2 D2/S1_3 D2/S1_3 S1/D2
PC739 <58,82> AC_DISC#
1 2 2.2U 16V K X5R 0402 PL701 2 +13.2VB_BATT
1
4.7U 16V M X5R 0402 short pad 19 6 LX2_CHG 3 6 1 4 6 3 1 4 3 5

100K_0201_1% <96> ACIN_CHG ACIN PHASE2 D1_1 D2/S1_2 D2/S1_2 D1_1
PR709 0_0201_5%
PR710 1 2 CMIN_CHG 20 5 UG2_CHG 4 5 2 3 5 4 2 3
S2
S2
PR713 0_0402_5% CMIN UGATE2 D1_2 D2/S1_1 LX1_CHG LX2_CHG D2/S1_1 D1_2
4
1 2 SDA_CHG 21 4 BOOT2_CHG 1 2 BST2_CHG_R
1 2
<58,83> PBAT_CHARGER_SMBDAT
2
10
10
SDA BOOT2
1
4.7_1206_5%
4.7_1206_5%
10U_0603_25V6M
10U_0603_25V6M
ACAV_IN1 PR715
1 2 0_0402_5%SCL_CHG 22 3 VSYS_CHG PC740 PR714 PQ700 PQ701
EMI@ PR717
EMI@ PR718
10U_0603_25V6M
<58,83> PBAT_CHARGER_SMBCLK SCL VSYS
1
0.47U_0402_25V6K 2.2_0603_1% AOE6936_DFN5X6E8-10 AOE6936_DFN5X6E8-10
PC741
PC742
1
1 PR719
1
1
2 PROCHOT#_CHG 23 2 CSOP_CHG
@ PC770
<14,44,58,88> PROCHOT#
AMON/BMON
PROCHOT# CSOP
PQ703
PR716
154K_0402_1%
1SNUB1_CHG 2
1SNUB2_CHG 2
2
CSON_CHG
BATGONE
0_0201_5% 24 1
4700P_0402_25V7K
<82> PROCHOT#_CHG
2
ACOK CSON
1
CMOUT
2 BGATE PR721 short pad

<58> AC_DIS
COMP
PROG
PSYS
VBAT
0_0402_5%
PC743
2
1
1 2
+13.5VB
680P_0402_50V7K
680P_0402_50V7K
BGATE_CHG
PR720 3
25
26
27
28
29
30
31
32
1M_0201_1%
EMI@ PC746
EMI@ PC747
PR724 1 2
2
105K_0402_1% COMP_CHG
AMON/BMON_CHG
PSYS_CHG
100K_0201_1%
2 PR725 1 PROG_CHG
VBAT1_CHG
BGATE_CHG
2
CMOUT_CHG
3
1 2 BATGONE_CHG @ PC745 3
2.2U_0402_25V6M
PR726
100K_0201_1%
1 2
+3.3V_ALW
PR727 @ PC748
<82> CMOUT 1 2 1U_0402_25V6K
0_0201_5% 1 2
short pad
PR733
1_0603_1%
1 2 CSOP_CHG_R
PSYS R on CPU Controller side
1
short pad
0_0402_5%
0.1U_0402_25V6
560P_0402_50V7K
1
PR728
short pad
1
1
PC750
short pad PC752

0_0201_5%
1
1
@ PC749
0_0201_5%
0_0201_5%
1U_0402_25V6K
PR729
2
CSON_CHG_R
PR743
PR731
1 2
2
2
PR734
2
0.012U_0402_16V7K
+3.3V_VDD
1
1_0603_1%
PC751
2
I_BATT
1 2 PC754
I_ADP
2
0.1U_0402_10V7K
PC753 1 2
0.22U_0402_25V6K
I_SYS
<58,88,96>
<44,82> EN_PD_HV_1
3
5
1 1
P
IN1 4
O ACAV_IN <58,79>
<58>
<58>
ACAV_IN11
I_BATT
I_ADP
<44,82> EN_PD_HV_2
2 2 2
G
IN2
1
1 2
100K_0201_1%
1
100K_0201_1%
PR741 PU701
PR739
PR744
PR738 PD705 0_0201_5% MC74VHC1G08DFT2G_SC70-5
Close to EC ADP_I pin +13.2VB_BATT
1
4 100_0402_5% BAT54CW_SOT323-3 4
@ PC755
2
short pad
0.1U_0402_25V6
2
2
DELL CONFIDENTIAL/PROPRIETARY Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-J261P
A B C D
A B C D E
ALW_PWRGD_3V_5V
ALW_PWRGD_3V_5V ALW_PWRGD_3V_5V <11,63>
1 1
PR102 +13.5VB
short pad 499K_0201_1%
+13.5VB ENLDO_3V5V 1 2
PR100
JUMP@ PJP100 0_0603_5% PC102 3VALWP
1
+13.5VB_3V BST_3V 2 BST_3V_R TDC 7.35A
499K_0201_1%
1 2 1 1 2
PR103
PAD-OPEN 1x2m~D PU100
0.1U_0402_25V6 Peak Current 10.5 A
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
OCP Current 11.5 A
1
27P_0201_25V8
SY8288BRAC_QFN20_3X3-X
82P_0402_50V8J
0.1U_0402_25V6
2
1
1
RF@ PC100
RF@ PC103
RF@ PC131
PC133
PC134
PC105
PC104
IN4
IN3
IN2
IN1
BS
1
1
RF@ PC101
LX_3V 6 20 PL100
2
LX1 LX3 1.5UH_TMPC0624H-1R5MG-D_9A_20%
2
RF@ 2
LX_3V
100P_0402_50V8J
100P_0402_50V8J
7 19 1 2
GND1 LX2 +3.3V_ALWP
RF@
PR106 @EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
8 18 PR104
GND2 GND4
4.7_0805_5%
0_0201_5% short pad
9 17 LDO_3V 1 2
RF demand PG LDO +3.3V_ALW2
27P_0402_50V8J
PC106
PC107
PC108
PC109
PC110
PC129
PC161
PC162
100P_0402_50V8J
PC135
PC136
10 16 PR105
NC1 NC3
1
0_0201_5%
OUT
NC2
2
EN2
EN1
21 1 2 +3.3V_RTC_LDO @ @
FF
GND3
1 SNUB_3V
2
2
PR107
11
12
13
14
15
680P_0402_50V7K
RF@
RF@
100K_0201_5% 3.3V LDO 150mA~300mA
@EMI@ PC112
2 1 2 2
+3.3V_ALW
2
ENLDO_3V5V
PC111 Vout is 3.234V~3.366V
4.7U_0402_6.3V6M
2
ALW_PWRGD_3V_5V
JUMP@ PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0201_5% 1 2
3V5V_EN FB_3V 1 2 1 2 JUMP_43X118
short pad
+13.5VB JUMP@ PJP103
PR111 +5V_ALWP 1 2 +5V_ALW
JUMP@ PJP101 0_0603_5% PC114 1 2
1 2 +13.5VB_5V BST_5V 1 2 BST_5V_R 1 2 JUMP_43X118
PAD-OPEN 1x2m~D 0.1U_0402_25V6

10U_0603_25V6M
10U_0603_25V6M
PU102
2200P_0402_50V7K
27P_0201_25V8
82P_0402_50V8J
0.1U_0402_25V6
SYV828C1RAC_QFN20_3X3-X
RF@ PC115
RF@ PC116
RF@ PC132
PC139
PC140
PC117
PC118
1
1
RF@ PC141
IN4
IN3
IN2
IN1
BS
2
LX_5V 6 20 PL101
2
RF@ 2
LX LX2
100P_0402_50V8J
100P_0402_50V8J
1UH_PCMB062D-1R0MS_9A_20%
LX_5V
RF@
7 19 1 2 +5V_ALWP
3 GND1 LX1 3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7_0805_5%
8 18
GND2 GND3
@EMI@ PC125 @EMI@ PR112

9 17 1 2
RF demand PG VCC
100P_0402_50V8J
100P_0402_50V8J
PC120
PC121
PC122
PC123
PC124
PC130
PC163
PC164
PC137
PC138
SNUB_5V
1
10 16 PC119
NC1 NC2 2.2U_0402_6.3V6M
OUT
LDO
2
EN2
EN1
21
FF
RF@ 2
GND
680P_0402_50V7K
RF@
11
12
13
14
15
1
5V LDO 150mA~300mA
+5V_ALW2
2
ENLDO_3V5V
3V5V_EN
+5V_ALW
1
ALW_PWRGD_3V_5V
PC126
0.1U_0402_25V6
4.7U_0402_6.3V6M 5VALWP
2
EMI@ PC142
1 2
58,83> ALWON
TDC 7.8 A
1
PR114
499K_0201_1% Peak Current 8.15A
2
3V5V_EN
OCP Current 11.5 A
1M_0201_1%
1
1
PR116
PC127 PR117
PC128 1000P_0402_50V7K 1K_0201_5%
FB_5V 1 2 1 2
0.1U_0402_25V6
2
2
4 4
EN1 and EN2 dont't floating
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
A B C D E
5 4 3 2 1
D D
+13.5VB short pad
PR203 PC205
JUMP@ PJP202 0_0603_5% 0.1U_0402_25V6
1 2 +13.5VB_DDR BS_DDR1 2BS_DDR_R1 2
PAD-OPEN 1x2m~D
27P_0201_25V8
10U_0603_25V6M
10U_0603_25V6M
82P_0402_50V8J
100P_0201_25V8J
0.1U_0402_25V6
1
1
PC200
PC201
RF@ PC230
RF@ PC231
RF@ PC202
RF@ PC203
2
2
PU200
21
5
1
SY8310RAC_QFN20_3X3-X RF@
RF@ PR202 PC204
IN4
IN3
IN2
IN1
PAD
BS
4.7_0805_5% 680P_0402_50V7K
1 2 SNUB_DDR1 2
LX_DDR 6
LX LX2
20
+1.2V_DDRP
C PL201 C
7 19 LX_DDR 1 2
<58> 1.2V_MEM_PW RGD PG LX1
330P_0402_50V7K
0.68UH_TMPC0624H-R68MG-D_13A_20%
1
100K_0201_1%
8 18
GND GND1
PC208
PR204
HW request for 1.2V_PG PR250
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V
10U_0603_6.3V
2200P_0402_50V7K
100P_0402_50V8J
5.11_0402_1%
R1
EMI@
EMI@
9 17 1 2 +3.3V_ALW
2
S5 BIAS
1
PC210
PC211
PC212
PC213
PC214
PC223
2
4.7U_0402_6.3V6M
1
1
PC206
10 16
SIO_SLP_S4#_R
2
S3 ALERT
VTTSNS
VTTREF
1K_0201_5%
PR213
PC216
PC217
VDDQ
2
VTT
FB
2
0.6V_DDR_VTT_ON_R
short pad
11
12
13
14
15
PR208
VTTREF_DDR
0_0201_5%
1
FB_DDR
97.6K_0201_1%
1 2
<11,17,79,87> SIO_SLP_S4#
PR206
R2
1M_0201_5%
1
+1.2V_DDRP
100P_0402_50V8J
100P_0402_50V8J
@ PR209
PC224
PC225
2
1
+0.6VSP
2
RF@2
1U_0402_6.3V6K
22U_0603_6.3V6M
Down size resisitance
RF@
1
1
PC218
short pad
1
B B
PC219
1 2 PC209
<23> 0.6V_DDR_VTT_ON
2
22U_0603_6.3V6M
2
PR210
1M_0201_5%
1
0_0201_5%
+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT
PR212
JUMP@ PJP200 JUMP@ PJP201

JUMP_43X118 JUMP_43X39
1 2 1 2
2
1 2 1 2
CML V1 + DDR4 => 1.2V_MEN

CML V2 + LPDDR4X => 1.1V_MEN
+1.2V_MEM 0.6Volt +/- 5%
TDC 5.78A TDC 0.735A
Mode S3 S5 VOUT VTT Peak Current 8.26A Peak Current 1.05A
Normal H H on on
Stadby L H on off OCP Current 12A Fix by IC OCP Current 2A (fix)
Shutdown L L off off
Note: S3 - sleep ; S5 - power off
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
short pad
PR429 +3.3V_ALW
0_0201_5%
1 2
+13.5VB <6,17> CPU_C10_GATE#
1
JUMP@ PJP301
+13.5VB_1.05VALWP
1 2 @0@ PR425 @ PR404
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
100P_0402_50V8J
0_0402_5% 10K_0402_1%
82P_0201_50V8J
82P_0201_50V8J
10U_0603_25V6M
10U_0603_25V6M
short pad 1 2 0
PAD-OPEN 1x2m~D <9,11,17,66,79> SIO_SLP_S0# X X 0(LPM)
27P_0201_25V8
1
1
PC304 JUMP@ PJP302
PC317
PC318
PC301
PC305
PC306
+1.05V_PRIM
2
PR304 0.1U_0402_25V6 +1.05VALWP 1 2 SY8057BQDC 1 0 0 0.80
RF@ PC303
BST_1.05VALWP BST_1.05VALWP_R 1 2
1 2 1 2 JUMP@ PJP401
2
JUMP_43X118 short pad JUMP_43X79
0_0603_5% 1 2
1 0 1 0.95
RF@
RF@
RF@
PR402 +0.95VS_VCCIOP 1 2 +0.95VS_VCCIO 1 1 0 1.00
PU301 1 2
LPM_0.95VS_VCCIO
RF@ PR303 RF@ PC302 <17,58,59,78,87> RUN_ON
EN_0.95VS_VCCIO
4
1
SY8386RHC_QFN16_2P5X2P5-X 4.7_0805_5% 680P_0402_50V7K
1 2
SNUB_1.05VALWP
1 2 0_0201_5%
1 1 1 1.05
IN3
IN2
IN1
BS
1
0.1U_0402_25V6
@ PC402
PR403
LX_1.05VALWP
5 17 1M_0201_1% Follow CML
2
LX EP PL301
1UH_PCMB051H-1R0MS_8A_20%
(607109_CML_U_PDG_Rev0p7)
LX_1.05VALWP
+1.05VALWP
2
PR313 16 1 2 @ PL405
100K_0201_5% 6 LX2 PU401
13
14
15
16
17
3A_Z120_40M_0603_2P
330P_0402_50V7K
1 2 GND 1 2 SY8057DQDC_QFN16_3X3-X
+3.3V_ALW Vin=3~17V
100P_0402_50V8J
100P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
15
+1.0VS_VCCIO
EN
LP
PGND1
PGND2
TP
LX1
1
D D
PC307
RF@ PC315
RF@ PC316
<58> 1.05V_PRIM_PWRGD 7 JUMP@ PJP403 TDC 2.3 A
+3.3V_ALW
PC308
PC309
PC310
PC311
VIN_0.95VS_VCCIO
22.1K_0201_1%
1
PG 14 1 2 12 1
+0.95VS_VCCIOP Peak Current 3.3 A
2
GND1 PVIN2 OUT
PR306
VCC_1.05VALWP PAD-OPEN1x1m
PL402 OCP Current 6 A Fix by IC
10U_0603_6.3V
10U_0603_6.3V
1
8 13 1UH_1277AS-H-1R0N-P2_3.3A_30%
TEST VCC LX_0.95VS_VCCIO TYP MAX
1
PR308
+3.3V_ALW 11 2 1 2
+0.95VS_VCCIOP
PC403
PC404
2
PVIN1 LX1
1K_0201_5% Choke DCR 48.0mohm
ILMT
BYP
1
EN
FB
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
PC313
1
10 3
PC406
PC407
PC425
PC426
2.2U_0402_6.3V6M
10
11
12
2
SVIN LX2
PR312
SNUB_0.95VS_VCCIO
2
1
100P_0402_50V8J
22K_0201_1%
EN_1.05VALWP VID0_0.95VS_VCCIO
47P_0402_50V8J
1
1
0.1U_0402_25V6
1 2 PR311 9 4
PC408
PC405
+3.3V_ALW
PC409
<11,78,87> PCH_PRIM_EN VID0 PG
29.4K_0201_1% EMI@ PR405
1
PR414
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1
MODE
0.1U_0402_25V6
SGND
PR302 10K_0201_1% 4.7_0402_5%
PC360
PC312
PC314
RF demand
VID1
2
FBS
+3.3V_ALW 1M_0201_1%
EMI@
RF@
RF@
2
2
2
1
@0@
VID0_0.95VS_VCCIO
5
@0@ PR421
1
1
EMI@ PC401
FBS_0.95VS_VCCIO
0_0201_5%
SS_0.95VS_VCCIO
VID1_0.95VS_VCCIO
PR307
VID1_0.95VS_VCCIO
0_0201_5% 470P_0402_50V7K Not to change short pad
2
<58>
FB_1.05VALWP
2
0.95VS_VCCIO_PWRGD
LIMIT_1.05VALWP
PR415
1
10K_0201_1% HW request for VCCIO_PG
@0@ short pad PR427 1 2
2
1
0_0201_5% VCCIO_SENSE <17>

PR310 PR422
0_0201_5%
0_0201_5% +1.0V_PRIM
2
1 2
TDC 3..3A VSSIO_SENSE <17>
2
PR412
Peak Current 4.7A 0_0201_5%
OCP Current 8 A Fix by IC
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
The current limit is set to 6A, 8A or 10A when this pin
is pull low, floating or pull high
short pad
+1.8V_PRIM
TDC 0.5 A PR430
0_0201_5% +3.3V_ALW
Peak Current 0.72 A <9> VR_LPM_R#
1 2
OCP Current 3.2 A f i x by I C
1
@ PR410
10K_0402_1%
2
C @ PL502 C
22U_0603_6.3V6M
3A_Z120_40M_0603_2P
1
1 2 JUMP@ PJP502
PC530
1 2
+1.8VALWP +1.8V_PRIM LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
2
JUMP@ PJP402
PAD-OPEN1x1m 0 X X 0.75(LPM)
LPM_1.05V_PRIM_CORE
JUMP@ PJP501 JUMP_43X79
VIN_1.8VALW
EN_1.05V_PRIM_CORE
1 2 PR406 1 2
+3.3V_ALW 1 2 +1.05V_PRIM_COREP 1 2 +1.05V_PRIM_CORE 1 0 0 0.9
Imax= 2A, Ipeak= 3A <11,78,87> PCH_PRIM_EN SY8057CQDC
PAD-OPEN1x1m
FB=0.6V 22K_0201_1%
1 0 1 0.95
1
0.1U_0402_25V6
1 1 0 1.00
PC411
@ PR407
PU501
PL501 1M_0201_1%
1 1 1 1.05
2
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_1.8VALW @ PL406
PR314 4 3 1 2
+1.8VALWP
2
0_0201_5% IN LX
1.05V_PRIM_PWRGD PG_1.8VALW 3A_Z120_40M_0603_2P PU402
1
1 2 5 2 1 2
13
14
15
16
17
Follow CML
68P_0402_50V8J
PG GND SY8057FQDC_QFN16_3X3
Vin=3~17V
1
22U_0603_6.3V6M
22U_0603_6.3V6M
6 1 (607109_CML_U_PDG_Rev0p7)
PC503
EN
LP
PGND1
PGND2
TP
FB EN
1
1
PR502
PC501
PC504
1SNUB_1.8VALW
short pad 4.7_0402_5% PR501 JUMP@ PJP404

VIN_1.05V_PRIM_CORE
2
SY8002IABC SOT23 6P PWM

PR504
+3.3V_ALW 1 2 12 1
+1.05V_PRIM_COREP
2
2
0_0201_5% RF@ 20K_0201_1% PVIN2 OUT
EN_1.8VALW
<11,78,87> PCH_PRIM_EN 1 2
Rup +3.3V_ALW PL404
2
10U_0603_6.3V
10U_0603_6.3V
1UH_1277AS-H-1R0N-P2_3.3A_30%
PAD-OPEN1x1m LX_1.05V_PRIM_CORE
1
11 2 1 2
+1.05V_PRIM_COREP
PC412
PC413
RF@ PC506 PVIN1 LX1
1
@ PC505
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
680P_0402_50V7K
2
1
.1U_0402_16V7K 10 3
PC424
PC415
PC427
PC428
2
SVIN LX2
FB_1.8VALW
1SNUB_1.05V_PRIM_CORE
2
RF@
1
100P_0402_50V8J
2200P_0402_50V7K
9 4 PR409
47P_0402_50V8J
VID0 PG
1
1
0.1U_0402_25V6
4.7_0402_5%
+1.0V_PRIM_CORE
PC417
PC416
VID0_1.05V_PRIM_CORE
PC418
PC414
PR417 PR418 short pad
Rdown TDC 2.23 A
MODE
1
SGND
PR506 10K_0201_1% 10K_0201_1%
VID1
2
FBS
10K_0201_1% PR315
Note: VID0_1.05V_PRIM_CORE Peak Current 3.2A
2
0_0201_5%
EMI@
EMI@
RF@
RF@
2
When design Vin=5V, please stuff snubber VID1_1.05V_PRIM_CORE OCP Current 6.8 A Fix by IC
5
to prevent Vin damage TYP MAX
2
RF@ PC419
VID1_1.05V_PRIM_CORE
SS_1.05V_PRIM_CORE
Choke DCR 48.0mohm
FBS_1.05V_PRIM_CORE
1.05V_PRIM_PWRGD
680P_0402_50V7K
2
@0@ PR408
0_0201_5%
Vout=0.6V* (1+Rup/Rdown) 1 2
<18> CORE_VID0
@0@ PR411 short pad

0_0201_5% PR423
1 2 1 2
+1.2V_RUN <18> CORE_VID1
TDC 0.34A 0_0201_5%
1M_0201_1%
Peak Current 0.49 A
@ PR428
JUMP@
OCP Current 1.3A f i x by I C
PJP503
2
B B
VIN_1.2V_RUN
2 1
+3.3V_ALW
PAD-OPEN1x1m
4.7U_0402_6.3V6M
JUMP@
PU502
1
PC508
PJP504
9
GND2 VOUT_1.2V_RUN
1 1 2
2
OUT +1.2V_RUN
1
8
IN 2
NC1 PAD-OPEN1x1m
1
7
NC3 ADJ_1.2V_RUN
3
6 ADJ/NC PR512
PR511
2
NC2
1
0.01UF_0402_25V7K
4
EN_1.2V_RUN GND1 PC511
1 2 5 5.1K_0402_1%
PC509
<17,58,59,78,87> RUN_ON EN 22U_0603_6.3V6M

2
100K_0201_5%
EM1109V-AD_DFN3308-8_3X3-X
1
PR509 PC510
1
1M_0201_1%
2
0.1U_0402_25V6
PR510
2
10.2K_0402_1%
2
2.5V_MEM
TDC 0.645A by power budget
EM1109BV-AJ Pd limit=1.7W
Peak loading=0.921A.
Pd=(3.3-2.5)*0.921=0.7368W < 1.7W
OCP Current 1.3 A f i x by I C
JUMP@ PJP505
VIN_2.5V_MEM
1 2
+3.3V_ALW
CML V1 + DDR4 => 2.5V_MEN
4.7U_0402_6.3V6M
PAD-OPEN1x1m
1
CML V2 + LPDDR4X => 1.8V_MEN

PC514
PU503
2
9 JUMP@ PJP506
GND2 VOUT_2.5V_MEM
1 1 2
8 VO +2.5V_MEM
1
VIN 2
NC1 PAD-OPEN1x1m
1
7
<58> 2.5V_MEM_PWRGD PG 3 PR515 PC515
A PR513 6 ADJ/NC 21.5K_0402_1% 680P_0402_50V7K A
2
NC2
1
0_0201_5% 4
EN_2.5V_MEM PC516
2
1 2 5 GND1
<11,17,79,86> SIO_SLP_S4# EN 22U_0603_6.3V6M
ADJ_2.5V_MEM
2
EM1109BV-AJ_DFN8_3X3-X
1
short pad @ PC513

.1U_0402_16V7K
2
PR516
10K_0402_1%
2
Title
+1VALWP/VCCIO/PRIM_CORE/1.8V/2.5V_MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCST
short pad
PR602
VCC_SA U42
0.1U_0402_25V6
1
1
TDC 4.0A
100_0402_1%
75_0402_1%
0_0402_5%
1
45.3_0402_1%
PC602
PR605
1 2
@ PR604
+5V_ALW Peak Current 6A
PR601
OCP current 12A
2
PR618
Choke DCR 13 m ohm
2
2
49.9_0402_1% 1 2
1 2 +13.5VB_CPU
4.7U_0402_6.3V6M
<15> VIDSCLK
1U_0402_25V6K
short pad PR603
1
0_0402_5%
PC603
PC604
PJP603
<15> VIDALERT_N PR625 1 2 0_0402_5%
1 2
+13.5VB_VCCSA +13.5VB
2
D PR678 <15> VIDSOUT 1 2 D
<14,44,58,84> PROCHOT#
100_0402_1% PR626 10_0402_1% PAD-OPEN1x1m
1 2 1 2 JUMP@
PC605 47P_0402_50V8J PR612 1.91K_0402_1%
+3.3V_RUN 1 2
SVID_ALERT#_PWR_CPU
VR_ENABLE_CPU_CORE
1 2
VR_READY_CPU_CORE
+13.5VB_VCCSA
VR_HOT#_CPU_CORE
1 2
SVID_DAT_PWR_CPU
SVID_CLK_PWR_CPU
<11,96> PCH_PWROK
PROG2_CPU_CORE
PROG1_CPU_CORE
PR614 0_0402_5% PR608
VIN_CPU_CORE
VCC_CPU_CORE
100K_0402_5%
PH601 near PU610 MOS Side <59,96> IMVP_VR_ON
1 2
PR616 0_0402_5% 1 2
PH601
10U_0603_25V6M
10U_0603_25V6M
82P_0201_50V8J
PR610
470K_0402_5%_B25/50 4700K
27P_0201_25V8
BOM structure PR620 PR611
10K_0402_1%
1
PC612
PC608
PC609
PC610
1 2 1 2 U42@ PR613 0_0402_5% short pad
9.31K_0402_1%
97.6K_0402_1% 1 2short pad
<58,84,96> I_SYS
1 2 1 2
2
PR631 PC613 PR693
PU602
PSYS_CPU_CORE
RF@
RF@
27.4K_0402_1% 330P_0402_50V7K 11.8K_0402_1%
40
39
38
37
36
35
34
33
32
31
1 2 1 2 ISL95857CHRTZ_TQFN40_5X5~D-X
PC614 PR617 Low noise MLCC
VR_ENABLE
VR_READY
SCLK
SDA
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
2200P_0402_50V7K 4.3K_0402_1% UG_SA
1 2 1 2 PSYS R on CPU site
PWM_C_SA
0.22U_0402_25V6K
U42@ PC616 30 PR619 2.2_0603_5%
BOM structure 68P_0402_50V8J BOM structure BOM structure 1 PWM_C BST_SA_R 1 2
1 2 U42@ PC617 U42@ PR621 PSYS 29 FCCM_C_SA
FCCM_C PU614
1
316_0402_1% IMON_B_IA
PC611
1200P_0402_50V7K 2
IMON_B
1
1 2 1 2 28 ISUMN_C_SA ISL95808HRZ-TS2778_DFN8_2X2~D PQ614
<15> VCC_SENSE_IA
U42@ PR622 NTC_B_IA 3 ISUMN_C EMB09A03VP 2N EDFN3X3-8 +VCC_SA
D1_3
D1_2
D1_1
G1
2
@ PC618 2.49K_0402_1% NTC_B 27 1 8
COMP_B_IA ISUMP_C UGATE PHASE PL614
0.082U_0402_16V7K
1 2 1 2 4
COMP_B BST_SA FCCM_SA10 9 LX_SA
@ PC620
26 2 7 4 1
RTN_C BOOT FCCM D1 D2/S1
1
330P_0402_50V7K BOM structure FB_B_IA 5

PC621 PR623 FB_B 25 FB_C_SA PWM_SA3 6 3 2
S2_1
S2_2
S2_3
C
PC619 1000P_0402_50V7K 2K_0402_1% 6 FB_C short pad PWM VCC C
G2
2
RTN_B
1
COMP_C_SA LG_SA
4.7_1206_5%
1 2 1 2 1 2 24 4 5
COMP_C GND LGATE 0.47UH_MMD05ABHR47MET1_7A_20%
RF@ PR627
7 PR606
TP
8
0.01UF_0402_25V7K ISUMP_B 23 IMON_C_SA
IMON_C 0_0201_5%
ISUMN_B_IA
3.65K_0603_1%
8 short pad
<15> VSS_SENSE_IA
9
ISUMN_B
1
22 PR699
PWM_C_SA 2
2
PWM_A
PR624
9 0_0603_5% short pad
ISUMN_SA
Local sense put on HW site ISEN1_B 21 1 2
1SNUB_SA
10 FCCM_A PR679
ISUMN_A
ISUMP_A
PWM1_B
PWM2_B
COMP_A
ISEN2_B
FCCM_B
680P_0402_50V7K
1
IMON_A
0_0201_5%
4.7U_0402_6.3V6M
+5V_ALW
NTC_A
RTN_A
<89> ISUMP_IA
ISUMP_SA 2
FB_A
FCCM_C_SA 2
4.99K_0402_1%
RF@ PC622
41
PC685
AGND
1
2
BOM structure
<89>
U42@ PR628
FCCM_A_GT
@ PC624 BOM structure
U42@ PC626 BOM structure
@ PR658
11
12
13
14
15
16
17
18
19
20
20M_0402_5%
2
<89>
PWM_A_GT
0.022U_0402_16V7K
0.1U_0402_25V6
<89> FCCM_B_IA
FB_A_GT
ISUMN_A_GT
NTC_A_GT
COMP_A_GT
IMON_A_GT
2
11K_0402_1%
<89> PWM1_B_IA
1
1
33P_0402_50V8J
2.49K_0402_1%
PR633
10K_0402_5%_B25/50 4250K
PR630
<89> PWM2_B_IA
4700P_0402_25V7K
PR632 PC627
PH603 near PU612 MOS Side
2
2
1
PH602 near PL610 Choke Side
2200P_0402_50V7K
PC628
1K_0402_1%
2
ISUMP_SA
1K_0402_1% 2200P_0402_50V7K
PH602
1 2 1 2
2
PC625 1 2
U42@ PR638 BOM structure 330P_0402_50V7K
2.61K_0402_1%
1
1
523_0402_1% 1 2 PR636 1.78K_0402_1%
2
PC631
1 2 1 2
PR642
<89> ISUMN_IA
1
PC630
1 2 1 2
PR629
2
365_0402_1%
10KB_0402_5%
U42@ PC635 86.6K_0402_1% PR635
1
0.022U_0402_16V7K 1 2 10K_0402_1% PC632 PR641
2
1
ISEN1_IA
11K_0402_1%
PR640
1 2 1000P_0402_50V7K 1K_0402_1%
3300P_0402_25V7K
0.015U_0402_25V7K
PR643
1
1
PC637
1
PR644
PC633
U42@ PC638 PH603
1
B 0.022U_0402_16V7K 470K_0402_5%_B25/50 4700K PR646 PC640 B
2
1 2 ISEN2_IA 1 2 1 2 1 2
PH604
U22@ PR634 PR647 316_0402_1% 2200P_0402_50V7K
330P_0402_50V7K
0_0402_5% 27.4K_0402_1%
PR649
2
48.7K_0402_1%
.1U_0402_16V7K
1 2 1 2
1
1
1 2
+5V_ALW
1
ISUMN_SA
PC641
PC643
PR651
1 2
<89> ISEN1_IA
PC629 PR639 PC644
2
2.05K_0402_1%
2K_0402_1%
<89> ISEN2_IA U22@ PR615 2200P_0402_50V7K 3.09K_0402_1% .1U_0402_16V7K PH604 near PL614 Choke Side
PR652
0_0402_5% 1 2 1 2 1 2
2
PC642
PC636 0.068U_0402_16V7K
33P_0402_50V8J 1 2
1 2
680P_0402_50V7K
1 2 @
VSS_SENSE_SA <17>
.1U_0402_16V7K
PC601
1
@ PC646
2
0.022U_0402_16V7K
PC645
PC639 PR645
1500P_0402_50V7K 316_0402_1% 1 2 PC649
2
1 2 1 2 @ 0.01UF_0402_25V7K
1 2
PR656
11K_0402_1%
1
1 2 1 2
2K_0402_1%
PR648 @ PC650 @ PC652

1
1.91K_0402_1% PR657 0.082U_0402_16V7K
2
330P_0402_50V7K
<16> VCC_SENSE_GT PH605
4.42K_0402_1% 1 2
PR650
Local sense put on HW site 1 2 1 2

PH605 near PL612 Choke Side
@ PC651
1 2
0.082U_0402_16V7K
1 2
10K_0402_5%_B25/50 4250K VCC_SENSE_SA <17>
680P_0402_50V7K
@ PC653
PC647
@ PR653
1
330P_0402_50V7K 2 1 ISUMN_GT <89>

20M_0402_5%
2
A A
2
PC654
ISUMP_GT <89>
1 2
0.01UF_0402_25V7K
<16> VSS_SENSE_GT DELL CONFIDENTIAL/PROPRIETARY
Title
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-J261P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, March 27, 2020 Sheet 88 of 106
5 4 3 2 1
5 4 3 2 1
JUMP@
PJP601
+13.5VB
1 2
PAD-OPEN 4x4m
VCC_core (U42)
+13.5VB_CPU TDC 48A
@EMI@ PL602
1 2
Peak Current 70A
OCP current 85A
RF@
RF@
RF@
RF@
9A Z80 10M 1812_2P
Choke DCR 0.88 +-5%m ohm
100U_D2_20VM_R100M
100U_D2_20VM_R100M
27P_0201_25V8
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
82P_0201_50V8J
1 1
0.1U_0402_25V6
2200P_0402_50V7K
1
1
+ +
PC682
PC656
PC657
PC658
PC606
PC607
1
1
PC659
PC660
PC689
PC690
D Follow as below D
CML PDG U42 15W/Power Map document

2
2
2 2
607109_CML_U_PowerMap_Rev1p1
2
Low noise MLCC
PL610
PU610
10 11 LX1_IA 4 1
9 PGND1
VIN2
SW1
SW2
12 +VCC_CORE
3 2
8 13
ISEN1P_IA
ISEN1N_IA
0.1U_0402_25V6
VIN1 GL1
1
PC655
BST1_IA_R
4.7_1206_5%
1
1
1 2 7 14 +5V_ALW 0.15UH_MMD06BDER15MEM_27A_20%
PC686
6 PHASE PGND2 15 PR667 PR666
RF@ PR663
0.22U_0402_25V6K NC1 PVCC 3.65K_0603_1% U42@ PR668 10_0402_1%
2
1 2 BST1_IA 5 16 1 2 1 2
4.7U_0402_6.3V6M
2
4 BOOT NC2 17 100K_0402_1%
PR660
2
AGND1 NC3
PC661
3.9_0603_1%
VCC1_IA 3
SNUB1_IA
FCCM1_IA 2 VCC 19 <88> ISEN1_IA
2
PR688 PWM1_IA 1 FCCM GL2 18
1_0603_5% PWM AGND2
ISEN2N_IA
VCC_GT (U42)
1 2 AOZ5038QI-05_PQFN31_5X5 1 2
TDC 22A
680P_0402_50V7K
@ PR670 Peak Current 31A
RF@ PC662
+5V_ALW +13.5VB_VCCGT
<88,89>
4.7U_0402_6.3V6M
ISUMP_IA
<88,89>
ISUMN_IA
100K_0402_1%
OCP current 37.2A
1
1
PC676
C C
Choke DCR 0.88 +-5%m ohm
2
27P_0201_25V8
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
82P_0201_50V8J
0.1U_0402_25V6
2200P_0402_50V7K
short pad
1
PR659 PJP602
PC675
PC674
PC664
PC665
PC666
PC667
PC691
PC692
0_0201_5% 1 2
<88,89> FCCM_B_IA 1 2 +13.5VB_VCCGT +13.5VB_CPU
2
PAD-OPEN 1x2m~D
PR687
RF@
RF@
RF@
RF@
JUMP@
0_0201_5%
1 2 Low noise MLCC
<88> PWM1_B_IA
RF demand
@EMI@ PR669 @EMI@ PC670

4.7_1206_5% 680P_0402_50V7K
1 2 SNUB_GT 1 2
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
U42@ PC683
U42@ PC684
U42@ PC672
U42@ PC673
1
PU612
PL612 +VCC_GT
2
Low noise MLCC 10 11 LX_GT 4 1

9 PGND1 SW1 12
VIN2 SW2 3 2
8 13 short pad
0.1U_0402_25V6
U42@ VIN1 GL1 PR698 0.15UH_MMD06BDER15MEM_27A_20%
PC663
BST_GT_R
+5V_ALW
1
1 2 7 14 0_0603_5%
PC687
PL613 PHASE PGND2 PR661
U42@ PU613 6 15 1 2
10 11 LX2_IA 4 1 0.22U_0402_25V6K NC1 PVCC 3.65K_0603_1%
+VCC_CORE
2
9 PGND1 SW1 12 1 2 BST_GT 5 16
4.7U_0402_6.3V6M
VIN2 SW2 3 2 4 BOOT NC2 17
PR665
2
AGND1 NC3
1
8 13
PC668
3.9_0603_1%
4.7_1206_5%
ISEN2P_IA
VIN1 GL1
1
<88>
<88>
ISEN2N_IA VCC_GT
ISUMP_GT
ISUMN_GT
U42@ PC671 0.15UH_MMD06BDER15MEM_27A_20% 3
BST2_IA_R
B B
0.1U_0402_25V6
+5V_ALW VCC
1
1 2 7 14 FCCM_GT 2 19
U42@ PC688
RF@U42@ PR676
2
PHASE PGND2 FCCM GL2
1
6 15 U42@ PR674 U42@ PR675 U42@ PR673 PWM_GT 1 18

0.22U_0402_25V6K NC1 PVCC 3.65K_0603_1% PR680 PWM AGND2
10_0402_1%
1 2 BST2_IA 5 16 1 2 1 2 1_0603_5% AOZ5038QI-05_PQFN31_5X5
4.7U_0402_6.3V6M
2
U42@ PR672 4 BOOT NC2 17 100K_0402_1% 1 2

+5V_ALW
2
AGND1 NC3
1
U42@ PC697
3.9_0603_1% VCC2_IA <88> ISEN2_IA

3
4.7U_0402_6.3V6M
SNUB2_IA
FCCM2_IA 2 VCC 19 @ PR677

2
FCCM GL2
1
PWM2_IA 1 18 ISEN1N_IA 1 2
PC669
PWM AGND2 100K_0402_1%
U42@ PR691 AOZ5038QI-05_PQFN31_5X5
2
1_0603_5%
1 2
+5V_ALW
<88,89>
ISUMN_IA
<88,89>
ISUMP_IA
short pad
680P_0402_50V7K
4.7U_0402_6.3V6M
1
PR662
U42@ PC677
RF@U42@ PC678
0_0201_5%
1 2
<88> FCCM_A_GT
2
PR664
0_0201_5%
short pad 1 2
<88> PWM_A_GT
PR671
0_0201_5%
<88,89> FCCM_B_IA
1 2
PR692
0_0201_5%
<88> PWM2_B_IA
1 2
A A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL CPU_CORE
5 4 3 2 1
A
+VCC_CORE
2 1 2 1 2 1 2 1
1
5
5
+
PC1091 PC1071 PC1041 PC1031 PC1000
470U_D2_2VM_R4.5M 47U_0603_6.3V6M 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
1
+
PC1092 PC1072 PC1042 PC1032 PC1001
2 1 2 1 2 1 2 1
1
+
PC1093 PC1073 PC1043 PC1033 PC1002
2 1 2 1 2 1 2 1
1
+
PC1094 PC1074 PC1044 PC1034 PC1003
2 1 2 1 2 1 2 1
1
+
PC1095 PC1075 PC1045 PC1035 PC1004
2 1 2 1 2 1 2 1
PC1076 PC1046 PC1036 PC1005

47U_0603_6.3V6M 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
RF@ PC1096 PC1077 PC1047 PC1037 PC1006

100P_0201_25V8J 47U_0603_6.3V6M 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
RF@ PC1097 PC1048 PC1038 PC1007

100P_0201_25V8J 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
RF@ PC1098 PC1049 PC1039 PC1008

27P_0201_25V8 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M 22U_0603_6.3V6M
4
4
2 1 2 1 2 1 2 1
RF@ PC1099 PC1050 PC1040 PC1009

82P_0201_50V8J 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
RF demand
RF@ PC1180 PC1051

27P_0201_25V8 2.2U_0201_6.3V6M
2 1
RF@ PC1181
27P_0201_25V8
2 1
470u_D2
220u_D7
47U_0603
2.2U_0201
22U_0603
+VCC_CORE
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Place on CPU:
*21 pcs
*7 pcs
*3 pcs
*10 pcs
*2pcs
3
3
+VCC_GT
+VCC_SA
2 1 2 1 2 1
2
1
+
PC1142 PC1131 PC1116 PC1101

330U_D3_2.5VY_R6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2 1 2 1
2
1
+
PC1143 PC1132 PC1117 PC1102

RF@ PC1166 PC1151 330U_D3_2.5VY_R6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
100P_0201_25V8J 22U_0603_6.3V6M 2 1 2 1 2 1
2 1 2 1
PC1133 PC1118 PC1103
2
2
RF@ PC1167 PC1152 2 1 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
100P_0201_25V8J 22U_0603_6.3V6M 2 1 2 1 2 1
RF demand
2 1 RF@ PC1146
100P_0201_25V8J PC1134 PC1119 PC1104
RF@ PC1168 PC1153 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
27P_0201_25V8 22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1 2 1
RF@ PC1147 PC1135 PC1120 PC1105
RF@ PC1169 PC1154 100P_0201_25V8J 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
RF demand
82P_0201_50V8J 22U_0603_6.3V6M 2 1 2 1 2 1
2 1 2 1 RF@ PC1148
27P_0201_25V8 PC1136 PC1121 PC1106
PC1155 2 1 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1
2 1 RF@ PC1149
82P_0201_50V8J PC1137 PC1122 PC1107

Date:
Size
Title
PC1156 2 1 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

22U_0603_6.3V6M 2 1 2 1 2 1
2 1
PC1138 PC1123 PC1108
Friday, March 27, 2020
Document Number
PC1157 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

22U_0603
+VCC_SA Place on CPU:
22U_0603_6.3V6M 2 1 2 1
2 1
PC1139 PC1109
PC1158 1U_0201_6.3V6M 22U_0603_6.3V6M

330u_D3
1U_0201
22U_0603
+VCC_GT Place on CPU:
22U_0603_6.3V6M 2 1 2 1
CPU Decoupling CAP
2 1
PC1140 PC1110
LA-J261P
PC1159 1U_0201_6.3V6M 22U_0603_6.3V6M

22U_0603_6.3V6M 2 1 2 1
2 1
*13 pcs
PC1141 PC1111
PC1160 1U_0201_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1
2 1
1
1
*2 pcs
*23 pcs
*11 pcs
PC1112
Sheet
PC1161 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1
2 1
PC1113
PC1162 22U_0603_6.3V6M
90
22U_0603_6.3V6M 2 1
2 1
PC1114
of
PC1163 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1
PC1115
106
22U_0603_6.3V6M
R ev
1.0
D
5 4 3 2 1
D D
C C
Reserve
B B
A A
Title
Reserve for PWR
1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Reserve for PWR
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
Title
Reserve for PWR
1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
Title
Reserve for PWR
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-J261P
5 4 3 2 1
5 4 3 2 1
D D
short pad PC3002

PR3006 0.01UF 25V +-10% X7R 0402
1 2 1 2
+3.3V_VDD
0_0402_5%
AZV3001
PR3002 Icc=9uA_max
200K _0201_1%
1 2 Vout=3.15V@Vcc=3.3V and Io=3mA short pad
Vf 1.4619V-1.4918V-1.5216V RB520SM
PR3003 PR3001
165K_0201_1%
Vf =0.29V@1mA 0_0201_5%
1 2 PU3000 Ir =1uA @Vr=10V 1 2
ACIN_CHG <84>
1
G1361A52U ADFN1X1.45 6P OP PD3001
place on BOT side @ PC3001
6
C 82P_0201_50V8J C
6
1 2 short pad
short pad PQ3003 PR3019
2
AOSS21311C 1P SOT23-3 4 0_0402_5%
PR3022 1 1 2 NO_SMOKE_OVP 2
OVP_alert
S
D
<59,88> IMVP_VR_ON 1 2 3 1 1 2 3
PJX138K_SOT563-6
1U_0402_6.3V6K
1
0_0402_5% PR3020 PQ3000A
1
10K_0402_1%
PC3008
G
0.1U_0402_10V7K
2
1
1
PR3013
1
200K_0402_1%
5.1K_0201_1%
1U_0402_6.3V6K
2
1
1
PR3030
PC3003
PR3015
@ PC3036
@ PR3021 100K_0402_1%
0_0402_5%
2
2
2
2
2
@ PR3004
200K_0402_1%
PC3035 1 2
I_SYS
<58,84,88>
+VCC_CORE
0.22U_0402_25V6K
1
1 2 @ PR3005
PR3018 100K_0402_1%
1K_0201_1% 1 2
5
@ PC3037
2
82P_0201_50V8J
1 2
4 3
<11,88> PCH_PWROK
PQ3000B
PJX138K_SOT563-6
B B
Remove Charger UVP function
A A
Title
VCORE_OVP
1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
Title
Reserve for PWR
1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
Title
Reserve for PWR
1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
D D
U22
Location U42 [2phase] U62 [2phase]
PC626 U22@ PR613 U22@ PR621 U22@ PR628 U22@ PC624 @U22@
PC626 V 0.1U V 0.1U
PR613 V 97.6K V 97.6K
0.047U_0402_25V7K 84.5K_0402_1% 316_0402_1% 4.99K_0402_1% 0.022U_0402_16V7K
PR621 V 316 V 316
PR638 U22@ PR622 U22@ PC616 U22@ PC617 U22@
PR628 V 4.99K V 4.99K
PR638 V 523 V 523
422_0402_1% 1.65K_0402_1% 33P_0402_50V8J 1200P_0402_50V7K
PR622 V 2.49K V 2.49K
PC616 V 68P V 68P
C
PC617 V 1200P V 1200P C
PC624 V 0.022U V 0.022U
B B
A A
Title
Reserve for PWR
1.0
LA-J261P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Item Page# Date Issue Solution Rev.
Description Description
PR3022 change to SD028000080 (0_0402_5%)

PC3003 change to SE000000K80 (1U_0402_6.3V6K)
X01
1 P096 8/2 Fine tune OVP protect circuit for more budget PR3020 change to SD034100280 (10K_0402_1%)
PR3003 change to SD034120380 (120K_0402_1%)
Add PR3006_0_ohm for study
In order to reduce power consumption Change PR56/PR846/PR45/PR855 from 10k to 100k

2 P082 8/8 (SD043100380 100K_0201_5%). X01
+1.2V_MEN f i ne t ur n t o 1. 23V
3 P086 9/17 Modify VDDQ FB pin resistor get more buffer for VRAM damage issue PR204 change to 105K X01
D D
PR206 change to 100K
4 RTC Power rail swap for AC mode supply source
P083 8/2 Swap PD3.1(+3.3V_TBAT_LDO) and PD5(+3.3VV_RTC_LDO) power rail X01
Tune 3V/5V power bring up sequence PR114 change to 499K_0201_1%

5 P083 8/9 to meet tPCH04 timing from VCCRTC to VCCDSW. X01
PC128 change to 0.1U_0402_25V
Roll back to Gen10 solut i on

6 Gen11 power path circuit have risk trigger LPS function depop: PR50/PR867
P082 9/18 pop:PQ1/PQ5/PR51/PR25/PR17/PR15/PR10/PQ806/PQ805 X01
/PR868/PR820/PR813/PR808/PR802
7 Charger vendor suggest change, Add PC790 for MLCC DC-Bias margin
P084 9/19 From Fiorano EVT peer view B+ no power issue Stuff PC745 for ripple voltage and surge voltage solution X01
PC624 change to unstuff

8 P088 9/9 Vendor request to tune R/C value by intel VRTT test result PC621 change to 1nF X01
PC646 change to unstuff
9 Stuff: PC746/PC747/PR717/PR718/PC711/PC712/PC713/PC714/PC816
All 8/2 EMI request PC704 change to 4.7ohm X01
10 Single N-channel MOS change to 2nd source PQ14/PQ15/PQ4001/PQ703/PQ812 change from

P082 8/26 because material shortage SB00000VD00 (DMN55D0UT) to SB00001KM00 (PJE138K) X01
11
P084 9/9 Charger choke change to H=2.4 for improve thermal PL701 change to SH00001Z200 (MMD-10BDN1R0M-R2L) X01
12 P084 10/14 Vender command VSYS_CHG funct i on can r es erve t he bypass cap PC745 change to un-stuff X02
Add PR86 (1M_0201_1%) to GND on PU800A output

13 Add PR870 (1M_0201_1%) to GND on PU800B output
10/16 Sometimes didn't charge when IE/BME attached to SUT issue-BITS428383 X02
P082 Add PR85 ,PR869 (47K_0201_1%) pull high to +3.3V_VDD
PR55 / PR835 change to un-stuff
C
PC4003 unstuff C
PR4011 change to 3M
14 10/17 Fine tune advance storage wake up sequence PR4017 and PR4007 change to 1M_0402_1%
P083 X02
PR4006 change to 1M
PC4001 change to 1U
15 P083 10/31 Reserve R/C simplify solution add discharge diode circuit Add PR4023/PC4004/PD4004 X02
Vender suggestion reserve for get more DC-bias budget

16 P084 11/11 Vender command VSYS_CHG function can reserve the bypass cap PC790 change to unstuff X02
1.PQ614 change from AONH36334 to EMB09A03VP

17 P088 11/15 For DIDT system ESD HBM < 500 fail issue 2.PQ5 / PQ11 / PQ803 / PQ805 / PQ3003 change from AO3409 to AOSS21311C X02
18 PD1 / PD2 change to SCA00004700 (CEST523NC5VB)

P083 11/27 ESD team request X02
19 P083 1/15 Change owner from EE to PWR Add QE31 / RE853 / CE399 A00
20 Un-stuff PR4017 / PQ4002 / PR4013 / PQ4003 / PC4004 /

P083 2/6 One shut use IC control A00
PR4023 / PD4004 / PC4002 / PD4003 / PR4009 / PR4008
21
22
23
24
B B
25
26
27
A A
Doc = LA-J261P
Title
PWR P.I.R
1.0

5 4 3 2 1
5 4 3 2 1

16
D D
17
18
19
20
21
22
23
C C
24
25
26
27
B B
28
29
30
A A
Doc = LA-J261P
Title
PWR P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0

5 4 3 2 1
5 4 3 2 1

16
D D
17
18
19
20
21
22
23
C C
24
25
26
27
B B
28
29
30
A A
Doc = LA-J261P
Title
PWR P.I.R

5 4 3 2 1
5 4 3 2 1
WLAN option AX201 EC option X76 DRAM Option DRAM Config Option
(Resistor pop location)
MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3 MEM_CONFIG4
AX@ WL1 5107NES@ UE1
Micron 4GB/2666(Channel A only)
RC710 RC711 UD1 UD2 UD3 UD4 RC393 RC394 RC395 RC396 RC392
AX@ AX@ M4G@ M4G@ M4G@ M4G@ M4G@ M4G@ M4G@ M4G@ M4G@
SD00000LF80 SD00000LF80 SA0000ARD2L SA0000ARD2L SA0000ARD2L SA0000ARD2L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
22_0201_5% 22_0201_5%
AX201.D2W MEC5107KD4LJTR_WFBGA176
D PK29S00AY1L SA0000CQ740
Micron 4GB/2666(Channel A only) D
X7688431L03 UD1 UD2 UD3 UD4 RC393 RC394 RC395 RC391 RC392
M4GN@ M4GN@ M4GN@ M4GN@ M4GN@ M4GN@ M4GN@ M4GN@ M4GN@
SA0000CMS1L SA0000CMS1L SA0000CMS1L SA0000CMS1L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
SA0000CQ740 : Non-ES, signed (SimilarX10 MEC5106)
Micron 8GB/2666
UD1 UD2 UD3 UD4 UD5 UD6 UD7 UD8 RC393 RC394 RC390 RC396 RC392
M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@
SA0000ARD2L SA0000ARD2L SA0000ARD2L SA0000ARD2L SA0000ARD2L SA0000ARD2L SA0000ARD2L SA0000ARD2L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
WLAN option AX201(N)
Micron 8GB/2666
AXN@ WL1 X7688431L06 UD1 UD2 UD3 UD4 UD5 UD6 UD7 UD8 RC393 RC394 RC390 RC391 RC392
M8GN@ M8GN@ M8GN@ M8GN@ M8GN@ M8GN@ M8GN@ M8GN@ M8GN@ M8GN@ M8GN@ M8GN@ M8GN@
RC710 RC711 SA0000CMS1L SA0000CMS1L SA0000CMS1L SA0000CMS1L SA0000CMS1L SA0000CMS1L SA0000CMS1L SA0000CMS1L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
AXN@ AXN@
SD00000LF80 SD00000LF80
22_0201_5% 22_0201_5% Micron 16GB/2666
AX201.D2WD.WQ X7688431L09 UD1 UD2 UD3 UD4 UD5 UD6 UD7 UD8 RC393 RC389 RC395 RC396 RC392
M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@
PK29S00AY5L
SA0000BC72L SA0000BC72L SA0000BC72L SA0000BC72L SA0000BC72L SA0000BC72L SA0000BC72L SA0000BC72L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Micron 16GB/2666
M16GN@ M16GN@ M16GN@ M16GN@ M16GN@ M16GN@ M16GN@ M16GN@ M16GN@ M16GN@ M16GN@ M16GN@ M16GN@
TBU TBU TBU TBU TBU TBU TBU TBU SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Micron 32GB/2666
DRAM SDP E9 option UD1
M32G@
UD2
M32G@
UD3
M32G@
UD4
M32G@
UD5
M32G@
UD6
M32G@
UD7
M32G@
UD8
M32G@
RC393
M32G@
RC389
M32G@
RC390
M32G@
RC396
M32G@
RC392
M32G@
SA0000CYF0L SA0000CYF0L SA0000CYF0L SA0000CYF0L SA0000CYF0L SA0000CYF0L SA0000CYF0L SA0000CYF0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
RD88 RD89 RD90 RD91
SDP@ SDP@ SDP@ SDP@
C
SD043000080 SD043000080 SD043000080 SD043000080 Hynix 4GB/2666(Channel A only) C
0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% X7688431L02 UD1 UD2 UD3 UD4 RC393 RC389 RC390 RC391 RC392
H4G@ H4G@ H4G@ H4G@ H4G@ H4G@ H4G@ H4G@ H4G@
RD92 RD93 RD94 RD95 SA0000BMN1L SA0000BMN1L SA0000BMN1L SA0000BMN1L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
SDP@ SDP@ SDP@ SDP@
SD043000080 SD043000080 SD043000080 SD043000080
0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% Hynix 8GB/2666
X7688431L05 UD1 UD2 UD3 UD4 UD5 UD6 UD7 UD8 RC388 RC394 RC395 RC396 RC392
H8G@ H8G@ H8G@ H8G@ H8G@ H8G@ H8G@ H8G@ H8G@ H8G@ H8G@ H8G@ H8G@
SA0000BMN1L SA0000BMN1L SA0000BMN1L SA0000BMN1L SA0000BMN1L SA0000BMN1L SA0000BMN1L SA0000BMN1L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Hynix 16GB/2666
SA0000BZJ1L SA0000BZJ1L SA0000BZJ1L SA0000BZJ1L SA0000BZJ1L SA0000BZJ1L SA0000BZJ1L SA0000BZJ1L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Hynix 32GB/2666
SA0000DAU0L SA0000DAU0L SA0000DAU0L SA0000DAU0L SA0000DAU0L SA0000DAU0L SA0000DAU0L SA0000DAU0L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Samsung 4GB/2666(Channel A only)

X7688431L01 UD1 UD2 UD3 UD4 RC388 RC394 RC390 RC391 RC392
S4G@ S4G@ S4G@ S4G@ S4G@ S4G@ S4G@ S4G@ S4G@
SA0000B6F2L SA0000B6F2L SA0000B6F2L SA0000B6F2L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Samsung 8GB/2666
S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@
SA0000B6F2L SA0000B6F2L SA0000B6F2L SA0000B6F2L SA0000B6F2L SA0000B6F2L SA0000B6F2L SA0000B6F2L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
B B
Samsung 16GB/2666
SA0000B9K1L SA0000B9K1L SA0000B9K1L SA0000B9K1L SA0000B9K1L SA0000B9K1L SA0000B9K1L SA0000B9K1L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
Samsung 32GB/2666
SA0000CHM1L SA0000CHM1L SA0000CHM1L SA0000CHM1L SA0000CHM1L SA0000CHM1L SA0000CHM1L SA0000CHM1L SD043100280 SD043100280 SD043100280 SD043100280 SD043100280
A A
Bom option
5 4 3 2 1
5 4 3 2 1

Issue Solution
Item Page# Date Description Description Rev.
1.Add RC510(100K_0201_5%) pull up to +3.3V_ALW_PCH connection to PCH_BT_RADIO_DIS#
1 9, 2019/09/11 Add reserve PCH control bluetooth GPIO solution 2.Change net TOUCH_SCREEN_DET# from UC1.CC35 to UC1.CN23 0.2(X01)
3.Add net PCH_BT_RADIO_DIS# to UC1.CC35 and RZ301.Pin1
14, 4.Add RZ300, RZ301(0_0201_5%), RZ301 depop
52, 5.Change UE1.A1, RE11.Pin1, RZ300.Pin1 net name from BT_RADIO_DIS# to EC_BT_RADIO_DIS#
D
58 6.Add net BT_RADIO_DIS# connect to RZ300.Pin2, RZ301.Pin2, DZ2.Pin1 D
Modified part according to PU and PD power consumption 1.Change RC401 from 10K_0201_5% to 100K_0201_5%
2 ALL 2019/09/11 improve plan
2.Change RC765 from 10K_0201_5% to 100K_0201_5% 0.2(X01)
3.Change RC278 from 10K_0201_5% to 100K_0201_5%
4.Change RC567, RC844 from 10K_0201_5% to 100K_0201_5%
5.Change RT80, RT90, RT91, RT92, RT552, RT553, RT554, RT551, RT93, RT94, RT556, RT555 from 10K_0201_5% to 100K_0201_5%
6.Change RR3 from 10K_0201_5% to 100K_0201_5%
7.Change RE704, RE826, RE21 from 10K_0201_5% to 100K_0201_5%
3 79 2019/09/11 Modified Part according Dell request Change RZ1482 from 1M_0201_5% to 330K_0201_5% 0.2(X01)
4 43 2019/09/11 Modified TR circuit according confirm with Intel result Change RT498(10K_0201_5%) from pop to depop 0.2(X01)
1.Add CD145(10U_0603_10V6M), Pin1 connect to +2.5V_MEM, Pin2 connect to GND
5 23,24 2019/09/11 Modified DDR circuit to correct 2.Add RD96, RD97, RD98(0_0201_5%) and Pin1 connect to DDR_A_BG1_R, Pin2 connect to GND 0.2(X01)
3.Add RD99, RD100, RD101(0_0201_5%) and Pin1 connect to DDR_B_BG1_R, Pin2 connect to GND
1.Change RV614 from 4.7K_0201_5% to 0_0201_5%
6 40 2019/09/11 Modified HDMI circuit to correct 2.Change RV614.Pin1 net name from +3.3V_RUN to TMDS_CFG1 0.2(X01)
3.Change CV777.Pin1 connection from UV19.Pin46, RV21.Pin1 to RV21.Pin2, UT1.R5, RT184.Pin1
1.Change DV13 from CEST523 to AZ5125
7 ALL 2019/09/12 Modified part according ESD request 2.Change DV14, DZ10, DZ21 from CEST523 to CEST23 0.2(X01)
C 3.Change DT5, DT6, DT9, DT10, DT13, DT14, DT17, DT18, DT55, DT48, DT51, DT49, DT50, DT53, DT54, DT52 from DESD3V3Z C
to AZ5B8S
8 ALL 2019/09/12 Modified part according RF request Remove CV765, CV767, CV766, CV768, CV769, CV770, CV771, CV772, CV773, CV774, CV775, CV776 reserve cap (0.1U_0201_10V6K) 0.2(X01)
9 59 2019/09/17 Change Board ID to X01 Change RE79 from 240K_0402_5% to 130K_0402_5% 0.2(X01)
1.Change DV13 from AZ5125 to L03ESDL5V
10 38 2019/09/17 Change part according ESD request 2.Change DV14, DZ10, DZ21 from CEST23 to L03ESDL5V 0.2(X01)
1.Add CZ337(0.1U_0201_25V6K) and Pin1 connect to +3.3V_RUN, Pin2 connect to GND
11 66,40 2019/09/17 Add part according EMI request 2.Add CV779(0.1U_0201_25V6K) and Pin1 connect to +3.3V_RUN, Pin2 connect to GND 0.2(X01)
3.Add CR29(0.1U_0201_25V6K) and Pin1 connect to +3.3V_RUN, Pin2 connect to GND
70,45 4.Add CT394, CT395(0.1U_0201_25V6K) and Pin1 connect to +20V_TBTA_VBUS, Pin2 connect to GND
1.Swap QV23.Pin1 from +3.3V_5V_RUN_QV8 to +3.3V_RUN
12 38 2019/09/17 Change touch screen circuit to correct 2.Swap QV23.Pin3 from +3.3V_RUN to +3.3V_5V_RUN_QV8 0.2(X01)
13 8 2019/09/17 Modified G3 sharing WDT circuit to reserved Change QC9, RC303, CC341 from pop to depop 0.2(X01)
14 58 2019/09/17 Change part to reserve Change RE11(100K_0201_5%) from pop to depop 0.2(X01)
1.Delete reserve RZ301(0_0201_5%), Pin1 disconnect PCH_BT_RADIO_DIS#, Pin2 disconnect BT_RADIO_DIS#
B
15 52 2019/09/17 Modified BT_RADIO_DIS# circuit to correct 2.Add reserve RZ302(100K_0201_5%), Pin1 connect +3.3V_WLAN, Pin2 connect EC_BT_RADIO_DIS# 0.2(X01) B
3.Change DZ2.Pin1 net name from BT_RADIO_DIS# to PCH_BT_RADIO_DIS#, DZ2.Pin2 net name from BT_RADIO_DIS#_R to
BT_RADIO_DIS#
4.Delete net name BT_RADIO_DIS#_R
5.Change WL1.Pin63 net name from BT_RADIO_DIS#_R to BT_RADIO_DIS#
Add net for thermal table to define WWAN and Non-WWAN sku 1.Add net WWAN_DET# and connect to UE1.L11, JIO1.B10
16 58,74 2019/09/18 according thermal team request
2.Add RE839(100K_0201_5%), Pin1 connect to WWAN_DET#, Pin2 connect to +3.3V_ALW 0.2(X01)
1.Add CE80(2200P_0201_25V7K) for reserve, Pin1 connect to UE1.B11 net name is REM_DIODE3_N, Pin2 connect to UE1.A11
17 58,59 2019/09/19 Add reserve circuit for thermal sensor net name is REM_DIODE3_P 0.2(X01)
2.Add QE30, CE81(100P_0201_50V8J) for reserve
3.REM_DIODE3_P connect to QE30.1, QE30.2 and CE81.1
4.REM_DIODE3_N connect to QE30.3 and CE81.2
1.Add RZ310(0_0402_5%), Pin1 connect to JTS1.6(TS_RST#_R), Pin2 connect to PCH_PLTRST#_AND
18 9,38 2019/09/19 Add reserve touch reset circuit 2.Add RZ311(0_0402_5%) for reserve, Pin1 connect to JTS1.6(TS_RST#_R), Pin2 connect to TS_RST# 0.2(X01)
3.Add net TS_RST#_R connect to JTS1.Pin6, RZ311.1, RZ310.1
4.Add net TS_RST# connect to RZ311.2, UC1.CM24
1.Add 3.3V_CAM_EN#_R connect to RZ388.2, CZ220.1, QZ1.2
19 38 2019/09/19 Add net align with X11 platform 2.Add 3.3V_TS_EN_R connect to RV326.6, RV323.2, QV7.2, RV324.2 0.2(X01)
3.Add +5V_RUN_QV7 connect to QV7.1, RV400.1, RV6.2
4.Add +5V_RUN_QV7_R connect to RV400.2, QV8.2, CV635.1
1.Change net name EN_LCDPWR to LCD_PWR_EN and disconnect UV24.Pin4, DV3.Pin1, RV3.1
20 38 2019/09/19 Add reserve LCDVDD enable RC delay circuit 2.Add RV180(0_0402_5%), CV80(1U_0402_6.3V6K) for reserve 0.2(X01)
3.LCD_PWR_EN connect to DV3.Pin1, RV180.1
A 4.Add net LCD_PWR_EN_R connect to RV180.2, CV80.1, RV3.1, UV24.Pin4 A
5.CV80.2 connect to GND
Title
EE P.I.R
LA-J261p
5 4 3 2 1
5 4 3 2 1

Issue Solution
1 38 2019/09/27 Change part according follow spyglass MLK Change RV2 from 4.7K_0201_5% to 2.2K_0201_5%(SD043470180 to SD000012R80) 0.2(X01)
2 44 2019/10/03 Modified part align with X11 platform Change RT85(0_0201_5%) from pop to depop 0.2(X01) D
D
Change HDA RF cap from pop to de-pop according fixed Change CZ330, CZ332, CZ334, CZ335(47P_0201_50V8J) from pop to depop
3 74 2019/11/19 audio device lost issue 0.3(X02)
Modified part according to PD power consumption Change RE342, RE56 from 10K_0201_5% to 100K_0201_5%
4 58 2019/11/19 improve plan 0.3(X02)
5 59 2019/12/10 Change Board ID to X02 Change RE79 from 130K_0402_5% to 62K_0402_5% 0.3(X02)
1.Add DZ16(RB751S-40) between on EC_BT_RADIO_DIS# and BT_RADIO_DIS#
6 52,58 2019/12/10 Modified BT_RADIO_DIS# circuit 2.Change RZ300(0_0201_5%) form pop to depop 0.3(X02)
3.Change RE11(100K_0201_5%) from depop to pop
7 38,66 2019/12/10 Change part according ESD team request Change DV13, DV14, DZ10, DZ21, DZ108 from L03ESDL5VOCG3 to CEST523NC5VB 0.3(X02)
8 64 2019/12/16 Add part according ESD team request Add CZ380(0.1U_0201_10V6K), Pin1 connect to BATT_WHITE#, Pin2 connect to GND 0.3(X02)
9 38 2019/12/16 Modify part according EMI team request Change LV1 from pop to depop, add RV999(0_0402_5%), Pin1 connect N32816135, Pin2 connect BIA_PWM, and colay with LV1 0.3(X02)
10 52 2019/12/16 Delete reserve location align with X11 Delete RZ302(100K_0201_5%), Pin1 connect +3.3V_WLAN, Pin2 connect EC_BT_RADIO_DIS# 0.3(X02) C
C
11 66 2019/12/16 Reserve 1.8V setting for future use with new FIPC tool Add reserve location RZ1600(10K_0201_5%), Pin1 connect +1.8V_PRIM, Pin2 connect TPM_PIRQ# 0.3(X02)
12 58 2019/12/16 Modify part according EC team request Change RE838(0_0201_5%) from depop to pop 0.3(X02)
Modify TS circuit for soft start and add discharge 1.Change CV635.Pin1 connection from TS_PWR_EN#_R to +3.3V_5V_RUN_QV8
13 38 2019/12/16 circuit
2.Change CV635.Pin2 connection from GND to TS_PWR_EN#_R 0.3(X02)
3.Change RV6.Pin2 connection from +5V_RUN to +3.3V_5V_RUN_QV8
4.Change RV6.Pin1 connection from TS_PWR_EN# to TS_PWR_EN#_R
5.Change RV400.Pin1 connection from TS_PWR_EN# to TS_PWR_EN#_R
6.Change RV400.Pin2 connection from TS_PWR_EN#_R to TS_PWR_EN#
7.Add RV775(100_0402_5%) for reserve, Pin1 connect to +TS_PWR, Pin2 connect to +TS_PWR_DIS
8.Add QV100(PJE138K) for reserve, Pin1 connect to +TS_PWR_DIS, Pin2 connect to TS_PWR_EN#_R, Pin3 connect to GND
1.Change QZ2(PJX138K), QZ19(PJE138K), RZ1(100K_0201_5%), RZ2(2M_0201_5%), RZ3(100_0201_5%), RZ4, RZ5(2.2K_0201_5%), LED3,
14 79 2019/12/16 Remove battery switch according Dell request SW4 from pop to depop 0.3(X02)
2.Change RZ6(0_0201_5%) from depop to pop
1.Add RE902(10M_0201_1%), Pin1 connect to LID_CL_SIO_TAB#, Pin2 connect to LID_CL#_QE32
15 59 2019/12/17 Add circuit fixed 360 casue auto power on solution 2.Add CE401(2.2U_0402_10V6M), Pin1 connect to LID_CL#_QE32, Pin2 connect to GND 0.3(X02)
3.Add DZ110(RB751S-40), Pin1 connect to N38978302, Pin2 connect to LID_CL#_QE32
4.Add RE903(49.9K_0201_1%), Pin1 connect to LID_CL_SIO_TAB#, Pin2 connect to N38978302
5.Add CE400(1U_0201_6.3V6M) for reserve, Pin1 connect to LID_CL_SIO_TAB#, Pin2 connect to LID_CL_SIO_TAB#_D1
6.Add DZ109(RB751S-40), Pin1 connect to LID_CL_SIO_TAB#, Pin2 connect to LID_CL_SIO_TAB#_D1
7.Add RE904(2M_0201_5%), Pin1 connect to +RTC_CELL, Pin2 connect to LID_CL_SIO_TAB#_D1
B B
8.Add QE32(PJX138K_SOT563-6), Pin1 connect to GND, Pin2 connect to LID_CL#_QE32, Pin3 connect to LID_CL#_D,
Pin4 connect to GND, Pin5 connect to LID_CL_SIO_TAB#_D1, Pin6 connect to LID_CL_SIO_TAB#_D1
16 66 2019/12/17 Add Fuse according factory request Add FZ6(0.5A_65V), Pin1 connect to +3.3V_RUN, Pin2 connect to +3.3V_RUN_FZ6 0.3(X02)
17 ALL 2019/12/18 Change 0 ohm to short pad(0603) Change RT508 to short pad 0.3(X02)
18 ALL 2019/12/18 Change 0 ohm to short pad(0402) Change RZ1408, RV180, RR20, RC216, RC440 to short pad 0.3(X02)
Change RC25, RC29, RC582, RC32, RC30, RC27, RC26, RC660, RC337, RC738, RC243, RC532, RC559, RC430, RC157, RC429, RC159,
19 ALL 2019/12/18 Change 0 ohm to short pad(0201) RC153, RC632, RC631, RC425, RZ1423, RC426, RZ1420, RZ120, RD87, RZ388, RV19, RV748, RV634, RV614, RV633, RV635, RV750, 0.3(X02)
RV749, RV632, RV751, RT40, RT394. RT105, RT520, RT521, RT78, RT403, RT110, RT548, RT402, RT511, RT79, RT510, RT77, RZ1385
, RZ56, RZ827, RE103, RE565, RE104, RE105, RE318, RE608, RE601, RE361, RE290, RE548, RE59, RE602, RE600, RE603, RE102,
RE552, RE90, RE275, RCH99, RZ347, RZ346, RCH95, RZ26, RZ400, RZ29, RZ152, RZ153, RZ350, RZ114, RZ112, RZ351, RN129, RN99,
RR9, RR10, RR7, RR8, RR6, RA54, RA48, RZ345, RC850, RC736, RZ6, RC851, RZ1415, RC853, RC735, RV628, RC852, RC737, RE30,
RC328, RC442, RC215, RT456 to short pad
20 64 2019/12/31 Change LED resistor according ME request Change RZ361, RZ28 from 1.5K_0402_5% to 1K_0402_1% 0.3(X02)
21 44 2020/01/06 Change PD circuit MLCC align with NBMLK Change CT82, CT83 from 1U_0402_25V6K to 2.2U_0402_25V6M(SE000010V00 to SE000013H00) 0.3(X02)
A A
22 ALL 2020/02/19 Change 0 ohm to short pad(0603) Change RC422, RC330, RC329 to short pad 1.0(A00)
Title
EE P.I.R
LA-J261p
5 4 3 2 1
5 4 3 2 1

Issue Solution
1 ALL 2020/02/19 Change 0 ohm to short pad(0402) Change RE32, RE314, RE315, RE316, RV999 to short pad 1.0(A00)
Change RC455, RV323, RZ1498, RZ311, RT96, RT98, RE838, RC845, RV765, RV762, RV758, RV759, RV760, RV757, RV761, RV756,
D 2 ALL 2020/02/19 Change 0 ohm to short pad(0201) RV764, RV763, RT123, RT121, RT120, RT122, RT535, RT532, RT534, RT533, RR5 to short pad 1.0(A00) D
Change RC455, RV323, RZ1498, RZ311, RT96, RT98, RE838, RC845, RV765, RV762, RV758, RV759, RV760, RV757, RV761, RV756,
3 ALL 2020/02/19 Change 0 ohm to short pad(0201) RV764, RV763, RT123, RT121, RT120, RT122, RT535, RT532, RT534, RT533, RR5 to short pad 1.0(A00)
4 11 2020/02/19 Change MLCC value to correct Change CC23, CC26 from 15P_0201_50V8J to 12P_0201_50V8J 1.0(A00)
5 59 2020/02/19 Change Board ID to A00 Change RE79 from 62K_0402_5% to 4.3K_0402_1% 1.0(A00)
6 79 2020/02/19 Change XDP circuit according ESD request Change RC328, RC735, RC736, RC737, RC850, RC851, RC852, RC853 to normal 0 ohm and depop part 1.0(A00)
1.Change RC222(1K_0201_5%) and SWME1 from pop to depop
7 79 2020/02/19 ME SW depop 2.Change RC221 to short pad 1.0(A00)
C C
B B
A A
Title
EE P.I.R
LA-J261p
5 4 3 2 1

Riverside TR MB LA-J261PR10 A00 20200327

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Riverside TR MB LA-J261PR10 A00 20200327

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5 4 3 2 1

COMPAL CONFIDENTIAL Riverside 13"14" UMA(TR)

BOM P/N :431AJS31LXX

RF@ : RF Component S4G@ : Samsung 4GB DRAM Component C

@RF@ : RF Nopop Component S8G@ : Samsung 8GB DRAM Component

NRTD3@ : RTD3 Component M4G@ : Micron 4GB DRAM Component

CONN@ : Connector Component

Riverside TR Block Diagram Memory Down

Memory BUS (DDR4)

Micro SIM CNVi Magnetometer/

HD Audio I/F HDA Codec Universal Jack

Left side front DEMUX AUTOMATIC POWER

PCIE-14 M.2 2280 SSD

S5 S4/AC ON OFF OFF

S5 S4/AC doesn't exist ON OFF OFF

Converter Single Load switch@SIO_SLP_S3#

(PU501) +1.8V_PRIM +1.8V_RUN

ISL95880 FDMF3035 Dual Load switch

Dual Load switch

+VCC_CORE VCCHDA SLP_LAN#

+5V_TSP LP2301ALT1G GPP_B21

EC 5107 1BAT 2AC

CPU_DP2_CTRL_DATA Strap Pin CH3 GPP_E20/DPPC_CTRLCLK LOW(DEFAULT) 38.4MHz

@ RC880 0_0201_5% 150_0201_1% 2 1 RC448 CNV_WT_RCOMP CP32 GPP_F12/EMMC_DATA0 CM201.8V MEM_CONFIG1_1P8

DDR4, Ballout for side by side(Non-Interleave)

DDR4 COMPENSATION SIGNALS

CH23 BY29 1.8V ESPI_IO1_1P8_R RC367 1 2 15_0201_5%

CH7 GPP_A14/SUS_STAT#/ESPI_RESET# 607554_CML-U_v1_AEP_SCH_Rev0p9

EC G3 SPI Flash Sharing with Wire-OR(1 Flash and 1TPM)

<11> VCCDSW _EN_Q PCH_RSMRST# <58,63,79> PCH_SPI_D1_PCH PCH_SPI_D1

WEAK INTERNAL PD 20K

@EMI@ +3.3V_SPI CC9 JXT_FP243A-020G1BM

Add according to Microchip 0410 review results PCH_SPI_CS#0 1 2 SPI_CS#0_R 1 8

20K_0201_5% 2 1 @ RC724 CNV_BRI_PRX_DTX_1P8

20K_0201_5% 2 1 @ RC733 CNV_RGI_PRX_DTX_1P8

PCH_TBT_PERST# pull up power rail

WEAK INTERNAL PD 20K

WEAK INTERNAL PD 20K

USB_OC3# RC836 2 1 10K_0201_5%

Refer RVP is 200K ohm +-1% CC21

2 1 LAN_W AKE# PCH_PLTRST# 1 2

2 1 PCH_PCIE_W AKE# PCH_PLTRST#_AND 1 2 1 2 SIO_SLP_SUS# 1 2

2 1 VCCST_PW RGD RB751S-40_SOD523-2 0_0201_5%

B 4 PCH_PLTRST#_AND @NDS3@ RC329 0_0603_5%

No Support DS3 X V X V X V RB751S-40_SOD523-2

'V' mean POP, 'X' mean DE-POP

External pull-up or pull-down is required.

2 1 SIO_SLP_S0# 3.0V Select

POP NO Support Deep sleep

CC196 ESD Request:place near CPU side

Reserved for support TOP SWAP feature

+3.3V_ALW_PCH RF Request. Place near CPU side (Intel MOW)

WEAK INTERNAL PD 20K

EAR-STALL/NOT STALL RESET PEG DEFER TRAINING

CFG12 1: (DEFAULT) PMSYNC 2.0

RC2181 2 1K_0201_1% H_THERMTRIP#_R

RC2191 2 49.9_0201_1% H_CATERR# CPU@

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

ESD request,Place near CPU side.

PSC(Primary side cap) : Place as close to the package as possible

1 2 C34 AW7 @ RC430

2 1 AJ27 RSVD_56 1 +VCC_CORE_G0 BB9 VIDALERT# @ RC429 RC151

+1.2V_DDR: 1.2V, 3.5A