Professional Documents
Culture Documents
Router Lint Report
Router Lint Report
-------------------------------------
RTL CODE:
-------------------------------------
Top module:
------------------
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:28:09 09/10/2023
// Design Name:
// Module Name: top_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_module(
input clk,
input resetn,
input read_enb_0,
input read_enb_1,
input read_enb_2,
input [7:0] data_in,
input pkt_valid,
output [7:0] data_out_0,
output [7:0] data_out_1,
output [7:0] data_out_2,
output valid_out_0,
output valid_out_1,
output valid_out_2,
output err,
output busy
);
//buffer clock
//fsm wires
wire ld_state,lfd_state,laf_state,rst_int_reg,write_enb_reg,full_state,detect_add;
//register wires
wire [7:0] dout;
wire low_pkt_valid,parity_done;
//fifo wires
wire empty_0,empty_1,empty_2;
wire full_0,full_1,full_2;
//synchroniser wires
wire soft_reset_0,soft_reset_1,soft_reset_2;
wire fifo_full;
wire [2:0] write_enb;
fifo fifo1(
.clk(clk),
.resetn(resetn),
.soft_reset(soft_reset_0),
.write_enb(write_enb[0]),
.read_enb(read_enb_0),
.data_in(dout),
.lfd_state(lfd_state),
.full(full_0),
.empty(empty_0),
.data_out(data_out_0)
);
fifo fifo2(
.clk(clk),
.resetn(resetn),
.soft_reset(soft_reset_1),
.write_enb(write_enb[1]),
.read_enb(read_enb_1),
.data_in(dout),
.lfd_state(lfd_state),
.full(full_1),
.empty(empty_1),
.data_out(data_out_1)
);
fifo fifo3(
.clk(clk),
.resetn(resetn),
.soft_reset(soft_reset_2),
.write_enb(write_enb[2]),
.read_enb(read_enb_2),
.data_in(dout),
.lfd_state(lfd_state),
.full(full_2),
.empty(empty_2),
.data_out(data_out_2)
);
synchroniser a1(
.clk(clk),
.resetn(resetn),
.read_enb_0(read_enb_0),
.read_enb_1(read_enb_1),
.read_enb_2(read_enb_2),
.empty_0(empty_0),
.empty_1(empty_1),
.empty_2(empty_2),
.full_0(full_0),
.full_1(full_1),
.full_2(full_2),
.data_in(data_in[1:0]),
.detect_add(detect_add),
.write_enb_reg(write_enb_reg),
.soft_reset_0(soft_reset_0),
.soft_reset_1(soft_reset_1),
.soft_reset_2(soft_reset_2),
.vld_out_0(valid_out_0),
.vld_out_1(valid_out_1),
.vld_out_2(valid_out_2),
.fifo_full(fifo_full),
.write_enb(write_enb)
);
router_fsm a2(
.clk(clk),
.resetn(resetn),
.pkt_valid(pkt_valid),
.parity_done(parity_done),
.data_in(data_in[1:0]),
.soft_reset_0(soft_reset_0),
.soft_reset_1(soft_reset_1),
.soft_reset_2(soft_reset_2),
.fifo_full(fifo_full),
.low_pkt_valid(low_pkt_valid),
.fifo_empty_0(empty_0),
.fifo_empty_1(empty_1),
.fifo_empty_2(empty_2),
.busy(busy),
.detect_add(detect_add),
.ld_state(ld_state),
.laf_state(laf_state),
.full_state(full_state),
.write_enb_reg(write_enb_reg),
.rst_int_reg(rst_int_reg),
.lfd_state(lfd_state)
);
router_reg a3 (
.clk(clk),
.resetn(resetn),
.pkt_valid(pkt_valid),
.data_in(data_in),
.fifo_full(fifo_full),
.rst_int_reg(rst_int_reg),
.detect_add(detect_add),
.ld_state(ld_state),
.laf_state(laf_state),
.full_state(full_state),
.lfd_state(lfd_state),
.parity_done(parity_done),
.low_pkt_valid(low_pkt_valid),
.err(err),
.dout(dout)
);
endmodule
FIFO(sub module):
-------------------------------
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:36:40 08/30/2023
// Design Name:
// Module Name: fifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo(
input clk,
input resetn,
input soft_reset,
input write_enb,
input read_enb,
input [7:0] data_in,
input lfd_state,
output full,
output empty,
output reg [7:0] data_out
);
//pointers
reg [4:0] rdptr;
reg [4:0] wrptr;
//memory
reg [8:0] mem [0:15];
//fifo counter
reg [5:0] fifocounter;
reg lfd_state_s;
//write operation
always@(posedge clk)
begin
if(~resetn)
begin:block
integer i;
for(i=0;i<16;i=i+1)
mem[i]<=0;
end
else if(soft_reset)
begin:block1
integer i;
for(i=0;i<16;i=i+1)
mem[i]<=0;
end
else
if(write_enb && ~full)
mem[wrptr[3:0]]<={lfd_state_s,data_in};
end
always@(posedge clk)
begin
if(~resetn)
begin
rdptr<=0;
wrptr<=0;
end
else if(soft_reset)
begin
rdptr<=0;
wrptr<=0;
end
else
begin
if(read_enb &&~empty)
rdptr<=rdptr+1'b1;
else
rdptr<=rdptr;
end
end
//fifocounter logic
always@(posedge clk)
begin
if(~resetn)
fifocounter<=0;
else if(soft_reset)
fifocounter<=0;
else if(read_enb &&~empty)
begin
if(mem[rdptr[3:0]][8]==1'b1)
fifocounter<=mem[rdptr[3:0]][7:2]+1'b1; //to store payload and parity also
else if(fifocounter!=0)
fifocounter<=fifocounter-1'b1;
end
end
endmodule
SYNCHRONISER(submodule):
---------------------------------------------
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:48:13 08/30/2023
// Design Name:
// Module Name: synchroniser
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module synchroniser(
input clk,
input resetn,
input read_enb_0,
input read_enb_1,
input read_enb_2,
input empty_0,
input empty_1,
input empty_2,
input full_0,
input full_1,
input full_2,
input [1:0] data_in,
input detect_add,
input write_enb_reg,
output reg soft_reset_0,
output reg soft_reset_1,
output reg soft_reset_2,
output vld_out_0,
output vld_out_1,
output vld_out_2,
output reg fifo_full,
output reg [2:0] write_enb
);
//softreset logic
reg [4:0] counter_0;
reg [4:0] counter_1;
reg [4:0] counter_2;
wire w1,w2,w3;
assign w1=(counter_0==5'd29);
assign w2=(counter_1==5'd29);
assign w3=(counter_2==5'd29);
always@(posedge clk)
begin
if(~resetn)
begin
counter_0<=0;
soft_reset_0<=0;
end
else
if(vld_out_0)
begin
if(~read_enb_0)
begin
if(w1)
begin
soft_reset_0<=1'b1;
counter_0<=0;
end
else
begin
counter_0<=counter_0+1'b1;
soft_reset_0<=1'b0;
end
end
end
end
always@(posedge clk)
begin
if(~resetn)
begin
counter_1<=0;
soft_reset_1<=0;
end
else
if(vld_out_1)
begin
if(~read_enb_1)
begin
if(w2)
begin
soft_reset_1<=1'b1;
counter_1<=0;
end
else
begin
counter_1<=counter_1+1'b1;
soft_reset_1<=1'b0;
end
end
end
end
always@(posedge clk)
begin
if(~resetn)
begin
counter_2<=0;
soft_reset_2<=0;
end
else
if(vld_out_2)
begin
if(~read_enb_2)
begin
if(w3)
begin
soft_reset_2<=1'b1;
counter_2<=0;
end
else
begin
counter_2<=counter_2+1'b1;
soft_reset_2<=1'b0;
end
end
end
end
//validout logic
assign vld_out_0=~empty_0;
assign vld_out_1=~empty_1;
assign vld_out_2=~empty_2;
always@(posedge clk)
begin
if(~resetn)
address<=0;
else
if(detect_add)
address<=data_in;
end
always@(*)
begin
write_enb=3'b000;
if(write_enb_reg)
begin
case(address)
2'b00:write_enb=3'b001;
2'b01:write_enb=3'b010;
2'b10:write_enb=3'b100;
default:write_enb=3'b000;
endcase
end
end
//fifofull logic
always@(*)
begin
case(address)
2'b00:fifo_full=full_0;
2'b01:fifo_full=full_1;
2'b10:fifo_full=full_2;
default:fifo_full=1'b0;
endcase
end
endmodule
ROUTER_FSM(sub module):
-------------------------------------------
parameter DECODE_ADDRESS=3'b000,
LOAD_FIRST_DATA=3'b001,
LOAD_DATA=3'b010,
LOAD_PARITY=3'b011,
FIFO_FULL_STATE=3'b100,
LOAD_AFTER_FULL=3'b101,
CHECK_PARITY_ERROR=3'b110,
WAIT_TILL_EMPTY=3'b111;
reg [2:0] pss,nss;
reg [1:0] address;
// sequential memory
always@(posedge clk)
begin
if(~resetn)
pss<=DECODE_ADDRESS;
else if((soft_reset_0&&data_in==2'b00)||(soft_reset_1&&data_in==2'b01)||
(soft_reset_2&&data_in==2'b10))
pss<=DECODE_ADDRESS;
else
pss<=nss;
end
//address storing logic
always@(posedge clk)
begin
if(~resetn)
address<=2'b00;
else if(nss==WAIT_TILL_EMPTY)
address<=data_in;
else
address<=address;
end
//nextstate logic
always@(*)
begin
nss=pss;
case(pss)
DECODE_ADDRESS:begin
if((pkt_valid && (data_in[1:0]==2'b00) && fifo_empty_0)||
(pkt_valid && (data_in[1:0]==2'b01) && fifo_empty_1)||
(pkt_valid && (data_in[1:0]==2'b10) && fifo_empty_2))
nss=LOAD_FIRST_DATA;
else if((pkt_valid && (data_in[1:0]==2'b00) && !fifo_empty_0)||
(pkt_valid && (data_in[1:0]==2'b01) && !fifo_empty_1)||
(pkt_valid && (data_in[1:0]==2'b10) && !fifo_empty_2))
nss=WAIT_TILL_EMPTY;
else
nss=DECODE_ADDRESS;
end
LOAD_FIRST_DATA:nss=LOAD_DATA;
LOAD_DATA:begin
if(fifo_full)
nss=FIFO_FULL_STATE;
else if(!fifo_full && !pkt_valid)
nss=LOAD_PARITY;
else
nss=LOAD_DATA;
end
LOAD_PARITY:nss=CHECK_PARITY_ERROR;
CHECK_PARITY_ERROR:begin
if(fifo_full)
nss=FIFO_FULL_STATE;
else if(!fifo_full)
nss=DECODE_ADDRESS;
else
nss=CHECK_PARITY_ERROR;
end
WAIT_TILL_EMPTY:begin
if((fifo_empty_0 && address==2'b00)||
(fifo_empty_1 && address==2'b01)||
(fifo_empty_2 && address==2'b10))
nss=LOAD_FIRST_DATA;
else
nss=WAIT_TILL_EMPTY;
end
FIFO_FULL_STATE:begin
if(!fifo_full)
nss=LOAD_AFTER_FULL;
else
nss=FIFO_FULL_STATE;
end
LOAD_AFTER_FULL:begin
if(!parity_done && !low_pkt_valid)
nss=LOAD_DATA;
else if(!parity_done && low_pkt_valid)
nss=LOAD_PARITY;
else if(parity_done)
nss=DECODE_ADDRESS;
else
nss=LOAD_AFTER_FULL;
end
endcase
end
endmodule
//dout logic
always@(posedge clk)
begin
if(~resetn)
dout<=0;
else if(lfd_state)//if we send data in lfd state end then we will have to make writeenbreg in load data state
only.
dout<=header_byte;
else if(ld_state && ~fifo_full)
dout<=data_in;
else if(laf_state)
dout<=fifo_full_data;
else
dout<=dout;
end
end
end
always@(posedge clk)
begin
if(~resetn)
low_pkt_valid=0;
else
begin
if(rst_int_reg)
low_pkt_valid<=1'b0;
else if(ld_state && ~pkt_valid)
low_pkt_valid<=1'b1;
else
low_pkt_valid<=low_pkt_valid;
end
end
//dparity logic
always@(posedge clk)
begin
if(~resetn)
dparity<=0;
else
begin
if((ld_state && ~pkt_valid && ~fifo_full)||(laf_state && ~parity_done &&
low_pkt_valid))
dparity<=data_in;
else if(rst_int_reg &&~fifo_full)
dparity<=0;
else if(detect_add)
dparity<=0;
end
end
endmodule