Professional Documents
Culture Documents
EE202-S24 w03 2 sinusoidalSteadyStateAnalysis
EE202-S24 w03 2 sinusoidalSteadyStateAnalysis
Week 3 – Lecture 2:
Sinusoidal Steady State Analysis
Abdurrahman Gümüş
Assistant Professor
Electrical and Electronics Engineering
March 06, 2024
Monday Thursday
10:30 – 12:00 office hour 14:00 – 15:00 problem solving session (Z41)
15:00 – 16:30 office hour
1
EE202-S24_w03_2
2
EE202-S24_w03_2
Nodal Analysis
3
EE202-S24_w03_2
4
EE202-S24_w03_2
10
5
EE202-S24_w03_2
11
12
6
EE202-S24_w03_2
At supernode
13
Mesh Analysis
14
7
EE202-S24_w03_2
15
KVL at mesh 1
KVL at mesh 2
For mesh 3
16
8
EE202-S24_w03_2
17
18
9
EE202-S24_w03_2
19
KVL at mesh 1
For mesh 2
KVL at supermesh
For supermesh
20
10
EE202-S24_w03_2
Superposition Theorem
21
Superposition Theorem
Because the exponential factor ejωt is implicit in sinusoidal analysis, and that
factor would change for every angular frequency ω
22
11
EE202-S24_w03_2
23
Z = -j2 || 8+j10
24
12
EE202-S24_w03_2
To get I’’
KVL at mesh 1
Mesh2
Mesh2
Substitute I1
25
26
13
EE202-S24_w03_2
27
28
14
EE202-S24_w03_2
At steady state,
a capacitor is an open circuit to dc
while an inductor is a short circuit to dc
29
By voltage division
30
15
EE202-S24_w03_2
To find v2
We set to zero both the 5 V source and the 2 sin 5t
current source and transform the circuit to the
frequency domain
31
32
16
EE202-S24_w03_2
To find v3
We set the voltage sources two zero
33
34
17
EE202-S24_w03_2
v1 = -1 V
35
Source Transformation
36
18
EE202-S24_w03_2
37
38
19
EE202-S24_w03_2
39
By voltage division
40
20
EE202-S24_w03_2
41
Case 1:
If the network has no dependent sources, we turn off all independent
sources. ZTh is the input impedance of the network looking between
terminals a and b
42
21
EE202-S24_w03_2
Case 2:
If the network has dependent sources, we turn off all independent
sources
Dependent sources are not to be turned off because they are controlled
by circuit variables
43
44
22
EE202-S24_w03_2
45
To find VTH
Apply KVL
46
23
EE202-S24_w03_2
47
To find VTH
KCL at node 1
48
24
EE202-S24_w03_2
To obtain ZTh
KCL
49
50
25
EE202-S24_w03_2
51
52
26
EE202-S24_w03_2
For mesh 1
For supermesh
At supermesh
53
By current division
54
27
EE202-S24_w03_2
Op Amp Circuits
The three steps in circuit analysis stated previously also apply to op amp
circuits, as long as the op amp is operating in the linear region
Three steps:
Convert circuit to frequency domain
Circuit analysis
Convert back to time domain
55
28