VLSI Physical Design with Timing Analysis

Lecture – 49: Time Borrowing in Latch

Bishnu Prasad Das

Department of Electronics and Communication Engineering

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 Contents
• Timing borrowing in Latch

– 2-phase Latch

– Pulsed Latch

• Examples of timing Borrowing

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 Latch timing violation windows

Latch timing violation windows.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

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 1

2
1 2 1
Latch

Latch

Latch
Combinational
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across

half-cycle boundary pipeline stage boundary
1 2
Latch

Latch
Combinational
(b) Combinational Logic Logic

Loops may borrow time internally but must complete within the cycle

N. Weste and D. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 3rd Edition, Pearson Addison Wesley

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Timing Report with timing borrowing

J. Bhasker and R. Chadha, Static

timing analysis for nanometer
designs: A practical approach. 2009.

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Thank You

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