2202 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO.
3, MARCH 2022
Neutral-Point-Clamped Five-Level Inverter With
Self-Balanced Switched Capacitor
Yuanmao Ye , Member, IEEE, Teke Hua , Shaojun Chen , and Xiaolin Wang
Abstract—In this article, a new five-level inverter is de-
veloped by inserting a switched-capacitor (SC) unit into the
traditional three-level neutral-point-clamped (NPC) inverter
phase leg. The SC unit consists of two capacitors and
one bidirectional switch, all of which withstand a quarter
of the dc input voltage. While increasing the output lev-
els, the performance is also improved in terms of power
loss, common-mode voltage, switching stress dv/dt, and
output filter. Compared to other five-level inverters like the
conventional NPC and active NPC five-level topologies, the
new solution not only reduces the number of components
and simplifies the design but also has the advantage of
self-balanced capacitor voltages. The analysis, simulation,
and experiment indicate that the proposed inverter is suit-
able for a wide range of applications like renewable source
grid-connected interfaces and motor drivers. Simulation
and experimental results of grid-connected operation verify
that the new inverter is capable of providing both active
and reactive power to the grid. Its excellent performance
is also experimentally evaluated by a 1.2-kW prototype and
the measured efficiency is above 97% for a wide range of
load.
Index Terms—Multilevel inverter, neutral point clamped
(NPC), switched capacitor (SC).
I. INTRODUCTION
INCE Nabae et al. [1] invented the neutral-point-clamped
S (NPC) inverter in 1979, Meynard and Foch [2] invented the
flying capacitor (FC) inverter in 1992; the two types of inverters
have caused a substantial attention and they have already been
put into medium-voltage high-power motor drivers. In 1995,
a cascaded H-bridge inverter was also successfully developed
as high-power motor drivers [3], [4]. In addition, the modular
multilevel converter presented by Marquardt in 2003 is very
popular in HVdc applications [5]. Due to the inherent advan-
tages of near-sinusoidal output voltage waveforms, reduced
dv/dt switching stresses, less switching losses, etc., these classic
Manuscript received August 25, 2020; revised November 5, 2020,
January 14, 2021, and February 17, 2021; accepted March 5, 2021.
Date of publication March 23, 2021; date of current version Decem-
ber 6, 2021. This work was supported in part by the National Natural
Science Foundation of China under Grant 51907033 and in part by
the Natural Science Foundation of Guangdong Province under Grant
2020A1515110977. (Corresponding author: Xiaolin Wang.)
The authors are with the School of Automation, Guangdong
University of Technology, Guangzhou 510006, China (e-mail:
eeyeym@gdut.edu.cn; 761741767@qq.com; 956432498@qq.com;
xiaolinwang@gdut.edu.cn).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIE.2021.3066932.
Digital Object Identifier 10.1109/TIE.2021.3066932
0278-0046 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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multilevel inverters have been commercialized by manufacturers
[6]. However, some inherent drawbacks limit the increase in
the number of output levels of these multilevel circuits [7], [8].
For instance, in addition to eight active switches, NPC employs
12 clamping diodes and FC employs six clamping capacitors
for each phase of five-level configurations. And four dc-link
capacitors employed in the five-level NPC require auxiliary
circuits to balance their voltages [9]–[11]. Otherwise, a complex
neutral point voltage balance method must be developed [12].
To overcome the above drawbacks, several new topologies
of three-phase five-level inverters have been proposed in re-
cent years [13]–[24]. Specifically, the conventional active NPC
(ANPC) five-level inverter developed in [13] combines some
features of three-level ANPC and three-level FC. As shown
in Fig. 1(a), it consists of four high-voltage transistors S1 –S4
withstanding a voltage stress of 2E, four low-voltage transistors
S5 –S8 having a blocking voltage of E, and one FC Cf with a volt-
age of E. Similarly, other two types of ANPC are introduced in
[14]. As shown in Fig. 1(b) and (c), they are also developed based
on three-level ANPC and three-level FC. By replacing the two
transistors S7 and S8 in Fig. 1(c) with two diodes, a six-switch
five-level inverter topology is derived, as illustrated in Fig. 1(d)
[15]. In the three topologies, the high-voltage transistors S1 , S2
withstand a voltage stress of 3E. In order to use all transistors
with the same blocking voltage of E, each of S1 and S2 is replaced
with three transistors rated in the voltage of E and multiple FCs
are added in [16]. In contrast, the five-level nested neutral point
clamped (NNPC) inverter presented in [17] use two FCs and
two bidirectional switches. In fact, the total standing voltage
(TSV) of transistors in the NNPC is the same as the conventional
ANPC. The T-type NNPC five-level inverter presented in [18]
has one less bidirectional switch than the NNPC, but a more
complex control strategy is required. Overall, these new inverters
use fewer components than the traditional five-level NPC and
FC inverters. However, they still employ one or two FC(s) to
generate the levels of ±E. The capacitor voltages need to be
monitored and a complex control strategy is required to ensure
that the voltages are balanced at a quarter of the dc input voltage.
Recently, two boost-type ANPC five-level inverters are devel-
oped in [19] and [20] to output the levels of 0, ±2E, and ±4E.
The first one is shown in Fig. 1(g), which has a similar structure
to the conventional ANPC of Fig. 1(a) but both S5 and S6 are
connected in reverse. As a result, the capacitor CS used in this
circuit is actually a switched capacitor (SC) rather than an FC.
Specifically, CS is charged by the dc input voltage 4E through
the transistors S1 , S2 , S5 , and S6 when the inverter outputs the
YE et al.: NEUTRAL-POINT-CLAMPED FIVE-LEVEL INVERTER WITH SELF-BALANCED SWITCHED CAPACITOR
Fig. 1. Phase legs of various new five-level inverters. (a) Conventional
ANPC [13]. (b), (c) Other two types of ANPC [14]. (d) Six-switch ANPC
[15]. (e) NNPP [17]. (f) T-NNPC [18]. (g), (h) Boost-type ANPC [19], [20].
(i) Hybrid H-bridge NPP [22], [23]. (j) Hybrid H-bridge ANPC [24].
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2203
levels of ±2E. In addition to boost capability, therefore, the
inverter has the advantage of self-balanced capacitor voltage.
The second one is shown in Fig. 1(h); it is also based on the SC
technique, and there are two fewer switches than the first one. In
addition, the work in literature [21] presents another boost-type
five-level inverter having a similar structure to Fig. 1(h). Their
main problem is that the two switches S5 and S6 need to have
a bipolar voltage blocking capability so that active and reactive
powers cannot flow through them, simultaneously, for the states
of ±2E. Hence, a special control strategy is required for nonunity
power factor operation, as analyzed in [20].
Structurally, all these inverters aforementioned employ two
dc-link capacitors and four series-connected transistors and this
is very similar to the traditional three-level NPC. From the
point of view of industrial applications, it is more desirable if a
five-level inverter can be implemented by using the commercial
three-level NPC modules directly, because it is very helpful for
simplifying the design process and speeding up commercial-
ization. Unfortunately, none of the above five-level inverters
are derived directly from NPC, so commercial three-level NPC
modules cannot be used in these inverters.
In addition, a single-phase five-level asymmetric hybrid
H-bridge inverter formed by a half-bridge leg and a T-type leg
is presented in [22] and [23] to reduce the number of switching
devices, as shown in Fig. 1(i). And a hybrid five-level ANPC full-
bridge inverter is developed in [24] for single-phase applications,
as shown in Fig. 1(j). As each phase of the two inverters involves
two asymmetric legs, their three-phase extensions require six
legs. Hence, commercial three-level NPC modules also cannot
be used in the two inverters.
The motivation of this article is to derive a new five-level
inverter directly from the traditional three-level NPC topology,
by using the simplest auxiliary circuit. Based on this idea, a
new five-level inverter is developed by inserting an SC unit
into three-level NPC phase leg directly. The mature three-level
NPC modules can therefore be used to design the new five-
level inverter. In addition, self-balanced capacitor, simple circuit
structure and control strategy, reduced switching stress dv/dt,
low switching frequency, and reduced common-mode voltage
(CMV) are also the superiorities of this new inverter.
II. TOPOLOGY AND OPERATION
A. Circuit Description
The proposed five-level inverter is shown in Fig. 2. Its phase
leg is developed directly by inserting an SC unit into the tra-
ditional three-level NPC phase leg, which is formed by S1 –S4 ,
D1 , and D2 . The SC unit consists of two capacitors CS1 and CS2
and one bidirectional switch S5 , which is usually designed by
two antiseries connected transistors. A small inductor Lr may
be added to suppress the inrush charging current of SCs. It can
be considered as a wire in steady state and its effect will be
neglected in the following analysis.
The same as the three-level NPC, transistors S1 –S4 and diodes
D1 and D2 in the five-level inverter have a blocking voltage of 2E.
 2204 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 3, MARCH 2022

Fig. 2. Proposed three-phase five-level inverter.

TABLE I
SWITCHING STATES OF THE PROPOSED FIVE-LEVEL INVERTER

The voltages of S5 , CS1 , and CS2 are rated at a quarter of the dc

input voltage, i.e., E. Hence, the proposed five-level inverter can
be implemented by combining various commercial three-level
NPC modules with a low-voltage SC unit. This is very helpful
to reduce the design difficulty and speed up commercialization.

B. Operation Principle
To facilitate analysis, it is assumed that all components used
in the five-level inverter are ideal and all capacitors are so large
that their voltages can be seen as constant.
As shown in Fig. 2, there are five switches S1 –S5 employed
in each phase of the proposed inverter. At any time, only one
of S1 , S2 , and S5 is turned ON while the other two are OFF. The
two switches S3 and S4 operate in a complementary manner.
As a result, there are six operation states corresponding to five
output levels, as illustrated in Table I, wherein x = a, b, or c.
Note that 1 and 0 represent ON and OFF states of the related
switches, respectively. Capacitors’ states are indicated by “C,”
“D,” and “N,” which are indicative of charging, discharging, and
idle states, respectively. The state circuits and the voltage stress
of each OFF switch are illustrated in Fig. 3. The detailed analysis
is given as follows.
1) uO = 0: When the switches S2 and S3 are turned ON while
others are OFF, the capacitors CS1 and CS2 are charged
by the dc-link capacitor Cdc2 through the diode D1 , as
illustrated in Fig. 3(a), making the sum voltage of CS1 and
CS2 is the same as the capacitor Cdc2 , i.e., 2E. The output
level of 0 is therefore generated by the series connection
of CS1 , CS2 , and Cdc2 . Similarly, the level of 0 can also
be generated by turning ON S1 and S4 simultaneously, as
illustrated in Fig. 3(b). In the two states, the output current
can flow in both directions.
Fig. 3. State circuits of the proposed five-level inverters. (a), (b) uO =
0. (c) uO = +E. (d) uO = –E. (e) uO = +2E. (f) uO = –2E. ∗Note:  1 and
2 represent the switches’ voltage stresses of E and 2E, respectively.
2) uO = ±E: When the switches S3 and S5 are turned ON
while others are OFF, the output level of +E is provided
by the capacitor CS1 directly, as illustrated in Fig. 3(c).
Similarly, the level of –E is provided by CS2 through the
ON switches S4 and S5 , as illustrated in Fig. 3(d). In the
two states, the output current can flow out of or into the
capacitors to provide active and reactive power.
3) uO = ±2E: When the switches S1 and S3 are turned ON
while others are OFF, the output level of +2E is provided
by the dc-link capacitor Cdc1 directly, as illustrated in
Fig. 3(e). In this state, the capacitors CS1 and CS2 are also
charged by Cdc1 through the diode D2 . Moreover, both
active and reactive power can be provided by Cdc1 through
S1 –S3 or their freewheeling diodes. Similarly, the level
of –2E is provided by Cdc2 through the ON switches S2
and S4 , as illustrated in Fig. 3(f). Both active and reactive
power in this state can be provided by Cdc2 through S2 –S4
or their freewheeling diodes.

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YE et al.: NEUTRAL-POINT-CLAMPED FIVE-LEVEL INVERTER WITH SELF-BALANCED SWITCHED CAPACITOR 2205

C. Self-Balanced Capacitor Voltages

As illustrated in Table I and Fig. 3, the capacitors CS1 and CS2
are charged by the dc-link capacitors during the output levels of
±2E and 0. When the same capacitance is used for the two
capacitors, they have therefore the same original voltage of E.
In addition, CS1 discharges to the load during the level of +E,
whereas CS2 discharges to the load during the level of –E. It
means that the two capacitors play the same role in one cycle of
the output voltage and they operate alternately in charging and
discharging modes. Their voltages can therefore be balanced to
a quarter of the dc input voltage automatically, but with some
ripples. In addition, the dc-link capacitors Cdc1 and Cdc2 are
alternately connected in parallel with the connection of CS1 and
CS2 to charge them. This alternate operation makes the voltages
of Cdc1 and Cdc2 automatically equalize to half of the dc input
voltage.

III. PERFORMANCE ANALYSIS WITH PHASE DISPOSITION

PULSEWIDTH MODULATION (PD-PWM) STRATEGY
A. Modulation
For the proposed inverter, various modulation strategies like
space vector modulation (SVM) and multicarrier PWM can be
applied to control its output voltage.
Fig. 4(a) and (b) shows the modulation logic and the typical
waveforms of the proposed five-level inverter with PD-PWM
strategy. Four carrier signals u1 , u2 , u3 , and u4 are compared
with the reference signals uref˙x to generate the gating signals
VGS1–5 .

B. Switching Loss Reduction

Fig. 4(b) indicates that the sum switching frequency for the
transistors S1 and S2 is the same as the carriers’ frequency and
this is the same as the traditional three-level NPC. However,
the sum switching frequency for S3 and S4 is reduced to the
fundamental frequency resulting in little switching loss, whereas
that in the traditional three-level NPC is also the same as the
carriers’ frequency. Although the switching frequency of S5 is
the same as the carriers’ frequency, its blocking voltage is a
quarter of the dc input voltage. Hence, the switching loss of
S5 should be far less than that of S3 and S4 in the traditional
three-level NPC when the input voltage for both inverters is the
same. Overall, the proposed five-level inverter with PD-PWM
has lower switching loss than the traditional three-level NPC. Fig. 4. PD-PWM strategy for the proposed five-level inverter. (a) Mod-
ulation logic. (b) Typical waveforms.
C. CMV Improvement
With the input voltage of 4E, the CMVs for both the pro-
posed five-level inverter and the traditional three-level NPC are From (1), it is found that the proposed inverter theoretically
uniformly expressed by has 13 different levels for the CMV, which are 0, ±E/3, ±2E/3,
±E, ±4E/3, ±5E/3, and ±2E, whereas the three-level NPC’s
Sa + Sb + Sc CMV levels are 0, ±2E/3, ±4E/3, and ±2E. Hence, the variation
CMV = E (1)
3 of the CMV at each switching state is ±E/3 for the proposed
where the switching functions (Sa , Sb , Sc ) of the proposed five- five-level inverter and it corresponds to one-half of that in the
level inverter on the balanced load condition are “–2,” “–1,” “0,” three-level NPC (±2E/3).
“1,” and “2,” whereas that of the three-level NPC are “–2”, “0,” When the PD-PWM strategy is applied, all of Sa , Sb , and Sc
and “2.” will not be positive or negative at the same time, and any two of

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 2206 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 3, MARCH 2022

Fig. 6. Duty ratio of switch S5 in a positive half-cycle.

Fig. 5. Alternate charging and discharging operation of capacitors.
(a) In positive half-cycle. (b) In negative half-cycle.

where θ = sin–1 (1/2Ma ) is the angle when the reference signal

them will not be –2 or 2 at the same time. As a result, the CMV of reaches to 1 and Ma is the modulation ratio, ω = 2πfref is the
the proposed inverter practically has five different levels, which angular frequency, D is the duty ratio of switch S5 as illustrated
are 0, ±E/3, and ±2E/3, as illustrated in the bottom of Fig. 4(b). in Fig. 6, and it is given by
The CMV of the three-level NPC with the PD-PWM has also 
five different levels, but they are 0, ±2E/3, and ±4E/3. 2Ma sin (ωt) , ωt ∈ (0, θ) ∪ (π − θ, π)
D (t) = (3)
Summing up the above analysis, both the amplitude and the 2Ma sin (ωt) − 1, ωt ∈ (θ, π − θ)
variation at each switching state of the CMV for the proposed and the load current iO is given by
five-level inverter are reduced to one-half of that in the traditional
three-level NPC. This is beneficial to reduce the leakage current iO (t) = IO sin (ωt − ϕ) (4)
caused by the CMV for photovoltaic (PV) applications where
the PV cells are virtually connected to the ground through a where IO is the amplitude and ϕ is the angle between the output
leakage capacitor and resistor. Furthermore, the CMV can be current and the output voltage.
further reduced or even eliminated by using the improved SVM, When the load is a pure resistor R, the amplitude of the pulse
as analyzed in [25] and [26]. discharge current of CS1 in the positive half-cycle is E/R. In
this case, the amount of charge flowing out of CS1 during the
IV. DESIGN OF SC UNIT positive half-cycle can be further expressed by
 θ  π 
A. Capacitance Determination 2E ω 2ω
QCs1 = D (t) dt + (1 − D (t)) dt . (5)
Usually, capacitance is inversely proportional to voltage ripple R 0 θ
ω
across a capacitor. Hence, the first step for the SC design is
to estimate the capacitor voltage ripple. This section takes the Substituting (3) and θ = sin–1 (1/2Ma ) into (5), the expression
five-level inverter with PD-PWM as an example to design the can be derived as
 
value CS1,2 of the two SCs. 2E  −1 1
As illustrated in Fig. 5, CS1 and CS2 operate alternately in QCs1 = 2Ma + π − 4 Ma − 0.25 −2sin
2 .
ωR 2Ma
charging and discharging modes in the positive and negative (6)
half-cycles of the output voltage, respectively. Both of them In the positive half-cycle, CS2 not only never discharges
discharge to loads through the bidirectional switch S5 . Their but also charges together with CS1 , as illustrated in Fig. 5(a).
voltage ripples are therefore determined by the load current, the The voltage VCs2 therefore rises gradually making VCs1 fall
duty ratio of S5 , and the capacitance. accordingly. Under the premise that the total impedance of the
In the positive half-cycle, the switch S5 is turned ON when charging loop is very small and the voltage drops of switches
u2 < uS < u1 . The capacitor CS1 discharges to the load in pulses are ignorable, their sum voltage can be charged to 2E every
and the discharging current is equal to the instantaneous value time. It means that the two capacitors have the same voltage
of the load current iO . When the carriers’ frequency fC is far ripple in half-cycle of the output voltage. And the total amount
higher than the reference signal’s frequency fref , the amount of of charge flowing into CS2 during the positive half-cycle is half
charge flowing out of CS1 during the positive half-cycle can be of that flowing out of CS1 , i.e., QCs1 /2. Similar charging and
expressed by discharging processes also occur in the negative half-cycle. The
 θ/ω voltage ripple across the two capacitors is therefore expressed
QCs1 = (D (t) × iO (t)) dt by
0
 (π−θ)/ω QCs1
ΔVCs = . (7)
+ ((1 − D (t)) × iO (t)) dt 2Cs1,2
θ/ω
 π/ω Usually, the maximum voltage ripple should be limited to
+ (D (t) × iO (t)) dt (2) within a certain percentage of the capacitors’ rated voltage E,
(π−θ)/ω e.g., δ = ΔVCs /E is 5% or 10%, etc. Then, the capacitance C1,2

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YE et al.: NEUTRAL-POINT-CLAMPED FIVE-LEVEL INVERTER WITH SELF-BALANCED SWITCHED CAPACITOR 2207

Fig. 7. Capacitance versus the modulation ratio Ma when R = 25 Ω.

Fig. 9. Maximum inrush charging current Icr˙max versus the resonant
inductor Lr and the total parasitic resistance rcr . (a) rcr = 0.1 Ω, CS1,2
= 1000 µF, Ma = 0.9, fC = 10 kHz. (b) Lr = 0.1 µH, CS1,2 = 1000 µF,
Ma = 0.9, fC = 10 kHz.

SCs flowing through Lr varies in the following laws:

CS1,2
iLr (t) = icr (t) = s1 A1 es1 t + s2 A2 es2 t (9.1)
2
⎧ 
⎪
⎪ rcr 2
rcr 2
⎪
⎪
⎨ s1 = − 2L + 4L2 − L C
r r S1,2
 r (9.2)
⎪
⎪ r 2
rcr 2
⎪
⎪ s2 = − cr − −
Fig. 8. Operation of SCs with a small resonant inductor. (a) Discharg- ⎩ 2Lr 4L2r Lr CS1,2
ing path. (b) Sneak circuit. (c) Charging loop. (d) Voltage and current
variations. ⎧ s2
⎨ A1 = ΔVCs1
s1 − s2 (9.3)
⎩ A1 = s 1
ΔVCs1
s2 − s1
can therefore be determined by
where rcr is the total parasitic resistance of the charging loop of
  Fig. 1(c) and ΔVCs1 is the capacitor voltage gap as illustrated
1  1
CS1,2 ≥ 2Ma+π − 4 Ma2 − 0.25 − 2sin−1 . in Fig. 8(d).
δωR 2Ma The maximum voltage gap ΔVCs˙max occurs at the charging
(8)
cycle when the reference signal uref˙x reaches to 1. With a unit
It indicates that the capacitance is inversely proportional to
power factor, the maximum charging gap is expressed by
the load and the ripple ratio δ. More intuitively, Fig. 7 shows
the relationship of the capacitance CS1,2 versus the modulation iO D IO
Δ VCs_max = |u =1 = (10)
ratio Ma when the load R is fixed at 25 Ω. It indicates that CS1,2 fC ref_x 2Ma CS1,2 fC
higher modulation ratio results in smaller capacitance and the where IO is the amplitude of the output current.
largest capacitance is required when the modulation ratio locates Letting the derivative of charging current of (9.1) equal to
between 0.55 and 0.6. zero, i.e., dicr (t)/dt = 0, the maximum inrush charging current
amplitude can therefore be derived from (10) and it is given by

B. Inrush Charging Current Limitation IO s1 s2
Icr_max = (es1 Tr − es2 Tr ) (11)
The SCs operate alternately in charging and discharging 4Ma fC s1 − s1
modes at the carriers’ frequency. Especially, the discharging where Tr is the time when the charging current reaches to its
and charging paths of CS1 are shown in Fig. 8(a) and (c) for peak value and it is given by
the levels of +E and +2E. During a small deadtime inserted
1 s2
between the two operation states, in practice, the energy stored Tr = ln . (12)
in the resonant inductor Lr will be dissipated through the sneak s1 − s1 s1
circuit of Fig. 8(b). This complicates the operation of the inverter. As illustrated in Fig. 9(a), with the increase in the resonant
In order to minimize this negative effect, Lr should be so inductor, the inrush charging current amplitude drops slowly.
small that the stored energy can be dissipated immediately at In contrast, with the increase in the parasitic resistance rcr ,
switching instants. In practice, the small resonant inductor can the inrush charging current drops significantly, as depicted in
be implemented by utilizing stray inductances [28]. Fig. 9(b). Hence, the inrush charging current amplitude can be
As Lr is very small and large capacitance CS1,2 is used suppressed easily by the parasitic resistance rcr of the charging
to reduce the voltage ripple, the charging circuit of Fig. 8(c) loops, whereas the resonant inductor Lr is mainly used to sup-
operates in an overdamping manner. The charging current icr of press the current variation di/dt at switching instants. The slow

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 2208
Fig. 10. Initial charging circuit for SCs. (a) Initial charging stage.
(b) Normal operation stage.
TABLE II
COMPARISON RESULTS OF DIFFERENT FIVE-LEVEL INVERTERS (PHASE LEG)
Note: VG is the ratio of the maximum ac line voltage to the dc input voltage.
current change rate di/dt is helpful to reduce the switching loss
and improve the efficiency of the inverter.
As the SCs are charged by the dc-link capacitors through
the transistor S1 or S4 as well as the diode D1 or D2 , the
maximum charging current Icr˙max is also the current stress of
these switching components.
C. Initial Charging Circuit
Fig. 10 shows a phase leg of the proposed inverter with an
initial charging circuit for SCs. Before normal operation, the
two low-power single-pole double-throw switches labeled by K
select the position “1.” Both capacitors CS1 and CS2 are charged
to a quarter of the input voltage through the four voltage divider
resistors having the same value Rdc . During normal operation,
the two switches K select the position “1.” The resistor network
is divided into two groups to assist the voltage balance of the
two dc-link capacitors and the two SCs, respectively.
V. COMPARISON WITH OTHER FIVE-LEVEL INVERTERS
Table II lists a comparative study for phase legs of the pro-
posed topology and other five-level inverters in terms of the
numbers transistors (NT ), diodes (ND ), capacitors (NC ), the TSV
and the maximum blocking voltage (MBV) for switching com-
ponents, the total capacitors’ voltage (TCV), the cost function
(CF), the voltage gain (VG), and self-balance (SB) capability for
capacitor voltages. The CF introduced in [27] is used to evaluate
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 3, MARCH 2022
TABLE III
COMPARISON RESULTS FOR THE SAME OUTPUT VOLTAGE
PEAK (PHASE LEG)
TABLE IV
SPECIFICATION AND COMPONENTS OF THE SIMULATION MODELS
the cost per level of the ac output voltage and it is defined by
NT + ND + NC + α × TSV + β × TCV
CF = (13)
5
where α and β are coefficients and both are set to 1 in this article.
As all compared inverters employ two dc-link capacitors, this
item is therefore not compared in Table II.
The comparison results indicate that the four five-level ANPC
inverters’ phase legs shown in Fig. 1(a)–(d) have the advantages
of a single capacitor and lower CF. But the FC’s voltage needs
to be sensed for control with a complex algorithm. The same
problem is also found in the NNPP of Fig. 1(e) and the T-NNPC
of Fig. 1(f).
The asymmetric hybrid H-bridge-NPP of Fig. 1(i) has the
advantage of minimal components, but the four transistors in the
H-bridge are rated at the total dc input voltage. Hence, its three-
phase extension requires 12 high-voltage transistors to form 3
H-bridges. The four transistors S1 –S4 in the boost-type ANPC
of Fig. 1(h) are also rated at the total dc input voltage, but it has
boost capability.
As illustrated in Table IV, to get the same peak of the output
voltage, Fig. 1(h) has the same number of switches and the
same voltage rating of transistors as the proposed inverter. It
uses a single high-voltage capacitor CS , whereas the proposed
inverter uses two low-voltage capacitors CS1,2 . Hence, from the
perspective of circuit structure only, the topology of Fig. 1(h) is
slightly better than the proposed inverter as two lower voltage
diodes D1,2 are used in Fig. 1(h). However, the proposed inverter
is superior to Fig. 1(h) in the following aspects.
1) Various commercial three-level NPC modules can be used
to simplify the design process.
2) The significantly reduced charging voltage gap of SCs
when the modulation ratio is higher, as depicted in
Fig. 11(a). It is beneficial to reduce the inrush charging
current.
3) Less power addressed by SCs when the modulation ratio is
higher, as depicted in Fig. 11(b). It is beneficial to reduce
power loss of SCs.
YE et al.: NEUTRAL-POINT-CLAMPED FIVE-LEVEL INVERTER WITH SELF-BALANCED SWITCHED CAPACITOR
Fig. 11. Comparison of the proposed inverter with the boost-type
ANPC. (a) Maximum charging voltage gap ratio. (b) Power addressed
by SCs.
4) Greatly simplified modulation and control strategies, es-
pecially for nonunity power factor operation.
Overall, for the same output voltage and power, both five-level
inverters have their own advantages. Specifically, the boost-type
ANPC of Fig. 1(h) is more suitable for low input-voltage appli-
cations as it has boost capability, whereas the proposed inverter is
more suitable for medium and high input-voltage applications as
it has lower MBV, lower inrush charging current, and less power
loss of SCs. Hence, the proposed inverter is not a competitor
to the boost-type ANPC of Fig. 1(h), but an alternative of the
transitional five-level NPC, which requires auxiliary balancing
circuits to equalize the dc-link capacitors’ voltages as described
in [9] and [11].
VI. SIMULATION AND EXPERIMENTAL RESULTS
To verify the feasibility of the proposed inverter, both sim-
ulation and experimental results for three-phase operation are
provided in this section.
A. Simulation Results of Grid-Connected Operation
With the parameters of Table IV, three simulation models
for the three-level NPC, the proposed inverter, and the boost-
type ANPC shown in Fig. 1(h) were built in PLECS. All of
them are three-phase configuration and are regulated by a dual
closed-loop controller. As shown in Fig. 12, the measured grid
voltages ua,b,c and currents ia,b,c are transformed to the rotating
D–Q reference frame, i.e., ud,q and id,q . The current references
id ∗ and iq ∗ are generated by the power outer loop, whereas the
current inner loop is used to generate the voltage references
uref˙a,b,c for sinusoidal pulsewidth modulation (SWPM). With
this controller, the active power and reactive power are fully
decoupled and they can be regulated individually by changing
their given values P∗ and Q∗. In the boost-type ANPC and the
proposed inverter models, each SC is connected in series with a
small resistor 30 mΩ as its equivalent series resistance (ESR) to
analyze power loss, and a small inductor 1 μH is added to limit
inrush charging current spike. As the boost-type ANPC has a
VG of 2, its input voltage is set to half of the other two models.
Fig. 13(a) shows the steady-state simulation results of the pro-
posed inverter model when P∗ = 2000 W and Q∗ = 1000 VAR. It
is verified that the proposed inverter is capable of generating five
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2209
Fig. 12. Diagram of the PLECS simulation model for the proposed five-
level inverter with the grid-connected operation.
levels of output voltage and providing both active and passive
power to the grid simultaneously. All capacitor voltages are
balanced automatically. Fig. 13(b) shows the output voltage and
current of the three-level NPC model. The result indicates that
the proposed five-level inverter has a smaller output current’s
ripple than the three-level NPC. This is resulted from the reduced
dv/dt of the output voltage and it is beneficial to reduce the output
filter.
When the active power P∗ is fixed at 2000 W while the reactive
power is set to three different values of 0, 1000, and 2000 VAR,
Fig. 14 shows the power loss distribution in one phase leg of the
three simulation models. The values given in Fig. 14 are the total
power loss of components in one phase leg. It indicates that the
proposed inverter has less power loss than the other two models,
especially for high reactive power. In the proposed phase leg, as
the SC unit just provides a small part of output power, the main
power loss is caused by the conduction loss of the four transistors
S1 –S4 as well as the switching loss of S1 and S2 . In contrast, as
the main power of the boost-type ANPC is provided by the SC
circuit, its main power loss is caused by the SC and the charging
paths formed by D1 , D2 , S5 , and S6 . This is consistent with the
work in [20]. In addition, all components’ loss of the three-level
NPC leg grows along with the rise of reactive power making its
total loss increases dramatically. Especially, the switching loss
of S3 and S4 in the NPC is almost zero when the reactive power
is zero, but it increases along with the rise of reactive power. In
contrast, the switching loss of S3 and S4 in the proposed phase leg
is always close to zero as they operate in fundamental frequency.
Although S1 and S2 in both the NPC leg and the proposed phase
leg have the same blocking voltage and operate in the same
switching frequency, their switching loss in the proposed phase
leg is obviously lower than the NPC leg. The reason is that
switching stress dv/dt is reduced by half in the proposed five-
level inverter.
With the step change of output power, simulation results of
the proposed five-level inverter are shown in Fig. 15. It indicates
that the simulation model can effectively track the change of the
given values of active and reactive power. The output voltage is
 2210
Fig. 13. Simulation results for steady-state operation with direct power
control (P∗ = 2000 W and Q∗ = 1000 VAR). (a) Proposed inverter.
(b) Three-level NPC.
very stable, whereas the output current and its D–Q components
change along with the variation of power.
Fig. 16 shows the balancing process of capacitor voltages with
imbalanced initial values. When the initial voltages of the two
dc-link capacitors are set to 360 and 340 V, respectively, whereas
all SCs’ initial voltages are 175 V, the simulation results shown
in Fig. 16(a) indicate that the dc-link capacitors’ voltages are
balanced very soon. Fig. 16(b) shows the process when the two
dc-link capacitors’ initial voltages are 350 V, whereas the SCs’
initial voltages are set to 160 and 190 V for phase a, 165 and
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 3, MARCH 2022
Fig. 14. Phase leg’s power loss distribution of the proposed inverter,
the three-level NPC, and the boost-type ANPC.
185 V for phase b, and 155 and 195 V for phase c. The result
indicates that the voltage gap among SCs gradually narrows.
B. Experimental Results of Off-Grid Operation
A downscale prototype of the proposed five-level inverter was
built by referring to its simulation model given in the third col-
umn of Table IV. One difference is that the bidirectional switch
S5 was implanted by two antiseries MOSFETs IRFB4229PBF.
Additionally, as the limitation of experiment conditions, the
prototype was powered by 300 VDC and its output voltage
was set to 100 V. To withstand fluctuations in load and input
voltage, a simple voltage closed-loop proportional integral (PI)
digital controller was developed in TMS320F28335 to generate
the reference signals uref˙a,b,c and the PD-PWM is implemented
in an EP4CE6F17C8N field-programmable gate array (FPGA)
controller. The experiment bench is shown in Fig. 17.
Fig. 18 shows the steady-state waveforms of the prototype
with three pure resistive loads 25 Ω connected in “Y” structure.
The output phase voltages and line voltages shown in Fig. 18(a)
and (b) have five and nine different levels, respectively. This con-
firms the feasibility of the proposed topology. Fig. 18(c) shows
voltage waveforms of the switches S1 , S3 , and S5 employed in
one phase leg. Compared with the traditional three-level NPC,
although the blocking voltage of the switches S1 to S4 is still
half of the input voltage, the switching frequency of S3 and S4
falls to the fundamental frequency, and the switching stress dv/dt
of S1 and S2 is also reduced by half. This is very beneficial to
YE et al.: NEUTRAL-POINT-CLAMPED FIVE-LEVEL INVERTER WITH SELF-BALANCED SWITCHED CAPACITOR
Fig. 15. Simulation results with the step change of output power.
the reduction of switching loss as found in the simulation result.
Voltage waveforms of the dc-link capacitors and the SCs in one
phase are shown in Fig. 18(d). It indicates that the capacitor
voltages are very stable and be balanced automatically without
the use of auxiliary circuits and special control strategies. The
dc-link current iDC flowing through the transistors S1 and S2
of three phase legs and the input current iSource are shown in
the bottoms of Fig. 18(c) and (b), respectively. It indicates that
the inrush charging current of SCs reflected in iDC has been
effectively suppressed by parasitic resistances of components
and it is further absorbed by the dc-link capacitors, so there is
no huge spike in the input current iSource . In addition, the CMV
shown in the bottom of Fig. 18(a) varies among 0, ±25, and
±50 V, and the amplitude is one-sixth of the input voltage.
When the load is switched between 25 and 50 Ω, the output
voltage, current, and capacitor voltages of one phase are shown
in Fig. 19(a). To ensure the constant output voltage of 100 V, the
controller adjusts the modulation ratio to increase from 0.94 to
0.95 when the load drops from 50 to 25 Ω. The results indicate
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2211
Fig. 16. Balancing process of capacitor voltages. (a) Imbalanced initial
dc-link capacitor voltages. (b) Imbalanced initial SC voltages.
Fig. 17. Experimental bench of the proposed three-phase inverter
prototype.
that capacitor voltage ripples increase along with the output
current, but the inverter is very stable when the load changes
suddenly. In addition, when the load is fixed at 25 Ω but the input
voltage changes from 280 to 300 V, the experimental results are
shown in Fig. 19(b). It indicates that overmodulation occurred
when the input voltage is 280 V. Moreover, with the voltage
closed-loop controller, the modulation ratio drops along with the
rise of the input voltage resulting in the increase in the voltage
ripple of SCs. This is consistent with the theoretical analysis
given in (6) and (7).
Fig. 20 shows the capacitor voltages, the output voltage, and
current as well as their frequency spectrum when the prototype
is used to power an inductive load 50 Ω–50 mH. It indicates that
the output voltage is still a staircase PWM waveform. Its low
 2212
Fig. 18. Experimental results for a resistive load 25 Ω. (a) Output
phase voltages and the CMV. (b) Line voltages and input current. (c)
Switches’ voltages and dc-link current. (d) Capacitor voltages.
harmonic components are successfully eliminated by the PD-
PWM strategy and there are few low-order harmonics, whereas
high harmonic components are mainly distributed around the
carrier frequency 5 kHz and its integer multiple. In contrast, the
output current is almost pure sinusoidal. Its high harmonics are
successfully suppressed by the inductive load and there are few
third and fifth harmonics. Capacitor voltages are still very stable
and self-balanced.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 3, MARCH 2022
Fig. 19. Waveforms for transient response. (a) Step change of load
between 25 and 50 Ω. (b) Step change of the input voltage from 280 to
300 V.
Finally, the efficiency of the prototype was measured and
was also analyzed by using the PLECS simulation model with
300 VDC input voltage, 100 VRMS output voltage, and different
resistive loads. As depicted in Fig. 21, although the measured
efficiency is always lower than the simulation model, it is above
97% for a wide range of load. In the F3L75R07W2E3_B11
modules, actually, the blocking voltage of components is 650 V,
and the conduction voltage drops of each insulated gate bipolar
transistor (IGBT) and diode are 1.45 and 1.55 V, respectively.
The efficiency can therefore be improved by increasing the dc
input voltage for industrial applications.
C. Experimental Results of Grid-Connected Operation
Fig. 22 shows the experimental waveforms when the pro-
totype is connected to a low voltage grid. Here, the dc input
voltage is 160 VDC, the grid phase voltage is 35 VRMS, and
the filter’s inductance is 9.3 mH. The controller is designed by
referring to the simulation model of Fig. 12, wherein the dual
YE et al.: NEUTRAL-POINT-CLAMPED FIVE-LEVEL INVERTER WITH SELF-BALANCED SWITCHED CAPACITOR
Fig. 20. Experimental results for an inductive load 50 Ω–50 mH. (a)
Output voltage, current, and SC voltages. (b), (c) Frequency spectrum
of the output voltage and current.
Fig. 21. Efficiency versus the output power.
closed-loop controller was developed in TMS320F28335 and
the PD-PWM is implemented in an EP4CE6F17C8N FPGA
controller. The results demonstrate that the prototype is capable
of injecting both active and reactive power into the gird. The
inverter phase voltage waveforms of Fig. 22(a) and (b) indicate
that the modulation ratio is significantly different when the
reactive power changes from 0 to 100 VAR, whereas the active
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2213
Fig. 22. Experimental results for grid-connected operation. (a) P =
500 W and Q = 0. (b) P = 500 W and Q = 100 VAR.
power is constant at 500 W. This is resulted from the operation
of the dual closed-loop controller.
Fig. 23 shows the inverter’s output voltages and the current
flowing through one SC. It indicates that the inrush charging cur-
rent of SCs varies in overdamping manner. Both the amplitude
and the variation rate di/dt have been effectively suppressed by
the small resonant inductor and the parasitic resistance of the
charging loop.
VII. CONCLUSION
By inserting a low-voltage SC unit formed by a bidirectional
switch and a pair of capacitors into the conventional three-level
NPC phase leg, a new five-level inverter was developed in this
article. Compared to the conventional five-level NPC inverter, of
which dc-link capacitor voltages were equalized by using extra
balancing circuits or complex control algorithms, the new topol-
ogy reduces the number of components without compromising
the reactive power capability. In addition to the circuit topology
and operation principle, modulation, CMV, capacitance design,
inrush charging current, initial charging circuit, and comparative
study were analyzed in detail. The results of grid-connected
operation with direct power control showed that the inverter has
good performance such as self-balancing capacitor voltages, low
power loss, and fast transient response when injecting active
and reactive power into the grid. The results of the off-grid
operation with voltage closed-loop control demonstrated the
feasibility and high efficiency of the inverter. The good perfor-
mance for both grid-connection and off-grid operations showed
 2214 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 3, MARCH 2022
Fig. 23. Capacitor current waveforms with overdamping operation.
that the new five-level inverter is suitable for a wide range of
applications like renewable energy grid-connected systems and
variable-speed drive systems.
REFERENCES
[1] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped
PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523,
Sep. 1981.
[2] T. A. Meynard and H. Foch, “Multi-level conversion: High voltage chop-
pers and voltage source inverters,” in Proc. 23rd Annu. IEEE Power
Electron. Spec. Conf., Jun./Jul. 1992, pp. 397–403.
[3] F. Z. Peng, J. S. Lai, J. McKeever, and J. Van Coevering, “A multilevel
voltage-source inverter with separate DC sources for static VAr genera-
tion,” in Proc. IEEE Ind. Appl. Conf. 30th IAS Annu. Meeting, Orlando,
FL, USA, Oct. 8–12, 1995, pp. 2541–2548.
[4] P. W. Hammond, “A new approach to enhance power quality for medium
voltage drives,” in Proc. Ind. Appl. Soc. 42nd Annu. Petroleum Chem. Ind.
Conf., Sep. 11–13, 1995, pp. 231–235.
[5] R. Marquardt, “Modular multilevel converters: State of the art and future
progress,” IEEE Power Electron. Mag., vol. 5, no. 4, pp. 24–31, Dec. 2018.
[6] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A.
M. Prats, “The age of multilevel converters arrives,” IEEE Ind. Electron.
Mag., vol. 2, no. 2, pp. 28–39, Jun. 2008.
[7] J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of
topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49,
no. 4, pp. 724–738, Aug. 2002.
[8] H. Akagi, “Multilevel converters: Fundamental circuits and systems,”
Proc. IEEE, vol. 105, no. 11, pp. 2048–2065, Nov. 2017.
[9] K. Hasegawa and H. Akagi, “Low-modulation-index operation of a five-
level diode-clamped PWM inverter with a dc-voltage-balancing circuit for
a motor drive,” IEEE Trans. Power Electron., vol. 27, no. 8, pp. 3495–3504,
Aug. 2012.
[10] A. Taghvaie, M. E. Haque, S. Saha, and M. A. Mahmud, “A new step-
up switched-capacitor voltage balancing converter for NPC multilevel
inverter-based solar PV system,” IEEE Access, vol. 8, pp. 83940–83952,
2020.
[11] N. Hatti, Y. Kondo, and H. Akagi, “Five-level diode-clamped PWM
converters connected back-to-back for motor drives,” IEEE Trans. Ind.
Appl., vol. 44, no. 4, pp. 1268–1276, Jul./Aug. 2008.
Authorized licensed use limited to: SRM Institute of Science and Technology. Downloaded on January 24,2024 at 11:04:51 UTC from IEEE Xplore. Restrictions apply.
[12] K. Wang, Z. Zheng, L. Xu, and Y. Li, “Neutral-point voltage balancing
method for five-level NPC inverters based on carrier-overlapped PWM,”
IEEE Trans. Power Electron., vol. 36, no. 2, pp. 1428–1440, Feb. 2021.
[13] P. Barbosa, P. Steimer, L. Meysenc, M. Winkelnkemper, J. Steinke, and N.
Celanovic, “Active neutral-point-clamped multilevel converters,” in Proc.
36th IEEE Power Electron. Spec. Conf., 2005, pp. 2296–2301.
[14] T. B. Soeiro, R. Carballo, J. Moia, G. O. Garcia, and M. L. Held-
wein, “Three-phase five-level active neutral point clamped converters for
medium voltage applications,” in Proc. Brazilian Power Electron. Conf.,
Oct. 27–31, 2013, pp. 85–91.
[15] H. Wang, L. Kou, Y. F. Liu, and P. C. Sen, “A new six-switch five level
active neutral point clamped inverter for PV applications,” IEEE Trans.
Power Electron., vol. 32, no. 9, pp. 6700–6715, Sep. 2017.
[16] E. Burguete, J. López, and M. Zabaleta, “A new five-level active neutral-
point-clamped converter with reduced overvoltages,” IEEE Trans. Ind.
Electron., vol. 63, no. 11, pp. 7175–7183, Nov. 2016.
[17] J. Li, J. Jiang, and S. Qiao, “A space vector pulse width modulation for five-
level nested neutral point piloted converter,” IEEE Trans. Power Electron.,
vol. 32, no. 8, pp. 5991–6004, Aug. 2017.
[18] A. Bahrami and M. Narimani, “A new five-level T-type nested neutral
point clamped (T-NNPC) converter,” IEEE Trans. Power Electron., vol. 34,
no. 11, pp. 10534–10545, Nov. 2019.
[19] W. A. Pineda C. and C. Rech, “Modified five-level ANPC inverter with
output voltage boosting capability,” in Proc. 45th Annu. Conf. IEEE Ind.
Electron. Soc., Lisbon, Portugal, 2019, pp. 3355–3360.
[20] Y. P. Siwakoti, A. Palanisamy, A. Mahajan, S. Liese, T. Long, and F.
Blaabjerg, “Analysis and design of a novel six-switch five-level active
boost neutral point clamped inverter,” IEEE Trans. Ind. Electron., vol. 67,
no. 12, pp. 10485–10496, Dec. 2020.
[21] M. J. Sathik, Z. Tang, Y. Yang, K. Vijayakumar, and F. Blaabjerg, “A
new 5-level ANPC switched capacitor inverter topology for photovoltaic
applications,” in Proc. 45th Annu. Conf. IEEE Ind. Electron. Soc., Lisbon,
Portugal, 2019, pp. 3487–3492.
[22] S.-J. Park, F.-S. Kang, M. H. Lee, and C.-U. Kim, “A new single-phase
five-level PWM inverter employing a deadbeat control scheme,” IEEE
Trans. Power Electron., vol. 18, no. 3, pp. 831–843, May 2003.
[23] G. E. Valderrama, G. V. Guzman, E. I. Pool-Mazún, P. R. Martinez-
Rodriguez, M. J. Lopez-Sanchez, and J. M. S. Zuñiga, “A single-phase
asymmetrical T-type five-level transformerless PV inverter,” IEEE J.
Emerg. Sel. Topics Power Electron., vol. 6, no. 1, pp. 140–150, Mar. 2018.
[24] L. Zhang et al., “A Si/SiC hybrid five-level active NPC inverter with
improved modulation scheme,” IEEE Trans. Power Electron., vol. 35,
no. 5, pp. 4835–4846, May 2020.
[25] W. Li, X. Zhang, Z. Zhao, G. Zhang, G. Wang, and D. Xu, “Implementation
of five-level DPWM on parallel three-level inverters to reduce common-
mode voltage and AC current ripples,” IEEE Trans. Ind. Appl., vol. 56,
no. 4, pp. 4017–4027, Jul./Aug. 2020.
[26] Y. Yang et al., “Computation-efficient model predictive control with
common-mode voltage elimination for five-level ANPC converters,” IEEE
Trans. Transp. Electrific., vol. 6, no. 3, pp. 970–984, Sep. 2020.
[27] R. Barzegarkhoo, M. Moradzadeh, E. Zamiri, H. Madadi Kojabadi, and
F. Blaabjerg, “A new boost switched-capacitor multilevel converter with
reduced circuit devices,” IEEE Trans. Power Electron., vol. 33, no. 8,
pp. 6738–6754, Aug. 2018.
[28] Y. Ye and K. W. E. Cheng, “Analysis and optimization of switched capac-
itor power conversion circuits with parasitic resistances and inductances,”
IEEE Trans. Power Electron., vol. 32, no. 3, pp. 2018–2028, Mar. 2017.
Yuanmao Ye (Member, IEEE) received the
B.Sc. degree in electrical engineering from the
University of Jinan, Jinan, China, in 2007, the
M.Sc. degree in control science and engineer-
ing from the South China University of Tech-
nology, Guangzhou, China, in 2010, and the
Ph.D. degree in electrical engineering from
Hong Kong Polytechnic University, Hong Kong,
in 2016.
He is currently a Professor of Electrical Engi-
neering with the School of Automation, Guang-
dong University of Technology, Guangzhou. His research interests in-
clude multilevel inverters, battery management systems, and switched-
capacitor technique and its industrial applications.
YE et al.: NEUTRAL-POINT-CLAMPED FIVE-LEVEL INVERTER WITH SELF-BALANCED SWITCHED CAPACITOR 2215

Teke Hua was born in Shaoguan, China, in
1995. He received the B.Sc. degree in electrical
engineering from Guangdong Polytechnic Nor-
mal University, Guangzhou, China, in 2019. He
is currently working toward the M.Sc. degree in
electrical engineering with the Guangdong Uni-
versity of Technology, Guangzhou, China.
His research interests include multilevel
inverters, switched-capacitor converters, and
intelligent control for renewable energy power
generation.
systems, energy balancing system, distribution system planning, and
vehicle to grid.
Xiaolin Wang received the B.Sc. degree in
electrical engineering and automation from
China Three Gorges University, Yichang, China,
in 2012, and the M.Sc. and Ph.D. degrees
in electrical engineering from The Hong Kong
Polytechnic University, Hong Kong, in 2013 and
2018, respectively.
She is currently an Assistant Professor with
the School of Automation, Guangdong Univer-
sity of Technology, Guangzhou, China. Her re-
search interests include battery management

Shaojun Chen was born in Jieyang, China, in

1997. He received the B.Sc. degree in electrical
engineering, in 2020, from the School of Au-
tomation, Guangdong University of Technology,
Guangzhou, China, where he is currently work-
ing toward the M.Sc. degree in electrical engi-
neering, with Guangdong University of Technol-
ogy, Guangzhou, China.
His research interests include multilevel in-
verters, switched-capacitor power conversion
technique, and intelligent control for renewable
energy power generation.

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