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IPD50P04P4L11ATMA1
IPD50P04P4L11ATMA1
OptiMOS®-P2 Power-Transistor
Product Summary
V DS -40 V
R DS(on),max 10.6 mW
ID -50 A
Features
PG-TO252-3-313
• P-channel - Logic Level - Enhancement mode
• AEC qualified
T C=25°C,
Continuous drain current ID -50 A
V GS=-10V1)
T C=100°C,
-40
V GS=-10V2)
Thermal characteristics2)
Static characteristics
Gate threshold voltage V GS(th) V DS=V GS, I D=-85µA -1.2 -1.7 -2.2
V DS=-32V, V GS=0V,
Zero gate voltage drain current I DSS - -0.03 -1 µA
T j=25°C
V DS=-32V, V GS=0V,
- -7 -70
T j=125°C2)
Dynamic characteristics2)
Fall time tf - 39 -
Qg V GS=0 to -10V
Gate charge total - 45 59
Reverse Diode
V GS=0V, I F=-50A,
Diode forward voltage V SD - -1 -1.3 V
T j=25°C
V R=-20V, I F=50A,
Reverse recovery time2) t rr - 40 - ns
di F/dt =-100A/µs
1)
Current is limited by bondwire; with an R thJC = 2.6K/W the chip is able to carry 60A at 25°C.
2)
Specified by design. Not subject to production test.
3)
VGS=+5V/-16V according AEC; VGS=+16V for max 168h at TJ=175°C
4)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
70 60
60
50
50
40
40
P tot [W]
-I D [A]
30
30
20
20
10
10
0 0
0 50 100 150 200 0 50 100 150 200
T C [°C] T C [°C]
1000 101
1 µs 0.5
0
10
10 µs
100
0.1
100 µs
Z thJC [K/W]
0.05
-I D [A]
10-1
0.01
1 ms
10
1 10-3
0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100
-V DS [V] t p [s]
200 20
-10 V -5 V
180 -4V
-4.5V
160
140
-4.5 V -5V
15
120
R DS(on) [mW]
-I D [A]
100
-4 V
80
10
60
-10V
-3.5 V
40
20 -3 V
0 5
0 1 2 3 4 5 6 0 30 60 90 120 150 180
-V DS [V] -I D [A]
160 14
140 13
12
120
11
100
R DS(on) [mW]
10
-I D [A]
80
9
60
8
40
175 °C 7
20 25 °C -55 °C
6
0
5
1 2 3 4 5
-60 -20 20 60 100 140 180
-V GS [V]
T j [°C]
2.5 104
2.25 Ciss
2 Coss
C [pF]
10
-850µA
1.75
-V GS(th) [V]
1.5 -85µA
1.25
102
1 Crss
0.75
0.5 101
0 5 10 15 20 25 30
-60 -20 20 60 100 140 180
T j [°C] -V DS [V]
103 45
44
43
42
102
41
-V BR(DSS) [V]
-I F [A]
40
39
101
175 °C 25 °C 38
37
36
100 35
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -60 -20 20 60 100 140 180
-V SD [V] T j [°C]
10
V GS
9
Qg
8
8V
7 32V
6
-V GS [V]
4 V g s(th)
2
Q g (th) Q sw Q gate
1
Q gs Q gd
0
0 10 20 30 40 50
Q gate [nC]
Published by
Infineon Technologies AG
81726 Munich, Germany
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties
of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact
the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the
express written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Revision History