SRAM DRAM © It stores informationas long as the © It stores informationas long as the power is supplied. power is supplied or a few milliseconds when power is switched off. * Transistors are used to store + Capacitors are used to store data in information in SRAM. DRAM. © Capacitors are not used hence no * To store information for a longer refreshing is required time, contents of the capacitor needs to be refreshed periodically. ‘SRAM is faster as compared to * DRAM provides slow access speeds. DRAM. * It does not have refreshing unit. *_Ithavea refreshing unit. «These are expensive «These are cheaper. *_ SRAMSs are low density devices. +_DRAMs are high density devices. ‘+ In this bits stored in voltage form * In this bits stored in the form of electric energy. «These are used in cache memories. «These are used in main memories. There are mainly 5 types of DRAM : 1. Asynchronous DRAM (ADRAM) — The DRAM described above is the asynchronous type DRAM. The timing of the memory device is controlled asynchronously. A specialized memory controller circuit generates the necessary control signals to control the timing. The CPU must take into account the delay in the response of the memory. 2. Synchronous DRAM (SDRAM) — These RAM chips’ access speed is directly synchronized with the CPU's clock. For this, the memory chips remain ready for operation when the CPU expects them to be ready. These memories operate at the CPU-memory bus withoutimposing wait states. SDRAMis commercially available as modules incorporating multiple SDRAM chips and forming the required capacity for the modules. 3. Double-Data-Rate SDRAM (DDR SDRAM) - This faster version of SDRAM performs its operations on both edges of the clock signal; whereas a standard SDRAM performs its operations on the rising edge of the clock signal. Since they transfer data on both edges of the clock, the data transfer rate is doubled. To access the data at high rate, the memory cells are organized into two groups. Each group is accessed separately. 4. Rambus DRAM (RDRAM) — The RDRAM provides a very high data transferrate over a narrow CPU memory bus. It uses various speedup mechanisms, like synchronous memory interface, caching inside the DRAM chips and very fast signal timing. The Rambus data bus width is 8 or 9 bits. 5. Cache DRAM (CDRAM) — This memory is a special type DRAM memory with an on-chip cache memory (SRAM) that acts as a high-speed butfer for the main DRAM.RISC Itis a Reduced Instruction Set Computer. It emphasizes on software to optimize the instruction set. Itis a hard wired unit of programming in the RISC Processor. It requires multiple register sets to store the instruction. RISC has simple decoding of instruction Uses of the pipeline are simple in RISC It usesa limited number of instruction that requires less time to execute the instructions. It uses LOAD and STORE that are independentinstructions in the register-to- register a program's interaction. RISC has more transistors on memory registers, The execution time of RISC is very short RISC architecture can be used with high- end applications like telecommunication, image processing, video processing, ete It has fixed format instruction The program written for RISC architecture needs to take more space in memory. Example of RISC: ARM, PA-RISC, Power Architecture, Alpha, AVR, ARC and the SPARC. Flag register | cise Itis a Complex Instruction Set Computer. It emphasizes on hardware to optimize the instruction set. Microprogramming unitin CISC Processor. It requires a single register set to store the instruction. CISC has complex decoding of instruction Uses of the pipeline are difficultin CISC. It uses a large number of instruction that requires more time to execute the instructions. Ituses LOAD and STORE instruction in the memory-to-memory interaction of a program. CISC has transistors to store complex instructions. The execution time of CISC is longer. CISC architecture can be used with low-end applications like home automation, security system, etc. It has variable format instruction. Program written for CISC architecture tends to take less space in memory Examples of CISC: VAX, Motorola 68000 family, System/360, AMD and the Intel x86 CPUs. (a)Status FlagsZero Flag (Z): When an arithmetic operation results in zero, the flip- flop called the Zero flag — which is set to one, Carry flag (CY): After an addition of two numbers, if the sum in the accumulator is larger than eight bits, then the flip-flop uses to indicate a carry called the Carry flag, which is set to one. Parity (P): If the result has an even number of 1s, the flag is set to 1; for an odd number of 1s the flag is reset. Auxiliary Carry (AC): In an arithmetic operation, when a carry is generated from lower nibble and passed on to higher nibble then this register is set to 1. Sign flag(S): It is a single bit in a system status (flag) register used to indicate whether the result of the last mathematical operation resulted in a value in which the most significant bit was set.(b) Control Flags Trap Flag (TF): Itsets to enable one step execution of program. This is used for debug purpose. Interrupt Flag (IF): It is used to enable or disable interrupt during execution. Direction Flag (DF): The direction flag is a flag that controls the left-to- right or right-to-left direction of string processing. Registers Accumulator: Stores the results of calculations made by ALU. Program Counter (PC) Keeps track of the memory location of the next instructions to be dealt with. The PC then passes this next address to Memory Address Register (MAR). Memory Address Register (MAR): It stores the memory locations of instructions thatneed to be fetched from memory or stored into memory. Memory Data Register (MDR): It stores instructions fetched from memory or any data that is to be transferred to, and stored in, memory. Current Instruction Register (CIR): It stores the most recently fetched instructions while itis waiting to be coded and executed. Instruction Buffer Register (IBR): The instruction thatis notto be executed immediately is placed in the instruction bufferregister IBR. Pipelining is a process of arrangement of hardware elements of the CPU such thatits overall performance is increased. Simultaneous execution of more than one instruction takes place in a pipelined processor. RISC processor has 5 stage instruction pipeline to execute all the instructionsin the RISC instruction set. Following are the 5 stages of RISC pipeline with their respective operations: Stage 1 (Instruction Fetch) In this stage the CPU reads instructions from the address in the memory whose value is present in the program counter. Stage 2 (Instruction Decode) in this stage, instruction is decoded and the register file is accessed to get the values from the registers used in the instruction. Stage 3 (Instruction Execute) In this stage, ALU operations are performed Stage 4 (Memory Access) In this stage, memory operands are read and written fromvto the memory thatis present in the instruction. Stage 5 (Write Back) In this stage, computed/fetched value is written back to the register present in the instructions.Gache Memory Cache Memory is a special very high-speed memory. It is used to speed up and synchronizing with high-speed CPU. Levels of memory: Level 1 or Register, Level 2 or Cache memory, Level 3 or Main Memory, Level 4 or Secondary Memory. Hit ratio = hit/ (hit+ miss) = no. of hits/total accesses Cache Mapping: There are three differenttypes of mapping used for the purpose of cache memory which is as follows: Direct mapping, Associative mapping, and Set-Associative mapping. Direct Mapping — Maps each block of main memory into only one possible cache line. Ifa line is previously taken up by a memory block and a new block needs to be loaded, the old block is trashed, An address space is split into two parts index field anda tag field, The caches used to store the tag field whereas the rest is stored in the main memory.Associative Mapping —A block of main memory can map to any line of the cache thats freely available at that moment. The word offset bits are used to identify which word in the block is needed, all of the remaining bits become Tag. Set- Associative Mapping —Cachelines are grouped into sets where each set containsk numberof lines anda particular block of main memory can map to only one particular set of the cache. However, within thatset, the memory block can map to any freely available cache line. Memory hierarchy a Ll = \Magnetic Tape Magnetic tape is a plastic tape with magnetic coating. It is a storage medium on a large open reel or in a smaller cartridge or cassette (like a music cassette). Magnetic tapes are cheaper storage media. They are durable, can be written, erased, and re-written. Magnetic tapes are sequential access devices, which mean that the tape needs to rewind or move forward to the location where the requested data is positioned in the magnetic tape. Due to their sequential nature, magnetic tapes are not suitable for data files that need to be revised or updated often. They are generally used to store back-up data that is not frequently used orto transfer data from one system to other. The working of magnetic tape » Magnetic tape is divided horizontally into tracks (7 or 9) and vertically into frames. A frame stores one byte of dala, anda track in a frame stores one bit. Data is stored in successive frames as a string with one data (byte) per frame. » Data is recorded on tape in the form of blocks, where a block consists of a group of data also called as records. Each block is read continually. There is an Inter-Record Gap (IRG) between two blocks that provides time for the tape to be stopped and started between records. » Magnetic tape is mounted on a magnetic tape drive for access. The basic magnetic tape drive mechanism consists of the supply reel, take-up reel, and the read/write head assembly. The magnetic tape moves on tape drive from the supply reel to take-up reel, with its magnetic coated side passing over the read/write head, » Tapes are categorized based on their width - % inch, % inch, etc. » The storage capacity of the tape varies greatly. A 10-inch diameterreel of tape which is 2400 feet long can store up to 180 million characters. The features of magnetic tape are + Inexpensive storage device + Can store a large amountof data + Easy to carry or transport + Not suitable for random access data + Slow access device + Needs dust prevention, as dust can harm the tape + Suitable forback-up storage or archivingstruction cycle The Fetch Cycle At the beginning of the fetch cycle, the address of the nextinstruction to be executed is in the Program Counter(PC). The Indirect Cycles Once an instruction is fetched, the next step is to fetch source operands. Source Operand is being fetched by indirect addressing it can be fetched by any addressing mode, here its done by indirect addressing). Register-based operands need not be fetched. Once the opcode is executed, a similar process may be needed to store the result in the main memory. The Execute Cycle The other three cycles(Fetch, Indirect and Interrupt) are simple and predictable. Each of them requires a simple, small and fixed sequence of micro-operations. In each case, the same micro-operation is repeated each time around. Execute Cycleis different from them. Like, for a machine with N different opcodes there are N different sequences of micro-operations that can occur. The Interrupt Cycle: At the completion of the Execute Cycle, a test is made to determine whether any enabled interrupt has occurred or not. if an enabled interrupthas occurred then Interrupt Cycle occurs. The nature of this cycle varies greatly from one machine to another. DMA controller provides an interface between the bus and the inputoutput devices. Although ittransfers data without intervention of processor, itis controlled by the processor. The processor initiates the DMA controller by sending the starting address, Number of words in the data block and direction of transfer of data ‘i.e. from VO devices to the memory or from main memory to 1/O devices, More than one extemal device can be connected to the DMA controller.DMA controller contains an address unit, for generating addresses and selecting I/O device for transfer. It also contains the control unitand data countfor keeping counts of the number of blocks transferred and indicating the direction of transfer of data. When the transferis completed, DMA informs the processor by raising an interrupt.Types of DMA transfer modes Burst Mode - In burst mode, a whole block of data is shared in one contiguous sequence. Since the DMA controlleris allowed access to the system buses by the CPU, it sends all bytes of data in the data block earlier yield control of the system buses back to the CPU. This mode is beneficial for loading programs or data records into memory, butit does provide the CPU inactive for associatively long periods. Cycle Stealing mode - In cycle stealing mode, the DMA controller gets access to the system buses as in burst mode, using the BR and BG signals. It can share one byte of information and then de-asserts BR, retuming control of the system buses to the CPU. It already issues requests via BR, sharing one byte of information per request, just before it has shared its whole block of data. Transparent Mode - Transparent mode needed the most time to share a block of data, yet it is also important in terms of whole system performance. In transparentmode, the DMA controller only shares data when the CPU is implementing operations that do not use the system buses. Asynchronous mode of data transfer is used in which two componenthave a different clock. Data transfer can occur between data in two ways serial and parallel. In case of parallel multiple lines are used to senda single bit whereas in serial transfer each bit is send oneat a time. To tell other devices when the character/data will be given a concept of start and end bit is used. A start bit is denoted by 0 and stop bit is detected when line retum to 1-state at least onetime, here 1-state means that there is no data transfer is occurring. When a character is not being sentthen line is kept in state 1 Start of character is detected when a0 is sent. The character bit always come after 0 bit. After last bit is sentthe state of line to become 1 Serial Parallel Require single line to send data Require multiple line Less error and simple model Error prone and complex working Economical Expensive Slower data transfer Faster data transfer Used for long distance used for short distance Example:Computer to Computer Example:Computer to PrinterHardwired vis Micro-programmed Control Unit Hardwired Control Unit — Fixed logic circuits that correspond directly to the Boolean expressions are used to generate the control signals. Hardwired control is faster than micro-programmed control. A controller that uses this approach can operate at high speed RISC architecture is based on hardwired control unit. Micro-programmed Control Unit - The control signals associated with operations are stored in special memory units inaccessible by the programmer as Control Words. Control signals are generated by a program are similarto machine language programs. Micro-programmed control unitis slower in speed because of the time it takes to fetch microinstructions from the control memory. There are two type Micro-programmed control Unit: Horizontal Micro-programmed control Unit- The control signals are represented in the decoded binary format thatis 1 bit/CS. Vertical Micro-programmed control Unit — The control signals re represented in the encoded binary format. For N control signals- Logn(N) bits are required. Programmed 0 The input/output (I/O) architecture is computer system's interface tothe outside world. Each /O module interfaces to the system bus and controls one or more peripheral devices. There are three basic forms of inputand outputsystems — Programmed I/O: In programmed I/O, the processor executes a program that gives its direct control of the /O operation, including sensing device status, sending a read or write command, and transferring the data. Interrupt driven V/O: In interrupt driven VO, the processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when the I/O module completes its work. Direct Memory Access(DMA): In Direct Memory Access (DMA), the I/O module and main memory exchange data directly without processor involvement