Experiment No.

06

AIM: To study and verify D and J-K Flip-Flop using their respective ICs.

APPARATUS:
1. Logic Gates Trainer board having IC’s 7400(4011)
2. Connecting wires.

Features of trainer Kit:

1. Built in regulated DC power supply
2. Power supply: voltage range AC 100V – 230V, Frequency 50Hz.

THEORY:

D Flip flop:
D flip flop is an electronic device that is known as “delay flip flop” or “data flip flop” which
is used to store single bit of data. D flip flops are synchronous or asynchronous. The clock
signal is required for the synchronous version of D flip flops but not for the asynchronous
one. The D flip flop has two inputs, data and clock input which controls the flip flop as shown
in Fig. 6.1. When clock input is high, the data is transferred to the output of the flip flop and
when the clock input is low, the output of the flip flop is held in its previous state.

Figure 6.1: D Flip flop

J-K Flip flop:

The JK Flip Flop is the most widely used flip flop. It is considered to be a universal flip-flop
circuit. The sequential operation of the JK Flip Flop is the same as for the RS flip-flop with the
same SET and RESET input. The difference is that the JK Flip Flop does not the invalid input
states of the RS Latch (when S and R are both 1).

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.

The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q’ as

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 Experiment No. 06

shown in Fig. 6.2. This cross coupling of the SR flip-flop allows the previously invalid condition
of S = “1” and R = “1” state to be used to produce a “toggle action” as the two inputs are now
interlocked.

If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the
lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status
of Q through the upper NAND gate. As Q and Q are always different, we can use them to
control the input. When both inputs J and K are equal to logic “1”, the JK flip flop toggles as
shown in Fig. 6.3 of truth table.

Figure 6.2: J-K Flip flop, symbol and circuit

Figure 6.3: Truth table of JK Flip Flop

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 Experiment No. 06

Figure 6.4 Trainer Kit for D and J-K flipflop

PROCEDURE:
1. Select any gate on the trainer board (as shown in Fig. 6.4) for truth-table analysis.
2. Connect the input terminals of the gate from trainer board input section.
3. Connect the output terminal of gate to output section of trainer board.
4. Switch on the power supply.
5. Vary the inputs of gate i.e. high or low and note down the output.
6. Draw the table and verify it from truth table of the gate.

Experiment with breadboard:

Components Required:

S. No. Components Specifications Quantity

1. Breadboard --- 1
2. IC 4011 IC, 7400 2
3. Resistances 1KΩ-10KΩ 1
4. LED --- 2
5. Jumper wires --- 5-10
6. Power supply --- 1
7. Voltmeter 1
8. Multimeter 1

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 Experiment No. 06

PROCEDURE:
1. Insert the LED, resistor, and a chip of any logic gate into the right half of the
breadboard, as shown in the Fig. 6.5. Make sure the notch in the chip is on the top,
and make sure the longer lead of the LED is on the left.

Figure 6.5: Breadboard Connections for D Flip flops

Figure 6.6: Breadboard Connections for J-K flip flops

2. Connect the outputs for switches 1 and 2 to the inputs of the 4011 IC .
3. Connect the output from the 4011 IC to the LED.
4. Connect the chip’s power and ground inputs to the + and – columns of the breadboard,
respectively.
5. Reconnect the power supply to the breadboard.
6. Complete the following truth table for every logic gate.

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 Experiment No. 06

Switch 1 Switch 2 LED

0 0
1 1

7. Disconnect the power from the breadboard again.

8. Carefully remove the chip using the chip extractor tool.

PRECAUTIONS:
1. The connections should be neat and tight.
2. Do not switch ON the trainer board without checking and verifying the connections.
3. It should be ensured that the applied voltage do not exceed the ratings of trainer board
(Maximum by 2V).
4. Read all instructions carefully before starting of the experiment.
5. The jumper wires should be connected in according to circuit for accurate output.

CONCLUSION: In this experiment the D and J-K flip flop were thoroughly studied and truth
table has been verified.

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