Basic Computer Organization and Design

Draw registers organization with memory bank. Give list of

Basic computer register with their Size and Range. OR Explain
Registers of basic computer.

 The data register (DR) holds the operand read from memory.
 The accumulator (AC) register is a general purpose processing register.
 The instruction read from memory is placed in the instruction register (IR).
 The temporary register (TR) is used for holding temporary data during the
processing.
 The memory address register (AR) has 12 bits.
 The program counter (PC) also has 12 bits and it holds the address of the next
instruction be read from memory.
 The input register (INPR) receives an 8-bit character from an input device.
The output register (OUTR) holds an 8-bit character for an output device.
Give the list of Memory Reference Instruction. Explain
any Three of It

AND to AC
This is an instaruction that perform the AND logic operation on pairs of bits in AC
and the memory word specified by the effective address. The result of the operation
is transferred to AC . The microoperations that execute this instruction are:

D0T4:DR<-M[AR]
D0T5:AC<-AC/\DR, SC<---0

The control function for this instruction uses the operation decoder D0 since this
output of the decoder is active when the instruction has an AND operation whose
binary code value 000. Two timing signals are needed to execute the instaruction.
The clock transition associared with timing signal T4 transfers the operand from
memory into DR . The clock transition associated with the next timing signal T5
transfers to AC the result of the AND logic operation between the contents of DR
and AC. The same clock transition clears SC to 0, transferring control to timing
signal T0 to start a new instruction cycle.

ADD to AC
This instruction adds the content of the memory word specified by the effective
address to the value of AC . The sum is transferred into AC and the output carry
Cout is transferred to the E (extended accumulator) flip-flop. The rnicrooperations
needed to execute this instruction are
D1T4:DR←M[AR]
D1T5: AC← AC + DR, E← Cout , SC ← 0
Same Two timing signals, T, and T5, are used again but with operation decoder D1
instead of D0, which was used for the AND instruction. After the instruction is
fetched from memory and decoded, only one output of the operation decoder will be
active, and that output determines the sequence of microoperations that the control
follows during the execution of a memory-reference instruction.

LDA: Load to AC

This instruction transfers the memory word specified by the effective address to AC.
The microoperations needed to execute this instruction are

D2T4: DR← M[AR]

D2T5: AC← DR, SC← 0

Looking back at the bus system shown in Fig. 5-4 we note that there is no direct path
from the bus into AC . The adder and logic circuit receive information from DR which
can be transferred into AC . Therefore, it is necessary to read the memory word into
DR first and then transfer the content of DR into AC . The reason for not connecting
the bus to the inputs of AC is the delay encountered in the adder and logic circuit. It
is assumed that the time it takes to read from memory and transfer the word through
the bus as well as the adder and logic circuit is more than the time of one clock cycle.
By not connecting the bus to the inputs of AC we can maintain one clock cycle per
microoperation.

STA: Store AC
This instruction stores the content of AC into the memory word specified by the
effective address. Since the output of AC is applied to the bus and the data input of
memory is connected to the bus, we can execute this instruction with one
microoperation:

D3T4: M [AR] ← AC, SC ← 0

Explain BSA Instruction

This instruction is useful for branching to a portion of the program called a

subroutine or procedure. When executed, the BSA instruction stores the address of
the next instruction in sequence (which is available in PC) into a memory location
specified by the effective address. The effective address plus one is then transferred
to PC to serve as the address of the first instruction in the subroutine. This operation
was specified in Table 5-4 with the following register transfer:

M[AR] <-- PC, PC <-- AR + I

A numerical example that demonstrates how this instruction is used with a

subroutine is shown in Fig. 5-10. The BSA instruction is assumed to be in memory at
address 20. The I bit is 0 and the address part of the instruction has the binary
equivalent of 135. After the fetch and decode phases, PC contains 21, which is the
address of the next instruction in the program (referred to as the return address). AR
holds the effective address 135. This is shown in part (a) of the figure. The BSA
instruction performs the following numerical operation:

M[135] <-- 21, PC <-- 135 + 1 = 136

The result of this operation is shown in part (b) of the figure. The return address 21
is stored in memory location 135 and control continues with the subroutine program
starting from address 136. The return to the original program (at address 21) is
accomplished by means of an indirect BUN instruction placed at the end of the
subroutine. When this instruction is executed, control goes to the indirect phase to
read the effective address at location 135, where it finds the previously saved address
21. When the BUN instruction is executed, the effective address 21 is transferred to
PC . The next instruction cycle finds PC with the value 21, so control continues to
execute the instruction at the return address.
Draw the Flow-Chart of Memory Reference
Instruction

Define Register Reference Instruction

The register reference instructions are identified by the operation code 111 with a 0 in
the leftmost bit (bit 15) of the instruction. It determines an operation on or a test of
the AC register. An operand from memory is not required because the additional 12
bits are used to determine the operation or test to be implemented.
Explain Register reference register

Register-reference instructions are recognized by the control when 07 = 1 and I = 0.

These instructions use bits 0 through 11 of the instruction code to specify one of 12
instructions. These 12 bits are available in IR(0-11). They were also transferred to AR
during time T2•
The control functions and microoperations for the register-reference instructions
are. listed in Table 5-3. These instructions are executed with the clock transition
associated with timing variable T3• Each control function needs the Boolean relation
D7I'T3, which we designate for convenience by the symbol r. The control function is
distinguished by one of the bits in IR(0-11). By assigning the symbol B, to bit i of IR,
all control functions can be simply denoted by rB;.
The first seven register-reference instructions perform clear, complement, circular
shift, and increment microoperations on the AC or E registers. The next four
instructions cause a skip of the next instruction in sequence when a stated condition
is satisfied.
The skipping of the instruction is achieved by incrementing PC once again (in
addition, it is being incremented during the fetch phase at time T1).
The condition control statements must be recognized as part of the control
conditions. The AC is positive when the sign bit in AC(IS) = 0; it is negative when
AC(IS) = I. The content of AC is zero (AC = 0) if all the flip-flops of the register are
zero. The HLT instruction clears a start-stop flip-flop S and stops the sequence
counter from counting. To restore the operation of the computer, the start-stop flip-
flop must be set manually.
Define and Explain Input-Output Register
These instructions are for communication between computer and outside
environment. The IR(14 – 12) is 111 (differentiates it from memory reference) and
IR(15) is 1 (differentiates it from register reference instructions). The rest 12 bits
specify I/O operation.

The input register INPR consists of eight bits and holds an alphanumeric input
information. The 1-bit input flag FGI is a control flip-flop. The flag bit is set to 1 when
new information is available in the input device and is cleared to 0 when the
information is accepted by the computer. The flag is needed to synchronize the timing
rate difference between the input device and the computer. The process of
information transfer is as follows. Initially, the input flag FGI is cleared to 0. When a
key is struck in the keyboard, an 8-bit alphanumeric code is shifted into INPR and
the input flag FGI is set to 1. As long as the flag is set, the information in INPR cannot
be changed by striking another key. The computer checks the flag bit; if it is 1, the
information from INPR is transferred in parallel into AC and FGI is cleared to 0. Once
the flag is cleared, new information can be shifted into INPR by striking another key.
The output register OUTR works similarly but the direction of information flow is
reversed. Initially, the output flag FGO is set to 1. The computer checks the flag bit; if
it is 1, the information from AC is transferred in parallel to OUTR and FGO is cleared
to 0. The output device accepts the coded information, prints the corresponding
character, and when the operation is completed, it sets FGO to 1. The computer does
not load a new character into OUTR when FGO is 0 because this condition indicates
that the output device is in the process of printing the character.
Draw and explain Control unit of Basic computer
system

The block diagram of the control unit is shown in above figure. Components of
Control unit are
 Two decoders
 A sequence counter
 Control logic gates

 A Hard-wired Control consists of two decoders, a sequence counter, and a number of logic gates.
 An instruction fetched from the memory unit is placed in the instruction register (IR).
 The component of an instruction register includes; I bit, the operation code, and bits 0
through11.
 The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
 The outputs of the decoder are designated by the symbols D0 through D7.
 The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
 The operation codes from Bits 0 through 11 are applied to the control logic gates.
 The Sequence counter (SC) can count in binary from 0 through 15.
Draw and Explain The Timing Signal of Control
Unit
Generated by 4-bit sequence counter and 416 decoder
 The SC can be incremented or cleared.
 Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC 0

 The last three waveforms shows how SC is cleared when D3T4 = 1.

 Output D3 from the operation decoder becomes active at the end of timing
signal T2.
 When timing signal T4 becomes active, the output of the AND gate that
implements the control function D3T4 becomes active.
 This signal is applied to the CLR input of SC. On the next positive clock
transition the counter is cleared to 0. This causes the timing signal T0 to
become active instead of T5 that would have been active if SC were
incremented instead of cleared.
Write a Short Notes on Instruction Cycle
A program consisting of the memory unit of the computer includes a series of
instructions. The program is implemented on the computer by going through a cycle
for each instruction.
In the basic computer, each instruction cycle includes the following procedures −
 It can fetch instruction from memory.
 It is used to decode the instruction.
 It can read the effective address from memory if the instruction has an
indirect address.
 It can execute the instruction.
After the following four procedures are done, the control switches back to the first
step and repeats the similar process for the next instruction. Therefore, the cycle
continues until a Halt condition is met. The figure shows the phases contained in the
instruction cycle.

As display in the figure, the halt condition appears when the device receive turned off,
on the circumstance of unrecoverable errors, etc.
Fetch Cycle
The address instruction to be implemented is held at the program counter. The
processor fetches the instruction from the memory that is pointed by the PC.
Next, the PC is incremented to display the address of the next instruction. This
instruction is loaded onto the instruction register. The processor reads the instruction
and executes the important procedures.
Execute Cycle
The data transfer for implementation takes place in two methods are as follows −
 Processor-memory − The data sent from the processor to memory or
from memory to processor.
 Processor-Input/Output − The data can be transferred to or from a
peripheral device by the transfer between a processor and an I/O device.
In the execute cycle, the processor implements the important operations on the
information, and consistently the control calls for the modification in the sequence of
data implementation. These two methods associate and complete the execute cycle.
State Diagram for Instruction Cycle
The figure provides a large aspect of the instruction cycle of a basic computer, which
is in the design of a state diagram. For an instruction cycle, various states can be null,
while others can be visited more than once.

 Instruction Address Calculation − The address of the next instruction is

computed. A permanent number is inserted to the address of the earlier
instruction.
 Instruction Fetch − The instruction is read from its specific memory location
to the processor.
 Instruction Operation Decoding − The instruction is interpreted and the
type of operation to be implemented and the operand(s) to be used are decided.
 Operand Address Calculation − The address of the operand is evaluated if
it has a reference to an operand in memory or is applicable through the
Input/Output.
 Operand Fetch − The operand is read from the memory or the I/O.
 Data Operation − The actual operation that the instruction contains is
executed.
 Store Operands − It can store the result acquired in the memory or transfer
it to the I/O.
Draw and explain the flowchart for instruction
cycle.
In the basic computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.

Explain Different types of Addressing modes

Addressing modes are nothing but the different ways in which the location of an
operand can be specified in an instruction. The number of addressing modes that a
processor supports changes according to the instruction set it is based on, however
there are a few generic ones that are present in almost all processors and are thus of
utmost importance.
They are as follows:
i. Immediate mode
ii. Register mode
iii. Absolute mode
iv. Indirect mode
v. Index mode
 vi. Base with index
vii. Base with index and offset
viii. Relative
ix. Auto increment
x. Auto decrement

Immediate mode: In this mode, the operand is specified in the instruction itself.
E.g. Move #200,R0
The above instruction places the value 200 in the register R0.Clearly Immediate mode
can be used only to specify the source operand.
Figure 1 shows the above concept i.e. the operand is a part of the instruction

Register mode: The operand is the contents of a register. We specify the operand in
this case by specifying the name of the register in the instruction. Processor registers
are often used for intermediate storage during arithmetic operations. This addressing
mode is used at that time to access the registers.
E.g. Move R0, R1
Contents of the R0 register are moved to R1 register.
As shown in Figure 2, the instruction names the register that holds the operand.

Absolute mode: The operand is in a memory location; the address of the operand is
passed explicitly in the instruction. Global variables are represented using this
addressing mode.
E.g. Move LOC, R0

Here LOC corresponds to the address from where the contents will be accessed by the
processor and placed in R0.
Indirect mode: The effective address (E.A.) of the operands is the contents of a
register (see Figure 3(b)) or the memory location whose address appears in the
instruction (see Figure 3(a)). The name of the register or the memory address is placed
in parentheses to denote indirection or in other words that the contents are addresses
of the operands.
This instruction fetches the operand from the address, pointed by the contents of the
register R1 or of the memory location ‘B’ and adds them to R0.

Index mode: The effective address of the operand is calculated by adding a constant
value to the contents of a register, which is clearly shown in Figure 4. The address can
be in a register used specially for this purpose or any of the general purpose registers.
In either case it is called as an index register.
E.g. Move X (R0), R1
Here, Contents at address X+R0 are moved to R1 .X contains a constant value.

Base with index mode: The effective address is the sum of contents of two registers.
The first register as before is called the index and the second register is called the base
register. This mode provides more flexibility since both the components are registers
and can thus be changed.
E.g. Move (R0, R1), R2
Here, Contents at address R0+R1 are moved to R2.

Base with index and offset mode: The effective address is the sum of contents of
two registers and a constant. The constant value in this case is often called the offset
or the displacement.
 E.g. Move X (R0, R1), R2
Contents at address X+R0+R1 are moved to R2.
Relative mode: For relative addressing, also called PC-relative addressing, the
implicitly referenced register is the program counter (PC). That is, the next instruction
address is added to the address field to produce the EA. typically, the address field is
treated as a twos complement number for this operation. Thus, the effective address
is a displacement relative to the address of the instruction as shown in the example
below.
Relative addressing exploits the concept of locality.
E.g. Move X (PC), R1
Here, Contents at address X+PC are moved to R1 .X contains a constant value.

Auto increment mode: The effective address of the operand is the contents of a
register specified in the instruction. After accessing the operand, the contents of this
register are automatically incremented to the next value. This increment is 1 for byte
sized operands, 2 for 16 bit operands and so on.
E.g. Add (R2) +, R0
Here are the contents of R2 are first used as an E.A. then they are incremented.

Auto decrement mode: The effective address of the operand is the contents of a
register specified in the instruction. Before accessing the operand, the contents of this
register are automatically decremented and then the value is accessed.
E.g. Add - (R2), R0
Here are the contents of R2 are first decremented and then used as an E.A. for the
operand which is added to the contents of R0. The auto increment addressing mode
and the auto decrement addressing mode are widely used for the implementation of
data structures like Stack. There may be other addressing modes that are unique to
some processors.
Explain Direct Addressing mode
Direct Addressing Mode is also known as “Absolute Addressing Mode”.In this
mode the address of data(operand) is specified in the instruction itself.That
is, in this type of mode, the operand resides in memory and its address is given
directly by the address field of the instruction. Means, in other words, in this
mode, the address field contain the Effective Address of operand .

EA=A

As an example: Consider the instruction:

ADD A [Means add contents of cell A to accumulator] .

It Would look like as shown below:

Here, we see that in it Memory Address=Operand.

Explain Indirect Addressing Mode

In this mode, the address field of instruction gives the memory address where on,
the operand is stored in memory.That is, in this mode, the address field of the
instruction gives the address where the “Effective Address” is stored in memory
EA=(A)
Means, here, Control fetches the instruction from memory and then uses its address
part to access memory again to read Effective Address.
As an example: Consider the instruction:
 ADD (A) [Means adds the content of cell pointed to contents of A to
Accumulator.]

It look like as shown in figure below:

Thus in it, AC <-- M[M[A]] [M=Memory]

(A)=1350=EA

Difference between Direct and In-direct

Addressing Mode
S.
Direct Addressing Mode Indirect Addressing Mode
No.

In this mode, the address field contains the In this mode, the address field contains the
1.
effective address of the operand. effective address of the operand.

This addressing mode requires one memory It requires two memory references.
2.
reference only.

It is a quick addressing mode. It is slower in comparison to direct

3.
addressing mode

There is no further classification in this mode. It can be further classified into two
4.
categories.

There are no further calculations required to It requires further calculation to determine

5.
perform the operation in this addressing mode. the effective address of the operand.