PIR MEHR ALI SHAH ARID AGRICULTURE UNIVERSITY

University Institute of Information Technology

CS-430 Digital Logic Design

Credit Hours: 4(3 2) Prerequisites:

Course Contents:
Introduction to concept and definitions used in digital logic design. Difference between
analog and digital system along with TTL and CMOS logics. Number systems, Boolean
algebra and logic gates. Analysis of gate level minimization with 2-level networks and
Karnaugh maps. Combinational logic systems that includes encoders, decoders,
multiplexers, demultiplexers. Sequential logic systems are gated latch and flip-flop i.e.
SR, JK, D and T. Design of sequential modules consist of registers, shift registers and
universal registers along with counters i.e. synchronous and asynchronous counters.
Programmable devices: microcontroller, ROM and programmable aarays.
Course Objective:
The aim of this course is to introduce the students with the electronics components of
modern digital world that includes the combinational and sequential logic circuits
analysis and design. Digital circuits are merger of logic gates, encoder, decoder,
multiplexers, registers, counters and programmable logic arrays.
Teaching Methodology:
Lectures, Assignments, labs, Projects, Presentations, etc. Major component of the
course should be covered using conventional lectures. Practical contact hours are
compulsory.
Courses Assessment:
Exams, Assignments, Quizzes, Project, Presentations. Course will be assessed using a
combination of written examinations and project(s). Practical evaluation, using rubrics,
is encouraged and suggested to make up around 20% of the course.
Reference Materials:
 Digital Design by Morris Mano (Book).
 Digital Fundamentals by Thomas Floyd (Book).
 DLD Lab Manual
 Software tools: Logisim or Lattice diamond software.

Week/Lecture # Theory Practical

Lecture-I Introduction to analog and digital systems.
Week 1 Lecture-II Number system conversions.
Lecture-III Conversion and compliments.
Lecture-I Binary, octal & Hexa addition/subtraction.
Week 2 Lecture-II Logic level. BCD addition.
Lecture-III Even odd parity bits. ASCII codes.
Lecture-I Logic gates, types, symbol & truth table.
Lecture-II Introduction to Boolean algebra & analysis
Week 3
Identities of Boolean algebra &
Lecture-III
simplification.
Week 4 Lecture-I Standard forms min-terms, max-terms,
 sum of product (SOP) and product of sum
(POS).
Logic operations. Introduction to
Lecture-II
Karnaugh-map.
Two, three & four variable k-map
Lecture-III
simplifaction.
Two, three & four variable k-map
Lecture-I
manipulation.
Two level implementation and selection of
Week 5 Lecture-II
prime implicates and
Don’t care conditions (two, three & four
Lecture-III
variable k- map).
Lecture-I NAND & NOR as Universal gates.
AND, OR, NOT implementation using
Lecture-II
Week 6 NAND & NOR gates.
Combinational logic implementation using
Lecture-III
gates.
Introduction to DLD
Lecture-I
tools.
Verification of AND,
Lecture-II OR and NOT gate
Week 7
according to truth table.
Verification of NAND,
Lecture-III and NOR gate
according to truth table.
Verification of XOR
Lecture-I gate according to truth
table.
Week 8 Verification of universal
Lecture-II
gates.
Verification of universal
Lecture-III
gates.
Midterm Exam
Lecture-I Design procedure for multilevel circuits.
Week 9 Lecture-II Half, full and parallel adder.
Lecture-III Half and full subtractor.
Encoder, decoder and magnitude
Lecture-I
comparator.
Week 10
Lecture-II Multiplexer, demultiplexer and ROM.
Lecture-III Sequential logic circuits implementation.
Lecture-I Flip Flop and their types. Clock.
Week 11 Lecture-II Triggering of Flip Flops.
Lecture-III Conversion of Flip Flops.
Lecture-I Registers and their types.
Week 12 Lecture-II Serial addition and shift registers.
Lecture-III Uni and bi-directional registers.
Lecture-I Universal shift registers.
Week 13 Lecture-II Introduction to counters. Ripple counter.
Lecture-III Synchronous and asynchronous counters.
 Design half and full
Lecture-I
adder.
Design half and full
Week 14 Lecture-II
subtractor.
Design BCD seven-
Lecture-III
segment decoder.
To check operation of
Lecture-I
multiplexer.
Design basic RS flip
Week 15 Lecture-II
flop operations.
Design basic JK flip
Lecture-III
flop operations.
Lecture-I Registers.
Week 16 Lecture-II Counters.
Lecture-III Project demo.
Final term Exam

Course Learning Outcomes (CLOs)

At the end of course the students will be able to:
1. Deal with the tools and techniques for the design of digital electronic circuits.
2. Understand and analyze both combinational and sequential logic circuits.
3. Design small scale digital circuits through logical reasoning.