INTERNSHIP| NOV 2021- PRESENT

Verification Intern
Maven Silicon Softech Private Limited, Bangalore

PROFESSIONAL TRAINNING| APR 2021-NOV 2021

Trainee (Advanced Design and Verification Course)

Maven Silicon Softech Private Limited, Bangalore

SANJAY SINGH
PROFESSIONAL SUMMARY
I am Pursuing M. Tech from Greater Noida Institute of
Engineering and Technology. Currently working as
Verification Intern at Maven Silicon Softech Pvt Ltd,
Bangalore. I have been trained in domains like Digital
Design, Verilog, System Verilog, and UVM with hands-on
experience of projects based on Industry-standard
protocols (AHB to APB Bridge).
ACADEMIC BACKGROUND
• M . Te ch .
V L S I D e s i g n | Gr e a t e r N o i d a I n s t i t u t e o f T e c h n o l o g y
2 0 2 0 - 2 0 2 2 | C u r r e n t Pe r c e n t a g e : 8 0 . 7 7 %
• B. T e ch .
Electronics & Comm.|Galgotia College of Engg. & Tech.
2 0 1 5 - 2 0 1 9 | Pe r c e n t a g e : 7 0 . 3 8 %
• Int er me dia te Sc ho ol
Bal Vikas Sansthan Inter College
2 0 1 3 - 2 0 1 4 | Pe r c e n t a g e : 8 7 . 6 6 %
• Se c ond ar y Sc ho ol
Bal Vikas Sansthan H igher Secondary School
2 0 1 0 - 2 0 1 1 | Pe r c e n t a g e : 7 2 . 5 %

Looking for an entry-level position in the Core Front-end

domain (RTL / ASIC Design, Design and Verification) CORE SKILLS
where I can utilize my knowledge about the subjects,
gained during my Training and Professional Courses.
• DESIGN DOMAIN:
✓ Dig ita l El e ctr oni cs :
C om bina ti onal & S e qu enti al ci rc ui ts , F S M ,
CONTACT ME AT Me m ori es .
✓ Ver il og P r o gr a mm ing :
Data ty pe s, O per at o rs, Pr oc es se s , B A & N BA ,
• Email: sanjaysingh1207@gmail.com
Delay s in Ve ril og, be gin - end & f o rk j oin bloc ks ,
• LinkedIn: www.linkedin.com/in/sanjaysingh8
lo opin g & br anchin g con s tr uc t, Sy s te m ta s ks &
• Mobile: 8742878516
F unc ti ons , co mpil er dire cti ve s, F S M c odin g,
Sy n the si s i ss u e s, R ac es in sim ul ati on , pi pe lining
R T L & TB C o ding , St ra tifi ed E ve nt Q ue u e.
VLSI DOMAIN SKILLS
✓ Cod e C ov er ag e: Sta t eme nt and br anch
co ve rag e, C ondi ti on & E xpr es si on C ov era ge,
HDL: Verilog T og gle & F S M C o ve r age
HVL: System Verilog
• VERIFICATIO N DOMAIN:
TB Methodology: UVM ✓ Sys te m V er i lo g H D VL (Dat a ty pe s / Int er fa ces &
C locki ng bl ock s / O OP C onc ept s / Inh eri tanc e /
Protocols: AHB, APB
P oly m or phis m / R and omi za ti on / T hr ead s)
EDA Tool: Mentor Graphics- Questasim ✓ Sys te m V er i lo g Fun ct ion al C ov er ag e ( R e u sabl e
Modelsim, Intel-Quartusprime C o ver g r o up / C r os s C o ver ag e / Tr ansi ti o n Bin s)
✓ Sys te m V er i lo g As s er tio ns ( S V A B uildin g Bl ock s,
Operating Systems: Linux, Windows Sy st em F un cti on s / W ritin g Se q uenc e s, an d
Implica ti on Op er at or s / R epe ti tio n Ope ra t or s and
Verification
Se q uenc e C o mp o siti on)
Methodologies: Constraint Random
Coverage Driven-Verification ✓ UV M ( U V M Ob jec t s & C o mp on ent s / UV M Fac t ory
Assertion Based Verification – & ov er ridin g m e th od s / S tim ul u s M o dellin g / U V M
(SVA) Pha se s / U V M C onfi g ur ati on / T LM / U V M
Se q uenc e, vi rt u al se qu enc e & s eq u enc er )
SUBJECT EXPERTISE PROJECTS (4)

• Digital Electronics Maven Silicon Projects:

PERSONALITY TRAITS ROUTER1X3 –RTL DESIGN AND VERIFICATION

HDL: Verilog
• Decision Making HVL: System Verilog
• Leadership TB Methodology: UVM
• Adaptability EDA Tools: Questasim
• Positive Approach
• Team Player Description:
The router accepts data packets on a single 8-bit port and
routes them to one of the three output channels,
ACHIEVEMENTS channel_0, channel_1 and channel_2.

Responsibilities:
• Qualified GATE(EC) | 2019 with Score 426 & • Implemented RTL using Verilog HDL.
All India Rank 8676
• Verified the RTL model using System Verilog.
• First Division Academic Record in both UG &
PG • Generated functional and code coverage for the RTL
verification sign-off
• Synthesized the design.
COLLEGE SKILLS
AHB2APB BRIDGE IP CORE VERIFICATION
• Synopsys- HSPICE Tool
• Microsoft Office Suite HVL: System Verilog
• CST Microwave Studio TB Methodology: UVM
EDA Tools: Questasim

CERTIFICATES
• Advanced VLSI Design and Verification
Maven Silicon Softech Private Limited,
Bangalore
• Course on Computer Concept
National Institute of Electronics &
Information Technology
Description:
The AHB to APB bridge is an AHB slave which works as an interface
between the high speed AHB and the low APB buses.
Responsibilities:
• Verified the RTL module with UVM Test Bench with different
test scenarios like single READ, WRITE & Burst READ, WRITE with
different burst length.
• Generated functional and code coverage for the RTL
verification sign-off.

• Industrial Project Training in Telecom M.Tech. Project:

Technology
Advanced Level Telecom Training Centre,
Low Power Energy Efficient Full Adder using GNRFET
BSNL (Ghaziabad)
Tool Used: Synopsys HSPICE
PUBLICATION
Description:
• In this work graphene nano-ribbon FET is used at 32 nm
• Singh, S., Kumar, A., Ojha, M.K. and technology node to reduce the power consumption
Gupta, D., 2022, April. Low Power Energy moreover the reduce size and better device parameters
Efficient Full Adder using GNRFET. In 2022 help GNRFET to provide excellent device performance.
6th International Conference on Devices, • The result of the proposed full adder validated and
Circuits and Systems (ICDCS) (pp. 413- compared with the already existing full adder design.
417). IEEE. • The proposed full adder circuit shows 99.92%, 85.46%,
97.28%, 87.14% reduction in power consumption, delay,
power delay product and leakage power respectively.
PROJECT

B.Tech. Project:

CIRCULAR SHAPED DUAL POLARIZED MICROSTRIP PATCH

ANTENNA WITH H SHAPED SLOT

Tool Used: CST Microwave Studio

Description:
• Microstrip antenna consists of a metallic patch on a
grounded substrate-shaped slot consisting of a wide main
slot with a coplanar waveguide (CPW) feedline.
• This antenna operates at 2.16 GHz to 2.64GHz with
resonating frequencies2.44 GHz and 2.46 GHz.

Responsibilities:
• Mathematical analysis of Antenna Geometry.
• Designing and Simulation of Antenna Prototype.

DECLARATION

I hereby declare above information is correct to the best of my

knowledge and belief.

Date: 18/06/2022
Place: Bangalore (SANJAY SINGH)