INTERNSHIP| NOV 2021- PRESENT

SANJAY SINGH Verification Intern

Maven Silicon Softech Private Limited, Bangalore

PROFESSIONAL TRAINNING| APR 2021-NOV 2021

Trainee (Advanced Design and Verification Course)

Maven Silicon Softech Private Limited, Bangalore

ACADEMIC BACKGROUND

 M. Tech.
V L SI D e si g n | Gr e a t e r N o i d a I n st i t u t e o f T e c h n o l o g y
PROFESSIONAL SUMMARY 2 0 2 0 - 2 0 2 2 | C u r r e n t Pe r c e n t a g e : 8 0 . 7 7 %
 B. Tech.
E l e c t r o n i c s & C o m m. | G a l g o t i a C o l l e g e o f E n g g . & T e c h .
I am Pursuing M. Tech from Greater Noida Institute of Engineering
2 0 1 5 - and
2 0 1 9Technology. Currently
| Pe r c e n t a g e : 7 0 . working
38 % as Verification Intern at Mav
Looking for an entry-level position in the Core Front-end domain (RTL / ASICSchool
 Intermediate Design, Design and Verification) where I can utilize m
Bal Vikas Sansthan I nter College
2013 - 2014 | Percent age: 87 . 66 %
 Secondary School
Bal Vikas Sansthan H igher Secondary School
2 0 1 0 - 2 0 1 1 | Pe r c e n t a g e : 7 2 . 5 %

CORE SKILLS

 DESIGN DOMAIN:
 Digital Electronics:
Combinational & Sequential circuits, FSM,
CONTACT ME AT Memories.
 Verilog Programming:
Data types, Operators, Processes, BA & NBA,
Email:
LinkedIn: Delays in Verilog, begin - end & fork join blocks,
Mobile: 8742878516 looping & branching construct, System tasks &
Functions, compiler directives, FSM coding,
Synthesis i ssues, Races in s imulation, pipelining
RTL & TB Coding, Stratified Event Queue.
VLSI DOMAIN SKILLS
 Code Coverage: Statement and branch
coverage, Condition & Expression Coverage,
HDL: HVL: Verilog Toggle & FSM Coverage
System Verilog
 VERIFICATION DOMAIN:
TB Methodology:UVM Sys te m V eri lo g H D VL ( Dat a ty pe s / Int er fa ces &

C locki ng bl ock s / O OP C onc ept s / Inh eri tanc e /
Protocols: AHB, APB
Polymorphism / Randomization / Threads)
EDA Tool:  System
Mentor Graphics- Questasim Modelsim, Verilog Functional Coverage ( Reusable
Intel-Quartusprime
Cover group / Cross Coverage / Transition Bins)
 System Verilog Assertions ( SVA Building Blocks,
Operating Systems: Linux, Windows System Functions / Writing Sequences, and
Implica ti on Op er at or s / R epe ti tio n Ope ra t or s and
Verification Methodologies: Sequence Composition)
Constraint Random Coverage Driven-Verification Assertion Based Verification – (SVA)
 UV M ( UV M Ob jec t s & C o mp on ent s / UV M
Fac t ory & overriding methods / Stimulus
Modelling / UVM Phases / UVM Configuration /
TLM / UVM
Sequence,
virtual
sequence &
sequencer )
 SUBJECT EXPERTISE PROJECTS (4)

Digital Electronics Maven Silicon Projects:

PERSONALITY TRAITS ROUTER1X3 –RTL DESIGN AND VERIFICATION

HDL: Verilog
Decision Making HVL: System Verilog
Leadership TB Methodology: UVM
Adaptability EDA Tools: Questasim
Positive Approach
Team Player Description:
The router accepts data packets on a single 8-bit port and
routes them to one of the three output channels,
ACHIEVEMENTS channel_0, channel_1 and channel_2.

Responsibilities:
Qualified GATE(EC) | 2019 with Score 426 & All India Rank 8676
First Division Academic Record in both UG & PG  Implemented RTL using Verilog HDL.
 Verified the RTL model using System Verilog.
 Generated functional and code coverage for the
RTL verification sign-off
 Synthesized the design.
COLLEGE SKILLS
AHB2APB BRIDGE IP CORE VERIFICATION
Synopsys- HSPICE Tool
Microsoft Office Suite HVL: System Verilog
CST Microwave Studio TB Methodology: UVM
EDA Tools: Questasim

CERTIFICATES Description:
The AHB to APB bridge is an AHB slave which works as an interface
between the high speed AHB and the low APB buses.
Advanced VLSI Design and Verification Maven Silicon Softech Private Limited, Bangalore
Responsibilities:
Course on Computer Concept National Institute of Electronics & Information
 Verified the RTL moduleTechnology
with UVM Test Bench with different
test scenarios like single READ, WRITE & Burst READ, WRITE with
Industrial Project Training in Telecom Technology different burst length.
Advanced Level Telecom Training Centre, BSNL (Ghaziabad)
 Generated functional and code coverage for the
RTL verification sign-off.

M.Tech. Project:

Low Power Energy Efficient Full Adder using GNRFET

Tool Used: Synopsys HSPICE

PUBLICATION
Description:
 In this work graphene nano-ribbon FET is used at 32 nm
Singh, S., Kumar, A., Ojha, M.K. and Gupta, D., 2022, April. Low Power
technology Energy
node Efficient
to reduce the Full
powerAdder using GNRFET. In
consumption
moreover the reduce size and better device parameters
help GNRFET to provide excellent device performance.
 The result of the proposed full adder validated and
compared with the already existing full adder design.
 The proposed full adder circuit shows 99.92%, 85.46%,
97.28%, 87.14% reduction in power consumption, delay,
power delay product and leakage power
respectively.
PROJECT

B.Tech. Project:

CIRCULAR SHAPED DUAL POLARIZED MICROSTRIP

PATCH ANTENNA WITH H SHAPED SLOT

Tool Used: CST Microwave Studio

Description:
 Microstrip antenna consists of a metallic patch on a
grounded substrate-shaped slot consisting of a wide main
slot with a coplanar waveguide (CPW) feedline.
 This antenna operates at 2.16 GHz to 2.64GHz with
resonating frequencies2.44 GHz and 2.46 GHz.

Responsibilities:
 Mathematical analysis of Antenna Geometry.
 Designing and Simulation of Antenna Prototype.

DECLARATION

I hereby declare above information is correct to the best of my

knowledge and belief.

Date: 18/06/2022
Place: Bangalore (SANJAY SINGH)