Yangyuan Wang

Min-Hwa Chi
Jesse Jen-Chung Lou
Chun-Zhang Chen
Editors

Handbook of
Integrated
Circuit
Industry
Handbook of Integrated Circuit Industry
Yangyuan Wang • Min-Hwa Chi •
Jesse Jen-Chung Lou • Chun-Zhang Chen
Editors

Handbook of Integrated
Circuit Industry

With 1014 Figures and 203 Tables

Editors
Yangyuan Wang Min-Hwa Chi
Institute of Microelectronics GTA Semiconductor Co., Ltd.
Peking University Shanghai, China
Beijing, China

Jesse Jen-Chung Lou Chun-Zhang Chen

School of Software and Microelectronics Peng Cheng Laboratory
Peking University Shenzhen, Guangdong, China
Beijing, China

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Preface

(The preface of “The Handbook of Integrated Circuit Industry” used here, is a translation of
that from its 2018 sisterbook in Chinese.)

Penning Past and Present: A History of The Handbook of Integrated Circuit Industry
Yangyuan Wang

Writing and compiling The Handbook of Integrated Circuit Industry has been of
special significance for me and my colleagues. After graduating from universities,
we have all been engaged in the field of integrated circuit and have established a
lifelong bond with it. Like members of one big family, we share the same aspiration,
which is to work innovatively and use the newest technologies in the integrated circuit
as a cornerstone to pave the way for the great rejuvenation of the Chinese nation.

“He who pursues truth today gains most from classical wisdom.”

“He who pursues truth today gains most from classical wisdom,” thus pronounced
Wang Fu, a thinker of the Eastern Han Dynasty (AD 25–220), in an essay called “In
Praise of Learning” in his work Thus Speaks a Hermit. This reveals how important
the role of classics is in learning, inheriting, and innovating in education and career
development. The purpose of compiling The Handbook of Integrated Circuit Indus-
try (or The Handbook) is thus to make it a “classic” that not only meets the demand
but also promotes the innovation in the field of integrated circuit.
It all started from the beginning of 1992, when a group of young people, all from
the Division of Basic Products, Ministry of Mechanical and Electronic Industry,
proposed to compile a book of this kind. Among them were Minzheng Zheng,
Xiaotian Xu, Xian Chen, and Yongwen Wang from the Departments of Integrated
Circuit and of Science and Technology. Driven by the needs of the IC industry and
the implementation of its major projects at that time, their initiative won the
immediate and enthusiastic support of the Division and the Ministry. A panel of
more than 100 young and middle-aged scientists, technicians, engineers, and project
managers were accordingly organized top-down, and I was made Editor-in-Chief. A
year’s collaboration eventually led to the publication of the Handbook in April 1993
by the Electronic Industry Publishing House. Qili Hu, then Minister of Mechanical

v
vi Preface

and Electronic Industry, calligraphed the title of the Handbook, and Peiyan Zeng,
then Vice-Director of the National Planning Commission, prefaced it. It was favor-
ably received by the profession, in the field of science and technology, and among
the educational circles. More than 20 years had passed, and it was still in demand
though it had long been out of print.
As is stated in the “Editor’s Note” in the Handbook, “This book serves as an
handbook of integrated circuits, covering not only the technologies and economy
related to these technologies, but also the management and construction of the
industry. It can be used as a handbook by administrators at various levels of the
industry as well as by front-line corporate executives, engineers and technicians for
their regular reference, with an aim to facilitate their decision-making in line with
professional rationale. It can also be used as a teaching guide for educators so that
students they cultivate can fully grasp the traits and rules of the industry besides
learning knowledge of the field. In the mean time, the Handbook also serves as a
convenient reference for scientists and technicians exploring information while
engaging themselves in research.” This was our original aspiration.
Time goes on and 25 years have passed. The form, size, and level of science and
technology and of the IC industry have undergone constant change and have made
tremendous progress. For example, the 1993 edition was able to project the scale of
the industry only as far as the year 2000, envisioning a level of technology reaching
0.12 μm/300 mm silicon integrated circuits, but this was surpassed as early as the
beginning of 2000. Some projections of device development have become true,
while others have not, as certain new configurations of the IC devices, especially
multi-gate and all-around gate, failed to be recognized back then. Nowadays, these
new devices with high performance and low power consumption have been indus-
trialized and become a core competitive force in large-scale production. This makes
it urgent to compile a new edition of the Handbook to meet the needs of the
development of the modern IC industry. The initial aspiration has remained
unchanged, but we must continue to move on.
How time flies! The young talents of the team who nurtured the birth of the 1993
edition have reached their 70s. Yet, despite their age, they are still staunch pro-
ponents of the new edition and they played a central role in its remaking. And I, an
octogenarian, inspired by these old colleagues, also joined in.
However, with the deepening of reform and the transformation of government
functions, it is all but impossible to accomplish this new edition in the same
top-down manner as it was with the 1993 edition.
Therefore I proposed to the National Advisory Committee on the Development of
the Integrated Circuit Industry (or National Advisory Committee) and the Ministry
of Industry and Information Technology (or MIIT) on August 31, 2015, to compile
A Series of Books on the Integrated Circuit (or The Series). An upgraded version of
The Handbook of Integrated Circuit Industry would be the first volume of the Series.
The proposal found favor with both the Committee and the Ministry.
With the needs of industrial development, the active participation of the col-
leagues, and the enthusiastic support of the leadership, it was time for us to “set sail
for the high seas.” On February 26, 2016, I chaired a meeting in preparation for the
Editorial Committee of the Series and the Handbook in Southern University of
Preface vii

Science and Technology in the city of Shenzhen. We brought forth an overall plan
for the compilation of the Series and the Handbook and proposed a list of nearly
100 scientists as the first panel members, on the basis of the group members who had
participated in the discussion on the strategic planning of the academic and industrial
development of microelectronics.
This new Handbook was to be divided into 10 chapters. Experts and authorities in
the related fields were invited to act as chief and deputy chief editors for each
chapter. Recommendation was made that an executive editor be further appointed
for each chapter to assist the chief and deputy chief editors. The whole Handbook
was designed to cover about 1000 entries, with an average length of about 1000
words for each entry. Together with all the graphs and tables, the Handbook would
be a tome of 1.2 million to 1.5 million words.
We also laid down that the headword of each entry was to be provided in
simplified and traditional Chinese as well as in English. Though the body of the
entry was to be in simplified Chinese only, this did not mean that there would be no
room for future expansion. The idea was to provide standard and uniform terminol-
ogy for the various realms of the IC industry so as to facilitate future academic
exchange both home and abroad.
On April 6, 2016, the Preparatory Committee of the Series and the Handbook
issued a “Letter of Inquiry” to more than 100 experts in the IC field in China. Most
experts responded with enthusiasm and showed support for the work. They agreed to
serve on the Editorial Committee and recommended more experts to join in.
Consequently, on April 26, 2016, MIIT’s Division of Electronic Information
announced, on behalf of the Secretariat of the National Advisory Committee, a
call for conference to members of the Editorial Committee. The conference took
place on May 7 in Beijing, chaired by Deputy Director Hongbing Peng and others of
the Division of Electronic Information. They announced the official establishment of
the Editorial Committee, and I was to serve as Editor-in-Chief. On behalf of the
Secretariat of the National Advisory Committee, letters of appointment to members
of the Editorial Committee attending the meeting were presented.
After offering an overall appraisal of China’s IC industry, attention was called to
the country’s “pressing need for talent cultivation, which made it an opportune
moment to initiate the compiling of the Series and the Handbook.” Also called for
was a strong sense of honor and responsibility among all the editorial members for
the compilation, urging them “to keep pace with the time and stay in close touch with
the industry” and to bring forth an Handbook “with full coverage and scientific
accuracy.”
At the inaugural assembly of the Editorial Committee, I quoted Gorky to illustrate
the importance of our compilation: “Books are the ladder of human progress.” I also
believe books are, as that well-known ancient Chinese poem says, “just rain that
knows the season and comes with the spring. It steals on the breeze into the night,
and moistens all things softly without sound.” Books are the potential and powerful
drive behind industrial development, talent growth, and cultivation of personal
integrity. They are also an essential part of the cultural construction of the IC
industry. Regarding some of the important questions in the compilation, I made
the following points:
viii Preface

1. Writing is serious work. Knowledge must be created on the basis of learning and
inheritance, so as to promote the progress of humanity and the development of
science, technology, and the IC industry. Learning, inheritance, and innovation
entail an arduous course of hard work in their own right, allowing no expediency
or opportunism. “Topless is the mount of learning, but we scale it by the path of
diligence; boundless is the sea of knowledge, but we sail it by the boat of
assiduity.”
2. Respect others’ intellectual property as we respect our own. No plagiarism or
“suspected plagiarism” is allowed anywhere in our work. We must be aware that
the slightest academic misconduct at a single point or in a single entry will ruin
the whole book and the whole Series, as well as spoil the achievements and
reputations of all those who contribute to the compilation. This therefore will be a
most important focus in our future review of the drafts. Any quote must be
specified of its source, and we will later seek permission collectively from the
proprietors of the copyrights concerned. Indication of the sources is required even
in the case of snippets of remarks from the Internet, which should be documented
in the reference section after the entry.
3. Humans are the messenger of knowledge, but human life is too short and limited
to be able to make more than a splash in the long river of history. Even though
colleagues here today can at best lead the research on integrated circuits for a
couple of decades, our words, the works we produce, will last longer. They will
have a much longer life and will exert more enduring influence than we do. No
matter how fast science and technology develops and how rapidly the industry
upgrades its various aspects, the philosophical inquiry and exploratory spirit
embodied in our scientific writing will have a far more lasting impact on future
generations to come than knowledge itself. “Much of what happened in the past
and present is to be found in writings.” All our contributors will find themselves
holding a heavy pen and bearing a historical responsibility.

After the establishment of the Editorial Committee, the writing of all the chapters
of the Handbook began. Plans for individual publication of the Series as monographs
were also under way. Up to December 31, 2016, the preliminary drafts of all the
chapters had been completed, with the number of entries reaching 1126, totaling
about 1.8 million words by 276 contributors. In order to ensure the quality of the
writing, we finalized a list of chief, deputy chief, and executive editors for all the
chapters and supplemented new editors in answer to the actual progress of the
project. After a self-review by the editors of each chapter, we organized the first
draft review meeting in Shenzhen from February 19 to 24, 2017, with the support of
the Shenzhen Industrial Base for Integrated Circuit Design and Shenzhen Guowei
Electronics Co., Ltd. Prof. Yongwen Wang, Deputy Chief Editor and Secretary-
General of the Editorial Committee, addressed the meeting on behalf of the Editorial
Committee on the progress of and problems existing in the writing.
The results of the first review sounded an alarm to us, with duplicate checking
greatly exceeding the standard, aberrations in the writing widely evident, and
plagiarisms or “suspected plagiarisms” spotted in many places. Some contributors
Preface ix

even copied and pasted materials directly from the Internet bearing the original logos
into the entry they wrote. This is an act we firmly oppose and strictly prohibit! This is
absolutely intolerable!
In view of this, I demanded with gravity that the attendees of the meeting ask
themselves the following questions: In writing the entries, did we work innovatively
on the basis of our own learning and inheritance? Do the entries have independent
intellectual property rights? Have we offered new knowledge to the reading public?
Have we honestly documented and cited the research work of others and included
them in the reference?
I reiterated at this meeting that we should always keep the bottom line of
academic integrity. Writing is the same as living our life and building our career;
absence of integrity will get us nowhere.
For this reason, in the minutes of the meeting, we demanded that every editor,
contributor, and reviewer abide by honesty as the fundamental principle. At the same
time, we offered counsels to inexperienced young scholars on the proper way to
write entries, i.e., how to write independently and innovatively through learning,
digestion, and absorption and how to quote others’ work and expositions from the
Internet correctly. This they could do by properly noting the quoted words, phrases,
sentences, and paragraphs and listing the sources in the reference. This process, in
essence, is a process of educating and training young scholars in the discipline of
writing. For drafts which failed the duplicate checking, the Committee requested that
they be re-examined by their respective chapter editors. Stimulated by this, the
Committee also decided to examine the Handbook entry by entry and chapter by
chapter for the second review.
The 3 months between the first and second reviews was the first critical stage for
the writing and improvement of the Handbook, in which all the contributors and
organizers reprocessed the preliminary draft in the spirit of “originality first, quality
first.” When the second review came, the total number of contributors and reviewers
involved surpassed 500. It was simply hard work to unify the ideas and standards of
them all. Nevertheless, we repeatedly stressed that this Handbook was to be a
stupendous undertaking by more than 500 experts who, through their collaboration,
aimed to yield a serious academic product that should be able to stand the test of time
and professional challenges from all over the world. It would not allow any relax-
ation or academic irregularity. Each contributor and reviewer should be responsible
for themselves, for all the other contributors, reviewers and editors, as well as for the
future of the IC industry. We must adhere to the bottom line of honesty and
reliability.
From May 7 to 31, 2017, with the support of Semiconductor Manufacturing
International Corporation (SMIC) and Huada Semiconductor Co., Ltd., the second
review and duplicate checking of the Handbook were successively carried out in
SMIC, Shanghai, and Wanshou Hotel, Beijing. It was a painstaking yet touching
enterprise which manifested the strength of China’s scientific core force. Loyal and
dedicated to the country’s IC industry, they were the hope for the thriving of our
cause.
x Preface

On these two meetings, editors, contributors, and reviewers worked with consci-
entiousness and responsibility. Obvious inaccuracies and discrepancies in the first
draft were corrected, and the quality of the second draft was greatly improved.
The second review turned out to be a process of entry-by-entry duplicate
checking and examination of more than 1000 items. It was like gold panning in
which one “sweeps and sifts the sand until gold peeps through the blown dust.”
Entries like “mixed mud and sand” had to be sifted and filtered repeatedly until the
good “gold extracts” appeared. It was worth it though, because that was why we
launched the enterprise in the first place.
A lot of touching things happened during the second review. First of all was that
the chief and deputy chief editors of each chapter took serious note of the revision.
They attended the two-day review meeting in person and listened to various opin-
ions. After returning from the meeting, they organized their editors, writers, and
reviewers to make improvements and give timely feedbacks. Yuan Pu, Executive
Editor of Chap. 8, came all the way from the United States to Shanghai to participate
in the review and did not return to the Silicon Valley until after the review was over.
Weiping Liu, editor and reviewer of Chap. 5, came to the review in no time upon
notification of revising the entries he was in charge of. He took the drafts back and
worked on them overnight until two o’clock in the morning. They passed the next
day’s review smoothly.
Here I would also like to express my special thanks to the four Deputy Chief
Editors of the Handbook, Yongwen Wang, Xian Chen, Min-Hua Chi, and Jesse
Jen-Chung Lou, for their full participation in the second and final reviews, and to
Chun-Zhang Chen, the Under-Secretary-General and Dr. Jian Cao from the Secre-
tariat, as well as the two editors from the Electronic Industry Publishing House, who
worked 8–11 h a day for more than 20 days with high intensity. The review not only
displayed the devotion of the participants to their work and their rigor, but also built a
wonderful atmosphere of academic solidarity, mutual respect, and tolerance of
different opinions. During the last 2 days of the review, Prof. Yongwen Wang was
unable to eat because of gastrointestinal discomfort. Though he could only drink
water, he persevered until the review was over. The spirit of science, democracy,
solidarity, patriotism, professionalism, and integrity that all our colleagues exhibited
during the review process was a valuable spiritual legacy for the furthering of
China’s IC industry. I was deeply convinced that through the writing and compiling
of the Handbook, we have come together as a team and that we are the backbone of
China’s IC industry.
During the two reviews, we had summed up the following tenets:

Observe one bottom line of honesty and independent originality and give credit
where it is due when quoting others’ work.
Observe the two principles of firstly making innovations on the basis of learning and
inheritance so as to offer new and updated knowledge to readers, and secondly
separating the wheat from the chaff and extracting gold from sand.
Preface xi

Observe the three directives of paying tribute to the old generations of predecessors,
displaying worthiness to the current generation, and inspiring future generations
by showcasing our philosophy and rationality in scientific development.
Observe the four equal emphases on text and graphics, vertical (historical lineage)
and horizontal (international breadth), market and technology, and on academic
worth and popular utility.
Observe the five-word precept: namely, trustworthiness, expressiveness, elegance,
precision, and accuracy. Trustworthiness is about the norms of writing; expres-
siveness is about the ability to articulate; elegance means to show certain literary
grace; precision means to be exact; and accuracy means to be correct.

From July 14 to 27, 2017, with the support of the National Integrated Circuit
Industry Investment Fund Co., Ltd., the final review of the chapters, appendices,
keyword index, English-Chinese index, and the binding design of the Handbook was
conducted. This was the third stage of the compilation.
At this final review meeting, the Editorial Committee reported the results of
duplicate checking. Through the collective efforts of the authors and reviewers of
each chapter, based on a manual white-listing of the definitions, theorems, laws,
special terms, policy/statutory documents that are declared immune from duplicate
checking, and a sorting out the references cited, our duplicate checking was executed
by PaperPass, currently the most astringent contrast system on Chinese document
similarity. The result revealed that the repetition rate was zero in four chapters, less
than 1% in another four chapters, and less than 1.5% in two other chapters. A
consequent manual analysis found that duplicates were mainly due to the greater
probability of the concurrence of some text descriptions, but these did not involve
intellectual property rights.
As we laid particular emphasis at this final review on fully respecting others’
intellectual property rights while protecting our own, we demanded that all refer-
ences, charts, and data used in the Handbook should be authorized. To ensure the
purity and authority of the Handbook, Jian Cao, Lele Jiang, and Xiaohai Xu were
invited to take charge of the authorization. The Editorial Committee also decided to
hire Xiaoqing Tian, full-time legal officer of the Electronic Industry Publishing
House, as legal adviser of the Handbook.
It was on the hottest summer days after 2.5 years of hard work that we finally
brought the compilation of the Handbook to a close. It was like a toiling farmer
tilling the land at high noon as one ancient poem famously describes: “With sweat
dropping into the soil, he is hoeing away the weed at noon.” Indeed, for our
Handbook, “Who knows but that every single [word] in it is the fruit of hard labor?”
Every sowing has its harvest, and every harvest has to be won by hard work.
When we got together again for the appraisal of the Handbook, we shared our serious
discussions at the Preparatory Meeting, the deliberation of words while writing the
entries, the joyful and bitter arguments during the review, and the sweet aftertaste
when the compilation was over.
xii Preface

Ours is a flourishing age. Our writing and compiling project is blessed with the
privileges of the right time, the right place, and the right people. They are the proper
conditions for making a canon.
The right time means a prime opportunity. Technologies of integrated circuit have
ushered mankind into the information era. And information revolution has created
countless platforms for innovation in government administration, economic pros-
perity, national security and talent cultivation. The level of development of the IC
industry has become an important index of the comprehensive strength of a nation’s
power. The successive promulgation of the State Council Documents No. 18 [2000]
and No. 4 [2011], the release of the National Integrated Circuit Industry Develop-
ment Promotion Program, and the establishment of the National Integrated Circuit
Industry Investment Fund have provided important opportunities for the country to
develop its IC industry. As a result, China’s IC industry has taken off rapidly since
the turn of the twenty-first century. In terms of technological development, the IC
industry has entered a post-Moore era. New device models, design methods, pro-
cesses, and packages are emerging, providing us with a wonderful opportunity for
“innovative development.” Our role may be able to change from a “follower” to a
“leader” in some areas. On May 28, 2018, General Secretary Jinping Xi said at the
Academicians’ Congress of the Two Academies: “We must clearly realize that our
intersection with history may sometimes produce historic resonance, while at other
times we may simply pass it up.” He also stressed that “practice has repeatedly told
us that the critical core technologies cannot be obtained by request, purchase, or
entreaty.” We therefore should not pass up our historic encounter with the post-
Moore era and must keep in our grip the critical core technologies of the integrated
circuit and push China’s IC industry to the middle-to-high-end level on the global
value chain.
Good place means that the environment is optimal. As China is the originator of
the Belt and Road Initiative, many of our products are being launched in the world
market. Ranging from high-speed rail, to smart phones, and regular products such as
televisions and computers, the label of “Made in China” is shining brightly in the
international market. China is also the largest consumer market of integrated circuits,
providing enormous space for all kinds of IC products, no matter whether it is the
high-end Beidou Navigation System or the more common consumer products. Being
the second largest economy in the world, China has the ability not only to support the
development of its own IC industry but also to digest all kinds of IC products from
abroad. Whatever new forms of information science and technology and economy
may take, such as AI systems, big data, Internet, Internet of Things, and cloud
computing, they are still based on integrated circuits and systems and software. With
the development of its information technology and economy, China is sure to
become a powerful player in the IC industry.
The right people are the key. General Secretary Jinping Xi stressed at the above-
mentioned Academicians’ Congress that “both hard power and soft power depend
ultimately on people.” All rivalries in the world boil down to rivalry for talent. It was
exactly with such talents as Xuesen Qian, Ganchang Wang, and Jiaxian Deng who
developed the country’s first atomic and hydrogen bombs and man-made satellite
Preface xiii

that China won the right to speak in the international arena. It was with Kun Huang,
Xide Xie, Shouwu Wang, and other pioneers that China began to delve into the field
of semiconductor research. It was with the large number of home-trained scientists as
well as scientists, educators, and entrepreneurs who returned from abroad that China
created its own discipline of microelectronics, its first IC design system, its first
300 mm OEM production line, its special IC equipment for export, as well as this
Handbook written by 468 people. As a crystallization of the energies of all the
contributors, reviewers, and editors, the Handbook is a manifestation of the harmony
among the right people.
After the above three reviews, the plenary meeting of the Editorial Committee
was held on July 27, 2017, and reached the following points of agreement:

1. The formal lists of the chief, deputy chief, executive editors and other editors of
the adjusted chapters were adopted.
2. The drafts of all the chapters were approved after the final review. The chief,
deputy chief, and executive editors signed their respective chapters in confirma-
tion and formally submitted them to the Electronic Industry Publishing House.
3. In order to guarantee the authority of the Handbook, I proposed a two-month
Objection Period after the final review. The chief, deputy chief, and executive
editors of each chapter should send their chapters by e-mail to all the members of
the Editorial Committee and other relevant professional authorities for comments.
4. The design scheme of the Handbook by the Electronic Industry Publishing House
was adopted.

Based on the opinions we had gathered by September, the Handbook was

finalized and jointly signed in confirmation by the five Chief and Deputy Chief
Editors of the Editorial Committee.
In a short while, this crystallization of good timing, place, and people will be
sending off its inky fragrance from the desks of the editorial members and the
shelves of bookstores.
When describing the arduous compilation of the Handbook, Deputy Chief Editor
Yongwen Wang quoted a poetic stanza from the Qing-Dynasty scholar Guowei
Wang’s essay of criticism Notes and Comments on Poetry: “All those in pursuit of
great undertakings and great learning, ancient or modern, must of necessity go
through the following three states. First, ‘the west wind having withered the green
trees last night, the solitary man went atop the tall tower alone, scanning for path that
leads to the end of the world.’ Second, ‘one’s girdle grows slacker with the day, yet
one cares for none but his love for whom he pines away.’ Third, ‘Having searched a
thousand times in vain for my love in the crowd, I, with a sudden turn of my head,
spot her right in the shadow of the fading light.’”
The first state was that of groundwork. On August 31, 2015, I proposed to the
MIIT to compile the Series and the Handbook. On February 26, 2016, the Prepara-
tory Meeting of the Editorial Committee was held at Southern University of Science
and Technology in Shenzhen, at which a preliminary list of the Editorial Committee
members was drawn up, a top-level design of the overall structure was made, and a
xiv Preface

specific work plan was adopted. On May 7, 2016, the Editorial Committee was
formally established. Since then, the journey had begun of “the solitary man going
atop the tall tower alone, scanning for path that leads to the end of the world.”
The second state was that of engagement. Since May 7, 2016, all the writers had
begun the first draft of the Handbook. On February 19, 2017, the first review meeting
of the first draft was convened in Shenzhen. From May 7 to 21, 2017, the second
review meeting was held in SMIC, Shanghai, and another was held in Wanshou
Hotel, Beijing, from May 25 to 31, 2017. From July 14 to 27, 2017, the final review
meeting took place at China Workers’ Home in Beijing. This means that over the
15 months from May 2016 to August 2017, writers and reviewers of the Handbook
had entered the state in which “one’s girdle grows slacker with the day, yet one cares
for none but his love for whom he pines away.” The second and final reviews were
especially challenging. All the chapter editors, deputy chief editors of the Handbook,
as well as members of the Secretariat devoted all their energy and effort, laying the
foundation for a work which is authoritative, exact, professional, and up-to-date.
As of September 2018, we will enter the third state of “searching a thousand times
in vain for my love in the crowd and spotting her right in the shadow of the fading
light with a sudden turn of my head.” Looking back on the difficult journey of the
past 3 years, we will relish it with heartfelt gratification and will never recall this
period of our life with regret.

There is no end to progress; there is no stop to the fight.

When the Handbook comes out in 2018, it will fall on the 60th anniversary of the
invention of the integrated circuit. Back in 1958 on his summer vacation, Jack
S. Kilby analyzed various schemes, believing that there was no way out for further
miniaturizing existing components. Only by integrating active and passive compo-
nents on a semiconductor substrate could it be possible to really reduce costs, break
free the predicament he was in, and head for a new prospect. Then he demonstrated
on September 12, 1958, the first integrated circuit he designed and developed, which
was a germanium-based phase-shifting oscillator. In October Kilby successfully
developed germanium-based flip-flops, for which Texas Instruments applied for a
patent on May 6, 1959. Then on July 30, 1959, Robert N. Noyce, co-founder of
Fairchild Semiconductor Company, also developed his silicon planar integrated
circuit by planar process and applied for a patent. Noyce’s invention was of the
two more suitable for mass production. Both Kilby’s and Noyce’s contributions were
recognized by the US government, and they were successively inducted into the
National Inventors’ Hall of Fame. Flipping through the pages of the 60 years’
development of the integrated circuit, we find that it was essentially a history of
innovation. The application of CPU, memory, and other inventions and innovations
had brought about an information civilization. In 2000, the Royal Swedish Academy
of Sciences awarded Kilby the Nobel Prize for Physics in recognition of his
invention of the integrated circuit. Noyce’s early death in 1990 made it impossible
for him to win the same prize.
Preface xv

When Kilby was invited to visit Peking University in 2001, he said to me, “I knew
the integrated circuit I invented was useful, but I never expected it to be so useful.”
Yet the rapid development and wide application of the integrated circuit over the past
60 years were only natural given its very nature. Having expanded into integrated
systems, it now incorporates functions of information acquisition, processing, stor-
age, transmission, and random execution into one single tiny chip and can be
manufactured in large quantities with high reliability and low cost. Because of its
high price-performance ratio, good reliability, and great ability to process informa-
tion, the all-pervasive integrated circuit has found extensive use in various civil and
defense military systems. Like cells that make up the human body, it has become the
basis of various information systems. While it certainly cannot work without soft-
ware, the growth of software technology springs from demand for applications, and
the integrated system which ultimately fuses software and hardware can lend support
to the developing of various information systems. Therefore, nowadays the IC
industry has inevitably become the foundation of the national economy and defense
system. It is where the core competency of a country lies, and one of the indexes to a
country’s comprehensive strength.
At the same time, with the reduction in the feature size of integrated circuits, 7 nm
circuits have entered into small-batch production, and 5 nm/3 nm integrated circuits
have also begun to be developed. Some people thereby believe that this is about the
limit of device physics, claiming that the days of integrated circuits are numbered
and that their future is doomed. This is a grave misconception, because in the post-
Moore era, the practical meaning of feature size has changed. If we change our
mindset and measure the progress of integrated circuits and systems by reducing
power consumption, improving performance and the power/performance ratio, we
will, just as an ancient Chinese poem spells out, enter a new realm where “in the
midst of the overlapping mountains and winding rivers, one doubts whether there is
a way out, yet dark willows and bright blossoms reveal another village ahead.” This
is the first feature of the post-Moore era.
At present, the integration of the integrated circuit has reached 1011 transistors.
The power consumption of a single unit is only a few picowatts (pW), with an area
about 100 nm2, which is smaller than a human cell. It can even be embedded in the
human body, human brain and various artificial intelligence devices, thus opening a
whole new field of innovation.
Information is the most active factor of all factors in the information era.
Mastering and utilizing information is a revolutionary innovation. Information and
its utilization system will penetrate all fields of science and technology, as well as all
aspects of human life and production.
Thus it is clear that the development of the integrated circuits and systems has
only just begun and that the future is limitless. Even the industrial production of
silicon integrated circuits will not shrink in the short term. It will exist in the twenty-
first century and the century beyond. Of course, its materials, processes, device
structures, and packaging forms are constantly improving and innovating, just as the
aircraft invented by the Wright brothers back in 1903 is still progressing rapidly after
more than a century. Likewise, the train was invented in 1814 and has had a history
xvi Preface

of more than 200 years, yet it still needs to be developed into new means of high-
speed transportation.
China’s integrated circuits still have a long way to go. Since the 18th National
Congress of the Communist Party of China held in 2012, the country’s integrated
circuits have been developing at a high speed. The average growth rate over the past
5 years is 2.7 times that of the world growth rate. Yet, there still remains the problem
that the core technologies are not in our own hands. We must therefore fully grasp
the dual properties of the integrated circuit in strategic significance and market value
and keep its sustainable growth by its own objective laws. We should rid ourselves of
all impetuosity, remain determined, and make steady, rapid, and orderly headway.
The IC industry is capital-, technology- and talent-intensive. Ever since the
establishment of the National Integrated Circuit Industry Investment Fund, there
have been signs of gradual increase in capital flow. But the key still lies in talent.
Capital ultimately calls for talent. Scientific and technological innovation is the
result of human creativity supported by capital. Only when combined with talent
can capital work magic. The shortage of talent is the biggest obstacle to the
development of the integrated circuits in China. The country’s opening up to the
world has attracted talent from all over the world to invest, start business, and seek
opportunities in China. But in the end, we have to depend on ourselves for the
cultivation of high-quality talent who can take it upon themselves to meet the
country’s strategic requirements. We welcome more entrepreneurs, particularly
leading talent in the chain of the IC industry. To this end, we must deepen our
reform across various fields such as the existing talent-evaluation system, disciplin-
ary distribution, faculty building, curriculum system, and better merge teaching with
industry. We must upgrade the discipline of Microelectronics and Solid-State Elec-
tronics from a Grade-2 Discipline to Grade-1 (tentatively named “Micro-
nanoelectronics Science and Integrated Circuit Engineering”) and adapt it to the
national strategic needs and market development. A sufficient talent supply serves as
the only means of achieving the grand goal of building a strong and modernized
socialist country.
To achieve breakthroughs in key technologies, we should first give support to
universities and research institutes to carry out basic research. Second, we should
vigorously support enterprises to carry out their R&D. Third, we should emphasize
the fusion of industrial application with teaching and research, establishing an
industry-university-research alliance. Only by persistence and perseverance can we
truly grasp the key technologies in the IC industry.
Ever since the outbreak of the Opium War in 1840, the Chinese nation had gone
through numerous historical hardships and difficulties. Now, under the leadership of
the Communist Party, it was reborn from fire and is quickly striding towards
prosperity and revival. In this information age, China is to take integrated circuit
and software as its support for furthering the sustainable development of its national
economy, achieving the Two Centenary Goals put forward by the Communist Party’s
Central Committee and building a strong, beautiful, democratic, civilized, harmoni-
ous, and modernized socialist power.
Preface xvii

Today, The Handbook of Integrated Circuit Industry has been written and com-
piled in this spirit. In the future, we will continue our compilation edition after
edition. When the time has come for the next compilation to be made, I may not be
the Editor-in-Chief, but the younger generations will certainly carry on. General
Secretary Jinping Xi said at the Academicians’ Congress: “The youth are the
prospect of the country, the hope of the nation, and the future of innovation.”
There is no end to progress and there is no stop to the fight. I believe younger
generations will surely do better than us, just like the waves of the Yangtze River
keep driving on those ahead, each higher than the ones ahead.
During the writing and compiling of the Handbook, our contributors and
reviewers were very diligent and conscientious. The chief editors of each chapter
organized reviews and revisions of their chapters many times, and the Editorial
Committee convened three review meetings. The second review was the most
rigorous of all as it inspected and revised the Handbook chapter by chapter, entry
by entry over a period of more than 6 months. When it was finally completed, the
Handbook had gone through six revisions. It is fair to say that we have done our best.
Still, we must allow that every contributor is a product of his time and place. His
knowledge is certainly limited; his writing may be inadequate, even incorrect. We
hope readers will not hesitate to criticize and correct the mistakes wherever there are
and offer suggestions for future improvement and reprinting. As I said at the
founding meeting of the Editorial Committee, we would pay close attention to the
feedback of the readers after the publication and consider bringing out versions in
traditional Chinese and English in due course. So there is still room for improvement
and development.
There are also drawbacks in the overall planning of the Handbook. For one thing,
the Handbook has not listed the management of the IC industry as an independent
chapter, though it is a great subject on its own. It is where efficiency and productivity
come from, especially when we are now in the middle of deepening the reform.
While almost all universities have management schools and there is a wealth of
management talent, both experience and talent in writing have yet to be accumulated
as far as management of the IC industry goes. In the case of our Handbook, the
content related to management is scattered over chapters. With the Series, however,
we have listed “Management of the Integrated Circuit Industry” as a single volume,
hoping to present a monograph on this subject. Similarly, we have not been able to
set industrial development, education, and talent training as a separate chapter. Even
if we have, education, as a constant concern of human society and basis of social
development, cannot be dealt with properly by a single chapter in our Handbook. A
look at the history of the IC industry shows that it always develops first in places
where education is advanced and talented people are gathered, such as the Silicon
Valley of the United States, Zhongguancun of China, and Tsukuba of Japan. The
links between the two are worth pondering. For this reason, we have listed education
and talent training as a separate volume in the Series. It is hoped that the above
shortcomings will be remedied when the Handbook is reprinted. There is no such
thing in the world as a thorough text, a complete book, or a perfect person. I know
xviii Preface

problems and shortcomings are inevitable, especially when the writing styles of
468 authors and 125 reviewers are so very different. “The sea refuses no river. It is
huge because of its capacity.” It is of great benefit for readers to allow different
academic viewpoints to exist under unified rules. I sincerely hope that readers will
not only tolerate but also point out the shortcomings, problems, and mistakes in the
Handbook so as to help us produce better editions in the future.

Acknowledgments
Finally, I would like to thank all the administrators, enterprises, entrepreneurs,
scientists, technicians, engineers, and publishers for their support for and participa-
tion in the writing, compilation, and publication of the Handbook. Without the
support of the National Advisory Committee and its Secretariat, as well as the
MIIT (especially its Division of Electronic Information), this Handbook would not
have been possible. It was also the result of the joint efforts of 468 writers, 125
reviewers and editors. They are the backbone and mainstay of China’s IC industry
and the country’s development in science and technology. We should cherish their
enthusiasm and safeguard their intellectual contribution as we protect our own eyes.
Just as the Confucian scholar Xi Zhu of the Southern Song Dynasty (1127–1279)
says in a poem, “Why does the pool remain so clear? For running water keeps
flowing in from its source, keeping it alive and fresh,” it is the trickles of these
people’s dedication that makes the river of originality flow forever.
I would also like to express my special thanks to Southern University of Science
and Technology, Shenzhen National Integrated Circuit Design Industrial Base,
Shenzhen National Microelectronics Co., Ltd., SMIC Co., Ltd., Huada Semicon-
ductor Co., Ltd., National Integrated Circuit Industry Investment Fund Co., Ltd., and
Beijing Huada Jiutian Software Co., Ltd., among others. They have generously
supported the convening of the preparatory meeting, the three review meetings,
and the acceptance meeting of the Handbook. I would also like to thank the Institute
of Microelectronics and Nanoelectronics, Peking University, for its generosity in
obtaining copyright licenses for data, charts, and all the references, thus enabling our
Handbook to have complete intellectual property rights. Pertaining to this, I would
also like to thank all the members of the Secretariat of the Editorial Committee for
their hard work in duplicate checking, copyright consultation, and conference
organizing. My sincere thanks also go to Editor-in-Chief Jiuru Liu, Senior Editor
Jian Zhang, and Associate Senior Editor Haiyan Liu, of the Electronic Industry
Publishing House, for their full participation, close cooperation, and effective
coordination in transforming the drafts into the Handbook. The elegant design
proposals they offered are pleasing to our eyes. We hope the Handbook will become
“a classic of this flourishing age” in China’s IC library and bring good luck to the
compilation of the Series. I hope the Series will continue to emerge as a spring of
wisdom and culture and be with us all our lives to nourish the continuous develop-
ment of the IC industry and science and technology in our country.
The innovative growth of the IC industry and its related science and technology in
China will surely make a unique contribution characteristic of the Chinese nation to
Preface xix

the continuous expansion of the global IC industry. The heyday of China’s IC

technology as well as industry will not keep us waiting for too long!

First draft during the Spring Festival 2018 in Shenzhen

Revised in midsummer 2018 in Peking University
Acknowledgments

The authors would like to acknowledge contributions for the following listed
individuals.
Contributions to Section 2: Yongle Qi, Xiaoyu Sun, Wentao Li, Xinke Liu, Cong
Hu, Ning Wang, Jack Pan, Yunfei Liu, Peter Feng, Yuzhen Liu, Chole Ma, Hongsha
Wang, Ting Ma, Yu-Hua Chen, Song Chen, Xiao Luo, Monica Liu, Kanglin Xiao,
Haotian Zhong, Kuan-Chang Chang, Hang Zhou, Huiling Lu, Xiaoliang Zhou, Yang
Shao, Ming-Jiang Wang, Lu Zhang, Hao Liu, Congwei Liao, He Huang, Wei Wang,
Bowei Huang, Wengao Lu, Hang Zhou, Xuanjie Liu, Qi Liu, Yuzheng Liu, Qianli
Ma, Guoxin Zhang, David Xu, Shipeng Sun, Yuxin You, Lingyun Zhang, He Sun,
Hao Ma, Qiuping Li, Yufan Feng, Yingying Wu, Bohang Li, Kangsheng Zhou, Cong
Jiao, Xian-Nian Lu, Qiquan Zhang, Yong Zhao, and Han Xiang.
Contributions to Section 6: Yu Wang, Jiajia Liu, Gang Du, Jun Ge, Zhaoyi Zhang,
Shaiying Shen, Jun Chen, Hao Wang, Wei Tian, Pin Li, Jian Wang, Yi Xiao,
Yongxiang Wen, Zhongwei He, Feng Qian, Rongzhong Xia, Weituan Jiang, Yong
Wang, Chuanfeng Xin, Yongliang Zhu, Hai Jiang, Zhiyong Yang, Gang Sun, Yijiao
Wang, Zhaozhao Xu, Huiyong Liu, Kaixuan Yu, Jianming Li, and Wei Su.

xxi
Contents

Volume 1

Section I Technology and Industry Development of

Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Min-Zheng Zheng, Yong-wen Wang, and Ke Li
1 Invention and Technological Progresses of
Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Yong-Wen Wang and Min-Zheng Zheng

2 Characteristics and Strategic Significance of IC Industry . . . . . . . 25

Yong-Wen Wang and Min-Zheng Zheng

3 The Development Law of the IC Industry . . . . . . . . . . . . . . . . . . . 31

Yong-Wen Wang and Min-Zheng Zheng

4 Development of World IC Industry ........................ 45

Da-Kang Mo and Ke Li

5 Development of Regional IC Industry ...................... 81

Guoming Zhang and Ke Li

6 Information Security in Integrated Circuits . . . . . . . . . . . . . . . . . . 91

Chaohui Wang, Qinsheng Wang, and Qian Peng

7 Integrated Circuit Intellectual Property . . . . . . . . . . . . . . . . . . . . . 109

Bulu Xu

8 International Competition and Cooperation . . . . . . . . . . . . . . . . . 115

Guoqiang Li, Zhaozhao Xu, and Min-Hwa Chi

9 Integrated Circuit Enterprise Management . . . . . . . . . . . . . . . . . . 123

Ke Li, Kai Zheng, and Min Zhu

10 Talent Cultivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Ke Li, Yong-Wen Wang, Yumei Zhou, and Chun-Zhang Chen

xxiii
xxiv Contents

Section II Classification and Applications of IC Products ......... 155

Shengming Zhou, Chun-Zhang Chen, and Xin-An Wang
11 Development and Classification of IC . . . . . . . . . . . . . . . . . . . . . . . 157
Song Zhang, Kaiwei Zhang, and Yutao Huo
12 Classification of IC Products by Manufacturing Processes . . . . . . 165
Xinnan Lin, Mingxia Qiu, Fei Wang, Lenian He, and
Jesse Jen-Chung Lou
13 Products of Digital Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . 187
David Hu, Alex Lin Jia, Fan-Yi Jien, Xia Ai, and
Chun-Zhang Chen
14 Analog and Mixed-Signal IC Products . . . . . . . . . . . . . . . . . . . . . . 233
Yuheng Guan, Fan Lai, Yuhua Chen, Yi Sun, and Gangyi Hu
15 Radio Frequency IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Bo Wang, Yan Li, and Xin-An Wang
16 Products of Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Xinnan Lin, Zheng Gong, and Jesse Jen-Chung Lou
17 Products of Optoelectronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . 335
Yizhe Sun, Wen Yu, Letao Zhang, and Shengdong Zhang
18 Products of Sensors and MEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Yu-Fei Han, Yun-Zhuo Sun, Mingjiang Wang, Qiang Liu, and
Ran Tao
19 Applications of IC Products in Consumer, Computer,
and Communication Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Yieji Zhu, Hui Liu, Yongxin Liu, Guoqiang Li, and
Shengming Zhou
20 Applications of IC Products in Automotive, Industrial,
and Medical Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Quan Yan, Qiquan Zhang, Xin-An Wang, and Huan Liu
21 Applications of IC Products in Aero-Mil . . . . . . . . . . . . . . . . . . . . 423
Gang Liu, Qiquan Zhang, Fang-Lin Yan, Yuewen He, and
Chuan Deng

Section III Integrated Circuit Industrial Economy and

Investment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Zixue Ζhou, Yue Liu, Fangfang Li, Ying Cai, and Ke Feng
22 Economic and Financial Theories Related to IC Industry . . . . . . . 451
Zixue Zhou, Fangfang Li, Yaoliang Qi, and Bojing Zheng
Contents xxv

23 Development Law and Development Index of IC Industry . . . . . . . 473

Tong Feng, Kai Zheng, and Kelu Hua
24 Financial Management Practice and Analysis of
Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Ying Cai, Yuwen Xue, Yanlun Yan, and Jianyue Pan
25 Investment and Financing of IC Industry . . . . . . . . . . . . . . . . . . . 533
Yingping Hu, Yang Liu, Ming Yin, and Cheng Zhang

Section IV Integrated Circuit Production Lines . . . . . . . . . . . . . . . . . 557

Richard Chang, Lei Jiang, Yibo Wang, and Yonghang Yu
26 Development History of IC Production Lines . . . . . . . . . . . . . . . . . 559
Janet Zeng
27 Location and Environmental Impact Assessment of IC
Production Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Thomas Hsu
28 Designing IC Production Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
T. C. Wang
29 Clean Room and Air Conditioning Systems . . . . . . . . . . . . . . . . . . 603
Deyuan Xiao
30 Central Gas and Chemical Supply Systems . . . . . . . . . . . . . . . . . . 611
Deyuan Xiao
31 Construction and Management of IC Production Lines ........ 621
Shuying Wang
32 Hazardous Chemicals Management . . . . . . . . . . . . . . . . . . . . . . . . 639
Deyuan Xiao
33 Energy Savings and Development Trends ................... 647
Deyuan Xiao and Janet Zeng

Section V Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Shaojun Wei, Xiaolang Yan, and Yuhua Cheng
34 Overview of IC Design .................................. 659
Shouyi Yin
35 Basics of Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . 667
Cheng Huang, Qinsong Qian, Chao Chen, Wei Ge, and Jian Cao
36 Digital Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Jun Yang, Peng Cao, Weiwei Shan, Longning Qi, and
Xinning Liu
xxvi Contents

37 Analog Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . 711

Yuhua Cheng, Song Ma, Lele Jiang, Long Zhao, and Bao Li
38 RF Integrated Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Pengcheng Xiao, Yumei Huang, Wei Li, Na Yan, and
Xiaoyang Zeng
39 Power Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Tianshen Tang, Hao Ni, and Xiaoyan Liu
40 Design of Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
Xiaolang Yan, Jianyi Meng, and Zhijian Chen
41 Memory Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
Fujun Bai, Xiaowei Han, and Liyang Pan
42 SoC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Xiaolang Yan, Kai Huang, and Jianyi Meng
43 Programmable Logic Circuit Design ....................... 821
Shaojun Wei and Shouyi Yin
44 Electronic Design Automation Tools . . . . . . . . . . . . . . . . . . . . . . . . 829
Xiaoming Liu, Yi Liu, Taotao Lu, Fan Yang, and Junqi Yang

Section VI IC Manufacturing and Management . . . . . . . . . . . . . . . . . 861

Min-Hwa Chi, Nanxiang Chen, Hanming Wu, Haijun Zhao, and
Weihai Bu
45 The Evolution of IC Manufacturing Technology . . . . . . . . . . . . . . 863
Weihai Bu and Wenbo Wang
46 Silicon-Based Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 871
Weihai Bu, Wenbo Wang, and Poren Tang
47 Compound Semiconductor Device and IC . . . . . . . . . . . . . . . . . . . 883
Min-Hwa Chi, Ying-Kun Liu, and Long Qin
48 Micro Electro-Mechanical Systems (MEMS) . . . . . . . . . . . . . . . . . 895
Yunqian He, Aisheng Yu, Xuanjie Liu, and Yuelin Wang
49 Unit Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
Hanming Wu, Hong Xiao, Weihai Bu, Shan Yu, and Poren Tang
50 Module Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Hanming Wu, Shan Yu, Hong Xiao, and Poren Tang
51 Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Min-Hwa Chi
52 Types of Integrated Circuit Corporations . . . . . . . . . . . . . . . . . . . 979
Nanxiang Chen, Shilin Fang, Rufei Chai, and Guoqiang Li
Contents xxvii

53 Management and Mode of IC Manufacturing

Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Xiangdong Chen, Jianxin Yan, and Liang Ma

Volume 2

Section VII Packaging and Testing of IC Products . . . . . . . . . . . . . . . 1013

Keyun Bi, Xiekang Yu, Hongwei Sun, and Daquan Yu
54 Development of Packaging and Testing Industry . . . . . . . . . . . . . . 1015
Jian Cai, Guoliang Yu, Hongwei Sun, Jian Wu, and Lin Tan

55 Integrated Circuit Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . 1027

Guoliang Yu, Haizhong Shi, and Honghui Wang

56 Key Technologies and Processes for Traditional Packaging . . . . . . . 1069

Daquan Yu, Zhi-Quan Liu, Ming Li, Linghua Zhu, and
Xiaowei Guo

57 Process and Key Technology of Typical Advanced Packaging . . . . 1093

Steve Xinfu Liang, Chihchung Liang, Hongyan Guo,
Weidong Liu, and Xusheng Bao

58 Design Technologies for Advanced Packaging . . . . . . . . . . . . . . . . 1129

Jun Li, Yunyan Zhou, Min Miao, Wei Wang, Fei Su, and
Fengman Liu

59 Integrated Circuit Testing Technology . . . . . . . . . . . . . . . . . . . . . . 1153

Zhiyong Zhang, Jianhua Qi, Kun Yu, and Qin Wang

60 Integrated Circuits Packaging Reliability . . . . . . . . . . . . . . . . . . . . 1185

Anjun Huang, Rongzheng Ding, Hanwu Xiao, Jian Lu, and
Hongwei Luo

61 Standardization of Integrated Circuits Packaging . . . . . . . . . . . . . 1207

Le Luo, Jing Wang, and Kun Li

Section VIII IC Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221

Tianchun Ye, Zhiyao Yin, Jinrong Zhao, Yuan Pu, and Baoqin Chen
62 The Development of the IC Equipment Industry . . . . . . . . . . . . . . 1223
Guoming Zhang

63 Manufacturing Equipment for Silicon Wafer . . . . . . . . . . . . . . . . . 1237

Bin Liu

64 Mask Manufacturing Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . 1285

Baoqin Chen, Boru Feng, and Jesse Jen-Chung Lou
xxviii Contents

65 Lithography Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327

Rongming He, Jianrui Cheng, and Fan Wang
66 Diffusion and Ion Implantation Equipment . . . . . . . . . . . . . . . . . . 1361
Zhaoyang Cheng, Xiaozhen Liu, Junyu Xie, and Zhuliang Zuo
67 Thin Film Growth Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
Yang Xia, Peijun Ding, Jinrong Zhao, Bin Yin, and
Xiaoping Shi
68 Plasma Etch Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1441
Yuan Pu
69 Wet Cleaning Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
Fuping Chen, Xiaoyan Zhang, Xi Wang, Zhaowei Jia, and
Yinuo Jin
70 Metrology and Inspection Equipment . . . . . . . . . . . . . . . . . . . . . . 1527
Feng Yang
71 Packaging and Assembly Equipment . . . . . . . . . . . . . . . . . . . . . . . 1569
Lezhi Ye and Qiangsheng Guo
72 Main Common Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
Zhaoyang Cheng, Dongshan Li, Changhua Mou, Jinwei Dong, and
Chunlei Li
73 Integrated Circuit-Testing Equipment . . . . . . . . . . . . . . . . . . . . . . 1629
Yanfeng Jiang, Zhiyong Zhang, Kun Yu, and Jianhua Qi

Section IX Integrated Circuits Materials . . . . . . . . . . . . . . . . . . . . . . . 1643

Deren Yang, Jingfeng Kang, and Xuegong Yu
74 Silicon Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
Deren Yang and Xuegong Yu
75 Silicon Wafer Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
Deren Yang, Xingbo Liang, and Xuegong Yu
76 Defects and Impurities in Silicon Materials . . . . . . . . . . . . . . . . . . 1677
Deren Yang and Xiangyang Ma
77 Compound Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
Deren Yang, Jingfeng Kang, and Xuegong Yu
78 Photomask and Photoresist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717
Deren Yang, Ying Shi, and Xuegong Yu
79 Auxiliary Material in Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
Deren Yang, Maojun Wang, and Xuegong Yu
Contents xxix

80 Package Structure Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1775

Deren Yang, Tong Yuan, and Xuegong Yu

Section X Basic Research and Frontier Technology

Development of Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801
Xing Zhang, Jun Xu, Longxing Shi, and Lifeng Liu
81 Non-traditional New Structure Devices . . . . . . . . . . . . . . . . . . . . . 1803
Yimao Cai, Jun Xu, Renrong Liang, Qianqian Huang, and
Zongwei Wang
82 New Type ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
Nanjian Wu, Huaxiang Lu, Yongpan Liu, Leibo Liu, and
Baoyong Chi
83 New Materials Used in IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
Yunyi Fu, Tianli Duan, and Hongyu Yu
84 Advanced IC Manufacturing Processes . . . . . . . . . . . . . . . . . . . . . 1865
Hanming Wu, Jesse Jen-Chung Lou, Hong Xiao, Yimao Cai, and
Yuancheng Yang
85 New Technology in Integration and Interconnection . . . . . . . . . . . 1873
Zheyao Wang and Xue Feng
86 Modeling and Simulation of Nano-devices . . . . . . . . . . . . . . . . . . . 1881
Fei Liu, Yijiao Wang, Lang Zeng, Gang Du, and Xiaoyan Liu
87 Flexible Semiconductor Devices (FSD) . . . . . . . . . . . . . . . . . . . . . . 1893
Yi Shi, Yun Li, and Sai Jiang
88 Integrated Microsystem Technology . . . . . . . . . . . . . . . . . . . . . . . . 1915
Wei Wang, Haixia Zhang, and Zhenchuan Yang
89 Advanced Characterization and Testing Techniques . . . . . . . . . . . 1923
Runsheng Wang, Jianhua Feng, and Jiayang Zhang
90 Aerospace Microelectronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939
Yuanfu Zhao, Suge Yue, Hongchao Zheng, and Liang Wang
Appendix A: List of Semiconductor Enterprises . . . . . . . . . . . . . . . . . . 1953
Appendix B: Reference Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
Appendix C: Abbreviations of IC Terminology . . . . . . . . . . . . . . . . . . . 1975
Appendix D: Common Glossaries of IC Industry . . . . . . . . . . . . . . . . . 1993
About the Editors

Yangyuan Wang is the Honorary Dean and Professor

of the School of Integrated Circuits at Peking Univer-
sity. He is an Academician of the Chinese Academy of
Sciences, an IEEE Life Fellow, IET (IEE) Fellow, and
CIE Fellow. His research in the field of microelectronics
primarily focuses on new devices, new processes, and
new structured circuits. He has authored more than
400 academic papers and 14 books and holds over
130 invention patents. Contributions include 20 major
scientific and technological achievements, and so far he
has been awarded 21 national and ministry awards,
including the National Science Congress Awards, the
National Invention Awards, the National Science and
Technology Progress Awards, and the inaugural
Yuanpei Tsai Award of Peking University. Throughout
his career, He has mentored over 100 MSc students,
PhD students, and postdoctoral researchers.
In 1958, he graduated from the Physics Department
of Peking University and began teaching at the same
institution. He was the Director of the Institute of Micro-
electronics, the Director of the Department of Micro-
electronics of Peking University, the Director of the
National ICCAD Expert Committee, the Director of
the National ICCAT Expert Committee, and the Director
of the National Integrated Circuit Product Development
Expert Committee. Additionally, he has served as the
Vice Chairman of the Chinese Institute of Electronics.
As one of the founders of SMIC Manufacturing Co.,
Ltd., he has served as the chairman of entities and listed
companies. He also established the IEEE International
Conference on Solid-State and Integrated Circuit Tech-
nology (ICSICT).

xxxi
xxxii About the Editors

Yangyuan Wang currently also serves as a Consultant

of the Electronic Science and Technology Committee of
the Ministry of Industry and Information Technology, and
as the Associate Chief Editor of the Journal of Semicon-
ductors and Journal of Electronics (English edition).

Min-Hwa Chi
GTA Semiconductor
Shanghai, China

Dr. Min-Hwa Chi received his BS, MS, and PhD in EE

at National Taiwan University, University of Rhode
Island, and University of California-Berkeley (1982),
respectively.
He has served VLSI industry in Intel (1982–1988),
KFI technology (1988–1994), and National Semicon-
ductor (1994–1997) in NVM, CMOS-Imager, and mod-
ule process development. He served foundry industry
for TSMC (1997–2005 as Sr. Director/R&D),
GlobalFoundries (2011–2015 as Sr. Fellow/Dir), SMIC
China (2006–2011 and 2015–2018 as SVP), and SiEn
(QingDao) Integrated Circuits (2018–2021 as SVP/TD).
He is now the chief scientist at GTA Semiconductor.
He served as guest professor at Qingdao University
(2019~) and Peking University (2010–2011) and honor-
ary professor at Fu-Dan University (2008–2010) at
China. He is IEEE Life Sr. member (2001). He has
262 US patents (or >600 international patents) and has
published 3 books and more than 105 technical papers in
areas of CMOS Logic/FinFET, Flash memory, CMOS
Imager, DRAM, and power devices.
Jesse Jen-Chung Lou
Peking University
Beijing, China

Professor Jesse Jen-Chung Lou graduated from the

Department of Physics and the Institute of Physics of
Tsinghua University (Taiwan). He received his Ph.D.
from the Department of Electrical Engineering and
Computer Sciences at the University of California,
Berkeley, USA. Prof. Lou has taught in the Department
of Electrical Engineering of Tsinghua University (Tai-
wan) and the Department of Electronic Engineering of
Chiao Tung University (Taiwan) for many years, and
About the Editors xxxiii

then severed as a full professor in the Department of IC

& Intelligent System Engineering at the School of Soft-
ware and Microelectronics of Peking University
(2010–2021). His research interests include high-K
dielectric growth technology, low-K dielectric materials,
silicon selective epitaxial growth technology, advanced
lithography process, defect and failure analysis technol-
ogy in integrated circuits, advanced RRAM materials
and device structures, MOCVD growth LED quantum
well and high brightness LED technology, GaN and SiC
heteroepitaxial growth technology, high power SiC
devices, etc. Prof. Lou’s team has participated in
research projects and training programs of TSMC,
UMC, PowerChip, MXIC, ITRI, BCD (Shanghai),
SMIC (Shanghai), Applied Materials (Taiwan), Chang-
zhou Jingyuan Optoelectronics (China), and other
companies.
Prof. Lou has published 104 papers and obtained
20 patents. In addition, he has translated 5 books on
integrated circuits and has been awarded as “an excel-
lent teacher” at the School of Software and Microelec-
tronics of Peking University seven times. Currently, he
continues to lead a research team to assist the integrated
circuit Fabs to develop products. Professor Lou also
participated in the establishment of the Semiconductor
Academy, acted as a technical consultant to several
enterprises, assisted the industry in developing training
systems, and implemented a number of integrated circuit
personnel training programs.

Chun-Zhang Chen
Peng Cheng Laboratory
Shenzhen, Guangdong, China

Dr. Chun-Zhang Chen is currently a research fellow at

Peng Cheng Lab in Shenzhen, Guangdong, China. He is
a professor adjunct at both University of Chinese Acad-
emy of Sciences (teaching a summer class since 2014)
and Zhejiang University (since 2021).
His research interests include design and verification
methodology of integrated circuit (IC), system-on-chip
(SoC), and high-speed interface IP. Research on IC
design is extended to its reliability including mechanism
of radiation resistance. In his job at Cadence Design
Systems (1997–2013), he has contributed to the industry
xxxiv About the Editors

timing-driven design (TDD) flow and hierarchical meth-

odology in IC/SoC design in the late 2000. Towards
SoC design using EDA, he co-authored a book on
digital IC physical design methodology and has trans-
lated a book of mixed-signal IC design guide. He has
worked in a variety of roles, from a field application
engineer (AE), EDA instructor, technical director, etc. In
2003, he also spent 3 years in a joint venture named
ZCIST, a.k.a. Cadence University, to lead then a world-
class IC training program of IC talents.
Dr. Chen’s previous career was as a research scien-
tist. He spent 8 years (1987–1995) at Brookhaven
National Lab, University of California – San Francisco,
and Columbia University, where his areas of focus were
the effects of ionizing radiations (X-, γ-rays, n, e, α, etc.)
on biological targets (mammalian cells, chromosomes,
and DNAs). After graduating from the University of
Science and Technology of China, he worked at the
Institute of Biophysics of the Chinese Academy of Sci-
ences, followed by receiving an MSc and PhD on Radi-
ation Physics (1984, 1987) from St. Andrews
University.
Contributors

Xia Ai Cadence Design Systems, Inc., Beijing, China

Fujun Bai Xi’an UniIC Semiconductors Co., Ltd., Xi’an, Shaanxi, China
Xusheng Bao JCET Group Co., Ltd., Wuxi, China
Weihai Bu Semiconductor Technology Innovation Center (Beijing) Corporation,
Beijing, China
Jian Cai School of Integrated Circuits, Tsinghua University, Beijing, China
Yimao Cai Institute of Microelectronics, Peking University, Beijing, China
Ying Cai Summitview Capital, Beijing, China
Jian Cao School of Software and Microelectronics, Peking University, Beijing,
China
Peng Cao National ASIC System Engineering Center, Southeast University, Nan-
jing, China
Rufei Chai China Resources Microelectronics Ltd., Wuxi, China
Baoqin Chen Institute of Microelectronics (IME), Chinese Academy of Sciences,
Beijing, China
Chao Chen National ASIC System Engineering Center, Southeast University,
Nanjing, China
Chun-Zhang Chen Peng Cheng Lab, Shenzhen, China
Fuping Chen ACM Research (Shanghai), Inc., Shanghai, China
Nanxiang Chen Yangtze Memory Technologies Co., Ltd., Wuhan, China
Xiangdong Chen Hangzhou Silan Microelectronics Co., Ltd., Hangzhou, China
Yuhua Chen Peking University, Beijing, China
Zhijian Chen Institute of VLSI, Zhejiang University, Hangzhou, China

xxxv
xxxvi Contributors

Jianrui Cheng Shanghai Micro Electronics Equipment (Group) Co., Ltd (SMEE),
Shanghai, China
Yuhua Cheng Institute of Microelectronics, Peking University, Beijing, China
Zhaoyang Cheng Beijing NAURA Microelectronics Equipment Co., Ltd
(NAURA), Beijing, China
Baoyong Chi Institute of Microelectronics, Tsinghua University, Beijing, China
Min-Hwa Chi GTA Semiconductor Co., Ltd., Shanghai, China
Chuan Deng National IC Design Shenzhen Industrial Centre, Shenzhen, China
Peijun Ding Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA),
Beijing, China
Rongzheng Ding China Key System Co., Ltd (CKS), Wuxi, China
Jinwei Dong Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing,
China
Gang Du Institute of Microelectronics, Peking University, Beijing, China
Tianli Duan Southern University of Science and Technology, Shenzhen, China
Shilin Fang China Resources Microelectronics Ltd., Wuxi, China
Boru Feng Institute of Optics & Electronics (IOE), Chinese Academy of Sciences,
Beijing, China
Jianhua Feng Institute of Microelectronics, Peking University, Beijing, China
Tong Feng Semiconductor Manufacturing International Corporation, Beijing,
China
Xue Feng Department of Electronic Engineering, Tsinghua University, Beijing,
China
Yunyi Fu Institute of Microelectronics, Peking University, Beijing, China
Wei Ge National ASIC System Engineering Center, Southeast University, Nanjing,
China
Zheng Gong Tunghai University, Taiwan, China
Yuheng Guan Huada Empyrean Software Co. Ltd., Beijing, China
Hongyan Guo Zhejiang Hexin Semiconductor Co., Ltd., Jiashan, China
Qiangsheng Guo CETC Beijing Electronic Equipment Co., Ltd., Beijing, China
Xiaowei Guo Huatian Technology (Xi’an) Co., Ltd., Xi’an, China
Xiaowei Han Xi’an UniIC Semiconductors Co., Ltd., Xi’an, Shaanxi, China
Yu-Fei Han Harbin Institute of Technology, Shenzhen, China
Contributors xxxvii

Lenian He Zhejiang University, Hangzhou, China

Rongming He Shanghai Micro Electronics Equipment (Group) Co., Ltd (SMEE),
Shanghai, China
Yuewen He Shenzhen Institute of Micro-nano IC and System Application,
Shenzhen, China
Yunqian He Huawei Technologies Co., Ltd., Shanghai, China
Thomas Hsu SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
David Hu EtownIP Microelectronics Co. Ltd., Beijing, China
Gangyi Hu China Electronics Technology Group Corporation 24th Institute,
Chongqing, China
Yingping Hu Hua Capital Management Co., Ltd., Beijing, China
Kelu Hua Semiconductor Manufacturing International Corporation, Shanghai,
China
Anjun Huang Shanghai Huahong Grace Semiconductor Manufacturing Corpora-
tion, Wuxi, China
Cheng Huang National ASIC System Engineering Center, Southeast University,
Nanjing, China
Kai Huang Institute of VLSI, Zhejiang University, Hangzhou, China
Qianqian Huang Institute of Microelectronics, Peking University, Beijing, China
Yumei Huang School of Microelectronics, Fudan University, Shanghai, China
Yutao Huo China Center for Information Industry Development, Beijing, China
Alex Lin Jia Cadence Design Systems, Inc., Shanghai, China
Zhaowei Jia ACM Research (Shanghai), Inc., Shanghai, China
Lele Jiang Shanghai Research Institute of Microelectronics, Peking University,
Shanghai, China
Sai Jiang School of Electronic Science and Engineering, Nanjing University,
Nanjing, China
Yanfeng Jiang Beijing Institute of Automatic Test Technology, Beijing, China
Fan-Yi Jien Advanced Memory Semiconductor Co. Ltd., Jiangsu, China
Yinuo Jin ACM Research (Shanghai), Inc., Shanghai, China
Jingfeng Kang School of Electronics Engineering and Computer Science, Peking
University, Beijing, China
xxxviii Contributors

Fan Lai China Electronics Technology Group Corporation 24th Institute, Chong-
qing, China
Bao Li Shanghai Research Institute of Microelectronics, Peking University, Shang-
hai, China
Chunlei Li Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing, China
Dongshan Li Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing,
China
Fangfang Li Publishing House of Electronics Industry Co., Ltd., Beijing, China
Guoqiang Li Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd.,
Shanghai, China
Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, China
ICWise Market Information Consulting (Shanghai) Co., Ltd., Shanghai, China
Jun Li Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
Ke Li Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing,
China
Kun Li China Electronics Standardization Institute, Beijing, China
Ming Li School of Materials Science and Engineering, Shanghai Jiao Tong Uni-
versity, Shanghai, China
Wei Li School of Microelectronics, Fudan University, Shanghai, China
Yan Li Shenzhen University, Shenzhen, China
Yun Li School of Electronic Science and Engineering, Nanjing University, Nan-
jing, China
Chihchung Liang JCET Group Co., Ltd., Wuxi, China
Renrong Liang Institute of Microelectronics, Tsinghua University, Beijing, China
Steve Xinfu Liang JCET Group Co., Ltd., Wuxi, China
Xingbo Liang Ql Electronics Co., Ltd., Ningbo, China
Xinnan Lin Electronic and Computer Engineering, Peking University, Shenzhen,
China
Bin Liu The 45th Research Institute of China Electronics Technology Group
Corporation (CETC45), Beijing, China
Fei Liu Institute of Microelectronics, Peking University, Beijing, China
Fengman Liu Institute of Microelectronics, Chinese Academy of Sciences, Bei-
jing, China
Contributors xxxix

Gang Liu China Electronics Technology Group Corporation 14th Institute, Nan-
jing, China
Huan Liu Southern University of Science and Technology, Shenzhen, China
Hui Liu Huaqiang Electronic Industry Research Institute, Shenzhen, China
Leibo Liu Institute of Microelectronics, Tsinghua University, Beijing, China
Qiang Liu Shanghai Institute of Microsystem and Information Technology, Shang-
hai, China
Weidong Liu Tianshui Huatian Technology Co., Ltd., Tianshui, China
Xiaoming Liu Huada Empyrean Software Co., Ltd., Beijing, China
Xiaoyan Liu Silicon Storage Technology Inc. (SST), Shanghai, China
Institute of Microelectronics, Peking University, Beijing, China
Xiaozhen Liu Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA),
Beijing, China
Xinning Liu National ASIC System Engineering Center, Southeast University,
Nanjing, China
Xuanjie Liu Semiconductor Manufacturing Electronics (ShaoXing) Corporation,
Shaoxing, China
Yang Liu Hua Capital Management Co., Ltd., Beijing, China
Yi Liu Huada Empyrean Software Co., Ltd., Beijing, China
Ying-Kun Liu Hebei Semiconductor Research Institute, Shijiazhuang, China
Yongpan Liu Department of Electronic Engineering, Tsinghua University, Beijing,
China
Yongxin Liu Shenzhen Institute of Micro-nano IC and System Application,
Shenzhen, China
Zhi-Quan Liu Shenzhen Institute of Advanced Electronic Materials, Shenzhen
Institutes of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China
Jesse Jen-Chung Lou School of Software and Microelectronics, Peking Univer-
sity, Beijing, China
Institute of Microelectronics, Peking University, Beijing, China
Huaxiang Lu Institute of Semiconductors, Chinese Academy of Sciences, Beijing,
China
Jian Lu WiFi CMC Electronics Co., Ltd., Wuxi, China
Taotao Lu Huada Empyrean Software Co., Ltd., Beijing, China
xl Contributors

Hongwei Luo China Electronic Product Reliability and Environmental Testing

Research Institute, Guangzhou, China
Le Luo Shanghai Institute of Microsystem and Information Technology, Chinese
Academy of Sciences, Shanghai, China
Liang Ma Hangzhou Silan Microelectronics Co., Ltd., Hangzhou, China
Song Ma Shanghai Research Institute of Microelectronics, Peking University,
Shanghai, China
Xiangyang Ma State Key Lab of Silicon Materials, Zhejiang University, Hang-
zhou, China
Jianyi Meng Department of Microelectronics, Fudan University, Shanghai, China
Min Miao Beijing Information Science and Technology University, Beijing, China
Da-Kang Mo Truth Semi Group, Shanghai, China
Changhua Mou Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing,
China
Hao Ni Semiconductor Manufacture International Corporation, Shanghai, China
Jianyue Pan Summitview Capital, Beijing, China
Liyang Pan Institute of Microelectronics, Tsinghua University, Beijing, China
Qian Peng Bank Card Test Center, Chengdu, China
Yuan Pu Advanced Micro-Fabrication Equipment Inc. (AMEC), Shanghai, China
Jianhua Qi Sino IC Technology Co., Ltd., Shanghai, China
Longning Qi National ASIC System Engineering Center, Southeast University,
Nanjing, China
Yaoliang Qi Hua Capital Investment Management Co., Ltd., Beijing, China
Qinsong Qian National ASIC System Engineering Center, Southeast University,
Nanjing, China
Long Qin Hebei Semiconductor Research Institute, Shijiazhuang, China
Mingxia Qiu College of New Materials and New Energies, Shenzhen Technology
University, Shenzhen, China
Weiwei Shan National ASIC System Engineering Center, Southeast University,
Nanjing, China
Haizhong Shi TongFu Microelectronics Co., Ltd., Nantong, China
Xiaoping Shi Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA),
Beijing, China
Contributors xli

Yi Shi School of Electronic Science and Engineering, Nanjing University, Nanjing,

China
Ying Shi Integrated Circuit Materials Innovative Alliance, Peking, China
Fei Su Beihang University, Beijing, China
Hongwei Sun National Center for Advanced Packaging Co., Ltd., Wuxi, China
Yi Sun University of Chinese Academy of Sciences, Beijing, China
Yizhe Sun Electronic and Computer Engineering, Peking University, Shenzhen,
China
Yun-Zhuo Sun Harbin Institute of Technology, Shenzhen, China
Lin Tan School of Integrated Circuits, Tsinghua University, Beijing, China
Poren Tang Semiconductor Manufacturing International Corp, Shanghai, China
Tianshen Tang Leapfive Technology Co., Ltd., Guangdong, China
Ran Tao Synopsys, Shanghai, China
Bo Wang Electronic and Computer Engineering, Peking University, Shenzhen,
China
Chaohui Wang Beijing Huada Infosec Co., Ltd., Beijing, China
Fan Wang Shanghai Micro Electronics Equipment (Group) Co., Ltd (SMEE),
Shanghai, China
Fei Wang School of Microelectronics, Southern University of Science and Tech-
nology, Shenzhen, China
Honghui Wang TongFu Microelectronics Co., Ltd., Nantong, China
Jing Wang China Electronics Standardization Institute, Beijing, China
Liang Wang Beijing Microelectronics Technology Institute, Beijing, China
Maojun Wang School of electronics engineering and computer science, Peking
University, Beijing, China
Mingjiang Wang Harbin Institute of Technology, Shenzhen, China
Qin Wang Shanghai Jiao Tong University, Shanghai, China
Qinsheng Wang IC Design Branch, China Semiconductor Industry Association,
Beijing, China
Runsheng Wang Institute of Microelectronics, Peking University, Beijing, China
Shuying Wang SiEn (Qingdao) Integrated Circuit Corp, Qingdao University,
Qingdao, China
T. C. Wang SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
xlii Contributors

Wei Wang Peking University, Beijing, China

Institute of Microelectronics, Peking University, Beijing, China
Wenbo Wang SiEn (Qingdao) Integrated Circuit Co., Ltd., Qingdao, China
Xi Wang ACM Research (Shanghai), Inc., Shanghai, China
Xin-An Wang Electronic and Computer Engineering, Peking University,
Shenzhen, China
Yijiao Wang Institute of Microelectronics, Beihang University, Beijing, China
Yong-Wen Wang Institute of Microelectronics, Peking University, Beijing, China
Yuelin Wang Shanghai Institute of Microsystem Information of Technology, Chi-
nese Academy of Sciences, Shanghai, China
Zheyao Wang Institute of Microelectronics, Tsinghua University, Beijing, China
Zongwei Wang Institute of Microelectronics, Peking University, Beijing, China
Shaojun Wei Institute of Microelectronics, Tsinghua University, Beijing, China
Hanming Wu School of Micro-nanoelectronics, Zhejiang University, Hanzhou,
China
Jian Wu National Technology Innovation Strategic Alliance for IC Assembly and
Testing, Wuxi, China
Nanjian Wu Institute of Semiconductors, Chinese Academy of Sciences, Beijing,
China
Yang Xia Institute of Microelectronics, Chinese Academy of Sciences (IME),
Beijing, China
Deyuan Xiao SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
Hanwu Xiao Wuxi ZhongWei High-tech Electronics Co., Ltd., Wuxi, China
Hong Xiao KLA-Tencor, Milpitas, CA, USA
Pengcheng Xiao School of Microelectronics, Fudan University, Shanghai, China
Junyu Xie China Electronics Technology Group Corporation (CETC), Beijing,
China
Bulu Xu Shanghai Silicon Intellectual Property Exchange Centre, Shanghai, China
Jun Xu Institute of Microelectronics, Tsinghua University, Beijing, China
Zhaozhao Xu Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd.,
Shanghai, China
Yuwen Xue Zhongjing Industrial, Xi’an, China
Fang-Lin Yan Shenzhen Yixingbiao Technology Co., Shenzhen, China
Contributors xliii

Jianxin Yan Hangzhou Silan Microelectronics Co., Ltd., Hangzhou, China

Na Yan School of Microelectronics, Fudan University, Shanghai, China
Quan Yan Mentor Graphics, Shanghai, China
Xiaolang Yan Institute of VLSI, Zhejiang University, Hangzhou, China
Yanlun Yan Summitview Capital, Beijing, China
Deren Yang State Key Lab of Silicon Materials, Zhejiang University, Hangzhou,
China
Fan Yang Huada Empyrean Software Co., Ltd., Beijing, China
Feng Yang Raintree Scientific Instrument (Shanghai) Corporation (RSIC), Shang-
hai, China
Jun Yang National ASIC System Engineering Center, Southeast University, Nan-
jing, China
Junqi Yang School of Microelectronics, Fudan University, Shanghai, China
Yuancheng Yang Institute of Microelectronics, Peking University, Beijing, China
Zhenchuan Yang Institute of Microelectronics, Peking University, Beijing, China
Lezhi Ye Department of Material and Manufacture, Beijing University of Technol-
ogy, Beijing, China
Bin Yin Institute of Microelectronics, Chinese Academy of Sciences (IME), Bei-
jing, China
Ming Yin Publishing House of Electronics Industry Co., Ltd., Beijing, China
Shouyi Yin Institute of Microelectronics, Tsinghua University, Beijing, China
Aisheng Yu SAIC(Shanghai Automotive Industry Corporation) Motor R&D Inno-
vation Headquarters, Shanghai, China
Daquan Yu School of Electronic Science and Engineering, Xiamen University,
Xiamen, China
Guoliang Yu TongFu Microelectronics Co., Ltd., Nantong, China
Hongyu Yu Southern University of Science and Technology, Shenzhen, China
Kun Yu Sino IC Technology Co., Ltd., Shanghai, China
Shan Yu China Semiconductor Industry Association, Beijing, China
Wen Yu Electronic and Computer Engineering, Peking University, Shenzhen,
China
Xuegong Yu State Key Lab of Silicon Materials, Zhejiang University, Hangzhou,
China
xliv Contributors

Tong Yuan China Electronics Materials Industry Association, Beijing, China

Suge Yue Beijing Microelectronics Technology Institute, Beijing, China
Janet Zeng SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
Lang Zeng Institute of Microelectronics, Beihang University, Beijing, China
Xiaoyang Zeng School of Microelectronics, Fudan University, Shanghai, China
Cheng Zhang Zhihu Inc., Beijing, China
Guoming Zhang NAURA Technology Group Co., Ltd., Beijing, China
Hwatsing Technology Co. Ltd., Tianjing, China
Haixia Zhang Institute of Microelectronics, Peking University, Beijing, China
Jiayang Zhang Institute of Microelectronics, Peking University, Beijing, China
Kaiwei Zhang Huada Semiconductor Co. Ltd, Beijing, China
Letao Zhang Electronic and Computer Engineering, Peking University, Shenzhen,
China
Qiquan Zhang Harbin Institute of Technology, Shenzhen, China
Shengdong Zhang Electronic and Computer Engineering, Peking University,
Shenzhen, China
Song Zhang China Center for Information Industry Development, Beijing, China
Xiaoyan Zhang ACM Research (Shanghai), Inc., Shanghai, China
Zhiyong Zhang Sino IC Technology Co., Ltd., Shanghai, China
Jinrong Zhao Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA),
Beijing, China
Long Zhao Shanghai Research Institute of Microelectronics, Peking University,
Shanghai, China
Yuanfu Zhao China Academy of Aerospace Electronics Technology, Beijing,
China
Bojing Zheng Hua Capital Investment Management Co., Ltd., Beijing, China
Hongchao Zheng Beijing Microelectronics Technology Institute, Beijing, China
Kai Zheng Semiconductor Manufacturing International Corporation, Beijing,
China
Min-Zheng Zheng Department of Information Technology Industry, Ministry of
Industry and Information Technology, Beijing, China
Shengming Zhou Southern University of Science and Technology, Shenzhen,
China
Contributors xlv

Yumei Zhou Institute of Microelectronics, Chinese Academy of Science, Beijing,

China
Yunyan Zhou Institute of Microelectronics, Chinese Academy of Sciences, Bei-
jing, China
Zixue Zhou China Federation of Electronics and Information Industry, Beijing,
China
Linghua Zhu Wuxi Zhongwei High-tech Electronics Co., Ltd., Wuxi, China
Min Zhu Shanghai HLMC Co., Ltd., Shanghai, China
Yieji Zhu Huaqiang Electronic Industry Research Institute, Shenzhen, China
Zhuliang Zuo China Electronics Technology Group Corporation (CETC), Beijing,
China
Spring Blossoms and Autumn Fruits: History of
Compiling The Handbook of Integrated Circuit
Industry

Introduction

The motion to compile The Handbook of Integrated Circuit Industry sprang at the
end of 1991. At that time, Professor Yangyuan Wang of Peking University served as
part-time Deputy Director of the Division of Microelectronics and Basic Products of
the then Ministry of Mechanical and Electronic Industry. Minzheng Zheng, Xiaotian
Xu, Xian Chen, and Yongwen Wang also worked there. As managers in industry,
they often encountered macro-problems such as industrial development strategy,
market analysis, industrial economy, and industrial management, and micro-
problems such as product application, product design, product technology, and
materials and equipment. To solve these problems, they had to consult references
or experts. However, books on integrated circuits published at the time were mostly
technical works or academic monographs, such as Semiconductor Physics (Kun
Huang, Xide Xie), Design Principles of Integrated Circuits: Bipolar Logical Inte-
grated Circuits (Pushan Tang as Editor-in-Chief), Computer Aided Plate Making
Software System for Large Scale Integrated Circuits (edited by Xianlong Hong,
et al.), Polycrystalline Silicon Film and Its Application in Integrated Circuits (edited
by Yangyuan Wang and T. I. Cummings), and Integrated Circuit Technology
Foundation (edited by Yangyuan Wang, Xudong Guan, and Junru Ma). Books
about packaging, testing, and special equipment and materials on the industrial
chains of the integrated circuit were rare. Most of the staff who had direct contact
with industrial management came from a background of science and engineering
without systematic knowledge about economy and management. It was also difficult
to find monographs on economics and management of the IC industry which they
could consult. For this reason, Xian Chen and Yongwen Wang, among others, came
up with the idea of compiling a monograph.
This monograph should first be “complete.” At the macro level, it should include
contents such as the direction of the development, strategic initiatives, market data,
historical evolution, forecast, and outlook. At the technical level, it should cover the
entire chain of the IC industry, including classification, application, design, pro-
cessing, packaging, testing, equipment, material, and plant construction of the IC
products. Second, this book should be like a dictionary, or a desk reference that could
be used at any time by managers, technicians, and teachers in the IC field. This

xlvii
xlviii Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . .

motion was immediately seconded by Director Dasheng Li of the Division of

Microelectronics and Basic Products and likewise won the support of other directors.
Vice-Director Yangyuan Wang was unanimously elected Editor-in-Chief of the
book, and the subtitle was designated “Technology, Economy, and Management.”
In 1991, conditions for writing books were very tough. There was no computer
with text editing software, no network, no mobile phone. Even the telephone was
mostly a wheeled dial extension; calls to the outside had to be transferred through a
switchboard. Texts had to be written by hand with a fountain pen on a 400-word
sheet of paper. Charts had to be drawn by hand with a duck-billed pen dipped in
drawing ink. References had to be consulted by the author in person in the library.
All paper manuscripts had to be sent by post. As conditions were inadequate for
convening a professional meeting of exchange, all information exchange had to be
done using letters with 8-cent stamps stuck to them and put into green mailboxes,
which took about a week to go back and forth in China. Peony Garden Hotel, located
in Beijing’s North Taipingzhuang area, was the destination where all the
manuscripts went.
In 1992, 114 authors and 2 editors from the Electronic Industry Publishing House
joined in the busy work of writing and editing. In April 1993, the 9.67-million-word
The Handbook of Integrated Circuit Industry was officially published (see Fig. 1).
Today, Shouwu Wang, Lanying Lin, Shoujue Wang, Zhijian Li, Chunguang Liang,
Dasheng Li, Weiqin Zheng, Xiaoyu Zhang, Huiquan Zhang, Jiasheng Xu, Tongzeng

Fig. 1 The 1993 edition of The Handbook of Integrated Circuit Industry

Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . . xlix

Zhuang, Lanfang Gong, and Xian Chen have left us, but their contribution to the
development of China’s IC industry will never be forgotten.

A Long-Cherished Wish

In April 1993, the State Council undertook institutional restructuring. The Ministry
of Mechanical and Electronic Industry was dissolved and the Ministry of Machinery
Industry and the Ministry of Electronic Industry were established instead. After the
restructuring, Yangyuan Wang returned to Peking University to continue his teach-
ing and research, but his enthusiasm for advancing the IC industry never slackened.
He provided suggestions for Projects 908 and 909 and published dozens of articles in
various media on strategic research and industrial construction of integrated circuits,
expressing his wish to “pursue the dream of China’s IC industry on the fast track.” In
2000, together with colleagues home and abroad, he founded Semiconductor
Manufacturing International Corporation Co., Ltd. (SMIC) and served as Chair
from 2000 to 2009. The establishment of SMIC has significantly narrowed the gap
between China’s manufacturing technology of the integrated circuits and the
advanced international level and has become a milestone in the construction of
China’s IC industry. Since 2008, Wang and his collaborators have co-authored
monographs such as The Road to the Development of Integrated Circuit Industry
in China, Green Micronanoelectronics, and Strategy: The Foundation of Survival
and Development. Yet, one wish had remained long-cherished and unfulfilled in his
heart, which was to re-compile The Handbook of Integrated Circuit Industry.
This was because, since 1993, the global IC industry has undergone tremendous
changes. New technologies and devices popped up one after another such as deep
ultraviolet lithography, copper interconnection, FinFET, high k gate dielectrics,
immersion lithography, multi-gate transistors, and 3D packaging. Generation after
generation of new IC products have opened up new application markets. Digital
cameras, notebook computers, tablets, mobile phones, the Internet, wearable devices,
and endless applications are transforming people’s lifestyles and ways of production
with each passing day. Since 2000, the Chinese government has promulgated the
Notice of the State Council on Issuing Policies to Encourage the Development of
Software Industry and Integrated Circuit Industry (State Council No. 18, [2000]) and
the Notice of the State Council on Issuing Policies to Further Encourage the Devel-
opment of Software Industry and Integrated Circuit Industry (State Council
No. 4 [2011]). It has also launched the National Promotion Program of the Integrated
Circuit Industry in an attempt to put forward important measures to accelerate China’s
IC industry. Obviously, the 1993 edition of The Handbook of Integrated Circuit
Industry has not been able to meet the new needs of practitioners, investors, industrial
planners, market pioneers, and users. It is imperative to compile a new edition.
On August 31, 2015, Academician Yangyuan Wang, the leading figure allying
production, teaching, and research, proposed to the MIIT to compile A Series of
Books on the Integrated Circuits and The Handbook of Integrated Circuit Industry.
His proposal had the full backing from Academician Jinpeng Huai, then head of the
l Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . .

National Advisory Committee, and many other experts in the industry. Huai
believed, “This will be a very beneficial pursuit. It showcases our scientists’ intel-
lectual aspirations and will be a major event in developing our country’s IC industry.
I recommend strong support for it!”

Flowering in Spring

February 26, 2016. While it was cold early spring in Beijing, it was already warm in
Shenzhen. The greenery in Southern University of Science and Technology was
exuding vigor and vitality, and the limpid lake was sending out ripples from its
center. In the conference room was Yangyuan Wang presiding over the preparatory
meeting of the Editorial Committee of the Series of Books on the Integrated Circuits
and The Handbook of Integrated Circuit Industry. The meeting drew up the prelim-
inary list of the Editorial Committee, established the basic structure of the Hand-
book, adopted the tentative design of its chapters, and formulated the working plan
for the compilation. A seed waiting for germination had been quietly sown in the
fertile soil of reform and opening up.
April 6, 2016, the last month of spring in Beijing. The pink peach blossoms were
in flower, the willows had turned a light yellow, the grass had become green, the
water was lucid, and the new buds were shooting forth. The preparatory committee
issued a “Letter of Inquiry” to 101 experts from the IC industry in China. The
majority of them responded positively, agreeing to serve on the Editorial Committee
and expressed their full support for the compilation.
May 7, 2016. As flowers came in a riot of colors, showing off the charming roses,
graceful cloves, and bright peonies, China’s IC industry had also ushered in a
blossoming spring. Senior scientists in their 70s and 80s, middle-aged scientists in
the prime of life and career, elite returnees from abroad who were working hard in
the production line, and enthusiastic youths who were venturing into the industry all
gathered in Beijing’s Wanshou Hotel for the compiling of the Handbook. The
Editorial Committee was thus formally established on this day. Nearly 100 people
attended the meeting, including officials from the Division of Electronic Informa-
tion, MIIT, and the China Semiconductor Industry Association, as well as scholars,
experts, and executives from universities, research institutes, enterprises, and pub-
lishing houses.
Academician Yangyuan Wang chaired the meeting.
Representative of the Division of Electronic Information, MIIT, congratulated the
establishment of the Editorial Committee and made suggestions on its work.
To enhance the sense of honor and responsibility of the members of the Editorial
Committees, letters of appointment to the Editor-in-Chief and Deputy Chief Editors
of the Handbook as well as other members of the Editorial Committee attending the
meeting were issued.
Academician Yangyuan Wang made a keynote speech, elaborating on the fol-
lowing four aspects:
Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . . li

1. The significance of compiling the Series and the Handbook

2. The method of selecting members of the Editorial Committee and the working
methods of the Editorial Committee
3. Issues related to funds and intellectual property rights
4. Expected achievements of the Committee by the end of 2020, during the 13th
Five-Year Plan period

Detailed plans for the compilation including chapter design, book length, and
rules for writing the entries were then discussed, a timetable was worked out, and
chief editors for each chapter were appointed.

Sharpening Up

With the dream of building a powerful IC industry in China which we took to be the
mission entrusted to our generation, the chief editors of the chapters began to organize
their teams and embarked on the writing of more than a thousand entries and a million
words. After 9 months of hard work, 468 writers finished the first draft. It was as if they
had excavated a huge rock from the mountain of knowledge. Whether it contained
precious jade inside or it was just common stone still needed to be tested by practice.
From February 19 to 24, 2017, 1 year after the preparatory meeting of the
Editorial Committee, the first review meeting of the Handbook was held in Qilin
Mountain Villa, Shenzhen.
Yangyuan Wang emphasized four basic principles of review at the meeting.

1. Correct and scientific. The content must be correct and scientific, or it will
mislead young people. Words written down can last longer than life. It must be
able to stand the test of history and withstand the challenge of tens of thousands or
even hundreds of thousands of readers.
2. Independent and innovative. To ensure that every entry is written independently,
we must stop plagiarism and must not allow any of it to be incorporated into the
Handbook. When citing other people’s work, we must make sure to indicate the
source in the reference. The intellectual property rights involved will be obtained
by uniform payment.
3. Rational and systematic. Is the distribution of content between each chapter
reasonable? Is there repetition? Is the Handbook systematically organized? Qual-
ity, not quantity, is our priority. Do not rush. High quality is the first criterion we
must follow and the first goal we must pursue.
4. Comprehensive and forward-looking in vision. Does the content cover all aspects
of the IC industry and the related science and technology both home and abroad?
We must ensure forwardness in our vision so as to make our Handbook more
useful, or it is likely to fall behind the times and lose practical value.

Members of the Editorial Committee present at the meeting read and commented
on the draft submitted by the executive editors of each chapter verbatim with great
lii Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . .

prudence. The conclusion was that “achievements are great, problems are many, and
prospects are bright.” The achievements referred to the 1200 entries with 1.6 million
words; the problems meant various degrees of academic misconduct spreading
across entries; the prospects were that there was indeed jade inside and that it
could eventually be sculpted into the “most lustrous gem” of the industry.
Compared with the writing method of the 1993 edition, we now have the software
for editing words and graphs available at any time and the Internet for accessing
information available at any time. Only the Internet is both a double-edged sword
and a key. Used properly, it opens the treasure house of culture and brings us a wealth
of knowledge; used improperly, it may enact Pandora’s Box, leading to the disaster
of intellectual property infringement.
Intellectual property rights are the exclusive rights of mankind over their intel-
lectual creation in social practice. The World Intellectual Property Organization was
established in 1967, and China became a full member in 1980. The Copyright Law
of the People’s Republic of China was adopted at the Fifteenth Meeting of the
Standing Committee of the Seventh National People’s Congress on September
7, 1990. In 2012, the State Copyright Administration published the Third Amend-
ment to the Copyright Law, which intended to raise the maximum compensation
standard for copyright infringement from 500,000 yuan to 1,000,000 yuan.
How to avoid infringement of intellectual property rights became the top priority
of the first review meeting in Shenzhen. The solution lies in personal integrity
(honesty and self-discipline) and legal restraint (the rule of law). Respect for others’
knowledge is the bottom line, the insurmountable red line, which all students and
scholars should observe. It is absolutely forbidden to patch up one’s own writing by
means of “copy and paste,” or to quote others’ work without proper citation, or to use
others’ diagrams and data without authorization. To this end, Yangyuan Wang
requested that the Secretariat of the Editorial Committee perform duplicate checking
to find out whether the drafts provided by the contributors were identical or very
similar to published documents. Wang expressed serious concern over the unsatis-
factory results obtained by using the PaperPass Chinese Document Similarity
Contrast System on the first draft. Blemishes must be mended; defects must be
eradicated. Passing muster in duplicate checking became the top concern after the
Shenzhen meeting. It was also like the first knife to sculpt the rock into jade, or the
sword of Damocles which served to warn us to be always on guard against intellec-
tual property infringements.

Forging Ahead

Duplicate checking demonstrated our reverence for knowledge and respect for
others. Its purpose was to eliminate dishonesty and impetuosity. After more than
2 months of revision and adjustment, the second review meeting was held on May
7, 2017, in SMIC, Shanghai (see Fig. 2), exactly 1 year from the establishment of the
Editorial Committee. Among the objects of the review were to make sure that the
entries were written authoritatively and accurately with professionalism and sophis-
tication; that the English and traditional Chinese words were correct; and that the
Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . . liii

Fig. 2 Participants of the second review meeting held in Shanghai who worked on Chap. 2 of the
Handbook

vocabulary, sentences, and references were standardized. At the same time, another
round of duplicate checking was conducted on each revised chapter.
This meeting was one of high intensity, quality, and efficiency. During the 15 days
from May 7 to 21, 2017, Chaps. 2, 4, 6, 7, 8, and 9 were reviewed, and 774 entries
totaling 1352 pages were printed and bound into a “mock” book.
From May 25 to 31, 2017, the reviewers went north to hold another review
session in Beijing. Chapters 1, 5, and 10 were reviewed. A total of 622 pages
covering 293 entries were printed and bound into another “mock” book.
These two meetings in Shanghai and Beijing reviewed 1974 pages of all the
9 chapters and 1037 entries of the Handbook. Counted by 1600 words per page
(including charts), this second review examined a total of about 3,160,000 words,
with an average of 160,000 words per day.
In view of the fact that Professor Zixue Zhou was chief editor of Chap. 3, the
review of Chap. 3 was postponed to June 25 to 30, 2017.
After nearly 3 months of careful revision, the results of the second duplicate
checking showed that the probability of the drafts being the same or similar to other
documents had been greatly reduced, and disputes over intellectual property had
been greatly curbed.
PaperPass can do a wide range of searches, including all media documents such
as books, magazines, and materials from the Internet. However, as a software
application, it cannot judge whether duplication is plagiarism and may produce
misjudgment on contents such as

1. Referenced literature or data

2. Descriptions of definitions, theorems, and laws
3. Publicly available laws, regulations, data, official documents issued by the state,
and excerpts of leadership speeches
liv Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . .

4. Proper nouns (including names of persons, places, things, books, etc.)

5. General descriptions that do not involve intellectual property rights

After manual clearing of the above contents, the repetition rate of all the reviewed
drafts was reduced to the lowest, with 0 rate for most of the chapters and less than 1%
for the rest. A total of 25,969 yuan was paid for the duplicate checking.
When the problem of duplication was solved, the payment of references, data, and
charts was put on the agenda. These were the second and third “barriers” that we
could not bypass and must cross. In other words, we should not only specify the
sources of all the referenced documents, charts, and data in detail but should also pay
to obtain authorized permission from copyright holders, including publishers,
authors, and statistical organizations, in order to ensure that our Handbook did not
have any flaws in intellectual property.
After nearly 2 months of careful work, the Editorial Committee thought it was
time for the final review of all the drafts and decided to hold this meeting in China
Workers’ Home in Beijing from July14 to 27, 2017
The aim of this gathering was to carry out the final review of all the chapters,
appendices, vocabulary index, English-Chinese index, and the binding design of the
Handbook. More than 70 people attended the meeting, including the Editor-in-Chief;
Deputy Chief Editors; members of the Secretariat of the Handbook; chief, deputy
chief, and executive editors of each chapter; as well as leaders and editors from the
Electronic Industry Publishing House.
At this final review meeting, Editor-in-Chief of the Handbook Yangyuan Wang
delivered a keynote report entitled “Topless is the mount of learning, but we scale it
by the path of diligence; boundless is the sea of knowledge, but we sail it by the boat
of assiduity.” He thanked all the 134 editorial members, 468 contributors, and
125 reviewers for their hard work in writing and reviewing the 1052 entries totaling
2.4 million words. He also thanked the Deputy Chief Editors and the Secretarial team
for their unity, cooperation, perseverance, and conscientiousness in compiling the
Handbook.
Wang said that the Handbook would first be published in simplified Chinese, and
then in English in cooperation with well-known publishing institutions abroad. That
would engage more overseas contributors in the writing of the English version. In
addition, he would consider issuing a traditional Chinese edition, according to the
market demand.
SMIC’s Chairman Zixue Zhou, former CEO of SMIC, Rujing Zhang, and Jiuru
Liu, Chief Editor of the Electronic Industry Publishing House, made enthusiastic
speeches. They believed that integrated circuits would surely take root and grow in
China. It was of great significance to make this Handbook, which we could proudly
present to future generations as a work representing the highest academic standard of
the country in our time. Not only could it pay tribute to the present age, but it would
benefit posterity for many years to come. This masterpiece would undoubtedly
become a fine addition to the national library.
In July 2017, an application was submitted by the Electronic Industry Publishing
House for the Series of Books on Integrated Circuits to the Planning and Manage-
ment Office of the National Publishing Fund. On February 8, 2018, the Office
Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . . lv

officially approved the application and announced the grant of the National Pub-
lishing Fund for the Series. The National Publishing Fund is the most influential
national cultural fund in the publishing industry, and the third largest national fund
after the National Natural Science Fund and the National Social Science Fund. As
the first volume of the Series, The Handbook of Integrated Circuit Industry adopted
the logo of the National Publishing Fund on its cover.

Fruits in Autumn

August 7, 2017, was the day that marked the beginning of autumn according to the
Chinese lunar calendar. Bidding farewell to the hot summer, Beijing was now
ushering in the golden autumn with cool breezes and a clear sky. The compiling of
the Handbook was also nearing its end, just as the ears of rice in the harvest time are
drooping and the branches are full of fruits.
The Editorial Committee decided to accept Chaps. 1, 4, 5, 6, 7, 9, and 10 from
August 24 to 29, 2017, and Chaps. 2, 3, and 8 from September 21 to 28.
September 29, 2017, saw the plenary meeting attended by the Editor-in-Chief and
Deputy Chief Editors of the Handbook, as well as chief, deputy chief, and executive
editors of each chapter. The meeting was briefed on duplicate checking and copy-
right licensing for citing documents, graphs, and data. For 110 graphs and docu-
ments that should be authorized, authorization had been obtained after contacting the
relevant parties such as IEEE and the individual authors. The total fee paid was
$3700.64. For data referencing, WSTS indicated that Historic Billing Reports and
other content published on its official website could be used; IC Insights indicated
that public data were available, and private data could be purchased from its
McClean Report; SEMI indicated that the content it had audited could be quoted;
Gartner indicated that the content of its official website could be quoted but should
be quoted strictly according to its required format; Semicast Research and Yole
allowed quoting content from its official website; CCID Consulting and China
Semiconductor Industry Association said their statistics could be cited. As a result,
103 items of domestic and foreign market data were authorized, of which 32 were
from IC Insights, with a payment of 50,954.41 yuan. The fees for checking dupli-
cates and purchasing intellectual property rights of documents, charts, and data
totaled 101,347.6 yuan, all of which was funded by the Institute of Microelectronics,
Peking University. The costs of all the meetings were funded by Southern University
of Science and Technology, Shenzhen Guowei Electronics Co., Ltd., SMIC (Shang-
hai) Co., Ltd., Huada Semiconductor Co., Ltd., National Integrated Circuit Industry
Investment Fund Co., Ltd., and Beijing Huada Jiutian Software Co., Ltd. To them
the Editorial Committee hereby expresses its appreciation.
After a series of adjustment, such as verifying content, unifying writing standards,
degrading duplicate checking, and obtaining authorization, the rock collected from
the peak of knowledge had its skin peeled off, cracks avoided, defects eliminated,
and scratches smoothed to become admirable jade. With the polishing and decorat-
ing done by the Electronic Industry Publishing House, it was now ready to be
presented to readers home and abroad.
lvi Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . .

At the acceptance meeting, Editor-in-chief Yangyuan Wang commented on the

project like this, “Integrated circuits are the Midas touch of the industry, capable of
turning stone into gold. The writing of this Handbook is a process of ‘sweeping and
sifting the sand until gold peeps through the blown dust’. It is about keeping the
valuable and discarding the valueless, or disentangling truth from falsehood. There is
no shortcut on the road to science, and no room for falsehood in the pursuit of science.
Honesty and credit are the basis of building this Handbook; they are the yardstick that
can stand the test of time and the scrutiny of the reader. The Handbook also adheres to
three directives, namely, ‘paying tribute to old generations of predecessors, displaying
worthiness to the current generation, and inspiring future generations.’ While record-
ing the arduous course of the predecessors’ hard work, it also reveals the overall
evolution of the macro-economy and technological advancement, as well as the
philosophy and thinking embedded in scientific development.”
If life is a journey, then books are the footprints human travelers leave in the
world. They convey ideas, spread information, store wisdom, and interpret culture.
While we integrate experience and knowledge into our lives like a river that never
ceases to flow, books continue as if our life forever.
Writing a book is like a test of the soul through which one gets purified. It is also a
process of constant absorbing and producing knowledge. The Handbook of Inte-
grated Circuit Industry records how the present generation carries forward past
traditions and blazes a trail for posterity. It is an important part of the cultural
construction of the integrated circuit and a valuable asset we offer future generations.
Kilby invented the integrated circuit back in 1958. Sixty years later, in 2018, The
Handbook of Integrated Circuit Industry is exuding life in the field of the IC
industry. Here, with a poem let us congratulate its publication as well as the 60th
anniversary of the invention of the integrated circuit.

Ode to the Publication of The Handbook of Integrated Circuit Industry

The bell, the drum, the beacon fire,

Also the stage post and the flying pigeon,
And the fish and the wild goose
Spring Blossoms and Autumn Fruits: History of Compiling The Handbook. . . lvii

For carrying the letters of love,

They were how messages were passed in the past.
Indeed, I marvel at the romances of the gods,
For the fantasies and phantoms they weave.
But sages of today offer their wisdom,
And make a wonderful idea come true.
Like gold extracted from sand, wisdom is condensed in a tiny chip.
Family and friends gather together in front of the screen,
Spanning both ends of the world,
And living lives past and present
All at the snap of a finger.

Pen and ink make words that last among men.

Now that I think of these past three years,
What a rough and rugged journey we have made!
Talents gathered from around the country.
Tilling and plowing, they created a classic,
In a volume of ten chapters.
Out of debates and discussions,
Emerged this history of 60 years,
And a guide of the industry, spread far and wide,
East and west, north and south,
A masterpiece of sweat and blood it is for sure.
Why is my heart attached to it so?
For the same spirit runs right through
Age and youth.

Editorial Committee of The Handbook of Integrated Circuit Industry

June 2018
 Section I
Technology and Industry Development of
Integrated Circuit
Min-Zheng Zheng, Yong-wen Wang, and Ke Li

Introduction

As one of the greatest inventions of the twentieth century, integrated circuit tech-
nology opened a new era in the history of electronic development. Since its inven-
tion, integrated circuits have undergone 60 years of development. Through
technology research and development, product innovation, and industrial change,
integrated circuit plays a leading role in the development of the electronic informa-
tion industry and the entire scientific and technological community. This section,
stands at the beginning of the book, sorts out the development history of global
integrated circuit technology and industry, focuses on reviewing the development
history of China’s integrated circuit industry, and reviews relevant policies, core
links, key institutions, and important events. Information security, intellectual prop-
erty rights, international cooperation, business management, and personnel training
have been comprehensively analyzed.
This chapter is written to help readers understand the development history and
current status of integrated circuit technology and industry.
In the process of writing this chapter, we have received the support and help of
China Semiconductor Industry Association, Northern Microelectronics Equipment
Company, and industry colleagues, and we would like to express our gratitude. In
addition, we have done our best to clearly describe all related subjects in this chapter.
Any updated information will be provided in future.
Invention and Technological Progresses
of Integrated Circuits 1
Yong-Wen Wang and Min-Zheng Zheng

Contents
Integrated Circuit (IC) and IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Technology Preparation Before the Invention of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Invention and Applications of Electron Tubes and Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Invention of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Milestones of Information Acquisition, Storage, and Processing in IC Industry . . . . . . . . . . . . . . . 11
Milestones of Development in IC Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Milestones in IC Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
From Industry Age to Information Age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Market Demand and Driving Force of Information Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Abstract
Integrated circuits (ICs) refer to circuits that can be fabricated on single crystalline
substrates to perform specific functions of logic, analog, memory, RF, and power.
IC technology and industry have been progressed for 60 years. IC applications
have gradually expanded from the initial military field to all aspects (e.g.,
industrial, agricultural, transportation, government, finance, security, communi-
cations, education, media, and entertainment). The first-generation semiconduc-
tor materials are mainly germanium (Ge) and silicon (Si). The second-generation
semiconductor materials are mainly gallium arsenide (GaAs), indium phosphide
(InP), indium antimonide (InSb), and cadmium sulfide (CdS). The third-
generation semiconductor materials typically have a wide forbidden bandwidth

Y.-W. Wang (*)

Institute of Microelectronics, Peking University, Beijing, China
e-mail: wangyw@pku.edu.cn
M.-Z. Zheng
Department of Information Technology Industry, Ministry of Industry and Information Technology,
Beijing, China

© Publishing House of Electronics Industry 2024 3

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_1
4 Y.-W. Wang and M.-Z. Zheng

(greater than 2.2 eV), such as silicon carbide (SiC), gallium nitride (GaN), zinc
oxide (ZnO), and aluminum nitride (AlN). The manufacturing of ICs in a broad
sense mainly includes design, fabrication, and packaging (with testing).

Keywords
Integrated circuits (ICs) · Logic · Analog · Memory · RF · Germanium (Ge) ·
Silicon (Si) · Manufacture · Packaging

Integrated Circuit (IC) and IC Industry

Integrated circuits (ICs) refer to circuits fabricated on single crystal substrates that
can perform specific functions of logic, analog, memory, RF, and power. The circuits
or systems can integrate active devices (e.g., transistors, diodes, etc.) as well as
passive components (e.g., resistors, capacitors, inductors, antennas, etc.) together on
semiconductor wafers, such as silicon (Si) or gallium arsenide (GaAs). Jack S. Kilby
(Texas Instruments) and Robert N. Noyce (Fairchild Co.) invented IC technology in
1958 and 1959, respectively. By 2019, IC technology and industry have been
progressed for 60 years.
Since the invention of ICs, there was active development in 1960s and 1970s, and
IC industry was in impressive progresses. In 1965, Fairchild’s Gordon E. Moore
published a prediction on the development of ICs in the Journal of Electronics. He
believed that the complexity of ICs would double every year at the lowest compo-
nent cost; this was the original “Moore’s Law.” In 1975, Moore revised the trend to
“double the IC complexity every 2 years.” So far, the change in the number of
transistors on the CPU is consistent with Moore’s prediction; and the number of
transistors in memory ICs doubled approximately every 18 months.
The initial manufacturers of ICs are basically “self-produced and self-sold”
system manufacturers. This kind of IC manufacturer that designs by itself, processes
with its own production line, packages, tests, and sells its own IC chips is called IDM
(Integrated Device Manufacturer). With the evolution of IC technology into the
1980s, several different independent enterprises have emerged with dedicated
focuses on IC packaging, design, or manufacturing, respectively. They formed
industry structures consisting of enterprises dedicated on IC packaging and testing,
IC design houses (or fabless production lines), professional chip manufacturing lines
(IC Foundry), and intellectual property houses (IP vendor) without actual designing
ICs. The IC industry also includes electronic design automation (EDA) tool vendors,
IC materials manufacturers and IC equipment vendors, as well as personnel training,
industrial investment, intermediate technical services.
The line width of earlier IC manufacturing was in the range of 10 μm. Along with the
emergence of new technologies (e.g., copper (Cu) interconnection, DUV immersion
lithography, and 3D packaging) the line width for IC manufacturing in 2023 has reached
3 nm technology node. The diameter of Si wafers has grown from the original 1 in.
(or 100 , 25.4 mm) to the present 300 mm (about 1200 ). In the early stage, the diameter
1 Invention and Technological Progresses of Integrated Circuits 5

(or size) of the Si wafer was in units of an inch (e.g., 300 , 400 or 500 ) and later changed to
units of millimeters (mm) when the diameter of Si wafer reached 150 mm. In the general
public, the silicon wafer with a diameter of 150 mm is commonly known as a 6 in.
silicon wafer in the domestic industry. The diameter of 200 mm silicon wafer is
commonly known as the 8 in. silicon wafer, and a silicon wafer with a diameter of
300 mm is commonly known as a 12 in. silicon wafer.
The IC technology, as born in 1958, opened the door for human society advanc-
ing toward an information society. IC applications have gradually expanded from the
initial military field to all aspects (e.g., industrial, agricultural, transportation, gov-
ernment, finance, security, communications, education, media, entertainment, etc.).
The science, technology, and industry of IC not only become the driving force to
accelerate the sustained economic growth and change the way of human production
and lifestyle, but also become an important factor related to the outcome of modern
war. The scale, level of science and technology, as well as innovation ability of IC
industry are becoming important symbols to measure the comprehensive national
strength of a powerful country. Integrated circuit technology has created a new
information world for human beings and has made indelible historical contributions
in the development of human society. Furthermore, in the information society,
integrated circuit has become the tripod of the strong country, the treasure of the
rich country, the tool of the national renewal, and the foundation of the national
stability.

Technology Preparation Before the Invention of ICs

Human understanding of electricity comes from the triboelectrification. Wang

Chong of the Eastern Han Dynasty discussed the phenomenon of “Dunmu Tuzhu
(顿牟掇芥)” in his book Lun Heng - Disorderly Dragon (论衡•乱龙). Dunmu,
namely, means amber, and Tuzhu, namely, to attract small and light things. However,
the amount of charge generated by the triboelectric effect is small and unsustainable.

1745: Professor Pieter van Musschenbroek of Leiden University in Leiden city, the
Netherlands, invented the container “Leiden bottle” that can store charges.
However, the charge in the Leiden bottle still cannot store enough electricity,
and the flow of charge cannot be controlled.
1752: Benjamin Franklin, an American scientist, carried out his famous experiment
of “kite electrification” and came up with terms such as “electric current,”
“positive charges,” and “negative charges.”
1799: Alessandro Volta, an Italian physicist, succeeded in making the world’s first
battery, a “voltaic pile.” Since then, human society has an artificially made and
controllable “power source.”
1820: Hans C. Oersted, a Danish physicist, discovered the magnetic effect of electric
current.
1826: Georg S. Ohm, a German physicist, published the famous Ohm’s law.
6 Y.-W. Wang and M.-Z. Zheng

1827: André M. Ampère, a French physicist, published the book of Mathematical

Theory of Electrokinetic Phenomenon and invented the electric current meter.
1831: Michael Faraday, a British physicist, discovered the phenomenon of electro-
magnetic induction, so that the human mastered methods of the mutual transfor-
mation between electromagnetic fields and motion as well as the mutual
transformation method between mechanical energy and electrical energy.
1864: James C. Maxwell, a British physicist, published a paper of “The Dynamics
Theory of Electromagnetic Fields.”
1865: The British physicist Maxwell predicted the existence of electromagnetic
waves and proved that the speed of electromagnetic waves in a vacuum is equal
to the speed of light, which became the basis of modern radio technology.
1866: Werner Siemens in Germany invented the self-excited DC generator.
1888: Nikola Tesla, a Serbian-American, invented the AC multiphase power trans-
mission system, which significantly promoted the process the second industrial
revolution and made human society rapidly enter the age of electricity. In the
same year, the German physicist Heinrich R. Hertz confirmed the existence of
electromagnetic waves predicted by Maxwell with experiments.
1897: Joseph J. Thomson, a British physicist, discovered the direct evidence for the
existence of electrons from experiments. The discovery of electrons revealed the
nature of electricity.
1900: Max K. E. L. Planck, a German physicist, put forward the hypothesis that the
radiation energy of matter is discontinuous, introduced the concept of energy
Quantum, and established the Quantum theory.
1913: Niels H. D. Bohr, a Danish physicist, proposed a new model of quantized
atoms.
1926: Erwin Schrödinger, an Austrian physicist, systematically expounded the
theory of wave mechanics and proposed the Schrödinger eq.
1928: Max K. E. L. Planck, the founder of quantum theory, put forward the basic
idea of solid “Energy Band Theory.” The theory elaborated that under the action
of an external electric field, the electric conduction of semiconductor is performed
by two kinds of carriers: the holes in the valence band and the electrons in the
conduction band. The conduction process in which “holes” participate is called
p-type conduction, and the conduction process in which electrons participate is
called n-type conduction (the basic operation principle of bipolar and MOS
integrated circuits). The energy band theory scientifically stated for the first
time that solids can be divided into conductors, semiconductors, and insulators
according to their electrical conductivity.
1930: Paul A. Maurice Dirac, a British physicist, wrote the book Principles of
Quantum Mechanics, to put forward the famous Dirac equation, and theoretically
predict the existence of positron and magnetic monopole.
1931: Alan H. Wilson, a British physicist, proposed the physical model of semicon-
ductor on the basis of energy band theory and explained the mechanism of
“impurity conduction” and “intrinsic conduction.” All the varying properties
and wide application value of semiconductors are determined by the conduction
1 Invention and Technological Progresses of Integrated Circuits 7

mechanism of impurities. The Wilson model laid the theoretical foundation of

semiconductor physics.
1939: Germany’s W. H. Schottky, Britain’s N. F. Mott, and the Soviet Union’s
Davydov (Б вавыдов) almost simultaneously applied the concept of “Potential
Energy Barrier” of metal-semiconductor contact to establish the “diffusion the-
ory” that explained the rectification of metal-semiconductor contact. Thus, these
three interrelated and gradually developed semiconductor theoretical models,
namely, energy band theory, mechanism of semiconductor conduction, and
diffusion theory, constituted the theoretical basis for establishing the technolog-
ical invention of the transistor. At this point, scientists had made theoretical and
practical preparations ready for the invention of transistors.

Invention and Applications of Electron Tubes and Transistors

At first, the key components of electronic equipment were the electron tubes, which
controlled the movement of electrons in a vacuum.

1879: Thomas A. Edison, an American inventor, lit up the first practical light bulb.
On January 27, 1880, Edison filed a patent for the invention of the electric
light bulb.
1904: J. A. Fleming, a British inventor, based on the “Edison effect” to add a metal
plate (anode) into the “light bulb” with only a filament, then invented a vacuum
diode and obtained a patent. After that, vacuum diodes have been used for
detection and rectification in radio technology.
1907: De F. Lee, an American inventor, created the first electronic vacuum triode by
adding a grid to the diode. The triode combined the “magnification,” “detection,”
and “oscillation” functions in one. This makes it a core component of radio
transmitters and receivers.
1918: The United States produced more than one million electronic tubes in a year.
This amount is more than 50 times that before the First World War (1914–1918).
By the mid-1950s, home radios were all made with electronic tubes.
1946: The University of Pennsylvania developed the world’s first Electronic Numer-
ical Integrator and Computer (ENIAC). John von Neumann was a member of the
R&D team. ENIAC utilized 17,468 electronic tubes, consumed electric power of
150 kW, weighted 30 t, and occupied an area of approximately 170 m2. It
performed 5000 addition operations or 400 multiplication operations per second.
The calculation speed was 1000 times faster than that of the relay computer and
200,000 times that of the manual calculation. The main disadvantages of the
electronic tube were that it took time to heat the filament with a prolonged start-up
process. At the same time, the heat generated by the filament must be discharged
from time to time, and the filament life was short. For example, it was possible to
burn a tube almost every 15 min and causing the entire computer to stop running.
It took more than 15 min to find the damaged one in 17,468 tubes. Therefore,
8 Y.-W. Wang and M.-Z. Zheng

Fig. 1.1 Transistor inventors. (From left: Bardeen, Shockley, Brattain)

ENIAC’s average trouble-free working time was only 7 min. For these reasons,
there is an urgent desire to replace the electron tube with a device that does not
require a preheated filament, and which consumes less power and can control the
movement of electrons in the solid.
1946: Bell Labs founded a solid physics research group consisting of William
B. Shockley, John Bardeen, and Walter H. Brattain (Fig. 1.1). On December
16, 1947, Brattain and Bardeen had successfully experimented a point-contact
germanium (Ge) transistor, which was the world’s first transistor, as shown in
Fig. 1.2. The preliminary test results showed that the device had a voltage gain of
100 and an upper frequency up to 10,000 Hz. Brattain thought of its resistance-
transformation characteristics, that is, it worked by transferring current from
“low-resistance input” to “high-resistance output,” so it was named as “Trans-
resistor,” and later shortened it to “Transistor.”
1948: Shockley proposed the theory of the pn junction transistor, and in 1950,
together with Morgan Sparks and Gordon K. Teal, successfully developed the
germanium npn triode (as Ge-npn transistor). The invention of the transistor
pioneered the subject of microelectronics. Compared with the electronic tube,
the transistor has the advantages of long lifespan, less power consumption, small
size, no preheating, impact resistance, and vibration resistance, so it soon gets the
favor of the market.
1953: Hearing aids were introduced to the market as the first commercially available
devices using transistors.
1 Invention and Technological Progresses of Integrated Circuits 9

Fig. 1.2 The world’s first

transistor

Oct. 18, 1954, the first transistor radio “Regency TR1” was launched to the market
and contained only four germanium (Ge) transistors. By 1959, transistors were
already used in half of the ten million radios sold.
Jan. 1954, Bell Labs assembled the world’s first Transistor Digital Computer,
TRADIC, with 684 transistors, as shown in Fig. 1.3.
1957: IBM started to sell computer IBM-608 that used 3000 transistors; it was the
world’s first commercially available computer. The IBM-608 computer con-
sumed 90% less power than a computer using electron tubes. Its clock frequency
was 100 kHz and supported 9 instructions. Its average time of multiplying two
9-bit BCD numbers was only 11 ms, and the weight was about 1 t.

Invention of ICs

Although the weight of the transistor computer IBM-608 was only 1/30 that of
ENIAC, the weight of 1 t was still impossible for the Army’s soldiers to carry, and it
was also not likely to be loaded on an aircraft. In the early 1960s, a calculator capable
of four arithmetic operations, powers, and taking the square root was comparable in
weight to a 2100 CRT TV set, and its volume also far exceeded that of the abacus and
calculation ruler. To this end, the National Bureau of Standards (NBS), US Air
Force, and US Navy were all committed to the research and development of
electronic equipment miniaturization. In the United States, there were three aspects
to the development of electronic equipment miniaturization: (1) The Army’s Signal
Corps supported the Micro Modules to miniaturize and integrate components on
existing ceramic substrates; (2) The Navy focused on supporting the thin film
10 Y.-W. Wang and M.-Z. Zheng

Fig. 1.3 TRADIC

technology; (3) The Air Force supported the integration work called “molecular
electronics.”
1952: The concept of integrated circuits was first introduced and described by a
British scientist, G. W. A. Dummer, at an electronic components conference at the
Royal Signal and Radar Establishment. He said: “With the advent of transistors and
comprehensive research on semiconductors, it now seems possible to imagine that
the future electronic equipment will be a solid module without interconnecting
wires.” Although Dummer’s idea was not implemented at that time, he pointed out
the direction for further research.
1958: Jack S. Kilby, who was responsible for the miniaturization of electronic
equipment at Texas Instruments (TI), proposed the idea of integrated circuits. He
said: “Since capacitors, resistors, transistors, and all other components could be
made of one material, I thought we would make them on a piece of semiconductor
material and then interconnect them to form a complete circuit” (this was Kilby’s
dialogue with Prof. Yangyuan Wang during his visiting to Peking University in
2001). On September 12 and 19, 1958, Kilby completed the manufacture and
demonstration of a phase-shifted oscillator and trigger, respectively, which marked
the birth of the integrated circuit (Kilby’s integrated circuit was made of germanium
transistors due to the limitations of TI’s production conditions at that time). On Feb
6, TI applied for a patent of a Miniaturized Electronic Circuit, Patent No. 3,138,743
and on May 6, 1959, applied patent 3,138,744, both were approved on June
23, 1964. Kilby and the first integrated circuit patent are shown in Fig. 1.4.
1 Invention and Technological Progresses of Integrated Circuits 11

Fig. 1.4 Kilby and the first IC patent

On March 6, 1959, TI announced the invention of the “Solid State Circuit,” or

Integrated Circuit (IC) at a press conference of the Institute of Radio Engineers (IRE,
the predecessor of the Institute of Electrical and Electronics Engineers, IEEE) in
New York.
On July 30, 1959, 5 months after TI patented the invention of integrated circuit,
Robert N. Noyce of Fairchild Co. applied for a patent of IC based on Si planar
technology (Patent No. 2,981,877, approved on April 25, 1961). Noyce and his
planar IC patent are shown in Fig. 1.5. Noyce’s invention is more suitable for the
mass production of integrated circuits.
In 2000, Kilby was awarded the Nobel Prize for Physics [1]. The Nobel Prize
committee said that Kilby “laid the foundation for modern information technology.”
Unfortunately, the Nobel Prize is not awarded to a deceased person, and Noyce died
on June 3, 1990, thus failing to receive the honor. When we saw the first sample of an
integrated circuit, we were surprised at its simplicity and roughness, but it was
always worth pondering the broad and profound wisdom it contains.

Milestones of Information Acquisition, Storage, and Processing

in IC Industry

Technology is the method and principle of problem-solving. It is the method that

people use existing things to form new things, and/or change the function and
performance of existing things. The development of technology is progressed by
mainly asking questions of why (demand), what to use (material), and how to do it
(process). At first, human beings could only obtain information directly through their
senses, such as Chinese medicine’s looking (vision), smelling (hearing), asking
(hearing), and cutting (touch).
12 Y.-W. Wang and M.-Z. Zheng

Fig. 1.5 Noyce and his planar IC patent

Imaging sensor and micro-electro-mechanical system (MEMS) are two mile-

stones of IC in the field of information acquisition.
Since visual information accounts for the largest proportion of the total amount of
information acquired by human beings (about 83%), how to convert this image
information into digital signals has become the most urgent demand of people. In
1969, Willard S. Boyle and George E. Smith of Bell Labs invented the Charge
Coupled Device (CCD). CCD solved the problem of converting optical images into
digital signals. In 2009, these two inventors won the Nobel Prize in Physics. In 1992,
Eric Fossum of the Jet Propulsion Laboratory (JPL) invented the CMOS Active
Pixel Sensor. Compared with CCD, CMOS has the advantages of smaller size, less
than 1/10 of the power consumption of CCD, and the price is 1/3 cheaper than CCD.
Currently, the photosensitive devices of digital cameras (including mobile phones)
are mostly CMOS image sensors.
The development of MEMS started with silicon micro-pressure sensors. In 1959,
Richard P. Feynman proposed the idea of micro-machinery. In 1988, Richard Muller
and colleagues in the Berkeley Sensor & Actuator Center (BSAC), of UC Berkeley,
1 Invention and Technological Progresses of Integrated Circuits 13

fabricated from silicon the world’s first operating micromotor [2], with a rotor
diameter of 60–12 μm. MEMS can integrate speed, temperature, humidity, altitude,
sound, pressure, orientation, gas, and other sensors, so that people can intuitively
feel the analog information (quick or slow, hot and cold, dry and wet, strength, etc.)
which can be accurately digitized. After the data collected by sensors are stored and
processed in MEMS, data can be output to internal actuators, such as gyroscopes and
motors, and can also be exchanged with external devices.
The most significant contribution of semiconductor memory is for the storage of
massive information. Humans originally stored information through the brain, and
the way they transmitted information was by oral instruction. Subsequently, infor-
mation about the development of human history was stored in natural objects (such
as rocks, tortoiseshells, bamboo slips, sheepskins), man-made artifacts (such as
bronzes, pottery), and buildings. Paper is the most extensive and oldest medium
used by man to store information. The memory of electronic computers was first
electromechanical devices (e.g., relays) and later magnetic media (e.g., drums, tapes,
cores). However, magnetic medium still has the disadvantages of large volume, large
mass, and small storage capacity.
After Frank Wanlass and Chi-Tang Sah of Fairchild put forward the concept of
metal-oxide-semiconductor (MOS) in 1963, in July 1967, two types of semiconduc-
tor memory were invented simultaneously: One was the Dynamic Random Access
Memory (DRAM) invented by Robert Dennard, who worked at IBM. The other is
the non-volatile Semiconductor Memory (NVSM) invented by Simon Min Sze, a
Chinese-American scientist, and Dawon Kahng, a Korean scientist working in Bell
Laboratories in the United States. In 1969, Intel successfully developed the 64-bit
bipolar Static Random Access Memory (SRAM) chip C3101as the pioneer of
semiconductor memory. In 1984, Fujio Masuoka of Toshiba of Japan developed
the Flash Memory based on the original NVSM concept.
DRAM stores data for a short time and requires refreshed periodically. DRAM is
generally used as computer memory. Flash memory can hold data for a long time and
is generally used as the external storage of a computer.
In 1970, Intel introduced 1Kbit MOS DRAM (Type C1103) using a 12 μm
process. The commercialization of 1 Kbit DRAM led to the rapid replacement of
magnetic core memories in computers by semiconductor memories. Today, the
memory capacity of DRAM has reached the order of magnitude of 109 bits. In
1988, Intel was the first to produce 256 Kbit flash chips and put them on the market.
Today, the maximum capacity of Solid State Drive (SSD) made up of flash memory
has reached the order of magnitude of 1013 bits, which is likely to replace Hard Disk
Drive (HDD).
The earliest data processors can be traced back to arithmetic, the abacuses, slide
rulers, mechanical computers, and later, electronic tube computers and transistor
computers. Although the latter was much faster than the former, its size, weight, and
power consumption were difficult for ordinary enterprises, families, and personal
users to handle.
14 Y.-W. Wang and M.-Z. Zheng

In 1971, Intel’s Hoff invented the Central Processing Unit (CPU) model 4400,
which played the most important role in the historical stage of information pro-
cessing. So far, the Microprocessor Unit (MPU) has become an indispensable core
component of all electronic devices.

Milestones of Development in IC Materials

The first-generation semiconductor materials were mainly germanium (Ge) and

silicon (Si).
The earliest semiconductor material was Ge, and the world’s first transistor and
the first IC were based on Ge. In 1886, the German chemist C. A. Winkler firstly
produced germanium, in honor of his home country. He named the new element
germanium, derived from the Latin German name Germania.
In 1950, American G. K. Teal and J. B. Little adopted J. Czochralski’s method
(also known as CZ method) and pulled out Ge monocrystalline. The thermal
conductivity of Ge is relatively low, 64 W/(m•K). Devices fabricated with Ge can
only operate below 90  C. When the temperature is higher than 90  C, the leakage
current of germanium devices increases significantly. The melting point of germa-
nium is only 937  C, and it is difficult to withstand such as doping, activation,
annealing, and other high temperature processes. At the same time, the oxide of Ge is
soluble in water and the structure is unstable. Therefore, it is impossible to make
MOS devices. More importantly, the mechanical properties of germanium are poor,
the diameter of germanium single crystal should not be very large, and the pro-
cessing and transportation of germanium chips also have certain safety problems.
In 1952, Teal and E. Buehler pulled out a single silicon crystal with the CZ
method. Subsequently, Texas Instruments (TI) successfully manufactured the first Si
transistor in 1954. Si has a large band gap width (1.106 eV) and the high thermal
conductivity (145 W/(m•K)). Silicon dioxide (SiO2) is the best dielectric insulating
material, and Si is one of the most abundant elements on earth (about 26% of the
weight of the earth’s crust). Because of these advantages, Si has become the
mainstream material of semiconductors since 1960s.
The second-generation semiconductor materials were mainly III-V compound
materials such as gallium arsenide (GaAs), indium phosphide (InP), indium antimo-
nide (InSb), and cadmium sulfide (CdS), which are suitable for the production of
high-speed, high-frequency, high-power, and light-emitting electronic devices. They
are excellent materials for making high-performance microwaves, millimeter-wave
devices, and light-emitting devices. They are also widely used for satellite commu-
nication, mobile communication, optical communication, and for applications such
as the global positioning system (GPS) and other fields.
The third generation of semiconductor materials mainly refers to silicon carbide
(SiC), gallium nitride (GaN), zinc oxide (ZnO), and aluminum nitride (AlN)
represented by wide band gap (band gap width greater than 2.2 eV) semiconductor
materials. These materials have many excellent properties, such as wide forbidden
band gap, high breakdown electric field, high power density (the power density of
1 Invention and Technological Progresses of Integrated Circuits 15

GaN is 10–30 times that of GaAs), high thermal conductivity, high electron satura-
tion velocity, and strong radiation resistance. Therefore, they are more suitable for
making high-temperature, high-frequency, radiation-resistant, high-power devices,
and semiconductor lasers. At present, the more mature third-generation semicon-
ductor materials are silicon carbide and gallium nitride. However, silicon carbide is
more mature than gallium nitride.
With the development of new devices, there is much more extensive research on
high-k dielectric materials (e.g., oxides of Mg, Ca, Sr, Ba, Zr, La, Hf, etc.), metal
gate materials (e.g., TiN, Al, Ni, lanthanide metals, rare earth metals, etc.), intercon-
nect materials (e.g., Al, Cu, Ti, Ta, W, etc.), memory materials of various transition
metal oxides (e.g., BaTiO3, SrTiO3, TiO2, ZrO2, NiO, MoO3, V2O5, WO3, ZnO,
etc.), epitaxial and substrate materials (e.g., strained silicon, FD-SOI, etc.), and
carbon-based materials (e.g., carbon nanotubes, graphene, etc.). For example,
III-V group materials are used for the Fin Field-Effect Transistor (FinFET) to
increase the carrier’s mobility. In interconnect structures, titanium (Ti), cobalt
(Co), nickel (Ni), or ruthenium (Ru) are used to form wires, and titanium nitride
(TiN), Ta, or TaN as barrier materials. In addition, Intel has applied metal Co for
local interconnection M0 and M1 in 14 nm technology node, and TSMC also applied
Co as local interconnection metal in its 7 nm technology node.

Milestones in IC Manufacturing

Generalized IC manufacturing mainly includes IC design, chip manufacturing, and

chip packaging (including testing) three aspects.
The initial design method of integrated circuit was all manual design, such as
manual drawing, manual-carved multilayer masks for exposure, etc. Manual design
was only suitable for small-scale integrated circuits. In 1970s, the first generation of
integrated circuit Computer Aided Design (CAD) system came out. Because com-
puters at the time did not have enough memory storage, and the computing speed
was also not fast enough, CAD tools could only handle simple tasks of layout level
design. In the late 1970s, simulation, automatic layout, and routing tools emerged to
improve the efficiency of integrated circuit design. In 1983, Workstation emerged on
the market and strongly supported the development of CAD technology, also the
beginning of commercial EDA. The second generation of CAD system or EDA now
appeared, which increased the function of logic-level design capabilities. In the
1990s, EDA entered the third generation, which brought behavior-level design
into the scope of automation design by means of Hardware Description Language
(HDL). After entering the twenty-first century, IC Design develops toward Design
for Manufacturability (DFM), and its important technical directions include hard-
ware/software co-design, IP library, low power design, reliability design, as well as
System on Chip (SoC) and System in Package (SiP).
Integrated circuit manufacturing is the process of making specific patterns on
specific thin films. Among them, oxidation, epitaxy, doping (diffusion, ion implan-
tation), and deposition (physical vapor deposition, chemical vapor deposition) are
16 Y.-W. Wang and M.-Z. Zheng

thin film manufacturing process, and photolithography (exposure and etching)

process are patterning processes.
Exposure and etching are the core technologies for the fabrication of IC patterns.
The first step is to reduce the wavelength of exposure light source for shrinking the
feature size.
Before the mid-1970s, the exposure source was mercury lamps, as multi-
wavelength light sources with a wavelength range from 400 nm to 700 nm. In
1982, the exposure light source was modified to Ultraviolet (UV) G-line (wave-
length 436 nm) and I-line (wavelength 365 nm). In 1994, the wavelength of
exposure light source entered the field of deep ultraviolet (DUV), and mainly are
excimer laser KrF (wavelength 248 nm) and ArF (wavelength 193 nm).
In December 2003, the company Advanced Semiconductor Material Lithography
(ASML) of the Netherlands released the world’s first commercial immersion lithog-
raphy equipment. By filling the pure de-ionized water between the lower surface of
the last lens of the objective projection lenses and the silicon wafer, thus the effective
wavelength of the exposure light source is shortened to extend the 193 nm lithog-
raphy to 32 nm CMOS technology nodes. In addition, by using double exposure/
double patterning technology (DPT), 193 nm immersion lithography has been
extended to 10 nm/7 nm technology nodes.
After a specific pattern exposure of the film, but also to remove the unwanted part
to get the desired graphics, this is the etching process. The initial etching technique is
wet etching, because of isotropic etching, so the controllability of pattern size is
poor. After 1980, the etching technology entered the era of dry etching, including
plasma etching and Reactive Ion Etching (RIE), which is the current mainstream
etching technology.
When all the transistors are made on silicon wafers using thin film technology and
lithography, millions or billions of transistors must be connected by interconnection
technology, according to the design rules, to form real circuits. The initial intercon-
nection material is aluminum (Al), and studies have shown that the delay generated
by the interconnection has exceeded the gate delay in the case of 0.25 μm process
(with aluminum wire, SiO2dielectrics). In 1997, IBM announced the introduction of
chips using copper (Cu, with conductivity of 59.6  106 S/m or resistivity of
1.7 μΩ cm) interconnection technology, known as the famous mosaic (Damascene)
technology.
The whole machine or system is the interface between ICs and the final consumer.
The value of the integrated circuit can be realized only through its application in the
whole machine or system. Packaging is the interface between the integrated circuit
chip and the whole machine or system. Only the packaged chips can be loaded into
the system and play their due role in the system.
The original IC packaging followed the transistor outline (TO) packaging form.
In the mid-1960s, dual in-line package (DIP) became the mainstream of IC packag-
ing. In the 1980s, the surface mount technology (SMT) was developed rapidly, with
the emergence of various packaging forms, such as plastic leaded chip carrier
(PLCC) package and plastic quad flat pack (PQFP).
1 Invention and Technological Progresses of Integrated Circuits 17

Fig. 1.6 Milestones in the developing process of IC manufacturing technology

From 1980s to 1990s, the leads of IC packages evolved from perimeter type to
surface arrays, such as pin grid array (PGA) packages. Since the Ball Grid Array
(BGA) packaging in the 1990s, the “plug-in” concept of packaging was subverted by
SMT, in which “pins” were replaced by “solder balls.” At the end of the twentieth
century, the Chip Scale Package (CSP) solved the contradiction between a small chip
area and the large package area, which led to the revolution of package technology.
In the future, IC packaging will develop toward the System in Package (SiP). The
most important technology in 3D packaging is the Through Silicon Vias (TSV),
based on IBM’s Merlin Smith and Emanuel Stern’s invention, patented in 1964, and
has been used in integrated circuit packaging since 2010.
Another trend in IC manufacturing technology is the continually increasing
diameter of silicon wafers. Take Intel production line as an example. In 1972, the
diameter of silicon wafer was 3 in. (or 75 mm), and in 1992, it was 200 mm. In 2002,
Intel established the first 300 mm silicon wafer production line.
In summary, important milestones in the development of IC manufacturing
technology are shown in Fig. 1.6.

From Industry Age to Information Age

Before the eighteenth century, the world was in the period of agricultural civilization.
As an indicator of economic development, the gross domestic product (GDP) had
been at a low level and only slightly increased with the natural growth of the
population. From the first year AD to 1820, the world’s population had a compound
annual growth rate of 0.0084%, and the GDP had a compound annual growth rate of
0.105%.
18 Y.-W. Wang and M.-Z. Zheng

In 1776, James Watt invented the first practical steam engine and triggered the
first energy-based industrial revolution.
In the arena of industry and society, the increased production efficiency and
improved life quality arrives at the cost of energy, especially the disposable energy.
Without the intervention of energy, there could be no progress in industry society. As
shown in Fig. 1.7, from 1820 to 1950, the world population increased to 2.42 times
of 1820, energy consumption increased to 3.36 times of 1820, and GDP increased to
7.73 times of 1820 [3].
The annual growth rate of world energy consumption and GDP from 1965 to
2015 is shown in Fig. 1.8 [4].

Fig. 1.7 Growth of population, energy, and GDP in industrial society

Fig. 1.8 Annual growth rate of world energy consumption and GDP in 1965–2015 [2]
1 Invention and Technological Progresses of Integrated Circuits 19

Fig. 1.9 Global transistor

yields

In 2014, semiconductor manufacturers worldwide produced 2.5  1020 transis-

tors (see Fig. 1.9), or 8 trillion transistors per second. At the time, the total number of
transistors shipped worldwide since the invention of the technology was 2.9 sextil-
lion (2.9  1022). However, as the manufacturing process continues to improve in
accordance with Moore’s Law, by 2018, the world has made a total of 13 sextillion
(1.3  1023) MOSFET transistors, that is, in 4 years, MOSFET transistor
manufacturing total increased by 10 sextillions. By 2022, the total number of
MOSFET transistors manufactured worldwide has exceeded 30 sextillions, com-
pared with 60 billion transistors per Intel CPU today.
According to IC Insights statistics, in 2015, the global IC market size was
USD$286.9 million and reached $ 452.3 million in 2021 [5]. As can be seen from
Fig. 1.10, the average annual growth rate of world GDP in agricultural societies from
A.D. 1 to 1820 was only 0.105%. In the early industrial society from 1820 to 1950,
the average annual growth rate of global GDP reached 1.585%. In the post-industrial
society from 1950 to 1998, the annual average growth rate of global GDP further
reached 3.908%. From 1998 to 2012, when human society entered the early stage of
information society, the average annual growth rate of global GDP jumped to
6.622% [6]. Between 2012 and 2019, the growth rate has been maintained between
2.33% and 3.28% [7].

Market Demand and Driving Force of Information Technology

Language is the first carrier for representing human’s information. Writing is the first
tool to record language (sound information) and has become the second carrier of
human recording information.
In 1877, the American inventor Thomas A. Edison invented the phonograph.
In 1887, the German inventor Emile Berliner invented records that could be
reproduced in large numbers.
In 1898, the Danish scientist Poulsen Valdemar invented the steel wire recorder.
20 Y.-W. Wang and M.-Z. Zheng

Fig. 1.10 Innovation is the source of value: changes in the global total GDP

In 1935, German company AEG built the world’s first practical reel-to-reel tape
recorder, K1, which was demonstrated at the Berlin Radio Show.
In 1963, the Dutch company Philips (now NXP) invented the cassette tape
recorder.
In 1980, Sony and Philips jointly developed the technical specification of CDs
(compact disks). The storage medium of sound changed from the magnetic domain
to physical deformation (depression) of the carrier (plastic), and the method of
accessing sound information changed from electromagnetic conversion to photo-
electric conversion. That is, what recorded was no longer analog sound but digital
audio.
In 1995, Karlheinz Brandenburg, a German, developed the MP3 format, and
digital music recording and playing with Flash memory gradually became the
mainstream of portable recorders.
The earliest recorded information by mankind was the image information. Gen-
eralized image information includes written words, paintings, artifacts, costumes,
sculptures, architecture, etc.
In 1826, the Frenchman Joseph Nicéphore Nièpce first left light on the object
(a lead-tin alloy was coated to the asphalt); for the first time, a “chemical reaction”
was added to the information processing method.
In 1895, the French brothers Louis and Auguste Lumière invented the motion
picture machine, which turned the still images into moving images for the first time.
In 1960, the American Ampere company successfully developed the first video
camera. Continuous images were recorded through the change of magnetic field, in
1 Invention and Technological Progresses of Integrated Circuits 21

which the carrier was plastic, and the information processing method changed from
chemical reactions to electromagnetic conversion.
In 1975, the American Kodak company invented the “digital camera,” so that
images can be converted to digital.
In 1993, the Chinese company Wanyan produced the world’s first VCD (Video
Compact Disc). The information recorded on the disc was represented as carrier
deformation (depression), and the information processing method was photoelectric
conversion.
In 1995, Sony and Toshiba groups launched DVD (Digital Versatile Disc)
products in different formats respectively.
In the twenty-first century, with the rapid development of the integrated circuit
industry, the capacity of semiconductor memory has expanded dramatically, and the
working speed of the processor has also improved rapidly, making it possible to take
and playback photos or videos including audio in real time.
In addition to sound and image information, abstract data is also an important way
of information expression. The tools used by humans to record and process data and
information have evolved over a long period of time from string recording, arith-
metic, abacus, mechanical computer, slide rule, and perforated paper tape.
In 1945, Von Neumann, an American scientist, a Hungarian origin, proposed the
principle of stored program, which formed the von Neumann architecture of com-
puters that have continued to this day.
In 1946, the research and development team of the University of Pennsylvania
developed the world’s first Electronic Computer ENIAC (Electronic Numerical
Integrator and Computer).
In 1948, An Wang, a Chinese American, invented a magnetic core memory made
of ferrite material.
In 1950, IBM introduced reel-to-reel magnetic tape as the computer data storage.
In the same year, Yoshiro Nakamats of the Tokyo University invented the
floppy disk.
In 1953, the first magnetic drum was used in the IBM 701 computer.
In 1956, the IBM 305 RAMAC computer used disks as its external storage for the
first time.
In 1970, Intel’s semiconductor memory quickly replaced the magnetic core
memory.
In 1971, Ted Hoff and Stanley Mazor conceived Intel’s 4004 4-bit device, the first
integrated CPU. As the most important role, IC appeared in history for data storage
and information processing.
In 1976, Steven Paul Jobs assembled the first microcomputer and founded Apple
Computer Company, today’s Apple Inc.
In 1981, IBM officially produced the Personal Computer (PC). Since then, the
storage and processing of all kinds of information, including text, sound, images,
and data, have really stepped into the era of electronic computers.
The activity of information exchange is an integral part of human civilization, and
information generates value through sharing and exchange. The earliest information
transmission activities were carried out through beacon towers, carrier pigeons,
 22

Table 1.1 Evolution of information technology

Time period Ancient 17–18C 19C 20C 21C
Record form Script, drawing, Analog information Analog Analog information, digital Digital information
of sculpture, construct information information
information
Record media Color, tracing, shape, Carrier form (abacus, Carrier form Carrier form (CD) Electric charge (RT information
of structure slide rule, punched (hand-cranked Magnetic field change (audio capture, RT information
information tape, mechanical phonograph) recording, video recording, storage, RT information
computer) Magnetic field magnetic core, magnetic disk, processing, RT information
change (steel magnetic drum) transmitting)
wire, magnetic Electric charge change
recorder) (semiconductor storage, audio
Chemical change recording, video recording,
(photo, movie) writing and image processing)
Record Bone, shell, stone, Paper, wood, metal Metal, plastic Metal, plastic, semiconductor Semiconductor
carrier of bamboo, wood, clay,
information cloth, paper, metal,
etc.
Transmitting Language, writing Writing, object, Conducting EM wave EM wave
of wire, electric
information code
media
Time period Ancient 17–18C 19C 20C 21C
Method of Voice-sound, hand Post-stand, post office Telephone, Broadcasting, TV Internet, satellite
information delivery telegram
transmission
Principal Human Human, mechanics Mechanics, Electron tube, transistor, IC, IC, software
subject of chemistry software
information
processing
Y.-W. Wang and M.-Z. Zheng
1 Invention and Technological Progresses of Integrated Circuits 23

drifting bottles, etc. Since then, the way of conveying information through the
combination of people and vehicles of transportation has been used up to now.
In 1837, Samuel F. B. Morse, an American, invented Morse code, which solved
the problem of instant text transmission.
On March 7, 1876, Alexander Graham Bell, an American, invented the telephone
and solved the problem of instant (wired) transmission of sound. Bell received the
first patent for an “apparatus for transmitting vocal or other sounds telegraphically.”
In 1906, the American physicist Reginald A. Fessenden used radio broadcasting
stations to achieve the wireless transmission of sound.
In 1923, the Russian American physicist Vladimir Kosma Zworykin invented the
photoelectric camera tube for converting the image into electrical signal for the first
time and opened a new method for image transmission.
In 1929, Vladimir Kosma Zworykin manufactured the television picture tube and
carried out the complete test of television image transmission, which completed the
process of making television camera shooting and display fully of electronic process.
In the twenty-first century, due to the progress of microelectronics technology,
liquid crystal and plasma flat panel displays (FPD) have gradually replaced the
Cathode Ray Tube (CRT) displays. Image sensing, transmission, and visualization
all are performed in “solids” of electronic devices, which make it possible for mobile
devices to transmit information. Microelectronic technology has created a new
information world for human beings and created indelible historical achievements
in the development of human society. Table 1.1 summarizes the evolution of
information technology.

References
1. Invention of the integrated circuit, https://en.wikipedia.org/wiki/Invention_of_the_integrated_
circuit
2. Fabrication of micromotor, https://www.sciencedaily.com/releases/2003/07/030724084133.htm
3. X. Wu, X. Xu, Y. Ye, et al., Madison World Economic History Millennium (Peking University
Press, Beijing, 2003)
4. Statistical review of world energy 2016; Spencerdale presentation. http://www.bp.com/en/global/
corporate/energy-economics/statistical-review-of-world-energy/downloads.html. Accessed
01 June 2023
5. IC Market Size, https://icinsights.com/news/bulletins/Worldwide-IC-Market-Forecast-To-Top-
500-Billion-In-2021/. Accessed 01 June 2023
6. W. Yangyuan, W. Yongwen, Strategy: The Foundation of Survival and Development (Science
Press, Beijing, 2015)
7. World GDP Growth Rate 1961–2022, https://www.macrotrends.net/countries/WLD/world/gdp-
growth-rate. Accessed 01 June 2023
Characteristics and Strategic Significance
of IC Industry 2
Yong-Wen Wang and Min-Zheng Zheng

Contents
ICs and Green Economy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ICs and Social Life and Culture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
The Value Goes to Where the Knowledge Is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Abstract
IC technology has both strategic and marketable dual characteristics. The former
displays strategically the importance of electronic content is so high and critical,
including (1) in national information security of political, economic, and military
aspects; and (2) in national defense system, such as weapons equipment, spacecraft,
satellites, etc. The latter manifests IC applications in the core of the Internet and the
Internet of Thing, through network, routers with chips and operating systems, and
these essential devices. It is acclaimed that IC is yet a middle-product, and the end-
user determines the market needs. Market driving force and technology
progress have been promoting IC development and application. China consumed
474.2 billion pieces of IC products (72% imported) in 2016, this consumption is
estimated for a total production by 237 1200 -fabs, each to run at 30,000 WPM and to
produce 2 billion chips per year. In 2021, the import value of IC in China was
$433B, for a total 538.4 billion pieces, displaying continuously a tremendous impact
on IC market. Therefore, IC industry results in values and leading forward the
development of technology, such as in the green economy, social and cultural life.

Y.-W. Wang (*)

Institute of Microelectronics, Peking University, Beijing, China
e-mail: wangyw@pku.edu.cn
M.-Z. Zheng
Department of Information Technology Industry, Ministry of Industry and Information Technology,
Beijing, China

© Publishing House of Electronics Industry 2024 25

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_2
26 Y.-W. Wang and M.-Z. Zheng

Keywords
Green economy · Internet · Internet-of-Things (IoT) · Energy consumption · PC

ICs and Green Economy

The progress of industrial society has gradually extended human physical labor to
mechanical operations, but people have also paid a huge energy price for this, e.g.,
coal, oil, and natural gas buried underground millions of years ago to maintain the
high-speed operation of industrial economy.
While enjoying the convenience, speed, comfort, and pleasure brought by indus-
trial products, people also began to experience the bitter fruit brought by industrial
pollution. In order to no longer breathe the air full of hazes, no longer drink muddy
polluted river water, no longer face the fine land eroded by wind and sand, no longer
sigh for the disappearance of rain forest, human beings began to save the earth’s self-
salvation. Governments around the world have put forward the environmental
protection and green economy on the agenda. It has been announced that, since
1973, individuals, communities, civil society, businesses, and governments around
the world marked World Environment Day to be June 5 – by making commitments
and calling for action to restore millions of hectares of ecosystems all around the
world for the benefits of people and nature [1].
Microelectronic technology is playing an important role in energy saving and
ecological civilization construction. Just take the lamp as an example: an ordinary
60 W incandescent lamp consumes 1 kWh power for 17 h, an ordinary 10 W energy-
saving lamp consumes 1 kWh power for 100 h, and a LED lamp of the same
illumination consumes 1 kWh power for 1000 h. That means LED lamps consume
only 1/60 of the energy of incandescent lamps.
Figure 2.1 is a forecast result for the US electricity consumption based on the
Semiconductor Technology and Applications Energy Efficiency Outlook Model

Fig. 2.1 Forecast results for the US electricity consumption based on the Semiconductor Tech-
nology Application Energy Efficiency Outlook Model [2]
2 Characteristics and Strategic Significance of IC Industry 27

(by The American Council for an Energy-Efficient Economy, ACEEE). If the

technical performance remains the same, the electricity consumption of economic
development in the United States could increase to 6.502  1012 kWh by 2030.
According to the US Energy Information Administration, the widespread use of
semiconductor technology and devices could reduce the consumed electricity to
4.606  1012 kWh. If some policies are introduced to encourage the development
and application of semiconductor technology, the electricity demand can be further
reduced by 1.242  1012 kWh.
In addition, microelectronics technology has excellent potential in the monitoring
and control of air pollution, water pollution, and soil pollution and other aspects of
improving the environment. Compared with traditional industries, microelectronics
industry itself is also an industry with lower energy and water consumption.
As can be seen from Fig. 2.2, the industry with the highest energy consumption is
coking industry, with the energy consumption of 3.407 t standard coal per ¥10,000
RMB (or CNY) of output value. As a representative of microelectronics manufactur-
ing industry, SMIC’s energy consumption per ¥10,000 RMB of output value is only
0.115 t of standard coal. As can be seen from Fig. 2.3, the water consumption of
microelectronic manufacturing industry is relatively high, which is 4.413 m3per
¥10,000 RMB of output value. Due to the use of reclaim water, SMIC’s actual
water consumption is 0.387 m3 per ¥10,000 RMB of output value (90% of SMIC’s
water is recyclable reclaim water and the actual consumption of city water is 10%),
which is only 3% of that of the cotton and chemical fiber textile printing and dyeing
industry.

Fig. 2.2 Comparison of comprehensive energy consumption per 10,000 CNY output value in
different industry sectors [3]
28 Y.-W. Wang and M.-Z. Zheng

Fig. 2.3 Comparison of water consumption per CNY10,000 output value in different industries [4]

ICs and Social Life and Culture

Integrated circuits first came into people’s lives with the help of audio and visual
equipment, including radios, tape recorders, video recorders, DVDs, and televisions.
In 1976, Steve Wozniak and Steve Jobs developed the microcomputer Apple I. In
1981, IBM successfully introduced the Personal Computer (PC) using Intel’s 8088
microprocessor and Microsoft operating system MS-DOS to the market and named
this new Computer as “Personal Computer,” initiating the PC era. In 1990, the global
PC penetration rate was 0.53 units/100 people, and it began to become the main
product driving the electronic product market. Soon after, laptop computers and
tablet computers have started to hit the market. In 2006, the global PC penetration
rate reached 15.4 units/100 people, and 67.5 units/100 people in developed countries
(according to the World Bank data). The application of the PC and related software
has dramatically improved the work efficiency. Its text and graphics editing and data
processing functions have replaced manual writing, typesetting, ink printing, draw-
ing, drawing tables, and other complicated and inefficient manual operation.
In 1978, Bell Labs of the United States successfully developed the Advanced
Mobile Phone System (AMPS) and built the cellular mobile communication net-
work. In the 1980s, the mobile communication was analog signal communication,
and Motorola 8900 [3] (commonly known as “big brick” and “Mobile phone”) was
the first generation of analog communication mobile phone that entered China. In the
1990s, the digital mobile communication emerged. In1982, at the Conference of
European Posts and Telecommunication Administrations (CEPT), a Group Special
2 Characteristics and Strategic Significance of IC Industry 29

Mobile (GSM) under the Technical Committee of European Telecommunications

Standards Institute (ETSI) was established. Its task was to develop a standard for
pan-European mobile communication roaming, which was also the Global System
for Mobile Communications (GSM; originally short for French Groupe Spécial
Mobile, Special Mobile Group, now officially short for Global System for Mobile
Communications). According to the Communications Business statistics bulletin
data of the Ministry of Industry and Information Technology in 2015, the total
number of mobile users in China reached 1.3 billion, the penetration rate of
94.5%, and almost everyone had a mobile phone.
The birth of the Internet further changed people’s lifestyle. The Internet originated
from ARPANET (Advanced Research Projects Agency Network, an experimental
computer network). ARPANET was funded by the Advanced Research Projects
Agency, or ARPA in the late 1960s, which was developed by the Defense Advanced
Research Projects Agency (DARPA). The network was put into use in 1969. In
1974, Transmission Control Protocol (TCP) and Internet Protocol (IP) are available
and together called the TCP/IP protocol. The disclosure of the core technology of
TCP/IP finally led to the rapid development of the Internet. In 1991, CERN (Conseil
Européen pour la Recherche Nucléaire), the predecessor of the European Laboratory
for Quantum Physics, published the World Wide Web (WWW, developed in 1989 by
Tim Berners-Lee); WWW offered an interface-friendly information service for
retrieving and reading about servers connected to the Internet servers. In 1991, the
Internet was officially launched.
In 1992, there were about 720,000 computers connected to the Internet world-
wide. After 1995, the PC market entered a mature stage and began to gradually enter
urban civilian families. The number of networked computers increased to 6.64
million units. In 2004, the number of PCs in the world reached 580 million units,
and the number of networked computers exceeded 100 million units.
Integrated circuits have led to the spread of computers and smartphones, which
have created a whole new network culture including various applications (or APPs),
such as sending and receiving emails, browsing news, WeChat in 2011, Weibo in
2009, games, audio, video, health data sensing and recording, telemedicine, network
broadcast, online shopping, payment, travel booking, education, making friends,
catering, and other software. It covers almost everything people need for informa-
tion. The network enables the dissemination of culture to break through the limita-
tions of time and space and brings a profound revolution to the development of
human culture.
Of course, every new thing has two sides. The virtual nature of the network can also
be used by people with ulterior motives to blackmail, cheat, steal information, spread
viruses, and bring in people’s competitiveness and innovation under new threats. We
need to continually clean up the dirt on the Internet and continually keep protecting the
healthy growth of the Internet. German poet, critic, and literary historian, Wolfgang
Menzel (1798–1873), first recorded in 1512 the German proverb saying, “Schüttet das
Kind mit dem Bade aus,” which in English is “Throw the baby out with the bathwa-
ter.” What people can learn from this phrase is to make a right judgment, that is, to take
advantage of the benefits of modern technology while cleaning up the dirt.
30 Y.-W. Wang and M.-Z. Zheng

The Value Goes to Where the Knowledge Is

The development of IC technology has brought humanity into the information

society. In 2016, the global semiconductor market was $338.931 billion USD, and
the total market value of electronic system was $1457 billion USD (statistics data of
IC Insights). In 2020, the global semiconductor market has grown to $425.96 billion,
and the total market value of electronic system market compound annual growth
rates (CAGRs) from 2017 to 2021 was between 3.3% and 6.4% by Statista [5]. As a
major manufacturer of electronic information products in the world, China’s annual
output in mobile phones, televisions, computers, and other products has long been
ranked the top in the world. However, the output first does not mean the labor value
first. International economic competition shows that without advanced microelec-
tronic technology, it is impossible to have an advanced electronic product
manufacturing industry, and the core products without mastering micro-electronic
technology can only be at the low end of the industrial chain in the international
division of labor and play the role of “workers” who are eaten and exploited by
others in the distribution of benefits in the international market. Currently, although
the export value of China’s electronic products is relatively high, but most of the
values are earned by processing products with imported materials.
At present, many Chinese machinery companies do not master the core technol-
ogy of microelectronics, because of the dependence on imported integrated circuits
and related technology, resulting in a very low product profit margin; its net interest
rate is only about 1%. As an example, an iPhone that sells with a profit for $600
USD, Apple’s profit is $360 USD (60% of total profit), and Foxconn’s assembly
revenue is only $6.54 USD (barely 1.1% of total profit). On a $40 USD mouse,
Logitech makes 22.5% of its profits, while the assembly company makes only 7.5%.
The rapid development of IC technology and the knowledge behind has resulted
in tremendous market value. The profit distribution of the example in the above has
demonstrated an economic cycle of value from technology and technology from
knowledge. In the past a half century or so, the market has shown that “the value
goes to where the knowledge is.”

References
1. World Environment Day 5 June, https://www.un.org/en/observances/environment-day. Accessed
15 May 2023
2. J. Laitner, C.P. Knight, V.L. McKinney, et al., Semiconductor Technologies: The Potential to
Revolutionize US Energy Productivity: Report Number E094 (ACEEE, Washington, DC, 2009)
3. Shanghai Economic and Information Technology Commission, Shanghai Statistics Bureau
Shanghai Industrial Energy Efficiency Guide 2011 Edition (11-26-2011), http://www.
sheitcgovcn/cynxzn/65384htm. Accessed 02 Apr 2017
4. W. Yongwen, W. Yangyuan, Ten years of grinding a sword: Discussion on the history review and
development law of integrated circuit industry. China Integr. Circuit 16(3), 9–14 (2007)
5. Statista, https://www.statista.com/statistics/783608/worldwide-electronic-system-cagr-by-cate
gory/. Accessed 15 May 2023
The Development Law of the IC Industry
3
Yong-Wen Wang and Min-Zheng Zheng

Contents
Moore’s Law and Bell’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Gene’s Law, Gilder’s Law, and Metcalfe’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Development Pattern of IC Technology and Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
The End of Moore’s Law and the Innovations of Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Physical Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power Consumption Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Economic Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Abstract
Moore’s Law has great significance in the development of integrated circuit
industry. In general, we can say that the number of components in IC doubles
every 18 to 24 months. As a complement to Moore’s Law, Bell’s Law predicted
that by keeping a computer’s capabilities unchanged, the price and volume of the
microprocessor would reduce by half in every 18 months. Gene’s Law indicated
that the power consumption/performance ratio of DSP reduces by 2 orders of
magnitude every 10 years. Metcalfe’s Law states: The value of the network is
proportional to the square of the number of network users; that is, N connections
can create benefits. Like Moore’s Law, both Gilder’s Law and Metcalfe’s Law are
empirical, approximate descriptions and predictions to be validated. Along with
the IC development path as forecasted by Moore’s Law, the line width of IC
technology is gradually scaled down. In 2023, the IC manufacturing technology

Y.-W. Wang (*)

Institute of Microelectronics, Peking University, Beijing, China
e-mail: wangyw@pku.edu.cn
M.-Z. Zheng
Department of Information Technology Industry, Ministry of Industry and Information Technology,
Beijing, China

© Publishing House of Electronics Industry 2024 31

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_3
32 Y.-W. Wang and M.-Z. Zheng

is at 3 nm node and entering the scope of mesoscopic physics. There are three
constraints for continuous scaling of technology: physical constraints, power
consumption constraints, and economic constraints.

Keywords
Moore’s Law · Bell’s Law · Gene’s Law · Metcalfe’s Law · 3 nm

Moore’s Law and Bell’s Law

On April 19, 1965, Gordon E. Moore, then director of the Fairchild Semiconductor’s
R&D Laboratory, was invited to write a review for the 35th anniversary issue of
Electronics magazine, entitled “Cramming More Components onto Integrated Cir-
cuits.” Figure 3.1 shows the home page of the review. In the middle of the right side
of the second page, the summary of the report further elaborated: “The complexity
for minimum component costs has increased at a rate of roughly a factor of 2 per
year. Certainly, over the short term this rate can be expected to continue, if not to
increase. Over the longer term, the rate of increase is a bit more uncertain, although
there is no reason to believe it will not remain nearly constant for at least 10 years.
That means by 1975, the number of components per IC for minimum cost will be
65,000. I believe that such a large circuit can be built on a single wafer.” This was the
original “Moore’s Law.”
In 1975, Moore published the article “Progress in Digital Integrated Electron-
ics” at the IEEE International Electron Devices Meeting (IEDM). This paper
revised the annual doubling by saying doubling every 2 years: “The new slope
might approximate a doubling every two years, rather than every year, by the end
of the decade.” Figure 3.2 shows the “Moore’s Law” published in 1965 and its
revisions made in 1975.It is worth noting that Moore himself has never stated that
“the integration degree of integrated circuits doubles in 18 months.” In an inter-
view with Scientific American magazine in September 1997, he specifically stated
that “I predicted we were going to change from doubling every year to doubling
every two years, which is kind of where we are now. I never said 18 months.” The
American Semiconductor Industry Association (SIA) cited the argument of dou-
bling every 24 months in the 2001 edition of ITRS and extended it all the way to
2020. The increase in the number of components in microprocessors did follow the
Moore’s forecast of doubling in 24 months, but the increase in the number of
components in DRAM was slightly faster than that in microprocessors, to the
extent of doubling in 18 months, as shown in Fig. 3.3. Therefore, we can generally
say that the number of components in the integrated circuit doubles every 18 to
24 months. However, this is not a law, but a statistical result of IC manufacturing
practice. It does really reflect the objective law of the development and change of
things under certain conditions. In this sense, it is not unreasonable to translate
“Moore’s Forecast” into “Moore’s Law,” but it is not a strict law in mathematics,
physics, and other scientific disciplines.
3 The Development Law of the IC Industry 33

Fig. 3.1 The home page of Gordon Moore’s review published on Electronics in 1965

In 1972, Gordon Bell, working for Digital Equipment Corporation (DEC), made
the following prediction about the development of microprocessor technology for
the VAX (PDP): If the computer’s capabilities remain constant, the price and the size
of the microprocessor would reduce by half in every 18 months. As a complement to
Moore’s Law, Bell’s predictions became known as Bell’s Law.
34 Y.-W. Wang and M.-Z. Zheng

Fig. 3.2 “Moore’s Law” published in 1965 and its revisions made in 1975 (original article
illustration)

Fig. 3.3 The growth of numbers of components in CPU, DRAM, and 3D-NAND

Gene’s Law, Gilder’s Law, and Metcalfe’s Law

In 2006, TI’s chief scientist, Gene Frantz, told the reporter of Electronic Engineering
Times (EE Times) at the TI Developer Conference: “Many DSP experts agree that
millions of multiply-accumulate operations per second (MMAC/s) is simple and fair
test indicator. I have carefully studied the power consumption for each MMAC/s of
the DSP, that is, the power consumption per MMAC/s reduced to half every
18 months.” His words can also be expressed as “The power consumption/perfor-
mance ratio of DSP decreases by two orders of magnitude every 10 years.” It means
3 The Development Law of the IC Industry 35

Fig. 3.4 Gene’s Law

that the power consumption/performance ratio of a DPS 10 years ago was 100 times
that of today. This is the famous “Gene’s Law.” It is shown in Fig. 3.4 [1].
In 1996 George Gilder, an American economist, put forward a prediction in his
book Telecosm that the bandwidth of the backbone network would double every
6 months over the next 25 years, and its growth rate would be four times faster than
that of CPU predicted by Moore’s Law. This argument was known as Gilder’s Law.
Mr. Gilder also asserted that the transmission price per bit would jump to free in an
“asymptotic curve,” with a price point infinitely close to zero, and that free Internet
access would be imminent.
Metcalfe’s Law was developed by the 3Com founder and computer networking
pioneer Robert M. Metcalfe and named in 1993 by George Gilder, publisher of the
Gilder SciTech Monthly. The law states that the value of a network is proportional to
the square of the number of users on the network, which means that N connections
can create N2 benefits. That is, if a network is worth ¥1 RMB to each person in the
network, then the total value of a network 10 times larger is equal to ¥100 RMB; a
network 100 times the size has a total value of ¥10, 000 RMB. When a network
grows 10 times in size, its value increases 100 times. In the era of network economy,
the higher the degree of sharing, the larger the user group, the more its value can be
reflected to the greatest extent. In short, the more people online, the more benefits
they generate. However, this description is currently controversial or flawed in that it
assigns the same “value” to all connections or groups. This led to the emergence of a
network bubble at the end of the twentieth century, which only pursued growth rather
than profit.
Like Moore’s Law, Gilder’s law and Metcalfe’s law are empirical, untested
predictions and rough descriptions, not laws in the sense of physics.

Development Pattern of IC Technology and Industry

Throughout the development of microelectronics over the past 50 years, the progress
of microelectronics technology, industry, and market has shown the following laws.
36 Y.-W. Wang and M.-Z. Zheng

Fig. 3.5 Sales of the global semiconductor market and Y/Y % change from 1996 to 2021

1. Driven by continuous advancements of technologies in microelectronics design,

manufacturing, packaging, materials, and equipment, the scale of the microelec-
tronics industry has expanded rapidly, and the sales volume of the semiconductor
market have been on the rise [2], as shown in Fig. 3.5.
2. The semiconductor market performance is also characterized by regular fluctua-
tions in growth rates, that is, an “M” shaped change appears approximately every
10 years, as shown in Fig. 3.6. The reasons for fluctuations in the growth rate of
the semiconductor market are complicated, but the main reasons are market
traction and technology driven by investment. The relationship between the
growth rate of world GDP and the growth rate of semiconductor market is
shown in Fig. 3.7.
3. The manufacturing technology of semiconductor products has reached a new
level in about every 10 years, as illustrated in Table 3.1.
4. Typical microelectronic products take about 10 years from R&D to mass pro-
duction as shown in Fig. 3.8, and Fig 3.9 shows a typical integrated circuit that
takes about 10 years from R&D to mass production.
3 The Development Law of the IC Industry 37

Fig. 3.6 Changes in the growth rate of the global semiconductor market from 1975 to 2020

Fig. 3.7 Correlation between global semiconductor sales growth rate and global economic growth
rate from 1986 to 2020

5. Engines that drive the information market have undergone a new change about
every 10 years or so, as shown in Fig. 3.10.
6. The price of transistors in integrated circuits is declining by two orders of
magnitude every 10 years (prices were 100 times higher 10 years ago), as
shown in Fig. 3.11. While DRAM/DDR market maintained up and down, price
of 1 Gb dropped to < $1, the Flash memory market [3] started to rise
(2013–2020).
 38

Table 3.1 Manufacturing technology of semiconductor products advanced one generation for about every 10 years
Stage Gen 1 Gen 2 Gen 3 Gen 4 Gen 5 Gen 6
Period 1965–1975 1975–1985 1985–1995 1995–2005 2005–2015 2015–2025
Main litho light Mercury lamp G-Line I-Line KrF ArF EUV, EPL
source
Typical wavelength Multi-wavelength 436 nm 365 nm 248 nm 193 nm (DPT Immersion 13.5 nm
Lithography & DPT)
Feature size 12 ~ 3 μm 3 ~ 1 μm 1 ~ 0.35 μm 0.35 μm ~ 65 nm 65 ~ 22 nm 22 ~ 7 nm
Memory 1 KB ~ 16 KB 16 KM ~ 1 MB 1 ~ 64 MB 64 MB ~ 1 GB 1 ~ 16 GB (Chipset) 16 GB-1 TB or
above 1 TB
(Chipset)
CPU Products (Intel From 4004 to From 8086 to From 386 to Pentium Core
as an example) 8080 286 486
CPU word length / 4,8 8,16 16,32 32,64 64
bit
Transistor number 103 104 ~ 105 105 ~ 106 106 ~ 107 108 ~ 109 Multi-core Multi-core
of CPUa architecture architecture
1
CPU clock 10 ~ 100 100 ~ 101 101 ~ 102 102 ~ 103 Non-standard frequency Non-standard
frequencya/MHz frequency
Wafer diameter 2 ~ 4in 4 in ~ 150 mm 150 mm, 200 mm, 300 mm 200 mm, 300 mm 200 mm, 300 mm,
200 mm 450 mm
Design tools Manual From logic From synthesis From synthesis to SoC, IP SoC, IP, SiP
editing to P&R to P&R DFM
Main package form From TO to DIP DIP From DIP to DIP, QFP, BGA Various packaging SiP SiP, 3D
QFP
a
The increase of CPU clock frequency will lead to a sharp increase in power consumption, and the main frequency increase is no longer the main factor of design
pursuit. Under the condition of keeping the dominant frequency unchanged, it has become the mainstream of CPU design by simplifying pipeline structure,
reducing design complexity, improving unit performance and processor energy efficiency, and adopting multi-core architecture.
Y.-W. Wang and M.-Z. Zheng
3 The Development Law of the IC Industry 39

Fig. 3.8 Typical microelectronic products take about 10 years from R&D to mass production

Fig. 3.9 Typical cases of IC, from R&D to mass production needs about 10 years
40 Y.-W. Wang and M.-Z. Zheng

Fig. 3.10 The change of engines that drive the information market

Fig. 3.11 The declining pattern of transistor price in integrated circuits. (a) Unit price of DRAM
transistor kept dropping (1968–2013); down: (b) the Flash memory market [2] started to rise
(2013–2020)

The End of Moore’s Law and the Innovations of Software

Along the development path of integrated circuits predicted by Moore’s Law, the line
width of ICs is gradually scaled down, and the minimum line width has reached 3 nm
in 2021, which has entered the category of mesoscopic physics. From the point view
3 The Development Law of the IC Industry 41

of technology, continuing to narrow the channel line width simply will be

constrained by three factors.

Physical Constraints

Mesoscopic scale materials, on the one hand, contain a certain number of particles,
which cannot be solved by the Schrödinger equation alone. On the other hand, the
number of particles is not large enough to neglect the statistical fluctuations. This
situation poses many physical obstacles to the further development of IC technology,
such as Fermi-Pinning, Coulomb Blockade, Quantum Tunneling, Impurity Fluctu-
ation, and Spin Transport. They need to be solved by mesoscopic physics and
quantum-based processing methods.

Power Consumption Constraints

Figure 3.12 shows a contradicted trend between improving device performance (the
clock frequency as a representing parameter) and reducing power consumption. With
the advanced technology nodes, the clock frequency of each generation of devices
increases by 20%, but the power density of device also increases greatly. If the power
density is kept at 40 W/cm2, the maximum clock frequency cannot be increased, and
even the clock frequency decreases after the adoption of 14 nm technology nodes.

Fig. 3.12 The contradiction trend between increasing the clock frequency and reducing power
consumption [4]
42 Y.-W. Wang and M.-Z. Zheng

Economic Constraints

Figure 3.13 shows the variation trend of gate cost with technology nodes, where the
cost per 100 M gates ($/100 MGates) of the 90 nm technology node is $4.01. After
that, the cost of 65 nm, 40 nm to 28 nm shows a downward trend. Among them, the
28 nm is one of the last planar technology nodes. However, after entering the 20 nm
technology node with 3D FinFET structures, the cost per 100 Mgates will no longer
decline according to the Moore’s Law, but instead, it will rise. This is driven by the
increased complexity of fabricating these chips with advanced device structures.
That is to say, in the future, in the three aspects of higher speed, lower power
consumption, and lower cost, if the cost is taken as the main indicator, performance
and power consumption will hardly be significantly improved. On the contrary, chip
manufacturers and users who focus on performance and power consumption will
have to pay the corresponding price instead of enjoying the “benefits” of cost
reduction brought by the Moore’s Law. However, if new materials and new device
structures are adopted, whether the integrating degree of IC continues to grow along
Moore’s Law remains to be tested by future practice.
Integrated circuits depend more on ecosystem and need hardware and software
co-development. For example, CPU competition is not only about CPU chips
themselves, but also about its software ecosystems. For instance, Intel’s CPU and
Microsoft’s operating system have built a stable Wintel industry development
environment. ARM and Google have also built ARM-Android system in the field
of mobile terminals.
The information industry was initially driven by hardware (IC) technology. With
the progress of IC processing technology, the integration degree of single chips is
getting higher, the speed of IC is getting faster, and the memory storage capacity is
getting larger. Thus, the software loaded on the IC can be more abundant, the
functions of software become more powerful, and more kinds of application soft-
ware are available. Figure 3.14 shows the positive correlation between the memory

Fig. 3.13 The variation trend

of gate cost with technology
nodes [5]
3 The Development Law of the IC Industry 43

Fig. 3.14 CPU dominant frequency, DRAM storage capacity, and the memory space occupied by
the operating system

Fig. 3.15 Trends of the

software-driven information
industry

space occupied by the Windows operating system, the Intel CPU dominant fre-
quency, and the storage capacity of typical DRAM during the same period.
At present, the capacity and speed of integrated circuits have been able to meet
the needs of almost any software. In this case, the trend of the information industry
driven by software began to emerge, that is, according to different operating systems
to develop the hardware suitable for the software. Mobile communications are a
prime example. Currently, Android and iOS are the mainstream operating systems in
the market. Recently, on August 4, 2023, Huawei officially released HarmonyOS 4,
which is the third largest smartphone platform after iOS and Android. At present, the
number of devices using HarmonyOS ecology has exceeded 700 million.
44 Y.-W. Wang and M.-Z. Zheng

HarmonyOS is a distributed operating system developed by Huawei, officially

known as Huawei Terminal HarmonyOS Intelligent Device Operating System
software. HarmonyOS system uses the “decentralized” technology to combine
multiple devices such as mobile phones, computers, tablets, TVS, cars, and smart
wearables into a hyperterminal that allows users to easily operate and share the
resources of various devices. Therefore, all hardware solutions should be developed
according to these three operating systems. All different mobile phones could be
manufactured by using different embedded CPUs, receiving and transmitting chips,
and human-machine interface chips that come from different manufacturers, if they
would work in the systems mentioned above. This is a software-defined system,
which determines the design and production of integrated circuits, as shown in
Fig. 3.15.
Gene Frantz, TI’s chief scientist, considers that: “The bulk of the innovation will
be in the software on top of the hardware. Hardware will become part of the platform
on which innovative designers will develop their ideas” [6]. Therefore, following the
trend of information industry development driven by software as an essential part of
the strategic layout, the corresponding software discipline research should be coor-
dinated deployment in line with market demand.

References
1. G.A. Frantz, Power: The Final Frontier for Technology Breakthroughs. Unpublished lecture PPT
in school of electronics and information engineering, Soochow University, 11-Sep-2009: 1–13
2. WSTS, https://www.semiconductors.org/global-semiconductor-sales-units-shipped-reach-all-
time-highs-in-2021-as-industry-ramps-up-production-amid-shortage/. Accessed 23 May 2023
3. Statistics, Flash Memory Market 2013–2021, https://www.statista.com/statistics/553556/
worldwide-flash-memory-market-size/. Accessed 23 May 2023
4. L. Chang, D.J. Frank, Technology Optimization for High Energy – Efficiency Computation,
Short Course on Emerging Technologies for Post 14nm CMOS, IEDM (2012)
5. 10nm node offers lower gate costs, https://archive.eetasia.com/www.eetasia.com/ART_
8800713357_1034362_NT_9ca5570a.HTM. Accessed 23 May 2023
6. Texas Instruments Microcontrollers (MCUs) & processors: https://www.ti.com/microcontrollers-
mcus-processors/overview.html. Accessed 23 May 2023
Development of World IC Industry
4
Da-Kang Mo and Ke Li

Contents
Global GDP and GDP per Capita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IC Supply Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Wafer Foundry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Evolution of IC Industrial Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revenue Change of the Top 10 World’s Semiconductor Companies (1985–2021) . . . . . . . . . . . . 57
Revenue, Distribution, and Product Category of Global Semiconductor Market
(1997–2021) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
World Semiconductor Council (WSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Semiconductor Equipment and Materials International . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Global Semiconductor Alliance (GSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
International Technology Roadmap for Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Worldwide Major Institutions of IC Research and Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interuniversity Microelectronics Center (IMEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Very Large-Scale Integration (VLSI) Consortium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Semiconductor Manufacturing Technology Research Consortium (SEMATECH) . . . . . . . . . 71
Semiconductor Leading Edge Technologies, Inc. (SELETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Semiconductor Market Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Days Sales of Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
The Annual Growth Rate of the Semiconductor Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Book-to-Bill Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Semiconductor Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
World Semiconductor Trade Statistics (WSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Worldwide Major IC Market Research and Consulting Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IC Insights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Gartner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TrendForce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Yole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

D.-K. Mo (*)
Truth Semi Group, Shanghai, China
K. Li
Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China

© Publishing House of Electronics Industry 2024 45

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_4
46 D.-K. Mo and K. Li

Perspectives of IC Science and Technology in Post-Moore Era . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Abstract
The major IC enterprises facing to the market directly are fabless design enter-
prises (no production line), integrated device manufacturers (IDM), and intellec-
tual property (IP) providers. EDA enterprises primarily provide design
methodologies and tool suites but not for providing chip fabrication services,
while wafer foundry (or Fab) can provide IC fabrication services. In the IC
industry chain, IPs are commonly provided as process-proven and can be embed-
ded in chips or known good dies (KGD); packaging and testing companies
mainly provide services for Fabs, and IDM companies, materials companies,
and special equipment companies mainly provide the required materials and
equipment, respectively, for chip manufacturers. The industry is subject to the
influences by several semiconductor organizations, such as World Semiconductor
Council (WSC), Semiconductor Equipment and Materials International (SEMI),
and Global Semiconductor Association (GSA). Additionally, there are also sev-
eral IC market research and consulting companies, World Semiconductor Trade
Statistics (WSTS), IC Insights, Gartner, Trend Force, and Yole, whose roles as if
are IC liaisons in between IC designs and research, chip manufacturing, and
product marketing.

Keywords
Fabless · Integrated device manufacturers (IDM) · Intellectual property (IP) ·
Foundry · SEMI · GSA

Global GDP and GDP per Capita

Gross domestic product (GDP) means the market value of all final products and
services produced by all resident units over a certain period in a country (within
national boundaries). GDP is the core index of national economic accounting. It is
also an important indicator to measure the overall economic situation of a country or
a region.
The variation in the total amount of the world GDP from the first year of AD
(Anno Domini 1, AD 1) to the year of 1973 is shown in Fig. 4.1. It is obvious that the
GDP growth of agricultural society is extremely slow before AD 1820. The total
world GDP was Int$102.36 billion dollars (1990 international dollars) in AD 1 and
Int$694.442 billion dollars in 1820, respectively. The total GDP increased 6.8 times
over about 2000 years period. After 1820, the first industrial revolution and the
second industrial revolution greatly raised the growth speed of the world GDP. The
GDP increased from Int$694.442 billion dollars in 1820 to Int$16,059.180 billion
dollars 1973. The total amount of world GDP increased 22 times over 153 years.
4 Development of World IC Industry 47

Fig. 4.1 The total amount variation of world GDP from the first year AD to 1973. 1990
International dollar (Int$, also known as the Geary-Khamis dollar, G-K$). It is a method to convert
different national currencies into a uniform currency or an international dollar based on the parity
comparisons in multilateral purchasing power. Originally created by Irish economic statisticians
R. G. Geary, then developed by S.H. Khamis. (Data source: Millennium History of the World
Economy, By Angus Madison, translated by Xiao-ying Wu)

Fig. 4.2 The variation in the total amount of world GDP from 1960 to 2021. (Data source:
Millennium History of the World Economy, By Angus Madison, translated by Xiao-ying Wu;
World Bank)
48 D.-K. Mo and K. Li

The variation of the total world GDP from 1960 to 2021 is shown in Fig. 4.2. It
indicated that the world GDP grew steadily from 1960 to 1980. Thereafter, there was
a world economic stagflation due to the depression in the United States and the slow
economic growth in Europe during 1980 to 1985. Thus, the United States grew by

0.2% in 1981 and
1.9% in 1982. In the European Union, meanwhile, the
corresponding growth rates of the Europe Union were 0.3% and 1.0%, respectively.
The growth rate of world GDP boosted rapidly from 1986 to 1996. As shown in
Fig. 4.2, the slope of GDP growth is significantly higher than that of the previous
period from1960 to 1980. During this period, the average annual growth rate of
world GDP was 2.9% and the total GDP doubled. Besides, Asia-Pacific region grew
at an average annual growth rate of 4.9% and its GDP grew 2.6 times. Moreover,
with an average annual growth rate of 10.1% and an aggregate GDP growth rate of
2.9 times, China has made an important contribution to the world GDP growth.
Total world GDP changed slightly between 1997 and 2001 as a result of the Asia
financial crisis. Since 2001, the information industry gradually surpassed the tradi-
tional industry and then became the world’s largest industry. This newly growing
industry has made a great contribution in GDP to the world economy. Therefore, the
slope of total world GDP growth in 2001 to 2021 was much higher than that in 1986
to 1996. Of which, in 2009, due to the global finance crisis trigged by the subprime
mortgage crisis in the United States, total world GDP amount declined again. In
addition, COVID-19 pandemic has also resulted in a serious decline of total world
GDP (84.75T USD) in 2020.
The COVID-19 pandemic led to the negative GDP growth in most of countries in
2020. Therefore, 2021 GDP growth is measured from a lower starting point of 84.75T
USD (2020) to 94.935T USD (2021). This can make the GDP growth rate appear
higher. To recover from the pandemic shutdown, almost all mature economies,
emerging markets, and developing economies experienced positive GDP growth in
2021. As shown in Fig. 4.3, in 2021, the world GDP growth rate is 5.9%, 8.9% in
India, 8.1% in China, 6.6% in emerging markets and developing economies, 5.9% in
USA, 5.5% in Euro area, and 5.1% in all mature economies. In addition, the GDP
growth rate of ASEAN-10 and Japan is 3% and 1.7%, respectively.
The variations of GDP proportion for various regions, including China, the
United States, Japan, etc., to the global total is shown in Fig. 4.4. In the agricultural
era, as a major agricultural country in the world, China’s GDP accounted for more
than 22% of the world’s GDP, and even reached to 32.9% in 1820 (the last year
of Jiaqing era of Qing dynasty). After the Opium War in 1840, the national strength
of Qing dynasty was declining day by day. It was only in 1913 that China’s share of
world GDP had fallen to 8.9%. At that time, American GPD share was 19.1% which
was more than twice of China’s share.
In 1961, China’s GDP accounted for 3.49% of the total world GDP, while Japan
overtook China and accounting for 3.77% of the world’s total. In 2009, China’s GDP
accounted for 8.46% of the world’s total, surpassing Japan’s GDP.
The variation in the GDP per capita of China, the United States, and the world
from A.D. 1 to 1820 is shown in Fig. 4.5. In the period of A.D. 1 to 1700, China [just
mentioned this in previous para.] and the GDP per capita was equal to or slightly
4 Development of World IC Industry 49

Fig. 4.3 The GDP growth rate for regions of world in 2021

Fig. 4.4 The proportional variations of China, America, and Japan to total world GDP from the
first year AD to 2019. (Data source: Millennium History of the World Economy, By Angus Madison,
translated by Xiao-ying Wu; World Bank)

higher than the world GDP per capita. However, after 1700, China’s GDP had failed to
keep pace with the industrial revolution; therefore, GDP per capita of China began to
gradually fall below the world average. Meanwhile, Europe and the United States relied
on the power of industrial revolution to achieve a rapid growth in GDP per capita.
50 D.-K. Mo and K. Li

Fig. 4.5 The variation in GDP per capita of China, America, and world from the first year AD to
1820. (Data source: Millennium History of the World Economy, By Angus Madison, translated by
Xiao-ying Wu)

Fig. 4.6 The variation in GDP per capita of China, the United States, and the world from 1960 to
2019. (Data source: World Bank)

Additionally, the variation in the GDP per capita of China, the United States, and
the world from 1960 to 2019 is also presented in Fig. 4.6. China’s GDP per capita
maintained a slow growth from 1960 to the end of the twentieth century. However,
the total amount of GDP rapidly increased since the beginning of the twenty-first
century, and the GDP per capita also started to increase annually, reaching
4 Development of World IC Industry 51

$10,261.68 USD in 2019. In any case, it was still slightly below the world GDP per
capita of $11,441.73 USD, compared with $65,297.52 USD in the United States.

IC Supply Chain

The composition of the semiconductor industrial chain (including ICs and discrete
devices) is presented in Fig. 4.7. The main enterprises facing the market directly are
fabless design enterprises (no production line), integrated device manufacturers
(IDM), and intellectual property (IP) circuit module vendors. Additionally, EDA
enterprises, which primarily provide design methodologies and tool suites, can not to
provide chip fabrication services. Thus, they are usually entrusted to contracts only.
The wafer foundry (or Foundry, Fab) provides IC fabrication services. IPs are
commonly provided as process-proven and can be embedded in a chip or well-
designed modules. Furthermore, IP modules are classified into three types: soft core,
firm core, and hard core. IP providers include chip design companies, foundry Fabs,
EDA enterprises (e.g., Synopsys), professional IP companies (e.g., ARM), and
design services companies. Furthermore, packaging and testing companies do not
have their own products and mainly provide services for foundry Fabs and IDM
companies. Materials companies and specialty equipment companies mainly provide
the required materials and equipment to chip manufacturers, respectively.
The much broader concept of the industrial chain should also include Industry
Associations, Intermediary Service Agencies, Venture Capitals, Market Research
Institutions, Talent Training Centers, etc. The development of IC technology orig-
inates from the progress of each link in the IC industry chain. The value created by
each industrial link constitutes the overall contribution of the IC industry to society.
As the base for talent training and basic research, fundamental and theoretical

Fig. 4.7 The composition of semiconductor industry chain

52 D.-K. Mo and K. Li

research conducted by universities and research institutes is also an important link in

the construction of the IC Industry chain. The ideas of technological innovation
often create a revolutionary impact on the progresses of technology, such as the
invention of Fin Field-Effect Transistor (FinFET). The main products manufactured
with semiconductor technology are integrated circuits (accounting for about 82–87%
of the total semiconductor market) and semiconductor discrete devices. Furthermore,
the main IC products include application specific standard products (ASSPs), micro-
processor units (MCUs), memory devices, applications-specific ICs (ASIC), analog
circuits, and general logic circuits, while the main products of semiconductor
discrete devices include diodes, triode tubes, power devices, high voltage devices,
and microwave devices. These discrete devices, optoelectronics, and sensors are
listed as DOS product sector.

Wafer Foundry

The original meaning of foundry is a casting plant or a casting factory. TSMC

(Taiwan Semiconductor Manufacturing Co.) pioneered the new business model of
entrusting contracts to fabricate integrated circuits for customers in 1987. At this
time, the industry used the term “foundry” to represent the IC foundry fabs. In the
1980s, a new business model emerged in the IC industry. That is, from the traditional
IDM model of the past to the evolution of today, IC design, IC manufacture, and IC
packaging and testing relatively are independent models. Foundries only provided
the service of IC manufacturing, not their own IC design and product development.
Later, the foundry business model took two different forms. One was the pure
foundry factory, and the other one was the IDM, which provided some surplus
capacity as foundry service. In general, the main clients of foundry fabs were IC
design companies.
China Taiwan was the birthplace to initiate the semiconductor foundry industry,
and TSMC was the most important foundry enterprise in the world. However, due to
two issues, the foundry model had not been favored by other manufacturers in the
world for a long period of time. The first issue was that the previous technology level
of foundry was at least 1–2 generations behind IDMs; thus the foundry could only
supply a capacity deficiency for IDMs when their capacity was in short. The second
issue was that the IDMs of global semiconductor industries could only provide IC
products for computers, while fabless enterprises had not yet developed
substantially.
One milestone after another for the global foundry industry started in the begin-
ning of the twenty-first century. On the one hand, the applications of the Internet
have promoted a faster updating cycle for terminal electronic products. On the other
hand, due to the rapid improvement of technology and the substantial increase of
plant construction costs, objectively, there is an urgent demand of foundry services to
reduce the development cost of IC products in the semiconductor industry. At the
same time, the technological capability of foundry enterprises such as TSMC, etc.,
has also been greatly improved to meet the requirement of advanced process
4 Development of World IC Industry 53

technology. As of 2022, TSMC has provided the foundry services for 5 nm, 4 nm,
and 3nm technology nodes. This technical achievement has surpassed the IDM giant
Intel currently. In addition, the gradually matured industry of intellectual property
(IP) companies has joined the development of foundry services. All these factors
have led to the rapid growth of global semiconductor foundry industry.
Presently, the smartphone and computer markets are gradually becoming satu-
rated. Additionally, the products of the new application market driving the rapid
growth of semiconductor industry have not yet appeared. The whole IC industry
needs more R&D for the development of advanced technology up to 3 nm and
below. Therefore, the growth of the global semiconductor industry may start to slow
down. Under this new situation, how to deal with this negative trend and maintain a
relatively higher growth rate than that of the whole industry has become a common
issue for both fabless enterprises and foundry enterprises. The revenue of major
global foundry enterprises in 2019 is shown in Table 4.1. The capacity of global
wafer foundry enterprises in 2016–2021 is shown in Table 4.2.
According to Trend Force, TSMC took 53.6% of the foundry market share in the
first quarter of year 2022. Samsung, ranked second, was the only company to see its
market share decline. In addition, the total foundry market share of mainland chip
companies, including SMIC, Huahong, and Hefei Wafer Integration, exceeded 10%
for the first time.

Evolution of IC Industrial Structure

From 1960 to 1967, all manufacturers producing and applying ICs were electronic
system manufacturers (e.g., TI, Fairchild, HP, etc.). At that time, the fabrication of
ICs had not really formed a separate industry yet. System manufacturers not only
produced ICs for their own internal supporting devices, but also provided some
products to the IC market and procured some products from the IC market.
Intel and AMD were founded one after another in 1968 and 1969, respectively.
They created a new era in the global IC industry. Instead of electronic system
companies, they acted as pioneers to supply general-purpose IC products only
(neither manufacturing systems nor procuring IC products from the market). The
kind of IC manufacturers that design, process, package, and test with their own
production lines and then sell final chips by themselves are called Integrated Device
Manufacturers (IDM). By 1990, the sales amount of IDM accounted for about 80%
of the world IC market.
As the integration of ICs was still in the period of small-scale integration (SSI)
and medium-scale integration (MSI), the technical content of IC packaging was
lower than that of process and design, and the investment of packaging equipment
was also lower than that of process equipment. From the viewpoint of efficiency and
benefit, some systems manufacturers of IC began to outsource the packaging, testing
and other post-processing work, etc., or transfer factories that were engaged in IC
packaging and testing to developing countries. In 1961, Fairchild Semiconductor
 54

Table 4.1 2019 world sales of main wafer foundries

2018 sales 2019 sales
2019 list 2018 list Company Fab types Head quarter (million USD) 2018 growth rate (million USD) 2019 growth rate
1 1 TSMC Pure foundry China Taiwan 34,196 6.5% 33,983
1.2%
2 4 Samsung IDM Korea 4634 4.6% 12,380
0.7%
3 2 GF Pure foundry USA 6176 0.0% 5639
9.1%
4 3 UMC Pure foundry China Taiwan 5009 1.3% 4758
6.2%
5 5 SMIC Pure foundry China 3360 8.4% 3116
7.2%
6 8 Tower Jazz Pure foundry Israel 1304
6.0% 1242
4.8%
7 7 Shanghai Huahong Pure foundry China 1610 13.5% 933 0.2%
8 9 VIS Pure foundry China Taiwan 961 17.8% 893
6.7%
9 6 PSC Pure foundry China Taiwan 1659 8.9% 907
28.6%
10 10 DongBu Pure foundry Korea 607 1.0% 579
3.3%
The sum of the top 10 59,520 5.3% 64,430
3.2%
Top 10 total market share 92.7% – 92.6% –
Sum of other wafer factories 4922 4.9% 5143 4.5%
Total wafer factory sum 64,216 4.5% 69,573 8.3%
D.-K. Mo and K. Li
 4

Table 4.2 World foundries capacity from 2016 to 2019 (200 mm wafer equivalent)
2019 2016/million 2017/million 2017 growth 2018/million 2018 growth 2019/million 2019 growth
list Company wafers wafers rate wafers rate wafers rate
1 TSMC 21.61 23.51 8.78% 24.19 2.90% 22.88
5.42%
2 UMC 5.44 6.13 12.59% 6.15 0.41% 5.92
3.74%
Development of World IC Industry

3 GF 6.17 6.84 10.79% 7.11 3.96% 7.16 0.73%

4 SMIC 3.96 4.31 8.89% 4.88 13.11% 5.04 3.28%
Main foundries 37.18 40.78 9.69% 42.33 3.78% 41.00
3.14%
wafer total
2021 rank 2020 rank Company 2020 capacity 2020 share % 2021 capacity 2021 share %
1 1 Samsung 3.364 17% 4.050 19%
2 2 TSMC 2.647 13% 2.803 13%
3 3 Micron 1.931 10% 2.054 10%
4 4 SK Hynix 1.881 10% 1.982 9%
5 5 Kioxia/WD 1.283 7% 1.328 6%
TOTAL 11.104 56% 12.217 57%
55
56 D.-K. Mo and K. Li

invested and set up an IC packaging plant in Hong Kong, China. By 1978, 80% of
ICs manufactured in the United States had been shipped overseas for packaging [1].
Due to the progress and popularization of computer technology, the design of ICs
had entered the computer-aided design (CAD) stage from the original manual design
style. The emergence of CAD tools greatly improved the efficiency and successful
rate in IC design, and also provided the initial capability to quickly match the market
demands. In the 1970s, a group of EDA tool manufacturers represented by CV
(Computer Vision), Applicant, ECAD, Daisy, and Valid emerged one after another.
Mentor and Cadence were founded in 1981 and 1983, respectively. CAD tools or
companies providing IC design solutions came to be known as EDA tools or
companies.
Intel introduced the 386 micro-processor in 1983, and its senior managers found
that the total investment cost of 386 chips was $100 million USD, while that of
286 chips was $50 million USD. In other words, “the value added by IC design has
exceeded the value created by IC manufacturing.” Therefore, when others realized
this, the separation of IC design from IDM became a natural necessity.
Since 1983, many new enterprises like Altera, Syntek, Cirrus Logic, Xilinx,
Qualcomm, and ATI have been born. These IC design companies had no IC
manufacturing lines and were known as fabless in the IC industry. Additionally, IP
vendors that did not manufacture any IC products are known as chipless companies.
ARM (Advanced RISC Machines) was founded in 1990 as the first IP provider.
ARM6, the first embeddable RISC core, was introduced in 1991.
In January of 1987, TSMC was established. This company has created a new IC
production model focusing on IC manufacturing services only. Because the com-
pany did not have its own products, it only provides wafer foundry services, so it is
also called “foundry.”
According to the statistics data from IC Insights, in 2020 the total sales amount of
the top 10 IDM enterprises was $257.4 billion USD. These IDM enterprises still
dominated the IC market. The total sales amount of fabless enterprises and foundry
enterprises is $127.9 billion USD and $82 billion USD, respectively. The evolutional
stages of global IC industry are shown in Fig. 4.8. In terms of company headquarters
location, Fig. 4.9 shows the total global share of IC market, as well as the market
share of IC sales of IDMs and fabless companies. Pure foundry players are not
included in this data. By 2021, the global market shares of IDMs, fabless companies,
and total IC sales volume are still led by US-based companies. Since 1990 the
market share of both Japanese companies and European companies has gradually
declined to only 6%. At present, Chinese companies (excluding foundry fabs) hold
only 4% of global IC market share by 2021. Additionally, in 2022, the Semicon-
ductor Industry Association of the United States (SIA) also predicted that the market
share of mainland companies (including IC design enterprises, IDMs, foundries, and
testing and packaging plants) in the global semiconductor market will grow from 9%
in 2020 to 17% in 2024, while the market share of South Korean companies will
remain around 20% in the next 3 years. From the perspective of IC demand, China is
planning to boost its own semiconductor production which is aiming to be more self-
reliant, and increase the global market share of Chinese companies by 2035.
4 Development of World IC Industry 57

Fig. 4.8 Evolution of world IC industry

Revenue Change of the Top 10 World’s Semiconductor

Companies (1985–2021)

The progress of the global semiconductor industry mainly relies on two wheels.
First, it relies on the progress of the shrinkage of technology process node. With the
development of advanced technologies, the critical dimension (CD) of IC scales
down by a factor of 0.7 every 1.5–2 years. The shrinkage ratio has been maintained
all the way up to 14 nm in 2015, 10 nm in 2017, 7 nm in 2019, 5 nm in 2020, and
3 nm technology in 2022. Based on experience, the 2 nm and below technologies are
also possible in the near future. Secondly, it relies on pushing the progress to increase
the wafer size. From 400 (inch) wafer in the 1980s, 150 mm wafer in the early 1990s,
200 mm wafer in the late 1990s, and 300 mm wafer in 2002, it is clear that 300 mm
wafer size still play a major role in today’s IC product lines. At present, the
technology of 450 mm wafer is feasible. However, the R&D and mass production
of 450 mm silicon wafer technology are at a standstill because of the economic
58 D.-K. Mo and K. Li

Fig. 4.9 Worldwide IC company market share by headquarters location in 2021

reasons. It is apparent that the continuous scaling down of technology nodes is the
primary factor to accelerate the growth of IC industry.
The market of terminal electronic products is the main driving force to promote
the industrial progress. As shown in Fig. 4.10, it was figuratively likened to an
inverted triangle before, in which the global electronic product market is at the
bottom side, which then determines the size of the global semiconductor industry,
the corresponding semiconductor equipment, and semiconductor materials market.
Driven by technology and applications of terminal electronic products, the
growth performance of the global semiconductor industry is variable, with the
ranking of the top 10 constantly changing. In the 1980s, Japan’s semiconductor
companies such as NEC, Hitachi, Toshiba, and Fujitsu occupied 50% global market
share, and the success of Japan’s memory IC products was more obvious. However,
in early years of the twenty-first century, South Korea’s Samsung and Hynix also
relied on the mass production of memory ICs, and then surpassed Japanese compa-
nies. Since 1992 to 2016, Intel also successfully managed to reach No. 1 with
its CPU.
The market share is the main factor to determine the change of global ranking for
top 10 semiconductor enterprises. Intel has held the top global ranking for 25 con-
secutive years (as of 2016), but Samsung and others are catching up. The ranking
order variation of the top 10 global semiconductor manufacturers from 1985 to 2021
is listed in Table 4.3. In 1990, there were six Japanese companies ranked within top
10, indicating that Japan’s enterprises reached the top at that time. Intel took the top
spot in 1992 and kept ranked No.1 until the end 2016. Samsung Electronics followed
4 Development of World IC Industry 59

Fig. 4.10 The upstream and downstream relationship of electronic industry. (Note: 80% of the
main investment in semiconductor industry is for equipment procurement, that is, the market scale
for semiconductor equipment. (Data source: IC insights))

Intel to be ranked No.2 in 2005 and maintained its position until 2016, and then
topped the list from 2017 to 2018. However, Intel ranked as No.1 semiconductor
enterprise again in 2019 and 2020. By 2021, Samsung regains the top spot. In
addition, TSMC, led by Dr. Morris Chang, entered the top 10 list for the first time
in 2010 and still maintained a good momentum of development in the third place for
many years. Despite this, only one Japanese enterprise, Kioxia (new name of
Toshiba Memory Co.), made it into the top 10 in 2019. Nvidia of the United States
 60

Table 4.3 The ranking order variation of the top 10 global semiconductor manufacturers in the last 35 years
Ranking 1985 1990 1995 2000 2005 2010 2015 2021
1 NEC NEC Intel Intel Intel Intel Intel Samsung
2 TI Toshiba NEC Toshiba Samsung Samsung Samsung Intel
3 Motorola Hitachi Toshiba NEC TI TSMC TSMC TSMC
4 Hitachi Intel Hitachi Samsung Toshiba TI SK Hynix SK Hynix
5 Toshiba Motorola Motorola TI STMicro Toshiba Qualcomm Micron
6 Fujitsu Fujitsu Samsung Motorola Renesas Renesas Micron Qualcomm
7 Philips Mitsubishi TI ST Hynix Hynix TI Nvidia
8 Intel TI IBM Hitachi Freescale ST Toshiba Broadcom
9 National Philips Mitsubishi Infineon NXP Micron Broadcom MediaTek
10 Panasonic Panasonic HY Philips NEC Qualcomm Avago TI
Data source: IC Insights
Note: Due to the limited space, this table only shows the rank of every 5 year
D.-K. Mo and K. Li
4 Development of World IC Industry 61

and MediaTek of China Taiwan are also ranked in top 10 semiconductor companies
in 2021.

Revenue, Distribution, and Product Category of Global

Semiconductor Market (1997–2021)

According to the WSTS statistics, the global semiconductor market sizes shown in
Fig. 4.11 are $137.0 billion USD in 1997, $204.4 billion USD in 2000, $227.5
billion USD in 2005, $298.3 billion USD in 2010, $335.2 billion USD in 2015,
$468.7 billion USD in 2018, $412.1 billion USD in 2019, and 555.89 billion USD in
2021. The corresponding year-on-year growth rate in 2021 is about 26.2%. Over the
past 30 years, the average annual compound growth rate has reached 8.9%.
Changes and advances in various end electronic products have effectively pro-
moted the continuous progress of semiconductor industry, such as mainframe
computers in 1970s, personal computers in the 1980s, notebook computers in the
1990s, smartphones and tablets at the beginning of the twenty-first century, etc. Up
to now, wearable devices, smart home products, automobile electronics, etc., are
emerging.
The market share of the global semiconductor market by region from 1986 to
2019 is shown in Fig. 4.12. The chart shows the market share in the Americas,
Europe, Japan, and Asia-Pacific region (excluding Japan), respectively. In 1986,
Japan accounted for 39.7% of the global semiconductor market, making it the largest
regional market. The Americas and Europe account for 32.3% and 20.3% of the
global market, respectively, while Asia-Pacific (excluding Japan) accounts for only

Fig. 4.11 Global semiconductor market (1997–2021). (Data source: WSTS)

62 D.-K. Mo and K. Li

Fig. 4.12 Global semiconductor market share by regions (1991–2019). (Data source: WSTS)

7.8% of the global market. However, Japan’s market share in 1986–2000 shows a
significant downward trend. In 2000, Japan’s share of the global market fell to 22.9%
with a reduced amount of 16.8% comparing to that in 1986. At the same time, the
market share in the Americas and Europe is relatively stable. In 2000, the Americas
and Europe accounted for 31.3% and 20.7% of the global market, respectively,
virtually unchanged from 1986. In addition, Asia-Pacific regional market (except
Japan) has maintained a rapid development to get 25.1% global market share in 2000
and became the world’s second largest regional market only after the Americas.
Since the beginning of the twenty-first century, the Asia-Pacific market (excluding
Japan) has continuously maintained rapid growth, while the market share of the
Americas, Europe, and Japan has shown a declining trend. As of 2019, the Asia-
Pacific market (excluding Japan) has already accounted for 63% of the global
market, while the Americas market accounted for 19% of the global market.
However, Europe and Japanese markets both fell below 10% of the global market
share. In 2021, US President Joe Biden declares to increase the US market share in
the semiconductor field and regain the global leadership in the semiconductor
industry. The European Union also announces that it will increase the European
market share to 20% in the semiconductor industry. By 2030, a new round of global
semiconductor industry landscape will gradually change.
The product structure of the global semiconductor market from 2006 to 2019 is
shown in Fig. 4.13. In 2006, the market size of discrete semiconductor devices was
about $16.61billion USD, accounting for about 8% of the semiconductor market. By
2019, the market size of discrete semiconductor devices grew to $23.88 billion USD,
and its share in the semiconductor market dropped to 5.7%. In 2006, the market size
of optoelectronic devices was about $16.29 billion USD, accounting for about 6.6%
of the semiconductor market. By 2019, the market size of optoelectronic devices has
reached 41.56 billion USD, accounting for 10.1% of the semiconductor market. In
4 Development of World IC Industry 63

Fig. 4.13 Global semiconductor market share by product sections (2006–2019). (Data source:
WSTS)

2006, the size of the sensor market was about $5.35 billion USD, accounting for
about 2.2% of the semiconductor market. By 2019, the sensor market reached
$13.51 billion USD, accounting for 3.3% of the semiconductor market. In 2006,
the integrated circuit market size was about $209.74 billion USD, accounting for
84.6% of the semiconductor market size. By 2019, the market size of integrated
circuits reached $333.15 billion USD; however, the market share was slightly
dropped to 80.8%.
Analog ICs, MCU, logic ICs, and memory ICs are four main products in the
category of integrated circuits. Figure 4.14 shows the product structure of the global
IC market from 2004 to 2019. In 2006, the market size of analog ICs was about
$36.94 billion USD, accounting for 18% of the integrated circuit market. By 2019,
the market size of analog circuit was up to $53.90 billion USD, accounting for 16%
of the integrated circuit market. In 2006, the market size of MCU ICs was about
$53.94 billion USD, accounting for 26% of the IC market. By 2019, the market size
was $66.43 billion USD, still accounting for 26% of the IC market. For logic ICs, the
market size in 2006 was about $60.16 billion USD, accounting for 29% of the IC
market; the market size then raised to $106.38 billion USD with a 32% market share
in 2019. Memory ICs in 2006 occupied a market size of $58.47 billion USD with a
28% market share, and its size had reached to $106.43 billion USD with a 32%
market share in 2019. Additionally, because of the rapid development of CMOS
technology, the market share of bipolar process products has declined rapidly and
now accounts for less than 1% of the global semiconductor market size. Therefore,
after 2004, WSTS no longer listed bipolar IC products as a separate item in the
category of IC. Bipolar technology-related products are included in the above four
categories of products.
64 D.-K. Mo and K. Li

Fig. 4.14 Global semiconductor market share by IC product sections (2006–2019). (Data source:
WSTS)

World Semiconductor Council (WSC)

The World Semiconductor Council (WSC) is an international non-governmental

organization for the global semiconductor industry. It was established on Aug.
2, 1996. Due to the continuous trade disputes between the United States and Japan
in the semiconductor industry, the Semiconductor Industry Association of the United
States and the Electronics Industry Association of Japan initiated and established the
WSC with their respective government support. WSC played a role as a negotiation
platform for the semiconductor industry and a competent group to discuss issues
related with trade disputes, intellectual property rights, electronic transactions,
environmental safety, etc., before these issues were appealed to the World Trade
Organization (WTO) and the World Customs Organization (WCO). Additionally, the
WSC will provide the WTO with the expertise of the semiconductor industry. In
April of 1997, the European electronic components association and Korea Semicon-
ductor association joined the WSC. The United States, Japan, Europe, and South
Korea became initial founding members.
On June 15, 2006, after 5 years of repeated negotiations and discussions on the
basis of “one-China principle,” Mr. Zhongyu Yu, chairman of the board of directors
of China Semiconductor Industry Association (CSIA), on behalf of CSIA, signed the
“Memorandum of China Semiconductor Industry Association joining the World
Semiconductor Council” with Mr. Brian Halla, the rotating chairman of WSC and
4 Development of World IC Industry 65

the president of the Semiconductor Industry Association of America (SIA) in 2006.

Later, CSIA officially joined WSC. Additionally, the Semiconductor Industry Asso-
ciation in Chinese Taipei (TSIA) had joined the WSC in 1999.
The current members of WSC are the China Semiconductor Industry Association
(CSIA), Semiconductor Industry Association in Chinese Taipei (TSIA), Semicon-
ductor Industry Association in Europe (ESIA), Semiconductor Industry Association
in Japan (JSIA), Semiconductor Industry Association in Kores (KSIA), and Semi-
conductor Industry Association in the United States (SIA).
The semiconductor industries of these six WSC member countries and regions
represent the economic scale and development level of the global semiconductor
industry. They own more than 90% of the global semiconductor industry share. The
WSC platform provides a global authority on the achieved consistent agreements
that related with world semiconductor industry market data, industrial policy, intel-
lectual property rights, global trade, and other related issues. Thus, the WSC can
provide professional advice pertaining to the semiconductor industry for WTO
and WCO.
The WSC holds three meetings every year: the Joint Steering Technology Com-
mittee (JSTC), whose main attendants are the staffs of secretariat in each semicon-
ductor association; the WSC council, whose main participants are CEOs and
chairmen of various semiconductor companies; the Government/Authorities Meet-
ing on Semiconductors (GAMS) whose main participants are officials in charge of
semiconductor affairs in government/authority of a country/region. The JSTC gen-
erally meets in February every year, the WSC council meets in May every year, and
the GAMS regularly meets in October every year.
The GAMS conferences mostly focus on issues affecting the semiconductor
industry and reach consensus on these issues. Moreover, GAMS receives and
discusses reports as well as recommendations on policy issues from the industry.
The joint statement of GAMS mentions that the parties have achieved virtually
barrier-free trade with each other in semiconductors, including the elimination of
tariffs. They also jointly seek to a global barrier-free trade and investment environ-
ment to support and coordinate the recommendations of the World Trade Organiza-
tion (WTO) – including the information technology agreement (ITA). Meanwhile,
policies adopted by all parties in protecting intellectual property, carrying out basic
scientific research, and protecting global environmental with positive ways are
conducive to the sustainable economy growth. In addition, more people will con-
tinue to benefit from the information age. These policies will increase the global
demand for semiconductors.
The chairmanship of GAMS rotates among the founding members for a 12-month
term. The chairman will draft the conference resolution and conclude the annual
meeting’s summary with reference to the WSC’s recommendations and the previous
GAMS resolutions. In addition, with the agreement of each member country, the
chair country may also organize symposiums to discuss the specific issues affecting
the semiconductor industry. In recent years, the GAMS has hosted several related
workshops, including policy discussions on encryption products and discussions on
semiconductor stimulus policies in various regions, etc.
66 D.-K. Mo and K. Li

In recent years, several GAMS meetings have made significant progress on many
key trade policy measures. For example, to get unanimity on agreements of duty
exemptions for next generation semiconductors (hereinafter referred to as multi-
component semiconductor, MCO) applied in a wider information technology, to take
ban policy restricting the use of encryption technology, to establish fair and open
rules to support for local government projects, to ratify agreements of trade facili-
tation for WTO to simplify semiconductor trading processes, to protect intellectual
property rights, to ban counterfeit semiconductor products from entering the market,
and to protect the environment.
Since joining WSC in 2006, CSIA has organized industry leaders, professionals,
and lawyers to participate in various activities of WSC Joint Steering Technology
Committee (JSTC), WSC Council, and Government/Authority Meeting on Semi-
conductors (GAMS). They also participate in the discussion of various working
groups and raise relevant issues. Furthermore, CSIA expresses clear opinions on
issues about the rules for country of origin, intellectual property rights, environmen-
tal safety and health (ESH), multicomponent semiconductor (MCO) and/or inte-
grated circuits, and the product range of transducers, so as to strive for discourse
power for China’s industrial development. It has effectively promoted the develop-
ment of China’s semiconductor industry.

Semiconductor Equipment and Materials International

Semiconductor Equipment and Materials International (SEMI) is a global organiza-

tion of industry association. It is dedicated to promoting the overall development of
supply chain system in the industries of microelectronics, panel displays, and solar
photovoltaic. Its members include manufacturing, equipment, materials, and service
companies in the supply chain system of the above industry. Since 1970, SEMI has
been dedicated to assisting member companies in getting market information
quickly, increasing profitability, creating new markets, and overcoming technical
challenges. SEMI has 14 offices around the world. They are based in China
(Shanghai, Beijing, Hsinchu), Japan (Tokyo), South Korea (Seoul), Singapore,
India (Bangalore), Belgium (Brussels), Germany (Berlin), France (Grenoble),
Russia (Moscow), and the United States (San Jose, Austin, Washington). The
main activities of SEMI include organizing conferences and exhibitions, promoting
international standards, developing public policies, conducting market research, as
well as advocating industry environment, health, and safety issues.
By 1970, the semiconductor industry has built up the momentum of development
for at least 10 years. At that time, the global revenues were only a few million
dollars. However, this industry has brought together many visionary leaders to create
a focused forum for suppliers of semiconductor equipment and materials. This
organization is SEMI, and this is how SEMI is formed.
The biggest contribution of SEMI to the semiconductor industry is to hold the
Semicon Equipment and Materials Exhibition annually in the United States, Japan,
South Korea, China, and other places. It brings the world’s latest products of
4 Development of World IC Industry 67

semiconductor equipment and materials, including technology to industry. At the

same time, various SEMI standard meetings are held too.
SEMI can provide customers with information that including monthly orders/
sales (i.e., Book-to-Bill ratio, B/B) of semiconductor equipment, a monthly or
3-month moving average value of equipment sales, the annual ranking of the top
10 semiconductor equipment suppliers worldwide, the revenue of semiconductor
front-end materials, the revenue of semiconductor back-end materials, and the
statistics of global IC foundry production line number.
SEMI has reinvested the proceeds from the exhibition to its business and
published the SEMI standards plan. SEMI has more than 30 years of history from
its earliest success in standardizing the specification of silicon wafers, devoting to
factory automation and software, to promoting market competition and reducing
semiconductor manufacturing costs. SEMI standards have also promoted the devel-
opment of new industries, including current wafer foundry models.
As the industry has grown, SEMI has developed more products and services for
its members, such as technology seminars, education and training activities, and
market data collection and analysis. SEMI speaks for the industry and represents the
common interests of its members. It concerns public policy, the environment, health,
safety, human resources, and investor relations. Therefore, SEMI contributes to the
development of semiconductor industry.

Global Semiconductor Alliance (GSA)

The Global Semiconductor Alliance (GSA) was renamed from the Fabless Semi-
conductor Association (FSA) in 2007. The FSA was established in 1994. In the
1990s, the global semiconductor industry began to evolve from the former IDM
model to the development of individual design, manufacturing, as well as packaging
and testing, respectively. The purpose to set up FSA was to provide a platform for IC
design companies and their cooperation partners, such as wafer foundries and
package-testing plants, to further create a more beneficial environment for industrial
innovation. With the growing industry, the FSA changed its name to GSA in 2007.
Currently, the GSA members from 30 countries and regions around the world
have covered more than 350 companies throughout the entire supply chain.
GSA provides supports for the industry and its cooperative partners. GSA can
cope and propose solutions to various challenges that arise within the supply chain,
including IP, electronic design automation (EDA) design, wafer fabrication, testing,
and packaging. GSA actively promotes the cooperation between global semicon-
ductor companies and their cooperative partners, and also provides a globalized
communication platform. Meanwhile, GSA continues to analyze and research
opportunities in the semiconductor market to encourage and support startup entre-
preneurship. Additionally, GSA also provides comprehensive market research
reports for enterprises.
In recent years, GSA has actively promoted the development of the global
semiconductor industry and held various seminars. For example, in June 2017,
68 D.-K. Mo and K. Li

GSA successfully held the “2017 GSA Memory+ Forum” in Shanghai to discuss
how to push the current storage technologies and system architectures to the next
generation to meet the requirements for future cloud computing, mobile, and new
applications. This forum delivered insights of the current situation, development
trends, and cooperation prospects of the global memory industry. The success of
forum promotes the cooperation between Chinese enterprises and the global
semiconductor industry. In recent years, several large mergers and acquisitions
(M&A) in semiconductor industry have also been driven by the GSA.
In March of 2011, Dr. David Wang, then the president and CEO of SMIC, was
elected as the director of GSA. On May 9, 2016, Dr. Leo-Liyou Li, the chairman and
CEO of Spreadtrum Communications Inc. (new name Ziguang Zhanrui), was
appointed as the chairman of GSA board of directors. In December 2020, the GSA
BOD appointed Simon Segars, CEO of Arm, as chairman of the GSA Board of
Directors.

International Technology Roadmap for Semiconductors

The International Technology Roadmap for Semiconductors (ITRS) publishes a set

of documents jointly completed by experts from the Semiconductor Industry Asso-
ciation of the United States (SIA), the Semiconductor Industry Association of
Europe (ESIA), the Semiconductor Industry Association of Japan (JSIA), the Semi-
conductor Industry Association of Korea (KSIA), and the Semiconductor Industry
Association of China Taipei (TSIA). This set of documents is intended for technical
evaluation only and has no commercial tendency to any independent products and
equipment. The purpose of ITRS is to ensure the performance improvement of ICs,
while trying to achieve higher cost efficiency for the use of IC products and
applications, so that the overall industry can maintain a sustained healthy and
successful development [2].
The fabrication of ICs or any semiconductor devices requires a series of process
steps, including lithography, etching, and deposition. In the early stage of indus-
trial development, most IDM companies used their own developed process equip-
ment to fabricate IC products. However, with the continuous development of
technology and the ongoing expansion of the industrial scale, the business model
for an IDM company to invest tremendous R&D budgets for self-use production
lines becomes unsustainable. Consequently, equipment manufacturing depart-
ments and material supplying departments are gradually spun off from IDM
companies to form independent external suppliers. Therefore, the industry urgently
needs a clear development roadmap for products, markets, and technologies to
guide each manufacturer’s product and R&D plans. The SIA was the first to do that.
It led and coordinated major manufacturers to develop the US version of the
technology roadmap, namely, the National Semiconductor Technology Roadmap
for Semiconductors (NTRS).
4 Development of World IC Industry 69

In 1998, SIA cooperated with ESIA, JSIA, KSIA, and TSIA to release the first
international roadmap, which was the first version of the International Technology
Roadmap for Semiconductors. It is expected to continuously update contents and
publish a new complete version in odd-numbered years [2].
The International Semiconductor Roadmap Committee (IRC) is responsible for
overall coordination of ITRS, hosting and conducting ITRS workshops, and editing
and publishing ITRS reports. Two to four members from Europe, Japan, Korea,
China Taipei, and the United States, each group has 2–4 members to represent an
individual region in IRC to collect information.
The technology section of ITRS is edited by the International Technical Working
Groups (ITWG). The International Technical Working Groups are divided into a
focus group and a lateral working group [3]. There are 17 ITWG to edit the ITRS of
2013 version, including system drivers, design, testing and test equipment, process
integration, devices and structures, RF and analog/mixed signal technology for
wireless communication, new devices research, front-end processes, photolithogra-
phy, interconnection, factory integration, packaging and assembly, micro-electro-
mechanical systems (MEMS), new emerging materials research, environment, safety
and health, yield improvement, metering, modeling, and simulation, respectively [3].
With the popularization of the Internet and the development of Internet of Things
(IoT), the IRC was launched in 2012, and then the reorganization of ITRS to ITWG
was completed in 2014. The original 17 working groups were reorganized into seven
working groups in 2015. Specifically, there are System Integration, Heterogeneous
Integration, Heterogeneous Components, External System Interconnection, More
Moore, Beyond CMOS, and Factory Integration [1]. The new roadmap is called as
the ITRS 2.0.
As the industry generally believed that Moore’s law was reaching its limits, the
final version of ITRS was released in 2016. Then a much broader roadmap named as
the International Roadmap for Devices and Systems (IRDS), which was created
through the IEEE’s initial plan for “restart computing,” will serve as a roadmap.
IRDS will be the continuation of ITRS [3].

Worldwide Major Institutions of IC Research and Development

Integrated circuit industry is a typical knowledge-intensive, technology-intensive,

capital-intensive, and talent-intensive high-tech industry, which requires enterprises
not only to have strong economic strength, but also to have a profound foundation of
technologies and talents. For the purpose to promote the overall healthy develop-
ment of the IC industry, each country continues to establish R&D institutes and
public service platforms to carry out industrial generic technology and key technol-
ogy research, assist IC enterprises to breakthrough technology bottlenecks encoun-
tered in development, and continue to cultivate talents with theoretical capability and
practical experiences for the industry. There are several successful examples for IC
research and development described below.
70 D.-K. Mo and K. Li

Interuniversity Microelectronics Center (IMEC)

The Belgium research center for microelectronics, also known as The Interuniversity
Microelectronics Center (IMEC), was founded in 1984. IMEC is a non-profit
microelectronics research center that mainly organizes universities and research
institutes to establish connections with industrial production. Its board of directors
consists of people from universities, governments, and industry. After more than
30 years of development, IMEC has become the largest and most active non-profit
microelectronics R&D center in the world, which continuously contributes new
technologies, new talents, and new companies to the industry.
Currently, IMEC has a high-tech R&D infrastructure including EUV lithography
equipment. It brings together more than 2500 top industry experts from 74 countries
and has established a network of cooperative partners with upstream and down-
stream links of the industrial chain such as Fabless, IDM, Foundry, semiconductor
equipment suppliers, and terminal equipment suppliers. IMEC has built an industrial
ecosystem with innovative research and development, which effectively connects
university’s technologies that have been ahead of the market for 10–15 years with
those of the industry that have been ahead of the market for 2–3 years. Meanwhile,
IMEC also supports various forms of innovation from all stages including basic
research, product development, prototype verification, small batch production, and
mass production. Meanwhile, IMEC has also built an innovation ecosystem around
the world. In addition to the Belgian headquarters, it also has established offices in
the Netherlands, the United States, China, India, Nepal, and Japan. In China, IMEC
has established talent training programs, an R&D center, and an IMEC fund.
In 2015, IMEC’s R&D expenditures reached 415 million euros and had gradually
become the global technology sources and innovation center of the “semiconductor
plus.”

Very Large-Scale Integration (VLSI) Consortium

The Very Large-Scale Integration Consortium (VLSI Consortium) was founded in

1976. It is a joint technology research and development organization promoted by
the Japanese government to develop VLSI to compete with the United States. Its
members include NEC, Toshiba, Hitachi, Fujitsu, Mitsubishi Electric, and other
large Japanese semiconductor companies. The consortium implements the manage-
ment mechanism of joint research on generic technologies and relatively indepen-
dent research and development for products. In addition, the government mainly
supports the research and development of generic and basic technologies with a
subsidy up to 50% of the total R&D expenditure. The enterprises in the consortium
can use the consortium’s patents for free. Before the launch of this consortium, more
than 80% of Japanese semiconductor manufacturing equipment was imported from
the United States, and by the mid-1980s, all semiconductor manufacturing equip-
ment was localized. The consortium also successfully developed a key equipment
for semiconductor manufacturing, that is, the projection lithography machine, which
4 Development of World IC Industry 71

laid the foundation for Japan to establish a dominant position in the entire semicon-
ductor equipment field.

Semiconductor Manufacturing Technology Research Consortium

(SEMATECH)

The Semiconductor Manufacturing Technology Research Consortium

(SEMATECH) was founded in 1987. It is an industrial alliance established by the
US government for the purpose of integrating the capitals and resources of various
enterprises, sharing R&D technology and financial risks, improving the semicon-
ductor manufacturing technology of the United States, and regaining the share of the
United States in the global semiconductor market. The successful operation of
SEMATECH resulted in a 59% reduction in research investment by member firms,
with a benefit-cost ratio of 2.8. Since its launch in 1987 to 1995, SEMATECH had
promoted American semiconductor industry back in the competitive position with
the number one rank again in the world. At the same time, it had a significant impact
on American trade policy, industrial policy, industrial institutes, national innovation
system, as well as the technological innovation theory and cooperation strategy
management. The SEMATECH ended in 2015 after the mission was accomplished.

Semiconductor Leading Edge Technologies, Inc. (SELETE)

Since Japan lost its leading position in semiconductor industry with the establish-
ment of SEMATECH in the United States, therefore, Semiconductor Leading Edge
Technologies Inc. (SELETE), a Japanese industry group, was founded in 2006. It
was a new attempt for Japanese industry to organize SELETE to regain the number
one position in the world. SELETE adopts a hierarchical organization structure.
Among the 11 team members, Fujitsu, NEC Electronics, Renesas, and Toshiba are
the core companies. Relying on their technology leadership, SELETE accelerates the
whole R&D progress and takes the lead in three advanced technologies: front-end
technology focusing on practical high-k metal gate (HKMG) materials; back-end
technology focusing on porous low-k materials; as well as lithography and masking
technology for 45 nm node, 32 nm node, and beyond. In this way, the Japanese
semiconductor industry has better integrated the strengths of industry, academia, and
the state.

Semiconductor Market Analysis

Market analysis and forecast are inseparable from the support of data, and the data in
the semiconductor industry are mainly collected and analyzed by market analysis
companies.
72 D.-K. Mo and K. Li

Because the data and their definitions of semiconductor market analysis companies
vary, such as semiconductor sales, OEM sales, Fabless sales, etc., in addition, the
sources of the data are also different; therefore, it is critical to focus on the continuity of
data provided by market analysis companies.
The world’s leading market analysis companies and institutions include WSTS,
SEMI, IC Insights, Gartner, TrendForce, IHS, iSuppli, etc. In general, market
analysis companies usually publish forecasts at the beginning or end of each year.
During the middle of the year, these forecasts will be revised several times according
to the actual conditions of the market.
For the development trend of the semiconductor industry, it is impossible to
obtain a comprehensive picture of the industry just based only on a certain data
acquisition. Therefore, it is often necessary to combine multiple data for observation.
However, to avoid the misjudgment, these data from various companies should not
be mixed. It is worth noting that the development of the semiconductor industry is
inseparable from the general situations of regional politics and economic trends,
such as the impact of the global financial crisis in 2009 and the US-China trade
conflicts starting from 2018.
Currently, due to the shortage of a large number of IC vehicle applications since
2020, the United States, the European Union, and Japan begin to plan to establish an
independent integrated circuit industry chain in their own country, which will change
the current global division of IC industrial structure. All these changes will affect the
market development of regional integrated circuit industry in the next 5–8 years.
There are certain criterions in the market forecast, e.g., the quarterly forecasts of
3 months must be very accurate, then the annual forecasts should be valuable, and
furthermore, the forecasts in the next 3 years must have good value for reference.
Some commonly used market data are listed below.

Days Sales of Inventory

Days Sales of Inventory are also called turnover days. It refers to the number of days
that starts from the inventory acquisition to consumption and sale of inventory in an
enterprise. The shorter the inventory turnover days, the faster the inventory
becomes cash.

The Annual Growth Rate of the Semiconductor Industry

The annual growth rate of the semiconductor industry (%) ¼ the growth rate of Unit
(%) þ the growth rate of ASP (%).
For example, global semiconductor industry sales reached $335.8 billion USD in
2014, an increase of 9.8% compared to 2013.
Based on the above formula, the Unit (shipment) of global semiconductor
industry in 2014 was 76.4 billion pieces, up 8.6%, and the ASP (average selling
4 Development of World IC Industry 73

price) up 1.2%. Therefore, the growth rate of global semiconductor industry in 2014
was 8.6% þ 1.2% ¼ 9.8%.

Book-to-Bill Ratio

The Book-to-Bill Ratio (B/B Ratio, B/B) is mainly used to measure the prosperity of
the semiconductor equipment industry. Usually, when the B/B ratio is less than 1, it
indicates that the equipment industry is in a downturn. If the B/B ratio is larger than
1.0, it indicates that the semiconductor equipment industry is booming.
The reason for this analysis is that the orders of semiconductor equipment are
customized according to the customer’s demands. In addition, the specifications of
each equipment are different; therefore, it is impossible to manufacture equipment in
advance and put them in warehouses for sale. Typically, the manufacturing cycle for
equipment is about 6 months. A large Book value indicates the urgent need to
expand its capacity or add new technologies to semiconductor production lines.
Therefore, the Book value is as larger as possible. Larger B/B ratio indicates that the
load on the semiconductor production line will increase in the next 6 months.
Similarly, when the industry is in a downward trend, the Book value will decrease.
Even before the shipment of equipment, the customer may request a delay in
delivery or cancel the order directly. Therefore, the industry calls the B/B ratio a
“barometer” of industrial prosperity.
In fact, the B/B ratio can be used not only in the semiconductor industry, but also
in other fields. At present, SEMI is the authority to release the B/B ratios, and it
calculates the B/B ratio of US semiconductor equipment on a monthly basis, which
reflects the prosperity of the US semiconductor industry as well as the prosperity of
global semiconductor industry.

Semiconductor Content

Semiconductor Content of the semiconductor industry can be described by a simple

definition, that is, the total value of semiconductor components in an electronic
product as a percentage of the product value. Therefore, it is a concept of average
value used to measure the future progress of semiconductor industry. The variation
of semiconductor content in electronic products from 1999 to 2021 is shown in
Fig. 4.15. It reveals that the value share of semiconductor content in electronic
systems has increased from 18.8% in 1999 to 33.2% in 2021. After entering the
twenty-first century, semiconductor components have entered thousands of house-
holds and the whole industry, such as household appliances, wear belt electronic
products, medical equipment, vehicles, industrial automation equipment, and other
related products. All these electronic products contain a large number of semicon-
ductor components. Therefore, the trend of Semiconductor Content will be further
developed with the development of the social civilization.
74 D.-K. Mo and K. Li

Fig. 4.15 The semiconductor content changes in electronic products from 1999 to 2021. (Data
sources: ST, TI, IC Insights)

World Semiconductor Trade Statistics (WSTS)

World Semiconductor Trade Statistics (WSTS) is a semiconductor industry statistics

company whose members include the major semiconductor manufacturers in the
world. WSTS’s monthly chip sales (Billing) reports have been widely adopted by the
industry. WSTS is currently recognized as one of the most important statistical
organizations for semiconductor market data. Research institutes including the
Semiconductor Industry Association (SIA) of America and many market analysis
organizations adopt WSTS’s data as the basic data to judge the chip industry and
predict the prosperity of the industry.
The WSTS office is located in Bruckm€u hl, Germany. According to the WSTS
official website, WSTS used to have 62 member companies, which accounted for
more than 75% of the global semiconductor market by sales. The market data
provided by WSTS covers a wide range with high precision and detailed contents.
WSTS collects and analyzes information from member companies to provide more
information needed by the semiconductor industry. This will not only improve the
efficiency of the entire industry but also assist to convince governments to adopt
4 Development of World IC Industry 75

strategies that support the development of the semiconductor industry. WSTS adopts
a membership system in which each member company pays a certain annual
membership fee. WSTS publishes monthly, quarterly, and annual data to member
companies. Some of these reports require additional fees, but member companies
can enjoy preferential prices. The membership fee of WSTS is based on individual
member’s revenue. According to data released by WSTS, for example, AMD’s 2011
revenue is $6.57 billion USD, and the annual membership fee is $1700 USD. WSTS
has a global semiconductor sales database available for reference which contains
sales data by month, quarter, year, and regional (the world is divided into four
regions: America, Europe, Japan, and Asia Pacific) for 30 consecutive years from
1986 to the present.
AMD announced its withdrawal from WSTS at the end of 2011, and Intel also
announced its withdrawal from WSTS in March 2012; therefore, the monthly global
chip sales statistics of WSTS will no longer include data from these two chip
vendors. Since no Chinese company has joined WSTS so far, only few references
are available to the media about China. Usually, WSTS will release two important
market data forecasts twice a year in the spring and autumn to provide regional
distribution data and product structure data of the global semiconductor market. In
addition, WSTS provides global semiconductor sales (Billing) reports, which
include the 12-month dynamic averages for the four major regions, as well as the
statistics and the forecasts data for global semiconductor sales.

Worldwide Major IC Market Research and Consulting Companies

There are several worldwide market research and consulting companies for the
integrated circuit industry including IC Insights, Gartner, TrendForce, and Yole.
Their majors are described below.

IC Insights

Founded in 1997, the company is headquartered in Scottsdale, Arizona, USA. IC

Insights is a market research firm focused on the semiconductor industry. Its analyst
team has an average of more than 30 years of industry experience. The company
provides analysis reports and information services covering integrated circuits,
photoelectric devices, sensors, and discrete devices. The most famous of these
reports was the McClean report on the IC industry published in 1998. This report
provides an overview of the current industry status from the perspective of the
impact of global macroeconomic conditions on the industry, the capital expenditure
plans of enterprises, the production capacity of wafer foundries, and details of each
product market. The McClean report also forecasts global and regional market trends
for the next 5 years, including developments in IC manufacturing and packaging
76 D.-K. Mo and K. Li

technology, market share of products, shipments, and price trends. IC Insights has
earned a good reputation for its professionalism and accuracy in forecasting data,
and the released data is often used as a reference standard for market analysis in the
IC industry.

Gartner

Founded in 1975, Gartner is headquartered in Stamford, Connecticut, USA. Gartner

is the world’s first research and consulting company in the IT field, as well as an
authority in this field. This company’s main businesses focus on research and
consulting, evaluation, and the Gartner community. The revenue in 2015 is $2.16
billion USD. Its research covers the whole range of the IT industry from the most
upstream hardware design and manufacturing to the most downstream end applica-
tions. More than 1100 professional analysts conduct research on 1304 subjects,
focusing on the business and technology issues that drive the economic develop-
ment, and serving clients in more than 90 countries. Supported by unique research
methods such as the original Hype Cycle model and a powerful industry benchmark
database, Gartner can accurately gauge the development cycle of a technology and
further make horizontal or vertical comparisons to a certain IT company. In addition,
Gartner hosts many expert conferences around the world every year, with the Gartner
Symposium being a high-profile event for the IT industry. The topics of the confer-
ences and Gartner’s forecast of future strategic technologies will serve as forward-
looking indicators for determining the development trend of the IT industry.

TrendForce

It is a professional research institute providing in-depth market analysis and indus-

trial consulting services, as well as an industrial information matching platform.
Nowadays, there are more than 500,000 registered members worldwide. These
professionals come from all major emerging industries and technology industries.
TrendForce has five main research departments – DRAMeXchange, WitsView,
LEDinside, EnergyTrend, and TRI. Research areas include DRAM, flash memory,
personal computers, smart phones, notebook computers, tablet computers, display-
related industries such as LCD TV, panel and touch screen technology, green energy-
related industries such as LED, lighting market, solar energy, electric cars and
lithium battery, semiconductor, telecommunication, intelligent appliance (IA), as
well as the regional market, such as the research on the structural trend of high-
tech industry in greater China. TrendForce [4] has a team of professional analysts
who are familiar with various industries. These analysts effectively use a variety of
research methods to combine the information of buyers and sellers with the latest
technology developing trend to provide professional consulting services.
TrendForce holds at least five international seminars in Shanghai, Guangzhou,
Shenzhen, and Taipei every year [4].
4 Development of World IC Industry 77

Yole

Founded in 1998, Yole Development Group is a market research and strategy

consulting company based on “Beyond Moore’s Law.” This company focuses on
MEMS and sensors, medical imaging technology, compound semiconductors, RF
electronics, LED displays, optoelectronics, power electronics, battery and energy
management, advanced packaging, semiconductor manufacturing, and other fields.
Yole provides market consulting, technology and strategy consulting, media ser-
vices, and financial operation services [5].

Perspectives of IC Science and Technology in Post-Moore Era

In the post-Moore era, the science and technology of IC will develop in four
directions. The first is “More Moore,” that is, the conventional CMOS will shift to
non-conventional CMOS. The half pitch of devices will continue to be scaled down,
and non-conventional device structures such as thin gate, multi-gate, and all around-
gate will be adopted. The second is “More than Moore”; devices/components with
different process and applications, such as digital circuits, analog devices, RF
devices, passive components, high voltage devices, power devices, sensors,
MEMS/NEMS, and biological chips, are integrated together through packaging
process and then combine with the non-conventional CMOS devices to form new
micro-nano systems such as SoC or SiP. The third is “Beyond Moore (or Beyond
CMOS),” that is, the basic units of ICs are quantum devices, spin devices, magnetic
flux devices, carbon nanotubes, or nanowires devices formed by bottom-up process.
The fourth is “Much Moore.” With the high overlap and integration of micro-
nanoelectronics, physics, mathematics, chemistry, biology, and computer technol-
ogy, new formed discoveries will create many new breakthroughs in science and
technology. Then this makes it possible to create a new form of information
technology and its industry, as shown in Fig. 4.16.
The main characteristic of the circuit system in the post-Moore era is the
performance per power ratio. Intel CEO Paul Otellini put forward the concept of
“performance per watt ratio” in 2005. He emphasized that “They are trying to meet
broader set of user needs. It is not just performance that matters most right now, but
performance per watt.” Academician Wang Yangyuan pointed out in his book Green
Micro/Nano Electronics that the driving force of the IC industry and the develop-
ment of science and technology in the future is to reduce the power consumption.
Technology nodes are no longer to increase the integration by reducing the critical
dimension only, but to improve the performance/power consumption ratio of
devices, circuits, and systems is the criterion.
Devices with new structures include ultra-thin body (UTB) Silicon-on-Insulator
(SOI) MOS devices, FinFETs, FD-SOI devices, planar double gate, vertical double
gate, tri-gate, Ω-gate, gate-all-around (GAA) devices, etc. Nanoelectronic devices
include carbon nanotube (CNT) devices, nanowire (NW) devices, quantum devices,
single-electron devices, spin devices, and resonant tunneling devices. Graphene
78 D.-K. Mo and K. Li

Fig. 4.16 Prospects for the development of micro-namoeiectronics

devices are also one of the carbon-based devices under investigation. At present, the
research of memory devices is developing toward the direction of charge free
memory devices. The main hotspot of research and development focuses on Ferro-
electric Random Access Memory (FeRAM), Magnetoresistive Random Access
Memory (MRAM), Phase Change Memory (PCM), metal-oxide-based Resistive
Random Access Memory (RRAM), Polymer RRAM, Polymer FeRAM, Carbon
Nanotube (CNT) Memory, Molecular memory devices, etc.
The development roadmap of the micro/nanoelectronic devices released by ITRS
in 2012 is shown in Fig. 4.17. Question marks in Fig. 4.17 indicate the prediction
result. Currently, the technology node of IC fabrication has reached 14 nm and
10 nm in 2014 and 2017, respectively. In addition, 7 nm technology and 5 nm
technology are in production in 2019 and in 2020, respectively. The 3 nm technology
is also kicked off in 2022 and 2 nm technology is to be ready in 2024–2025.
In the aspect of new device design, the main research directions are low-power
design technology, system-level design technology, and new general-purpose pro-
cessor platform technology. In terms of manufacturing process, the main research
directions are EUV lithography, computational lithography, multi-e-beam direct
write, and nano-imprint lithography (NIL).
The development direction of packaging technology is multi-functional inte-
grated system-in-package (SiP). The main technical direction is 3D packaging,
4 Development of World IC Industry 79

Fig. 4.17 The development roadmap of micron-nanoelectronic devices

including package stacking, chip stacking, TSV technology, and silicon substrate
technology. The main application fields include artificial intelligence (AI) brain,
deep neural network (DNN) processor, composite biological signal processor, quan-
tum communication technology, holographic glasses, assisted driving, large-scale
distributed e-commerce processing platform, industrial control security
platform, etc.

References
1. Y.-Y. Wang, Y.-W. Wang, The Development Road of IC Industry in Our Country (Science Press,
Beijing, 2008)
2. ITRS 2.0, www.itrs2.net/. Accessed 29 May 2023
3. IRDS Roadmap, https://irds.ieee.org/editions. Accessed 29 May 2023
4. About TrendForce, http://www.trendforce.cn/about. Accessed 29 May 2023
5. About Yole development, https://www.yolegroup.com/. Accessed 29 May 2023
Development of Regional IC Industry
5
Guoming Zhang and Ke Li

Contents
IC Industry Development in the United States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
IC Industry Development in Europe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
IC Industry Development in Japan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
IC Industry Development in South Korea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
IC Industry Development in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
IC Industry Development in Chinese Mainland . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
IC Industry Development in Chinese Taiwan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Abstract
The development of China’s IC industry began with the successful development
of the first Si-based digital IC in 1965. The period of 1965–1978 was the
beginning of China’s IC industry, to establish a number of research institutes
and semiconductor devices factories. From 1978 to 1990, it was the stage that the
IC industry introduced the foundry technology, equipment, and explored the
development roadmap. In the last decade of the twentieth century, China’s IC
industry entered a period of key construction including a 150 mm silicon-based
IC production line. Entering the twenty-first century, the industry has stepped into
a golden period of development. In order to speed up the development of its IC
industry, the state council issued “the Notice of the State Council on Printing and
Distributing the Policies for Encouraging the Development of the Software
Industry and the IC Industry”, “Notice of the State Council on Issuing Several

G. Zhang (*)
NAURA Technology Group Co., Ltd., Beijing, China
Hwatsing Technology Co. Ltd., Tianjing, China
e-mail: zhangguoming@naura.com
K. Li
Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China

© Publishing House of Electronics Industry 2024 81

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_5
82 G. Zhang and K. Li

Policies on Further Encouraging the Development of the Software and Integrated

Circuit Industries”, and “the Guidelines for National IC Industry Development”
(referred to as the Guidelines). Among the organizational efforts, the Chinese
Semiconductor Industry Association (CSIA) has played a liaison role.

Keywords
Roadmap · State council · Software industry · IC industry · Guidelines · CSIA

IC Industry Development in the United States

The United States is the birthplace of the integrated circuit industry. Jack S. Kilby of
Texas Instruments in 1958 made the first IC concept sample by using germanium
material and filed a patent application. In 1959, Robert Noyce of Fairchild Semi-
conductor proposed the “semiconductor devices-wired structure” based on silicon
material, which was soon patented, officially marking the birth of the integrated
circuit. Since the birth of IC, the United States has been in a leading position in the
global IC industry in terms of technology, scale, and industrial structure.
In the early days, the development of the American IC industry mainly relied on
government orders. Fairchild, Texas Instruments, and Motorola were important
enterprises in the early stage of the development of the American IC industry.
These companies were responsible for the development and manufacture of IC
products for the “Militia Missile”, “Apollo Guidance Computer (AGC)”, and W2F
aircraft data processor. With the support of government procurement, American IC
companies have achieved initial rapid growth.
In the meantime, the American IC industry rapidly expanded its scale with the
help of venture capitals. Five young scientists and three engineers resigned from
Shockley Semiconductor Laboratory and then founded Fairchild Semiconductor.
These eight are often referred to as the “traitorous eight,” namely, Julius Blank,
Victor Grinich, Jean Hoerni, Eugene Kleiner, Jay Last, Gordon Moore, Robert
Noyce, and Sheldon Roberts [1]. On July 18, 1968, Gordon Moore and Robert
Noyce co-founded Intel, and Andrew Grove joined Intel the same day as the third
employee. In 1969, Jerry Sanders and seven others from Fairchild co-founded AMD.
Co-founder Jack Gifford later went on to work at Intersil, a unit of General Electric,
and founded Maxim Integrated Products in 1983.
From the perspective of industrial structure, the structure of American IC enter-
prises is constantly changing with the market competition. On the one hand, the IDM
model from the initial stage of the industry has gradually shifted to the separation
model based on the industrial chain. For example, AMD has completely turned into
an integrated circuit design company after it removed its foundry business. In
addition, Qualcomm is currently the world’s largest fabless company. On the other
hand, some semiconductor companies have also become subsidiaries of enterprises
manufacturing end products, and some expanded the direction of producing end
products for whole machine systems. In addition, the processor chips of Apple’s
iPhone are developed by Apple itself, manufactured by foundry companies such as
5 Development of Regional IC Industry 83

TSMC and Samsung, and packaged and tested by ASE and other companies. That is,
Apple has created a new model of virtual IDM.
In the late 1980s, the U.S. semiconductor industry was once surpassed in size by
Japan. This was mainly because the high demand for DRAM at that time, and
American companies withdrew from the DRAM market, while Japanese companies
had an absolute market competitive position in DRAM field. In November 1989, the
U.S. Semiconductor Advisory Committee, headed by Ian M. Ross, submitted a
report of “The Strategic Industry in Crisis” to the then President of the United States,
George Bush, and proposed recommendations on the development strategy for the
U.S. semiconductor industry. George Bush adopted these recommendations and
implemented a series of measures that eventually led the United States to regain its
leading position in 1993.
In 2016, the size of the American semiconductor industry accounted for about 50%
of the global semiconductor industry. According to IC Insights data, 22 of the world’s
top 50 semiconductor suppliers are American enterprises, in which Intel, Qualcomm,
Micron, and Texas Instruments ranked among the top 10 in the world. There were
21 U.S. companies in the world’s top 50 Fabless, including Qualcomm, Apple, Avago
Technologies (Broadcom), Nvidia, AMD, Marvell, and Xilinx, etc., and 6 companies
of them are in the top 10. In addition, GlobalFoundries ranked No. 2 among the top
10 Foundry in the world, and Amkor ranked No. 2 among the global top 10 OSAT. In
2021, the United States has six companies in the world’s top 10 semiconductor
suppliers. They are Intel, Micron, Qualcomm, Nvidia, Broadcom, and TI, with Intel
ranking No.2. In addition, the American IDM and fabless enterprises own 54% of the
world’s market share. This means that American semiconductor enterprises are still
very competitive in the global semiconductor industry.

IC Industry Development in Europe

Europe is an important part of the global integrated circuit industry. Its processors,
analog circuits, power devices, and other products have strong competitiveness in
fields of industrial control, automotive electronics, smart cards, and others. Com-
pared with the United States, South Korea, Japan, and Taiwan of China, the
characteristics of European IC industry are more dispersed. Although Germany,
France, Italy, the United Kingdom, the Netherlands, Belgium, and Spain all have
certain IC strength, but due to the lack of unified resource allocation and develop-
ment capability, the overall industrial competitiveness is relatively weak.
At the end of the twentieth century and the beginning of the twenty-first century,
many well-known European IC enterprises have become independent of the entire
system manufacturers. Based on the parent system manufacturers in the relevant
industry background and customers, these European IC enterprises have strong com-
petitiveness in the market of IC products. For example, Infineon, which became
independent from Siemens AG in 1999, has inherited and continued Siemens’ business
and product lines, and is in a leading position in the fields of industry, automobile, and
smart card. Another example is NXP, spun out of Philips in 2006. It has inherited and
continued the business and product lines of Philips and maintains its leading position in
84 G. Zhang and K. Li

consumer electronics, communications, networking, smart cards, and other fields. ST

Microelectronics (STM) is an example of joint European multinational corporations.
With the headquarter in Geneva [2], STM was founded in 1987 through the merger of
SGS Micro-electronica of Italy and Thomson Semiconductors of France.
Europe’s advantages in fundamental scientific research and talent training have
laid a good foundation for the development of IC industry. Belgium’s IMEC has
made a great contribution to the technology exportation for global industry. At
present, ARM based in the United Kingdom is the world’s largest chipless integrated
circuit design house (Chipless Design House, CDH). The company’s intellectual
property (IP) rights on ARM processors are applied to almost all mobile terminal
processors. Imagination Technology’s graphics processor supports Apple’s mobile
phone with excellent performance. Also, Dialog, a German company, is the world’s
leading fabless emulator manufacturer.
In addition, Europe is highly competitive in the field of lithography equipment.
ASML’s high-end lithography tools have unique advantages in the global market. In
particular, the trend of technology node continuously keeps scaling; ASML is
leading the research and development of EUV lithography and equipment manufac-
turer in the field of lithography.
In 2016, the size of the European IC industry accounted for about 10% of the
global market, while in 2021 the share had dropped to 6%. According to IC Insights
data, five European companies were among the top 50 semiconductor companies in
2016, with Infineon, NXP, and ST Microelectronics in the top 20. Dialog was ranked
14 among the global top 50 fabless enterprises. In 2021, ASML Holdings and NXP
were listed in top 20, while Infineon and ST entered the top 30 [1]. Not a single
European Foundry or OSAT company is in the top 10 globally.

IC Industry Development in Japan

Japan is a powerful country in the global integrated circuit industry. The develop-
ment of its IC industry originated from the technology transfer of American semi-
conductor industry in the late 1960s. In 1963, NEC of Japan licensed the planar IC
technology from Fairchild Semiconductor Corporation. Under the request of Japa-
nese government, this technology license was shared with other Japanese compa-
nies; thus Mitsubishi, Kyoto Electric Appliances, and other enterprises began to
enter the semiconductor industry, which kicked off the development of the IC
industry in Japan [3]. Subsequently, the Japanese IC industry embarked on a
low-risk development path of “introduction and catch up” [1]. During this period,
the Japanese IC industry continued to import technology and patents from the United
States to enhance its manufacturing capacity. From 1976 to 1979, Japan began to
implement the VLSI alliance, which narrowed the technology gap with the United
States and established Japan’s position in the global IC industry in the 1980s. The
VLSI alliance has obtained more than 1000 patents in total. The 64 Kbit DRAM
technology was successfully developed 6 months ahead of the United States, and the
256 Kbit DRAM technology was successfully developed 1 year ahead of the United
5 Development of Regional IC Industry 85

States. At the same time, the Japanese industry adopted the model of the IC industry
development driven by civil electronic products. With the help of this model, Japan
occupied the global market with its own manufactured end products and American
IC products to create the space for the development of its own IC industry.
By the 1980s, Japanese companies had taken the lead in DRAM products. NEC,
Toshiba, and Hitachi had long been the top three semiconductor suppliers in the
world, while Intel ranked fourth place. Eventually, from 1985 to 1992, Japan
overtook the United States to become the world’s largest manufacturing country of
semiconductors. In 1989, the market share of Japanese IC products once reached
53% of the global market, far ahead of the 37% of the United States, which opened
the golden age of Japanese integrated circuit industry [3]. In 1990, six Japanese
companies were among the global top 10 semiconductor companies. They were
NEC, Toshiba, Hitachi, Fujitsu, Mitsubishi, and Panasonic. At that time, Japanese IC
products mainly relied on DRAM. However, in the mid-1990s, the United States
began to refocus on the IC industry. Furthermore, the development of new emerging
applications such as personal computers and mobile communication products, etc.,
and the rapid rise of DRAM industry in South Korea and Taiwan, the proportion of
Japanese IC industry in the global market size has begun to decline. By 2012, the
only remaining Japanese DRAM company, Elpida, had been acquired by Micron
Technology while its technology was still at the forefront.
The technology in the Japanese IC industry remains strong and influential despite
its declining proportion in global IC market share. In terms of products, Renesas was
the world’s largest MCU supplier in 2015. Toshiba is the world’s second large
NAND Flash supplier, and SONY is the world’s largest supplier of CMOS Image
Sensors (CIS). Meanwhile, Hitachi, Renesas, Toshiba, Mitsubishi, and Fujitsu are
the world’s largest suppliers of power devices. In terms of semiconductor materials,
Japan produces more than 50% of the world’s semiconductor materials. Shin-Etsu
Chemical is an important silicon wafer supplier worldwide. Toppan Printing is the
largest photomask supplier in the world. In terms of semiconductor equipment,
Japan has five companies among the global top 10 semiconductor equipment
manufacturers. They are Tokyo Electron, DNS, Advantest, Hitachi, and Nikon. In
2016, Japanese IC industry accounted for about 11% of the global semiconductor
market, and in 2021 the share was 6%. According to IC Insights data, eight Japanese
companies were among the world’s top 50 semiconductor companies in 2016.
However, Toshiba was the only Japanese company in the global top 10 semiconduc-
tor companies. MegaChips of Japan was ranked 25th among the top 50 fabless
enterprises in the world. None of the world’s top 10 foundry FABs or OSAT
companies are Japanese. In 2021, Tokyo Electron was ranked number 14.

IC Industry Development in South Korea

South Korea is a leading country in the global IC industry, with the semiconductor
industry accounting for 5% of the national GDP. At present, there are more than
20,000 enterprises supporting its semiconductor industry. The South Korean IC
86 G. Zhang and K. Li

industry originated in the 1960s, when US semiconductor companies moved their

packaging capacity to South Korea. Starting in 1966, American companies such as
Fairchild, Motorola, and Signetics had begun to use South Korea’s low-cost advan-
tages to invest in setting up packaging or assembly plants in South Korea to transfer
related production capacity. Subsequently, local South Korean companies
represented by Nanya, LG, and Hyundai also began to enter the semiconductor
packaging and testing segment. Meanwhile, based on the normalization of diplo-
matic relations between Japan and South Korea, Japanese semiconductor manufac-
turers represented by Toshiba also began to invest and build factories in South
Korea. The above laid the foundation for the development of the South Korean IC
industry [4].
In 1973, South Korea established the National Science and Technology Commis-
sion. In 1975, the Korean government formulated a 6-year plan to promote the
development of the semiconductor industry and established the Korea Advanced
Institute of Science and Technology (KAIST). In 1976, South Korea then established
the Korea Institute of Electronics Technology (KIST) to conduct the research on
VLSI. In 1974, Korean American expert Kang Ki-Dong founded the first Korean
semiconductor company, Korea Semiconductor Corporation (later acquired by
Samsung), which marked the country’s own semiconductor manufacturing com-
pany. By the end of the 1970s, South Korea had acquired the manufacturing
technology for IC industry through the United States and Japan to achieve the
technological level of producing VLSI [4].
In 1981, the Korean government formulated the “Comprehensive Development
Plan for Semiconductor Industry” to support the development of 4 Mbit and
256 Mbit DRAM [4]. At the same time, with the governmental supports, Samsung,
Hyundai, and LG began to enter the field of integrated circuit manufacturing. In
1982, Samsung established a semiconductor research and development laboratory,
which focused on the reverse engineering and technology absorption of bipolar and
metal-oxide-semiconductor ICs. In 1983, several major semiconductor companies in
South Korea began to manufacture DRAM chips for IBM, Texas Instruments, and
Intel. In 1986, South Korea started to independently develop memory chips, includ-
ing 4 Mbit DRAM as a national project. At the same time, Samsung, LG, and
Hyundai then formed an alliance, with the Korea Institute of Electronics Technology
(KIST) acting as a coordinator between manufacturers, universities, and govern-
ment. During the 3 years from 1986 to 1989, South Korea invested a total of $110
million USD in 4 Mbit DRAM research and development, of which the government
provided 57%. This amount far exceeded budgets of other national projects. The
successful research and development of 4 Mbit DRAM has narrowed the gap
between South Korea, the United States, and Japan in DRAM technology. In
addition, large companies such as Samsung, Hyundai, and LG have established
their own research and development capabilities. In 1992, South Korea developed
and manufactured 64 Mbit DRAM chips during the same period of the United States
and Japan. In 1995, South Korea took the lead in manufacturing 256 Mbit DRAM
products, which was already ahead of the United States and Japan.
5 Development of Regional IC Industry 87

In addition to its leading position in the memory field, South Korea also has
strong competitive in IC fields such as application processors and ASICs. Samsung
Electronics is one of the world’s two largest manufacturers with 3 nm production
capacity. Moreover, South Korea is highly competitive in the field of semiconductor
equipment and materials. Companies such as SEMES, WONIK IPS, KC Tech,
Nepes, and SK Materials have made great contributions to the localization of
South Korean semiconductor industry. Meanwhile, South Korea’s memory capacity
is also moving overseas. China’s Xi’an and Wuxi have taken over the memory
production capacity from Samsung and SK Hynix, respectively.
In 2016, South Korea’s IC industry accounted for 17% of the global market,
ranking second in the world. According to IC Insights data, Samsung and SK Hynix
ranked second and sixth among the global top 10 semiconductor companies in 2016,
respectively. Also, Silicon Works ranked 22nd among the global top 50 fabless
companies in the world, and DongBu Hitech was ranked 9th among the world’s top
10 foundry companies. In the nearly 5 years from 2017 to 2021, Samsung is further
ranked as the first among semiconductor company in 2017, 2018, and 2021 [4]; it
ranked second in 2019 and 2020, respectively. The total sales revenue in 2021 was
$91.3B, up 30.5% from the previous year.

IC Industry Development in China

This section includes two topics: (1) IC Industry Development in Mainland China
and (2) IC Industry Development in Taiwan, China.

IC Industry Development in Chinese Mainland

As early as in 1956–1958, the two founders of semiconductor technology, Kun

Huang (Peking University) and Xide Xie (Hsi-teh Hsieh, Fudan University), once
held a professional training class on “Semiconductor Physics” at Peking University,
which was attended by 300 people from five universities in China. The course covers
Solid State Physics, Semiconductor Physics, Semiconductor Experiments, Semicon-
ductor Materials, Semiconductor Devices and Transistor Circuits, etc. Subsequently,
the Chinese textbook Semiconductor Physics (in Chinese) co-authored by Kun
Huang and Xide Xie was published in 1958 [5], which has been widely recognized
laid the theoretical foundation of semiconductor research and development of IC
industry in China. From the training class, academicians Yangyuan Wang and Juyan
Xu and others, Shoujue Wang and Shouwu Wang, to name a few, have become
pioneers in China’s IC Industry. In 1945–1947, Kun Huang received his Ph.D. from
Nevill F. Mott (Nobel prize winner in Physics in 1977) of Bristol University; Huang
then in 1947 collaborated with Max Born (one of the founders of quantum mechan-
ics and Nobel prize winner in Physics in 1954) at Edinburgh University; they
published a book in 1954 [6].
88 G. Zhang and K. Li

In 1965, the first silicon-based prototype IC was developed by using the epitaxy
method for the pn junction at the Institute of Metallic Research and the planar method
at Shanghai 5th Devices Factory. Meanwhile, the research of p-channel MOS,
n-channel MOS, and CMOS technology started at Peking University. With the strong
support of the State, from 1965 to 1977, high-speed ECL logic circuits, 1 kbit DRAM,
p-channel 1 kbit MOS shift registers, GaAs film growth by MOCVD technology, and
GaAs microwave field effect transistors were successfully developed.
In Feb. 1998, Beijing Nonferrous Metal Research Institute built China’s first
200 mm silicon single crystalline wafer polishing production line. In Feb. 1999, the
first 200 mm IC production line of Shanghai Huahong NEC Electronics Co., Ltd.
was officially put into operation.
Initiated and founded in 2000 by Academician Yanguan Wang and Dr. Richard
Chang, Semiconductor Manufacturing International Corporation (SMIC), supported by
scientists and entrepreneurs from both mainland and Taiwan, collaborates with domestic
capital and international capital to target the domestic and global IC markets.
Headquartered in Shanghai, the first 200 mm fab of SMIC was in production in
2001, followed by a 300 mm fab built in Beijing in 2004, to produce 130 nm/90 nm
processes for microprocessors and SoC products. By the end of 2005, the IC production
capacity of this 300 mm fab reached 20,000 WPM. Subsequently, the process nodes
have been progressed to 65 nm/55 nm and 45 nm/40 nm. In recent years, the IC fabs of
SMIC have stepped into the mass production of 28 nm and 14 nm technology nodes,
and under the continuous leadership of the new board of directors, its 7 nm technology
has made rapid progress in 2023. SMIC was incorporated in the Cayman Islands with
funding from worldwide; and today the domestic government has become the major
investor. Entering the twenty-first century, several design companies, such as Zhanrui
(Spreadtrum) and Hisilicon (of Huawei) had been ranked in top 10 global fabless
enterprises in 2016.
At present, China’s development in the field of IC Design [7], IC Manufacturing,
IC Packaging and Testing, Semiconductor Equipment, IC Materials, etc., is focusing
on the overall technological development of the semiconductor industry chain.
Today, academic research on semiconductor and/or IC is positive and active, both
in institutions and in university education.

IC Industry Development in Chinese Taiwan

In 1966, GI Corporation of the United States took the lead in setting up an IC

packaging factory in Kaohsiung, Taiwan province. In 1969, TI and Philips began to
move their industry and then set up packaging plants in Taiwan. In the same period,
the first semiconductor manufacturing enterprise in Taiwan, Fine Product Electronic
Corporation, was established, which laid the foundation for the initial development.
In 1974, “Industrial Technology Research Institute of Taiwan” established the
Electronic Research Institute, and the full name of the institute was Electronic
Research and Service Organization, short for ERSO. ERSO concentrated manpower,
5 Development of Regional IC Industry 89

material resources, and financial resources to develop the independent IC technology,

and thereafter signed a technology transfer agreement with RCA in 1976 to import
RCA’s 5 μm IC manufacturing technology and design technology. In 1978, ERSO
successfully mastered the CMOS technology and acquired its own design and mask
manufacturing capabilities to set up a CMOS IC demonstration plant. With the
participation of the Taiwan governmental authorities and the industry, IC manufactur-
ing plants, the foundry model [7], such as UMC, TSMC, and Winbond, were
established in Taiwan in the 1980s. The connection and exchange between Taiwan
resources and the US Silicon Valley technology had been opened, which had enabled
the rapid development of the IC industry in Taiwan and formed a virtuous circle.
At present, Taiwan has become one of the largest semiconductor industrial forces
outside the United States, Japan, South Korea, and Europe. The production value of
Taiwan’s semiconductor industry totaled $146.76 billion USD in 2021 [8], accounting
for a 26% market share of semiconductor revenue, ranking second in the world. In
addition, its IC design and packaging and testing industries also account for a 27% and
20% global market share, ranking second and first in the world, respectively.
According to IC Insights data in 2021, there are eight Taiwanese companies ranked
on the top 50 semiconductor suppliers in the world, among which TSMC ranked third
and MediaTek ranked top 10 in 2021. Also, there are 15 companies in Taiwan ranked
on the global top 50 IC design companies, of which MediaTek is the fourth largest
fabless semiconductor company globally. In addition, TSMC, UMC, Powerchip, and
VIS are also among the top 10 foundry fabs in the world. Also, ASE, SPIL, PTI, and
ChipMOS are among the top 10 packaging and testing companies in the world.
Semiconductor enterprises of Taiwan have begun the cooperation between the
semiconductor industry across the Taiwan Strait. For example, TSMC has
established a 300 mm wafer foundry fab in Nanjing to manufacture 16 nm wafers;
Powerchip and Hefei Municipal Government jointly established a 300 mm wafer
foundry fab named as Nexchip.

References
1. T. Charboneau, The “traitorous eight” and the rise of Fairchild semiconductor. All about Circuits,
Feb. 28, 2022. https://www.allaboutcircuits.com/news/the-traitorous-eight-and-the-rise-of-fair
child-semiconductor/. Accessed 24 May 2023
2. STMicro, https://www.st.com/content/st_com/en.html. Accessed 24 May 2023
3. Semiconductor History Museum of Japan, https://www.shmj.or.jp/english/integredcircuits/ic60s.
html. Accessed 24 May 2023
4. W. Li, Samsung Takes Semiconductor Crown from Intel in 2021. Counterpoint, 28 Jan. 2022. https://
www.counterpointresearch.com/semiconductor-revenue-ranking-2021/. Accessed 24 May 2023
5. K. Huang, X. Xie, Semiconductor Physics (Science Press, 1958). In Chinese ISBN 978 70303
46148
6. M. Born, Kun Huang: Dynamic Theory of Crystal Lattices (Oxford Clarendon Press, 1954).
ISBN 0-19-850369-5
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digitimes.com/news/a20220519VL202/china-ic-design.html. Accessed 24 May 2023
8. M. Liu, Taiwan and the foundry model. Nat. Electron. 4, 318–320 (2021)
Information Security in Integrated Circuits
6
Chaohui Wang, Qinsheng Wang, and Qian Peng

Contents
IC and Information Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Kinds of Attacks to Information Security in ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Non-invasive Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Invasive Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Semi-invasive Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Information Security Protection in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Anti-Sniffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Anti-Data-Remanence Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Prevention from FIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Information Security Protection in CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Anti-FIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Anti-sniffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Defense Against SCA to the Implementation of Cryptography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Defense Against FIA to the Implementation of Cryptography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Fault Tolerance Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Error Detection Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Robustness and Information Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Abstract
Information security is the foundation of information systems and the forever
theme of the information society. The main issues of information security includ-
ing non-invasive attacks, invasive attacks, and semi-invasive attacks have

C. Wang (*)
Beijing Huada Infosec Co., Ltd., Beijing, China
e-mail: wangzh@istecc.com
Q. Wang
IC Design Branch, China Semiconductor Industry Association, Beijing, China
Q. Peng
Bank Card Test Center, Chengdu, China

© Publishing House of Electronics Industry 2024 91

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_6
92 C. Wang et al.

become the hot topic of concerns and focus. As the basic components of elec-
tronic information systems, IC plays a critical role in the era of the IoT (Internet-
of-Things) and is indispensable for all operations and applications in information
security system. The attack and defense technology based on ICs becomes a very
important research topic in the field of information security and has been also
widely used in many industries practically.

Keywords
Information security · Non-invasive attacks · Invasive attacks · Semi-invasive
attacks · Attack and defense

IC and Information Security

Information security is the foundation of information systems and the forever theme
of the information society.
With the wide applications of computers, networks, Internets, etc. the issues of
information security have attracted widespread attention and research. With the rapid
rise of smart devices such as smart phones, smart wearable devices, smart homes,
smart cars, and intelligent robots, the information security issues of these products
have also become a hot topic of concerns and focus [1]. Information security plays
an increasingly important role in the era of Internet of Things (IoT). As the basic
components of electronic information systems, integrated circuit chips are indis-
pensable in all operations and applications in information security system. There-
fore, they are closely related to information security and are the key components
supporting information security. With the continuous progress of IC manufacturing
technology, the function of integrated circuit is increasingly more powerful, and the
internal structure is more and more complex. SoC chips, as the relatively indepen-
dent information processing system, are getting more and more widely used; there-
fore, the security of sensitive information in SoC chips often determines the security
of the upper systems and applications.
Cryptographic algorithm is the core technology to protect the information secu-
rity, which can be divided into symmetric cryptographic algorithm and asymmetric
cryptographic algorithm. Symmetric encryption algorithm is applied for data encryp-
tion and decryption operations. The encryption and decryption operations use the
same key, which is secretly stored and protected by the encryption and decryption
parties. Typical symmetric cryptography algorithms include DES, AES, and SM4.
Asymmetric cryptographic algorithm is also known as the public key cryptography,
which provides security functions such as digital signature, encryption and decryp-
tion, and key negotiation. The key used for digital signature and decryption is called
the private key, which must be stored and protected by the users in secret. The key
used to verify digital signatures and encryption is called the public key, which can be
made public. Typical asymmetric cryptographic algorithms include RSA (Rivest-
Shamir-Adleman), ECDSA, and SM2.
6 Information Security in Integrated Circuits 93

The implementation of cryptographic algorithm in integrated circuits can not only

achieve higher cryptographic performance but also provide better protection for key
and other sensitive information, including the protection of key storage, read/write,
and key participated cryptographic operations. Integrated circuits realize the security
control of password algorithm, such as smart card chips, USB key chips, and various
secure-element chips, and have become key information security devices on the
Internet and Internet of Things security application systems. At present, there are two
main reasons to promote the wide use of security controllers: first, sensitive data
including keys must be stored in a way to avoid unauthorized access, and security
controller can provide a good storage protection; secondly, the security controller
provides secure computing methods and environment for the processing of these
sensitive data.
To discuss the problem of information security in ICs, it is necessary to under-
stand all kinds of attacks against the information in ICs first, then to understand and
study the corresponding defense measures, and evaluate and test the effectiveness of
these defense measures. Attacks on information in ICs have been around for a long
time. For ICs without cryptography algorithms, the main target of the attacker is to
clone circuits, obtain or manipulate the sensitive data in memory. For security
controllers, the attacker’s goals also include acquiring or manipulating the key in
security controllers.
The attack and defense technology for information security in ICs is not only a
very important research direction in the field of information security but also has
been applied in many industries as a practical technology. Typical applications, such
as financial IC card chips, have established the corresponding security testing
standards and testing certification system both at home and abroad, to enhance and
protect the overall information security level of industry applications. The Common
Criteria Evaluation Assurance Level (EAL) test evaluation system and EMVCo’s
vulnerability assessment method are mainly used to carry out the assessment and
testing internationally. The relevant standards for domestic financial IC cards include
the “JR/T 0098.2-2012 China Financial Mobile Payment Inspection Specification
Part 2: Security Chips” issued by the People’s Bank of China and the “Q/CUP 040.1-
2016 Security Specification for UnionPay Card Chip Part 1: The IC Security
Specification” issued by China UnionPay. The national standard GB/T 18336
(equivalent to ISO/IEC 15408 (CC)) puts forward the general security assessment
criteria for information security products and systems, which is suitable for infor-
mation security level assessment in integrated circuits.

Kinds of Attacks to Information Security in ICs

The attacked object of an attacker is a security controller, and there are many ways to
classify the attacking behavior [2]:

1. According to the degree of invasion of the attacked object, it can be divided into
non-invasive (non-intrusive), invasive, and semi-invasive attacks.
94 C. Wang et al.

(a) Non-invasive attack does not need to open the chip package or contact the
internal circuit of the device. During an attack, the chip can be placed in the
test circuit for analysis, and the chip can also be monitored and analyzed in
the normal working environment.
(b) Invasive attack would require unwrapping the chip and removing the passiv-
ation layer with a focused ion beam (FIB) or laser to reach the internal
circuitry buried deep beneath the passivation layer.
(c) Semi-intrusive attack, like the intrusive attack, needs to open the chip pack-
age, but the chip passivation layer remains intact, does not require to make
electrical contact with the IC surface, and will not cause mechanical damage
to the IC.
2. Based on whether the attacker interacts with the attacked object, the attack
methods can be divided into active and passive attacks.
(a) In an active attack, the attacker interacts with the attacked object to make it in
a state favorable to the attack or to make use of the favorable state or fault
information to achieve the purpose of attack.
(b) In a passive attack, the attacker does not interact with the attacked object, but
only monitors the operational results and status information of the attacked
object, and then utilizes the operational results and status information to
achieve the purpose of attack.
3. According to the tools and means used by attackers, the known attacking methods
include microprobe technology, reverse engineering, software attack,
eavesdropping technology, and fault injection attack.
(a) Microprobe is used to directly access the chip surface and can be used to
observe, modify, or interfere with the operation of integrated circuits.
(b) Reverse engineering is a technique used to understand the structure and
function of software and hardware. It can be used to derive the internal
structure of integrated circuits and to learn or emulate its functions.
(c) Software attack refers to finding the defect of security protection in the
protocol, cryptographic algorithm, or cryptographic algorithm execution
module through the communication interface of the security controller.
(d) Eavesdropping technology refers to that the attacker can accurately monitor
the interface communication protocol of the security controller, the simula-
tion characteristics during normal operation, and any electromagnetic radia-
tion and then deduce the key data in the security controller by analyzing the
obtained information.
(e) Fault injection attack (FIA) means that an attacker causes a data or operational
failure of the security controller to gain additional data or the ability to read
and write the security controller.

Non-invasive Attack

Non-invasive attack is easy to implement and does not need a lot of overhead to
repeat attacks, leaving no traces of attack, which is considered to be the biggest
security threat to security controllers.
6 Information Security in Integrated Circuits 95

Non-invasive attack [2] can be passive or active. Passive non-invasive attack is

also known as side-channel attack (SCA). The attacker does not interact with the
attacked targets, but usually only monitors and collects the electrical signals or
electromagnetic radiation information of the attacked targets. Common SCA
includes power analysis (PA) and timing attack (TA). An active non-invasive attack
interferes with the security controller, such as a power pulse attack that adds a pulse
signal to the chip’s power cord to put the chip in the desired state or workflow of the
attacker.

1. Timing attack: Some operations related to information security will use the input
data and keys. Different input data and keys will lead to different execution time
of the security operation in the chip. The attacker can recover the keys through
clock measurement and analysis. Many cryptographic algorithms are vulnerable
to timing attacks, especially software cryptographic algorithms, including pro-
gram branches, operating conditions, the use of caches, and the operation of
non-fixed time processing, which will lead to the difference in execution time due
to the difference of input data and key, thus leading to security risks. Timing
attack can also be used to crack personal identification numbers (PINs) in security
controllers. In general, the risk of PIN verification is that the different check times
are performed for correct and incorrect PINs. To prevent timing attacks, PIN
verification should ensure that correct and incorrect PINs are the same at the
check time, which can be done by adding additional dummy operations to the
program.
2. Brute force attack: Brute force attack has different meanings for cryptographic
algorithms and ICs. Brute force attacks for cryptographic algorithms are attempts
to find the correct matching key by trying a large number of keys. The brute force
attack for ICs, one is to try a large number of logic combinations to try to obtain
the function of the integrated circuit, which is especially effective for small logic
devices. Another is to apply an external high voltage signal (usually twice the
supply voltage) to the chip pins in an attempt to get the chip into test mode or
programming mode.
3. Power analysis: The power consumption of an operational circuit depends on its
current state. According to the characteristics of CMOS transistors, the dynamic
power consumption of each unit module is higher than its static power consump-
tion. When the input voltage is applied to the inverter, it causes a short circuit in
the transistor, and the increase in the current of this transistor is much larger than
the parasitic leakage current consumed in the static state. For cryptographic
algorithm circuits, the power consumption state of input data and key is quite
different, and the key can be analyzed by measuring the current fluctuation on the
power line. There are two methods of power analysis: simple power analysis
(SPA) and differential power analysis (DPA). The SPA is to directly observe the
power consumption information of IC during cryptographic operation, so as to
analyze the key values during the operation. This method requires the attacker to
be familiar with how cryptographic algorithm is executed. DPA is a more
effective analysis method. The attacker does not need to know how the crypto-
graphic algorithm is executed, but to obtain the hidden key value by analyzing a
96 C. Wang et al.

large number of power consumption curves. That is, statistical methods are used
to identify the subtle differences in power consumption, so as to obtain the value
of a certain bit or a certain segment of the key.
4. Template attack: The template attack is to construct a template with information
leakage characteristics for all the keys in the key space of the cryptographic
algorithm in advance. Then based on the leaked information obtained from the
security controller to find the most matching template, and then deduce the most
likely correct key or effectively reduce the key search space of an attack.
Template attacks are often combined with SCA, called template-enhanced SCA.
5. Glitch attack: The glitch attack is a non-invasive fault injection attack, which affects
the normal operation of the security controller by rapidly changing the signal input to
the security controller. A pulse is usually applied to a power supply or clock signal, or
it can be an external transient electric field or electromagnetic pulse.
(a) Clock glitch attack: Clock glitch attack usually aims at the instruction stream
in the security controller; it has no effect on the security operations performed
by the hardware. If the internal clock of the security controller is difficult to
synchronize with the external clock, it is difficult for an attacker to estimate
the accurate time window to implement a clock glitch attack. In addition, the
random delay is added to the instruction stream, which will also increase the
difficulty of the clock glitch attack.
(b) Power glitch attack: Fluctuations in the power supply voltage can lead to the
threshold level of the transistor to drift. As a result, some triggers are sampled
at different times, and the state of their inputs or security fuses are misread.
Power glitches can be applied to a security controller with any programming
interface that can affect CPU operation and hardware security circuitry. Each
transistor and its associated circuitry form an RC circuit with time-delay
characteristics, and the maximum available clock frequency of the processor
depends on the maximum delay of this circuit. Similarly, each flip-flop has a
time characteristic window between the received input voltage and the
resulting output voltage, which is determined by a given voltage and temper-
ature. If a clock glitch or voltage glitch affects some transistor within the chip,
causing one or more flip-flops to go into the wrong state, the processor will
execute many different wrong instructions, some of which cannot even be
supported by microcode.
6. Temperature attack: Temperature attacks are non-invasive fault injection
attacks. The attacker interferes with the normal operation of the security control-
ler by changing the external temperature, causing data or operational failures to
obtain the desired state or data.
7. Data remanence analysis: When the security controller executes the password
algorithm, it usually needs to store the key temporarily in the static RAM
(SRAM). When detecting the attack, it will execute the power off operation to
make the contents in the SRAM disappear to protect the key from being stolen. It
is well known that contents in SRAM can be “frozen” at temperatures below

20  C, so many security controllers treat temperature below this threshold as an
attack event. Experiments have shown that data residue in static RAM can also be
6 Information Security in Integrated Circuits 97

a security issue at temperatures higher than
20  C. The data residue of SRAM is
related to the chip power consumption, and the lower the power consumption, the
longer the data residue time. Data residual security problems exist not only in
SRAM, but also in DRAM, EPROM, EEPROM, and Flash. As a result, some
residual information of the data can still be obtained from these erased memories,
which brings a great threat to the security controller. Unlike SRAM with only two
stable logic states, EPROM, EEPROM, and Flash cells actually store memory
charges in the form of analog quantity in the floating gate of transistors. Floating
gate charges change the threshold voltage of the transistor, which can be detected
by sensitive amplifiers when the memory cell is being read. Experiments have
shown that the electrons do not completely leave the floating gate even after
multiple erasures, making it feasible to obtain the erased content.

Invasive Attack

Invasive attacks [2] require good equipment and rich cracking experiences, and as
the size of IC features scaling and complexity increasing, the cost of attacks becomes
more expensive. Intrusive attacks generally include the following process:

1. Preparation of sample. Intrusive attacks first require partial or complete removal

of the package of the chip, usually using chemical or laser methods. The chemical
method usually involves dropping a strong acid onto the surface of the chip
package to dissolve the epoxy resin encapsulating the IC, and then cleaning it
with acetone/deionized water.
2. Reverse engineering. The structure and function of ICs can be understood
through reverse engineering. Usually, the IC is stripped layer by layer in physical
or chemical way, and then photographed by optical or electron microscope, and
the layout of the IC is reconstructed by analyzing the optical image.
3. ROM information extraction. No matter what kind of encoding method is used
in ROM, its encoding characteristics can be generally recognized, and the data
stored in ROM can be obtained after a special processing. The ROM program-
ming methods are mainly lead hole mask programming, active region mask
programming, and ion implantation mask programming. In ROMs with lead
hole mask programming and active region mask programming, the stored data
is related to the structure of the line, and the structural characteristics can be
directly observed. The different features of the 0 and 1 codes in ion-implanted
ROM can be observed only by staining methods.
4. Use microprobe technology. The passivation layer is removed with a laser cutter
so that the microprobe can reliably contact the top wiring layer to capture or inject
a signal. To obtain keys or other sensitive data in memory, microprobes are
usually placed on the data bus. If necessary, the connection with the IC can be
established through FIB workstation, and the test point can be led out at any
position in the IC, so that the microprobe station can directly observe the internal
signals of the IC.
98 C. Wang et al.

5. Modify the chip. Keys or other sensitive data in memory may not be necessarily
only available on the data bus through the microprobe. For some security
controllers, FIB can be used to cut off the internal metal interconnects or destroy
the security control circuits to shield the security protection, and then read the key
or other sensitive data in the IC without security protection.

Semi-invasive Attack

With the shrinkage of IC feature size and the increase of complexity, the require-
ments for implementing invasive attacks will become higher and higher, and the cost
will become more expensive. Semi-intrusive attacks are suitable for small feature-
sized ICs, which do not require expensive tools, and can get results in a shorter time,
making them more attractive to attackers. Semi-invasive attacks typically use ultra-
violet (UV) light, X-rays, lasers, electromagnetic fields, and heat, and can be used
alone or in combination.

1. UV attack: UV attacks are effective against many OTP and UV EPROM con-
trollers. It just requires opening the package of the IC, finding the security fuse,
and resetting the security fuse to an unprotected state with UV light.
2. Backside imaging technique: The first step in the analysis of ICs is to observe
them under a microscope. For ICs with small feature sizes, it is difficult to see
anything in natural light, while using infrared, near-infrared microscopes, and
infrared sensitive lens, whether direct or reflected, these small features can be
seen from the back of the chip. The back-side imaging technique can obtain the
contents of the ROM or observe the internal interconnections of the chip using a
focused ion beam (FIB).
3. Active photon probing technology (active photon probing): A scanning laser
beam is applied to an IC to ionize the specific areas of the IC when the energy of
the photon is greater than the bandgap of the silicon, then a specific region of the
IC can be ionized. In the analysis of ICs, there are two main laser scanning
techniques: one is Optical Beam Induced Current (OBIC), which is used on chips
without bias voltage; the other is Light Induced Voltage Alteration (LIVA), which
is used on chips in operation. The OBIC can be directly used to generate images
of ICs. For LIVA, images of ICs can be generated by monitoring voltage changes.
If photons reach near the pn junction, the photocurrent will be generated due to
the photoelectric effect. When photons enter the p or n region, conduction carriers
are injected to lower the channel resistance of the memory cell, which allows the
state of the storage cell to be read from the scanned image.
4. Fault injection attack (FIA): The semi-intrusive fault injection attack usually
uses the laser irradiation to affect the state of the target transistor, so as to produce
a temporary fault, and use the output or influence generated by the fault to obtain
sensitive information such as the key in the security controller.
6 Information Security in Integrated Circuits 99

Information Security Protection in Memory

The security controller is designed to provide a secure environment for storing and
processing sensitive data including keys. Therefore, it is necessary to provide
all-round security protection in memory [3], CPU, and cryptographic operations to
cope with various possible security attacks. The following describes the security
protection technology of the memory.

Anti-Sniffing

There is a consensus to protect the stored contents of security controllers from

microprobe sniffing. The initial protection method used was to implant sensitive
information into the ROM, but the attacker quickly discovered a way to learn the
contents of the ROM. As a result, designers of security controllers began to adopt
more secure measures, and one of the initial adopted countermeasures was memory
address scrambling. However, the attacker quickly overcame this obstacle by using a
computer program to reassemble the plaintext from the scrambled storage informa-
tion. Thus, simple address scrambling is generally replaced by memory and internal
bus encryption, creating a truly effective hedge against sniffing and reverse engi-
neering. In order to prevent attackers from using the test port to attack, the test port
circuit of the security controller is usually destroyed during production.
The use of a shielding layer is also a common anti-sniffing method. In the 1990s,
active shielding measures covering the entire chip surface became popular, and the
shielding layer also provided good protection against illegal access and physical
attacks. Security controller designers can also consider signal rewiring, such as
hiding key signal lines or placing key signal lines at the bottom of the chip, which
can increase the difficulty of microprobe sniffing, and can also provide PIN protec-
tion for the secure storage area to prevent illegal access.

Anti-Data-Remanence Analysis

In order to prevent the analysis of data residue in the memory of the security
controller, the designers of the security controller and the developers of the security
applications should follow the following design guidelines:

(a) Do not store keys, PINs, and other sensitive data in static RAM for long periods
of time, change their storage location frequently, and clear the value of the
original location.
(b) Set the temperature sensor in the security controller to activate the protection
state when the rated low temperature is detected and perform the protection
operation.
100 C. Wang et al.

(c) Before writing any sensitive information to EEPROM and Flash, use a random
number loop to erase 10–100 times to eliminate any detectable effects caused by
using the new cell.
(d) Before erasing sensitive data, the corresponding units of EEPROM and Flash are
programmed with random numbers to eliminate the influence of detectable
residual charges.
(e) Note that some non-volatile memory devices still leave a copy of sensitive data
in a specific area after erasing it.
(f) Using the latest and highest density memory devices, because the latest storage
technology usually makes data recovery more difficult.
(g) Using proper encryption methods makes it more difficult to recover data from
erased storage units. For secure applications in a secure controller, the ideal state
is that every memory in the controller is under its protection.

Prevention from FIA

A security controller must consider preventing an attacker from FIA (fault injection
attacks) against the memory in it. One of the earliest defenses still used today in
low-end security products is the parity protection, where an extra parity bit is added
to each portion of memory content (e.g., 1 byte) to check whether the sum of the bits
is odd or even. Obviously, the level of parity protection is very low, the success rate
is only about 50%, that is, about half of the attacks will be successful, so people will
not be satisfied with this kind of security protection.
Hardware-supported secured fetching is another way to protect storage from fail-
injection attacks. Secured fetching usually means that the contents of memory are
checked for integrity before being processed on the way to the CPU. These measures
have many possibilities for design and implementation, such as the use of arithmetic
error detection codes in high-security chips, which can not only detect one or more
errors but also have error correction functions. In designing and implementing
the secure fetching mechanism, we should pay attention to the balance between
the computing performance and security of the security controller. In addition, the
process of the memory content being processed in the CPU should also be protected.
Otherwise, the secure fetching mechanism is meaningless to defend against some
attacks.
It is possible to prevent some FIA against memory with tamper-proof sensors and
security fuses. Using multiple fuses is better than using single fuses to improve the
security of memory. The distance between multiple fuses can be set relatively large,
which makes it very difficult to implement the fault injection attack. The security
fuse can also be provided with two units, and the fuse can be shielded only when
both units are in a fusing state to further enhance the safety of the fuse.
A dual-track logic design can also be used to prevent fail-injection attacks (FIA).
One approach, for example, is to use dual-track logic on the data line, in which signal
0 or 1 is no longer a high or low voltage on a single line, but a combination of a pair
of line signals, for example, 0 may be LH and 1 may be HL. When using the self-
6 Information Security in Integrated Circuits 101

synchronous dual-track logic, LL stands for static, and HH is a redundant state, so

HH can be used as an error signal. This signal can be obtained by a tamper-proof
sensor, and the presence of the HH signal will cause the component to lock,
preventing the output of sensitive information. To succeed, the attacker must inject
both failure states at the same time to make the transmission line switch from LH to
HL; otherwise the transmission line will instantly enter the HH state and immedi-
ately trigger an alarm.

Information Security Protection in CPU

The CPU and memory in the security controller are the attack points that the attacker
is interested in. Therefore, it is necessary to adopt various security protection
measures in the design [4].

Anti-FIA

An attacker may find opportunities to introduce faults during the CPU processing to
obtain keys or manipulate software execution. Early ways to protect the CPU from
fail-injection attacks were to install sensors that detect environmental conditions,
such as clocks, voltages, light, or temperatures. However, fault injection attacks are
still possible for other CPU faults, such as laser and electromagnetic radiation
attacks, or direct attacks through physical methods, such as FIB manipulation,
microprobe, and other technologies. As with the protection methods originally
employed by memory systems, the initial solution to enhance CPU security is to
use parity bits.
The parity bits in CPU registers are very easy to implement without having to
design a security controller from scratch, but this simplicity comes at a huge cost to
security. The CPU parity protection, like memory parity protection, also has signif-
icant drawbacks, so there is a need for better ways to protect the CPU. A very simple
way for the CPU to defend against fail-injection attacks is to perform the same
operation twice in sequence, compare the results of the two operations, and issue an
alarm if the results do not match. However, this approach will degrade CPU
performance and can be bypassed by an attacker by performing two fault-injections.
Nowadays, multiple fault injection (MFI) attacks are often used by attackers, and the
MFI appears more frequently in the process of IC security evaluation and
authentication.
The typical multiple operation defense approach (with redundancy on the time
scale) is vulnerable to multiple failure injection (MFI) attacks because the
corresponding attack devices are already present and can override the microcontrol-
ler instructions and clock cycle time scales to disrupt the security precautions made
through the time scale redundancy. A more secure measure involves the use of
tightly integrated dual CPU cores, with both cores constantly checking on each
other’s operations and conditions. If the CPU can perform encryption operations, the
102 C. Wang et al.

two cores can even use different dynamic keys to greatly enhance the protection
against multi-fault injection attacks from multiple times and/or multiple zones.

Anti-sniffing

In addition, the CPU must be protected from sniffing attacks. In the development
history of security controller in recent decades, the CPU basically works in plaintext
mode, which means that an attacker eavesdropping on the CPU can completely
obtain the plaintext data processed in the CPU. Early sniffing attack defenses
included adding several metal layers to protect valuable signals from theft; shielding
measures to fully cover the chip later emerged, some with self-checking capabilities
or dynamic arbitrary digital feedback capabilities to check the integrity of the
shielding.
Today, these measures have very limited effectiveness in the face of FIB, micro-
probe, microsurgery on a chip, and other attack methods. In addition, there are attack
methods that steal the contents of the CPU without any actual manipulation, such as
light radiation analysis. This is because silicon transistors emit a very small amount
of light during operations, which can be used to read the contents of registers.
Security controller designers have recognized the need to enhance the CPU
security. The advanced method used today is for the CPU to dynamically encrypt
its calculations, so that an attacker can only access the encrypted data. This approach
requires a redesign of the CPU, which is not as simple as modifying an existing CPU,
but this effort has significant security advantages.

Defense Against SCA to the Implementation of Cryptography

For the security controller, the implementation of cryptographic algorithms is closely

related to security. The implementation module of cryptographic algorithms should
be able to resist various side-channel attacks (SCA) [2] effectively. The side-channel
information (such as power consumption curve, electromagnetic radiation curve,
time, etc.) disclosed by the operation involved in the key is related to the input data
including the key. The security implementation of cryptographic algorithms should
mask or eliminate this correlation.
Both symmetric and asymmetric cryptographic algorithms are implemented in the
security controller to eliminate the following relations as the guiding principle of
defending against side channel attacks. That is,

1. the relationship between the data of the key operation and the disclosed side
channel information and
2. the relationship between the actual data used in the key operation and the
input data.
6 Information Security in Integrated Circuits 103

Taking the power analysis protection of the asymmetric cryptographic algorithm

as an example, the following methods can be used to eliminate the above relation-
ship: power consumption compensation, so that the same power is generated when
the private key bit value is 0 or 1; unified operation, so that the private key bit value
is 0 or 1 to perform the same operation; to randomize the input data or intermediate
value of the private key operation, that is, to mask the real data with a random
number before performing the calculation.
In order to defend against the power analysis implemented by symmetric cryp-
tographic algorithms, the power consumption compensation and the randomization
of the intermediate data (also known as random masking) used in the
key-participating operation are also the main methods. The core idea of the mask
method is to randomize the intermediate data of the symmetric cryptographic
operation, so that the power consumption does not depend on the real intermediate
value, which destroys the basic condition of differential power analysis (DPA)
implementation. The attacker cannot correctly group large amounts of plaintexts
according to the intermediate value and cannot calculate the expected assumed
power consumption from the intermediate value. The operations of masking inter-
mediate values with random numbers mainly include exclusive OR, addition, and
multiplication. The corresponding masking methods are called Boolean mask,
addition mask, and multiplication mask, respectively.
The initial method to deal with the side channel attack (SCA) is to apply various
noises to the output signal of the chip, but this method is not very effective,
especially the analysis method such as DPA has a strong noise filtering capability.
At the circuit level, dual-track logic can be used to defend against side channel
attacks (SCA). Another advantage of dual-track logic is that all states have the same
power consumption weight, making power analysis difficult to perform. However,
the implementation cost of dual-track logic is relatively high. It is the most effective
and economical way to resist side-channel attack to set up a random number
generator in the chip and use random numbers to protect the cryptographic
operation.

Defense Against FIA to the Implementation of Cryptography

The cryptographic algorithm implementation module in the security controller can

also resist various fault injection attacks (FIA) effectively. At present, the main
protection methods include fault tolerance technique and fault detection technique.

Fault Tolerance Technique

Taking the ECC algorithm as an example, the fault injection attacks (FIA) against
ECC can be divided into three categories: security fault attack, weak curve attack,
and differential fault analysis (DFA). Security failure attacks implement the analysis
104 C. Wang et al.

based on failures that do not change the output. Weak curve attacks attempt to move
the point multiplication operation from a strong elliptic curve to a weak elliptic curve
to obtain the private key or random number as the multiple of the point multiplica-
tion operation by solving the discrete logarithm problem of the elliptic curve. The
DFA derives the multiple of the point multiplication bit by bit through analyzing the
difference between the correct and incorrect outputs.
The corresponding defense methods of these attacks include using error detection
technology to detect whether the parameters of elliptic curve are correct, whether the
point multiplication base point is on the elliptic curve, and whether the fault is
inserted into the data in the point multiplication operation. Once the fault is detected,
the execution of the point multiplication operation is aborted, and the output of any
results is rejected. The fault-tolerant technique can be used to select an elliptic curve
so that even if a fault is introduced into the point multiplication operation, the
attacker cannot derive the multiple of the point multiplication from the wrong result,
such as twist-strong curves that are fault-tolerant under twist-curve attacks.
In addition, some side-channel attack defense methods of ECC also have the
capability to defend against some fault injection attacks (FIA), such as the Mont-
gomery ladder and the randomized multiple of point multiplication operation, which
make secure fault attacks more difficult to implement. The base point blinding
method of point multiplication can defend against the weak curve attack.
For the RSA (Rivest-Shamir-Adleman) algorithm, the private key used in the
signature can be analyzed based on incorrect and correct signature results. Therefore,
it is necessary to perform the fault detection or verify the signature results in the
private key operation process. Once faults or incorrect signature results are found,
the signature results are rejected.
For the public key encryption algorithm that achieves the IND-CCA2 security
level, the algorithm itself has built-in error detection technology, which naturally has
certain capabilities to defend against fault injection attacks.
In the symmetric cryptographic algorithm, the key operation is mainly adding the
round key or the S-box substitution, so this also becomes the main attack point
selected by the fault injection attacker. Fault injection attacks (FIA) can be classified
into temporary and permanent fault injection attacks. In a temporary fault injection
attack, an attacker can use techniques such as irregular clock pulses, radiation, and
transient high voltage to change a bit in the cache or memory. In a permanent fault
injection attack, the attacker can use ultraviolet light or the like to clear a bit in the
EEPROM or use a microprobe to set or clear a bit in the EEPROM. Bit fault is an
effective fault injection attack in which only one bit is introduced into the encrypted
intermediate result while the other bits remain unchanged. As this method is applied
to the symmetric cryptographic algorithm, if the attacker repeatedly introduces a bit
fault into the intermediate encryption result that is about to enter the last round of
encryption, that is, the fault introduced in each encryption changes some of the
intermediate result while ensuring the other bits remain unchanged, it is possible to
obtain the round key of the last round. DFA is an effective cryptographic analysis
6 Information Security in Integrated Circuits 105

technology. The basic idea of DFA is to obtain the correct and incorrect ciphertexts
corresponding to the plaintext through the fault induction in the encryption process
after selecting the plaintext, and then analyze the data of these two ciphertexts to
obtain the key.

Error Detection Technique

In the implementation of symmetric cryptographic algorithms, the error detection

technique is the main principle to defend against fault injection attack. The error
detection technique can detect the fault inserted in a symmetric cryptographic
operation. Once the fault is detected, the execution of the cryptographic operation
is stopped, and the output of any result is rejected. Error detection technique for
symmetric cryptographic algorithms includes redundancy-based error detection
techniques, code-based error detection techniques, and a mixture of these two
techniques.
Error detection technique based on redundancy can be classified into hardware
redundancy and time redundancy (1). The hardware redundancy-based error
detection technique directly copies the cryptographic algorithm hardware as a
self-checking method and compares the output of the replica circuit with the result
of the original circuit. If it does not match, it indicates an error. (2) The error
detection technique based on time redundancy performs the second encryption/
decryption operation on the same data, then compared with the result of the first
encryption/decryption operation. This method increases the extra time cost by
100% and can only defend against a single fault injection. (3) Hardware redun-
dancy and time redundancy techniques can be combined to find a balance between
hardware and time cost, and an error detection scheme suitable for symmetric
cryptographic algorithms to be implemented securely in a security controller can
be designed.
The simplest error-detection code is the parity code, which can be set to one or
more check bits as needed. However, the error detection coverage of parity code is
not high enough. When using parity code in the implementation of symmetric
cryptographic algorithm, it is necessary to analyze whether its error detection
coverage is enough to deal with the possible fault injection attack of the security
controller.
In order to improve the error detection coverage, the Concurrent Error Detection
(CED) method for symmetric cryptographic algorithm is proposed. The CED detects
the operation in the symmetric cryptographic operation of the security controller to
ensure the correctness of the output. If the CED detects an incorrect calculation, the
security controller will discard the wrong result before the output, so the chip can
resist the threat of FIA. The coverage of CED error detection is usually much higher
than the parity, but it also depends on the coding mechanism adopted and the
hardware implementation details.
106 C. Wang et al.

Robustness and Information Security

Robustness was originally a term used in statistics. It began to be popular in the study
of control theory in the early 1970s to characterize the insensitivity of control
systems to characteristics or parameter perturbations. In practical applications, the
disturbance of system characteristics or parameters is often inevitable. There are two
main reasons for the disturbance: one is that the actual value of the characteristic or
parameter will deviate from its design value due to the imprecision of measurement;
the other is the slow drift of characteristics or parameters caused by environmental
factors in the process of system operation.
Robustness has become a fundamental issue that must be considered in the design
of all types of control systems. In terms of integrated circuits, disturbances come
mainly from three aspects: process disturbances; high electrical noise, such as
voltage transients and electrostatic discharge (ESD); operating temperatures (such
as
40  C to +125  C required by automobile industry). Robust design is required to
enable integrated circuits to operate reliably in all extremes of these three parameters.
Although robustness and information security are two different concepts, there is
a strong correlation between these two concepts in the security controller. The
attacker may implement the fault injection attack by changing the environmental
factors of the chip. Some measures to deal with fault injection attacks, such as error
detection technique and fault tolerance technique, come into play after the occur-
rence of faults, and the purpose of robust design is to avoid the occurrence of faults.
In addition, the robustness of the security controller can also ensure that the security
module can play the normal security protection function under the disturbance of
various environmental factors.
By setting temperature, clock, light, and voltage sensors in the security controller,
abnormal fluctuations of temperature, clock, light, and voltage can be detected, and
corresponding security protection measures can be taken. However, these security
sensors cannot shield faults or damages caused by ESD on integrated circuits. With
the continuous shrinkage of feature size and the reduction of oxide layer thickness,
integrated circuits are more sensitive to ESD strikes. The wide application of lightly
doped drain (LDD) and silicide technologies has greatly reduced the ESD protection
performance of previously used ESD protection circuits, such as field devices, MOS
transistors, and diodes. The SCR (silicon controlled rectifier) structure of the ESD
protection circuit has the highest ESD protection performance per unit area due to its
low holding voltage characteristics, so it has become the mainstream ESD protection
device.
The robustness of the security controller has a significant gain effect on some
aspects of its security and has become a key characteristic index of many security
controllers. For example, in the financial field with a huge number of smart cards,
due to the diverse acceptance environment of financial IC cards, robustness and
security are key indicators of financial IC card chips, especially ESD protection
capabilities.
6 Information Security in Integrated Circuits 107

References
1. M. Areno, 4 integrated circuit security threats and how to protect against them. Physical Security.
https://www.darkreading.com/physical-security/4-integrated-circuit-security-threats-and-how-
to-protect-against-them/a/d-id/1341486. Accessed 23 May 2023
2. ADI, Cryptography: Planning for Threats and Countermeasures. https://www.analog.com/en/
technical-articles/cryptography-planning-for-threats-and-countermeasures.html#:~:text¼A%
20security%20IC%20can%20be%20attacked%20by%20one,array%20tampering%2C%20such
%20as%20a%20cold%20boot%20attack. Accessed 23 May 2023
3. D. Neustadter, Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks.
https://www.design-reuse.com/industryexpertblogs/53687/secure-ddr-dram-against-ro-hammer-
rambleed-and-cold-boot-attacks.html. Accessed 23 May 2023
4. L. Constantin, The second Meltdown: New Intel CPU attacks leak secrets. https://www.
csoonline.com/article/3395458/the-second-meltdown-new-intel-cpu-attacks-leak-secrets.
html. Accessed 23 May 2023
Integrated Circuit Intellectual Property
7
Bulu Xu

Contents
Silicon IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Status of IC Intellectual Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
The Transactions, Cooperation, and Sharing of IPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Abstract
The supplies of China’s Si intellectual property (IP) cores are mostly from the
overseas companies, e.g., ARM, Synopsys, and others. The “China’s IC Industry
Intellectual Property Annual Report,” which is published by the department of
intellectual property of China Semiconductor Industry Association (CSIA) and
Shanghai Silicon Intellectual Property Exchange Inc., introduces the annual
status, including the applications, reuse and service platforms, of IP cores. Si
intellectual property cores (IP cores, or briefly IPs) refer to pre-designed and
verified functional circuit modules in the design of ICs, including logic, circuit, or
layout designs. With the development of VLSI design and CMOS manufacturing
technology, SoCs are the products based on VLSI design and supported by the
submicron/nano-scale technologies, IP cores, and standard IC modules with the
capability of reuse and portable, as well as hardware and software co-design.

Keywords
IP cores · VLSI · CMOS · SoCs · IP reuse

B. Xu (*)
Shanghai Silicon Intellectual Property Exchange Centre, Shanghai, China
e-mail: blxu@ssipex.com

© Publishing House of Electronics Industry 2024 109

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_7
110 B. Xu

Silicon IP Core

In terms of technology, the silicon IP core is an important category of IC

intellectual property. It refers to the pre-designed and verified functional circuit
modules in the design of ICs with intellectual property rights (including but not
limited to silicon), including logic, circuit, and layout unit. Because of high
performance, low power consumption, high technology intensity, congregational
feature of intellectual property, and high commercial values, the silicon IP core is
the most critical industrial factor and the embodiment of competitiveness in the
IC design industry.
The concept of IP core has been used in IC design for nearly 30 years, while the
standard cell library was an early form of IP. At present, the SoC design platform
based on IP reuse is adopted by almost all major IC design companies.
In practical applications, IP cores include the following connotations: IP must be
specially designed according to certain standards for easy reuse and conform to the
application interface protocol after the optimization, so as to emphasize the read-
ability of IP codes, the openness of applications, process applicability, debug
measurability, port standardization, and data confidentiality.
IP design is different from IC design. IPs are used by third-party design compa-
nies. In order to make IPs run in the SoC system designed by the third party, it is
necessary to establish a compatible environment, including the specification of
documents, evaluation environment, and verification methods, especially those
configurable and large IPs. The commercial IP core should be equipped with good
development documents and reference manuals, including data sheets, user guides,
simulation, and reuse models, so as to meet the future SoC integration. In order to
solve the applicability problem of IPs, there have been several IP standardization
organizations such as Virtual Socket Interface Alliance (VSIA, 1996–2008, USA),
Structure for Packaging, Integrating and Re-using IP within Tool-flows (SPIRIT
Consortium, merged with Accellera [1] in 2009), Open Core Protocol International
Partnership (OCP-IP, acquired by Accellera in 2013), and IP trading organizations
such as Design and Reuse (D&R [2], 1997-, France), Virtual Component Exchange
(VCX, 1997-, UK), and SSIPEX (2003-, China).
IP core owner may use or license the IP core to others. In this sense, the term
silicon intellectual property is derived from existing patents and/or original code
copyrights (licensing models) in the design industry. Based on features by Gartner,
IP is divided into processor IPs (such as MP, DSP), physical IPs (such as PHY,
SRAM, DRAM, Flash, I/O, GPS), other digital IPs (such as graphics IP, CODEC,
Embedded PLD), wireless interface IPs (such as BT, WLAN), wired interface IPs
(such as USB, DDR, PCI, HDMI, MIPI, SATA, Ethernet), and analog mixed-signal
IPs (such as AD, DA, AFE, PLL, PM, RF).
In the legal field, silicon intellectual property also has specific derivative mean-
ings, that is, patents, copyrights, layout-designs, and process secrets related to all
branches of the industry chain in the field of ICs. In 1989, the World Intellectual
Property Organization adopted the “Treaty on Intellectual Property in Respect of
7 Integrated Circuit Intellectual Property 111

Integrated Circuits”. In addition, the Intellectual Property Agreement regulates the

layout design of ICs. Its contracting parties shall provide protection for it in
accordance with the conventions mentioned before. The layout design protection
of IC in China is relatively late. On March 28, 2001, the State Council passed the
Regulations on the “Regulations on Protection of Integrated Circuit Layout Design”,
which took effect on October 1, 2001. In accordance with the “Regulations on
Protection of Integrated Circuit Layout Design”, the “Detailed Rules for the Imple-
mentation of the Regulations on the Protection of Integrated Circuit Layout Design”
are hereby formulated and shall come into force on October 1, 2001. In accordance
with the “Regulations of the People’s Republic of China on the Protection of Layout-
Design of Integrated Circuits”, the “Administrative Law Enforcement Measures on
Layout-Design of Integrated Circuits” were formulated, which took effect on
November 28, 2001.

Status of IC Intellectual Property

With the development of VLSI design and CMOS manufacturing technology, SoC
supported by IP core reuse, hardware and software co-design, and ultra-deep
sub-micron/nanometer design has become an important development direction of
VLSI. The IP core reuse and transaction of IC modules and supporting files that meet
certain standards not only shorten the system design cycle but also improve the
success rate of system design. More than 90% of current SoCs in the industry are
designed with IP cores as the main design, and a lot of silicon intellectual property
such as IP core code and patents are reused.
On the whole, IP core field as the upstream in the IC industry, the market presents
an unprecedented situation of monopoly and aggregation. From the statistics of the
2014 IP cores sales provided by Gartner, the global semiconductor IP market size
reached $2.683 billion USD, of which license revenue was $1.439 billion, royalty
income was $1.056 billion, and service income was $188 million. Among the
suppliers, the UK ARM’s income was $1.23 billion USD (46% of the market
share), the US Synopsys’s income was $370 million (13.8% of the market share),
and the British Imagination’s income was $240 million (8.8% of the market share).
The top 10 IP providers accounted for a total of 82.6% market share, with a
compound growth rate of 12.5% (higher than the average growth rate of 9%).
According to the statistics of SSIPEX and D&R, there are 440 global IP suppliers.
On the top 50 suppliers, 30 suppliers are American companies. The IP cores sales
were reported to be $5.2B in 2021; expected to reach $7B by 2026 and $9B by 2030,
growing at a CAGR of 5–6% approximately.
The IP core industry values the establishment of the entire ecosystem. It is
difficult for companies that only provide a single type of high-performance IP core
products with technological advantages to gain a foothold in the market. Corre-
spondingly, in addition to IP cores, but also providing EDA tools, IC manufacturing,
design solutions, system supports, and other services of the company, even if the
112 B. Xu

performance of IP cores is slightly inferior, however, combining its comprehensive

advantages, the formation of a large ecosystem can still obtain customers’ favor. At
the same time, IP suppliers can also form a competitive advantage through providing
multiple types of IP cores, establishing a small ecosystem, and saving overall costs
for customers. At present, the industry’s leading IP companies are constantly through
mergers and acquisitions (Ms&As), on the one hand, to establish a comprehensive
competitive advantage in the whole process, on the other hand, also continue to
enrich their IP product series.
With the rise of artificial intelligence (AI), algorithmic IP is becoming a new
active IP category, such as gesture, recognition, semantic recognition, expression
recognition, panoramic view of audio algorithm, flight control algorithm, and image
stabilization algorithm. These algorithms are gradually integrated into large IP cores
or IC chips on the terminal to form chips with AI functions. This trend has already
emerged, for example, Apical Technology for the visual algorithm IP was acquired
by ARM (2016). Qualcomm has also acquired many high-tech companies in recent
years.

The Transactions, Cooperation, and Sharing of IPs

The silicon intellectual property IP core transaction is essentially authorized by the

IP provider due to the excessive concentration of IP providers. In addition, foundry
and design service companies can provide their own process IPs and some related
IPs. In terms of IP cooperation and sharing, TSMC has proposed and built the Open
Innovation Platform (OIP) design ecosystem, through which customers can be
provided with design assistance tools, IPs, and process technology, so that customers
can shorten the time from product design to mass production.
There are two modes of patent transaction in the field of integrated circuit: One is
that the patent holders give authorization personally, and another is that the IP
operating companies are involved in the trade. The latter model has been commer-
cially successful in recent years. A few typical cases are as follows.
In 2010, Intel and the Federal Trade Commission (FTC) jointly announced that
they had reached a preliminary settlement over allegations that Intel illegally
suppressed the competition in the processor chip market. Intel would revise its
intellectual property agreements with AMD, Nvidia, and VIA to give them more
freedom to consider mergers or joint ventures with other companies without the
threat of lawsuits over Intel’s patent infringement. It also extended its x86
licensing agreement with VIA for another 5 years, through 2018, from the current
agreement.
In 2012, Bridge Crossing LLC, a consortium affiliated with the patent-operated
company AST, acquired ownership of MIPS’ 580 existing patents and 498 pending
patents, for which the group would pay $350 million USD. Of this, $167.5 million
USD would be paid by ARM. Imagination acquired the operating business of MIPS,
the remaining 82 patents, and would permanently retain the royalty-free access to all
patents sold to AST for $60 million USD.
7 Integrated Circuit Intellectual Property 113

At the end of 2015, the patent operating company WiLAN [3] acquired 3300
patents from Freescale.
At the beginning of 2016, Xiaomi purchased 332 US patents from Intel
Corporation.
As a knowledge-intensive and capital-intensive international industry, intellectual
property is the key competitiveness of IC enterprises. According to the SSIPEX
statistics, as of the filing date of May 31, 2014, Intel Corporation had a total of
38,392 US patents and 6866 Chinese patents. According to the information in the
Intel CPU Design Technology Patent Database, Intel has 5511 US patents and
926 Chinese patents in the field of CPU design. Patents have always been the
effective and main means to protect the IC technology innovation in the world,
and the patent licensing is also an important source of income for enterprises. For
example, Qualcomm’s 2013 financial report showed that the ratio of license business
revenue to baseband chip business revenue was about 1:2, but the contribution of
pre-tax profit ratio was nearly 9:1. In this way, Qualcomm has combined its standard
patent licensing business with the baseband chip design and manufacturing business.
Patent operation in the form of license and lawsuit is an integral part of IC
industry ecology. From 1997 to 2007, there were more than 900 semiconductor
patent litigation cases handled by federal courts in the United States. In recent years,
many large IC companies have entrusted patents to specialized patent management
agencies.
The typical cases about patent litigation are as follows. Marvell, the world’s 8th
largest semiconductor design company, agreed to pay Carnegie Mellon University
$750 million USD to settle the patent litigation on Feb. 17, 2016. In the Beijing
Intellectual Property Court and the Shanghai Intellectual Property Court, Qualcomm
accused Meizu of infringing a number of Qualcomm patents covering various
smartphone features and technologies, including those related to 3G (WCDMA
and CDMA2000) and 4G (LTE) wireless communications standards. These patents
are related to radio frequency (RF) circuits. The case, which was accepted by
Hangzhou Intermediate People’s Court in Zhejiang Province, was that the (United
States) Analuo Corporation accused Hangzhou Silan Microelectronics Co., Ltd., of
infringing the exclusive right of the IC layout design. The case, which was accepted
by Shanghai Intermediate People’s Court, was that the (United States) Analuo
accused Shanghai Belling Co., Ltd. of infringing the exclusive right of IC layout
design. The case, which was judged by Nanjing Intermediate People’s Court, was
that Resources Silicon PowTech Co., Ltd. accused Nanjing Yuanzhifeng Technology
Company of infringing the exclusive right of IC layout design (one of the ten
intellectual property cases of Chinese courts in 2010). The dispute between
Shenzhen Runteng Micro Technology Co., Ltd. and Shanghai Yachang Electronic
Parts Co., Ltd. over the exclusive right of IC layout design (one of the top ten
intellectual property cases of Chinese courts in 2014), which was judged by Shang-
hai High People’s Court.
In addition, a typical case of copyright infringement includes the dispute over
copyright infringement between Microchip Technology and Shanghai Haier IC
Co., Ltd.
114 B. Xu

References
1. Accellera Systems Initiative, https://accellera.org/. Accessed 23 May 2023
2. Design & Reuse, https://www.design-reuse.com/. Accessed 23 May 2023
3. About WiLAN, http://www.wilan.com/news/news-releases/news-release-details/2015/WiLAN-
Announces-Patent-Acquisition-From-Freescale-Semiconductor/default.aspx. Accessed 23 May 23
International Competition and Cooperation
8
Guoqiang Li, Zhaozhao Xu, and Min-Hwa Chi

Contents
Customer-Owned Tooling (COT) and Foundry-Owned Tooling (FOT) . . . . . . . . . . . . . . . . . . . . . . . 116
Technology License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
IP License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Process Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Semiconductor Corporation Merge and Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Future Trend and Business Model of Foundry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Abstract
Alongside integrated circuit (IC) invention, IC chip design companies need to
own not only EDA design tools but also fabrication line, testing tools, and
packaging line. Such company is referred to as the integrated device manufacturer
(IDM). This situation lasted into the late 1980s, and then the pure-play foundry
enterprises and fabless IC design companies appeared into existence. As the
foundry model appeared, the IC industry has entered a mature stage. At this
stage, in order to realize the strategic intentions of enterprises, mergers and
acquisitions (M&A) occur one after another. At present, each sector, IC design,
manufacturing, packaging, and testing of global IC industry, is still in the process
of integration. In the next few years, M&A in global semiconductor industry will
continue to occur.

G. Li (*) · Z. Xu
Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd., Shanghai, China
e-mail: Alex.li@icwise.com.cn
M.-H. Chi
GTA Semiconductor Co., Ltd., Shanghai, China

© Publishing House of Electronics Industry 2024 115

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_8
116 G. Li et al.

Keywords
Design tools · Fabrication line · Testing tools · Packaging line · IDM · Mergers
and acquisitions

Customer-Owned Tooling (COT) and Foundry-Owned

Tooling (FOT)

In the early stage of the development of the semiconductor industry in the 1950s,
integrated circuit (IC) chip design and IC manufacturing technology were in the
exploratory stage. One company designed a certain chip, and at the same time, the
company also had to develop the corresponding fabrication technology, such as
manufacturing, testing, and packaging, to support the IC production. No one com-
pany provided manufacturing services for other companies. In addition, a process
technology may only be applicable to some IC chips, and chip design companies
engaged in similar products will be competitors. Therefore, companies engaged in
IC chips development generally have both chip design technology and chip
manufacturing technology, which is called Integrated Device Manufacturing Com-
pany (IDM). There are also a few companies that have not only design teams and
manufacturing plants but also end product development teams. Such companies are
referred to as system companies.
Global Information, Communication, Telecom, and ICT Industry, after decades of
development and accumulation, it had entered the stage of large-scale commercial
applications by 1987. Personal computers (PC) have become ubiquitous in society;
the telecommunication industry was mature, Stored Program Control (SPC)
exchange system had been widely used; the first generation of wireless communi-
cation technology was fully commercialized; and the second generation of wireless
communication technology began to be developed. The large-scale commercializa-
tion of the ICT industry benefited from the mature semiconductor industry at that
time, and its essence was the complete variety of semiconductor chips and the
complete maturity of semiconductor technology. At that time, semiconductor tech-
nologies were mostly owned by IDM, system companies, or Customer-Owned
Tooling (COT) [1]. In the era of IDM and system companies, the relationship
between IC chip design and fabrication technology was complementary and
inseparable.
This situation continued until the late 1980s, when the fabless IC design industry
was born. In order to further enhance the market competitiveness, some fabless IC
design companies have developed their own differentiated technologies, which have
become an integral part of the customer-owned technologies.
The technology research and development of pure wafer foundry enterprises has a
sequence of process from the purchase authorization to the independent research and
development. In the early stage of foundry industry, pure wafer foundry enterprises
generally purchase technologies from third-party technology research institutions or
IDM companies to establish the basis of independent technology research and
8 International Competition and Cooperation 117

development. When the process technology accumulation and R&D capability reach
a higher level, pure wafer foundry enterprises gradually carry out independent
technology research and development and gradually establish an independent tech-
nology system, such as standard cells and some IPs. These technologies are referred
to as Foundry-Owned Tooling (FOT) [2] or Foundry Model [3] and are typically
available to all or some of the company’s customers (IC chip design companies),
including current IDM companies.
The technology research and development achievements of pure wafer foundry
industry are remarkable, among which Taiwan Semiconductor Manufacturing Com-
pany (TSMC) is the typical enterprise. The main performance of TSMC is as
follows: First, it has formed the technical standard of foundry industry (T-like) and
become the industry benchmark; second, it creates the situation of providing
manufacturing services for systems-on-chip (SoC), lays a solid foundation for the
outbreak of the smart phone industry, and has strongly promoted the development of
the global semiconductor industry. At present, the application of the technology
category independently developed by pure wafer foundry enterprises has covered
most semiconductor chips, and basically only high-end memory chips (NAND and
DRAM) and CPUs are still dominated by IDM companies. In the future, the
technologies independently developed by the pure wafer foundry industry will be
expanded in several ways, including the development of advanced technologies and
the integration of various technologies, such as the integration of radio frequency
(RF) technology and embedded non-volatile memory (eNVM) technologies.

Technology License

Technology licensing in semiconductor industry mainly includes IP (Intellectual

Property) and manufacturing technology licensing.

IP License

The term IP in the semiconductor industry has two meanings: One is commonly
defined as the intellectual property (IP) right (e.g., patents); the other is a circuit
module (i.e., IP cores) with specific functions designed based on some patented
device structures or circuit topology. IPs can be reused and ported to a variety of
technology platforms, with multiple IPs often integrated in some IC chips. In this
context, the IP mainly refers to the second type.
In the early twenty-first century, with the rise of System-on-Chip (SoC) applica-
tions in mobile phone industry, the IP industry has entered a stage of rapid devel-
opment, among which the most famous IP company is ARM Holdings. After years
of development, the current IP category can cover many aspects of IC applications,
mainly used in a variety of general or dedicated processors, microprocessors,
microcontrollers (MCU), digital signal processors (DSP), and other products.
118 G. Li et al.

In terms of type, IPs mainly include library core and other IPs such as interface
IPs. Libraries mainly include Standard Cell Library, Input/Output Library (I/O),
Read Only Memory (ROM), and Random Access Memory (RAM). IP cores mainly
include embedded processor and microcontroller IPs, non-volatile memory (MVM)
IPs, power supply IPs, signal conversion IPs, and interface IPs.
Take ARM as an example. Its A-series application processor cores have been
widely used in mobile phones and other application processor products. Typical
products include Apple’s application processor in mobile phones and tablets,
Qualcomm’s/Mediatek’s/Huawei’s mobile application processors, AMD’s server
processors, etc. For the microprocessor class, take ARM again as an example. The
company’s Cortex-M series 32-bit microcontroller cores have become the main-
stream product of 32-bit microcontroller core in the current market.
Non-volatile memory IPs mainly include embedded Flash IP, one-time program-
mable (OTP) storage IP, multi-time programmable (MTP) storage IP, and embedded
EEPROM IP.
Power IPs include Power on Reset (POR) IP, Reference Voltage (Vref) IP, Voltage
Regulator (VR) IP, Low-Dropout regulator (LDO) IP, Charge Pump IP, Voltage
Detector (VD) IP, etc.
Signal conversion IPs mainly include Analog-to-Digital Converter (ADC) IP and
Digital-to-Analog Converter (DAC) IP.
There are many types of interface IP, including USB, CAN, LIN, RS-232,
RS-485, UART, HDMI, SerDes, PCIe, parallel port, and network port IPs.
There are two main IP licensing modes: purchase of “the right of use” and “one-
time buyout”. The purchase of “the right of use” refers to the cooperation mode in
which the chip design company or the semiconductor manufacturing company
purchases the verified IP from an IP owner for limited use, and the purchaser
needs to pay IP usage fee and royalty fee. IP usage fee is paid in a lump sum,
while royalty fee is charged on the basis of wafers or chips. A “one-time buyout” is a
cooperative model in which the buyer buys a verified IP address for unlimited use
from an IP owner and only pays for the IP usage. In the case of embedded
non-volatile memory (NVM) IPs, some of these IP technologies are so tightly
integrated with the fabrication process, and the purchase of IP means the purchase
of the fabrication process or even the proprietary equipment from the licensor. In this
case, the purchaser can develop a customized IP based on the licensor’s technology
to meet the specific demands of the customers.

Process Licensing

Process licenses can be divided into complete set of process licenses and process
module licenses. In terms of complete sets of process authorization, advanced
process license and differentiated process license are more common, such as
IMEC of Belgium licensed 65 nm logic process to Shanghai Huali Microelectronics.
8 International Competition and Cooperation 119

The upfront fee is similar to the royalty fee model for IP licensing, where the buyer
pays the upfront fee and/or royalty fee.

Semiconductor Corporation Merge and Acquisition

According to data released by WSTS in 2022, the growth rate of the global
semiconductor industry from 1987 to 2021 is shown in Fig. 8.1. During the
15 years from 2007 to 2021, the industry experienced negative growth in 2008,
2009, 2012, 2015, and 2019. In recent years, the growth rate of the global semicon-
ductor industry has been lower than 10% except for a few years, indicating that the
semiconductor industry has entered a mature stage.
At this stage, in order to realize some strategic intentions of the enterprises,
merger and acquisition (M&A) [4] events emerge one after another. Currently, the
design industry, the manufacturing industry, and the packaging and testing industry
in the global semiconductor industry are still consolidating, and the semiconductor
industry will continue to see mergers and acquisitions in the next few years.
Since 2014, there have been many of mergers and acquisitions in the semicon-
ductor industry. According to IC Insights, the total value of major M&A in the global
semiconductor industry in 2015 (see Fig. 8.2) reached $103.3 billion USD.
According to statistics, by 2021, mergers and acquisitions in the global semicon-
ductor industry reached a new height in 2016 (see Table 8.1). Among the top ten
mergers and acquisitions, the largest M&A is Qualcomm’s acquisition of NXP,

Fig. 8.1 Growth rate of the global semiconductor industry, 1987–2021

120 G. Li et al.

Fig. 8.2 Total annual value of major mergers and acquisitions in the global semiconductor industry
from 2010 to 2021

Table 8.1 Major M&A Number Buyer Seller Total ($B)

cases in semiconductor
1 Qualcomm NXP 470.0
industry in 2016
2 Softbank ARM 320.0
3 ADI Linear 148.0
4 Samsung Harman 80.0
5 Siemens Mentor Graphics 45.0
6 Microchip Atmel 35.6
7 Renesas Intersil 32.0
8 ASML Hermes 31.4
9 CSCEC NXP BP 27.5
10 Infineon Wolfspeed 8.5
11 CSCEC IML 1.36
12 SMIC LFoundry 0.55

valued at $47 billion USD. This set a new record in the history of global semicon-
ductor industry M&A. However, this merger was eventually called off in 2018 after
China failed to approve it. The lowest of the ten M&A deals was Beijing JAC
Capital’s $2.75 billion USD acquisition of NXP’s standard product business.
The types of M&A are generally classified into pure financial investment and
business development. Pure financial investment focuses on the return and with-
drawal of capital, and does not seek to control or change the business of the acquired
enterprises, such as SoftBank’s acquisition of ARM Holdings and Beijing JAC
capital’s acquisition of NXP’s standard product business. Business expansion
mergers and acquisitions generally integrate their own businesses and expect the
acquired target to help the existing business to achieve “1+1 > 2”, such as scale
expansion, business supplement, monopoly of a certain market, etc. Typical cases
8 International Competition and Cooperation 121

are Qualcomm’s acquisition of NXP and SMIC’s acquisition of LFoundry. The

challenge in such M&A is to integrate the acquisition object with the existing
business, including the integration of technology, management teams, and corporate
culture.

Future Trend and Business Model of Foundry

The wafer industry is expected to maintain a high growth rate of around 11% from
2016 to 2021, but the market is becoming increasingly competitive for three main
reasons.
First of all, because the wafer foundry industry has invested tremendously in
advanced process production lines over the years, the global 300 mm wafer produc-
tion capacity has expanded rapidly from 48 million wafers per month in 2012 to
62 million wafers per month in 2016. Furthermore, data released by SEMI showed
that global shipments of silicon wafers had increased by 14% year-on-year in 2021,
with total shipments reaching 14.165 billion square inches (MSI), and revenue went
up 13% year-on-year to $12.62 billion. Secondly, although the growth of the global
economy was slow, even the annual growth rate was 3.6% for 2020, a 6.52%
decline from 2015; however, from 2016 to 2021, the compound annual growth rate
(CAGR) for the global semiconductor market was 11.0%, due to a very strong
period, including the dramatic surge in DRAM and flash memory markets in 2017
and 2018, as well as the strong post-Covid recovery in 2020 and 2021. Nevertheless,
IC Insights forecasts that total semiconductor sales will rise at a more moderate
compound annual growth rate of 7.1% over the next 5 years. More semiconductor
chip demand is needed to fill the capacity expansion, but the market demand is far
below the capacity growth rate. Therefore, the fierce competition has become a fact.
Finally, because the end products or applications with high demand for emerging
semiconductor chips in the current market have not yet emerged, the existing
computer market has entered recession, and the smartphone market is increasingly
saturated, resulting in the slow growth of the semiconductor market.
To cope with market challenges and better support and serve customers, the
upstream and downstream enterprises of the semiconductor industry chain, includ-
ing wafer foundry companies, chip design companies, packaging and testing com-
panies, equipment manufacturers, IP suppliers, and end product design companies,
should establish a closer cooperation to achieve win-win situations. This is the
strategic alliance of virtual IDM models between all members of the chain. The
virtual IDM model first appeared in high-end System-on-Chip (SoC) projects, such
as Application Processor (AP), which has more than one billion transistors, includ-
ing multiple large/small processor IPs, multiple image processor IPs, embedded
memory IPs, noise reduction processor IPs, various high-speed interface Ips, and
many other IPs. It is essential to use advanced EDA design tools to accomplish these
advanced chip designs of this scale. At the same time, in order to minimize the chip
space, large capacity NAND Flash memory, DRAM memory, and application
processor are often packaged into system-in-package (SiP) types to save the space,
122 G. Li et al.

such as A-series of Apple processors. In this case, it requires the strong support of
packaging and testing vendors are required to step in, even at the design stage, to
choose the appropriate pin locations for the future packaging and testing. This is the
typical virtual IDM cooperation model. Recently, an enhanced version of virtual-
IDM business model, referred to as “Commune-IDM” (C-IDM), has been proposed,
which tightly ties the ownership of the design, the system, and the fabs together.
The market demand of China’s domestic semiconductor industry is huge. In recent
years, with the increasing demand for integrated circuits in various domestic indus-
tries, especially in memory, communication chips, various sensors, and other high-end
fields, the import quantity and amount of integrated circuit products are also soaring.
According to the 2021 annual market summary report released by China General
Administration of Customs and China Semiconductor Industry Association (CSIA),
the total IC import value was about $ 432.6 billion USD in 2021, ranking first among
overall China imported goods. Although there are many domestic chip design com-
panies, most of the chips developed by domestic companies are low-end or peripheral
supporting chips, such as various household appliances, portable products, computer
accessories, and peripheral chips of various mobile terminals and mobile phones. Only
a few are high-end or core chips, and the overall output value is low.
On the one hand, most of the domestic chip design companies have not accumulated
enough preliminary technology or application knowledge in many fields to design
high-end chips with complex functions and high reliability. At present, only a few
companies in China, such as Huawei HiSilicon and Unisoc, have made breakthroughs
in core chips of mobile phones and can design and mass produce high-end chips such
as mobile application processors and baseband processors. On the other hand, many
domestic end-product manufacturers are reluctant to use chips designed by domestic
companies. How to promote the application of domestic semiconductor chips in
domestic manufacturing industry, the virtual IDM or C-IDM enhanced cooperation
model is one of the effective measures. Domestic system manufacturers, chip design
companies, and related enterprises jointly define the required chips and apply the
required IC chips, which can promote the transformation and upgrading of domestic
manufacturing industry, promote the application of domestic chips and the develop-
ment of semiconductor industry, and achieve a win-win situation. Recently, the Huawei
Mate 60 and Mate 60 Pro/Pro+ / RS are high-end smartphone products released by
Chinese company Huawei in 2023. It uses the Kirin 9000 SoC chipset designed by
Hisilicon and produced by SMIC Foundry. Mate 60 smartphone can support satellite
network communications and 5G. It is a big breakthrough in China’s IC industry.

References
1. ASIC Model vs. COT Model, https://anysilicon.com/asic-model-vs-cot-model/. Accessed
23 May 23
2. F.C. Tseng, Foundry Technologies IEEE Xplore 06 Aug. 2002. https://doi.org/10.1109/IEDM.
1996.553030. Accessed 23 May 23
3. M. Liu, Taiwan and the foundry model. Nat. Electron. 4, 318–320 (2021)
4. Mergers & Acquisitions (Ms&As), https://en.m.wikipedia.org/wiki/Mergers_and_acquisitions.
Accessed 23 May 23
Integrated Circuit Enterprise Management
9
Ke Li, Kai Zheng, and Min Zhu

Contents
Types of IC Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
The Division of Industry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
The Segments of Semiconductor Industry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Management Structure of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Operation Management of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
The Four Aspects of IC Enterprises Operation Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
The Fields that IC Enterprise Management Must Break Through . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Production Management of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Field Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Production Support Business . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Asset Management of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Fixed Assets Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Intangible Assets Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Inventory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Monetary Capital Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Information Management of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
The Management IT System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
The Manufacturing IT System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
The IT Service System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Information Security Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
High Output Management at Intel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Three Core Concepts of “High Output Management at Intel” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Managerial Leverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Increasing Managerial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

K. Li (*)
Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China
e-mail: like@ccidconsulting.com
K. Zheng
Semiconductor Manufacturing International Corporation, Beijing, China
M. Zhu
Shanghai HLMC Co., Ltd., Shanghai, China

© Publishing House of Electronics Industry 2024 123

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_9
124 K. Li et al.

Concentrating on High-Leverage Activities and Ignoring the Rest . . . . . . . . . . . . . . . . . . . . . . . . 141

Meetings: The Medium of Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Decision-Making . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Management by Objectives and Key Results (OKRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Abstract
The IC industry has progressed rapidly for nearly 60 years. The business model of
IC industry has evolved from “all in-house” to specialty focus, which means from
the vertical integration model (e.g., IDM) to the specialty division model. The
specialty division includes fabless design house, IC manufacturing (also known
as wafer foundry), IP design and services, outsourced semiconductor assembly
and test (OSAT), etc. Organizational structure is a system established by man-
agers to effectively realize planning, organization, command, coordination, and
control. The operation management of IC enterprises can be divided into four
aspects, i.e., strategic, sales, human resources, and financial. The production
management of enterprises generally includes three parts: production process
management, enterprise logistics management, and enterprise quality manage-
ment. Asset management is an important part of enterprise management, which is
mainly divided into three parts: current asset management, fixed asset manage-
ment, and intangible asset management.

Keywords
Business model · OSAT · Organizational structure · Operation management ·
Production management · Asset management

Types of IC Companies

Since the invention of integrated circuit in 1958, after over 60 years of rapid and
sufficient development, the IC industry has changed from the initial “all-purpose”
enterprise structure model to the current structure model featuring cluster and
specialized division of work. That is, the evolution from the vertically Integrated
Device Manufacturer (IDM) [1] to the specialized division model. Specialized
division model includes no production line IC design (fabless), IP design and
services, Original Equipment Manufacturer (OEM, such as wafer OEM, Foundry),
Outsourced Semiconductor Assembly and Test (OSAT), etc.

The Division of Industry Chain

At present, the scale of IDM [2] is still dominant in the global integrated circuit
industry chain, which basically maintained at $200 billion USD from 2010 to 2015,
about 1.2 times the total revenue of Fabless, Foundry, and OSAT [3] in 2015. From
9 Integrated Circuit Enterprise Management 125

2010 to 2015, Fabless and Foundry are growing rapidly globally, with an annual
compound growth rate of 6% and 12%, respectively.

The Segments of Semiconductor Industry Chain

According to business types, IC enterprises located in the main link of the industrial
chain can be divided into integrated device manufacturers (IDMs), module manu-
facturers (MM), electronic design automation vendors (EDA) [4], chipless design
house (CDH or IP house), fabless design house (FDH), photo mask manufacturer
(PMM), open wafer foundry (OWF), outsourced semiconductor assembly and test
(OSAT), etc.

Integrated device manufacturer (IDM). An IDM refers to a company that sells its
own branded products within enterprise organization that covers the entire
manufacturing process from IC circuit design, wafer fabrication, to package and
testing. Representative companies include Intel, Samsung, SK Hynix, Micron,
Texas Instruments, Toshiba, and Infineon. Some IDM manufacturers also have
the capability of designing and manufacturing system-in-package (SiP) products.
Electronic design automation vendor (EDA). This refers to an EDA tool supplier
that provides IC design-related software tools and computer-aided design (CAD)
technology. Typical vendors include Cadence, Siemens (Mentor Graphics), Syn-
opsys, and Empyrean.
Chipless design house (or IP house). It is an enterprise that designs IP cores used in
an IC with intellectual property rights and provides corresponding services by
using process technology of wafer manufacturing. Typical enterprises include
ARM, Silicon Image, Rambus, Ceva, D&R, eMemory, etc.
Fabless design house. It specializes in design and sale of hardware devices and IC
chips while outsourcing the fabrication of IC devices to wafer foundry. Typical
enterprises include Qualcomm, Broadcom, MediaTek, Huawei HiSilicon,
Unisoc, Huada Semiconductor, and so on.
Semiconductor or IC foundry. It has been specializing in manufacturing semicon-
ductor chips for a variety of fabless companies at the same time. Typical foundry
enterprises include TSMC, Samsung, GlobalFoundries, UMC, SMIC, HLMC,
HHGrace, and so on. In addition, the wafer manufacturers provide wafer products
to these IC foundries; some top silicon wafer vendors include Shin-Etsu (Japan),
Sumco (Japan), Global Wafer (Taiwan), Siltronic (Germany), Soitec (France),
Okmetic (Finland), ZingSemi (China), etc.
Outsourced semiconductor assembly and test (OSAT). An OSAT company pro-
vides chip packaging and testing services for customers. Typical enterprises
include ASE, Amkor, SPIL, Changdian Technology, Tianshui Huatian, Fortis
Microelectronics, etc. The structure of IC industry chain is shown in Fig. 9.1.

It is worth noting that with the continuous development of the industry, there are
signs of business convergence within the upstream and downstream of the IC
126 K. Li et al.

Fig. 9.1 Structure of semiconductor industry chain

industry chain. For example, EDA suppliers, fabless design houses, and wafer
foundries also develop IP business. Some IC foundries have begun to involve
advanced packaging and testing process. In the future, the IC industry will continue
to evolve with the development of economy and technology.

Management Structure of IC Enterprises

Organizational structure is an organizational system established by managers to

effectively realize the functions of planning, organization, command, coordination,
and control. Through this system, managers can reasonably allocate the resources of
the organization and successfully accomplish the goals of the enterprise. Typical
enterprise organizational structure can be divided into linear system, linear func-
tional system, divisional system, matrix system, and so on. The current large-scale
IC enterprise usually adopts the division-based organizational structure, or a busi-
ness unit with a typical example shown in Fig. 9.2 for reference.
Functions of various organization structures of a typical business unit (BU) in
Fig. 9.1 are described as below.
The general meeting of shareholders is the highest authority of the company. It is
composed of all shareholders and makes decisions on major matters of the company.
The general meeting of shareholders shall have the power to elect, appoint, and
remove directors and shall have broad decision-making power over the operation
and management of the company.
The board of directors is elected by the general meeting of shareholders and is the
business executive organ. It is responsible for the command and management of the
business activities of the company or the enterprise. Additionally, it is also respon-
sible for reporting on its work to the general meeting of shareholders of the company
and reports on its work. The board of directors must implement the decisions made
by the general meeting of shareholders or the general meeting of staff shareholders
concerning major matters of the company or the enterprise. The board of directors is
a decision-making organization composed of directors, which controls the affairs of
the company internally and represents the company externally.
9 Integrated Circuit Enterprise Management 127

Fig. 9.2 Organizational structure of a typical business unit (BU)

The board of supervisors is composed of supervisors elected by the company’s

employees democratically. It is responsible for supervising the company’s daily
operation activities and correcting the behavior of directors, managers, and other
personnel violating the system and regulation of association. The president is the
main responsible person or administrative leader of an IC enterprise and has the right
of planning, suggestion, veto power, and scheduling for the company’s production
and operation. The president is authorized to have the right to examine and verify the
completion of the tasks by the various subordinate functional departments and have
the guiding power and examination power over the work of managers of subordinate
functional departments. In addition, the president is responsible for organizing and
coordinating the completion of the company’s annual production and operation plan
and responsible for organizing and promoting the company’s medium- and long-
term development plan. If the serious distortion of research information affects the
company’s major decisions and causes losses to the company, the president should
assume corresponding economic and administrative responsibilities.
The planning and development department mainly analyzes the development
trend of the industry and the situation of competitors, formulates the company’s
business development plan, provides strategic analysis suggestions for the decision-
making of the company’s senior management, and makes business strategies for new
businesses.
The public service department is mainly responsible for archival document
management, confidentiality, stamp management, and other work. The general
affairs department is overall in charge of the administration and general affairs of
the whole company.
The legal department mainly has three functions: the review of contract docu-
ments, the custody and management of finalized documents, and the establishment
and survival of companies. The review of contract documents mainly includes the
128 K. Li et al.

review, modification, and confirmation of all contracts, agreements, memoranda,

letters of intent, and other documents signed externally, the negotiation and consul-
tation of major documents, the review and modification of all external documents
that need to be sealed, and the collaborative review of contracts coordinated with
consultants and lawyers.
The technology research and development (R&D) department is mainly respon-
sible for the formulation of the overall technology R&D plans of the company, as
well as the R&D of new products, new technologies and new processes, the design
of technology transformation projects, the technology management of production
processes, the organization of the application of new technologies and new pro-
cesses, and technology exchange activities.
The factory operation department is mainly responsible for the production man-
agement of the IC factory, including organizing production lines and setting up
production management systems, preparing production plans, controlling produc-
tion schedule, inventory, quality, and cost, as well as ensuring customer product
delivery according to the production schedule.
The marketing department is mainly responsible for the management, supervi-
sion, coordination, and service of all sales links in the process of realizing the value
of the company’s products. Its main work includes market research, marketing
planning, preparing and organizing the implementation of annual marketing plans,
being responsible for the review and implementation of specific sales contracts
(orders), customer management and credit risk management, after-sales service
management, being responsible for the management of marketing revenue and
sales expenses, brand building, building the marketing personnel team, participating
in the preparation of the annual work report of the enterprise, responsible for
providing relevant data to the finance department, participating in the formulation
of science and technology development strategy, providing the technical department
with domestic and foreign market situation and trend analysis report, participating in
annual new product development, providing market information to technical
department, etc.
The engineering service department is fully responsible for the production sup-
port work of the wafer manufacturing factories or packaging test factories and is
generally subordinate to the factory administration, safety, environmental protection,
health department, and procurement department.
The factory affairs department is fully responsible for the water, gas, electricity,
air conditioning and clean room environment in the production process, as well as
whether the production equipment is in normal operation conditions to meet the
production requirements and ensure the normal and orderly production activities. In
addition to ensuring the normal operation of the production process, the factory
affairs department also formulates plans to reduce production costs.
The Department of Environmental Health and Safety (EHS) is mainly responsible
for the safety of the factory operation, including the fire protection system, environ-
mental protection, safety production, and other related services.
9 Integrated Circuit Enterprise Management 129

The procurement department is mainly responsible for the preparation and man-
agement of purchasing plans for equipment and raw materials needed in the pro-
duction process.
The Human Resource Management (HRM) is mainly responsible for the formu-
lation of employment system, personnel management system, employee compensa-
tion system, personnel file management system, the preparation of staff manual,
training programs, etc. At the same time, HR department implements recruitment,
training, performance, compensation, and employee relations five modules of man-
agement, to provide and cultivate qualified personnel for the company.
The logistics support department provides material services for the smooth
implementation of functions of other departments, including canteen, accommoda-
tion, cleaning, security, vehicle scheduling and management, greening, office sup-
plies, IT support, etc.

Operation Management of IC Enterprises

The Four Aspects of IC Enterprises Operation Management

The management of IC enterprises can be generally divided into strategic manage-

ment, marketing management, human resources management, and financial
management.

Strategic Management
Strategic management refers to the long-term and overall plans made by enterprises
for their survival and development based on summarizing historical experiences,
investigating the current situation, and predicting the future in the fierce market
competition environment. The most classic IC enterprise strategy is Intel’s “Tick-
Tock” strategy, also known as the “pendulum” strategy. The key to this strategy is
Intel’s 2-year cycle of product and process development. In the first year, the “Tick”
year releases CPU products manufactured on the new process. In the second year, the
“Tock” year, an improved version of the CPU is released based on the previous
year’s process. The “Tick-Tock” strategy enables Intel to continue to move forward
along Moore’s Law and gradually grow into the world’s largest IC enterprises.
However, for advanced nodes of 14 nm, 10 nm, and beyond, Intel says it will
move away from “Tick-Tock” in 2016 and take advantage of the 3-year rhythm in
process, architecture, and optimization strategy.

Marketing Management
Marketing management is the intermediate link between market demand and enter-
prise response, and it is also an important method to defeat competitors and gain
profits. Enterprise marketing activity is a systematic work, and its management
130 K. Li et al.

process should use systematic methods to find, analyze, and select market opportu-
nities, and then turn market opportunities into profitable opportunities for enter-
prises. Marketing management mainly includes identifying market opportunities
through research, selecting target markets, determining marketing mix, developing
marketing plans, as well as implementing and controlling marketing plans.
Different types of IC enterprises provide different types of products and services,
and they also face different customer situations. Fabless companies sell their IC
products to the downstream application manufacturers in the industrial chain, not
only through direct sales, but also through distributors or agents. IDM enterprises not
only sell products, but also open some capacity of production lines to other IC
manufacturers, and their customers are more complex. Foundries and OSATs pro-
vide manufacturing services to IDM or fabless, so the focus of marketing manage-
ment for these two types of IC companies is to meet customers’ process technology
requirements, ensure stable orders, and maintain high levels of capacity utilization.

Human Resource Management

Human resources refer to the total number of management personnel, technical
personnel, operation personnel, and auxiliary personnel in an enterprise. Human
resource management (HRM) refers to the planning, organization, leadership and
control of human resource acquisition, training, rational allocation of human
resources, and full use of human resources. There are seven aspects specifically
involving human resource planning management, job analysis and job design
management, enterprise recruitment and employment management, enterprise per-
formance management, enterprise compensation and welfare management, enter-
prise human training and development management, and enterprise labor relations
management.
Different types of IC enterprises have great differences in human resources alloca-
tion, and the specific management content is also different. IDM enterprises include
three main links of IC industry chain, among which the composition of human
resources is the most complex. Fabless, on the other hand, relies heavily on intellectual
workers. In addition to IC design, which including systems, circuits, and software,
fabless enterprises also recruit Application Engineers (AE) and Field Application
Engineers (FAE) to accelerate the alignment of application requirements. Especially
in recent years, fabless enterprises have increasingly hired technicians with process
and packaging backgrounds to speed up the time-to-market and better connect with
foundries and OSATs. Process yield is one of foundry’s core competencies, so in
addition to production line operators and process development engineers, foundry
companies also need a significant number of operation management personnel. In
addition, foundry companies are also increasingly hiring IC designers and IP managers
as it expands into design services alongside manufacturing. In a word, although from
the perspective of the enterprise operation, the three-core links of the industrial chain –
design, manufacturing, and packaging and testing – are developing independently, the
human resources of the three links are continuously integrated.
9 Integrated Circuit Enterprise Management 131

Financial Management
Financial management is the general term of a series of economic management
activities in which enterprises organize the capital operation and deal with financial
relations. It is an important part of enterprise operation and management, mainly
including capital raising, capital investment, capital operation, income distribution,
and financial analysis.

The Fields that IC Enterprise Management Must Break Through

In addition to many similarities with traditional enterprises, IC enterprises, as capital

and technology-intensive high-tech manufacturing enterprises, must make break-
throughs in the following areas of management.

Cost Management
At present, most IC enterprises only do the standard cost management down to the
processing layer, which means that the cost of wafer only roughly depends on the
number of mask layers. However, some enterprises have developed a special stan-
dard cost accounting process. That is, according to fixed assets budget, depreciation
of fixed assets, expense budget, master production plan, standard process flow, and
cost element apportionment method, the standard detailed cost can be calculated by
recipes. Then according to these data, combined with the actual number of fabrica-
tion steps taken by the product in the production management system, the actual
manufacturing cost of the current period can be calculated. The cost of equipment
depreciation accounts for more than 50% of the cost of integrated circuit enterprises.
And the standard cost in the operation management system can be treated as the daily
accounting, in which the formulation method is the key.

Supply Chain Management

The supply and demand as well as the input and output are the basic problems faced
by every manufacturing enterprise. Due to fluctuations caused by the business cycle,
investment in production equipment is extremely expensive, and many chemicals
and gases are involved in special procurement restrictions; therefore, it is necessary
to establish a series of management methods related to medium and long-term
strategic planning, production planning, order delivery management, calculation of
equipment processing capacity, etc., so as to support capacity planning and distri-
bution, wafer fabrication planning, order delivery, and other complete planning of
different data sources.
In addition, since most of equipment spare parts and raw materials are imported,
the quantity planning, logistics control, and inventory capital must be considered
comprehensively. For example, the technological process of different products must
be carried out according to the production plan, and alternative materials should be
considered in combination with safety stock, fixed quantity of materials, on-site
132 K. Li et al.

allowance, and other attributes of material procurement. All abovementioned factors

should be incorporated into enterprise specific material requirements planning.

B2B Data Exchange

Due to the industry characterized by an extremely high degree of automation and the
production performed according to the customer orders, this industry must convey
information of customer interest in a timely and accurate manner. Therefore, it is
necessary to establish a B2B system with the automatic data transmission mecha-
nism between enterprises and customers. A common way to do this is to provide the
real-time B2B information about Working in Process (WIP) and shipping. WIP
information enables customers to keep up to date with the production process. On
the one hand, the ship information can inform customers of actual shipping infor-
mation. On the other hand, engineering-related information can be transferred to
downstream manufacturers by customers. This not only greatly increases the speed
of delivery but also avoids human error to a certain extent.

Paperless Complex Business Processes

In the actual work of enterprises, there are many complex processes related to
business systems and production systems. The efficiency of factories and business
departments can be improved only by making complex business processes paperless,
such as process change review and management, instrument management, circulat-
ing product management, work order management, and recipe change.

Quality System Construction

There are various types of downstream manufacturers and end customers of ICs. In
order to meet the demands of different groups on product quality, it is necessary to
establish a complete quality management system, and through the third-party certi-
fication, such as ISO 9001, ISO 27001, TS 16949, etc. At the same time, full
attention should be paid to the management of all business secrets, such as enter-
prise’s independent patents, design intellectual property rights (IP), and indepen-
dently developed software.

Production Management of IC Enterprises

The production management of enterprises generally includes production process

management, enterprise logistics management, and enterprise quality management.
For IC enterprises, IDMs, foundries, and OSATs are the main enterprise types to
manufacture IC products. Integrated circuit production management refers to the
production activities formed by planning, organizing, directing, supervising, and
adjusting related resources according to the established goals of the company. Its
goal is to minimize costs and maximize output under the premise of ensuring safety
and quality. IC production management includes clean room safety management,
9 Integrated Circuit Enterprise Management 133

clean room personnel protocol management, production equipment operation man-

agement, online product management (on-time delivery, exceptional handling), lean
production, automatic production scheduling, etc.
Integrated circuit production management is generally divided into three major
businesses, namely, security business, on-site production business, and production
support business. Integrated circuit enterprises usually run 24 h a day throughout the
year. According to the working hours, the production management department is
divided into shift personnel (4 shifts and 2 operations) and daily personnel.

Security

The security service refers to the full-time security manager and online security
personnel. Through the connection with the company-level security department, to
ensure the production line is under safe operation by full-time online security
personnel for 24 h a day. The largest investment in the integrated circuit industry
is concentrated in the clean room, so the safe operation of the clean room is the most
important, because every small security risk may cause huge losses.
The safety team is organized by the production line employees, who are more
familiar with the site and have shorter response time for abnormal situations, so that
the hidden dangers can be eliminated as soon as possible to avoid greater losses later.
The security personnel shall consist of one daily staff member and at least one
security officer per shift.

Field Production

The main responsibility of the field production operation is to manage all the
machines and products on site by adopting the “4 shifts and 2 operations” mode.
The clean room area is relatively large, usually 10,000 ~ 30,000 m2, generally
grouped and managed by process module, usually divided into photography, etch-
ing, cleaning, diffusion, ion implantation, chemical vapor deposition, metallization,
planarization, copper process, and in-out inspection. There are 1–2 on-duty man-
agers for each shift and 1 team leader for each district. Employees are usually
calculated according to the man-machine ratio. The man-machine ratio of automatic
production line is 1:10, and that of semi-automatic production line is 1:3. Usually,
the staff is responsible for the basic 6S work in their team area, monitoring the
machine status and product processing status, managing non-product silicon wafers,
contacting and informing abnormal problems, and accepting special treatment as
instructed by the engineering department. Semi-automatic production lines need to
perform the wafer lot handling according to the production control requirements,
while automatic production lines only need to supervise the processing sequence of
wafer lot handling in equipment.
134 K. Li et al.

Production Support Business

Production support services include employee qualification training, assessment and

certification, automated production control, lean production promotion, as well as
production planning and on-time delivery for order (OTDO) control.

Employee Qualification Training, Assessment, and Certification

A complete operator training system and electronic assessment process shall be
established to ensure that each operator has been fully certified before working in the
production line and should be re-certified annually.

Automatic Production Control

Integrated circuit enterprises generally adopt information-based production manage-
ment system, including enterprise resource planning (ERP), manufacturing execu-
tion system (MES), automatic material handling system (AMHS), equipment
automation program (EAP), automatic process control system (APC/FDC/SPC),
real-time dispatcher (RTD), etc. Through the pre-programmed standard process
flow, the information of product to be processed, as well as EAP/APC/FDC/SPC
online equipment status and process parameters, will be fed back to MES system in
real-time. After the operation of the RTD system, the assign production tasks will be
delivered to the AMHS and EAP system of equipment to achieve the automation and
standardization of manufacturing process, seek the optimal solutions of manufactur-
ing process, and provide reasonable product scheduling algorithms for the produc-
tion real-time dispatching system.

Lean Production Promotion

Through the integration of big data, systems, and platforms, the data sharing within
the enterprise can be achieved to identify bottleneck equipment in production lines
and then make the capacity improvement request to equipment, process, and engi-
neering departments.

Production Planning and OTDO Control

According to the balance of customers’ orders and production lines, the planning
department and sales department of the counterpart company promise the delivery
date and quantity of orders to customers, ensure that products are put in place, and
timely deal with all kinds of urgent needs of customers and abnormal situations of
production lines.

Asset Management of IC Enterprises

Asset management is an important part of enterprise management, which is mainly

divided into three parts: current asset management, fixed asset management, and
intangible asset management. The asset management of IC enterprises refers to that
such enterprises aim at improving the utilization rate of assets and reducing
9 Integrated Circuit Enterprise Management 135

operating costs, based on enterprise information management system, to implement

the whole process management from requisition, purchase, acceptance, use, and
maintenance to scrapping of the enterprise-owned assets, including physical assets
management and the value of the asset management. Physical asset management is
usually led by the finance department or a separate asset management department,
and is jointly implemented by the procurement department, production planning
department, equipment management department, warehouse management depart-
ment, and manufacturing department. The asset value management is the responsi-
bility of the finance department.
In terms of asset types, IC enterprise asset management can be divided into fixed
asset management, intangible asset management, inventory management, and mon-
etary fund asset management.

Fixed Assets Management

The fixed assets of integrated circuit enterprises usually include machinery and
equipment, power systems, tools and appliances, and office equipment. IC equip-
ment is usually very valuable. The equipment investment of an advanced integrated
circuit production line is usually more than ¥10 billion RMB or even more than tens
of billions of RMB. Therefore, the management of fixed assets is an important part of
asset management of IC enterprises.
From the management practice of fixed assets in integrated circuit enterprises, the
first is to reasonably define the standard classification of fixed assets. The accounting
standards for enterprises issued by the Ministry of Finance no longer specify the
value standard of fixed assets. Therefore, it is necessary for enterprises to reasonably
define the classification standard of fixed assets according to the value, service
lifetime, use mode, and other factors of assets, taking into account the objectives
and efficiency of asset management in accordance with the principle of importance.
A fully covered fixed assets management system should be established. In order
to meet the refined requirements of IC enterprises for asset management and ensure
the implementation of asset management responsibilities, enterprises need to com-
bine their own organizational structure, according to the principle of management
responsibility without blind spots, with the help of enterprise management informa-
tion system (ERP), to establish a full coverage of fixed asset management system.

Intangible Assets Management

As a technology-intensive industry, integrated circuit enterprises usually have a large

number of intangible assets, including patent rights, non-patented technologies,
concessions, etc. Once the occurrence of intellectual property disputes, it will
cause huge losses to enterprises. Therefore, integrated circuit enterprises need to
attach great importance to the management of these assets without physical form,
especially to pay attention to the correct maintenance and use management of
136 K. Li et al.

intangible assets. Enterprises can set up specific departments responsible for the
management according to the category of intangible assets. For independently
researched and developed self-intangible assets, the whole process management
covering project approval, implementation tracking, achievement evaluation, patent
examination, and other links shall be established. For the purchased intangible
assets, the whole process management covering procurement examination and
approval, acceptance, use management, and other links shall be established.

Inventory Management

Inventories refer to the finished products or commodities held by the enterprise in its
daily sales activities, products in the process of production, and materials consumed
in the production process or materials for providing services. IC enterprises consume
many kinds of materials and materials in the production process, some of which also
need to be imported. There are many varieties of finished products and products in
the production process, and each product has many production steps. Once the
supply of raw materials is interrupted (commonly known as “raw material break-
age”), the loss will be huge. Therefore, there is a high demand for inventory
management. The objective of inventory management is to reduce the inventory
cost and the capital occupation as much as possible under the premise of ensuring
smooth production and operation. For the materials consumed in the production
process, integrated circuit enterprises usually set up the special materials manage-
ment department, together with the production planning department, procurement
department, manufacturing department, etc., according to the regularly updated
production plan, to dynamically adjust materials procurement and arrival plans.
For finished and semi-finished products, they are usually managed and monitored
dynamically by the production planning department.

Monetary Capital Management

Monetary capital usually includes cash assets (cash, bank deposits, etc.) and quasi-
cash assets (marketable securities, accounts receivable, etc.). The objectives of the
monetary capital management of IC enterprises are basically the same as that of other
enterprises, that is, on the premise of ensuring the turnover and security of monetary
capital, to improve the benefit of monetary capital as much as possible.

Information Management of IC Enterprises

Enterprise information management refers to the collection, processing, input, and

output of information. The ultimate goal of information management is to improve the
utilization efficiency of enterprise and social resources. The main contents of enter-
prise information management include formulating information planning, collecting
9 Integrated Circuit Enterprise Management 137

Fig. 9.3 Enterprise information management architecture

information, processing information, storing information, maintaining information,

and outputting information. The construction of informatization for IC enterprises
refers to the process in which enterprises continuously improve the efficiency and level
of production, operation, management, and decision-making by using a series of
modern technologies, such as computer technology and network technology, through
the development and utilization of information resources, so as to improve the
economic benefits and competitiveness of enterprises. As shown in Fig. 9.3, the
information management structure of chip manufacturing enterprises mainly includes
four systems that are management information technology, manufacturing information
technology, information technology service, and information security.

The Management IT System

The functions of management information technology system in enterprises mainly

include administration management, business management, customer relationship
management, accounting system management, planning system management, pro-
curement system management, data application integration, and so on.

The Manufacturing IT System

Manufacturing information technology system mainly refers to the automatic man-

agement system of production chain, including the manufacturing execution system,
the equipment automatic control system, and the engineering data analysis system.
The manufacturing process of integrated circuit chip is many and complicated. Dozens
or even hundreds of products run on the production line every day. A large amount of
138 K. Li et al.

data will be generated in the manufacturing process, including the data reflecting the
state of the production equipment, the data reflecting the parameters of product
performance, and the data reflecting the yield. At the same time, due to the particularity
of semiconductor chip production, the production management of the whole factory is
not only responsible for the automation control of the whole production process, but
also responsible for the automation control of each equipment and its connection with
the manufacturing execution system. In addition, a large number of regular reports
should be provided to management and engineers to monitor the production line.
Therefore, this makes the whole factory production management system face with
real-time, accuracy, stability, high automation, and other requirements.

(a) The Manufacturing Execution System (MES) is mainly responsible for

manufacturing system architecture design, project management, development,
and maintenance, to achieve continuous improvement of production efficiency
and quality, assist in production cost control, and support the achievement of key
performance indicator (KPI). It mainly involves workflow, real-time dispatch
(RTD), simulation-based scheduling (SBS), statistical process control (SPC),
plant management system (PMS), equipment constraint system (ECS), and
alarm management system (AMS).
(b) The equipment automation control system mainly involves the integration of
advanced process control (APC), fault detection and classification (FDC), recipe
management system (RMS), automatic material handling system (AMHS),
equipment automation program (EAP), and manufacturing execution systems
(MES). The basic workflow includes:
① To collect, analyze, and confirm user’s requirements for the equipment
automation system
② To analyze, inspect, and verify the characteristics and functions of the
equipment
③ To perform the program development, testing, and user interface design of
the equipment automation system
④ To conduct online testing of equipment automation systems and equipment
⑤ To deploy the equipment automation system on the associated equipment
(c) The engineering data analysis system provides professional and efficient reli-
ability system solutions for the plant process integration department,
manufacturing department, and quality control reliability department. Mean-
while, this system provides timely and reliable system support and services for
customer’s production schedules and process monitoring yield data require-
ments, as well as provides professional and reliable data support for product
shipment and quality analysis.

The IT Service System

The information technology (IT) service system mainly provides efficient, safe,
and stable office information system for enterprise users by integrating and
improving internal resources according to the business development requirements
9 Integrated Circuit Enterprise Management 139

of the company. Furthermore, the IT service system will provide 24 h a day

(7D/24 h) hardware and software services for enterprise users and production
systems to ensure timely, rapid, and efficient quality of service. Main missions
are described below:

① To maintain the daily operation of the database and deal with the related faults of
the database to ensure the normal operation of each system and ensure the
reliability of the system operation
② To maintain the daily operation of the system platform, the database, backup
systems, and troubleshoot the related software and hardware failures of IT
systems to ensure the normal operation of each system and improve the reliability
of the system operation
③ To plan, supervise, and control the infrastructure of data voice communication
services so as to ensure the security, efficiency, and stability of data voice
communication services
④ To monitor, maintain, troubleshoot, back up, and restore the network and
communication systems to ensure high availability of the network systems
⑤ To analyze and optimize network and communication systems to ensure the good
performance of systems

Information Security Systems

Information security system (ISS) mainly involves the design, development, and
maintenance of information security system architecture. There are two key points:
one is to guard against external invasion, such as viruses, hackers, and malicious
software, so as to prevent from internal communication system and production
management system paralysis. Second, to prevent internal leakage of semiconductor
enterprises’ production processes, production recipes, production test data, etc.
Security operations are required; and only authorized personnel can carry out
relevant operations.

High Output Management at Intel

Dr. Andrew Grove is one of the founders of Intel. As the CEO from 1987 to 1997, he
increased the company’s market value from $4 billion to nearly $200 billion with
64,000 employees. In other words, he was in the big leagues of Intel Cooperation. He
is considered one of the best CEOs in Silicon Valley. Of all the management books
he had read over the years, his favorite is The Practice of Management, written in
1954 by Peter Drucker, the legendary Master of Management Theory [5]. As Intel
was founded, organized, and managed, Dr. Grove found that all Intel employees
“produced” in some sense – some made chips, others prepared bills, and still others
created software designs or advertising documents.
He also found that when we approached any work done at Intel with this basic
understanding in mind, the principles and discipline of production gave us a
140 K. Li et al.

systematic way to manage, just as the language and concepts of finance created a
universal approach to evaluate and manage investments. Based on his 20 years of
management work in semiconductor industry, Dr. Grove introduced Intel’s man-
agement methods in his famous book High Output Management [6]. The most
important sentence in his book is that the output of a manager is the output of the
organizational units under his supervision or influence [7]. The high output
management consists of three core concepts.

Three Core Concepts of “High Output Management at Intel”

1. You can apply the principles and discipline of IC manufacturing to management.

2. Intel’s work is done by teams, not individuals.
3. Teams only perform well when they elicit the best performance from their
members.

Managerial Leverage

As a manager, your output is equal to the output of your organization plus the output
of neighboring organizations you influence. Output can be positively or negatively
affected through one or more of the five management activities:

1. Information-gathering: Reading reports, customer complaints, or memos

and talking to people inside and outside the organization. This is where all
other management work is based and where you should spend the most of
your time.
2. Information-giving: Transferring knowledge to members of your team and
groups you influence. In addition to facts, you must communicate objectives,
priorities, and preferences. This is extremely important because subordinates
need the context to know how to make their own decisions.
3. Decision-making: Sometimes, you’ll make a decision. Prefer to participate in
decision-making by providing input, promoting better choices, reviewing deci-
sions, and providing feedback. Decision-making comes in two forms: proactive
decision-making (identifying a set of activities) and response to developing
problems, which may be technical or may involve people.
4. Nudging: You should not always provide instruction but push people in a
preferred direction of action.
5. Role modeling: You are a role model for your organization, your subordinates,
your peers, and even your supervisors.

All these activities can improve output, but you need to spend your time where
the leverage is the greatest. For some, this is in large groups. For others, one-on-one
is the best in a quieter, more intellectual environment.
9 Integrated Circuit Enterprise Management 141

Increasing Managerial Output

For every activity you perform, the output of your organization should increase by a
certain degree. The extent to which it increases is determined by leverage. Leverage
is a measure of the output generated by a given activity. The higher the leverage, the
more output a given activity produces. But not all activities raise output and doing
more may often reduce output. That is why the key to raising output lies in increasing
leverage, not economic activity.
In summary, you can increase management efficiency in three ways:

1. By doing things faster

2. By improving the leverage of existing activities
3. By shifting the activity portfolio from low leverage to high leverage

High-leverage activities include:

• To affect many people

• To change a person’s activity or behavior due to a brief interaction over a long
period of time
• To influence the work of a large team by providing critical information

Concentrating on High-Leverage Activities and Ignoring the Rest

Delegating as Leverage
When you delegate tasks, you are still responsible for getting them done. Supervis-
ing delegated tasks is the only practical way to ensure this. And it is easier to monitor
what you know, so if you have a choice, delegate what you know best. As with any
production flow, it is monitored at lowest-value stage. Furthermore, it is better to
review rough drafts, not final reports.
The second principle we have borrowed from IC production is variable inspec-
tion. Different sampling rates are applied to different subordinates. How often you
check should be based on your subordinate’s maturity relative to the task, not what
you think they can do in general. As the mission-related maturity of your subordinate
increases, you will monitor less often.
Finally, enter details randomly. To check everything is like stopping the product
line and check for faults. Remember, always choose in-process testing, not stop-
production testing.

Production Principles for Time Management

As a manager, most of your time is focused on the allocation of resources: manpower,
money, and capital. But the most important resource you can allocate is your own time.
Your time is your only truly limited resource. Improving the way you spend your time
is the most important thing you can do to make yourself more productive.
142 K. Li et al.

You can use production principles to better manage your time:

(a) Identify the limiting step: Determine what is immovable and manipulate it with
more flexible activities.
(b) Batch similar tasks: Everything requires some mental preparation. Effective
work relies on grouping related activities.
(c) Build forecasts: Most of your work is prediction-based, and the medium is your
calendar. Most people use the calendar as a place to receive orders. You should
use it as a production planning tool. Schedule non-time pressing tasks between a
limiting number of steps each day. Just as factory managers refuse to take on
extra work when the factory is at capacity, you should also refuse to take on tasks
that overload your system.
(d) Say no earlier: Stop working before things get more expensive.
(e) Allow slack in your schedule: One distraction should not ruin your whole day.
(f) Keep the original list: In the form of projects that do not need to be completed
now but can improve your team’s productivity in the long run. This also prevents
you from interfering in the work of your subordinates.
(g) Standardization: At the same time continue to think critically about what you do
and the methods you use.

Meetings: The Medium of Management

Meetings are just a medium for management. You need to choose the most influen-
tial medium to achieve your goals.
Meetings fall into two categories: Category 1: Process-oriented. These meetings
are held regularly to facilitate knowledge sharing and information exchange. Cate-
gory 2: Mission-oriented. These special meetings aim to resolve specific issues by
making decisions.

Category 1: Process-Oriented Meetings

The goal of regular process-oriented meetings is to improve efficiency. Partici-
pants should know how the meeting will be conducted, what important issues will
be discussed, and what the goals of the meeting will be. This ensures that the
meeting has a minimal impact on output. There are three types of process-
oriented meetings:

1. One-on-one: Meet with you and report back directly.

2. Staff meetings: Meetings with you and all your direct subordinates.
3. Operational reviews: You can meet people there that you do not usually see.
Operational reviews should include formal presentations in which managers
describe their work to other managers who are not directly responsible, as well
as colleagues in other parts of the company.
9 Integrated Circuit Enterprise Management 143

One-on-one: At Intel, one-on-one is a meeting between you and your direct

subordinates. It is the primary way to maintain and deepen your relationship. They
can be incredible high impact, as the amount of time you spend together can affect
the subordinate’s work for weeks. The main purpose of one-to-one is mutual
teaching and information exchange. You pass on your skills, know-how, and
problem-solving advice to your team members, while they provide information
about what they are doing and what they care about.
One-on-one arrangements are based on the job- or task-related maturity of each
subordinate. Always meet one-on-one (once a week) with those who are less
experienced in the given situation, and reduce the number of meetings to, say,
once a month for experienced veterans. You should reserve at least an hour for the
meeting. Anything meeting less an hour tends to limit people to simple problems that
can be solved quickly. The key thing to understand is that one-on-one meetings are
reporting meetings. They should set the tone and agenda. This increases your
leverage because you do not have to plan for every direct subordinate. It is also
important because it forces your subordinates to think ahead what they want to talk
about. Meetings usually begin by reporting on management metrics, such as order
rates, production output, or project status. Watch for signs of trouble. You should
also cover anything important that has happened since the last meeting: recruitment
issues, staffing issues, organizational issues, and new initiatives. The criterion for
inclusion is whether the issue is bothering your subordinates. Your role is to learn
and mentor. When they stop talking about a topic, ask another question until you feel
you have got to the root of the problem.
You should all have a copy of the agenda and take notes. Note-taking promotes
active listening and ensures that the action requested by either party is not lost.
Consider using a “hold” file where you can accumulate essential but not urgent
issues for future discussion. Encourage heart-to-heart conversations where possible.
One-on-one is a great place to tackle subtle issues at work. Scheduling regular one-
on-one interviews is a good practice. Set the next task to the end of current task so
that other tasks can be easily explained and cancelled.
Staff meetings: Staff meetings include you and your team members, and allow
for interaction between colleagues, as they are in an ideal place for decision-making.
Anything that affects more than two people is fair game. If something deteriorates
into a conversation between two people, end it and move on to something that affects
more people. It is recommended that two people make separate appointments to
discuss the meeting.
Staff meetings should be relatively compact, with an agenda prepared in
advance so that everyone has a chance to prepare. You should also include irregular
times so that people can ask whatever questions they want. If necessary, matters
raised at irregular time can become part of the agenda for future meetings. Your
role is to be the leader, observer, facilitator, questioner, and decision-maker when
necessary. But ideally, you just keep things on track while your team works
issues out.
144 K. Li et al.

Operation reviews: Operation reviews are the interactive media for those who do
not have the opportunity to meet. They allow employees at different organizational
levels to teach and learn from each other.
Operation reviews involve four groups:

1. Organizing managers: They help speakers decide what issues and details to
present, book meetings, and are timekeepers.
2. Review managers: The review manager is usually a senior management person.
They ask questions, offer opinions, and are role models for junior managers in
the room.
3. The presenters: The presenter spends 4 min for each slide presentation and
discussion, using visual aids where possible.
4. The audience: Audience participation is the key, so they should ask questions and
make comments.

Category 2: Mission-Oriented Meetings

Mission-oriented meetings are designed to produce concrete outputs, such as deci-
sions. The key to their success is the chairperson, who has the biggest stake in
the outcome. Mission-oriented meetings are held for a specific purpose. If you call
the meeting, you are responsible for the logistics, arranging the agenda, and writing
the minutes. Once the meeting is over, you must share the minutes quickly before the
participants forget what happened. They should be as clear and specific as possible,
telling the reader what was decided, who did it, and when. You need to get attendees
to finish the minutes as quickly, so they don’t forget what happened.
In practice, 80% of problems should be solved in daily meetings. Ad-hoc
meetings are needed to deal with the rest. A special session is needed to deal with
the remaining issues. If you spend more than 25% of your time in impromptu
meetings, that is a sign of poor organization.

Decision-Making

Participation in the decision-making process is an essential part of management.

Traditionally, the chain of command has been precisely defined, and a person’s
ability to make decisions is determined by his position on the organizational chart.
Today, businesses deal mainly with information and technology. This can lead to a
large gap between one person’s power based on position and another person’s power
based on knowledge. Increasingly, people at the top of companies are not suited to
making decisions. Subordinates usually have a better idea of the right solution. They
are closer to the problem, immersed in it every day.
The faster the business changes, the greater the divergence between knowledge
and position power will be. As a manager, your job is to make sure the best decisions
are made, not to make them alone.
The ideal decision-making processes: The ideal decision-making process
begins with free discussion and open debates of all perspectives and aspects of the
9 Integrated Circuit Enterprise Management 145

issue. The greater the disagreement, the more important it is to have free discussion.
When things get heated, people tend to hang back and wait for the possible outcome.
Once they know, they support the idea and avoid being associated with a losing
position. All these outcomes are bad decisions because knowledgeable people
reserve their opinions to themselves and whatever decisions are made are based on
potentially incomplete information and insights. A good way to avoid this is to have
the most junior person state their opinion first.
The next step is to make a clear decision. Again, the greater the disagreement, the
more important this step is. You need to communicate your decision clearly and
make sure everyone understands it.
Once a decision is made, everyone must be on board. Not everyone has to agree
that it is the right decision, as long as they commit to supporting it. The bottom line
is, disagree but a commitment to support.
This process may seem simple, but it is more acceptable in theory than in practice.
It is hard to express your viewpoints forcefully and make unpleasant decisions, and
even against groups. But it pays to make the best decision.
When decisions need to be made, the senior people who have been guiding,
mentoring, and driving the team must make decisions. If the ideal decision-making
process has been followed, the decision-maker has heard all points of view, facts,
opinions, and judgments and has the information needed to make the decision. Like
all other management activities, focus on output which in this case is the decision-
making.

Management by Objectives and Key Results (OKRs)

Finally, we should mention Management by Objectives and Key results (OKRs)

system, which was invented by Intel management team and widely used by Silicon
Valley’s top technology companies [2–4]. At Intel, it is called Intel Management by
Objectives (IMBO). Once the requirements are defined and the plan is completed,
you can use management by objectives and key results (OKRs). The idea behind
OKRs is simple: if you don’t know where you’re going, you are not going to get
there.
To use OKRs successfully, you need to answer two questions:

1. Where do I want to go? The answers provide your objective.

2. How will I know if I get there? This gives you your key results.

The purpose of OKRs is to provide feedback related to the task at hand, telling
you how you are doing and whether adjustments need to be made. In order for
feedback to be effective, you need to receive it as soon as possible. Therefore, the
OKRs setup time should be relatively short. If you plan for a year, you should set a
quarterly or even monthly OKRs.
Minimize the number of goals. If you focus on everything, you may focus on
nothing. A few carefully selected OKRs can make the system work.
146 K. Li et al.

References
1. IDM, https://semiengineering.com/knowledge_centers/manufacturing/integrated-device-manu
facturer-idm/. Accessed 23 May 2023
2. I. Cutress, Intel’s New IDM 2.0 Strategy. 23 Mar. 2021. https://www.anandtech.com/show/
16573/intels-new-strategy-20b-for-two-fabs-meteor-lake-7nm-tiles-new-foundry-services-ibm-
collaboration-return-of-idf. Accessed 23 May 2023
3. OSAT: Top 10 OSAT Companies in World, https://www.marketresearchreports.com/blog/2019/
04/24/top-10-osat-companies-world. Accessed 23 May 2023
4. EDA: List of EDA companies, https://en.wikipedia.org/wiki/List_of_EDA_companies.
Accessed 23 May 2023
5. P.F. Drucker, The Practice of Management, Reissue edn. (Harper Business, 2006). ISBN-10:
0060878975, ISBN-13: 978-0060878979
6. S. Andrew, Grove, High Output Management (Vintage Books, A Division of Random House,
Inc., New York, 1995)
7. J.Z. Xie, C. Damin, The Big Bang of Chip, Chinese edn. (Shanghai Publishing Group of Science
and Technology, 2018). ISBN-10: 7547840760, ISBN-13: 978-7547840764
Talent Cultivation
10
Ke Li, Yong-Wen Wang, Yumei Zhou, and Chun-Zhang Chen

Contents
Development of Modern Science Education . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Training of IC Talents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Talent Needs of Semiconductor Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Abstract
The essence of competition in comprehensive national strength is the competition
in integrated circuit (IC) talents. At present, the rapid development of China’s IC
industry is in urgent need of a large number of IC professionals and specialists.
Since 2000, China has published a series of policies to strengthen the effort in
training IC talents or professionals, and to promote the development of micro-
electronics discipline. Around the strategic development and talent demand of the
IC industry, the talent training in the IC industry is characterized by the combi-
nation of the national policy guidance and the market mechanism.

Keywords
IC talents · IC professionals · Training · Policy guidance · Market mechanism

K. Li (*)
Department of Integrated Circuits (IC), CCID Consulting Co., Ltd., Beijing, China
e-mail: like@ccidconsulting.com
Y.-W. Wang
Institute of Microelectronics, Peking University, Beijing, China
Y. Zhou
Institute of Microelectronics, Chinese Academy of Science, Beijing, China
C.-Z. Chen
Peng Cheng Lab, Shenzhen, China

© Publishing House of Electronics Industry 2024 147

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_10
148 K. Li et al.

Development of Modern Science Education

The essence of competition in comprehensive national strength is the competition for

talents. Hu Yuan, a scholar of the Song Dynasty in China, wrote in his Songzi County
Study Notes that “The governance of the world depends on talents, the cultivation of
talents depends on education, and the school is the foundation of education.” The
reason why China failed to keep up with the pace of the first and second industrial
revolutions is mostly due to a lack of science education.
From 1776 when James Watt made the first practical steam engine to 1906 when
radio broadcasting was implemented, the period of 130 years witnessed the vigorous
development of natural science and technological inventions, and the transition of
human society from agricultural society to machine society and further to electric
society. At the same time, the Qing Dynasty of China gradually declined from strong
to weak. In 130 years, a wave of advancements of natural sciences and technologies
was emerged, but China’s performance was lackluster in this wave. The suite of
Confucianism Four Books and Five Classics was still regarded as the supreme
principle and guidance of the government rulers, while the concepts of “studying
the science of things” that could increase social wealth, enhance the efficiency of
production, and improve people’s lives were disdained. During the 130 years in
China, when those scholars who planned to go to Beijing to take the examinations
were still reading at night under candlelight, but western electric power had already
lit up people’s lives. While Chinese soldiers and local warriors still opened the way
for officials wearing feathers in sedan chairs, European cars and airplanes had
already become the new favorite means of transport. When the Chinese rich flaunted
their wealth in silks and satins, synthetic fabrics and dyes have made their way into
history. While military messages were still being sent by horses in the Qing Dynasty
of China, the transatlantic telegraph was already actively used in the West. These big
differences in concept and social life are the main cause of China’s weak national
situation in the past centuries. Only education can change the past decadent situation.
University education has nurtured pioneers in various fields for the Renaissance
and Industrial Revolution. Some milestones are described below:

1088: The University of Bologna was established in Italy. It was declared the
“Mother of the University” (Alma Mater Studiorum) in the “European University
Charter” by 430 universities in Europe. Three masters of the Renaissance:
Leonardo da Vince, Michelangelo (Buonarroti), and Raphael (Raffaello Sanzio
da Urbino), scientist Galileo Galilei, and astronomer Nicolaus Copernicus all
studied at the University of Bologna.
1209: The University of Cambridge was founded. Among the well-known alumni
included scientists Isaac Newton, Charles Darwin, Francis Bacon, James Clerk
Maxwell, Ernest Rutherford, and Stephen Hawking, economist John Maynard
Keynes, and philosopher Bertrand Russell.
1257: University of Paris (Université de Paris) was founded. Among the well-known
alumni were physicists Pierre Curie, Madam Marie Curie, and Louis de Broglie.
10 Talent Cultivation 149

1472: The University of Munich (Ludwig-Maximilians-Universität München) was

founded. Among the famous alumni included physics masters Wilhelm Conrad
Roentgen, Wilhelm Wien, Wolfgang Pauli, Max Planck, Heinrich Rudolf Hertz,
and Werner Karl Heisenberg, chemists Adolf von Bayer, and Peter Debye.
1724: St. Petersburg University (Saint-Petersburg State University) was established.
Among the well-known alumni included chemist Dmitri Mendeleev, radio inven-
tor Alexander Popov, biologist Ivan Pavlov, writers Nikolai Gogol, Ivan Turge-
nev, and Nikolai Chernyshevsky. Both Vladimir Lenin and Vladimir Putin
studied at St. Petersburg University.
1734: Göttingen University (Georg-August-University of Göttingen) was
established. Among the well-known alumni were mathematicians Carl Friedrich
Gauss (Gauß) and Bernhard Riemann, physicist J. Robert Oppenheimer, and
Enrico Fermi. The famous Chinese students were Zhu De, Ji Xianlin, and
Ganchang Wang.
1740: The University of Pennsylvania was founded. Among the well-known Chi-
nese alumni were architect Phyllis Lin (a.k.a. Lin Huiyin) and semiconductor
material expert Lin Lanying.
1754: Columbia University was established. Among the well-known Chinese
alumni included physicists Tsung-Dao Lee (Li Zhengdao in pinyin) and Wu
Chien-Shiung (Wu Jianxiong in pinyin), poet Xu Zhimo, scholar Wen Yiduo,
educator Tao Xingzhi, philosopher Feng Youlan, Peking University former pres-
ident Jiang Menglin, and Hu Shi, chemist Hou Debang, and Tang Aoqing.
1810: Humboldt University of Berlin (Humboldt-Universität zu Berlin) was
established. Among the well-known alumni included physics masters Gabriel
Lippmann, Wernher von Braun, Albert Einstein, Erwin Schrödinger, and Max
Born (teacher of Huang Kun), mathematics masters John von Neumann, philos-
opher Georg Wilhelm Friedrich Hegel, Ludwig Feuerbach, and poet Heinrich
Heine. Karl Marx and Friedrich Engels studied at Humboldt University. Among
the famous Chinese students at Humboldt University included Zhou Enlai,
physicist Wang Ganchang, geophysicist Zhao Jiuzhang, and historian Fu Sinian.
1826: University College London (UCL) was established. Among the well-known
alumni were telephone inventor Alexander Graham Bell, vacuum tube inventor
John Ambrose Fleming, fiber inventor Charles Kuen Kao (Gao Kun in pinyin), and
former dean of the Chinese Academy of Sciences Chia-Si Lu (Lu Jiaxi in pinyin).
1861: The Massachusetts Institute of Technology (MIT) was established. Among the
well-known alumni included physicist Samuel Chad-chung Ting (Ding
Zhaozhong in pinyin), former UN Secretary-General Kofi Annan, scientist Qian
Xuesen (also spelt as Tsien Hsue-shen), architect Pei Ieoh Ming (I. M. Pei),
semiconductor physicist Xie Xide, founder of IC foundry model Zhang
Zhongmou (Morries Zhang), and electronics scientist Ge Shouren.
1868: The University of California, Berkeley (UCB), was established. Among the
well-known alumni were historian Jian Bozan, founder of Moore’s Law Gordon
Moore, and mathematics master Cheng-sheng Chen.
1895: Beiyang University (predecessor of Tianjin University) was established.
150 K. Li et al.

1898: Peking University, China’s first national multi-disciplinary comprehensive

university, was established.
1911: Tsinghua University was founded by using Gengzi indemnity (Boxer
indemnity).

From the University of Bologna (in 1088) to Beiyang University (in 1895),
8 centuries (807 years) passed. From 1609, when Galileo, the pioneer of experimen-
tal physics, observed celestial bodies through a telescope and denied the “Geocentric
theory,” to 1905, when the Qing Dynasty abolished the imperial examination
system, China abandoned “Science” for nearly 300 years. The backwardness of
China’s science leads to its economic decline, which in turn leads to military
weakness. Then the fate of being bullied and slaughtered is inevitable.

Training of IC Talents

Around the strategic development and talent demand of the IC industry, the talent
training in the IC industry is characterized by the combination of national policy
guidance and market mechanism.
Since 2000, the Ministry of Science and Technology has approved the establish-
ment of eight national IC design industrialization bases in Beijing, Shanghai,
Shenzhen, Wuxi, Guangzhou, Xi’an, Chengdu, Jinan, and other regions with certain
advantages in scientific research, education, industry, and talents. Through years of
development, each base has established a certain basic IC design technology service
platform, in addition to carrying out technical services, but also carry out personnel
training and professional technology training services to radiate IC enterprises in
each base area. Under the guidance of national policies, in order to implement the
requirements of “Running the National International Training Base for Software and
Integrated Circuit Talents” put forward in “Several Policies for Further Encouraging
the Development of Software and Integrated Circuit Industry, the State Administra-
tion of Foreign Experts Affairs has entrusted China Foundation for International
Exchange of Talents to set up” “National International Training Base for IC Talents”
in Xiamen, Dalian, Beijing, Fuzhou and Shanghai, and “National International
Training Center for IC Teachers” in Hangzhou. According to the needs of the
base, foreign experts will be invited to work in China, personnel will be trained
abroad, foreign intellectual resources such as advanced technology, scientific
research achievements, and knowledge systems will be introduced, and interna-
tional, compound, practical, and innovative personnel training will be carried out.
In order to implement the “Outline for promoting the Development of the
National IC Industry,” the Ministry of Industry and Information Technology has
also organized and implemented the “Software and IC Talent Training Program” and
set up the national IC talent Training platform. Through the cooperation with
10 Talent Cultivation 151

Interuniversity Microelectronics Center (IMEC) at Belgian and other institutions, the

ministry has carried out comprehensive technical training in the field of IC for
“senior management training”, “engineer training”, “university teacher training”,
and “doctoral student training”.
At the same time, the strong market demand for talents in the IC industry also
gave birth to a number of market-oriented IC training institutions, which provide
high-skilled personnel and social training for IC design, manufacturing, packaging,
and other fields. Domestic manufacturing process R&D centers and packaging
process R&D centers also open platforms to provide practical training programs
for IC enterprises, universities, and research institutes, and to carry out process
technology training and IC packaging training. With the rise of Internet education,
new formats for online training have emerged in the IC industry one after another.

Talent Needs of Semiconductor Industry

Semiconductor and/or integrated circuit industry is typically divided into six major
areas or sectors (see Fig. 10.1). These sectors may include (1) IC and IP design,
(2) IC manufacturing, (3) packaging, board design (PCB), and testing (OSAT),
(4) EDA methodology, (5) semiconductor equipment, and (6) semiconductor
materials.
This short discussion covers major topics related to the first three sectors, together
with requirements of technical background and engineering knowledge involved in
these sectors. Technical, engineering, and textbooks are collected and listed in the
reference at the end of this chapter.
Due to the nature of variety of technologies and engineering processing involved,
the talent development and management in these sectors vary. Skilled engineers and

Fig. 10.1 Semiconductor/IC industry chain

152 K. Li et al.

professional talent demands are changing labor markets. Well-trained personnel in

STEM (science, technology, engineering, and mathematics) subjects are obvious and
essential in each of these sectors; trainings in some other subjects may be hidden or
cross-over. Overall, very few talents can technically cover or explain thoroughly the
detailed demands in the whole map presented in Fig. 10.1. Qualification of talents for
design, manufacturing, and packaging-test are respectively discussed.
In the sector of IC/IP design, including System-on-Chip (SoC) design or
Application-Specific Integrated Circuits (ASIC) design, talents of the following
major three types of design areas should be highlighted. (A) Custom IC (CIC)
design that includes analog [1–4], RF [5], analog-mixed signal/AMS [6] designs,
circuit simulation [7], and layout design [8, 9]. The research of device modeling and
study of standard cell characterization are also falling into this area. (B) Digital IC
(DIC) design [10–18] that includes register transfer level (RTL) design, logic
synthesis, and physical implementation [19, 20]. Achieving good performance,
low power, and smaller area of the DIC are ultimate goals in this area.
(C) Electronic System-level Design (ESD) which covers architectural configuration
[21–24], hardware-software codesign (HSC), high-level synthesis (HLS), RTL or
logic design [25–28], IP design and SoC and ASIC integration [29–32], and system
verification [33–35]. An additional detail related to this sector is found in Sect.
2 (Classification and Application of IC Products) and Sect. 5 (Integrated Circuit
Design).
In the sector of manufacturing foundry operation, or IC fabrication (FAB), the
demands of talents are from understanding of solid physics of microelectronic
devices; manufacturing of these CMOS based technology [36–40], developing
nanometer process techniques, and modern fabrication operations [41–43]. An
additional detail related to this sector is found in Sect. 4 (Integrated Circuit Produc-
tion Lines) and Sect. 6 (IC Manufacturing and Management).
In the sector of packaging, printed circuit board (PCB) design, and test, the
demands of talents are to deal with IC products, to accomplish the assembly of the
products, and to assure the quality of the components to be used in the final
electronic devices or equipment. The demands of talents can be simply classified
into PBT areas, i.e., packaging [44, 45], board [46–48], and test [49, 50]. An
additional detail related to this sector is found in Sect. 7 (Packaging and Testing of
IC Products).
For the sectors of EDA, IC Equipment, and Integrated Circuits Materials in
Fig. 10.1, the requirements of talent expertise vary from one field to another; each
of these sectors involves variety of specialties of STEM subjects. For example, EDA
for IC [51, 52] needs skills of system architect, extensive SW programming, and HW
partition. Additional information can be found in Sect. 8 (IC Equipment) and Sect.
9 (Integrated Circuits Materials).
The oldest university and in continuous operation, University of Bologna [53], in
the world, for example, delivers students STEM courses over a thousand years; on
the other hand, complex as it is, training classes for semiconductor talents need fixed
long-term classes, mid-term courses, and many short-term classes too.
10 Talent Cultivation 153

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31. W. Wolf, Modern VLSI Design: IP-Based Design, 4th edn. (Prentice Hall, New Jersey, USA, 2008)
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Modeling (Pearson, London, England, 2000)
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England, 2001)
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 Section II
Classification and Applications of IC Products
Shengming Zhou, Chun-Zhang Chen, and Xin-An Wang

Introduction

The development of integrated circuits (ICs) is progressing with each passing day.
The applications of IC as a core technology in various electronic products are
emerging in an endless stream; in a sense, electronic systems relying on ICs today
are a verdict that ICs are global needs and secure measure of an enterprise to survive.
IC products have become standard judgment of life quality; they serve as an
exchange or corporation tools among people. IC products are the critical part of
people’s daily life; we cannot live without them.
The world is colorful; IC products are comprehensive and complex. Viewing
from the manufacturing processes, IC products have developed from discrete
devices to integrated system chips; observing from the research and application
pathway of ICs, they have walked from military camp to individual household, and
to folks of all walking. Then the question now is: How to collect and organize the IC
products? What to emphasize of key IC products while not to list every odds and
ends? We have tried our best to introduce them, while we invite readers to navigate
through 11 chapters in this Section, to find out your admired items.
There are three parts in this section. Part one introduces the development and
classification of IC products, presented in Chaps. ▶ 11 and ▶ 12. Part two describes
the types of IC products based on the design methodology and manufacturing
technology, collected in Chaps. ▶ 13, ▶ 14, ▶ 15, ▶ 16, ▶ 17, and ▶ 18. Part
three lists various applications of IC products in different occasions, summarized
in Chaps. ▶ 19, ▶ 20, and ▶ 21.
We wish to appreciate the contributions from 117 writers, 37 reviewers, and
members of Chap. ▶ 12 committee; our acknowledgment is extended to the Editorial
Committee of the three-volume book, for their patient guidance and careful editing.
Though the writers and reviewers come from various industry backgrounds and have
divergent work experiences, the common goal achieved here is to offer readers an
often referenced desk handbook.
Development and Classification of IC
11
Song Zhang, Kaiwei Zhang, and Yutao Huo

Contents
Overview of the Development of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
IC Products in the Mainframe Era . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
IC Products in the Era of PC and Internet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
IC Products in the Era of Mobile Phones and Mobile Internet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
IC Products in the Era of Smart Terminals and IoT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Classification of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Function and Structure of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Abstract
An overview is presented to describe the development of IC products at various
stages, which include the mainframe, PC and Internet, mobile communication,
and Internet-of-Things (IoT) eras. Various types of IC products were developed
which closely follow the trends in these eras; the technology and functions of IC
products are continuously enhanced. The IC products are thus classified, based on
materials, into the Ge-Si process, compound process, and other processes. The
functions of IC products can be classified into digital, analog-mixed signals, RF,
power devices, and others.

Keywords
Mainframe · Personal Computer (PC) · Internet of Things (IoT) · Process ·
CMOS · SoC

S. Zhang (*) · Y. Huo

China Center for Information Industry Development, Beijing, China
e-mail: zhangsong@ccidthinktank.com
K. Zhang
Huada Semiconductor Co. Ltd., Beijing, China

© Publishing House of Electronics Industry 2024 157

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_11
158 S. Zhang et al.

Overview of the Development of IC Products

The development of IC technology and their related products has experienced the
Mainframe era, Personal Computer (PC) and Internet era, Mobile Telephony and
Mobile Internet era, the Intelligent Terminals (including smartphones), and Internet-
of-Things (IoT) era.

IC Products in the Mainframe Era

The development of IC technology and products originated from the demand for
information in national defense and military affairs and were then widely used in
such important fields as weaponry and aerospace. Early mainframe computers
mainly adopted vacuum tubes that were procured by the national defense depart-
ment. ENIAC (Electronic Numerical Integrator and Computer), the first general-
purpose computer completed in 1946 which was designed to calculate the ballistic
trajectory for the United States Department of Defense, was composed of 17,468
vacuum tubes, with a total weight of 30 t and a floor area of 167 km2 [1]. Then, in
1954 came the supercomputer TRADIC (TRAnsistor DIgital Computer or TRansis-
torized Airborne DIgital Computer), the size of which shrunk to that of a wardrobe
and was composed of 684 transistors and 10,358 diodes. Transistors solved the
problems of poor reliability, large power consumption, and large volume of these
vacuum tubes (or electronic tubes) and extended the functions of electronic products
from pure scientific calculation to data processing, process control, and many other
aspects. As a result, transistors replaced electronic tubes quickly and gave rise to an
electronic revolution. Announced in April 7, 1964, IBM System/360 (S/360) became
the first computer that used an integrated circuit as the integration process improved
so that multiple transistors could be installed in a single integrated circuit [2]. As a
mainframe, the cost of IBM System/360 was more than 5 billion dollars to develop
and was sold at an extremely high price—2.5 million dollars, but thousands sets
were ordered within a short period of time and then widely used in the financial and
defense systems of the United States.

IC Products in the Era of PC and Internet

With R&D personnel constantly improving semiconductor process and design

architecture, IC products have become increasingly smaller in size, more integrated
functions, and systemized. Fairchild Semiconductor and Texas Instruments have
successively introduced commercial ICs, and medium and small-scale ICs
manufactured with such processes as resistor-transistor logic (RTL), diode-transistor
logic (DTL), emitter coupled logic (ECL), transistor-transistor logic (TTL), MOS,
and CMOS came out one after another, symbolizing the inception of the IC era [3].
The Internet was originated from the ARPANET (the Advanced Research Pro-
jects Agency Network) of the US army, funded by DARPA (Defence Advanced
11 Development and Classification of IC 159

Research Projects Agency) in late 1960s. The NSFNET, established in 1985

(by National Science Foundation, NSF), replaced APARNET, thus, to become the
US nationwide backbone networks and open to the public as the Internet in April
1995. Access of the public using personal computers (PCs) to the Internet promoted
and accelerated the PC business that boomed the CPU products to new climax one
after another.
In 1971, Intel introduced the first commercial computer microprocessor—4004,
ushering in a new era of micro-programmable computers. In 1981, IBM introduced
the commercial PC with Intel microprocessor 8008, marking the emergence of the
personal computer (PC) system based on microprocessors. Afterward, Intel succes-
sively introduced a multiple of processor chips including Pentium series (1, 2, 3, 4, M),
and Core series (Celeron, Core Solo, . . .Core i3, Core i5, Core i7), while adopting
“Tick-Tock” strategy to upgrade architecture and process and finally established
its dominant role in the desktop processor area. At the same time, Intel cooperated
with Microsoft in setting up the “Wintel” alliance or duopoly which defined the
PC era and promoted the collaborative development of CPU and operating system
in the PC field.

IC Products in the Era of Mobile Phones and Mobile Internet

With the vigorous development of mobile communication around 1990, an applica-

tion processor (AP) suitable for mobile intelligent terminals was invented by
simplifying the complex functions of CPU before integrating it with GPU. Further-
more, with the continuous improvement of radio frequency chips and baseband
chips, feature phones and smartphones have undergone explosive growth. Taking
advantage of low-power consumption of ARM architecture CPUs, ARM formed an
alliance with Google who owns Android OS; Apple who owns its own iOS, together
with Qualcomm, Samsung, MediaTek, Spreadtrum, and other mobile phone manu-
facturers, who focused on application processor (AP) and baseband (BB) chip
designs, quickly grabbed the mobile Internet market shares. From GSM in the 2G
era to WCDMA, CDMA, TD-SCDMA in the 3G era, and then to FDD LTE and
TDD LTE in the 4G era, the processing capacity of communication chips has been
continuously enhanced. Qualcomm, MediaTek, and Spreadtrum expanded their
market volume rapidly through the chips developed based on ARM architecture.
As 4G has been used extensively for commercial purpose, 5G communication
directed at 2020 and the future has become global R&D hotspot, which puts forward
new demands for communication infrastructure and various newborn chips.

IC Products in the Era of Smart Terminals and IoT

With the rapid rise of cloud computing, big data, Internet of Things (IoT), and other
emerging application fields, the era of the IoT focusing on smart terminals is coming,
offering new opportunities for the growth of IC industry [4]. To connect electronic
160 S. Zhang et al.

equipment and provide related services via mobile Internet, low-power wide-area
network (LPWAN) is a demand; the third-generation partnership project (3GPP)
aimed at mobile IoT (MIoT) for LPWAN is a new topic; based on RF technology
standard, the narrowband IoT (NB-IoT) [4] established in 2016 is still a hot topic.
These new schemata have brought in new areas of development in digital ICs, analog
ICs, AMS ICs, RF ICs, optoelectronic and MEMS products, and their applications.
According to International Technology Roadmap for Semiconductors (ITRS), the
development of IC products will be continued in three directions [5]. First, IC
products continue developing according to Moore’s Law, namely its feature size
keeps shrinking, and classical CMOS devices are replaced by CMOS multi-gate
FET, for example, the FinFET and the gate-all-around FET (GAAFET). Secondly,
IC products will extend Moore’s Law by innovatively focusing on heterogeneous
device system integration which means integrating various components and parts
such as passive RF components, power devices, and biosensors into the same chip
through three-dimensional packaging or other technologies, so as to improve chip
functions and realize higher product value. Third, IC products will transcend
Moore’s Law by relying on new principles, new processes, new materials, new
devices, and equipment instead of narrowing of device line width. For concurrent
innovative technologies, including AI chips for machine learning, quantum comput-
ing devices, the third-generation semiconductor material devices and the
two-dimensional materials, are stepping on stage to expanding the development of
semiconductor technology and IC products.

Classification of IC Products

IC products can be divided into computer ICs, consumer ICs, and communication
ICs. There are also emerging IoT ICs and automotive ICs according to the market
segments they applied to. Of those applications, computer ICs take the greatest
market share. However, the market size of computer ICs declined obviously since
2014, and consumer products including smartphones and tablet PC became a new
momentum driving the IC market. In 2016, as smartphone market was slow, and the
market growth then also slowed down gradually. Instead, IoT, cloud computing, and
automotive electronics became the target of market. IDC (Internet Data Center), a
market research institution, forecasted that the market volume of the IoT would reach
1.1 trillion by 2023 [6].
According to manufacturing technology, ICs can be classified as Ge-based and
Si-based processes, compound materials process, and other process, as shown in
Fig. 11.1. Advanced technologies include CMOS (Complementary Metal-Oxide-
Semiconductor Transistor), FinFET (Fin Field-Effect Transistor), and FD-SOI (Fully
Depleted Silicon on Insulator). As the feature size of semiconductor components
was reduced to less than 20 nm, the traditional CMOS technology begun to be
confronted with challenges in many aspects. In such circumstances, Intel first
adopted FinFET (they called it 3D Tri-gate) in 2011 using 22 nm technology, and
IBM first proposed the FD-SOI technology came out as brand-new solutions.
11 Development and Classification of IC 161

Fig. 11.1 Classification of IC products by manufacturing technology

Fig. 11.2 Classification of IC products by functions

According to product function, ICs can be divided into digital ICs, analog-mixed
signal (AMS), RF ICs, power devices, optoelectronic devices, sensors/MEMS ICs,
etc., as shown in Fig. 11.2. Based on the function, structure, and nature of the
162 S. Zhang et al.

semiconductor manufacturing processes, sometimes for convenience, people may

refer to the digital, memory, logic, and analog/AMS/RF products as the “IC prod-
ucts” while combining discrete devices, optoelectronic, and sensors/MEMS as the
“DOS” products.

Function and Structure of ICs

The basic units of IC are active transistor devices and passive components such as
resistors and capacitors. Analog ICs use the amplification characteristics of transis-
tors to adjust signal amplitude and power, while digital ICs use the switching
characteristics of transistors to accomplish information processing and transmission.
Most of the early IC used bipolar junction transistor (BJT). As the manufacturing
process of complementary metal-oxide-semiconductor (CMOS) became mature,
CMOS technology was widely used in IC [7]. Based on the functional and structural
features of IC modules, various applications can be fulfilled through system integra-
tion of these modules.
A simplified IC system suitable for an IoT application is shown in Fig. 11.3, the
function and structure of these modules are indicated by their names. The IC system
includes a digital sub-system and an AMS sub-system. The digital sub-system
applied for digital signal processing, write/read and control processing, can be
realized through CPU, memory (e.g., SRAM), and external memory (e.g., NAND
Flash), interface (I/F) modules (e.g., timer and USB). AMS sub-system is applied to
process RF and analog signals, through RF circuit, analog circuit, and analog-mixed
signal (e.g., ADC, DAC, Op-Amp) to carry out these tasks.
There are varieties of IC products. The modules in Fig. 11.3 themselves can be
listed as independent IC products; different combinations and some of them, of these

Fig. 11.3 A simplified IC system suitable for an IoT application

11 Development and Classification of IC 163

modules, can realize new functions and become new products. Towards the early
twenty-first century, due to the increased size of the electronic systems, to maintain
portability, while increase the performance, higher degree of integration, a new
concept of system-on-chip (SoC) [8] was proposed to integrate many single or
individual chips or IPs into a single chip. SoC has become a common name today;
yet it remains much more complicated, it aggregates at lease CPU, memory, logic
module, and analog module; in Fig. 11.3, it demonstrates a relatively simple SoC
product.

References
1. ENIAC. https://en.wikipedia.org/wiki/ENIAC. Accessed 12 Feb 2020
2. IBM System/360. https://www.ibm.com/ibm/history/ibm100/us/en/icons/system360/. Accessed
12 Feb 2020
3. Y.Y. Wang, Y.W. Wang, Development Road of China’s IC Industry: A Country from Consumption
to Production (Science Press, Beijing, 2008), pp. 148–179. ISBN 9787030216557
4. NarrowBand – Internet of Things (NB-IoT). https://www.gsma.com/iot/narrow-band-internet-of-
things-nb-iot/. Accessed 12 Feb 2020
5. ITRS 2.0. (2015). http://www.itrs2.net/itrs-reports.html. Accessed 12 Feb 2020
6. IoT Ecosystem and Trends. https://www.idc.com/getdoc.jsp?containerId¼IDC_P24793.
Accessed 12 Feb 2020
7. IC. https://www.dictionary.com/browse/integrated-circuit. Accessed 12 Feb 2020
8. G. Martin, H. Chang (eds.), Winning the SoC Revolution: Experiences in Real Design (Kluwer
Academic, Boston, 2003)
Classification of IC Products by
Manufacturing Processes 12
Xinnan Lin, Mingxia Qiu, Fei Wang, Lenian He, and
Jesse Jen-Chung Lou

Contents
IC Manufacturing Processes and Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Bipolar Junction Transistor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Planar CMOS ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Double-Diffused Metal Oxide Semiconductor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Bipolar Complementary Metal Oxide Semiconductor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Bipolar Complementary Double-Diffused Metal Oxide Semiconductor ICs . . . . . . . . . . . . . . . . . . 172
Fin Field-Effect Transistor ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Silicon-on-Insulator IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Gallium Arsenide Devices and ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Indium Phosphide Devices and ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Gallium Nitride Devices and ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Silicon Carbide Devices and ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Heterojunction Bipolar Transistor (HBT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
System in Package IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Micro/Nano-Electro-Mechanical System and IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
IC Products of Other Advanced Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

X. Lin (*)
Electronic and Computer Engineering, Peking University, Shenzhen, China
e-mail: xnlin@pkusz.edu.cn
M. Qiu
College of New Materials and New Energies, Shenzhen Technology University, Shenzhen, China
F. Wang
School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
L. He
Zhejiang University, Hangzhou, China
J. J.-C. Lou
School of Software and Microelectronics, Peking University, Beijing, China
Institute of Microelectronics, Peking University, Beijing, China

© Publishing House of Electronics Industry 2024 165

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_12
166 X. Lin et al.

Abstract
The invention of the first IC by Jack Kilby in 1958 led to the bipolar junction
transistor (BJT) process, while the first planar IC process conceived by Robert
Noyce in 1959 evolved into planar CMOS process by C. T. Sah and Frank
Wanless in 1963. The planar CMOS process has been the most widely used
process to date for IC designs from the early technology node of 10 um in 1971.
The combination of BJT and CMOS processes has also brought in several new
technologies, such as double-diffused metal oxide semiconductor (DMOS), bipo-
lar CMOS (BiCMOS), and Bipolar-CMOS-DMOS (BCD) processes. In 1998,
the FinFET technology, a “3-D transistor” or a non-planar process, had been
demonstrated at UC Berkeley. Meanwhile, the SOI technology, being immune to
the latch-up issue, was developed to meet radiation-resistant requirement in space
applications. These IC technologies together with several technologies based on
III-V compound semiconductor materials, including gallium arsenide (GaAs),
indium phosphide (InP), gallium nitride (GaN), and others, are discussed in this
chapter.

Keywords
BiCMOS · FinFET · BJT · DMOS · BCD · SOI · GaAs · InP · GaN · SiC · HBT ·
SiP · MEMS

IC Manufacturing Processes and Products

The first Si-based process of integrated circuit (IC) by Jack Kilby at TI in September
1958 would lead to a bipolar junction transistor (BJT) process. In January 1959, the
planar IC process was conceived by Robert Noyce then at Fairchild Semiconductor
International. In 1963, C. T. Sah and Frank Wanless of Fairchild first reported in a
conference paper about CMOS configuration, which was patented in 1967. There-
after, the planar CMOS process was widely used and well known as it is easier to
integrate more devices on a large scale as Noyce initially noted.
Meanwhile, MOSFETs have become the mainstream products of modern IC due
to their high-input impedance, low-static power consumption, and high density of
integration. To achieve faster speed, the bipolar complementary metal oxide semi-
conductor (BiCMOS) IC has been developed, due to the advantages of both BJT and
CMOS. With the continuous shrinking of the mainstream CMOS from a few μm to
0.18 μm and then to 28 nm technology nodes, the device performance continuously
improved. However, as the CMOS devices continue to further scale down, their
electrical performance becomes more and more difficult to control due to the short-
channel effect (SCE), which results in a series of problems, e.g., the poor
sub-threshold characteristics and large leakage current. In order to suppress the
short-channel effect effectively, it is necessary to develop a novel device structure
with stronger gate control capability. Consequently, the multi-gate field-effect
12 Classification of IC Products by Manufacturing Processes 167

transistor (MuGFET) and silicon-on-insulator (SOI) techniques have been proposed

and developed successively. The main forms of MuGFET are FinFET and gate-all-
around FET (GAAFET). The FinFET has become the main device structure since
Intel’s 22 nm node [1], the 14 nm/10 nm/7 nm FinFET processes are widely or
increasingly used in applications, e.g., CPU and/or microprocessor unit (MPU),
memory, system-on-chip (SoC). At present, the 5 nm FinFET is for a risk production
in 2020; R&D on 3 nm and 2 nm GAAFET is underway.
In the field of high-frequency devices, the semiconductor compound materials,
such as gallium arsenide (GaAs) and indium phosphide (InP), are listed as the
second-generation semiconductor materials. With their wide band gap and high
carrier mobility, the second-generation semiconductor materials have been used to
fabricate high-performance and high-frequency devices, which are widely used in
the electronics of high speed and communications.
In the 1990s, as the manufacturing technology of semiconductor materials
became matured, researchers began to study the third-generation semiconductor
materials, such as gallium nitride (GaN), silicon carbide (SiC), and other materials
with band gap of more than 3 eV. The third-generation semiconductor materials are
very suitable for high-voltage devices with high-voltage resistance due to their
strong atomic bonds, high thermal conductivity, and high critical breakdown
voltage.
At the same time, new ICs with two-dimensional channel materials, such as
carbon nanotube (CNT) and graphene, have been developed and expected to become
mainstream technologies for next-generation ICs due to their excellent electronical
characteristics.
At present, the matured CMOS processes are expanding into other research areas
including the emerged MEMS/NEMS technology as well as to the integration of
other materials such as GaAs and SiC. In the future, they will extend to new IC
manufacturing, which is based on two-dimensional (2D) materials like carbon
nanotubes, graphene, and black phosphorus. It will find a feasible way toward
smaller device sizes and better device performance for microelectronics technology.
Using three-dimensional (3D) IC technology combined with micro-sensors, micro-
actuators, micro-mechanical structures, micro-power supplies, and signal pro-
cessing/control circuits, a variety of micro-devices and systems can be fabricated
to fit various application needs.

Bipolar Junction Transistor ICs

Bipolar IC is consisted of bipolar junction transistors (BJTs) which are mainly used
in multimedia terminals, power amplifier, radio communication, and industrial
control. The first BJT was a contact crystal triode; it was invented in 1947 in Bell
Labs by Brattain, Bardeen, and Shockley. With further study of the materials and
processes, alloyed junction transistor, surface-barrier transistor, graded-base transis-
tor, diffused transistor, and thin-film transistor were developed.
168 X. Lin et al.

Fig. 12.1 Schematic diagram of basic structure and current flow of an npn transistor

Figure 12.1 shows a basic structure and current flow of npn-type transistor. It is
consisted of two pn junctions and the current is produced by both types of charge
carriers (electrons and holes). With respect of npn bipolar junction transistor, the
middle region is p-type Base (area), the left region is n++ heavy doped area which
mainly supplies electrons as referred to as Emitter, and the right region is the
Collector which mainly collects electrons. When apply a small current on the
p-type base, a large current will occur between the Emitter and the Collector
which is called the current amplification effect of the bipolar transistor. Such
characteristics enable the bipolar device widely used in signal amplification, switch
circuit, and so on. Using the BiCMOS process, BJTs can be integrated with high-
speed CMOS digital logic circuit. To make use of the known temperature and current
relation between the Base and Emitter under a positive bias, BJT can be used to form
a temperature sensor. According to I-V characteristics between Base and Emitter,
BJT can also be used in operational circuit for logarithmic operation.
Despite the conventional junction bipolar transistor, there is still heterojunction
bipolar transistor (HBT), which performs well in high-frequency signal processing
in hundreds GHz; and HBTs are widely used in super-high-speed circuit and
radiofrequency (RF) circuit systems.
Bipolar junction transistor plays an important role in the modern electronic and
electric devices which can be both used as discrete devices and combined in other
systems like thyristor and insulated gate bipolar translator (IGBT).

Planar CMOS ICs

A planar complementary metal oxide semiconductor (CMOS) field-effect tran-

sistor (FET) is used for voltage amplification that is composed of a p-type planar
MOS field-effect transistor (pMOSFET) and an n-type MOS field-effect
12 Classification of IC Products by Manufacturing Processes 169

transistor (nMOSFET). When the input is at low voltage, the pMOSFET is turned
on, the nMOSFET is turned off, and the output is at high voltage; when the input
is at high voltage, the nMOSFET is turned on and the pMOSFET is turned off,
and the output is at low voltage. Under this working principle, the p-type and
n-type MOSFETs are in opposite states for most of the time except during the
high- and low-voltage transition of the input signal. The electronic phase of input
and output of the planar CMOS is also opposite. This operation mode can greatly
reduce the static power consumption of CMOS devices, also with high noise
immunity, extremely low-static power consumption, high-input impedance, and
good temperature stability. After the advent of planar CMOS, it has become the
mainstream technology for designing and manufacturing large-scale ICs,
although its fan-out capability is weaker, and its speed is relatively slow as
compared with bipolar transistors.
A schematic cross-sectional view of a typical planar-enhanced CMOS IC is
shown in Fig. 12.2. It uses p-type silicon as the substrate and forms an n-well by
locally doping and diffusing on the surface. First, a pMOSFET is fabricated in the
n-well; then, an nMOSFET is fabricated on the p-type substrate and finally form the
Source (S) region, Drain (D) region, and Gate (G) region.
In 1963, C. T. Sha and Frank Wanlass from Fairchild Semiconductor invented
CMOS IC [2] in 1967, Wanlass filed US patent 3,356,858. In 1968, the RCA
successfully produced the world’s first planar CMOS IC. Thereafter, planar CMOS
IC can be continuously scaled down in accordance with Moore’s Law, thereby
continuously increasing the integration density of transistors per unit area. In
1971, Intel released the first microprocessor chip 4004 based on planar FET tech-
nology, which contained 2250 transistors. In 1985, Intel released the
386-microprocessor based on 1.5-μm technology node. In 2002, Intel introduced a
planar CMOS IC at 90 nm node, which adopted the strain technology and high-speed
copper (Cu) interconnect technology to improve the overall circuit performance. In
2007, the 45 nm node technology is released by Intel for the planar CMOS IC, with
new features of high-κ (or high-k) metal gate (HKMG) for the first time and
prompted a new multi-core processor based on this technology.

Fig. 12.2 A schematic cross-sectional view of a typical planar enhanced CMOS IC

170 X. Lin et al.

Double-Diffused Metal Oxide Semiconductor ICs

Double-diffused metal oxide semiconductor (DMOS) FET is widely used as high-

voltage power device. By adding a lightly doped drift region between the source and
drain, the DMOS device can sustain most of the voltage across the lightly doped drift
region, thereby increasing the breakdown voltage of the device [3].
Based on the structure difference, the DMOS devices can be regarded as two
types: lateral double-diffused MOS (LDMOS) and vertical double-diffused MOS
(VDMOS). In 1969, Y. Tarui et al. proposed a lateral double-diffusion MOS
technique, as shown in Fig. 12.3a, using a secondary diffusion method. This kind
of device formed a lateral channel according to the different doping concentration.
The lightly doped drift region can guarantee the high breakdown voltage of the
device [4]. The different diffusion regions of conventional LDMOS devices are
isolated, which reduces unnecessary capacitance effects. Meanwhile, the three
electrodes of source (S), drain (D), and gate (G) in the LDMOS device lie on the
surface of the chip device, which is suitable for the large-scale production by using
traditional semiconductor lithography process although the integration of silicon
wafer devices will be slightly lower. In 1979, H.W. Collins et al. proposed a vertical
double-diffused MOS structure [5]. As shown in Fig. 12.3b, similar to LDMOS, the
VDMOS devices also use double diffusion to form the different regions, though the
channel of the lightly doping drift region is vertical. The drain electrode (D) is
distributed on the bottom surface of the device, thereby improving the high break-
down voltage of the device and suitable for high-voltage application at harsh
environment. The VDMOS vertical structure can reduce integration cost of the
chips, due to the drain electrodes on the bottom surface and other electrodes on
the upper surface.
Compared with common conventional CMOS devices, the DMOS device adds a
low-doping drift region, which can improve the high-voltage capability. Since the

Fig. 12.3 DMOS device structure

12 Classification of IC Products by Manufacturing Processes 171

LDMOS and VDMOS are significantly different in the direction of the drift channel,
they are utilized in different application areas. The LDMOS technique is a relatively
mature process and is more compatible with other semiconductor processes, which is
easy to integrate with traditional CMOS devices suitable for high-voltage and low
switching speed. The VDMOS has been widely used in various consumer electron-
ics and industrial control applications due to its faster switching speed and lower
power consumption.
At present, the DMOS process is mature and widely used. Several Fabs such as
TSMC, GlobalFoundries, Samsung, and SMIC have already achieved mass produc-
tion of DMOS. DMOS devices are common in a variety of electronic circuits,
especially those requiring high voltage and high frequency for applications
depending on the operating voltage. For example, under a working voltage of less
than 20 V, DMOS is used in mobile phones and digital cameras; at a working voltage
between 20 V and 100 V, DMOS can be used in computers, set-top boxes, car audio,
motor controllers, and monitors; at a working voltage between 100 V and 800 V,
VDMOS is used in TVs, water heaters, washing machines, power adapters; for a
working voltage above 800 V, it is the most obvious advantage of VDMOS, such as
high-voltage inverters, generator sets, and substation equipment.

Bipolar Complementary Metal Oxide Semiconductor ICs

Bipolar technique used to be the major integrated circuit (IC) technique. Since 1980,
complementary metal oxide semiconductor (CMOS) device has been developed to
be dominant in the market. The bipolar and the CMOS techniques have different
merits, and bipolar complementary metal oxide semiconductor (BiCMOS) technique
can take advantages of these merits of both in the circuit system, as shown in
Fig. 12.4. The CMOS process has progressed to nanoscale toward high speed and
even approaching the speed of bipolar device.
BiCMOS IC is the technology that integrates both bipolar junction transistor
(BJT) and CMOS transistor in a single IC. Bipolar device offers high-speed,
low-output resistance, whereas CMOS technology offers low-power logic gates,
high-input resistance, high signal-noise ratio, and high integration in process. As a
result, BiCMOS IC exploits both advantages of bipolar and CMOS, with benefits of

Fig. 12.4 The speed vs

power dissipation for Bipolar,
CMOS, and BiCMOS
172 X. Lin et al.

Fig. 12.5 Cross-sectional diagram of a BiCMOS structure [1]

less power dissipation and higher packing density than bipolar IC, and better
switching speed and analog circuit performance than CMOS IC [6].
The major fabrications of BiCMOS IC are based on the standard CMOS process
with additional process to form bipolar transistors. Compared to the standard CMOS
process, the fabrication of BiCMOS IC requires only a few extra masking steps and
costs for the additional process for bipolar portion. A typical structure of BiCMOS
IC is shown in Fig. 12.5 [6].
BiCMOS IC is widely employed in microprocessors and radio frequency
(RF) communications. In early stage, it was used to fabricate static random-access
memory (SRAM). In 1993, Intel used BiCMOS IC technology to introduce the first
Pentium microprocessor [7]. BiCMOS IC has applied in the amplifier, RF trans-
ceivers, and oscillator in telecommunications [6]. In RF application, the BiCMOS
heterojunction bipolar transistor (HBT) offers higher cut-off frequency comparing to
bulk CMOS technology, and it is employed in RF amplifiers and receivers.
The main manufacturers for BiCMOS IC in RF telecommunication include IBM,
TowerJazz, STMicroelectronics, GlobalFoundries, Hua Hong Semiconductor,
Advanced Semiconductor Manufacturing Corporation (ASMC), and Taiwan Semi-
conductor Manufacturing Company (TSMC). As it is required to achieve high-
quality data transmission in wireless communications, the BiCMOS IC has exploited
the high analog circuit integration to expand the applications in IC products for the
fourth-generation (4G) and fifth-generation (5G) communications [8, 9].

Bipolar Complementary Double-Diffused Metal Oxide

Semiconductor ICs

Bipolar complementary double-diffused metal oxide semiconductor (BipoIar-

CMOS-DMOS, BCD) IC is manufactured by simultaneously preparing IC chips of
Bipolar, CMOS, and DMOS structures on the same silicon substrate. The devices
fabricated by the BCD process not only have the advantages of high frequency and
strong load of bipolar devices, but also have low loss and high density of CMOS
devices, and have high resistance, strong driving, and fast switching speed of
DMOS devices. They have been widely used in the preparation of power manage-
ment devices, high-voltage power devices, display drivers, and automotive
electronics [10].
12 Classification of IC Products by Manufacturing Processes 173

Fig. 12.6 Schematic diagram of the cross-sectional structure of the 700 V BCD process integrated
circuit

In 1986, STMicroelectronics (ST) used the first generation of BCD process

technology in driver ICs. Based on the bipolar device junction isolation process
and compatible with the vertical 4 μm 60 V DMOS structure, the BCD process can
be applied to the fabrication of driver ICs [11]. In 2014, a high-voltage AC LED
driver chip was developed to re-verify the application of the high-voltage BCD
process in this field [12].
By the end of 2016, the technical node of the BCD process has grown from the
first generation of 4 μm to the ninth generation of 0.11 μm with expanded applica-
tions. In the field of high-voltage devices, a 700 V high-voltage BCD compatible
process platform has been successfully built [13]. The full-injection technique is
adopted on p-type single crystal substrate, which can realize the monolithic integra-
tion of 700 V BCD devices only with 10 more photomask plates than CMOS
process.
The section structure diagram of the 700 V BCD process integrated circuit is
shown in Fig. 12.6. The 700 V BCD process can be used for the preparation of high-
voltage and high-power integrated device products. The BCD process is also applied
to the preparation of power management chips. In 2012, Dialog developed a
low-power power management chip using TSMC’s 0.13 μm BCD technology.
In the future, with the establishment of advanced CMOS and DMOS mature
process platforms, the BCD integration technology will be more widely used in
low-power, high-efficiency, and energy-saving power electronic products.

Fin Field-Effect Transistor ICs

The Fin Field-Effect Transistor (FinFET) is a novel three-dimensional CMOS

transistor. The prototype structure of FinFET based on SOI technology was firstly
proposed by D. Hisamoto’s team from Hitachi in 1990 and referred to as DELTA
structure [14]. Later, Hisamoto joined the group of Professor Chenming Hu at the
University of California, Berkeley, which first proposed the n-channel FinFET in
1998 [15] and p-channel FinFET in 1999 [16]. Because the shape of the transistor
gate is similar to a fin, Chenming Hu’s group named it as “Fin Field-Effect
Transistor.” An SEM (scanning electron microscope) image of FinFET published
174 X. Lin et al.

Fig. 12.7 SEM image of

FinFET by Intel

by Intel is shown in Fig. 12.7. The channel of FinFET rises from the surface of the
silicon substrate to form a vertical channel structure, and then, the gate is fabricated
on the upright channel, so that the three faces of the channel can be controlled by the
gate. The 3D structure increases the control area of the gate to channel and leads to
greatly enhanced gate-to-channel controllability; suppressed short-channel effect
(SCE); and reduced sub-threshold leakage. In addition, the channel of FinFET is
usually lightly doped or even undoped, so it can effectively improve the mobility of
carriers due to the suppressed scattering effect and reduce the variations of device
performance.
At present, FinFET has been developed into a variety of structures, which can
be divided into double gate, triple gate, surrounding gate, and so on, wherein the
surrounding gate has the strongest control on the channel. Although FinFET has
excellent control over the channel, its channel surface roughness is subject to
process variations, e.g., lithography and etching to impact the device perfor-
mance and yield. In addition, the Fin becomes thinner in future further scaled
device, which causes the channel resistance to increase and the effective current
to reduce.
The superior performance of FinFET has led major semiconductor companies to
develop new products based on FinFET technology. In 2012, Intel firstly announced
the use of FinFET into its products, starting with the 22 nm processors [17]. In 2015,
Samsung and TSMC used the FinFET to fabricate 14 nm and 16 nm A9 chips,
respectively, which greatly improved the performance of the A9 chip [18]. Com-
pared with the 20 nm process node, the speed of new products increased by 40% and
the power consumption was reduced by 50%. In January 2016, AMD released a
GPU chip based on 14 nm FinFET. In July 2016, Qualcomm also produced pro-
cessors based on Samsung’s 10 nm FinFET technology.
12 Classification of IC Products by Manufacturing Processes 175

Silicon-on-Insulator IC

Silicon-on-insulator (SOI) process was developed in 1960s. In order to obtain better

radiation hardness in IC for military use, P. K. Weimer [19] developed a process of
silicon on sapphire (SOS). SOS is actually an example of SOI processes. However,
the high dislocation density due to the lattice mismatch at the sapphire/silicon
interface often results in serious leakage current, and this SOS process did not
achieve sustained development [20].
In 1966, M. Watanabe [21] implanted oxygen ions into silicon and obtained the
SiO2 layer. This SiO2 with new process has the same breakdown voltage, dielectric
constant, and other parameters as the SiO2 grown with the thermal growth method.
In 1978, after K. Izumi [22] injected oxygen into silicon, a continuous SiO2 buried
layer with excellent electrical properties was obtained, which was called separation
by implanted oxygen (SIMOX) technology. SIMOX technology promoted the
development of SOI in IC. In 1992, the appearance of plasma-assisted chemical
etching (PACE) promoted the development of wafer bonding which was another SOI
technology. In 1995, M. Bruel [23] developed smart cut technology which was later
widely used in the FD-SOI (Fully Depleted SOI) technology with small line width.
The cross section of MOSFET on SOI is illustrated in Fig. 12.8.
Unlike conventional silicon-based IC, SOI can reduce junction capacitance and
wire capacitance. In addition, thin-film SOI process has lower vertical electric field,
lower surface scattering effect, and higher mobility, which can lead to better speed
characteristics. Furthermore, the SOI process can eliminate the vertical parasitic
devices, obtain the dielectric isolation of components, so that parasitic effects like
latch-up can be avoided, and the crosstalk between components can be reduced.
Therefore, the IC manufactured by SOI process can achieve very high integration
density and have excellent radiation hardness feature, and anti-error triggering
ability.
SOI process can be applied to different IC according to the thickness of top
silicon, mainly including FD-SOI CMOS, partially depleted SOI (PD-SOI) CMOS,
bipolar CMOS (BiCMOS), power/high-voltage ICs, micro-electromechanical sys-
tems/sensors (MEMS/Sensors), etc. The applications with different top silicon
thicknesses for SOI are shown in Fig. 12.9.

Fig. 12.8 Cross section of

MOSFET on SOI substrate
176 X. Lin et al.

Fig. 12.9 SOI is applied to

different ICs according to the
thickness of top silicon [20]

In the field of advanced semiconductor technology with small linewidth, FD-SOI

and FinFET technologies have both attracted the attention of the industry. Between
these two technologies, FD-SOI is produced on SOI substrates, which can follow the
original CMOS process. FinFET uses the traditional silicon substrate, but its process
is different from the traditional CMOS process. Therefore, FD-SOI is easier to
implement, but its substrate technology is more demanding. By early 2017, large
IDMs (e.g., Intel) clearly promoted FinFET development, while those represented by
GlobalFoundries had devoted to FD-SOI process development. At present, Samsung
provides customers with these two technologies at different linewidth nodes. Some
manufacturers such as Freescale would try to combine FD-SOI and FinFET tech-
nology together.

Gallium Arsenide Devices and ICs

Gallium Arsenide (GaAs) is III-V compound semiconductor material. It has a

sphalerite crystal lattice structure with a lattice constant of 0.565 nm, a melting
point of 1238
C, and a forbidden band width of 1.424 eV. It is one of the most
important semiconductors after silicon and germanium (SiGe). GaAs devices have
special features like high frequency, high speed, high temperature resistance, bottom
noise, strong radiation resistance, etc. However, due to the defects of GaAs mate-
rials, its integration scale is limited, and the cost is high.
GaAs devices are widely used in the microwave field. They are fully classified as
microwave discrete devices, microwave hybrid IC, microwave analog, digital single-
chip IC and so on. In 1967, Turne’s team produced the first GaAs-FET with a
diffused gate structure [24], which opened a new wave of research on microwave
semiconductor devices. In 1974, Fujitsu produced a GaAs MESFET with a power
breaking through one-Watt in the X-band (8–12 GHz) [25]. In 1980, Fujitsu and
other companies developed a first high-electron mobility field-effect transistor
12 Classification of IC Products by Manufacturing Processes 177

(HEMT) with GaAs as the channel using modulation-doped super-lattice technology

[26]. The GaAs heterojunction bipolar transistor (GaAs HBT) developed in the early
1980s is superior in frequency and speed characteristics. Compared with GaAs
FETs, GaAs HBT has higher transconductance, lower output conductance, and
stronger current handling capability.
Due to the continuous improvement of chemical ratio of material, defects,
controllability of impurities, the improvement of thermal stability and uniformity,
the high-quality single-crystal substrates have been obtained that makes mass
production and expansion of gallium arsenide integrated circuits possible. GaAs
digital and analog circuits have been put into mass production, mainly for military
fields such as radar, laser-guided missiles, and satellite communications. Also in the
consumer applications, GaAs integrated circuits are mainly used in wireless com-
munications, automotive electronics, and so on. In addition, GaA materials have a
direct transition energy band structure; thus, it has high photoelectric conversion
efficiency in the preparation of solar cells. In terms of bulk devices and quantum
effect devices, GaAs materials also have great potential applications.
At present, GaAs integrated circuits are fabricated on 4-in/6-in wafers. GaAs
materials are mainly from four major companies such as Freiberger Compound
Materials, Hitachi Cable, Sumitomo Electric, and AXT. In recent years, the devel-
opment speed of China’s GaAs industry has accelerated. In 2016, Sichuan
Tonglineng Photovoltaic Technology, Zhongke Gallium Semiconductor, and Lion
Dongxin Microelectronics are building up a number of 6-in GaAs integrated circuit
production lines.

Indium Phosphide Devices and ICs

Indium Phosphide (InP) is an III-V compound semiconductor, which has a sphalerite

crystal lattice structure with a lattice constant of 0.5869 nm, a forbidden bandwidth
of 1.344 eV at ambient temperature, and a melting point temperature of 1062
C.
Similar to GaAs, it has high-electron mobility, which is suitable for high-frequency
microwave devices and circuits. Solar cells prepared with InP have high photoelec-
tric conversion efficiency.
In 1975, Barrera’s team first produced a MESFET based on InP [27]. In 1987, the
first InP high-electron mobility transistor (HEMT) was fabricated [28]. The InP
HEMT is considered as the most promising three-terminal device in the field of
microwave and millimeter-wave devices and circuits. Due to the high peak current,
fast electron drifting speed, and high thermal conductivity of InP materials, InP
HEMT can exhibit high operating frequency and output power. With the develop-
ment of epitaxial material process and lithography, the performance of InP HEMT
has been continuously improved. Reports show that the InP HEMT frequency has
reached fT ¼ 610 GHz, fmax ¼ 1.5 THz, and a very low room temperature noise
figure [29, 30]. Compared to GaAs devices, InP HEMT have higher cut-off
178 X. Lin et al.

frequency, higher conversion efficiency, and better reliability, making them ideal for
millimeter-wave applications. In 2016, Urteaga reported an InP HEMT with
fT ¼ 500 GHz, fmax ¼ 1 THz, and current density greater than 25 mA/μm2 at the
International Electron Devices Meeting (IEDM) [31]. At present, the operating
frequency of InP circuits has reached the W band (75–110 GHz) and has been
practically applied to weapons and equipment. InP devices have been widely used in
microwave communication, image sensors, artificial satellites, and other fields.
InP devices and circuits have excellent performance, but their high cost and low
yield are the key factors limiting their widespread application. The InP research is
focused on simplifying polycrystalline synthesis process, increasing wafer size,
reducing defect density, and improving material surface quality. At present, indus-
trially grown InP single crystals mainly adopt vertical gradient freeze (VGF) solid-
ification method, vapor controlled Czochralski (VCZ) method, high pressure
horizontal Bridgman (HPHB) method, and so on. Internationally, the process of
fabricating devices on 4-in InP chips is mature and commercialized. Crystacomm
has released 4-in InP chips in 1997. AXT uses the VGF method to prepare InP.
Sumitomo Electric has a large number of patents in InP researches and has success-
fully produced 6-in InP single crystals. In addition, several companies (e.g., InPACT
of France, MCP of UK, CGC of Germany, and HSRI of China) have made great
progress in InP material research.

Gallium Nitride Devices and ICs

Silicon power devices have been widely used in high-power switches, like batteries,
motor control systems, factory automation, and automotive electronic devices. These
silicon power devices are mainly concerned about the descending of power loss. In
these applications, higher breakdown voltage and lower on-resistance are the key
points to reduce the power loss. However, the performance of silicon power devices
has been reaching the theoretical limitation. Besides, many power electronic systems
require ultra-high breakdown voltage and switching frequency. Silicon power
devices are not able to meet such high requirements yet. Thus, wide bandgap
semiconductors attract much attention. The power devices prepared by wide
bandgap semiconductor can act as a high-voltage switch with low on-resistance.
Therefore, they can take place of silicon power devices. Furthermore, the wide
bandgap heterojunction field-effect transistors have high carrier density, 2D electron
gas channel, and high critical electric field strength, among which such as gallium
nitride (GaN) is able to prepare excellent power switch.
The structure of GaN HEMT device has been shown in Fig. 12.10. Due to the
polarization effect, one layer in GaN HEMT will generate 2D electron gas. It can act
as a channel of the device. Gate functions as the switch by depleting 2D electron gas.
Like other FETs, GaN FETs also have high frequency. Thus, they can be used as
high-frequency digital switch, e.g., mobile phones, satellite television receivers,
voltage converters, radar, and microwave communications.
12 Classification of IC Products by Manufacturing Processes 179

Fig. 12.10 Schematic cross section of a GaN HEMT [32]

Silicon Carbide Devices and ICs

Silicon carbide (SiC) has superior electrical properties. The forbidden band width is
2.3 eV–3.3 eV, which is about 3 times of silicon. The breakdown electric field is in
the range of 0.8  106 – 3  106 V/cm, and it is about 10 times larger than that of
silicon. The saturation drift speed (2.7  107) is 2.7 times that of silicon, and the
thermal conductivity (4.9 W/(cmK)) is about 3.2 times that of silicon. The physical
parameters of Si, GaAs, and 4H-SiC are shown in Table 12.1. Readers can refer to
Appendix B for more complete information [33].
Silicon carbide (SiC) is mainly used in high-voltage power devices, and many
devices based on SiC material have been put into use. The SiC industry chain
includes SiC material production, chip manufacturing, device sales, and equipment
supply. At present, the United States is in a leading position in chip manufacturing
and device sales of SiC, and Japan is mainly in the leading position in the supply of
SiC equipment.
SiC is a new generation of wide bandgap semiconductor materials with great
potential for semiconductor applications. The military applications of SiC include
missile chips, phased array radars, and aircraft carriers. Its application of new energy
sources includes LED green lighting. In terms of energy saving and environmental
protection, SiC chips can be used for power generation/transmission inverter
switches, which can save 50%–70% of power loss during power transmission. In
terms of electric vehicles, the SiC chips can save energy and reduce consumption
and can save about 80% of space in volume, which has greatly helped the develop-
ment of the electric vehicle industry. In high-end equipment manufacturing, a large
number of SiC chips are required for new energy vehicles, ships, aerospace, space
shuttles, and communication systems.
The global research on SiC materials and the development of commercialized SiC
power devices are still in their infancy. The industry needs to integrate SiC
180 X. Lin et al.

Table 12.1 Physical parameters of three semiconductor materials, Si, GaAs, and 4H-SiC
Material Si GaAs 4H-SiC
Band gap 1.11 1.43 3.26
Electron mobility, cm2/Vs 1400 8500 900
Breakdown electric field, MeV/cm 0.3 0.4 2.2
Thermal conductivity, W/cmK 1.5 0.54 4.9
Saturation velocity, cm/s 1.0  107 2.0  107 2.7  107
Dielectric constant 11.8 12.8 10.0

technology into the entire product chain. The purification technology of SiC raw
materials, the SiC crystal growth equipment, the SiC crystal growth technology, SiC
chip production technology, the related SiC device design, and manufacturing
technologies are all important to be developed.

Heterojunction Bipolar Transistor (HBT)

Unlike general bipolar transistors, different materials were used at the Emitter region
and Base region in the heterojunction bipolar transistor (HBT). The structure of the
HBT is shown in Fig. 12.11. The semiconductor materials used in emitter region
have a large bandgap, a pn heterojunction is formed between the emitter region and
the base region. Compared with conventional bipolar transistors, HBT can operate at
higher frequencies (usually up to hundreds of GHz), with higher conversion effi-
ciency and high base emissivity. Based on these advantages, HBT is mainly used in
radio frequency (RF), high power, and high-speed circuits and mobile phones [34].
Because the wide bandgap semiconductor material is used in the emission area of
the heterojunction, the discontinuity will occur at the energy band of the hetero-
junction. For a npn heterojunction bipolar transistor, a large abrupt change in valence
band energy will prevent the hole from injecting into the n-type emitter from
the p-type base region. The emission efficiency of the heterojunction is basically
the same (that is, the electron moves through the emitter area to the base area), and
the emission efficiency is independent of the doping concentration of the emitter area
and the base area. Therefore, the emission efficiency of HBT emitter junction (also
known as amplification factor) is independent of the concentration of both sides of
the emitter junction, so the doping concentration in the base area can be higher than
that in the emitter area, and then, the frequency band can be optimized by amplifying
the coefficient, so that HBT can work in the millimeter-wave range. The maximum
current gain (without considering base recombination) formula of HBT is as follows:

βmax ¼ I En =I Ep 1 exp ΔEg =kT

The ratio βmax of HBT to traditional BJT can be determined by the energy
difference of the bandgap ΔEg:
12 Classification of IC Products by Manufacturing Processes 181

Fig. 12.11 Schematic of basic structure of HBT

βmaxðHBTÞ =βmaxðBJTÞ ¼ exp ΔEg =kT

Generally, ΔEg > 250 meV, the gain of HBT is 104 times that of traditional
BJT [35].
The applications of HBT were as following:

1. Low noise amplifier (LNA): Noise factors and correlation gain are very important
parameters for receiver/transmitter in mobile communication equipment, and low
noise amplifier (LNA) in the front-end design has a great impact on these
parameters. The excellent noise characteristics of HBT can improve the perfor-
mance of LNA.
2. Multiplexer: In 1993, the German scientist H.U. Schreiber et al. developed a
16 Gbit/s with 2:1 ratio of multiplexer using a double-mesa self-aligned SiGe-
HBT (T ¼ 40 GHz); in 1999, a 30 Gbit/s selective chip with a total power
consumption of 1.1 mW was developed using the same type of SiGe-HBT.
3. Power Amplifier (PA): SiGe-HBT monolithic IC and BiCMOS have been greatly
developed and laid the foundation for the integration of mixed signal systems.
SiGe-HBT has excellent characteristics at temperature, radiation resistance, and
frequency. It is also compatible with existing CMOS processes and rapidly
developed in all aspects of applications.

System in Package IC

System in Package (SiP) was technically in analogous to system-on-package (SOP)

that developed at Georgia Institute of Technology in 1997 [36]. The novel concept
for electronic package featured the integration of all the functional devices into a
single-chip carrier, which can hence possess all necessary function. SiP has become
an essential technology for advanced electronic package and system integration.
Besides, this technology is believed to be promising in the pursuit of the shrinking
and multi-functional electronic goods.
182 X. Lin et al.

Fig. 12.12 (a) SoC-SiP package, (b) MEMS-SiP Hall sensor

In SiP, chips (or dies) can be stacked vertically or placed horizontally on a carrier,
while SoC (System-on-Chip) features a highly integrated single chip [37]. Moreover,
package cap cannot contact the microelectromechanical devices in a MEMS (Micro-
electromechanical Systems) package, which is different from the conventional
electronic package [38]. A SoC design using SiP and a MEMS design with Hall
sensor using SiP are shown in Fig. 12.12a, b, respectively.
With the emerging market of high-speed wireless communication, materials for
package become more demanding for high-frequency application, while the smaller
package size and low cost are expected. A novel SiP module embedded into Apple
iWatch included NFC (Near Field Communication), Bluetooth, MEMS, and flash
memory has been succeeded, it is the SiP module that enabled the wearable multiple
functions and delicate design.

Micro/Nano-Electro-Mechanical System and IC

Since the middle of the twentieth century, microelectronic technology and related
fabrication techniques have been developed fast. Based on that, micromachining
technology has also been significantly improved especially for the micro-sensors and
micro-actuators. Micro-Electro-Mechanical Systems (MEMS) is an integrated sys-
tem with microelectronic device, microstructure, and micromachinery parts such as
micro-sensors and micro-actuators. MEMS typically involves physical or chemical
exchange between electric domain and other energy domains, which is a cross-
discipline of various research fields. In addition to the traditional components of
microelectronic and micromechanics, MEMS has recently emerged with some other
areas including micro-heat, micro-optics, micro-magnet, micro-fluidics, microbiol-
ogy, and micro-chemistry, as shown in Fig. 12.13. Micro-sensor and micro-actuator
are also called transducers.
Developed from the IC technology, MEMS has kept many fundamental processes
such as lithography, implantation, doping, sputtering, evaporation, PECVD,
LPCVD, oxidation, and wet etching. Many featured processes have also been
developed during the development of MEMS, such as surface micromachining,
12 Classification of IC Products by Manufacturing Processes 183

Fig. 12.13 Scheme for the

development of MEMS
subjects

Fig. 12.14 Self-powered wireless sensor network

bulk micro-machining of silicon, wafer bonding, LIGA technology for structure with
high aspect ratio, and non-silicon processes.
MEMS products are mainly applied for the consumer electronics, especially for
the automobiles and the cell phones. For instance, MEMS-based gyroscope, tem-
perature sensor, humidity sensor, microphone, display sensor, proximity sensor, and
light intensity sensor have been widely used in smartphones.
Moreover, MEMS is usually integrated with various sensing components, actu-
ators, and some related IC microprocessors. Ideally, it should also be integrated with
micro-energy (such as energy harvesting devices [39–41]) and communication
components. Figure 12.14 shows a self-powered wireless sensing network
consisting of the MEMS energy harvester, IC, and wireless communication
components.
Nano-Electro-Mechanical System (NEMS) is developed based on MEMS, while
the feature size of the NEMS device and system is as small as nanoscale. Some
effects other than the macro scale properties such as the surface effect and scaling
effect of the material may emerge at nanoscale, which would dominate the
184 X. Lin et al.

performance of the device and system. With respect to the material and the process,
NEMS device is not merely scaling down the MEMS device. It typically explores
new function by utilizing some novel nanomaterials such as graphene, fullerene,
carbon nanotube, and other 2D materials and biomaterials. Advanced techniques
such as E-beam lithography and nanoimprint process have also been widely used to
fabricate NEMS devices.
NEMS has mainly been applied for sensors with super-high sensitivity, biomed-
ical devices, dense data storage, and high-frequency resonator, etc. The sensing
mechanism includes various physical principles such as the resistive response,
frequency response, fluorescence, and magnetic response of the nanomaterials and
nano-structure. For example, silicon cantilever of 50 μm  6 μm  0.17 μm has been
fabricated with a batch of carbon nanotubes at the free end to adsorb hydrogen gas.
The cantilever is driven electrostatically, whose resonance frequency in a vacuum
pressure of 107 Pa is shifted upon a tiny change of the effective mass [42, 43]. With
a feedback control, the resonant frequency of the cantilever can be 1 MHz, and the
quality factor of the device in vacuum could be as high as 50,000, which gives a
mass resolution of 5  1018 g. With such excellent mass resolution, it is possible to
detect 150 million molecules of hydrogen gas.

IC Products of Other Advanced Processes

With the increasing requirements of integrated circuit performance, there are three
main development directions of process technology: (1) the three-dimensional
technology to integrate the system, including three-dimensional packaging, and
multi-active layer three-dimensional process; (2) novel materials and processes
technology, and (3) new physical mechanisms and novel device structures.
Many new semiconductor materials have emerged in recent decades of research,
and many novel devices have been fabricated based on these new materials and
related processes. For example, SiGe heterojunction bipolar transistors (SiGe-HBT),
SiC devices, GaN blue light devices, and various nano-electronic products. Taking
the strained silicon process as an example, the strained silicon is valued for their high
mobility [44]. The preparation methods of strained silicon can be divided into two
categories: global strained silicon process and local strained silicon process.
With the rapid development of IC technology, the device size has shrunk dramat-
ically; the physical and process integration technology of devices has become more
and more complicated. The carrier transport will exhibit significant quantum
mechanical properties. Therefore, low-dimensional semiconductor devices are
based on quantum effects stand out. Graphene is a typical two-dimensional material,
which is a honeycomb planar film formed by carbon atoms in a sp2 hybrid manner.
Graphene has high-electron mobility, low resistivity, and good thermal conductivity
as well as mechanical properties, making the graphene devices be regarded as the
electronic components for future integrated circuits [45]. In 1991, S. Iijima discov-
ered carbon nanotubes (CNTs) from carbon fibers produced by the arc method [46].
CNT is a one-dimensional nanomaterial with a tubular carbon molecular structure. It
12 Classification of IC Products by Manufacturing Processes 185

has high modulus, high strength properties, good thermal conductivity, and special
electrical properties. Hence, it has a good application prospect in future molecular
devices or nano-electronic devices. Stanford University has developed a computer
prototype based on CNT, which is expected to evolve into a faster and more efficient
computing device than Si-based computers [47]. Quantum dots are a zero-
dimensional material, and its unique electronic density of states makes them more
suitable for lasers.

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Products of Digital Integrated Circuit
13
David Hu, Alex Lin Jia, Fan-Yi Jien, Xia Ai, and Chun-Zhang Chen

Contents
Digital Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Static Random Access Memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Dynamic Random Access Memory (DRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Double Data Rate (DDR) SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Low-Power Double Data Rate SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Graphics Double Data Rate SDRAM (GDDR SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
OTP and MTP Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
One-Time Programmable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Multi-Time Programmable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Solid-State Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Multimedia Card and Embedded MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Multi-Chip Package Memory and eMCP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
X86 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
IA-64 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
POWER Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
MIPS Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
ARM Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
UltraSPARC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
C-SKY Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

D. Hu
EtownIP Microelectronics Co. Ltd., Beijing, China
A. L. Jia
Cadence Design Systems, Inc., Shanghai, China
F.-Y. Jien
Advanced Memory Semiconductor Co. Ltd., Jiangsu, China
X. Ai
Cadence Design Systems, Inc., Beijing, China
C.-Z. Chen (*)
Peng Cheng Lab, Shenzhen, China
e-mail: chenchzh@pcl.ac.cn

© Publishing House of Electronics Industry 2024 187

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_13
188 D. Hu et al.

Graphics Processing Unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Microcontroller Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
RISC-V ISA and RISC-V Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Field Programmable Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Application-Specific Integrated Circuit and System on Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Network Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Secure Cryptoprocessor and Cryptographic Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Advanced Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Abstract
Among all semiconductor and IC products in the global market, digital IC
contributes to about 70%, which includes memory, CPU, logic, ASIC, and IP
products. Over the past 50 years or so, various types of memories have been
developed, including embedded SRAM, DRAM, their derivatives (DDR,
LPDDR, and GDDR), and external flash memories (NAND, NOR). Started
from 8086 in 1978, the x86 CPU series from Intel has the longest development
history, variety of CPU instruction set architecture (ISA) are co-exiting in the
industry today, including POWER series from IBM, MIPS from Imagination, and
ARM series from ARM Holdings. Broadly speaking, MPU, MCU, and DSP are
also members of CPU family. This chapter reviews the digital IC products of
memories, CPUs, ASIC, and FPGA.

Keywords
SRAM · DRAM · DDR · Flash · x86 · MIPS · ARM · MCU · DSP · RISC-V ·
FPGA · ASIC

Digital Integrated Circuit

Digital integrated circuit (IC) products offer various features, such as high density in
integration, portability, low power consumption, and high reliability so as to be
processed in electronic systems. Digital IC products in the form of CPU, DSP, SoC,
memory chips, special functional die, and modules, presented in electronic systems
or equipment form(s), are widely used in communications, consumers, Internet of
things (IoT), and medical devices, as well as in industrial controlling, aeronautics
and astronautics, military, robotics, and artificial intelligence (AI) products.
In 1968, the first commercial CMOS digital IC 4000 series was released by Radio
Corporation of America (RCA). In 1970, Intel Corporation released the 1103 chip,
which used the 8 μm pMOS process and was mass produced in 1971 [1]. The 1103
chip has 1 Kbit dynamic random access memory (DRAM) and remarked the
emergence of large-scale integration (LSI, more than 500 transistors on a chip).
Intel released the first microprocessor 4004 in 1971; it integrated 2300 transistors on
10 μm process. In 1980, very large-scale integration (VLSI, more than 104 transistors
13 Products of Digital Integrated Circuit 189

on a chip) IC was released. The era of ultra-large-scale integration (ULSI, more than
106 transistors on a chip) IC arrived in 1989 [2]. In 2005, the scale of digital IC was
more than 1 billion components (more than 109 transistors on a chip), and it ushered
the era of SoC products. In 2019, Cerebras Systems announced a Wafer Scale Engine
(WSE) chip containing 1 trillion (1.2
1012) transistors on a single wafer [3].
Digital IC usually integrates various functional modules. For example, a digital
memory product (ROM or RAM) is composed of many memory units that are called
ROM or RAM cells. A SoC product integrates the CPU, many logic standard cells,
digital memory units, input/output (I/O) cells, and other IP modules.
There are various types of digital IC products, which have different functions and
applications. In the 1990s, the main products of digital IC were CPU, DSP, and
memory cells, microcontroller unit (MCU), microprocessor unit (MPU), and ASIC,
and the applications focused on “3C,” then so-called computer, communication, and
consumer. Early ASIC products are designed for specific applications, such as color
graphics adapter (CGA) and video graphics adapter (VGA) chips for monitor display
of computers and televisions. As the demand of chips was growing, in home
appliances and consumer products, MCU and MPU have been developed. In the
early of twenty-first century, SoC has been highly valued and promoted. People liked
to integrate the multiple independent chips such as CPU and memory on one chip,
which greatly promoted the development of smart electronic products. In the last
decade, various new digital IC products appeared, which are based on more complex
system designs, such as GPU, integration based on heterogeneous system architec-
ture (HSA), and AI chips, such as these chips in machine learning applications, etc.

Static Random Access Memory (SRAM)

In semiconductor, a patch of data is stored in “memory.” According to their state

after power is cut off, for those data no longer in existence is called volatile memory
(VM), and for those after the power is cut off, data still stored are called nonvolatile
memory (NVM). For example, the most commonly known NVM is the flash
memory, or simply, flash. The static random access memory or SRAM and the
dynamic random access memory (DRAM) both belong to the VM category.
The first 1 Kbit 6T-SRAM was developed by Intel in 1976 [4]. In 1980, T. Iizuka
et al. successfully developed a pure CMOS-based SRAM having capacity of 16 KB
[5]. The single integrated SRAM chip during that period is normally having capacity
of 32 B–128 KB. In general, embedded SRAM from a few kilobytes to megabytes is
found in the stand-alone single chip for common electronic products such as
electronic toys, digital cameras, mobile hand-phones, and digital music instruments.
SRAM according to their accessing speed and operational manner can be cate-
gorized as single-port SRAM and double-port one. Signal processing circuit, as in
the digital signal processor (DSP) has no restriction in accessing the memory, so
dual-ported SRAMs are widely used for faster operation [6]. A typical SRAM chip
consists of one or multiple core cell arrays, line and column decoder, sense amplifier,
and control circuits. The SRAM makes use of a transistor’s on/off state to form a
190 D. Hu et al.

flip–flop circuit; their switching speed is in nanoseconds. The 6T-SRAM cell is

commonly comprised of 2x PMOS and 4x NMOS transistors. There is also
4T-SRAM, which has four transistors plus two resistors. Other than the 4T- and
6T-SRAM, there are also 8T-SRAM and 10T-SRAM, but that would compromise
the chip area and hence less used in the commercial applications. Less than
4T-design is found in the DRAM, which requires highest compact density such as
1T-DRAM or 3T-DRAM.
Whether “refresh” is needed or not during operation is the key difference between
DRAM and SRAM. SRAM does not need to refresh, and the data previously stored
are always there. However, DRAM if not refreshed from time to time, the data stored
may be lost. Comparing to DRAM, SRAM has higher speed and low power
consumption, especially during its idle state, but also higher price. Therefore,
SRAM is commonly used in the high bandwidth and low power consumption or
both; SRAM has advantages of easy to control, random access, and read/write faster
but it suffers low capacity and low density and bigger areas than DRAM of similar
capacity. Therefore, SRAM is not suitable for large memory-required applications.
SRAM is normally used as cache of the first-level buffering unit (L1) or second-level
buffering unit (L2). Since 80,486 of Intel’s microprocessor series, the high speed is
partially attributed to the fast-accessible cache memory from SRAM embedded
inside the microprocessor chip, and later, in its Pentium CPU the L1 and L2 cache
memories became the norm. The L1 cache memory is commonly designed inside the
CPU, and the L2 is built at outside of the CPU. With both L1 and L2 cache
memories, the CPU single-chip size is relatively big. The current CPU architecture
making use of ARM core also introduces the cache memory to solve the speed
mismatch issue with the core DRAM. As DRAM cell can only have one transistor
and one capacitor (1T1C), hence it is used largely in the internal memory of a
computer, which requires maximum capacity and density with minimum chip area.
Intel, Samsung, and TSMC have all mass productions of 6T-SRAM in 45 nm,
32/28 nm, and 16/14 nm technology nodes. The current competition is in their 10 nm
tech node, making use of FinFET with small area but high-performance 128 megabit
SRAM products [7]. With the development of high-speed dynamic audio/video
image exhibitions, such as in the applications of virtual reality (VR), augmented
reality (AR), and artificial intelligence (AI), the ultrafast read/write SRAM is
increasingly demanded, it is therefore the search of new types, and high-performance
SRAM device have ever intensified.

Dynamic Random Access Memory (DRAM)

In the 1970s to mid of 1990s, dynamic random access memory (DRAM) normally
used the asynchronous interfaces [8]. An asynchronous DRAM (“ADRAM”) corre-
sponds with the control input signal at any time, and this asynchronous interface also
provides direct control of internal timing.
13 Products of Digital Integrated Circuit 191

DRAM is usually arranged in a rectangular array of charge storage cells

consisting of one capacitor and one transistor (1T1C) per data bit. The horizontal
lines connecting each row are known as word lines. Each column of cells is
composed of two bit lines, each connected to every other storage cell in the column.
They are generally known as the “+” and “” bit lines.
A sense amplifier is essentially a pair of cross-connected inverters between the bit
lines. The first inverter is connected with input from the “+” bit line and output
to the “” bit line. The second inverter’s input is from the “” bit line with output to
the “+” bit line. This cross-connection circuit results in positive feedback, which
stabilizes after one bit line is fully at its highest voltage and the other bit line is at the
lowest possible voltage.
The concept of synchronous DRAM (SDRAM) was introduced as early as in the
1970s. It was well adapted even though most of the DRAM is still using asynchro-
nous interface for example in the early Intel microprocessor. However, it was only
widely accepted in the electronic industry ever since 1993. Samsung demonstrated
their KM48SL2000 SDRAM in 1993 [9]. Not until 2000, SDRAM has eventually
replaced “ADRAM ” and becomes dominant in computer memory.
SDRAM has the below features comparing with a normal DRAM. Its operation
can be multiple piped. The data transfer rate can be raised when the speed of MCU
increases. It also prevents failure rate due to the input signal distortions, and it has
low power consumption and high band width. All instruction signals are synchro-
nized with the master clock; therefore, it is easy and quick to manage; however, it is
rather more complex than the synchronous interfaced one. SDRAM has architecture
of multiple banks, and each bank can be regarded as an individual RAM array, which
consists of row and column address lines and word buffers. The most significant
change, also the primary reason that SDRAM has supplanted asynchronous RAM, is
the support for multiple internal banks inside the DRAM chip. Using a few bits of
“bank address,” which accompany each command, a second bank can be activated
and begin reading data while a read from the first bank is in progress. By alternating
banks, an SDRAM device can keep the data bus continuously busy, in a way that
asynchronous DRAM cannot. Each bank of the SDRAM shares a common input/
output (I/O) with one another. The capacity of SDRAM is determined by its number
of addresses (#Addresses), number of bits (#Bits), and number of banks (#Banks),
namely the capacity (density) of SDRAM ¼ (#Addresses)
(#Bits)
(#Banks).
As a type of volatile memory, DRAM has simpler structure compared to SRAM.
It only needs one transistor and one capacitor, 1T1C, to formulate a bit cell. Hence,
the highest density and capacity can be achieved in a small single stand-alone chip. It
is widely used in the internal memory for computer, and with the development of the
CPU, and high-performance computing (HPC), the requirement for the ever faster
accessing memory is increasingly challenging. The older framework of the DRAM
is no longer suitable, to make it simple, as far as the read/write is concerned, there are
SDRAM and “ADRAM ”. In terms of the data rate, there are single data rate (SDR)
and double data rate (DDR); also, there is quad data rate (QDR) SDRAM. For
192 D. Hu et al.

applications, the DRAM can also be categorized into GDDR just for the graphical
use, or depending on the level of voltage, there are ordinary DDR and low power
DDR (LPDDR). If the DRAM is embedded together with other functional blocks
such as CPU, it is also called embedded DRAM or eDRAM [10].

Double Data Rate (DDR) SDRAM

Synchronous DRAM (SDRAM) if based on the data accessing rate can be differen-
tiated as single data rate (SDR), double data rate (DDR), and quad data rate (QDR)
SDRAM [11], as illustrated in Fig. 13.1.
A computer bus operating with double data rate (DDR) transfers data on both
the rising and falling edges of the clock signal. The manufacturing process of DDR is
the same as the SDRAM, and the manufacturer only needs a little modification to the
equipment can readily put DDR in mass production. The development of SDRAM
has been through five generations unto the present: The first generation is SDR; 2nd
generation is DDR; the third generation is DDR2; and the fourth is DDR3; and the
fifth generation is DDR4 (see Table 13.1).
On March 30, 2017, JEDEC has published the DDR5 specifications, which have
been finalized on May 2019. It is simply based on the DDR4 with double data
bandwidth and the array density of DDR4; DDR5 is expected twice as fast as its
previous precursor. In the meantime, lower the power consumption and increase the
read/write speed. This development is in line with the graphic advancing with the
virtual reality (VR) and its applications.
There are two commonly packages of stand-alone SDRAM found in the market.
The first one is the early product of 168 pins dual in-line memory module (DIMM)

Fig. 13.1 Comparison of data speed between SDR, DDR, and QDR
13 Products of Digital Integrated Circuit 193

Table 13.1 Detailed comparison of different specifications of DDRs

Specs DDR DDR2 DDR3 DDR4 Remarks
Internal clock/MHz 133–200 133–200 133–200 133–200 Master clock
Bus clock/MHz 133–200 266–400 533–800 1066–1600
Data transfer 200, 266, 333, 400, 533, 667, 800, 1066, 1600,1866,
rate/(Mb/s) 400 800, 1066 1333, 1600, 2133, 2400,
1866, 2133 2667, 3200
Theoretical 1.6, 3.2 6.4 12.8 19.2, 25.6
bandwidth, GB/s
Operating voltage 2.5 V 1.8 V 1.5 V (1.35 V/ 1. 2 V Lower power
DD3L) better heat
dissipation
I/O interface SSTL2 SSTL18 SSTL15 POD12
Prefetch 2n 4n 8n 8n Buffer depth
Burst length/bit 2/4/8 4/8 8 Burst length
Number of banks 2, 4, 8 4, 8 8 Bank number
Single-chip density 128 Mb–1 Gb 256 Mb–4 Gb 512 Mb–8 Gb 4–16 Gb |
On-die termination, None Medium, Medium, Medium, Improved
ODT Dynamic dynamic dynamic, signal transfer
park rate and lower
the power
Package TSOP or BGA FBGA FBGA FBGA Higher speed,
improved EMI
Note: Prefetch represents the buffer size. For example, for DDR3, its Prefetch buffer size is 8n,
representing every single buffer depth to be 8

but that was ceased in production since 2012. In place of it is the newer 184 pins
DDR memory chips. At present, DDR DIMM, DDR2 DIMM, and DDR3 DIMM
also DDR4 DIMM are all incompatible with one another. So be aware of this and
mix usage is not permitted.

Low-Power Double Data Rate SDRAM

A low-power double data rate SDRAM (LPDDR SDRAM, or simply LPDDR) is a

special type of DDR SDRAM. It is extensively used in the mobile communications
and hence acquired the name of mDDR; here, m stands for mobile or mobile DDR.
The product series includes LPDDR/2/3/4, and its standard was defined by JEDEC
targeting only to the low power and small die area, because its small die size,
LPDDR, is specialized in the application of mobile product [12].
Many improvements have been made to the LPDDR. The most significant one is
to reduce the operating voltage from 2.5 V to 1.8 V and also introduced the
temperature-compensated refresh technique; hence, the power consumption is fur-
ther reduced. LPDDR2 has some further improvement in its array technology; the
low-power feature is almost the same as LPDDR, but both LPDDR and LPDDR2 are
incompatible with DDR1 and DDR2, respectively.
194 D. Hu et al.

Table 13.2 Major feature comparisons of LPDDR2, LPDDR3, and LPDDR4

FEATURES LPDDR2 LPDDR3 LPDDR4
Internal clock/MHz 200 200 200
Bus clock/MHz 400 800 1600
Data rate/(Mbit/s) 800 1600 3200
Band width/(GB/s) 6.4 12.8 25.6
Prefetch 4n 8n 16n
VDD2/VDDQ/VDD1 1.2 V/1.2 V/1.8 V 1.2 V/1.2 V/1.8 V 1.1 V/1.1 V/1.8 V
Command/ADDR bus 10 bit, DDR 10 bit, DDR 6 bit, SDR
Bank number 4/8 8 8/CH, total 16
Chip density 64 Mbit to 8 Gbit 4 to 32 Gbit 8 to 32 Gbit
Interface HSUL_12 HSUL_12 (OR ODT) LVSTL
I/O width 16 bit/32 bit 16 bit/32 bit 16 bit/CH, TOT 32 bit
Package MCP/PoP MCP/PoP MCP/PoP

In May 2012, JEDEC has officially announced the LPDDR3 standard. It is in

support of the package on package (PoP) in order to meet the various requirements of
mobile application [13]. The power consumption feature of and the interface to
signal of LPDDR2 can be also found in the LPDDR3. In addition, one key feature of
LPDDR3 is the introduction of write leveling and CA Training and on-die termina-
tion (ODT). Comparison of LPDDR2, LPDDR3, and LPDDR4 can be found in
Table 13.2.
JEDEC defined in early 2019 the (I/O) data rate of LPDDR5 to be 6400 MT/s
(T stands for I/O throughput), while Samsung announced LPDDR5 in July 2018
and released mass production of LPDDR5 in July 2019 on 10 nm process at data
rate of 5500 Mb/s, with chip density 12 Gb, which can be expanded to 12 GB
package [14].

Graphics Double Data Rate SDRAM (GDDR SDRAM)

The modern GPUs are demanding higher-performing solutions to keep pace with
their ever-increasing bandwidth requirements of data access. The graphics double
data rate synchronous dynamic random access memory (GDDR SDRAM or simply
GDDR) is designed with high bandwidth to speeding through heavy graphics task.
While the GDDR SDRAM shares design similarities with the DDR SDRAM, it
achieves higher bandwidth, higher clock speed, lower power consumption, and heat
dispersal requirements. The GDDR is not compatible with DDR for several speci-
fications, such as operation voltage, package, and interface, especially the huge
difference of performance.
The first-generation GDDR is developed from DDR technology. The GDDR is
nearly same as DDR, but clock speed is up to 900 MHz, while DDR is up to
600 MHz.
13 Products of Digital Integrated Circuit 195

Table 13.3 Specifications of GDDR3/GDDR5/GDDR6

Specifications GDDR3 GDDR5 GDDR6
Density (Gb) 1–2 4–8 8/16
VDD, VDDQ 1.5 V (1.35 V) 1.5 V, 1.35 V 1.35 V
Clock speed (MHz) 800/900 1750 1750
Data rate (Gbit/s) 1.6–1.8 5–8 12–16
I/O width per channel 4, 8.16 32/16 32/16
Number of banks 8 16 16
Prefetch 8n 8n 16n
Burst length 4 burst chop 8 16
Cyclic redundancy check (CRC) N/A Yes Yes
Package BGA-78/96 BGA-170 BGA-180

The second-generation GDDR2 is developed from DDR/DDR2 and NVIDIA

first-made improvement on GDDR2 for GeForce FX 5800 in 2003 [15], and it is two
times faster as DDR.
The third-generation GDDR3 specification was promoted by ATI
(AMD-acquired ATI in 2006) and DRAM vendors and finally was adopted as
JEDEC standard. GDDR3 comes from DDR2, which is specially designed for
GPUs. GDDR3 could send two 32-bit wide data words per clock cycle. It has two
unidirectional and single-ended data strobe that could save read/write turnaround
time. It is operated at lower voltage and leads to lower power consumption, lower
heat output, and high clock frequencies. The first card to use the GDDR3 SDRAM
was NVIDIA GeForce FX 5700 Ultra in early 2004.
The fourth-generation GDDR4 SDRAM is developed by JEDEC. GDDR4 is
developed from DDR3 technology and was intended to replace GDDR3. ATI used
the GDDR4 for few types of GPUs from 2006, while other manufacturers used the
GDDR5 to replace the GDDR3 directly.
The fifth-generation GDDR5 SDRAM is based on DDR3 SDRAM and is devel-
oped by JEDEC and several other companies [16]. GDDR5 is twice the data rate of
GDDR3. GDDR5 is widely used in the last couple generations of GPUs from 2008.
In January 2016, JEDEC standardized a new GDDR5 version GDDR5X, whose data
rate is twice of GDDR5.
In 2017, JEDEC standardized GDDR6 SDRAM [17], which offers max data rate
up to 16 Gbit/s and lower operating voltage (Table 13.3), and the power consumption
is farther reduced. The industry-leading graphics vendors have adopted widely in
market applications of the graphics GDDR, for high-performance computing, net-
working, and data centers.

OTP and MTP Memories

There are two categories of programmable memories, viz. one-time programmable

memory and multi-time programmable memory.
196 D. Hu et al.

One-Time Programmable Memory

One-time programmable (OTP) memory is a type of memory, which cannot be

erased once it has been programmed.
Programmable read-only memory (PROM) is a typical OTP memory [18]. It was
invented in 1956 by Wen Tsing Chow [19], an American Scientist, to fulfill the
requirement of data memory in airborne computers for United States Air Force.
There are two common PROM types: bipolar fuse PROM and Schottky PROM. By
introducing high current, the former can be programmed by melting down fuse,
shown as Fig. 13.2, and the latter by permanently breaking down Schottky diode.
In 1971, Dov Frohman from Intel invented erasable PROM (EPROM), which is
mainly used for storing program code of microcontroller. Storage content can only
be removed by an EPROM eraser. For this purpose, a fused quartz window is
installed on the package of EPROM (see Fig. 13.3). Storage content can be erased
by exposing EPROM die to ultraviolet light through the fused quartz window, which
therefore should be covered to protect data after programmed [20]. OTP EPROM
was produced by mounting die directly into opaque package. Without fused quartz
window, OTP EPROM cannot be erased after programming. Major OTP EPROM
manufacturers are Atmel, STMicroelectronics, and NEC.

Multi-Time Programmable Memory

Multi-time programmable (MTP) memory is a type of memory, which can be

programmed multiple times.
Erasable programmable read-only memory (EPROM) [3] and electrically eras-
able programmable read-only memory (EEPROM or E2PROM) are common MTP
memories.
EEPROM can electrically erase storage content. It can be written, modify, or
erased by a programmer. Therefore, EEPROM is used to memorize data, which
require modification for multiple times.
An EEPROM cell array is composed of floating gate transistors (see Fig. 13.4).
Floating gate technology was invented and published by Simon M. Sze and Dawon

Fig. 13.2 Simplified

schematic of bipolar PROM
13 Products of Digital Integrated Circuit 197

Fig. 13.3 ERPOM

Fig. 13.4 Cross-sectional

view of floating gate transistor

Kahng from Nokia Bell Labs in 1967 [21, 22]. In 1977, EEPROM using
Fowler–Nordheim tunneling was invented by Eliyahou Harari from Hughes Air-
craft, which was acquired by General Motors in 1985. In the early days, EEPROM
can only allow single-byte operation. It now can allow multi-byte page operations
for more than one million times. The erase speed limitation of EEROM results in the
invention of flash memory, which has an advantage in the capability of operating
erase in a block.
Emerging nonvolatile memories, such as phase change memory (PCM) or resis-
tive random access memory (RRAM), are gradually replacing EEPROM in specific
applications. Advanced Memory Semiconductor Co. (AMS) in Jiangsu, China,
launched a PCM-based EEPROM in 2019.

Flash Memory

Flash memory is a kind of nonvolatile memory (NVM). Common flash memory

restrains two types of technologies: NOR flash and NAND flash memory. Fujio
Masuoka, an engineer from Toshiba, invented NOR flash in 1984 and NAND flash
in 1987; he received the IEEE Morris N. Liebmann Memorial Award in 1997.
198 D. Hu et al.

In 1988, Intel launched the first NOR flash product. NOR flash technology
featured as eXecuted In Place (XIP), which can execute programs without copying
the code into RAM. Based on NOR flash technology, Mitsubishi and Hitachi
invented divided bit-line NOR (DINOR) structure [23]. Compared with NOR
flash, DINOR flash is slightly slower in byte-write operation, but it is also faster in
block-erase and block-write operations. Major NOR flash manufacturers are four
IDMs, including Micron Technology, Spansion (merged in 2014 to Cypress, who
was in 2020 merged to Infineon), Macronix, and Winbond.
NAND flash was launched by Toshiba in 1989. It has higher erase/write operation
speed but has simpler erase circuitry than NOR flash. Based on NAND flash
technology, ultra NAND [24] is invented by AMD and Fujitsu. Ultra NAND is
compatible with conventional NAND flash, with better reliability and higher storage
efficiency. Ultra NAND flash is suitable for high-reliability application, such as SSD.
Characteristics and applications of flash memories are listed in Table 13.4. Major
NAND flash manufacturers are four IDMs, including Samsung, Toshiba, SK Hynix,
and Micron.
Among them, NAND flash comes with the highest capacity. It is commonly
used in a variety of digital terminal devices. The data content in NAND flash is
stored in memory cells, which are characterized as three types, including SLC,
MLC, and TLC cells (single-level cell, multi-level cell, and trinary-level cell).
Numonyx (acquired by Micron in 2010) produced floating gate structural NAND
flash made in SLC and MLC type and is capable of write and erase for 105–106
cycles count. SLC, MLC, and TLC NAND flash characteristics are compared in
Table 13.5.
In advanced technology process node, the oxide layers in NAND flash become
thinner and consequently weaken the reliability of the NAND flash. Without moving
to more advanced technology, 3D NAND flash memory (3D NAND) can expand
capacity from planar NAND flash by stacking memory array layers. Memory
vendors launched variable 3D flash, e.g., V-NAND (vertical NAND) developed by

Table 13.4 Characteristics and applications of flash memories

Type Characteristics
NOR flash eXecuted In Place, high reliability, fast
random access read/write operation,
slow block read/write operation, byte
writable but not byte erasable
NAND Fast block-write operation, bad block
flash management, low cost, slow random
access read/write operation, no byte
read/write operation, driver required
EEPROM Combination of EPROM and NOR Flash.
flash faster random access read operation than
NOR Flash, fast read/write operation,
lower cost than EPROM
Applications
Suitable for smaller capacity
application, such as BIOS memory
in PC
Suitable for high-capacity application,
such as SSD
Suitable for small capacity. Replacing
EPROM, such as MCU programming
code memory
13 Products of Digital Integrated Circuit 199

Table 13.5 SLC, MLC, and TLC NAND flash performance comparison
Type Bit number per cell Erase/write life time Features
SLC 1 bit/cell 105 cycles High speed, long lifetime, high cost
MLC 2 bit/cell 3
103 – 104 cycles Intermediate speed, life time, and cost
TLC 3 bit/cell 5
102 cycles Low speed, short lifetime, low cost

Samsung, and bit cost scaling (BiCS) 3D NAND co-developed by Toshiba and
SanDisk [25]. 3D NAND technology has been a research hotspot since 2017.
Samsung, Toshiba, Western Digital, Micron, and SK Hynix strengthened investment
in the development of 64- and 72-layer 3D NAND. The first 3D flash was launched
by Western Digital in June 2017. The 128-Layer 3D NAND was in production in
2021 at YMTC, followed by the 192-layer 3D NAND Flash in 2022.

Solid-State Drive

Solid-state drive (SSD) is mainly composed of controller, nonvolatile memory

(NVM), and circuit board. NAND flash is primarily adopted as NVM in SSD.
Compared with hard disk drive (HDD), SSD takes advantages in better vibration
tolerance, lower power consumption, no noise, and higher speed. The capacity of
SSD exceeds HDD. However, the price of SSD is slightly higher than HDD of the
same capacity.
SSD is applied to four major fields. The first one is the consumer electronics
market, including applications in laptop, desktop, and all-in-one computer. The
second field is embedded systems including car PC (or vehicle PC), industrial PC
(IPC), and advertising player (computer). The third is the enterprise and data center
application in server and storage array. The last one is the application for military,
aviation, or medical use.
There are several type interfaces of SSD to choose from, including fiber
channel (128 Gbit/s for server), PCIe (PCI Express, Gen3 X4, 31.5 Gbit/s),
USB (10 Gbit/s), and serial attached SCSI (SATA, 12 Gbit/s for server) [26]. In
the consumer electronics market, SATA is commonly adopted, but PCIe is
gradually widespread. In the enterprise and data center market, SATA and PCIe
are dominant. With the development of PCIe Gen3 X4, PCIe gradually dominant
SSD interface in the server due to its higher transmission rate. Each SSD contains
an embedded processor as a controller, which integrates memory and interface
circuits.
The development of IC packaging technology and the trend of slimmer handheld
devices push more on SSD to adopt small size BGA package. PCIe SSD usually
adopts BGA package compliant with PCI-SCG standard. It usually come with
11.5 mm
13 mm, 16 mm
20 mm, 22 mm
24 mm, 22 mm
28 mm, and
28 mm
28 mm. BGA SSD simplifies PCB and reduces the cost by integrating
controller and flash memory. Compared with conventional 2.5 in HDD, BGA SSD is
200 D. Hu et al.

smaller in volume and area. Therefore, BGA SSD can fulfill the storage requirement
of tablet, Ultrabook, and server by saving space and power.
In 2016, enterprise SSD reached 20 PB (petabyte) in capacity and protected data
with redundant array of independent disk (RAID) functionality. Samsung, Toshiba,
and Micron pushed SSD to higher capacity and started mass production of 64-layer
3D NAND in 2017.

Multimedia Card and Embedded MMC

Multimedia card (MMC) was released in 1997 by SanDisk and Siemens. In 1998,
14 companies jointly established the MMC Association (MMCA), which is cur-
rently managed by JEDEC [27]. MMC is mainly used for digital video, music,
smartphones, PDAs, e-books, toys, and other electronic products. Like the SD card,
the MMC is compatible with the same connector slot. There are many types of
MMC, for example, reduced size (RS)-MMC. The size is about half of the MMC,
similar to the MiniSD card. Early MMC used pluggable design, but it is with low
capacity, performance, and having reliability issues.
MMC package type is also used for embedded multimedia card (eMMC); see
Fig. 13.5. Defined by JEDEC in early 2019 [28], the latest standard v5.1A for
eMMC is specifically designed for embedded memory devices, primarily used for
tablet pads or iPads, smartphones, smart TV boxes, educational electronics, etc. As
eMMC is using Surface Mount Technology (SMT) package, so it is high-
performance reliable storage devices.
Inside the eMMC are a logic control chip and a few flash (NAND flash) chips. It
is integrated in a JEDEC standard BGA package [29], as shown in Fig. 13.6. The
functions of the logic controlling chip include (1) providing a standard eMMC
interface for managing the flash memory chip, which is used for receiving external
data from the eMMC interface, writing to the flash chip; (2) reading data from the
flash chip and transmitting it to the external device via the eMMC interface [30].

Fig. 13.5 Package form of eMMC

13 Products of Digital Integrated Circuit 201

Fig. 13.6 Logic components of eMMC

Table 13.6 Comparison of MMC and eMMC

Feature MMC eMMC
Components MMC controlling chip and flash chip eMMC controlling chip and flash chip
Dimensions MMC: 32 mm
24 mm
1.4 mm 11.5 mm
13 mm
1.0 mm (153球)
RS-MMC: 24 mm
18 mm
1.4 mm 12 mm
16 mm
1.2 mm (169球)
12 mm
18 mm
1.2 mm (169球)
14 mm
18 mm
1.4 mm (169球)
Types of 128 MB, 256 MB, 512 MB, 1 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB
capacity 2 GB
Applications Early digital camera, functional mobile Android mobile phone
phone, or basic smartphones

The major manufacturers of NAND flash are Samsung, Toshiba, SK Hynix,

Micron, etc., but their products are not compatible with each other. The memory
driver should be re-deployed following each technical characteristics or performance
of different NAND flash specifications. While for eMMC (Table 13.6) products, the
users only need to follow standard interface to control flash memory, the standard
interfaces for MMC and eMMC have contributed greatly in reducing the develop-
ment difficulty and in speeding up the time to market.
The eMMC can also manage both MLC NAND flash and TLC NAND flash very
well. The firmware program in the controller can be implemented with “error
correcting code (ECC),” “block management,” “wear leveling,” “command man-
agement,” “low power management”, etc. Equipment manufacturers only assemble
eMMC to PCB board and load standard driver; then, it will work well. There is no
need to solve compatibility and management issues. Therefore, eMMC has replaced
NAND flash and became the main memory solution for smart electronic products
such as smartphones and tablets.
202 D. Hu et al.

In February 2015, JEDEC released the eMMC Product Standard 5.1 Edition
(eMMC v5.1). The JESD84-B51 defines a new standard for embedded high-capacity
flash drives that are widely used in smartphones and other mobile devices. To
enhance the end-user experience, the new version of eMMC provides command
queues for the first time and improves security.

Multi-Chip Package Memory and eMCP Memory

Multi-chip module (MCM) is also called by national semiconductor multi-chip

package (MCP) memory, and it is a kind of memory package, where multiple
memory chips are contained in one package [31], while embedded multi-chip
package (eMCP) memory is a hybrid product that combines MCP memory and
eMMC memory together.
The chip types included in the MCP memory can be NOR flash, NAND flash, low
power DRAM, and pseudo-static RAM (PSRAM). The main purpose of using MCP
memory is to save PCB size, as smart handheld and wearable devices have driven the
MCP memory technology toward that goal. There are two kinds of memory chips in
the BGA (MCP package), and the chips are arranged side by side. Depending on the
size and number of internal memory chips, some MCPs may also be stacked on each
other (i.e., top–bottom stacks), or stacked side by side.
MCP memory can increase PCB placement density, improve system perfor-
mance, reduce PCB board and system-level size, improve system quality, enhance
system functionality, reduce PCB routing complexity, improve memory high-speed
performance, and solve signal integrity (SI) issues. MCP supports flip chip, wire
bonding, and SMT process; it also supports Package on Package (PoP) process.
The application of MCP memory is mainly tablet, wearable electronic products,
and smartphones. These products not only have high requirements on smaller
dimensions, but also have high requirements for avoidance of SI issues. MCP uses
the SiP method to integrate different specifications of the chip into a single package.
It has the advantages of short production cycle, low manufacturing cost, low power,
and high-speed transmission. It is the most important specification for the built-in
memory of portable electronic products. Various types of MCP have also been
widely used in digital TVs, set-top boxes, and network communication products.
The main package types of MCP memory are WFBGA, VFBGA, LFBGA, PoP,
etc. Since the internal memory includes a plurality of types of memory, each of the
chips has different uses, so the capacity cannot be added simply, and the storage
capacity is separately listed in different types. Typically, the industry denotes or
defaults to putting flash (NAND or NOR) capacity in front and DRAM capacity in
the back. For example, if an MCP consists of an 8 GB NAND flash and two 2 GB
LPDDR2s, its capacity should be labeled 8 GB þ 4 GB.
The key to the development of MCP technology is the control of thickness and
yield. More chips stacked on the MCP then make MCP thicker, but portable
13 Products of Digital Integrated Circuit 203

electronic products such as mobile phones (especially ultra-thin electronic products)

require as thinner as possible, as well as to avoid production difficulties. The
thickness defined by the MCP chip at birth is about 1.4 mm (currently 0.8 mm). If
one of internal chip fails, the entire module will fail. With the development of
technology, the size of MCP cannot meet the requirements of some devices, so
there is a through-silicon via technology, referred to as TSV technology. TSV is a
new vertical packaging technology for interconnecting stacked chips in 3D inte-
grated circuits [32]. It can optimize the density of chip stacks, interconnect between
chips, external dimensions, and improve signal transmission and low power perfor-
mance. The advantage of TSV technology is to further reduce the package size and
increase the space for product design. TSV offers excellent high-frequency charac-
teristics, reduction in transmission delay, and noise reduction as well. So, it can meet
higher speed design requirements. TSV also can reduce the power of chip up to about
40% and has the advantages of low thermal expansion coefficient and high
reliability.
The eMCP memory is a hybrid memory package that combines MCP and
eMMC features, as shown in Fig. 13.7. The current mainstream eMCP adds mobile
DRAM (LPDDR1/LPDDR2/LPDDR3/LPDDR4) to the eMMC architecture. It
meets JEDEC standard and use the MCP package type [33]. Compared with the
traditional MCP, the eMCP has more eMMC control chips. An eMCP control chip
manages its large-capacity NAND flash memory and reduces the computational
burden of the chip; because of its smaller size, it reduces the number of circuit
connection designs, facilitates compatibility debugging and testing, and thus
facilitates the design and production of smartphone manufacturers. The eMCP
has the same size as the eMMC in the size of 11.5 mm
13 mm
1.0 mm (ultra-
thin size is 11.5 mm
13 mm
0.8 mm). When eMCP assembled eMMC and
DRAM together, it created large capacity, yet it also results in some difficulty to
design – because it might have introduced signal crosstalk and more performance
issues. Normally, the larger capacity needs more chips; however, more chips lead
to lower yield; hence, lower yield results in higher cost. Therefore, the conse-
quence of the impacts has become the difficulties for eMCP to serve the high-end
market. The scope and difference of mainly MCP and eMCP in mobile phones are
shown in Table 13.7 [34].

Fig. 13.7 Structure and

package form of eMCP
204 D. Hu et al.

Table 13.7 Applications and differences of MCP and eMCP in mobiles phones
Types MCP eMCP
Components NOR flash+LPDDR2 or NANDF NAND flash+eMMC controlling
flash+LPDDR2 chip+LPDDR3
Packaging 8.0 mm
9.0 mm
1.0 mm 11.5 mm
13 mm
1.0 mm
(130 solder balls) (162 solder balls)
10.5 mm
13.0 mm
1.0 mm 11.5 mm
13 mm
1.0 mm
(137 solder balls) (221 solder balls)
10.5 mm
8 mm
1.0 mm
(162 solder balls)
Storage capacity 2 GB þ 2 GB 8 GB þ 4 GB
4 GB þ 2 GB 8 GB þ 8 GB
4 GB þ 4 GB 16 GB þ 16 GB
32 GB þ 24 GB
64 GB þ 32 GB
128 GB þ 32 GB
Applications Functional mobile phone or low-end Mid- or low-end mobile phone
smartphones

Typical features of eMCP memory are the ability to implement more powerful
functions through chip integration: (1) increased design density and performance,
(2) reduced board and system-level size and quality, (3) reduced PCB board area,
(4) reduced PCB routing complexity, (5) reduced additional cost of using other chips
in PCB board level, (6) reduced time to market, and (7) reduced product design
difficulty.
With the development of 3D NAND flash and LPDDR4 standard, eMCP will
become larger and faster. In view of the features of eMCP memory, they are used not
only in mainstream portable electronic products such as smartphones but also are
used in many other consumer electronic products or devices that require data storage.

X86 Processors

X86 Instruction Set Architecture (ISA) first appeared in the 8086 CPU of the 16-bit
processor that Intel introduced in 1978, and the 8086 CPU evolved from the early
Intel 8008 CPU. Since IBM started working with Intel to launch a PC-based 8086
CPU, it has achieved great success in the market, which has made the x86 architec-
ture a PC standard platform and is recognized as the most successful CPU architec-
ture. The term “x86” came from the names of several successors to 8086 processor
ending in “86,” including the 80,186, 80,286, 80,386, and 80,486 processors.
In addition to Intel, there were other companies that originally design x86
architecture processors, but most of the companies lost in the market competition
with Intel and gradually abandoned. The only competitor in x86 architecture pro-
cessors with Intel is AMD.
In 1985, Intel introduced the 80,386 CPU based on 32-bit, which extended the
x86 architecture digits and improved the performance of the CPU. The x86 is well
13 Products of Digital Integrated Circuit 205

known as the complex instruction set computer (CISC) architecture with variable
instruction lengths. The CISC block (word, 4 bytes) is stored in the corresponding
memory in the order of the low byte first and the high byte after, and the memory
allows the address not to be aligned when the access is called [35]. Compared with
other common ISAs, such as reduced instruction set computer (RISC) and explicitly
parallel instruction computing (EPIC), CISC does not have obvious advantages, and
even many computing experts believe that CISC is not efficient.
Forward compatibility is both a major force driving the development of x86 and a
major historical burden that plagues the performance of x86. New version of Intel
x86 architecture, which converts x86 instructions into RISC-like microinstructions,
is then executed to achieve comparable performance with RISC while still
supporting forward compatibility.
By 2002, due to the 32-bit digital length limitation, x86 began to reach the
theoretical limit of design. When dealing with data storage larger than 4 GB, it
would be difficult and inefficient, especially for database and video processing
applications. This limitation is more apparently exposed.
Intel has decided that the new Itanium processor will adopt the new x86 for 64-bit
architecture (IA-64) and will abandon the forward compatibility feature, but IA-64 is
inherently incompatible with x86 software, and it can only run x86 software in a
variety of analog or virtual ways. Obviously, this kind of support will occupy the
corresponding computing resources of the processor, resulting in very inefficient
operation and affecting the operation of other parallel programs. AMD used a
completely different strategy, inherited and developed the x86 architecture, and
expanded the x86 architecture to 64-bit (named AMD-64) based on the 32-bit x86
architecture (or IA-32), and AMD introduced the first 64-bit x86 CPU product based
on AMD-64 architecture, including the single-core Opteron and the Athlon 64 pro-
cessor family in 2003 [36]. AMD-64 meets the customer’s requirements for com-
puting digits and computing power.
Since AMD introduced the 64-bit x86-based CPU in the market before Intel, due
to Microsoft’s compatibility with operating systems, Intel was forced to adopt the
AMD 64 instruction set and added some new instructions based on it. The instruc-
tions are extended to their own 64-bit architecture, and Intel using the name EM64T.
EM64T was officially renamed Intel 64 (also known as x86-64, x64, x86_64) due to
marketing reasons [37].
X86 was extended from 32 bit to 64 bit and was first promoted and launched in
1999–2000 by AMD, not Intel. This major improvement and upgrade made AMD a
very good success in the market at that time, once able to compete with Intel. The
main products of the x86 architecture-based processors introduced over the years are
shown in Table 13.8.
The x86 family of processors is very successful, and it is widely used in PCs,
servers, workstations, and other fields. Currently, PCs that dominate the market
(including Apple MacBook series) are using x86 architecture processors, but Google
Chromebook partially uses ARM architecture processors. CISC-based x86 ISA from
Intel theoretically limits CPU perform further. To maintain its leading position in the
206 D. Hu et al.

Table 13.8 Main products of x86 architecture-based processors introduced over the years
Linear
Introduction Prominent CPU models address/bit
1978 Intel 8086, Intel 8088 (1979), and its derivatives 16
1982 Intel 80,186, Intel 80,188 and its derivatives, NEC V20/V30 16
1982 Intel 80,286 and its compatible products and their derivatives 16
1985 Intel 80,386 and its compatible products, AMD Am386 (1991) 32
1989 Intel 80,486 and its compatible products, AMD Am486 (1993) 32
1992 Cyrix Cx486SLC, Cyrix Cx486DLC 32
1993 Pentium, NexGen Nx586 (1994), Rise mP6 (1998) 32
1995 Pentium Pro, AMD Am5x86, Cyrix 5x86 32
1996 Pentium MMX, AMD K5, Cyrix 6x86/MII, Centaur IDT-C6, 32
VIA Cyrix III (Samuel 2)
1997 Pentium Overdrive, Pentium II, AMD K6 32
1998 Celeron, Xeon, AMD K6-2 32
1999 Athlon, Athlon XP (2001), Pentium III, AMD K6-III 32
2000 Pentium 4, Cyrix III-Samuel, Transmeta Crusoe 32
2001 Itanium IA-32, VIA C3 “Ezra” (C5C), Transmeta Efficeon 32
2003 Pentium M, AMD Athlon 64, Opteron 64
2004 AMD Sempron, Prescott 64
2005 Prescott 2M, Pentium D, VIA C7 64
2006 Intel Core Solo/Duo 64
2007 DM&P Vortex86, Athlon 64 X2, AMD Phenom 32
2008 Intel Core i7 (Nehalem/Westmere), AMD Phenom II, VIA 64
Nano, Intel Atom
2009 Intel Core i5 64
2010 Intel Core i3 64
2011 AMD FX, AMD APU C, E, and Z series (Bobcat) 64
2011 AMD APU A and E series (Llano) 64
2011 AMD APU A series (bulldozer, trinity and its derivatives) 64
2011 Intel Core i3, Core i5 and Core i7 (Sandy Bridge/Ivy Bridge) 64
2012 Intel Xeon Phi (Larrabee) 64
2013 Intel Core i3, Core i5 and Core i7 (Haswell/Broadwell) 64
2015/2016 Intel Core i3, Core i5 and Core i7 (Skylake/Kaby Lake/ 64
Cannon Lake)

market, Intel not only improves the performance of x86 through advanced technol-
ogies, but also does a lot of optimization and improvement on x86.

IA-64 Processors

The IA-64 processors were the abbreviation of Itanium architecture processor in the
beginning, which supports 64-bit processing. However, due to the lack of market
recognition of Itanium processors, Intel must launch a new Intel architecture, which
13 Products of Digital Integrated Circuit 207

is compatible with x86–64 instruction set. The IA abbreviation usually refers to Intel
architecture processor at present.
The IA-64 was created by Hewlett-Packard (HP) in 1989 [39]. HP thought both
CISC and RISC architectures have some drawbacks. RISC executes only one
instruction during each CPU cycle, while CISC architecture is designed to execute
multiple instructions under one clock, but it needs a high-performance decoder to
decompose instructions into RISC-style microinstructions. HP has proposed a new
architecture named explicitly parallel instruction computing (EPIC). It is composed
of three instructions into a single–instruction package using very long instruction
word (VLIW). Each instruction package contains a series of RISC instructions that
can be executed concurrently, which makes EPIC a great potential to replace the
other two architectures, but as a system company, HP does not have the ability to
develop processors independently. So, in 1994, HP cooperated with Intel to develop
EPIC-based processors. In 1999, Intel renamed the processor to Itanium processor.
At the beginning, Intel and Hewlett-Packard believed that IA-64 would become
the mainstream of the future computer server, workstation, and high-performance
computer market. Although the EPIC instruction set is incompatible with x86
architecture processor, while the IA-64 processor has 64-bit data path, 64-bit storage
space, and 64-bit parallel computing capability, which breaks through many limita-
tions of traditional 32-bit architecture. These improvements are expected to greatly
improve the efficiency of data processing, stability, security, availability, and man-
ageability of the system. Many companies are attracted by the potential of IA-64 and
decide to join the EPIC architecture group. Compaq (acquired by HP in 2001) and
Silicon Graphics (acquired by HP in 2016) decided to abandon DEC alpha and MIPS
architectures and changed to develop IA-64 instead. At the same time, the operating
systems based on IA-64 have been developed one after another, including HP-UX
(Hewlett-Packard Unix), Solaris (Sun Microsystems, acquired in 2010 by Oracle),
Tru64 UNIX (owned by DEC, Compaq, then HP), and Project Monterey (IBM and
others).
However, IA-64 processor requires lots of transistors for ultra-long instruction
words and many caches, which seriously affects the overall performance of the
processor. Therefore, when the first generation of Itanium processor was introduced
in 2001, their performance was inferior compared to that of RISC and CISC pro-
cessors of the same generation. In addition, there are many problems in the research
of IA-64 processor compiler, which delayed in the progress of development. How-
ever, the most important reason for IA-64 architecture failure is incompatibility with
x86 instruction set, which requires developers to re-develop programs and create
new ecological environment. Meanwhile, as a competition, AMD added 64-bit
register based on the x86–32-bit architecture and worked out the AMD-64 architec-
ture processors, which are compatible with 16-bit and 32-bit software forward,
which allows the early x86 compiler be used in AMD-64 architecture processors
[38]. The good compatibility of AMD-64 architecture led operating system manu-
facturers to gradually abandon their support for the IA-64 architecture. Oracle and
Microsoft quit the IA-64 camp in 2011 and 2013.
208 D. Hu et al.

Facing the rapid development trend of AMD-64 architecture and the pressure
from software industry, Intel obtained the authorization of AMD X86–64 extended
instruction set by cross-licensing with AMD and developed the Intel 64 architecture,
namely x86–64 architecture.

POWER Family Processors

In 1974, John Cocke and his team at IBM Research began work on designing a
controller for telephone exchange, and the project was leading to the first prototype
reduced instruction set computer (RISC) in 1980 [39], based on CYK algorithm. The
RISC architecture design enabled computers to execute computing tasks with the
simplest instructions and execute each instruction per clock cycle or a few clock
cycles, which will enable computers run much faster and more powerful.
In 1990, the first CPU from IBM that incorporates the Performance Optimized
With Enhanced RISC (POWER) instruction set architecture (ISA) was introduced
into the market and called POWER1 CPU [40]. In 1993, IBM announced the
POWER2 processor, which had leadership performance at that time.
In 1998, IBM announced that the POWER3 processor, a 64-bit symmetric multi-
processor, supports 32/64-bit both PowerPC ISA and POWER ISA. The subsequent
POWER family microprocessors are all 32/64-bit architectures.
In 2017, IBM launched the latest POWER-based microprocessor POWER9.
POWER9 is manufactured with a 14 nm FinFET process and the performance is
much more powerful than those of x86 processors, POWER10 was made in 7 nm,
and POWER11 is being forecasted. POWER architecture products are summarized
in Table 13.9.
IBM POWER-based server microprocessors are mainly built for high-end server
market. Comparing the POWER processor with x86 processor, the former takes the
advantages in data-intensive and high-performance computing. In hardware,

Table 13.9 Summary of POWER architecture products

Release year Product CPU frequency Technology
1990 POWER1 25–62.5 MHz 1.0 μm
1993 POWER2 55–71.5 MHz 0.25 μm
1998 POWER3 200 MHz 0.22 μm
2001 POWER4 1.1–1.9 GHz 0.18 μm/0.13 um
2004 POWER5 1.5–2.3 GHz 0.13 μm/90 nm
2007 POWER6 3.6–5 GHz 65 nm
2010 POWER7 2.4–4.25 GHz 45 nm
2013 POWER8 2.5–5.0 GHz 22 nm
2017 POWER9 4 GHz 14 nm
2020 POWER10 >4 GHz 7 nm
13 Products of Digital Integrated Circuit 209

POWER architecture uses symmetric multi-processing (SMP), which makes multi-

ple processors work in parallel and use a single operating system and share the
common memory and I/O resources. POWER architecture is modular and scalable
with increasing the CPU numbers, and the performance will be higher. In software,
IBM AIX operating system is secure, scalable, and robust. Many featured software
and tools work on POWER system.
The x86 servers market share is about 90% with three main reasons. First, the x86
server ecosystem has more than 30 years of development; it is robust and cost-
effective. Second, the business computing model such as cloud computing will
provide competitive services in existing server market, which are going to replace
minicomputer. Third, IBM competes with others on chip, system, and server market,
while x86 chip vendors as Intel or AMD are focused to provide the chips and
corporate with others.
In 2013, Google, IBM, Mellanox, Nvidia, and Tyan announced to form the
OpenPOWER Foundation. IBM opened up POWER technologies, include chip
specifications, microcode and software, and enable third-party vendor join the
ecosystem for POWER and build customized hardware. Currently, Google, IBM,
Inspur, and Yadro are platinum members of OpenPOWER [41].
To compete with Microsoft and Intel in PC and low-end workstation market,
Apple–IBM–Motorola formed an alliance known as AIM in 1991. They developed
Performance Optimization With Enhanced RSIC-Performance Computing
(PowerPC) architecture, which is based on IBM POWER ISA [4]. In 1993, IBM
released the first-generation single-chip PowerPC processor, which is a
high–performance superscalar microprocessor, supports 32-bit address bus and
64-bit data bus, and supports 32-bit integer operations and IEEE 754, single- and
double-precision floating-point operations, and SMP features.
From 2006, PowerPC could be licensed to third-party companies and allow them
to design and manufacture the compatible processors. PowerPC has three main
product lines, 32-bit PowerPC 700, 64-bit PowerPC, and embedded PowerPC
400 [42].
PowerPC is energy-efficient, ecosystem is limited and slowly updated, and it
cannot compete with x86 system. In 2005, Apple adopted a new x86 processor
indicating PowerPC failed partially in PC market. Nevertheless, PowerPC is still
used in automotive, aviation, and networking.

MIPS Processors

Microprocessor without Interlocked Pipeline Stages (MIPS) processor is one of the

popular RISC architecture processors that can avoid the conflict and risk of pipeline
by software. John L. Hennessy team of Stanford University researched and devel-
oped MIPS processor in 1981 and founded the MIPS Computer Systems in 1984.
210 D. Hu et al.

Fig. 13.8 Classification of

MIPS architectures

The first 32-bit MIPS processor named R2000 was released in 1985 and then
released 64-bit processer R4000 in 1991. The series of processors were widely
used in SGI workstations, DEC workstations and servers, and other computer
systems during the 1990s [43].
There were two MIPS architectures: 32 bit and 64 bit, as showing in Fig. 13.8.
Many versions of MIPS ISA existed, such as MIPS I, MIPS II, MIPSIII, MIPS IV,
MIPS V, MIPS32, and MIPS64. Both MIPS32 (32 bit) and MIPS64 (64 bit) define a
set of control registers and instruction sets, and there are some extensible instruction
options available to be selected, such as MIPS-3D [44–46].
MIPS is a module-based architecture, which supports four coprocessors (COP0/1/
2/3). In general, COP0 is defined as system control coprocessor. COP1 is a floating-
point unit (FPU). COP2 and COP3 are undefined selected coprocessors. For exam-
ple, in early PS game machine from Sony, COP0 was defined as system control
coprocessor, and COP2 was used as geometry transfer engine (GTE), while at PS2
product, COP0 is R5900 chip design by Toshiba, COP1 is defined as FPU, and
COP2 was used as VPU0.
MIPS processor was the hotspot of RISC CPU design and widely used in the
mid-1980s. About one-third of RISC microprocessors were based on MIPS archi-
tecture in the mid- to late 1990s; it was the most competitive RISC CPU architecture
in the market at that time. Today, there are three architectures compete against each
other: ARM RISC architecture, MIPS RISC architecture, and x86 CISC architecture.
MIPS architecture processors were mainly used in the embedded system, router,
Internet gateway, media game control center, and other application fields. MIPS
Technologies, Inc., was merged by Imagination Technologies Group plc in 2013,
and MIPS architecture thus continued. For example, Loongson processor was based
on MIPS architecture and be used at Shuguang 6000 supercomputer.
13 Products of Digital Integrated Circuit 211

ARM Processors

Acorn RISC Machine (ARM) was the first RISC microprocessor designed in 1985
by Acorn Computers Ltd. in Cambridge, England (founded in 1978). Spun off from
Acorn Computers Ltd., advanced RISC machine was established in 1990. ARM
Holdings has been a new name at its IPO in 1999 [47, 48]. ARM processors have
general characteristics of the RISC architecture. For example, fixed length instruc-
tion format, single-cycle command pipelining operation, using many registers, data
processing instruction just deal with registers. Only load/store instruction can access
memory to improve the efficiency of the operation of the instruction.
Early ARM processors support simple instruction set, and they have features of
low power and low cost and suited for mobile device and widely used in embedded
systems. From ARMv4 (ARM7 series), the performance focused on power-sensitive
wireless devices; from ARMv7, the applications have extended to other areas. After
Cortex-A9, the performance of ARM processors improved a lot, and gradually used
in enterprise devices and servers. The new ARMv8 architecture ARM64 is suitable
for the application of large memory, virtualization, security, and ARM development
[49]. Table 13.10 lists the technical features, application scenarios, and processor
names of the latest CPU architecture Armv7 and Armv8. Table 13.11 lists the release
time, versions, names, and applications of the ARM AMBA buses.
According to application domains, ARM products can be divided into A, R, and
M series. For example, Cortex-A series can be widely used on wireless devices,
network infrastructure, home and consumer electronics, in-vehicle infotainment
(IVI), and other embedded systems. Cortex-R series can be used in medical equip-
ment, aeronautics, and astronautics, because of their high reliability and high
security. Cortex-M series are developed for Internet of Things (IoT), and they belong
to smart embedded application processors, which can work efficiently and easy to
use. Through coding effort for standard safety system and open platform, Cortex-M
can help the designers to develop many kinds of market demanded products in a
short time with lower cost.

Table 13.10 Features and applications of ARM processors

Architecture Features Applications Processors
Armv7-A A32(32b) Multicore design Cortex-A5/A7/A9; A17
T32(32b,16b mixed)
Armv7-R 32b High performance Cortex-R4/R5/R7
Armv7-M 32b Low power Cortex-M0/M0+/M3/M4/M7
Armv8-A 32b/64b Smartphones Cortex-A53/A57/A72
Armv8-R 32b MMU, MPU Cortex-R series
Armv8-M 32b (16b) MCU/loT Cortex-M0/M0+/M3/M4/M7/m
Armv9.0-A 64b AI/IoT Cortex-A510/A710/A715/X2/X3
etc.
212 D. Hu et al.

Table 13.11 Release time, versions, features, names, and applications of ARM AMBA Bus
Year of Bus/ Application
release Version Interface Full name examples
1996 AMBA ASB, APB Advanced system bus, and
advanced peripheral bus
1999 AMBA2 AHB High-performance bus A7, A9, Cortex-M
Series
2003 AMBA3 AXI, ATB Advanced extensible interface, Cortex-A Series,
advanced trace bus Include Cortex-A9
2010/11 AMBA4 AXI4, ACE Advanced extensible interface 4, Cortex-A Series,
AXI coherency extensions Include A7/15
Languages, etc.
2013 AMBA5 CHI Coherent hub interface Support
(Verification) VIP,
SystemVerilog

UltraSPARC Processor

UltraSPARC architecture is based on RISC ISA, originally developed at Sun Micro-

systems aimed at high-end applications; the initial version was the Scalable Proces-
sor ARChitecture (SPARC), one of the superscalar instruction sets. To increase its
adoption and expand its ecosystem, Sun authorized several vendors to use, which
included TI, Cypress, and Fujitsu; later fully opened up to any company, organiza-
tion, or individual to develop SPARC-based processor or other products, as long as
they are authorized to.
The design goal of SPARC processor [50] was for increased efficiency of the
compiler, easy to implement the HW pipeline instructions, and thus to increase
operational and executable speed, such that to help users to reduce time and period
of the product development. Due to the provided scalability and benefit of cost
efficiency, the technical specifications of SPARC can be used as embedded, or CPU
of servers. There were three important revised versions of SPARC, viz. 32-bit
SPARC V7 in 1986; 32-bit SPARC V8 in 1990; and 64-bit SPARC V9 [51] in
1993. All of these were forward compatible.
SuperSPARC [52] is based on SPARC V8 ISA, developed in 1992 by Sun and
fabricated by TI in Japan. SuperSPARC had two derivatives: SuperSPARC+ and
SuperSPARC-II, and the later was replaced in 1995 by UltraSPARC. SPARC64 V
(Zeus) was based on SPARC V9 and designed by Fujitsu [53]. The SPARC64 V
became the basis for a series of successive processors designed for servers and later
supercomputers. The server series are the SPARC64 V+, VI, VI+, VII, VII+, X, X+,
and XII. As of October 2017, the SPARC64 XII is the latest server processor, and it
is used in the Fujitsu and Oracle M12 servers.
Based on SPARC V9 ISA, UltraSPARC was developed in 1995. UltraSPARC III
chip first appeared in June 1999. Adopted Visual Instruction Set (VIS), it supported
64-bit, clock 600 MHz, fabricated on then advanced 0.18 μm process. The obvious
13 Products of Digital Integrated Circuit 213

feature was that it supports up to 1000 processors of the same type for a
co-processing; the highly expandability is most suitable for large server, providing
high-performance computing; and for workstations as well. In 2006, Sun announced
the new specifications of UltraSPARC, named as UltraSPARC Architecture
2005 [54].
UltraSPARC Architecture 2005-based processors are mainly for workstations, for
example, Sun and Fujitsu designed SMP servers. Specifically, Sun developed Solaris
OS for UltraSPARC, and others, such as NeXTSTEP (NeXT Computer), Linux,
FreeBSD (Berkeley Software Distribution), OpenBSD, and NetBSD systems also
provided OS for SPARC versions.
Sun promoted several 64-bit UltraSPARC III processors, which were succeeded
by UltraSPARC IV processors. UltraSPARC IV+ had a clock frequency of 1.5 GHz.
In 2009, Oracle Corporation acquired Sun Microsystems and continued to promote
HPC processors. Oracle published in 2007 the Roadmap of SPARC and its related
Solaris.

C-SKY Processors

C-SKY architecture-based processors, with independent intellectual property (IP) of

local 32-bit series-embedded CPU cores, are developed by C-SKY Microsystems
founded in 2001 [55]. Users have option to design their own processor based on the
C-SKY V2-independent instruction architecture, configured by different hardware
units, tailored to their needs. C-SKY processors (CK products) have experienced two
stages of development: 1) adopted SIMCODE instruction set to develop two embed-
ded CPUs (CK510 and CK610); 2) developed its own instruction set from 2004.
Alibaba Group Holding [56] acquired C-SKY Microsystems in 2018.
According to market needs, C-SKY processors are divided into series of low cost,
low power, and medium performance, such as CK801, CK802, and CK803, and
series of high efficiency, high performance, and high computing power, such as
CK610, CK807, CK810, and CK860. The technical features of CK-CPU series are
listed in Table 13.12.
Focused on various technical sectors, C-SKY processors are applied in specific
fields (expressed as tailorable hardware function module), mainly in the following

Table 13.12 Features of CK-CPU products

Features CK610 CK810 CK807 CK803 CK802 CK801
Instruction width, bit 16 32/16 32/16 32/16 32/16 32/16
Pipeline 8-stage 8-stage 8-stage 3-stage 2-stage 2-stage
Issue width Dual Dual Dual Single Single Single
Memory management MMU MMU MMU MPU MPU MPU
General register, bit 16 þ 16 32 þ 16 32 þ 16 16 16 8
Performance, DMIPS/MHz 1.78 2.5 2.0 1.5 1.0 0.7
Remark: Dhrystone million instructions executed per second (DMIPS)
214 D. Hu et al.

four aspects. (1) Security: CK-CPU can be applied to debit cards security, where
CPU technology with the highest level of confidentiality is a must, as well as to the
sensitive information and code isolated by trusted execution environment (TEE)
technology, to application signature and to accelerated password algorithm. The
security technology of CK-CPU covers such fields as resistance to time attack,
differential power analysis, error injection resistance, and resistance to buffer over-
flow. (2) High-efficient computing: CK-CPU offers highly efficient computing
ability through configured vector engine for multimedia, digital signal processing
(DSP) engine and floating-point unit (FPU), and other hardware units. CK-CPU can
enable extra computing power and perform common operations such as Fourier
transform, trigonometric functions, and various filters, to allow these computing
tasks more convenient and efficient. (3) Storage subsystem: CK-CPU supports
cache, scratch-pad memory (SPM), and storage enhancement, and CK-CPU
enhances the software operating efficiency. (4) Multicore: It supports symmetrical
and asymmetrical multicore designs, making C-SKY processors able to deal with
more complicated in hybrid and high-level SoC architecture design, and it can
maximize its energy efficiency as a central processor.
CK-CPU processors are equipped with processor design and verification plat-
form, compiler and debugger, embedded operating system, C-Sky Development
Suite (CDS), and CDK (C-Sky Development Kit), and support mainstream embed-
ded operating systems, such as Alibaba YunOS, FreeRTOS, uCos, and eCos. These
are useful for SoC designs to adopt CK-CPU for both hardware and software
developments.
Gradually, CK-CPU series processors are being widely used in China, and their
product forms are diversified and scalable, to be further applied in SoC security and
cloud services infrastructure.

Graphics Processing Unit (GPU)

A graphics processing unit (GPU) [57] is an accelerator-type of ASIC design that

used to create and process 2D/3D graphics operations and output data to display
devices. Before the term GPU has been widely used, many ASICs are designed as
accelerate engine for 2D graphics or limited 3D graphics operations. In 1999, Nvidia
announced the GeForce 256 as “the world’s first GPU” [58]. It was defined as a
“single-chip processor with integrated transform, lighting, triangle setup/clipping,
and rendering engine, which can process over 10 million polygons per second” [58].
ATI Technologies created the term “visual processing unit” (or VPU) with the
release of the Radeon 9700 in 2002, which is similar to GPU [59].
In computer industry, the GPU is a stand-along chip in video card or embedded on
the motherboard or as a submodule, which is integrated into central processing unit
(CPU). In mobile device, GPU generally is an IP and is integrated into SoC. GPUs
are widely used in game consoles, personal computers, workstations, and mobile
devices for graphics operation and display. They are also equipped to datacenter and
supercomputer for data processing.
13 Products of Digital Integrated Circuit 215

Generally, applications make calls to graphics Application Program Interface

(API) and to command GPU computing 3D geometry. A typical 3D GPU will do
following operations. First step is the processing of vertex of 3D model, such as
transform, and lighting using Vertex Shader. Second step is the processing triangle
setup transform vertex of 3D model to 2D-based viewpoint, and the complex
polygon will be resolved into triangle and discard the overlap part. Third step is to
transform the vectorgram to bitmap, using what is called Rasterizer. Forth step is the
use of Pixel Shader to process each pixel, use texture mapping unit (TMU) to find
out the pixel texture, and calculate the color and transparency. Fifth step is to use
Raster Operations Pipeline (ROP) to do final operations, and the composited images
are transferred to fame buffer for display; see Fig. 13.9.
In the graphics processing, computing efforts are spent on the large data work-
loads of vertexes/triangles and pixels/fragments; the modern GPUs are required for
real time, high speed, and parallel processing. With the development of architecture,
software programmability, and progress of manufacturing process, GPUs are opt to
not only work for graphics but also work in general-purpose data processing, the
so-called general-purpose computing on GPU (GPGPU) [60]; see Table 13.13. In
some type of GPGPUs, the display part is removed and dedicated to data processing
only. More and more GPGPUs are installed in supercomputers and high-
performance computers and provide them the power to accelerate the data
processing.
CPUs using very long instruction word (VLIW) architecture can approach
instruction-level parallelism (ILP), while GPUs are for data parallelism, a new
architecture called heterogeneous system architecture (HSA) [61], is developed to
make these various devices work together on the same bus with shared memory and
task. The HSA combining CPU and GPU designs is widely used on gaming and
entertainment, cloud and data center, self-driving cars, deep learning in AI, auton-
omous machines, design, and visualization areas.

Fig. 13.9 An example of GPU workflow

 216

Table 13.13 Development of parallel architecture and software programmability of GPUs

Year Product Feature GAPI Process Programmability General purpose
1999–2001 GeForce 256 Fixed function pipeline DirectX 7/ 220 nm–180 nm N N
Radeon OpenGL 1.2
2001–2002 GeForce 3 Vetex+pixel shader DirectX 8/ 150 nm Limited N
Radeon R200 OpenGL 1.3
2003–2007 Radeon R300 Vetex+pixel shader DirectX9/ 150 nm–90 nm Y Limited
GeForce FX OpenGL 2.0
2007–2009 GeForce 8 Unified shader/ DirectX 10/ 80 nm–55 nm Y Y
Radeon R600 IEEE754 float point OpenGL3.3/
2009–2014 Radeon HD5000 Unified shader/CUDA/multithread/ DirectX 11/ 40 nm–28 nm Y Y
GeForce 400 IEEE754 double floating point OpenGL4.x/
OpenCL1.1
2015– GeForce 900 Unified shader/HSA/multithread DirectX 12/ 28 nm–12 nm Y Y
Radeon Rx 200 OpenGL4.x/
OpenCL1.2
D. Hu et al.
13 Products of Digital Integrated Circuit 217

In the last century, SiS, VIA, S3 Graphics, 3dfx, and Matrox were the vendors in
personal computer for 2D/3D cards, and today, Nvidia and AMD are the leading
GPU vendors. In mobile device including smartphones and tablets, the GPU prod-
ucts are seeking applications and competing with others such as Imagination,
Qualcomm, and ARM. The latest products from Nvidia include high-performance
Tensor Core GPU A100 and H100. A100 is manufactured with TSMC 7 nm,
containing 54
109 transistors and maximum power 400 W, while to date H100
containing 80
109 transistors can reach a computility of 67 TFLOPS at FP32. It is
said that H100 is seven times better than A100 for HPC applications.

Microcontroller Unit

A microcontroller (MCU), also called single-chip microcomputer, is a small com-

puter on a single IC [62, 63]. It is believed that TI engineers Gary Boone and Michael
Cochran created the first microcontroller TMS 1000 in 1971, which became com-
mercially available in 1974. The TMS1000 family MCU then enjoyed a tremendous
success in consumer electronics at that time.
The diagram of MCU architecture is shown in Fig. 13.10. The CPU is the core of
MCU and is responsible for arithmetic processing and controlling. The memory
consists of on-chip program memory and data memory. The memory can be ROM,
one-time programmable (OTP), multiple-time programmable (MTP), eFlash, or
SRAM, which may appear in various product forms. All the memories can transfer
instructions or data by CPU through bus or interface. The direct memory access
(DMA) controller is used to transfer data between memory and I/O directly with high
speed. The MCU can integrate different interface controllers according to

Fig. 13.10 Diagram of MCU architecture

218 D. Hu et al.

applications, such as inter-integrated circuit (I2C) bus, integrated inter-chip sound

(I2S), universal asynchronous receiver/transmitter (UART), serial peripheral inter-
face (SPI), controller area network (CAN), universal serial bus (USB), and serial
digital interface (SDI). Timer is a basic component in an MCU; it can be categorized
into general-purpose timer (GPT), real-time clock timer (RTC), motor control timer,
and pulse-width modulation timer (PWM). As a small system-on-chip design, the
MCU integrates power, clock, and reset controlling components. Low dropout
regulator (LDO) is used for power on/off and reset; oscillator/PLL is responsible
for stable, reliable on-chip clock source. There is also power on/off controlling logic
to optimize power consumption according to the performance requirement. Besides,
the MCU can also integrate ADC, DAC, operation amplifier, or other analog
components.
The MCU can be classified into 8-bit, 16-bit, 32-bit, or 64-bit series according to
the instruction bit width of the CPU. Intel 8051 is a typical 8-bit MCU. A popular
32-bit one is usually with ARM Cortex-M core. MCU provides many kinds of
processing performance or operating frequency according to which CPU is used.
The 8-bit and 16-bit CPU have more advantage on power consumption and area, but
less processing performance, than 32 bit and 64 bit. The MCUs can also be classified
into ROM-type, OTP/MTP-type, eFlash-type, according to their memory form. The
ROM-type MCU offers low price; however, its program and data cannot be changed
after manufacture. The eFlash-type MCU supports million times of reprogramming
which is more flexible, but with higher cost. The OTP/MTP-type MCU ranks at
medium price, but only supports one time or multiple times of reprogramming;
however, it is suitable for products which require some flexibility and are cost-
sensitive.
MCU has a wide variety of applications. The 4-bit and 8-bit MCU are mainly
applied to radio, telephone, pager, liquid crystal display controller, calculator,
vehicle instrument and meter, toy, tire pressure monitor, thermometer, hygrometer,
electronic scale, remote controller, electricity meter, facsimile printer, motor con-
troller, household appliance, and industrial control product. The 16-bit and 32-bit
MCU are mainly applied to mobile phone, digital camera, digital video, modem,
GPS terminal, PDA (personal digital assistant), set-top box (STB), router, laser
printer, IoT terminal product, and so on. The 64-bit MCU are mainly applied to
multimedia interaction and workstation systems. With the increasing performance of
8-bit MCU and the decreasing price of 32-bit MCU, the boundary of 8-bit and 32-bit
product is not that clear and their application market is intersected.

Digital Signal Processor

Digital signal processor (DSP) is a kind of special microprocessor, which optimizes

signal processing in architecture. The first single-chip DSP was the MAC4 micro-
processor developed at Bell Labs in 1979. The first complete DSPs appeared at the
IEEE ISSCC (International Solid-State Circuits Conference) in 1980. They were
NEC’s uPD7720 processor and AT&T DSP1 (started in 1977) processor. The chip
13 Products of Digital Integrated Circuit 219

Fig. 13.11 Schematics of DSP system

that finally opened up the DSP market was the TMS32010 produced by TI in 1983
[64, 65].
DSP can measure, filter, and compress continuously changing analog signals in
the real world. A typical digital signal processing system is shown in Fig. 13.11. The
principle of digital signal processing system is to convert the signal (e.g., the sensor
signal from audio video) from analog signal to digital signal and carry out effective
digital signal operation.
The operation of DSP module in a design usually needs to be completed by
combined microprocessor chip. Most microprocessors can complete the operation of
digital signal processing algorithm, but they cannot be applied to mobile devices and
Internet of thing (IoT) devices that require low power consumption. In order to meet
the requirements of low power consumption and ensure good performance and fast
processing speed, special digital signal processing chips, voice signal processing
chips, image processing chips, and visual signal processing chips have been devel-
oped for mobile devices [66].
The clock frequency of TI’s C6000 series is 1.2 GHz, and the fastest execution
speed is 8000 MIPS. Freescale (merged by NXP in 2015) multicore DSP, each core
clock frequency is 1 GHz. XMOS’s multi-threaded DSP execution rate is
400–1600MIPS [67]. CEVA has 16-bit or 32-bit DSPs, single or two MAC DSPs,
which can be structured in either super-long instruction or single-instruction data
flow. Based on the super Harvard architecture, ADI designs floating-point and fixed-
point DSPs with a mega floating-point operation range of 198–2400 MFLOPS
(corresponding frequency of 66–400 MHz). Cadence Tensilica Vision P6 is an
image processing chip for computer vision applications that simultaneously supports
OpenVX, the vector single-precision floating-point accelerator [68].

RISC-V ISA and RISC-V Processors

RISC-V (pronounced “risk-five”) is a free, open-source, extensible instruction set

architecture (ISA) that is based on established RISC principles. RISC-V processors
are processors implemented on the basis of RISC-V ISA. RISC-V ISA was invented
at University of California, Berkeley, by Professor Krste Asanovic, his Ph.D.
students Yunsup Lee and Andrew Waterman, and advised by David Patterson,
with many more contributors from industry and academia [69]. It emerged at the
backdrop of the slowdown of Moore’s Law and Dennard Scaling, when the industry
embracing domain-specific architecture (DSA), and customers’ demand for agile
and cost-effective custom silicon designs.
220 D. Hu et al.

Chip builders choosing RISC-V have the advantage of knowing there are many
competing suppliers for RISC-V IP. They can select among multiple commercial
RISC-V IP vendors or use an open-source core, or even roll their own. This is even
more important for a second-generation chip product, where selecting a proprietary
ISA would have led to vendor lock-in or worries about vendor long-term viability.
Chip customers will also be assured of many sources of supply for RISC-V parts
spanning a wide range of applications.
To help prevent ISA fragmentation while supporting customization, RISC-V has
been designed to be modular and extensible. RISC-V ISA has a small simple fixed
base ISA and modular fixed standard extensions that work well for the large majority
of code, while leaving ample space for application-specific extensions that do not
interfere with the standard ISA core [70]. The current RISC-V ISA base and
extensions are presented in Table 13.14.
RISC-V ISA has been designed to have features to increase computer speed yet
reduce cost and power use. These include a load–store architecture, bit patterns to
simplify the multiplexers in a CPU, simplified standard-based floating point, a
design that is architecturally neutral, and placing most significant bits at a fixed
location to speed sign extension. Sign extension is said to often be on the critical
timing path.
The instruction set is designed for a wide range of uses. It supports three word
widths, 32, 64, and 128 bits, and a variety of subsets. The definitions of each subset

Table 13.14 RISC-V ISA bases and extensions

Name Description Version Status
Base
RV32I Base integer instruction set, 32 bit 2.0 Frozen
RV32E Base integer instruction set (embedded), 32 bit, 16 registers 1.9 Open
RV64I Base integer instruction set, 64 bit 2.0 Frozen
RV128I Base integer instruction set, 128 bit 1.7 Open
Extension
M Standard extension for integer multiplication and division 2.0 Frozen
A Standard extension for atomic instructions 2.0 Frozen
F Standard extension for single-precision floating point 2.0 Frozen
D Standard extension for double-precision floating point 2.0 Frozen
G Shorthand for the base and above extensions N/A N/A
Q Standard extension for quad-precision floating point 2.0 Frozen
L Standard extension for decimal floating point 0.0 Open
C Standard extension for compressed instructions 2.0 Frozen
B Standard extension for bit manipulation 0.90 Open
J Standard extension for dynamically translated languages 0.0 Open
T Standard extension for transactional memory 0.0 Open
P Standard extension for packed-SIMD instructions 0.1 Open
V Standard extension for vector operations 0.2 Open
N Standard extension for user-level interrupts 1.1 Open
13 Products of Digital Integrated Circuit 221

vary slightly for the three word widths. The subsets support small embedded
systems, personal computers, supercomputers with vector processors, and
warehouse-scale rack-mounted parallel computers.
The instruction set is variable width and extensible so that more encoding bits can
always be added. Space for the 128-bit stretched version of the ISA was reserved
because 60 years of industry experience has shown that the most unrecoverable error
in instruction set design is a lack of memory address space [71].
Due to its open nature and extensible modern design, RISC-V has quickly gained
traction across the industry. RISC-V Foundation, initiated by the RISC-V inventors
in 2015 and now part of the Linux Foundation, has grown to more than 200 members
by June 2019. There is also a thriving group of companies who either license their
commercial RISC-V processors cores or open source their core designs, including
SiFive, Western Digital, NVIDIA, Andes, Codasip, and many others. By July 2019
when this was written, there are 65 various cores and SoCs that endeavor to
implement the RISC-V specification [72].

Field Programmable Gate Array

Field programmable gate array (FPGA), also known as field programmable device,
is a semi-customized integrated circuit, developed on the basis of programmable
devices, such as programmable read-only memory (PROM), programmable logic
device (PLD), programmable logic array (PLA), gate array logic (GAL), and
complex programmable logic device (CPLD). Therefore, FPGA has the character-
istics of hardware programmability.
In 1985, Xilinx introduced CX2064, the world’s first FPGA, which uses 2 μm
manufacturing process and contains 64 logic blocks (1200 logic gates) [73]. In 2003,
Xilinx launched a series of Spartan-3 products with 90 nm manufacturing process,
followed by a series of Virtex-5 products with 65 nm manufacturing process and a
series of Virtex-6 products with 45 nm manufacturing process. In 2011, Xilinx and
Altera (acquired by Intel in 2015) launched a series of FPGA on 28 nm manufactur-
ing process, which have high efficiency for logic integration and lower power
consumption. In 2016, Xilinx and Altera launched the FPGA on 16 nm manufactur-
ing process.
The main components of the FPGA are programmable input/output units (I/O
blocks), configurable logic block (CLB), embedded RAM, programmable wiring,
underlying embedded functional units, and embedded dedicated hardcore. CLB is
the basic logic unit of FPGA. It consists of trigger and look-up table (LUT).
FPGA contains millions of logic units. It is very complex to configure them to
achieve specific logic functions. Therefore, it is necessary to compile corresponding
configuration files or binary code streams using special EDA development tools. The
main EDA development tools of the mainstream FPGA manufacturers are Quartus
from Altera, ISE and Vivado from Xilinx [74], ispLEVER from Lattice, pASSP from
Atmel (acquired by Microchip in 2016), and Libero from Actel (acquired by
Microsemi in 2010).
222 D. Hu et al.

The development of the design method of FPGA can be divided into three eras,
namely the era of hardware description, the era of embedded soft core, and the era of
heterogeneous systems.
The era of hardware description is the first era of FPGA design. The designers use
the hardware description language (HDL) to complete the research and development
based on the circuit functions to be designed. Since the modular digital circuit can be
packaged into an intellectual property (IP) core, the final design of the FPGA can be
accomplished by using an IP core, which can greatly increase efficiency.
The era of embedded soft core is the second era of FPGA design, which is
represented by Altera’s microprocessor soft core named Nios II and Xilinx’s micro-
processor soft core named microblaze. Designers use the logic resources inside the
FPGA to build the microprocessor soft cores and then connect the IP soft cores such
as I/O interface to the microprocessor soft core bus to form a programmable system
on chip (PSoC). Designers can use C, C++, and other high-level languages to control
the operation of the PSoC to co-design software and hardware.
Driven by factors such as power consumption, performance, and development
cycle, FPGA design has entered the era of heterogeneous systems. The CPU-centric
architecture such as Harvard architecture (or Feng’s structure) and programmable
logic circuits exist in the FPGA at the same time, making heterogeneous systems
more comprehensive. For example, both Altera Cyclone V-series and Xilinx Zynq-
series include ARM hardcores. At the same time, with the introduction of high-level
synthesis (HLS), the EDA tools of FPGA have been further developed, and hardware
programming of FPGA can be directly used in languages such as C and C++, which
greatly improves the design efficiency of FPGA.
After 2010, neural network technology has been widely used in the field of
artificial intelligence. FPGA has attracted much attention due to its high parallelism,
high throughput, low power consumption, and reconfigurability. It has become
important devices for improving performance-to-power ratio in systems that imple-
ment deep learning algorithms.

Application-Specific Integrated Circuit and System on Chip

ASIC products are customized digital integrated circuit (IC) for special purposes.
Compared with digital IC products in the form of CPU, DSP, and FPGA, ASIC
products have the advantage of being able to design for needed applications and
implementing specific functions [75]. Microprocessors, memories, and other IPs are
often included in modern ASIC products. A classical type of IP, named customer-
owned tooling (COT) module, less common to others, is commonly used in ASIC
products.
System-on-chip (SoC) design in general has embedded CPU, memories, includ-
ing ROM and RAM, and various IPs (e.g., PLL, LVDS, ADC, and LDO), input/
output (I/O), and external memories (e.g., flash) integrated to process system-related
functional tasks. The application processor (AP) is an upstart in mobile devices,
where it undertakes primary functions (OS, audio, imaging, security, camera). AP
13 Products of Digital Integrated Circuit 223

belongs to SoC design category. In practice, the terms of ASIC and SoC are often
mixed up names in use.
The mainstream design flow of ASIC [76, 77] is based on the system design and
specification. RTL code for ASIC design can be written with Verilog HDL (hardware
description language) or VHDL language, followed by functional simulation and
test. The gate-level netlist (GLN) that generated by EDA synthesis tool from RTL is
passed by logic verification and/or conformal checking, and then, design for test
(DFT) circuit is added. GLN is delivered to physical design team for place and route
(P&R) and meeting the signoff demands such as clock tree synthesis (CTS), static
timing analysis (STA), and power dissipation analysis. Physical verification and
DFT also must be passed before the signoff and tape-out to chip foundry for
production. A typical ASIC design flow is shown as Fig. 13.12.
There are two mainstream design methods of ASIC, full custom and semi-
custom, respectively. In a full custom design, the implementation is to follow a
standard design flow, while in a semi-custom design, one of the goals is to optimize
various design-related resources, such as reuse and integration of mature IPs to
achieve specific functions. The vendors offer a variety of solutions including but not
limited to memories, standard cells, and complicated IPs.
ASIC saves more development time and less R&D costs with existing platform in
comparison with the COT mode that the entire back-end process would be com-
pleted by designers. In addition, structured ASIC can improve design performance,
decrease the cost of non-recurrence expense (NRE), and reveals characteristics of
both ASIC and FPGA at the same time, for example, the product model of eASIC
company.

Fig. 13.12 Typical flow chart of ASIC designs [76]

224 D. Hu et al.

Fig. 13.13 Advanced technological nodes used for ASIC designs by global semiconductor
manufacturers

As the semiconductor process becomes more advanced, reduction of transistor

gate width, on the same area of the chip, ASIC product can integrate more transistors
(e.g., in 2017 in an IBM design, 30
109 transistors are integrated [78] on a 5 nm
chip) and achieve lower cost and higher performance. Figure 13.13 shows as the
advanced technology node and relative process that ASIC products used by global
semiconductor manufacturers of 2012–2018.
The development of ASIC products cannot be separated from the software
development of electronic design automation (EDA), which includes system design
and verification tools, such as incisive, VCS; logic synthesis for GLN and physical
design tools, like Innovus, Calibre; circuit design and simulation tools, for instance,
Hspice, Spectre; and PCB design tools, like Sigrity and Xpedition. Currently,
Cadence, Mentor Graphics (acquired by Siemens in 2017), and Synopsys can able
to offer various tool methods to composite complete ASIC design flows.
ASIC and SoC products are widely used in smartphones, computers, communi-
cation devices, automotive electronics etc. The common ASIC products can be seen
in the series of Snapdragon 800/600/400/200 chips from Qualcomm, the series of
Kirin of HiSilicon, and the series APU (CPU combined with GPU) based on Opteron
processor from AMD, as well as GeForce graphics card GPU series of NVIDIA.
ASIC or SoC design is typically for a single customer; when ASIC product aims
to a number of customers, it is called application specific standard product (ASSP);
thus, ASSP seems more a generic special case of ASIC. ASSP can be used as ready-
made products, such as independent USB interface chips, while ASIC is usually
used in specific systems requiring specific functions.

Network Processor Unit

Network processor unit (NPU) is used to process variety of network communication

tasks, including processing of data packets, protocol analysis, routing search, voice
and data collection, establishing internet firewall, and ensuring quality of service
(QoS) of networks [79]. NPU is widely used in routers of Internet connections,
13 Products of Digital Integrated Circuit 225

Internet switches, and Internet monitor and protector equipment. As these electronic
units are located at the Internet exchange point (IXP) to process data communication,
the NPU is sometime called IXP network processor.
There are some special requirements in network data processing, such as conges-
tion management, queue scheduling, data stream classification, and QoS function, to
meet extreme high searching and transferring tasks. The general-purpose CPU (e.g.,
x86), limited by the speed of PCI bus, is not most suitable for network communi-
cation processing. Combining software algorithm and hardware design, specially
designed NPU can resolve the above listed problems. NPU can follow the develop-
ment of the firewall, with its programmable flexibility, to simplify the application
needs. The advantages of NPU are as follows, increased processing ability by using
of multicore parallel processors; increased system performance using special hard-
ware coprocessor; optimized reduced instruction set architecture (ISA) for pro-
cessing network protocols; memory hierarchy to apt various applications; enriched
I/O interface providing strong processing capability on its parallel hardware; and
scalable massive and high-performance network processing tasks by using clusters
formed of multiple NPUs.
The widely used NPU products include IXP Series from Intel, who authorized
IXP2800 to Netronome in 2011. Based on x86, Netronome has lately designed Agilio
LX SmartNIC products that have data rate of 2
40 GbE or 100 GbE (Gbps or Gbit/s
Ethernet). The router and switch products, EX9200 series, from Juniper Networks, a
software-defined networking (SDN) company, can provide 480 Gbps per slot, up to
3.2/9.6/13.2 Tbps backplane bandwidth capacities. Broadcom announced in early
2019 that their Tomahawk® 3 is for routing and switching at a 12.8 Tbps performance
on a single 7-nm process chip [80]. Marvell’s Prestera Series using ARMv7 CPU
supports 40 GbE and total of 1.2 Tbps. Acquired Alcatel-Lucent in 2015, Nokia
provides 10/40/100 GbE speed with 7450 Series, and the total speed of their switch
product is 2–4 Tbps [81]. Neux 9500 Series Switch Chassis from Cisco can support up
to 172.8 Tbps bandwidth, it can be configured to 32-port 100 GbE, and the number of
port channel is up to 512. CE12800 Series Switch Chassis from Huawei has a
backplane bandwidth of 178 Tbps [82]. Acquired EZchip in 2016, Indigo NPS from
Mellanox supports Open System Interconnect (OSI) protocol, using ARMv8 and
100 A53 cores on 28 nm, and the data rate is 240 Gbps [83].
Compared with general processors (CPU and MPU), NPU chips (switch and
control) require high performance and high data rate and require software technique,
such as in software-defined networks (SDN). In today’s application of NPU in cloud
computing services, such as in data center, one needs to not only consider the
throughput of data, but also the security of data, which adds additional period of
R&D effort and increased the complexity of architecture design.

Secure Cryptoprocessor and Cryptographic Processor

Secure cryptoprocessor is a processor that can generate secure key; it does not
generate secured data or programming instructions [84]. The applications of
cryptoprocessor include the widely used smart cards, automated teller machines
226 D. Hu et al.

(ATM), TV set-top boxes (STBs), and military application systems. According to the
design technology and methodology, there are two categories of cryptoprocessor
1) based on non-volatile memory (NVM) cryptography technology; 2) based on
physical/physically unclonable function (PUF) cryptography technology [85].
Under secure circumstances, for a cryptographic processor, it combines
cryptoprocessor (or cryptoprocessor) and an encryption scheme together, and the
electronic data encryption, storage, and read-out via bus are then realized. The most
common encryption technique used in cryptographic processor is the data encryption
standard (DES) algorithm.
Cryptographic processor using NVM cryptography is a mature technology and
widely adopted. In this IC type design, the key and code are executed in the
embedded CPU. Through the logic protection circuit, the internal encryption algo-
rithm and programmable operation can protect the data to be encrypted by using the
password or by other meanings. The certification process can be done via the trusted
platform module (TPM), executed under the trusted execution environment (TEE),
so the uploaded password and data maintain their privacy and integrity. NVM-based
cryptographic processors can be installed in a Hardware security module (HSM),
which is usually made of a single plug-in card or an external device. HSM can
contain one or more cryptographic processors and is connected to a PC or a server
when in use, so to prevent malicious tampering and peeping on the buses.
PUF design technique was first reported in 2002 by Gassend et al. [86], and it has
received increased attention in 2010–2013, to be expected as silicon fingerprint used
in smart card. The special features of PUF, with the key and certification combined,
are that the system protocol becomes non-reproducible, new encryption protocol
fused with its original system architecture.
There are two types of cryptographic processors on the market: The first type is
made of the traditional logic chip using I2C (or I2C) interface protocol, with internal
hardware protection circuit and external EEPROM to establish a protection with an
encryption algorithm. The second type is an internal encryption chip in a smart card
using I2C (I2C) or GPIO interface on either internal clock or external crystal. These
encryption chips are programmed with a MCU that is partial algorithm, code and
data are executed in the MCU. In addition, these chips must meet EAL5 security
standard.
In practice, the user needs to select a cryptographic processor first and then
select a secure, rational, and effective encryption technique, such that the data can
be protected. Secure cryptoprocessor and IC design can result in new innovative
techniques. For example, back to 1989, Charles Bennett et al. of IBM have
proposed to combine cryptology with quantum mechanics to become quantum
cryptology for quantum key distribution (QKD), compared with human security
network (HSN), and QKD offers advantages of automation, high reliability, and
low cost [87].
Examples of cryptoprocessor are smartcards, TPM (with RSA encryption) chip,
and hardware security module (contains one or more cryptoprocessor) chip. Intel
claims that the Xeon chip has improved performance of Advanced Encryption
Standard (AES) cryptofeature that is suitable for datacenter security.
13 Products of Digital Integrated Circuit 227

Advanced Processors

In addition to various existing processors, such as CPU, MPU/MCU, and DSP,

several new types of processors have been developed over the past decade(s). For
example, parallel computing type graphic processing unit (GPU) is on the popular
list. A fusion of CPU and GPU, the accelerated processing unit (APU) [88], is
another example. In artificial intelligence (AI) development, for a cognitive com-
puter, many processors on a single neuromorphic CMOS chip, TrueNorth, were
developed at IBM in 2014 [89]. Similarly, based on an application-specific inte-
grated circuit (ASIC) design, Google has developed a tensor processing unit (TPU)
in 2016 [90].

1) APU and HSA. AMD acquired a GPU technology-based Canadian company

ATI in 2006. This has led from traditional CPU of serial computing to GPU of
parallel computing, which is further fused to a single-chip APU. Table 13.15 lists
APU products at AMD [88]. This has led to the heterogeneous system architec-
ture (HSA) that integrates CPU and GPU on the same bus, with shared memory
and computation tasks.
In a HSA application [61], the core HW components are the CPU and GPU, in
some cases to add DSP for specified tasks. Meanwhile, the SWs are developed in
correspondence to the HSA needs. These include system-level languages C/C++,
Python supporting multiple operating systems (OS), the Open Computing Lan-
guage, OpenCL) for sharing computing in HSA, for the Open Graphics Library
(OpenGL), the Open Multi-Processing (OpenMP) Application Program Interface
(API), and the Compute Unified Device Architecture (CUDA) developed by
NVIDIA. OpenCL has become a new industry standard for task-parallel and
data-parallel processing in HSA designs. HSA Foundation was formed in June
2012, and the founding members were AMD, ARM, Imagination, MediaTek
Qualcomm, and Samsung. Focused on the development and definition of various
processors in the same system, the HSA Foundation emphasizes the specifica-
tions and interfaces of CPU, GPU, and DSP, together with graphic memory
GDDR, the system virtual memory (SVM) was defined (Fig. 13.14).

Table 13.15 APU generations and applications developed at AMD

Year APU (former name Fusion) Project Process Features and Applications
Jan. 2011, APU Llano, K10 arch., 2–4 CPU cores GF 32 nm HKMG SOI, 65–100 W, the
Gen. 1 integrated with GPU Radeon HD 6000 first APU multicore design. Used in
Series; renamed HSA in 2012 desktops and laptops
Oct. 2012, APU Trinity, Piledriver arch., 2–4 CPU GF 32 nm HKMG SOI, CPU
Gen. 2 cores and GPU Radeon HD 7000/8000 1.4–4.2 GHz, better CPU than Llano,
Series used in desktops and laptops, Sony PS4
Jan. 2014 APU Kaveri, Steamroller arch., GF 28 nm HKMG bulk, 3.9–4.1 GHz,
integration of CPU with 195–512 core 15–95 W, for Sony PS4 and MS Xbox
GPU One. Better performance than similar
Intel products
228 D. Hu et al.

Fig. 13.14 Schematics of SW and HW in a HSA

Some latest CPUs can be combined with GPU in HSA designs. For example,
in 2016, AtomTM x5-Z8350 processor using 14 nm process from Intel has
4-core 4-thread, 2 MB L2 cache to work at maximum 1.92 GHz. Intel also
announced 72-core Xeon Phi serial processor 7290, manufactured in 14 nm
process, integrates 16 GB memory to work at 1.5 GHz. In 2018, Intel
announced its 8th/9th-generation 4(8)-core processor Core-i7 serials, which
can work at 4.5–4.7 GHz.
2) Neuromorphic Chip and TrueNorth. John McCarthy first used the phrase
artificial intelligence (AI) in 1956, so as called the father of AI. Through machine
learning (ML) algorithms of AI, the development and design of IC products are
rapidly growing. Geffrey Hinton et al. published a paper of back-propagation
algorithm in 1986; the work made a new progress in 2006 that is today know as
deep learning (DL). Based on DL of ML, the convolutional neural network
(CNN), or the deep neural network (DNN), and the long short-term memory
(LSTM, a type of recurrent neural network, RNN) methods have promoted
various designs of AI chips. IBM undertook the research project SyNAPSE
from DARPA for the cognitive computer design. IBM announced in 2014 for a
neuromorphic network, the TrueNorth many-core chip design [89] that contained
4096 CPUs. The CMOS chip has a total of 5.4
1012 transistors, and power
consumption is only 70 mW. TrueNorth can simulate 2.68
1012 synapses in a
human cerebrum; each CPU core can simulate 256 programmable neurons,
which is equivalent to a total of 1
106 neurons. TrueNorth can be used in
ML for AL training purpose.
3) AI Training and Cambricon Chips. In AI training, CPU is slower than GPU;
while original GPU was not designed for such purpose, the advantage of perfor-
mance is drawn back by its high-power consumption. Cambricon [91] announced
in 2014 DianNao chip (Cambricon-1) and DaDianNao chip (Cambricon-2) to
first demonstrate high performance and low power versus GPU in the market.
Released in 2016, PuDianNao chip (Cambricon-3) could process seven differ-
ence AI algorithms including k-means, support vector machine (SVM), and deep
13 Products of Digital Integrated Circuit 229

neural network (DNN). ShiDianNao chip (Cambricon-4) in 2018 further

improved data read/write (R/W) delay. In ML algorithm such as sparsely neural
network (SNN), reduce the number of weighting factors of SNN for high
performance, and the latest AI-chip Cambricon-1H8 aims for visual application;
the third-generation Cambricon-1 M on 7 nm process aims on DL for video and
ADAS data processing, which shows an energy efficiency of 5 TOPS/W, has
been integrated in a smartphone Kirin 980 of Huawei.
4) TPU and TensorFlow. Google has started their tensor processing unit (TPU)
chip design in 2013, through PCIe interface to optimize the CPU and GPU
groups. The TPU was specially designed for a DL platform TensorFlow, which
can transport complex datasets to AI neural network for analysis and processing.
Acquired DeepMind of England in 2014, Google developed AlphaGo to defeat
Lee Sedol in May 2016 and later AlphaGo 2.0 to defeat the 19-year-old Chinese
prodigy Ke Jie in June 2017. Both systems are operated on TPU. In real-time
completion of GO in TPU, maximum of 1920 CPU and 280 GPU were in use.
Google released TPU architecture on April 5, 2017, through their official blog.
The TPU has a 15–30 times AI process speed of other combined GPU and CPU
mode, and the energy efficiency of computation is 50–80 times.

Though other processors, such as application processor (AP) and baseband

processor (BB) in mobile device, are called or listed under ASIC or SoC designs,
these technical progress and advancement have brought in new stimuli for advanced
designs for future processor market.

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Analog and Mixed-Signal IC Products
14
Yuheng Guan, Fan Lai, Yuhua Chen, Yi Sun, and Gangyi Hu

Contents
Analog IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Digital-to-Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Specialty Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Power Management IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
AC/DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Switching Power Supply Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Low Dropout Regulator (LDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Light-Emitting Diode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Liquid Crystal Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Motor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Serializer/Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Serial Communication and Universal Serial Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Ethernet Interface IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Interface for Standard-Definition Television and High-Definition Television . . . . . . . . . . . . . . . . . 256
High-Definition Multimedia Interface IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Advanced Technology Attachment Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
DDR SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Y. Guan
Huada Empyrean Software Co. Ltd, Beijing, China
F. Lai · G. Hu
China Electronics Technology Group Corporation 24th Institute, Chongqing, China
Y. Chen (*)
Peking University, Beijing, China
e-mail: chengyh@pku.edu.cn
Y. Sun
University of Chinese Academy of Sciences, Beijing, China

© Publishing House of Electronics Industry 2024 233

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_14
234 Y. Guan et al.

Protocol Converter IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Controller Area Network Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Inter-Integrated Circuit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
High-Frequency Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Digital Video Broadcasting Modulation/Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Mobile Communication IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Audio Codec IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Video Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Power Line Communication (PLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Digital Subscriber Line (DSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Passive Optical Network and Cable Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Abstract
Among all semiconductor and IC products in the global market, analog and
mixed-signal and RF ICs contribute to about 15% of the total. Different from
digital products, AMS and RF products can be used in stand-alone, or they can be
embedded in SoC/ASIC designs. Analog and AMS ICs have experienced from
operational amplifiers (Op-Amp), comparators, voltage regulators, to the more
complicated ones (e.g., PLL) The types of analog and mixed-signal (AMS)
products are versatile and include very commonly used ADC, DAC, Op-Amp,
LDO and various drivers, SerDes, Ethernet, USB interfaces, and audio/video
codecs. This chapter introduces commonly used commercial analog and AMS IC
products, their basic functions, features, applications, and some typical product
names.

Keywords
AMS · ADC · DAC · LDO · Drivers

Analog IC

Analog IC is applied to process analog signals; analog and mixed-signal (AMS) ICs
are used to process analog signals and digital signals on one silicon chip. Hereinafter,
analog IC and AMS IC are collectively referred to as analog IC(s). Analog IC is
integrated into electronic system to generate, convert, and process signals and
provide power supply, specifically, works to sample, amplify, transmit, and drive
analog signals and manage power supply. Application diagram of analog signal
processing is shown in Fig. 14.1. The working process diagram among analog IC
technology, design, and application is shown in Fig. 14.2.
According to the relation of input to output, analog IC features both linear circuit
such as operational amplifier and nonlinear circuit such as analog multiplier. By
function, it includes amplifier, comparator, power supply, power management,
analog switch, data converter, and RF IC. By application, it has general-purpose
IC and application-specific IC, specifically, operational amplifier, voltage regulator,
14 Analog and Mixed-Signal IC Products 235

Fig. 14.1 Analog IC applications in a signal processing chain

Fig. 14.2 Relations between analog processing, design, and applications

phase-locked loop (PLL), active filter, analog-to-digital converter (ADC), and

digital-to-analog converter (DAC) for the former; audio circuit and television
receiver for the later.
The world first IC was an analog IC that made by Jack S. Kilby in 1958, which
was an oscillator on germanium (Ge) substrate featuring five components. At that
time, analog IC was usually fabricated in bipolar process featuring one single
function. Later, Fairchild semiconductor launched μA709 operational amplifier in
1965. In 1968, David Fullagar [1] developed μA741 operational amplifier, which
had widest applications. Then, OP serial operational amplifier, 12-bit ADC AD565,
236 Y. Guan et al.

8-bit DAC DAC08 by ADI [2], and MC78/79 series voltage regulator by Motorola
were popular in the market for more than 30 years.
As market grows and technology develops, analog IC process has made a great
progress in bipolar, CMOS, BiCMOS, BCD, etc., as well as in substrate technology
of Si, SiGe, and SOI. At present, we have analog IC products featuring high-speed
converter in GHz range, 24-bit ADC, switch regulator in MHz switch frequency
range and 95% efficiency, sub-μV offset amplifier, and voltage reference of sub-1

106/ C. We can find various kinds of analog IC products on market, with new
products being constantly launched.
The mutual push between customer demand and technology development is the
essential driver for analog IC industry. Single-functional analog ICs are designed for
higher resolution, ultra-wideband, ultra-high speed, lower noise, higher linearity, and
higher power density. As technology develops, digital and analog circuits are
integrated on a single chip for special and novel applications, with the help of
auxiliary and calculation, in ways that enhance AMS IC development. The typical
products include ADC, DAC, direct digital frequency synthesizer (DDS), frequency-
to-voltage converter, phase-locked loop (PLL), and analog front-end (AFE) circuit.
In 2017, Xilinx released a programmable RF SoC in 16 nm CMOS process, featuring
FPGA, 12-bit 4GSPS (SPS: sample per second) RF-ADC, and 14-bit 6.6GHz
RF-DAC on a single chip. In 2019, RF SoC was released featuring input/output
frequency up to 6 GHz at the full sub-6GHz band and ADC sample rate ranging from
4 GSPS to 5 GSPS and resolution from 12 bit to 14 bit. It works to realize 2GHz
bandwidth RF signal directly sampling and transmit-mode software-defined radio
(SDR). Heterogeneous integration of analog IC and AMS and MEMS is the main-
stream for the development of intellectual sensor industry.

Analog-to-Digital Converter (ADC)

Analog-to-digital Converter (ADC, A/D, or A-to-D) is a kind of IC that converts

analog signals to digital signals. With reference to conversion ways, analog-to-
digital converter is categorized as flash ADC, multistep ADC, successive approxi-
mation register analog-to-digital converter (SAR ADC), pipelined ADC, sigma-delta
ADC (  Δ ADC), hybrid ADC, and time-interleaved ADC.
Flash ADC works well for ADC with resolution from 1 bit to 8 bit. SAR ADC is
fit for ADC with resolution from 5 bit to 10 bit, and pipelined ADC for 8 bit to 16 bit.
-Δ ADC is perfect for 16-bit to 32-bit ADC. Hybrid ADC is a good choice when
the trade-off between power and speed matters. Time-interleaved ADC consists of
many single-channel ADC for high-speed applications where sample frequency is
multiplied by using time-interleaved sampling and parallel conversion.
Resolution (bit), sample rate (samples per second, SPS), and power are key
performance parameters for ADC. As desired resolution increases, the sample rate
needs to increase, and power increases as well. In that way, 4-bit to 6-bit ADC is
expected featuring GSPS (106 kSPS) sample rate, but 32-bit ADC has sample rate of
38kSPS at the top due to high power.
14 Analog and Mixed-Signal IC Products 237

Look back the development of ADC, ADC employed successive approximation

structure in bipolar and CMOS process with larger critical dimension. It featured
6-bit to 12-bit and sample rate of kSPS. In 1978, by using thin-film resistors, Paul
Brokaw of ADI launched the first monolithic ADC AD571 in bipolar process. It
featured 10-bit resolution, 25kSPS sample rate, and 180 mW power. With technol-
ogy in sub-micron and deep sub-micron, ADC features hundreds of MSPS sample
rates by using pipelined structure. In 2001, ADI launched AD9235 in 0.35 μm
CMOS process featuring resolution of 12-bit, sample rate of 65MSPS, and power
of 300 mW. In 2009, linear technology introduced a series product of LTC2204,
LTC2207, LTC2208, and LTC2209 in 0.35 μm CMOS, which had sample rate of
160MSPS, 16-bit resolution, and 1.45 W power.
The technology developed fast around 2012 emerging a great number of high-
performance ADC. These products, in CMOS process, feature sample rate being
multiplied while unit power being multiple decreased. For example, ADI AD9625 is
a 12-bit 2.5GSPS ADC and AD9680 a 14-bit 1.25GSPS ADC. Texas Instrument
(TI) provided ADC54J60 featuring 16-bit 1GSPS. Being fabricated in 65 nm CMOS
process, all products feature more than five times of speed than ever with power not
being increased. In 2016, it was reported that Broadcom’s ADC intellectual property
(IP) features much less power than that of monolithic ADC [3]. ADI has published
12-bit 10GSPS ADC in 2017 International Solid-State Circuits Conference (ISSCC)
that enter the age of medium resolution 10GSPS ADC for high-speed mobile
communication in next generation [4].
ADCs are designed for higher resolution, higher conversion rate, lower power,
single power supply, and lower voltage. In advanced CMOS power, ADC perfor-
mance is enhanced by using time-interleaved sampling and various digital auxiliary
calibration technologies. More and more low-power high sample rate ADC IP
emerges as IC technology develops. At present, ADC products tend to find wide
applications in industrial control, instrument, communication, auto-electronics, avi-
ation and space, medical electronics, and customer electronics.

Digital-to-Analog Converter (DAC)

Digital-to-analog Converter (DAC, D/A, or D-to-A) is an IC, which converts digital

signals to analog signals. DAC features conversion rate and resolution. With respect
to sample rate, it has Nyquist rate DAC and oversampling DAC. Nyquist rate DAC
can be categorized into resistor ladder DAC, resistor network DAC, capacitive
charge redistribution DAC, current-steering DAC, and hybrid or sectional DAC
[5]. In terms of applications, it has general-purpose and application-specific types.
Application-specific DAC has wide applications in wideband communication base/
medium frequency/radiofrequency signal generation, video/audio output, industrial
control drive, and other things.
In the 1970s, DACs were fabricated in bipolar, CMOS process, such as μDAC
AD550 in 1970, 10-bit/500 ns multiplier AD7520 in 1974, 8-bit/80 ns DAC08 in
238 Y. Guan et al.

1976, 10-bit/250 ns band-reference current output AD561, 12-bit/1 μs multiplier

AD565, 8-bit/150 ns band-DAC buffer, and μP interface AD7524.
ADI, TI, Maxim, and E2V are main competitors in the market of DAC products.
At present, typical DAC products are as follows: 16-bit 12GSPS AD9162/AD9164
by ADI in 65 nm CMOS process, dual-16-bit 12GSPS AD9172 by ADI in 28 nm
CMOS process, 14-bit 9GSPS DAC38RF8x Series by TI in 40 nm CMOS process,
and 12-bit 6GSPS EV12DS460 by E2V in 0.35 μm SiGe Bipolar process.
DACs have wide applications in industrial control, high-end measuring instru-
ment, communication, automotive electronics, medical electronics, and customer
electronics [6]. Besides its applications in baseband signal generator and medium-
frequency synthesizer, high-speed DACs start to find applications in wideband RF
direct synthesizing and output. Digital signal process function is integrated into
digital-to-analog converter, such as digital up-conversion, digital pre-distortion, and
equalization. Two to four channels products with SerDes high-speed interfaces in
series are presented working to integrate high-speed DAC and high-speed ADC as
an integrated transceiver front end. Also, an RF front-end transmitter was launched
by integrating high-speed DAC and RF up-converter. As process and design tech-
nology develops, DAC products feature high resolution, high dynamics, low power,
multiple channels, and multifunctions, building up a great foundation for electronic
system of “software definition” and “cognitive adaptation.”

Comparator

Comparator is used to compare input current or voltage to references to generate the

output digital as shown in Fig. 14.3. Usually, it is considered as a 1-bit analog-to-
digital converter, serving as basic cells for analog-to-digital converter of high
resolution.
At the very beginning, comparator was realized by integrating operational ampli-
fier (Op-Amp), featuring narrow input range, low speed, low compatibility between
output and referred digital level, no latch function, and other issues [7]. Typical early
products include BG307, LM111, and LM119, which possess delay time of μs in
bipolar process without latch function. In 1985, linear technology published LT1016
TTL comparator featuring delay of 10 ns. AD9696, AD8561, and Maxim’s
MAX903 from ADI also reached the same performance.

Fig. 14.3 Schematic diagram of a comparator

14 Analog and Mixed-Signal IC Products 239

Comparator performs well depending on output digital level, response delay time,
resolution, and power. Referring to output digital level, comparators are categorized
as TTL/CMOS comparator and ECL/CML comparator. There is high-speed com-
parator, high-resolution comparator, and low-power comparator in terms of speed,
resolution, and power, respectively. ECL/CML comparator features shorter response
delay than TTL/CMOS comparator does. The conventional TTL/CMOS comparator
has response delay of 4 ns, such as AD 8611/8612 by ADI. High-speed comparator
tends to use ECL/CML level output, such as AD96685/AD96687, featuring
response delay lower than 2.5 ns.
Comparator is one of fundamental parts for analog IC, with wide applications in
high-speed analog-to-digital conversion, high-speed sample and hold, crystal oscil-
lation, clock recovery, zero-crossing detection, phase detection, voltage monitoring,
etc. [8]. In future, comparators develop toward features of shorter response delay,
better sensitivity, and adaptability for high-speed digital applications.

Operational Amplifier

Operational amplifier (Op-Amp or OP) is a circuit being utilized to amplify weak

signals. Input signals can be usually DC coupling, AC coupling, single-end input,
and differential input signals. It outputs single-end or differential signals. Key
performances matter for Op-Amp, such as offset, noise, low-frequency gain, band-
width, power, output swing, common-mode rejection ratio, and other things.
Fairchild semiconductor was the first company who developed Si-integrated
operational amplifier in 1960 and launched μA709 [9] and μA741 in 1965 and
1968, respectively. ADI introduced OP07 in 1975, featuring offset voltage of
30 μV, temperature drift of 0.3 μV/ C, and time drift of 0.3 μV/month. Both
μA741and OP07 were and are typical products with wide applications at present.
At the 1970s, by using junction field-effective transistor (JFET) [10] and metal-
oxidation semiconductor field-effective transistor (MOSFET) at input stage,
Op-Amp features better input impedance and lower input current in ways that well
amplify and process weak signals.
Op-Amp has various categories by different applications, such as general-purpose
Op-Amps, high-speed Op-Amps (bandwidth greater than 50 MHz), high precision
products (offset voltage less than 1 mV), and low-voltage/low-power ones (with
power supply lower than 1 mA). General-purpose products work to amplify signals.
High-speed ones feature high slew rate and high wideband, finding wide applica-
tions in communication equipment, video system, and test instruments. AD8003 of
ADI is one of typical products, featuring bandwidth of 1.65GHz and slew rate of
4300 V/μs. Low-power Op-Amp has low operational voltage and low static current,
with applications in portable and wearable electronic products. As cellphone and
tablet market blooms, low-power Op-Amp develops fast. As for high accurate
Op-Amp, it is widely applied in instruments and meters, sensors, and medical
equipment for testing and measuring. The product ICL7650 features offset voltage
of only 0.7 μV and unit gain bandwidth of 2 MHz. So far, Op-Amp products
240 Y. Guan et al.

develop lower noise, wideband, and high slew rate, being fabricated in bipolar,
JFET, CMOS, and other processes.

Instrumentation Amplifier

Instrumentation amplifier (IA) is a kind of looped-gain amplifier, featuring high

input impedance
p (>109Ω), high common-mode rejection ratio (>70 dB), low noise
(10nV Hz), low linearity error (typical value 0.01% and lower than 0.0001% is
available), differential input with flexible gain setting, and single-end outputs [11].
As shown in Fig. 14.4, an instrumentation amplifier typically has two operational
amplifiers A1 and A2 working to buffer and amplify signals in a way that guarantees
high input impedance and decreases load effective of weak signals by instrumenta-
tion amplifier. Op-Amp A3 is used to amplify the difference between the two
buffered signals from the latter two Op-Amps and restrain the common-mode signals
at two input ends for better common-mode rejection ratio. When R1 equals R2 and R3
equals R4, gain G is calculated as shown in eq. G ¼ (1 þ 2R1/RG)RF/R3, so that
circuit gain can be adjusted by regulating RG.
ADI launched typical product AD627, AD620, AD8420, AD8229/8429, and TI
introduced INA188 p and INA333 [11]. Hereinto, AD8229/8429 featured ultralow
input noise of 1 nV/ Hz for measuring tiny signals.
It is simple and easy-to-operate instrumentation amplifier by setting gain resistor
RG to attain required gain. Figure 14.5 shows how instrumentation amplifier pro-
cesses bridge signal, wherein the number of peripheral devices is small and circuit
debugging is simple and effective. Instrumentation amplifier has wide applications
in amplification of weak signals for sensors and accurate voltage-to-current conver-
sion, such as signal sample equipment by using bridge signals (voltage, temperature,

Fig. 14.4 A typical structure

of IA
14 Analog and Mixed-Signal IC Products 241

Fig. 14.5 Signal application

of an IA processing bridge

and others), industrial process control equipment, electrocardiogram monitoring

instrument, and high-end audio.

Specialty Amplifier

Specialty amplifier is an IC for special applications, which provides amplified

signals. It consists of operational amplifier as core and peripheral devices as being
specific costumed. Specialty amplifier features a variable gain amplifier (VGA),
differential driving amplifier (DDA), linear isolation amplifier, and video amplifier
(VA). The typical products are shown in Table 14.1.
As for signal processing, VGA works to convert unfixed-input signals into fixed-
output signals resulting enhanced dynamic performance for system signal process
[12]. In terms of control mode, the VGA is categorized as analog and digital VGA,
being ideal for wireless communication, instrumentation, high-performance signal
sampling, ADC signal conditioning, etc.
Differential drive amplifier (DDA) is a wideband signal buffering and driving
amplifier at front end of ADC, enabling impedance isolation and driving. It is typed
as fully differential amplifier and single-end-to-differential amplifier. Differential
drive amplifier works to, respectively, set differential and common-mode output
voltage and flexibly configure common-mode voltage for ADC signal conditioning.
It has wide applications in medical imaging, industrial process controlling, and
portable equipment [13].
On condition of indirect electrical connection, linear isolation amplifier enables
signal amplification and transmission to improve the capability of system security
and anti-interference. It is ideal for safety and security application of medical
electronic equipment and industrial process control. So far, the advanced iCoupler
technology and enhanced capacitive isolation technology substitute for conventional
optocoupler and shunt regulation in ways that provide isolation solution for appli-
cations in linear feedback power supply and sensor signal transmission.
Video amplifier is specially designed for video signal processing, enabling
enhancement in video brightness, color, and simultaneous signals to guarantee
242 Y. Guan et al.

Table 14.1 Product list of typical specialty amplifier

Specialty
Amplifier Type Company Description
Variable gain AD8331 ADI There is an ultralow noise preamp; a VGA with
amplifier 48 dB of gain range, and a selectable gain post-
amp with adjustable output limiting in each
channel. The gain control interface provides linear
in dB over a wide dynamic range
PGA281 TI It is an instrumentation amplifier with three
amplifiers, enabling signal gain control with
digital codes
Differential AD8137 ADI It features low noise, low distortion, and ultralow
driving ADA4940 power. It is ideal for high-resolution ADC signal
amplifier conditioning, single-end to-differential
conversion, differential buffering, and signal
driving
Linear ADuM3190 ADI ADI uses magnetic isolation coupler and TI
isolation AMC1301 TI employs enhanced capacitive isolator to realize
amplifier the linear isolation amplifier. Both perform
excellent in isolation and common-mode transient
rejection. Linear isolation amplifier enables
improvements in stability and lifetime as
compared to opt coupler isolator
Video THS7319 TI The THS7319 incorporates functions of level
amplifier shifting, low-pass filtering, and fixed-gain
amplification. It is ideal for three-channel high
definition or RGB video signal transmission,
featuring low power and small-sized package

high-quality image signals through long-distance transmission. As video resolution

is improved, video amplifier tends to require higher bandwidth, lower distortion,
higher speed, and lower power to meet the requirement of high-resolution video
signal process.
Besides, specialty amplifier also includes transconductance/transresistance ampli-
fier, charge integral amplifier, limiting amplifier, logarithmic amplifier, current-sense
amplifier, linear variable differential transformer, sensor amplifier, and sample/hold
amplifier. Specialty amplifier has wide applications in portable equipment, testing
and measuring instrument, medical system, and special signal processing. It
develops for higher bandwidth, lower distortion, and lower power with various
novel amplifiers for special applications.

Power Management IC

Power management IC (PMIC) works to offer management solutions for voltage

conversion, sequential control, charge-and-discharge management, energy distribu-
tion, and detection. It provides a stable power supply for the load, enabling a highly
14 Analog and Mixed-Signal IC Products 243

efficient, low power, and smart power system. PMIC is categorized into linear power
supply, switch power supply, μ-module, digital power, and protection chip [14].
As portable smart technology grows, PMIC develops featuring multiple func-
tions, multichannels, low power, and highly integration. Power management unit
(PMU) is innovated and goes popular. For example, a PMU in cellphone is inte-
grated with multichannel DC/DC, low dropout regulator (LDO), communication
interface, and management units, in ways that realize higher power conversion
efficiency, lower power, less components, and smaller size.
Linear power regulator works in the linear region of amplifier, featuring small
ripple wave, small number of peripheral devices but low efficiency. Three-terminal
regulator and LDO of 78xx and 79xx product series are all linear power supply.
Switch power supply operates at switching status. According to negative feedback
principle, switch controller works to regulate the on-to-off switch ratio of power
devices, such as MOSFET, enabling a stable output voltage. Switch power has
isolation and non-isolation types. As for the former, optical isolators, transformers,
and capacitive couplers are usually employed as isolation components in DC/DC
converters. The non-isolation type usually uses peripheral components, such as
inductors. Switch powers are small-sized, light, and high efficient, with wide
applications in power technology.
The μ-module products went public about 10 years ago, wherein switch power
controllers, power transistors, inductors, and capacitors were packaged into one
module. It features large output current, high efficiency, and small size. In October
2007, Linear Technology launched the first μ-module product LTM46xx, taking the
lead in technology. Then, easy-to-use product LMZ13609 series were introduced by
TI in 2011, which had wide applications in power management system.
As for small power management system, it mainly uses monolithic chip to offer
over-voltage, over-temperature, and ESD protections, as well as power supply and
driving function, with applications in circuit power supply, battery-to-supply switch,
and USB management.
PMIC enables a high-efficient, low-power, smart power supply system and
develops fast with accelerated production (productivity) to meet the requirement of
wireless charging technology for mobile products.

AC/DC Converter

AC/DC converter is used to convert alternating current (AC) into direct current
(DC) [15]. Depending on how it rectifies, AC/DC converters are classified into half-
wave rectifying converters and full-wave rectifying converters and are available for
three-phase AC and single-phase AC.
AC/DC conversion module can be directly plugged and played on PCB, so it has
wide applications in switch device, interface, mobile communication, microwave
communication, optical communication, routers, and motor electronics, aviation,
and space applications.
244 Y. Guan et al.

Monolithic AC/DC converter is ideal for small power driving applications, by

integrating magnetic modules with AC/DC conversion controller on a single chip.
Power Integrations [16] launched the first three-terminal isolation PWM AC/DC
switch in 1994 and then in 2000 presented 290 W TOP250 single chip of AC/DC
converter, from TOPSwitch-GX family wherein high-voltage MOSFET, PWM
controller, ESD, and other control circuits were integrated on a CMOS chip.
ROHM developed an AC/DC converter enabling the control IC BD7682FJ-LB.
As IC analog design technology makes use of power devices in SiC process, the gate
driver of SiC-MOSFET can be integrated on the chip enabling miniaturization and
high conversion efficiency. The chip had wide applications in large power inverter
(high-voltage multiplies large current) and servo in industrial equipment. A novel
flyback topology goes popular and is used for power circuits. TI launched
5 W–100 W flyback AC/DC converter in 2014, featuring low-power stand-by status
of 5 W–10 W, minimum constant output current tolerance of 5%, and average
efficiency more than 88% [17].
In 1980s, AC/DC converters use switch power for low-power applications such
as computers. At the moment, AC/DC switch power IC remarkably grows in the
market of portable products and digital consumer electronics. The way to improve
the performance of AC/DC switch power is concluded as follows. Firstly, its switch
frequency is improved by using zero-voltage switching (ZVS) and zero-current
switching (ZCS) soft-switch technology for greater power density and smaller
size. Secondly, intelligent control components are used to decrease power consump-
tion through second rectification. Thirdly, material (Mn-Zn) performance is
improved and new materials are used for better performance. Besides, both minia-
turized passive module and surface mount technology (SMT) play a part in the
improvement of switch power.
In the future, microgrid will develop with the help of distributed AC/DC power
IC. Mirogrid AC/DC technology tends to provide a solution for an ideal trade-off
between power quality and power flow, well-performed voltage and frequency
control and power management. It also solves the problems concerning stability,
reliability, and over-voltage/current protection, dynamic modeling, and operation
with low cost.

DC-DC Converter

DC-DC converter works to realize voltage conversion for a stable voltage. It belongs
to a branch circuit of switch power supply. DC-DC converter [18] has wide appli-
cations in telecommunication, portable digital devices, computers, office automation
system, and industrial equipment, military use, spacecraft, and motor transportation.
In 1980, the initial product was a monolithic DC-DC converter L4960 family from
STMicroelectronics. Vicor Corporation takes the lead in soft switching DC-DC
converter worldwide, whose products feature maximum power of 300 W, 600 W,
and 800 W, correspondingly power density of 6.2 W/cm3, 10 W/cm3, and 17 W/cm3,
and efficiency of 80%–95%. The soft switching technology keeps developing for
14 Analog and Mixed-Signal IC Products 245

high-frequency and high-power density, and its frequency reaches megahertz range.
With the development of semiconductor and packaging technology, high-frequency
soft switching technology grows enabling power density exceeding 50 W/cm3 and
efficiency over 90%.
To meet the requirement of DC test equipment, computer video display, and
computer and military communication, low-power DC-DC converter grows remark-
ably in market, especially for 6–25 W DC-DC converter. As for applications in
medical instrument, industrial control system, and telecommunication, DC-DC
converter develops from lower power to medium and high power ranging from
251 W to 750 W. As a part of power management, DC-DC converter works to serve
not only computers but also other applications such as the driver of cellphones and
active matrix organic LED of portable devices.
Digital DC-DC converter [19, 20] is available as DC-DC converter technology
develops. Digital DC/DC products bring variety of intelligent module DC power
supply. More types of intelligent DC-DC converters are coming to market for
applications in distributed power system of spacecraft and aerospace network.

Switching Power Supply Controller

Switching power supply controller [21] is used to realize closed-loop control and
other protection functions for switch power supply. As a core part, it consists of
reference, error amplifier, oscillator, PWM comparator, latch circuit, and output
stage. Switching power supply controller features high integration, good consis-
tency, and simple peripheral components. Switching power supply controller is
sorted into pulse-width modulation (PWM), pulse-frequency modulation (PFM),
phase-shift resonant (PSR) controller, and synchronous rectifier controller. PWM
controller features highest efficiency among other switch power supplies on a wide
load range, which makes it the most mature product and has widest applications.
On condition of a consistent output signal frequency, PWM controller regulates
the pulse width (duty cycle) of power switch controlling signals to control charging/
discharging time of inductor for a stable output voltage. The topologies of single-
end, push-pull, semi-bridge, buck, boost, isolation, and non-isolated type are used.
The typical products are SG1525A from Microsemi, UC1843 from TI, and UC1825
and LT3845 from ADI. How PWM feedback control works is shown in Fig. 14.6.
On condition of a consistent pulse width of power switch control signals, output
signal frequency, PFM controller regulates the frequency of output signals by using
feedback control circuit to control charging/discharging time of inductor for a stable
output voltage. Sine wave is substituted for square wave, which greatly decreases
high-frequent noise of switch power supply. PFM controller works to enable zero-
voltage switching (ZVS) or zero-current switching (ZCS) of switch tubes. As switch
tube is on and off at zero voltage or zero current, the voltage and current crossover
loss is evidently decreased and power efficient is increased. The size is decreased,
and quality is improved by increasing switch frequency. The products, such as
246 Y. Guan et al.

Fig. 14.6 Feedback control principle of PWM

UC1860, UC1864, and UC1868, feature operation frequency over 1 MHz, driving
current larger than 200 mA.
With wide applications in full-bridge topology, PSR controller has invariable
frequency and duty cycle of output signals at each channel. By adjusting the phase of
power switch drive signals at bridge arms, the converter works to regulate operation
pulse width for a consistent output voltage. It features advantages that PFW and
PWM have. It regulates the pulse width the way PWM does and keeps zero voltage
(or zero current) status while the switch is on and off. Finding wide applications in
large power switch power supply, it has typical products, such as UC1875, UC1876,
and UC1879.
Synchronous rectifier controller is designed to solve the problem of high positive
voltage of rectifier Schottky diode, as the Schottky diode has forward voltage drop
above 0.3 V. The synchronous rectifier is replaced by power MOS device, which
enables low on-resistance of several milliohms (mΩ) resulting lower on-resistance
consumption and higher switch power conversion rate. Synchronous rectifier con-
troller has applications in non-isolation DC-DC converter, such as LT3844 and
LT3845.
Digital converter is a novel switch power controller, consisting of analog-to-
digital converter, discrete compensator, and digital PWM. The main product is
TMS320LF2407A from TI.
The performance of high-power density, high reliability, and low noise matters for
switching power technology and products. The way to improve power density and
reliability is mostly realized by increasing conversion rate and being miniaturizing.
Downing the road, the switch power controller develops for higher operation
frequency and digitalized controlling way. The improvement of operation frequency
is helpful to not only decrease the noise and the size of capacitors, inductors, and
invertors, but also ameliorate dynamic performance of power supply.
14 Analog and Mixed-Signal IC Products 247

Low Dropout Regulator (LDO)

Low dropout regulator (LDO) is a linear regulator featuring low output/input voltage
drop and offering a stable output voltage at limited power supply. In 1967 for the first
time, Robert Dobkin [22] presented a low-voltage-drop linear regulator featuring the
difference of 0.7 V of input and output voltage. Fabricated in BCD process, the LDO
operates featuring 115 mV at 3A output current, with power and size being evidently
decreased.
Board-level power or batteries bring large voltage fluctuation, so voltage regula-
tors are used to improve the quality of power supply for electronic components at
back-end input power supply. Compared with DC-DC switch regulator, LDO is a
voltage linear regulator, featuring low noise itself and high-power supply rejection
ratio (PSRR) in ways that greatly improve the quality of front-stage power supply.
LDO has low static power, small size, low cost, and simple peripheral applications. It
features higher conversion power and lower efficiency than DC-DC converter does.
As shown in Fig. 14.7, low dropout regulator uses negative feedback controller to
output a stable voltage. The core part of LDO consists of a reference, error amplifier,
and regulator tube and feedback resistor. The regulator tube works at linear area and
serves as an adjustable resistance. When input voltage or load transiently changes,
the output voltage from regulator tube is consistent by employing sample, error
amplification, and negative feedback.
According to the types of regulator tubes, LDO types include npn quasi-LDO,
pnp-LDO, pMOS LDO (p-FET LDO), and nMOS LDO (n-FET LDO). The trans-
mission transistor, respectively, uses npn transistor, pnp transistor, and pMOS and
nMOS transistors in sequence of from highest to lowest dropout voltage. Concerning
the power supply types, it has positive LDO to regulate positive voltages and
negative LDO to regulate negative voltages.
To meet the requirement of system-on-chip and high-performance devices, LDO
is not developed for low power and large current anymore, but for high PSRR and
highly integration [23]. Power clutter is decreased, and noise band of power supply
suppression is enlarged, which meets the demand of power supply for RF, high-end

Fig. 14.7 Structural diagram

of LDO
248 Y. Guan et al.

ADC and DAC. A novel frequency compensation method is employed to realize

off-chip capacitor design, in a way that enables multiple LDO integrated on SoC. As
a mainstream, LDO develops for highly integration of SoC with multiple LDOs.
Speaking of this, key issues for LDO technology are concerned: load transient
response, over-hoot resistance, and recovery time.
TI developed an LDO product for various applications. For example, low noise
TPS7A88 is launched for RF and analog circuits, featuring noise root mean square
(RMS) of 3.8 μV. For battery supply, TPS782 features static current of 500 nA.
TPS7A4001 has enlarged input voltage up to 100 V for transient voltage of wide
input range. To eliminate the switch noise of FPGA and DSP, TPS7A84 has output
current up to 3A, noise RMS of 4.4 μV, and accuracy of 1%.

Light-Emitting Diode Driver

Light-emitting diode (LED) driver is a power supply regulator device being used to
drive LED lighting or LED modules. Initial LED only features red, green, and
yellow lights for signal indication. It was driven by switch current-limiting drive.
Several novel drivers were developed for lighting and display applications. In 2005,
a novel AC LED was launched without driver [24].
LED driver works to provide constant voltage or current for LED in ways that
expand the lifetime of LED device and enable stability of LED lighting, brightness
control, and improvement in efficiency of the driver. According to the way of LED
driver works, it is categorized into constant voltage resistance-limiting current drive
and constant current drive. The way constant voltage resistance-limiting current
driver works is shown in Fig. 14.8, wherein the driver works to provide pulse
voltage to regulate LED visual brightness. But the constant current driver tends to
regulate the LED brightness by changing the internal reference voltages. As for RGB

Fig. 14.8 Principle of

constant voltage resistance
and current-limiting LED
driver
14 Analog and Mixed-Signal IC Products 249

color model, full-color display is realized by controlling the brightness of red, green,
and blue lights. The constant current drive LED driver is categorized into linear
constant LED driver and switch constant current-driven LED driver as, respectively,
shown in Figs. 14.9 and 14.10.
As for constant voltage resistance-limiting current LED driver, the current is
defined by LED voltage dropout and the dropout at limiting current resistor of LED
in series. The driver tends to control on–off status of voltage signals. Due to the
negative temperature characteristic of LED, the drive current is not immune to
environment conditions, featuring bad stability. LED lifespan is directly related to

Fig. 14.9 Principle of linear

constant LED driver

Fig. 14.10 Principle of

switch constant current-driven
LED driver
250 Y. Guan et al.

drive current. So the driver is used for low-end products, such as the LED driver of
single- and dual-colored display, wherein the LED lifetime is not strictly required.
Linear constant current LED driver employs linear regulator with reference error
amplifier and power tubes integrated. It works to control the voltage at current
sample resistor which is connected to LED in series in a way that keep a constant
current through LED. The driver features good constant current but low efficiency,
because the driver must take large voltage dropout resulting from the difference
between input voltage and LED voltage at amplification status.
Switch constant current LED driver uses the way switch power supply controls by
controlling the voltage at sample resistor to enable a stable LED current. As it
operates at switching status, the power device features low power consumption
and high efficiency but tiny ripple-wave current through LED. Attention must be
paid to EMI issue when it comes to switch driver. Filter is required to filter EMI
when necessary.
Constant voltage resistance-limiting current LED driver tends to provide pulse
voltage to regulate LED visual brightness. Constant current LED driver works to
control LED brightness by changing internal reference voltage.
So far, LED finds wide applications. LED driver providers are mainly TI, Maxim,
etc. Only speaking of TI, it produces various LED drivers exceeding 300 categories.
LED driver develops higher efficiency and lower power consumption in an
environment-friendly way.

Liquid Crystal Display Driver

Liquid crystal display (LCD) driver is used to regulate phase, peak, and frequency of
level signals at both ends of LCD in real time in ways that display electronic devices
through liquid crystal.
Comparing to CRT (cathode-ray tube), LCD features low operation voltage, low
power, easy to be colorful, high definition, no electronic–magnetic radiation and
long lifetime. For early calculators and timers, only color (usually black) and
colorless (Twisted Nematic, TN) are available for the liquid crystal display. Later,
super-twisted nematic (STN) LCD is introduced featuring wider visual angle and
finer character. The thin-film transistor (TFT) LCD features short image developing
time for dynamic pictures and real-time display, which has wide applications in
digital camera display and large-sized flat panel TV displays. According to the
relation between control electrode and each pixel, the LCD driver is categorized
into static and dynamic driving [25].
In the static driving, each segment of display has an independent drive circuit.
Directly regulate the relative voltage and phase between segment electrode and
common electrode to change the segment display. The static driving method has
advantages of simple structure and well-performed display with applications in
stroke liquid crystal display of numbers, letters, and special figures.
It is impossible for pictures requiring millions of pixels to use static driving
method. Dynamic driving method is introduced, wherein electrodes are displayed in
14 Analog and Mixed-Signal IC Products 251

matrix way. The electrode matrix is controlled by logic circuit side and liquid crystal
drive side. Logic circuit side works to transmit and latch display data according to
required display. And liquid crystal drive side tends to control corresponding line
driver and column driver according to the data from logic circuit side. It updates the
data column by column. When all data of updated line are latched, it starts to switch
from line to line. There are gate drive and source drive circuits available for LCD
driver. When scanning, the gate driver controls to switch on transistors in column
and the source driver works to control the brightness, greyscale, and hue line by line.
Driving output at drive side usually has more than one ends, which determines the
ability of the LCD driver.
The main LCD providers are Renesas Electronics, Samsung, Magnachip, etc. At
present, character LCD driver and graphic dot matrix LCD driver are popular in the
market with wide applications in MSTN (monochrome super-twist nematic), CSTN
(color super-twisted nematic), TN, TFT, and OLED displays. The control signals of
LCD driver come from LCD controller which transmits LCD image data of system
storage to external LCD driver. In future, developing for large-size, LCD display is
about to provide large rail-to-rail output swing to enable large dynamic range
required by video operational amplifier.

Motor Controller

Motor controller, also named as motor driver, consists of several circuits for con-
trolling speed, moment, position, and overload protection. According to input
signals and other sensing signals, motor controller operates to control the direction
of motor winding current by using internal algorithm, in ways that start, stop,
forward rotate, and backward rotate the motor. Motor controller tends to set and
stabilize rotation rate, level off, and set a limit to a rotation moment and protect the
motor when it comes to overload and locked rotor. General-purpose motor controller
[26] is used to keep an expected operation status. Some of the special application
motor controllers, such as servo controller, work to control the whole servo system
(including motor, decelerator, and sensor) at a normal operation status. Motor
controller is integrated with logic and power drive circuits. On condition of electro-
nic–magnetic interference, motor controller is designed and fabricated in bipolar-
CMOS-DMOS (BCD) process with highly strict requirement. The operation voltage
range, continual current output, peak current output, and ESD are the key specifica-
tions of the motor controller.
Monolithic power switch motor control finds applications in tiny-small power
devices, such as printer, office automation, fans, and camera. Large power motor
controllers for washer and vacuum cleaner, featuring hundreds or thousands watts,
are configured with programmable processors for motor controller. It has power
switch devices to realize large current controller.
Motors have various categories with each having unique control mode; thus, there
are DC brush motor driver, DC brushless motor driver, and stepper motor driver
[27]. As semiconductor technologies and motor control technologies are progressed
252 Y. Guan et al.

over past years, some IC companies are able to provide full solutions for motor
controller, including TI, ST, Allegro and MicroSystems, as well as Chinese enter-
prises, such as Hangzhou Silan Microelectronics, Sinotech Mixic Electronics,
Shanghai Bright Power Semiconductor, and Fortior Technology.

Serializer/Deserializer

The serializer/deserializer (SerDes) is characterized in that the data and the clock are
transmitted in the same channel, and the clock information contained in the data is
extracted by the clock data recovery (CDR) technology at the receiving end and
sampled and received by the clock. The basic SerDes function is made up of two
functional blocks: the parallel-in serial-out (PISO) block (aka parallel-to-serial
converter, PSC) and the serial-in parallel-out (SIPO) block (aka serial-to-parallel
converter, SPC). Currently, most high-speed signal transmission uses the SerDes
structure.
The transmitter (TX) of SerDes includes parallel–serial converter, encoder, trans-
mitter equalization, and driver. The receiver (RX) of SerDes includes receiver
attenuator, receiver equalization, clock data recovery, decoder, and serial–parallel
conversion. At present, SerDes mainly includes (1) parallel clock SerDes, (2) embed-
ded clock SerDes, (3) the 8b/10b SerDes, and (4) bit-interleaved SerDes [28].

1. In the parallel clock SerDes scheme, the clock and data are separated, and the
data and control/address bit signals are respectively transmitted, wherein the data
and the clock signal are, respectively, transmitted through a specific line, which is
commonly used for low-speed transmission. The advantage is that no clock data
recovery circuit is required, the circuit is simple, and the jitter requirements are
low; the disadvantage is that an additional clock line is required, and the clock
line causes electromagnetic interference (EMI) and crosstalk, so it cannot be used
on a high-speed link. Currently, this type of SerDes is used in DDRs and other
similar designs.
2. The architecture of embedded clock SerDes is a standard SerDes architecture in
which the clock is embedded in the data signal and recovered at the receiving end
via the CDR. The advantages are that the effects of electromagnetic interference
and crosstalk caused by separate clock lines are eliminated, reducing the impact
of the clock line on the PCB layout; the disadvantage is that the remote clock
recovery requires small jitter. PCIe, USB 3.0, USB 3.1, and SATA all use this
SerDes solution.
3. The 8b/10b SerDes scheme adds additional code to the serial data to balance the
DC component and reduce the CDR pressure. The encoding is not necessarily
8bit/10bit, but also has a more efficient encoding, such as 128-bit/132-bit
encoding used in PCIe3.0. The advantage is that the inserted bits prevent long
“1” or “0” patterns, and thus, it is enough to let the CDR receive 0/1 hopping to
ensure its normal operation; the disadvantage is that the inserted bit will be
redundancy. The 8-bit/10-bit encoding can achieve up to 20% redundancy.
14 Analog and Mixed-Signal IC Products 253

4. The bit-interleaved SerDes scheme combines multiple low-speed serial data

into one high-speed serial data. The advantage is that it can increase the rate and
reduce the number of data transmission channels, which is beneficial to the PCB
layout, and reduce crosstalk; it requires additional clocks, selectors, and CDR
circuits. Ten gigabit attachment unit interface (XAUI) is implemented through
this architecture.

Due to the continuous increase in data transmission speed, the SerDes architec-
ture has been continuously developed. When the early signal transmission speed is
only kbit/s to Mbit/s, the parallel interface is sufficient. However, as IC manufactur-
ing processes are progressed and transmission rates increase, crosstalk caused by
high-speed signals, especially clock signals, to other transmission lines is increas-
ingly serious and impacts transmission quality. At the same time, miniaturization of
application products requires reduction of the lines on PCB. Therefore, the SerDes
that uses a serial line and does not require a separate clock line is the best choice. The
SerDes architecture is widely used in civilian high-speed interface protocols. At
present, major companies use SerDes architecture to implement high-speed interface
products, such as Synopsys USB/PCIe/SATA IP, Huawei 10 Gbit/s Enterprise
SerDes, and Xilinx 26 Gbit/s SerDes launched in 2011. Intel in 2019 is showing
off 112Gbps SerDes that was produced in 10 nm FPGA process [29].

Serial Communication and Universal Serial Bus Interfaces

In 1960, Electronic Industries Alliance (EIA) issued the first serial communication
standard, namely RS-232 (Recommended Standard). RS-232 standard initially
serves for telephone/telegraph signal transmission and then for interface connection
between PC and peripheral equipment (such as printers). RS-232 tends to provide
standards of transmission distance less than 15 m, rate of 20 kbit/s, for single driver,
and single receiver. EIA published RS-422 in 1994, which says that data transmis-
sion rate up to 10 Mbit/s, transmission distance up to 1200 m. In 1998, RS-485
standard was issued, wherein 32 bus receivers were available as bus multipoint
output was realized by adding three-status output function. The standard interface
features 9 and 25 pins. Specifications of the three standards are shown in Table 14.2
and interface modes in Fig. 14.11. Now, these interfaces are gradually replaced by
universal serial bus (USB) and Ethernet interface. RS series protocols are typically
adopted for universal asynchronous transceiver (UART) in serial port communica-
tion of asynchronous serial communication computers.
In 1994, Inter, Microsoft, IBM, and Compaq proposed USB protocol, which was
highly related to high-speed serializer/deserializer (SerDes) technology. A USB
interface enables serialization and deserialization; wherein multichannel parallel
low-speed data signals are converted into serial signals at transmission end and
transmitted through coaxial line at high speed, the signals are then deserialized into
multichannel parallel low-speed data signals. This is called P2P serial
254 Y. Guan et al.

Table 14.2 Parameters of RS-232, RS-422, and RS-485 serial communication standards
Protocols RS-232 RS-422 RS-485
Transmission mode Single-end Differential Differential
transmission transmission transmission
Number of BUS node 1 driver/1 receiver 1 driver/10 1 driver/32
(maximum) receivers receivers
Cable transmission length 15 m 1500 m 1500 m
(maximum)
Transmission rate (maximum) 20 kbit/s 10 Mbit/s 10 Mbit/s
Output driving voltage 25 V 0.25 V to +6 V 7 V to +12 V
(maximum)
Load impedance at drive end 3 to 7 kΩ 100 Ω 54 Ω
Slew rate (maximum) 30 V/μs – –
Input voltage at receiving end 15 V 10 V to +10 V 7 V to +12 V
Input range at receiving end 3 V 200 mV 200 mV
Input impedance at receiving 3 to 7 kΩ 4 kΩ (min) 12 Ω
end
Common-mode voltage at – 3 V to +3 V 1 V to +3 V
drive end
Common-mode voltage at – 7 V to +7 V 7 V to +12 V
receive end

Fig. 14.11 Interface modes of RS-232, RS-422, and RS-485

communication technology which takes less transmission channel and device leads
in a way that realizes high-speed transmission and saves the cost at communication
transmission.
USB interface internally consists of only two cables and two signal lines working
to transmit signals at serial mode. According to USB transmission protocol, data are
packed up by USB transceiver chip, converted into serial data flow and sent at high-
speed through the two signal lines (D+, D-). USB at receive end works to receive and
deserialize the serial data which ends the whole data transmission. USB interface
system consists of hub, host computer, and function peripherals. Hub and function
peripherals are called as external devices. USB standards are updated at high
frequency of which the regulated data transmission rate is greatly improved, as
shown in Table 14.3 [30].
The physical size of USB connectors has been keeping down. In 2007, USB-IF
published micro-USB (micro-A, micro-B) standard, featuring similar width to mini-
USB (mini-A, mini-B) standard but half thickness of the mini-USB. In 2014, USB
14 Analog and Mixed-Signal IC Products 255

Table 14.3 Parameter comparison of different USB standards

Version Data transmission rate Mode Issue year
USB 1.0 1.5 Mbit/s Low speed 1996
USB 1.1 12 Mbit/s Full speed 1998
USB 2.0 480 Mbit/s High speed 2000
USB 3.0 5 Gbit/s Super speed 2008
USB 3.1 10 Gbit/s Super speed+ 2014
USB 3.2 20 Gbit/s Super speed+ 2017
USB 4.0 40 Gbit/s Super speed+ 2019

Fig. 14.12 Profiles of USB interfaces (not proportional)

type-C protocol published by USB-IF gave a definition of a smaller and thinner

connector which substitute for type-A and type-B connector. Cables can be positive
and negative plugged. The plug works at both host computer and peripheral equip-
ment, which enables a simple connection. On September 2012, Apple Company
launched a novel lighting interface specialized for data bus of specific use computers
and power cable connection. It works to substitute for Apple 30-pin base connector
for Apple mobile portable devices. USB interfaces are shown in Fig. 14.12 [31].
USB interfaces meet the requirement of cascade connection between devices and
feature simple connection, high-speed transmission, plug in and out, and no need for
extra power supply. It finds wide applications in keyboard, mouse, flash memory,
and camera which makes it a standard interface for all computers and many other
electronic devices.

Ethernet Interface IC

Ethernet is a kind of computer network technology (CNT) enabling communications

at local area network (LAN) and metropolitan area network (MAN). Interfaces that
work to realize connection between these network devices are called as Ethernet
interfaces; all network interfaces in the market are named as Ethernet interfaces.
Some of them are common and popular including RJ-45 interfaces, RJ-11 interfaces,
SC fiber interfaces, fiber distributed data interfaces (FDDI), adaptive user interfaces
(AUI), Bayonet Neill–Concelman (BNC) interfaces and console interfaces.
256 Y. Guan et al.

In 1980, 3Com, DEC, Intel, Xerox, and other companies together published
agreement of the DIX (Digital Intel Xerox) Standard providing data speed of
10 Mbit/s Ethernet features 48-bit target and source address and global 16-bit
Ether-type fields [32]. Original Ethernet data transmission reached 10 Mbit/s by
using carrier sense multiple access with collision detection (CSMA/CD). IEEE 802.3
protocol was established in 1983 which formally standardized Ethernet protocol. As
demands for network application grow, Ethernet attains higher data transmission rate
and longer transmission distance for network data transmission. So Ethernet protocol
was improved to meet the requirement [33]. On October 1993, Grand Junction
provided the first fast network interface card (FastNIC 100) and hubs
(10/100 Mbps fast Ethernet switch) which succeeded in commercial application.
3Com, Intel, Bay Networks, and SynOptic successively launched various fast
Ethernet devices. In March 1995, IEEE published IEEE802.3u fast Ethernet standard
in the form of 100Base-T. Gigabit Ethernet technology is going popular in applica-
tion, and Terabit Ethernet starts to find applications. Terabit Ethernet works to
support 10 Gbit/s transmission rate in IEEE802.3ae standard. IEEE802.3ae standard
is based on IEEE802.3 standard.
Ethernet physical structure consists of medium access control (MAC) and phys-
ical interface transceiver (PHY). MAC chip works to control the physical medium of
physical layer and provides a system to address and control channel access, which
enables multiple terminals or network nodes to communicate between multiple
accesses network with shared medium. PHY transceiver chip enables transmission/
receiving function of Ethernet physical interfaces. The chip works to convert parallel
data into serial data for transmission, convert data coding into analog signals
according to coding rules of physical layer, and transmit the analog signals. For
receiving data, it works in reverse procedure. Besides, PHY transceiver features
carrier sense and collision detection.
Main Ethernet interface products include 10/100 megabit Ethernet and gigabit
Ethernet PHY transceivers, such as Cisco WS-C2960 series and WS-C3850 series
and Huawei S57xx series gigabit Ethernet with wide application in network printer,
Broadband Gateway, smart TV, set-top box (STB), smart grid, and building auto-
mation system. For applications in Web virtual reality technology, distributed arti-
ficial intelligence, 4K high-definition TV (HDTV, UHD), network virtual game, and
network bandwidth demand grow fast which beef up terabit Ethernet technology to
substitute for gigabit Ethernet.

Interface for Standard-Definition Television and High-Definition

Television

Standard-definition television (SDTV) technology generally supports the “standard-

definition” video formats such as VCD, DVD, and TV programs; SDTV is typically
480i signal, where 480 represents the vertical resolution, and letter i represents
interlaced. SDTV technology is often used in multimedia equipment, like TV sets,
TV set-top boxes, cameras, and video conference. The video signal transmission
14 Analog and Mixed-Signal IC Products 257

interface of SDTV, like CVBS, S-Video, and VGA, is mostly using analog signal.
The pixel display aspect ratio (DAR) of SDTV has 4:3 and 16:9 two types.
The CVBS interface stands for composite video broadcasting signal (CVBS) or
composite video blanking and sync (CVBS) [34]. The CVBS interface, also known
as baseband video or RCA (Radio Corporation of America) video, is a traditional
image data transmission method for television signals developed by the
U.S. National Television System Committee (NTSC) since 1954, which uses analog
waveforms to transmit data.
The S-video interface (separate video interface) specification was developed in
Japan, which separates the luminance signal and the chrominance signal to avoid
interference of luminance and chrominance when the mixed video signal is trans-
mitting [35]. The S-video is a five-core interface consisting of two video brightness
signals, two video chrominance signals, and one common shielded ground wire. The
S terminal is commonly available in 4-pin, 7-pin, 8-pin, and 9-pin models.
The video graphics array (VGA) interface belongs to the analog interface. The
standard VGA (640
480, 60 Hz) interface transmits 3 RGB analog signals,
horizontal sync (HS), and vertical sync (VS) [36]. Firstly, VGA converts the digital
signal into an analog signal in computer and sends the signal to the LCD display, and
then, the display converts the analog signal into a digital signal to a picture.
Generally, when the analog signal exceeds 1280
1024 resolution, obvious error
will occur. The higher the resolution is, the more serious the error is. Therefore, VGA
is being gradually replaced by the high-definition multimedia interface (HDMI).
High-definition television (HDTV) mainly supports the following three formats:
① progressive scan 1080p, 1920
1080p, about 2.07MP (megapixels) per frame;
② interlaced (interlaced scan) 1080i, 1920
1080i, about 1.04MP per field or
2.07MP per frame; and ③ progressive scan 720p, 1280
720p, about 0.92MP per
frame. The aspect ratio of HDTV includes 4:3 and 16:9. HDTV format has been
widely used in terrestrial broadcast television, cable television, satellite television,
DVD, etc. [37].
The MPEG-1 (Moving Picture Experts Group Phase 1), which was developed in
1993, brings three standards for Digital Video Broadcasting (DVB): ① DVB-S (for
satellite television), ② DVB-C (for cable television), and ③ DVB-T (for terrestrial
broadcast television). DVB supports both MPEG-2 and H.264, also known as
MPEG-4 AVC (advanced video coding) standards. AVS (Advanced Video coding
Standard) and AVS+ are the audio and video standard proposed by China, and its
encoding performance is basically equivalent to H.264 (or H.264/AVC). H.265
(or H.265/HEVC) is a new-generation standard of high-efficiency video coding
(HEVC) based on H.264, while AVS2, the new-generation standard of AVS, has a
competitive performance of H.265/HEVC.
From SDTV and VGA to HDTV and DVB, as well as related standards of HEVC
and AVS2, these standards contain a very rich content, and the application scenarios
are also very broad, so that many types of interface IC chips are needed and to be
developed. These requirements create many challenges for the IC design of HDTV
products.
258 Y. Guan et al.

High-Definition Multimedia Interface IC

High-definition multimedia interface (HDMI) is a proprietary audio/video interface

for transmitting uncompressed high-definition (HD) video data; multichannel sur-
round sound audio data and consumer electronic control (CEC) signal over a single
cable between electronic devices [38]. HDMI can be utilized with high-bandwidth
digital content protection (HDCP) to prevent unauthorized copying of audio and
video content for copyright protection. HDMI also supports digital audio formats
such as DVD audio, which enables multichannel 96 kHz or stereo 192 kHz digital
audio transmission and uncompressed audio and video signal transmission. The
HDMI system module is shown in Fig. 14.13.
HDMI can be used in set-top boxes, DVD players, personal computers, game
consoles, amplifiers, digital speakers, and televisions. As EDID (extended display
identification data) and DDC (display data channel) are both supported by HDMI,
devices with HDMI feature “plug and play” and a “negotiation” is performed
between the source and display device automatically to select the most appropriate
video/audio format.
HDMI 2.1, the latest version officially announced in January 2017, adds support
for 4K and 8K ultra-high-definition videos with a maximum data rate 14.4 Gbit/s.
Meanwhile, there is no need for digital/analog or analog/digital conversion before
any signal transmission.

Fig. 14.13 HDMI system module. DDC display data channel, EDID extended display identifica-
tion data, CEC consumer electronic control, HEAC HDMI, Ethernet, audio, control, HPD hot plug
detect
14 Analog and Mixed-Signal IC Products 259

Commonly used HDMI chips are HD transmitter, HD receiver, HD splitter, HD

switch, HD converter, HD matrix, etc. Well-known manufacturers are Silicon Image,
Pericom, Explore, CAT, etc. Additionally, the DisplayPort (DP), the successor of
DVI (Digital Visual Interface) and VGA, has been mainly used between computers
and monitors, and the newer video cards and computers in DP [39] are integrated
with HDMI and DVI.
Recently, HDMI Licensing, LLC, [40] has released the HDMI transfer mode
developed by HDMI Founders for the USB type-C specification, which allows
HDMI-enabled source devices to connect to HDMI-enabled displays directly,
using USB type-C connectors. This enables local HDMI signal transmission, with-
out any demand for protocols and connectors, adapters, or hardware protection
devices, but over a single cable.

Advanced Technology Attachment Interface

In 1984, IBM launched Advanced Technology (AT) Personal Computer (PC) which
featured parallel interface Advanced Technology Attachment (ATA); the original
parallel ATA was then called PATA since Serial ATA (SATA) was launched in 2003
[41]. At present, SATA dominates over PATA according to the market share.
ATA is highly related to disk drive which is realized by integrated drive electron-
ics (IDE). Generally, ATA is a disk-controlling technology and IDE a disk-driving
technology. Normally either of them stands for the other. Development and appli-
cations of ATA are related to IDE, as they belong to IDE technology. Initially, IDE
was only used as an interface between controllers and disks. International standard
organizations provided disk industrial standards according to ATA interface speci-
fications in a way that generates ATA Standard.
Small computer system interface (SCSI) is used to connect computers to periph-
eral devices [42]. SCSI standard defines commands, protocols, electrical interfaces,
and optical interfaces. SCSI mostly has application in disk drive and magnetic tape
drive and connection to other equipment, such as scanner and CD driver. SCSI is a
set of parallel interface standards developed by ANSI, while PATA was made from
ATA interface, as one kind of SCSI interfaces for early PC product. Synonyms and
other informal names of ATA/ATAPI are used at the moment, especially Extended
IDE (EIDE) and Ultra ATA (UATA).
Either ATA or SATA of host computer control chip is integrated into each
mainboard, enabling connection to four devices at least. Most microprocessors
and motherboard controllers are configured with SATA interfaces, such as products
from Intel, IBM, and AMD. Up to date, ATA (IDE) interfaces can be categorized
into ATA-1 (IDE), ATA-2 (Enhanced IDE/Fast ATA, EIDE), ATA-3 (Fast ATA-2),
Ultra ATA, Ultra ATA/33, Ultra ATA/66, Ultra ATA/100, and Serial ATA. ATA
interfaces are modified and improved many times. First generation of ATA inter-
faces is ATA-1, namely the first standard specification being used in desk 386 series
of Compaq (acquired by HP in 2013). It is regulated as master/slave structure with
following version being published successively ATA-2, ATA-3, ATA-4, ATA-5,
260 Y. Guan et al.

ATA-6, ATA-7 and Compact Flash6.0. ATA-4 regulates the transmission rate of
16.7–33.3 MB/s, that of ATA-7 up to 133 MB/s, and that of Compact Flash6.0 up
to 167 MB/s.
First-generation SATA interface (SATA version 1.0) was released on January
2003, featuring communication rate of 1.5 Gbit/s. The second-generation SATA
version 2.0 (3 Gbit/s, 300 MB/s and Serial ATA-300) was published on April 2004,
compatible with SATA 1.5 Gbit/s version. Physical layer specifications of SATA
version3.0 (6 Gbit/s, 600 MB/s and Serial ATA-600) were drafted by SATA Inter-
national Organization (SATA-IO) in July 2008. And its final version 3.0 was
provided on May 2009. SATA version 3.3 was published in February 2016, featuring
transmission rate up to 16 Gbit/s.
At present, ATA interface products have broad applications in computer data
processing and transmitting devices, including mainboard, disks, CD-ROM, and
other things. These products are usually integrated on internal devices in the form of
chips, featuring simple connection, high-speed transmission, and meeting the
requirement of cascade connection of multiple devices. It became one of indispens-
able interfaces for computers.

DDR SDRAM Interface

Double data rate synchronous dynamic random-access memory (DDR SDRAM) is

briefly denoted as DDR. Samsung demonstrated the first DDR SDRAM prototype in
1996, with the DDR interface double pumping (transferring data on both the rising
and falling edges of the clock signal), to achieve double data rate (or two words per
clock cycle) than a SDR SDRAM (single data rate SDRAM, SDR SDRAM,). DDR
interface connects DDR to DDR physical interface (PHY) and DDR controller.
A DDR interface (DDR I/F) entails each DDR module transferring data to/from
the memory controller by means of several digital data streams [43], which are
accompanied by a strobe signal. As these data can flow both from the controller to
the DRAM (write operation) and from the DRAM to the controller (read operation),
these digital lines are bidirectional in nature.
The DDR interface standard is defined, upgraded, and maintained by the JEDEC
organization. The existing protocol standards are DDR (JESD79), DDR2 (JESD79-
2) DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209). LPDDR2
(JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), and LPDDR4X
(JESD209-4-1); LPDDR5 and DDR5 protocols are under development. There is
also a GDDR (graphics DDR) interface for graphics processing chips. The charac-
teristics of the DDR interface protocols are shown in Table 14.4 [44–46].
From the system level, the main chip needs to access the memory DRAM (in the
synchronous working state, that is, SDRAM) through the DDR interface, so the
DDR controller and the DDR physical interface (PHY) need to be included in the
main chip design. The DDR controller is used to process SoC access to DDR
 14

Table 14.4 Comparison of DDR/LPDDR standards

Feature DDR1 DDR2 DDR3 DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 LPDDR4X
Peak data 400 800 2133 3200 400 1066 2133 4266 4266
transfer rate/
(Mbit/s)
Bus feature Single Single Single Single channel Single Single Single Multichannel Multichannel
channel channel channel channel channel channel 16 bit per 16 bit per
channel channel
Burst length 2, 4, 8 4, 8 4 (burst 4 (burst 2, 4, 8, 16 4, 8, 16 8 16, 32 16, 32
(BL) chop, BC), 8 chop, BC), 8
I/O voltage 2.5 V 1.8 V 1.5 V/1.35 V 1.2 V 1.8 V 1.2 V 1.2 V 1.1 V 0.6 V
Analog and Mixed-Signal IC Products

Command/ SDR SDR SDR SDR DDR DDR DDR SDR SDR
address bus command command command command command command command command command
sampling sampling sampling sampling sampling sampling sampling sampling sampling
Bank group 0 0 0 2, 4 0 0 0 0 0
Maximum 4 8 8 16 4 8 8 8 8
bank number
Monolithic 4, 8, 16 4, 8, 16 4, 8, 16 4, 8, 16 16, 32 16, 32 16, 32 16, 32 16, 32
width/bit
On chip- N ODT ODT signal Dynamic, ODT N N Support Support Support
resistor signal required signal not DQ (CA, DQ) (CA, DQ)
matching required required
Reference N N N Y N N N Y Y
voltage
training
CRC N N N Y N N N N N
DBI N N N Y N N N Y Y
261
262 Y. Guan et al.

Fig. 14.14 Structural diagram of DDR main chip

commands. It supports bus multiport arbitration and maps the arbitrated command
address to the DDR address space. The DDR PHY converts the DDR controller’s
access SDR signal into a DDR dual-edge data access signal and sends it to the
appropriate DRAM (or SDRAM) according to the electrical characteristics required
by the DDR PHY; the sampled read data are converted to a single edge data transfer
to the DDR controller. The structure of the DDR main chip is shown in Fig. 14.14.
Some DDR PHYs also include DDR initialization, eye diagram training, and ZQ
calibration. The DDR controller is interconnected with the DDR PHY by a DFI
(DDR PHY Interface) bus defined by the DDR PHY. This interface defines the
handshake between the DDR controller and the DDR PHY, normalizing the interface
design, and the current major controllers and PHY IP vendors follow this protocol.
At present, the mainstream suppliers of DDR SDRAM chips are Samsung, SK
Hynix, and Micron. Each company can provide a full range of DDR SDRAM chips
of various capacity and speed grades, such as DDR4 SDRAM, DDR3 SDRAM,
DDR2 SDRAM, DDR SDRAM, GDDR, LPDDR4, LPDDR3, and LPDDR2.
These DDR chips are packaged in VFBGA, WFBGA, TFBA, PoP, FBGA, and
UFBGA. The application market of DDR SDRAM is very broad: For the consumer
market, there are many DDR chips with multiprotocol interface. For example,
monitoring products and set-top boxes mainly use hybrid DDR chips (DDR3,
DDR4, and LPDDR3). In-vehicle devices mainly use DDR3 and LPDDR2,
LPDDR4 and other chips that meet the vehicle standard; smart watches generally
use LPDDR3, LPDDR4, and LPDDR4X; mobile terminals generally use
LPDDR4, and some use LPDDR4X to further improve performance and reduce
power consumption; UAVs generally use DDR4, LPDDR3, and LPDDR4; in the
server market, low-end PCs typically use DDR3 UDIMMs, DDR4 UDIMMs, and
high-end servers use DDR4 RDIMMs, DDR4 RLDIMMs, and NVDIMMs
[46, 47].
14 Analog and Mixed-Signal IC Products 263

Protocol Converter IC

Protocol converter, also called interface converter, works to convert one device
protocol into the other device protocol including data information, events, com-
mands, and time synchronization information in ways that realize mutual operation
among devices. The ICs for interface conversion are referred to as interface conver-
sion ICs. Protocol converter electronics [48] has broad applications in electricity
generation, transmission and distribution of electricity, oil and gas, automation,
public utility, remote monitor, and control.
Interface conversion ICs (or converters) include the following categories: ①
Specific interface conversion chip works to enable seamless connections among
various customer electronics, commercial computers, and commercial multimedia
devices, such as ST Mystique Series DisplayPort and HDMI interface converter. ②
Special interface conversion chips are used as a specific network processor. It tends
to convert network data format into general data format based on TCP/IP protocol.
③ Embedded network protocol chip works to realize interface conversion by
employing protocol conversion function of the embedded system. It operates in
two ways, viz. by processing software directly and by hardware chip from hardening
of software, such as ARM’s embedded system. ④ Network control chip and single
MCU chip, which can be functionally expanded according to various demands.
With main applications in network protocol conversion, interface conversion ICs
are connected to host computers with various high laver protocols for mutual
collaboration that realizes distributed applications [49]. At present, the circuit is
categorized into E1/Ethernet protocol converter, RS-232/485/422/CAN converter,
RS-232/USB converter, and protocol converter based on field bus. For instance,
Silicon Laboratories’ CP2102/CP2103 tends to realize mutual conversion between
RS-232 protocols and USB protocols. Protocol converter or interface conversion ICs
are capable of realizing connectivity between various technology standards. When
updating, reforming, and restructuring existing communication, users can apply the
circuit into original applications to enable multipoint networking of standards and
telecommunication with no necessity to rewrite original communication software.

Controller Area Network Bus

Controller area network (CAN) bus is a bus standard, initially designed to commu-
nicate between the microcontroller and device, used in automobiles, without a host.
CAN bus is an ISO international standardized serial communication protocol,
featuring high performance and high reliability. It is one of the most widely used
field buses.
In 1986, Robert Bosch GmbH (or Bosch) of Germany first proposed the CAN bus
technology [50], and officially released at the Society of Automotive Engineers
(SAE) conference in Detroit. The first CAN controller chip produced by Intel and
Philips was launched in 1987. The 1988 BMW 8 Series is the first vehicle to be
produced on a CAN bus-based multiroute system. Subsequently, the CAN bus
264 Y. Guan et al.

technology is certified to ISO 11898 (the 2003 standard was updated in 2015)
standard [1] and ISO 11519 (vehicle area network, VAN) standard [51].
The CAN controller converts the transceiving information into a compliant CAN
frame on the bus via the CAN transceiver. The CAN controller chip can be a stand-
alone chip or a chip containing a microcontroller. The CAN transceiver is the
physical interface between the CAN protocol controller and the CAN bus, which
has a level-shifting function that converts digital protocol information into analog
signal communication.
In automotive electronics, the CAN bus is often used in key areas such as engine
control, ABS systems and airbags, and those important parts to guarantee car safety
[52]. Therefore, the CAN bus system has strict requirements on electromagnetic
interference (EMI) and electrostatic discharge (ESD) standards. It is necessary to
ensure that the system is not affected by external interference or interfere with the
normal operation of other electronic components. In addition, for some devices used
outdoors, the CAN bus interface also needs to use a large current surge protection
circuit to improve system protection. CAN bus is also widely used in the fields of
train, aviation, ship, building, medical equipment, machinery manufacturing, traffic
management, etc., due to its high reliability, real-time performance, and flexibility.
These unique technical features, such as a wide range of applications, and as an
international standard, have further promoted the rapid development of CAN bus.

Inter-Integrated Circuit Bus

In 1982, Philips Semiconductor (now NXP) developed a two-wire, synchronous,

multimaster, multislave, packet-switched, single-ended, and serial computer bus,
which is called inter-integrated circuit (I2C, I2C, or IIC) bus [53]. The I2C bus is
used for the communication connection between integrated circuits.
The I2C bus supports IC connections from any manufacturing process (nMOS,
CMOS, bipolar) devices. The I2C bus has two bidirectional signal lines, a serial data
line (SDA) and a serial clock line (SCL), which are connected to the power supply
through a current source or pull-up resistor. When the bus is idle, both SDA and SCL
are pulled high, as shown in Fig. 14.15. The typical supply voltage VDD1 is +5 V or

Fig. 14.15 Multisupply voltage devices sharing a I2C bus

14 Analog and Mixed-Signal IC Products 265

+3.3 V. It also allows other supply voltages (VDD2/VDD3) to be used. Devices with
different supply voltages can share the same bus. The I2C serial bus has fewer
connections and a simpler structure, thus greatly simplifying the hardware design
and reducing power consumption of the system.
Usually, I2C bus is divided into low-speed mode (10 kbit/s), standard mode
(100 kbit/s), fast mode (400 kbit/s), and high-speed mode (3.4 Mbit/s) according
to different data transmission speeds, among which fast mode and high-speed mode
are more widely used in embedded systems. The I2C bus is a multimaster bus with
multiple devices with the ability to control the bus. With SDA and SCL, the host
(usually a microprocessor) can control the transfer of data on the bus; each device
connected to the I2C bus is assigned a unique address that the host addresses and
communicates with.
Simple interface mode and efficient transmission rate make the I2C bus widely
used in the field of microelectronic communication control, with a wide variety of
related products. For example, the I2C bus is used for buffers, repeaters, hubs, and
expanders in addition to audio and video chips. The I2C bus can also be used for
level shifters of different power supply voltages and communication channels for IC
sensors. Besides, a large number of I2C buses are used in smartphones. The
improvement and expansion of the I2C bus have greatly facilitated the development
of the bus. For example, Intel, NEC, TI, ST, etc., have also developed some similar
standards. Intel defined the system management bus (SMBus or SMB), a subset of
the I2C bus, in 1995; SMB [54, 55] is most commonly found in computer mother-
boards for communication with the power source for on/off instructions.

High-Frequency Tuner

The high-frequency tuner is mainly used to tune the received TV signal, that is, to
select, amplify, and convert the video signal received by the antenna, which is the
forefront circuit of the TV signal channel.
The block diagram of the high-frequency tuner circuit is shown in Fig. 14.16. It
includes VHF (very high-frequency) tuner and UHF (ultra-high-frequency) tuner to

Fig. 14.16 Block diagram of the high-frequency tuner circuit

266 Y. Guan et al.

Table 14.5 Classification of high-frequency tuner

Divided by tuning method
Mechanical high-frequency tuner
Electronic high-frequency tuner
Divided by the range of receiving TV channels
VHF high-frequency tuner
UHF high-frequency tuner
Ordinary full-channel high-frequency tuner
Cable TV full-channel high-frequency tuner

process signals in different frequency bands. The VHF tuner includes input circuit,
high-frequency amplifier, local oscillator circuit, and mixer circuit. The UHF tuner
includes input circuit, high-frequency amplifier, and frequency conversion circuit.
The working principle of the two tuners is basically the same, receiving high-
frequency television signals of different channels from the antenna, selecting the
television channel through the input circuit, and suppressing interference of adjacent
channels and other signals; after frequency selective amplification, mixing with the
local oscillator signal, and finally, the IF (intermediate frequency) TV signal is
output through the UHF intermediate amplifying circuit. Since the high-frequency
tuner is susceptible to electromagnetic interference, the high-frequency tuner is
usually placed in a metal box to shield electromagnetic interference.
The high-frequency tuner can be divided into mechanical high-frequency tuner
and electronic high-frequency tuner according to different working modes, as shown
in Table 14.5. Regardless of tuning method, the tuning parameters of the input
circuit, the high-frequency amplifier, and the local oscillator circuit must be changed
together to switch the TV channel. Depending on the application, common elec-
tronic high-frequency tuners have antenna high-frequency tuner, HDTV ATSC
(Advanced Television Systems Committee) high-frequency tuner for watching
high-definition digital TV, radio high-frequency tuner such as FM (frequency mod-
ulation, 88–108 MHz) radio tuner, TV high-frequency tuner card (for watching TV
on computer), and TV digital network high-frequency tuner [56, 57].
As the front-end component of the TV signal channel, the high-frequency tuner
plays a decisive role in the performance of the whole machine. There should be
several aspects to be noted in the design process: first, to achieve impedance
matching with antennas, feeders, and amplifier circuits; second, to achieve higher
power gain and smaller noise figure, while stronger automatic gain control capability
of high-frequency amplifier; third, its local oscillator frequency is stable and has a
proper pass band with good selectivity. With the development of technology, circuit
integration and reliability requirements are getting higher and higher. High-
frequency tuner is also made more sophisticated with more excellent performance.

Digital Video Broadcasting Modulation/Demodulation

Digital Video Broadcasting (DVB) is an internationally recognized standard for

digital television broadcasting, maintained by the DVB Project [58]. The DVB
Project is an international industry consortium with more than 300 members,
14 Analog and Mixed-Signal IC Products 267

initiated by Joint Technical Committee (JTC) of European Telecommunications

Standards Institute (ETSI) [59], European Committee for Electrotechnical Standard-
ization (French for Comité Européen de Normalisation Électrotechnique,
CENELEC), and European Broadcasting Union (EBU).
Compared to traditional analog TV transmission systems, the DVB standard is
used in television transmission systems using all-digital technology for communi-
cation. The main components of the DVB standard include data scrambling, error
correction coding, digital modulation, equalization and synchronous clock extrac-
tion, as well as baseband interfaces, baseband filters, and IF filtering. The core
technologies of the DVB system are error correction coding, digital modulation,
and echo equalization. Digital modulation includes quadrature phase-shift keying
(QPSK), quadrature amplitude modulation (QAM), and orthogonal frequency-
division multiplexing (OFDM).
The DVB standard is a general-purpose digital television system specification
based on the conversion of different transmission methods. The transmission of
DVB digital video broadcasting system mainly transmits through cable
(corresponding standard is DVB-C/C2) [59], satellite (corresponding standard is
DVB-S/S2), and terrestrial wireless (corresponding standard is DVB-T/T2). The
main difference between these transmission methods is the different modulation
schemes used for different applications. (1) Digital Video Broadcasting—Cable
(DVB-C) that uses VHF/UHF carrier and QAM (16-QAM, 32-QAM, 64-QAM,
128-QAM, or 256-QAM) modulation, with cable TV networks as transmission
medium, has a wide range of applications. (2) Digital Video Broadcasting—Satellite
(DVB-S) uses SHF carrier and QPSK, 8-PSK, or 16-QAM modulation. Compared to
DVB-S, DVB-S2 [60] has more modulation modes like QPSK, 8-PSK, 16-APSK, or
32-APSK. With satellite as the transmission medium, DVB-S2 is designed for the
transmission characteristics of satellite signals which meet the bandwidth require-
ments of satellite transponders. This type of transmission has a wider coverage and a
larger number of programs. (3) Digital Video Broadcasting—Terrestrial (DVB-T)
uses VHF/UHF carrier with combined modulation method of 16-QAM or 64-QAM
(or QPSK) and coding orthogonal frequency-division multiplexing (coded OFDM,
C-OFDM) [61] and also can support layered modulation. Four sets of TV programs
can be transmitted in 8 MHz bandwidth, with high transmission quality, and are well
covered in local area. It has outstanding advantages in the mixed transmission with
the current analog TV. The block diagram of DVB transmit and receive system is
shown in Fig. 14.17.
DVB transmitter encodes then multiplexes audio and video signals and finally
transmits the modulated RF signal. DVB receiver implements the opposite working
process of the transmitter, receives the RF signal for demodulation, de-multiplexes,
and finally decodes completing the reception. Since different digital video broad-
casting systems correspond to different modems, demodulator chips integrated with
digital cable broadcasting system standards (DVB-C), digital satellite live broad-
casting system standards (DVB-S), and digital terrestrial broadcasting system stan-
dards (DVB-T) have been produced. The chip is implemented in small size and
multistandard demodulation scheme, which simplifies hardware and software
268 Y. Guan et al.

Fig. 14.17 Block diagram of DVB transmitting and receiving system

design. In addition, the integration of multistandard protocols in one chip reduces the
number of pins, thereby reducing the number of peripheral components and provid-
ing a highly integrated system solution.

Mobile Communication IC

Though not all cell phones are mobile, people today use “mobile” and “cell”
interchangeably as mobile or cell phones have the same features. Mobile communi-
cation network connects the terminals and network devices through a wireless
channel in cellular wireless networking manner to perform information exchange
between mobile users. Terminal mobility is the main feature of mobile communica-
tion networks. It can be used for handoff and automatic roaming across local
networks to transmit voice, data, video images, etc. [62].
The progressing of mobile communication networks drives the development of
communication ICs, toward higher integration, faster speed, more functions, and
lower power consumption. Core IC in the mobile terminal includes radiofrequency
(RF) IC and baseband IC. The RF IC is used for implementing RF transceiver,
frequency synthesis, and power amplification; the baseband IC is responsible for
signal processing and protocol processing, synthesizing the baseband signal for
transmission, and decoding the received baseband signal. In addition, power man-
agement and multimedia processing ICs are also important parts of mobile terminals.
The third-generation (3G) mobile communication technology combines wireless
communication with multimedia communication such as the Internet, which can
process various media forms such as images, music, and video data streams.
14 Analog and Mixed-Signal IC Products 269

Compared with the previous two generations (1G, 2G), the data transmission speed
of the third-generation mobile communication network is relatively fast, and data
communication bandwidth is generally above several hundred kbit/s [63], so the IC
chips are required to have strong data storage and processing abilities. Qualcomm
RF and baseband ICs are technologically advanced in the industry, and they have a
monopoly on code-division multiple access (CDMA) technology patents. Infineon,
Maxim, Freescale, MediaTek, Broadcom, and other companies have also launched
their own mobile phone RF transceiver and baseband chip solutions.
The fourth-generation (4G) mobile communication technology that combines 3G
technology with WLAN enables high-quality video image transmission and faster
data transmission rate. The typical download rate is 15 Mbit/s (4G, LTE Cat4) and
can reach 90 Mbit/s (4G+, LTE-Adv Cat16), which basically meets the requirements
of all users for wireless transmission applications. The requirements of the 4G
system for communication ICs have also increased accordingly. HiSilicon IC design
at Huawei has increased the market share of domestic 4G mobile phone chips. The
performance of HiSilicon Kirin 960 chip has reached the same level as Qualcomm
Snapdragon 820; HiSilicon’s Kirin 980 (2019) has announced with world-leading
performance. Table 14.6 shows the comparison of 1G–5G wireless communication
methods, typical data rates and year of implementation.
With the rapid development of smart terminal technology, mobile data traffic has
increased dramatically. In addition to 1G adopting analog mode of wireless mobile
communication, the existing wireless 2G–4G digital communication technology has
continuously improved the transmission speed. HD video such as VR, AR, and
smart home propose higher requirements on the transmission speed of the fifth
generation, 5G, mobile communication [64]. For 5G, some upload speed has reached
60 Mbit/s (suitable for 8K UHD) and expected to be 100 Mbit/s whenever needed,
and the download speed is 1 Gbit/s and peak to be 20 Gbit/s. It is the worldwide
interest and activity to promote 5G networks, and major semiconductor companies
are investing heavily on 5G communication ICs [65].

Table 14.6 Comparison of 1G–5G wireless communication methods

Technical System Upload rate, Enabled
generation technology download rate time Feature
1G AMPS (Analog) 14.4 kbit/s, 14.4 kbit/s 1970 Voice only
2G GSM, TDMA, 9.6 kbit/s, 14.4 kbit/s 1990 Data and voice
CDMA
2.5G GPRS, TDMA 9.6 kbit/s, 115 kbit/s 2001 Internet access
3G WCDMA, 64 kbit/s, 2 Mbit/s 2004 Cell phone and
CDMA2000 PDA
3.5G HSDPA, HSPA 384 kbit/s, 14.4 Mbit/s 2006 Higher data
rates
4G WiMax, LTE, 8 Mbit/s, 20 Mbit/s 2012 Supports HD
Wi-Fi video
5G 5G NR, Wi-Fi 60 Mbit/s, 1 Gbit/s 2019 Supports FR1,
FR2
270 Y. Guan et al.

Audio Codec IC

An audio codec is a device or program that is capable of encoding or decoding audio

data streams. The IC for audio codec often appears as an IP design, viz. IP audio
codec. The audio codec can represent high-fidelity (Hi-Fi) audio signals with a small
number of bits while maintaining audio quality, effectively reducing the storage
space and the bandwidth required for transmitting audio files. Audio codecs are
widely used in smartphones and multimedia phones, digital cameras and digital
video cameras, portable media players and portable audio players and telephone
accessories.
In the implementation of the hardware chip design, the audio encoding process
converts analog audio signals into digital information and performs encoding.
Besides, the audio decoding process decodes digital signals and converts them into
analog audio signals. That is, the audio codec contains analog-to-digital converters
(ADCs) and digital-to-analog converters (DACs) that operate at the same clock and
can be used for sound cards that support audio input and output.
Moving Picture Experts Group (MPEG) is a working group of the ISO. MPEG-1
is designed to compress VHS-quality raw digital video and CD audio down to
1.5 Mbit/s (26:1 and 6:1 compression ratio, respectively). The MPEG-1 technology
has made video CDs, digital cable and satellite TV, and DAB possible. The best-
known part of MPEG-1 is perhaps the MP3 audio format.
Audio coding includes the following technologies: (1) MPEG-1 (VCD), which
mainly solves multimedia storage problems, is a lossy data compression method
[65]; (2) MPEG-2 (DVD), whose development can be divided into three phases as
increased low sampling frequency for MPEG-1, multichannel extension for MPEG-
1 and Advanced Audio Coding (AAC) for MPEG-2 [66]; (3) MPEG-4 compression
efficiency is further improved, with better interactivity, and it can store and transmit a
variety of audio contents [67]; (4) AC-3 (Active Coding-3) [68], introduced in 1991,
is a multichannel encoding technology based on AC-1 and AC-2, all developed at
Dolby Laboratories. Among them, AAC (successor of MP3) [66] and AC-3
(or Dolby Digital, originally named Dolby Stereo) are high-fidelity, with high
sampling rate audio standards, which are mostly used in high-definition digital TV,
digital cinema, and other fields.
AC-3 is a 5.1 format, which means that it provides five full-bandwidth channels:
(1) front left, (2) front right, (3) center, (4) surround left, and (5) surround right.
There is also a low-frequency effect (LFE) channel included, known as the
subwoofer channel, for the sound needed for special effects and action sequences
in movies. ADI, Cirrus Logic, IDT, and Maxim Integrated are audio codec IC
providers. Some of the products available are using audio codec IC, VoIP
technology-based phones, digital and analog media servers, and gateways. Other
audio codec IC products include wearables such as smart watch, home speaker, or
media player [69].
14 Analog and Mixed-Signal IC Products 271

Video Codec

A video codec is a circuit or software that compresses and decompresses digital

videos. Codec is a concatenation of “encoder” and “decoder.” The original videos
were stored on tape as analog signals, and with the advent of optical disks, digital
form storage gradually replaced analog form storage. Since recording and transmit-
ting raw videos require a very large amount of storage and bandwidth, there is an
urgent need for a method to reduce the amount of data used to represent original
videos, whereby a solution for compressing digital video data came into being, and
some related technologies were also been developing. The format of compressed
data is in accordance with the video compression specification. Usually, the com-
pression is lossy, that is, the compressed video loses some information existing in the
original video. Since there is not enough information to accurately reconstruct the
original video, the decompressed video quality will be lower than the original
uncompressed video quality. There are more complex relationships among video
quality, the amount of data used to represent videos, the complexity of encoding and
decoding algorithms, the sensitivity to data loss and errors, the ease of editing,
random access, and end-to-end latency.
Common video encoding methods are H.26X series (including H.261, H.262,
H.263, H.264, and H.265), MPEG series (MPEG-1, MPEG-2, MPEG-4), and other
encoding methods such as AMV and AVS. There are many types of software video
codec on personal computers and consumer electronics, and users can install mul-
tiple video codecs on these devices to meet different needs. Video codecs are widely
used in DVD/VCD playback, video recording, video broadcasting, and other
applications.
MPEG was established in 1988 by the initiative of Hiroshi Yasuda (Nippon
Telegraph and Telephone) and Leonardo Chiariglione. The first MPEG standard
was MPEG-1. It provides the video resolution of 352
240 at 30 fps (frame per
second). The quality of MPGE-1 is lower than VCR (video cassette recorder).
Released in 1997, MPEG-2 is used on DVD and supported by Blu-ray disk; it
provides the resolution of 720
480 and 1280
720 at 60 fps. MPEG-3 was
designed for HDTV but was abounded and incorporated into the MPEG-2. Stan-
dardized in 1998, MPEG-4 has a higher video quality than its precedents. The well-
known MP4 video file is related to MPEG-4. MPEG-7 was standardized in ISO/IEC
15938, and it is a multimedia content description standard. There is also MPEG-21
for digital data processing and creating a dynamic and interactive multimedia format.
IC design for video codec-based technology is usually in the form of various IP
designs [70]. These IP products are offered for processing HEVC (High-Efficiency
Video Coding, known as H.265), IP for UHD (4K 60 fps), VCU (Video Codec Unit),
24bit Audio ADC/24bit Video DAC, etc. For images of multimedia and the related
interface technology, separate MIPI standards are to be followed; typical MIPI IP
includes MIPI controller and MIPI PHY [71].
272 Y. Guan et al.

Power Line Communication (PLC)

Power line communication (PLC), also known as power line carrier communication,
is a communication technology that uses power lines as a transmission medium [72].
The PLC technology can make full use of the extensive line resources of the power
distribution network to transmit data on power lines of different voltage levels such
as high-voltage power lines (35 kV and above), medium-voltage power lines (10 kV
class), or low-voltage distribution lines (380 V/220 V). The PLC technology trans-
mits data by loading the modulated high-frequency signal on the transmission
current, transmits the signal to the receiving end, and then filters and demodulates
to recover the original signal, thereby realizing information transmission.
PLC technology can be divided into broadband over power line (BPL) commu-
nication technology and narrowband over power line (NPL) communication tech-
nology. (1) BPL communication bandwidth is generally limited to 2–30 MHz, the
communication rate 1 Mbit/s or more. Nowadays, spread spectrum communication
techniques of which OFDM as the core are widely used, and a broader bandwidth
provides a wider development space for a variety of broadband data services and
broadband markets. (2) The NPL communication bandwidth is limited to
3–500 kHz, and the communication rate is lower than 1 Mbit/s. The common PSK
(phase-shift keying) technology, DSSS (direct-sequence spread spectrum) technol-
ogy, and chirp technology are mainly used to control communication with the data
acquisition network, which can satisfy the communication requirement of low data
volume well, with a low cost and easy to implement.
The PLC chip is a two-way transmission system composed of modules such as a
modulator, an oscillator, a power amplifier, a T/R (transmit/receive) switch, a
coupling circuit, and a demodulator. When transmitting data, the oscillator provides
carrier signals to the modulator, and data signals modulated by the modulator are
amplified at the amplifier stage and loaded onto the power line through the T/R
switch and the coupling circuit. When receiving data, modulated signals enter the
demodulator via the coupling circuit and the T/R switch, and demodulated and
extracted raw data signals are sent to the digital device received by the next stage.
PLC can convert a common power grid into a communication network, enabling
smart grid connections including the connection of smart meters, smart homes,
automated monitoring, and streetlight monitoring.
At first, power companies could only transmit data on the power line at a speed of
1 Mbit/s. With the maturity of PLC technology, PLC of 2 Mbit/s, 14 Mbit/s, and
45 Mbit/s bandwidths has gradually spread. PLC technology is also moving toward
higher speed to above 200 Mbit/s. For the domestic grid environment, it needs to
optimize the SoC design of the power line communication. For example, the analog
front-end (AFE) design of the power line modem becomes very challenging. In
addition, because the power line produces noises, these factors need to be considered
in the architecture design to ensure data reliability. At the same time, developers need
to optimize the design for different applications and working environments and
comply with relevant protocol standards and modulation schemes. PLC products
14 Analog and Mixed-Signal IC Products 273

are available from several companies [73–76] worldwide, including various

PLC-related products and applications.

Digital Subscriber Line (DSL)

Digital subscriber line (DSL) technology is a digital communication technology

based on ordinary telephone lines, which can transmit voice and data signals on the
same telephone line. DSL mainly includes ISDN DSL (IDSL), high-speed DSL
(HDSL), symmetric DSL (SDSL), asymmetric DSL (ADSL), rate-adaptive DSL
(RADSL), and very high bit rate DSL (VDSL), etc., which are collectively called
xDSL technology [77]. Since DSL technology can achieve a downlink transmission
rate of 100 Mbit/s (VDSL2+) on a common telephone twisted pair, it is widely used
in digital broadband communication because it meets the requirements of low cost
and high bandwidth and can be used as a supplement to the passive optical network
(PON). DSL can achieve high-speed digital data transmission on ordinary analog
telephone lines by using high signal transmission frequency and specific modulation
technology on twisted-pair copper lines. There are four kinds of code modulation
and demodulation methods: 2B1Q, QAM, CAP, and DMT.
Since DSL technology needs to be separately modulated and demodulated at both
ends of the transmission line, xDSL ICs take the form of a chipset solution in
practical applications. The xDSL chipset mainly includes the analog part and the
digital part: The main function of the analog part is to transmit and receive data
signals, through analog front end (AFE) and lines drivers, and digital-to-analog
conversion, analog-to-digital conversion, anti-aliasing, signals filtering, gain con-
trolling, lines driving, and other functions are implemented. The digital part is
mainly composed of framer/mapper module, DSP module, microprocessor core,
and other functional modules to realize DSL frame structure processing, data
encoding, communication schedules controlling, and other functions. DSL and its
related ICs include modems or routers or a modem/router combo; these modems/
routers can connect to work with copper wires at the input; the output can be a data
wire(s) or wireless—the latter has become much more common today.

Passive Optical Network and Cable Modem

Optical fiber communication is a communication method for transmitting optical

wave signals by using optical fibers, which has the advantages of wide transmission
frequency band, large communication capacity, strong anti-electromagnetic interfer-
ence capability, small signal attenuation, and high transmission quality. Besides, it is
one of the main technologies of modern communication. The currently widely used
fiber-optic communication system is a digital code–intensity modulation–direct
detection system, which consists of a light transmitting part (a light source and an
optical transmitting end), an optical transmitting part (an optical fiber and an optical
274 Y. Guan et al.

repeater) and a light receiving part (a light receiving end, a light detecting and a
converting module). The optical transmitting end converts data electrical signals into
optical signals of light intensity modulation, sends them to the optical fiber, and
transmits optical signals to the optical receiving end through the optical fiber. Then
optical signals are detected and converted into an electrical signal by the receiver and
demodulated to recover the original data information [78].
With the development of high-speed Ethernet, passive optical network (PON) has
become a key technology for broadband access. PON is mainly divided into APON
(Asynchronous Transfer Mode PON, ATM PON, i.e., earlier ITU-T G.983 standard),
GPON (Gigabit PON), and EPON (Ethernet PON). Chips design companies are
introducing ICs for new-generation PON network equipment, striving for high
integration and providing cost-effective solutions for system vendors to achieve
the lowest system cost. The ITU-T G.987 standard defines that the downlink
transmission rate of GPON is 10 Gbit/s, and the uplink transmission rate is
2.5 Gbit/s; according to the IEEE 802.3av and IEEE 802.3ah technologies, EPON
can simultaneously achieve two downlink transmission rates of 10 Gbit/s and 1 Gbit/
s. The transmission line on the PON server consists of an optical line terminal (OLT)
and multiple optical network units (ONUs), or optical network terminals (ONTs) at
the customer premises. The IC requirements corresponding to GPON/EPON include
the OLT chips at the service center, the ONU/ONT chips at the user end, and the relay
chips of the optical transport network (OTN).
Coaxial cable communication is a wired communication method. The coaxial cable
is composed of some coaxial tubes. The common specifications are 2, 4, 6, 8, 12, 18,
and 22 pieces of wire, which can be divided into small coaxial, medium coaxial, and so
on. The coaxial cable has good transmission quality, small loss, and large capacity
during transmission. Coaxial cable communication is mainly used for long-distance
trunk line communication, which plays an important role in long-distance news
communication trunk lines that require high-quality transmission and multiple service
transmissions. Cable modem is used to modulate a certain transmission band of cable
TV. The data to be transmitted is first transmitted through the cable television network,
and cable television signals are sharing communication medium [79]; after reaching
the receiving end, it is demodulated by the cable modem, and the transmission rate can
reach 10 Mbit/s or more. Cable modem can be divided into two-way symmetric
transmission and asymmetric transmission, one-way data transmission and two-way
data transmission, synchronous and asynchronous. There are also external form, built-
in from, and interactive set-top boxes of its appearances.

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Radio Frequency IC Products
15
Bo Wang, Yan Li, and Xin-An Wang

Contents
RF and Microwave IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Radio Frequency Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Low-Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
RF Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
RF Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
RF Duplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
RF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Microwave Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Millimeter Wave Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Terahertz Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Radio (Receiver) Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Navigation Receiver IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Wireless Fidelity Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Bluetooth Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
ZigBee Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Radio Frequency Identification Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Abstract
RF CMOS products are in principle part of analog, mixed-signal IC products; RF
ICs together with analog, mixed-signal contribute to about 15% of the total
semiconductor products in the global market. In engineering practice, due to
the specific nature, such as RF products in general operating at much higher
frequency of 500 MHz and up to today’s 300 GHz, RF IC products are therefore
listed in a separate catalog. Widely used in wireless communications (e.g.,

B. Wang · X.-A. Wang

Electronic and Computer Engineering, Peking University, Shenzhen, China
Y. Li (*)
Shenzhen University, Shenzhen, China
e-mail: liyan@szu.edu.cn

© Publishing House of Electronics Industry 2024 279

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_15
280 B. Wang et al.

cellular networks, Bluetooth, ZigBee, Wi-Fi, GPS, etc.), RF IC products are

commonly found in applications of mobile phones, IoT networking (e.g., RF
ID), automotive radar, and many others. Typical RF CMOS IC includes RF power
amplifier (PA), RF switch, low-noise amplifier (LNA), RF Mixer, Oscillator,
Duplexer, and Filter; other RF products include microwave (MW) devices, mil-
limeter (MM) wave devices, and terahertz (THz) devices. This chapter introduces
commonly used commercial RF CMOS IC products and RF devices, their basic
functions, features, applications, and some typical product names.

Keywords
RF IC · Wi-Fi · RF PA · LNA · Wireless communications

RF and Microwave IC Products

Radio frequency integrated circuits (RFICs) have been developed quickly since
1990s and become the main-stream RF products by replacing discrete RF devices
gradually. RFICs and microwave ICs are found in the household, offices and
industry applications, connection of the computers, mobile phones, electrical appli-
ances, TVs, intelligent home, digital cameras, printers, projectors, etc.; and also enter
the domain of municipal facilities and environment monitoring, such as noncontact
payment, borrowing book at open library, building and frontier security monitoring,
etc. On one hand, this benefits from the cost down due to the CMOS technology
scaling, the main stream technology node advanced from 0.5 μm node (middle
1990s) to 130 nm node (2005), down to 16/14 nm node (2015). Due to the cost
down, RFIC (e.g., Bluetooth, Wi-Fi, navigation chips) enters little by little into the
civic applications in our daily life. On the other hand, the performances of CMOS
technology have increased dramatically, approaching and even overpass the discrete
devices or the III/V (element materials) devices. For example, the noise perfor-
mances of the early CMOS devices were poor; they could not meet the strict
requirements of the wireless communications, so only the more expensive III/V
devices could be used. After 2000, as the technology evolved, the noise perfor-
mances of the CMOS devices gradually achieved the strict requirements of the
wireless communications and became main-stream products.
Besides, the frequency of the RFIC increases continuously, from 500 MHz in the
middle 1990s to 70 GHz at the beginning of 2000s, and up to 300 GHz in 2017. The
applications of RFIC cover the frequency band of below 10 GHz, (e.g., 2G/3G/4G
communication, navigation, Wi-Fi, RFID, Bluetooth), and the frequency band above
10 GHz (e.g., millimeter wave and THz applications) for broader applications.
As the CMOS integration density increases and the chip size decreases, it appears
that RFIC products can integrate multiple functions on a single chip. For example, in
the wireless communication domain, the multimode multiband chips can be com-
patible with different communication systems. As more functions integrated in a
single chip, the design of RFIC is also increasingly challenging.
15 Radio Frequency IC Products 281

The main RFIC products include the following.

1. Radio Frequency IC Module: including the power amplifier (PA) which

amplifies the output power, the low-noise amplifier (LNA) which amplifies the
weak input signal and suppresses the noise, the mixer which up-convert or down-
convert the RF signal, the oscillator which provides the high-frequency low-noise
clock signal, the duplexer which separates the reception and transmission signals,
and the filter which removes the signals with different frequency band, etc.
2. RF Devices: including the microwave devices, millimeter devices, and THz
devices.
3. RF Integrated Chips: including the radio chips, navigation chips, Wi-Fi chips,
Bluetooth chips, Zigbee chips, RFID chips, NFC chips, etc.

Radio Frequency Power Amplifier

In 1996, Motorola successfully demonstrated an integrated power amplifier circuit

on a silicon substrate based on GaAs and bipolar technology. Currently, GaAs is the
most widely used and mature technology.
PA is widely used in wireless communications and audio-driven applications, etc.
Radio Frequency Power Amplifier (RF PA) can transform low-power RF signal
into high-power signal, i.e., through amplifying small RF signal to produce a large
output power. Basic applications of RF PA include driving another high-power
signal source, transmitting antennas, and stimulating a microwave cavity resonator,
among them driving antenna load is the most common [1].
According to the difference of the conduction angle of the device, PA can be
categorized under Class-A, Class-B, Class-AB, and Class-C. A typical Class-A PA is
illustrated in Fig. 15.1. A typical power amplifier consists of input matching
network, transistor amplifier circuit, impedance conversion network, DC bias, and
output impedance matching network. The load of Amplifier circuit is usually
replaced by large inductance for enlarging the output range at constant supply

Fig. 15.1 A typical Class A

RF PA circuit
282 B. Wang et al.

voltage. In order to reduce the peak voltage of the output transistor and improve
efficiency, a matching network is inserted between the amplifier and the output load
in order to reduce the load resistance and thus transmit the power under lower output
swing.
The indices of RF PA performance mainly include:

1. Output Power
2. Efficiency: (a) Drain Stage Efficiency Pout, (b) PAE (Power Added Efficiency)
3. Power Gain
4. Linearity, which includes: 1 dB Compression Points; IP3 (Third-order Intercept
Point), and ACP (Adjacent Channel Power Ratio)

The additional power amplifier’s linearity and PAE, the range of which is between
10% and 60% have been the critical technology for PA and the key focus and hotspot
of research. Currently the technology of enhancing linearity is mainly including
feedforward, predistortion, power back-off, EER (Envelope Elimination and Resto-
ration), LINC (Linear Amplification of Nonlinear Components), and Doherty
amplifier.
According to the performance, based on the work modes (linear or constant
envelope), PAs are classified to linear PA and switch mode PA. Linear PA
(Class A, B, AB, and C) has lower efficiency yet broader applications; switch
mode PA (Class D, E, F) is an efficient nonlinear PA. In ideal condition, it can
achieve 100% power efficiency. Driven by overdrive voltage, the output transistor is
equivalent to an ideal switch, so that the transistor current waveform and voltage
waveform will not overlap and improve the output efficiency. Performance of each
type of PA is compared, as shown in the Table 15.1 below.
With the development of the submicron CMOS technology, the characteristic
frequencies of CMOS devices are greatly increased, RF PA in CMOS technology
will be more prevalent as driven by the market [3].

Table 15.1 Performance comparison among different types of RFPA [2]

Type of Class A AB B C D E F
Working mode Current Current Current Current Switch Switch Switch
source source source source
Conduction 2π π~2π π 0~π π π π
angle
Output power Medium Medium Medium Low High High High
Theoretical 500% 50%~78.5% 78.5% 78.5%~100% 100% 100% 100%
efficiency
Typical 35% 35%~60% 60% 70% 75% 80% 75%
efficiency
Gain Low Medium Medium Low Low Low Low
Linearity Super Good Good Bad Bad Bad Bad
Drain voltage 2Vdc 2Vdc 2Vdc 2Vdc 2Vdc 3.6Vdc 2Vdc
peak value
15 Radio Frequency IC Products 283

Low-Noise Amplifier

The low-noise amplifier (LNA) effectively amplifies the signal while contributing
very low noise. It is generally applied to the front of the signal receiving branch of
the radio receiver and amplifies the received weak signal for later processing. LNA
has a broad range of applications, such as high-sensitivity electronic detection
equipment, radar systems, near-field communication, satellite communication cards.
The factors that affect LNA are Noise Figure (NF), gain, input inflection loss,
stability, bandwidth, and power consumption. Since the noise figure generated by the
amplifier is directly superimposed on the input signal, it will severely interfere with
the input signal. It is necessary to reduce the noise and improve the signal-noise ratio
to improve the ability to suppress noise. The NF is defined as NF ¼ SNR SNRin
out
, where
SNRin is the input signal-noise ratio, SNRout the output signal-noise ratio. The noise
level of the amplifier cannot be zero, so the output noise is always greater than the
input noise.
The circuit of LNA connected to the input signal and it is equivalent noise model
are shown in Fig. 15.2a, b, where AV is the gain of LNA, U 2n,RS is the thermal noise of
antenna. U 2n is the output noise of LNA.
One can reduce NF of circuit by increasing the circuit gain, but this method
usually decreases the linearity. Since LNA does not have a large effect on the
linearity of the receiver in most applications, its linearity is rarely considered in
design. The input reflection loss of the low-noise amplifier, that is, the matching
degree of the input resistance, is defined as the ratio of the reflected power to the
incident power.

2
zin  Rs
Γ¼ ,
zin þ Rs

where RS is the equivalent signal source impedance, zin is the equivalent input
impedance of LNA, in unit of dB. The lower the input reflection loss, the better
will be, which requires the input impedance to match the source impedance as much

Fig. 15.2 Low-noise amplifier circuit and equivalent noise model

284 B. Wang et al.

as possible. LNA usually trades off the Noise Figure and Power consumption during
design.
The main topology of LNA can be divided into common source, common gate,
and broadband topologies [1].
With the development of CMOS technology and the improvement of high-
frequency performance, future LNA will develop in the direction of low-power
consumption, high gain, and wide bandwidth [4].

RF Mixer

RF Mixer or Frequency Mixer used in RF design is an important circuit in wireless

transceivers that performs frequency conversion through the nonlinear or time-
varying characteristics of the circuit itself. The main function of mixer is to convert
the RF signal received by the analog front-end of the receiver into a low-frequency
signal by down-conversion, and convert the low-frequency signal of the analog
front-end of the transmitter into a RF signal by up-conversion. At present, mixers
have been widely used in radar, communications, radio and television, remote
sensing telemetry, and other fields.
The working principle of mixer is to multiply the two input signals in the time
domain to complete the addition and subtraction of the frequency in frequency
domain. When two sinusoidal signals ω1 and ω2 are input to the multiplier, an
output consisted of a sum frequency component (the frequency is ω1 þ ω2) and a
difference frequency component (the frequency is ω1ω2) can be obtained. There-
fore, the frequency is converted [5]. A mixer typically has two inputs (a local
oscillator input and a receiving or transmitting signal input) and an output port.
The symbols and functions are illustrated in Fig. 15.3.
Mixers can be divided usually into active and passive mixers [1] while active
mixers can be divided into double-balanced mixers, single-balanced mixers, and
unbalanced mixers. And passive mixers can be divided into mixers based on a single
CMOS switch, single-balanced passive mixers, and double-balanced passive mixers.
The single-ended CMOS mixer is the simplest mixer structure. It has two single-
ended inputs and mainly consists of three parts in circuit structure: switch stage,
transconductance stage, and load stage, as shown in Fig. 15.4. Single-ended CMOS
mixer is simple in circuits, but the isolation of the RF port and the LO (Local
Oscillator) input port causes loss of the RF signal, so the isolation of the circuit is
not high.

Fig. 15.3 Schematic of

symbols and function of a
mixer
15 Radio Frequency IC Products 285

Fig. 15.4 Schematic of

single-ended CMOS mixer

Fig. 15.5 Schematic of

double-balanced passive
mixer (Gilbert mixer)

The current commutated active mixer with double-balanced structure is shown in

Fig. 15.5. This type of mixer is characterized by its ability to effectively suppress
interference, useful intermodulation components, and provide a certain conversion
gain with better isolation. These excellent properties make them widely used in
wireless transceivers.
The main performance indicators of the mixer are noise figure (ratio of input
signal-to-noise ratio to output signal-to-noise ratio), conversion gain (ratio of output
signal to input signal), linearity (usually described by 1 dB compression point and
third-order intercept point and determines the maximum input signal), and port
isolation (the degree of interaction between the three ports in mixer) [6].
286 B. Wang et al.

In the future, how to implement high-performance mixer is a hot topic, and

the key to solving these problems lies in the innovation of circuit architecture
and the research and application of new semiconductor materials.

RF Oscillator

Oscillator is an electronic circuit used to generate periodic analog signals usually in

the form of voltage. Its main function is to generate an accurate reference frequency.
Oscillators are used in a wide range of applications, including wireless communica-
tions, sensors, computers, medical equipment, and other fields.
With self-sustaining mechanism, noise of a specific frequency inside the oscillator
will be amplified and finally a stable periodic signal is formed and output. Most
oscillators can be viewed as a feedback loop and analyzed in the perspective of
feedback. The oscillator feedback analysis is shown in Fig. 15.6. Its transfer function is

Uout ðωÞ H ðjωÞ

¼ :
U in ðωÞ 1  H ðjωÞ

If certain phase shift and loop gain conditions (Barkhausen conditions) are
satisfied, the feedback system can realize the output of a stable oscillating signal
with a specific frequency determined by its frequency selective network.
Oscillator implemented in CMOS circuits is typically ring oscillator (RO), LC
oscillator, and RC relaxation oscillator. Among them, RO is achieved by connecting
an odd number of inverters in series in a closed-loop feedback form, and the output
signal frequency is determined by the number of ring oscillator stages and the
inherent delay of the inverter. A simple three-stage RO circuit is shown in
Fig. 15.7. RO is very simple in circuit structure with a wide tuning range and
multiphase output. From a perspective of manufacturing, RO can be manufactured
in a standard CMOS process with a very small layout area. However, it is difficult for
a RO to obtain lower oscillation frequency and low frequency-temperature
sensitivity.
Passive resonant devices for LC oscillators include inductors and capacitors. By
connecting inductor L and the capacitor C in parallel, a LC oscillator is implemented
and will resonate at a frequency of p1LC. Cross-coupled oscillator is a typical LC

Fig. 15.6 Schematic of

feedback analysis of oscillator
15 Radio Frequency IC Products 287

Fig. 15.7 Schematic of a three-stage ring oscillator circuit

Fig. 15.8 Schematic of a LC

oscillator circuit

oscillator, as shown in Fig. 15.8. LC oscillator has excellent performance in high

output frequency, high quality factor, and low noise, but remains great challenges in
modeling the inductor device, increasing its narrow tuning range and decreasing the
large power consumption.
The performance indicators of an oscillator include mainly oscillation frequency,
quality factor Q (the higher the Q value, the better the frequency selection charac-
teristic), phase noise (the circuit output phase jitter caused by the device noise), and
frequency stability (the ability for an oscillator to maintain a constant frequency in
the long or short term) [7].
With the scaling of CMOS technology with lower chip voltage; how to design
and implement high-performance oscillators with low-power consumption, high
frequency, low noise, and large tuning range are hot research topics in future Internet
of Things (IoT) era. RF oscillators are commercially available [8, 9].
288 B. Wang et al.

RF Duplexer

Duplexers are used to isolate receiving and transmitting signals, so that receiving and
transmitting circuit modules can share one channel (a pair of antennas). The duplexer
is an important part of modern communication systems.
The main functions of Duplexers include: suppressing mutual interference
between receiving and transmitting signals; isolating frequency band, which
means that it can separate multiple frequency bands which are contained in one
signal source and, making impedance change so that signals can be transmitted with
maximum power [10].
In the 1960s, Matthaei and Cristal first proposed a duplexer integrated design
method for star-shaped common junctions. In the late 1970s, another method of
synthesizing common junction microwave duplexer was proposed by Haine et al. In
this method, channel filters are synthesized into dual-terminal filters. Since then,
duplexers have been studied extensively [11].
The duplexer is a three-port device (Fig. 15.9). The common terminal (port 1) is
connected with the external antenna, the transmitting side is connected with the
external transmitting module via the transmitting filter TX and port 2, and the
receiving side is connected with the external receiving module by the receiving filter
RX and port 3.
According to its working principle, duplexers can be divided into two types: time
division duplexer (TDD) and frequency division duplexer (FDD) [12].
A TDD uses the same frequency band to transmit and receive signals, but do not
transmit at the same time. TDD behaviors like a switch: when the signal is to be
transmitted, the receiving module is cut off; when the signal is to be received, the
transmitting module is cut off.
A FDD can process different frequency signals at the same time. The implemen-
tation method is using filters to separate the transmission and reception channels.
That is to say, two filters are tuned at the radio frequency rate and reception
frequency respectively so that the two filters can isolate the sending and receiving
ports and let the signals of the port pass through. There are three traditional methods
to realize this type of duplexer: ① adding a directional coupling loop between the
antenna and the two filters; ② tuning the circuit by using the admittance-elimination
circuit (or reactance-elimination circuit) attached to the public terminal, thereby

Fig. 15.9 General structure

of duplexer
15 Radio Frequency IC Products 289

reducing the mutual interference between the filters; and ③ the “fully complemen-
tary” duplexer, i.e., its input admittance (or input impedance) remains unchanged in
the full spectrum. It can effectively cancel the interference between two channels.
Frequency division multiplexing (FDM) is widely used [13] because of its higher
efficiency and better anti-jamming ability.
The traditional design methods mentioned above do not start from the overall
structure, but only consider the influence of each filter separately, so these methods
have limitations. At present, the mainstream of research is to find a more general
design method which can synthesize the characteristic polynomials of duplexers and
eliminate the influence among the filters. At the same time, the size of the duplexer is
decreasing, and its developing trend is modularization. The main design indicators of
duplexer are working frequency (the working frequency of duplexer should be larger
than the frequency band of sending and receiving modules), bandwidth (the respec-
tive bandwidths of transmitting and receiving bands), isolation degree (to measure
the isolation between transmitting and receiving ports), insertion loss (the attenua-
tion of useful signals in the corresponding passband of each port), the matching
impedance (duplexer should match the impedance of transmitting port, receiving
port, and antenna, usually 50Ω). RF Duplexer Products are commercially
available [14].

RF Filter

A filter can effectively remove signals outside the selected frequency band to obtain
the desired signal in the selected frequency band. The main purpose is to obtain or
eliminate the signal at a specific frequency. Filters are generally used for signal
transmission and processing, and have been widely used in aerospace, military,
medical, telecommunications, communications, machinery, energy, and other fields.
The original filter circuit is a passive circuit composed of a resistor, a capacitor, an
inductor, etc. The rapid development of modern high-tech information technology
and the improvement of the process of IC transistors are gradually promoting the
rapid development of various new filter circuits such as RC active filters and digital
filters.
The basic principle of a filter is to block or turn on a specific frequency signal in a
signal by utilizing the impedance characteristics of the inductor and capacitor. The
filter has the characteristics of a frequency selective network, which is traditionally
powered by electricity. A frequency selective network circuit is composed of a
frequency selective function component such as a resistor, a capacitor, and an
inductor. A common frequency selective network circuit composed of RC filters is
shown in Fig. 15.10.
The important performance indicators of the filter include cutoff frequency, ripple
amplitude, passband bandwidth, quality factor, and amplitude-frequency character-
istics. The cutoff frequency of the filter refers to the frequency value generated when
the average value of the amplitude-frequency characteristic of the filter is attenuated
to 3 dB. In a general circuit, the smaller the ratio of the waveform amplitude to the
290 B. Wang et al.

Fig. 15.10 Frequency

selective network circuit
composed of RC filter

amplitude-frequency characteristic of the filter is designed, the higher the perfor-

mance of the filter; and the amplitude-frequency characteristic generally exhibits the
shape of the ripple in the circuit simulation. The bandwidth of the difference between
the two cutoff frequencies of the filter is the passband bandwidth.
There are many types of filters. Signal-based processing and analysis functions
can be divided into analog and digital filters. Based on the frequency response
method, filters can be divided into low-pass filters, high-pass filters, band-pass
filters, band-stop filter (or band-rejection filter). In addition, the digital filter can be
implemented either by a DSP processor or by an FPGA through digital design
[15, 16].
As variety of filters are used in modern high-speed communications, the design
requirements for filters are increasing. In recent years, new structures and new
materials, such as Defected Ground Structure (DGS), Substrate Integrated Wave-
guide (SIW), multimode structure, and Low-Temperature Co-fired Ceramic (LTCC)
have emerged. The emergence of these new structures and new materials will lead
the way in the development of new filters in the future. RF Filter Products are
commercially available [17].

Microwave Devices

Microwave devices work in the microwave band (300 MHz to 300 GHz), they are
usually used in electronic products such as signal transmitters, signal receivers, radar
systems, mobile communication systems, etc. Microwave devices include micro-
wave vacuum device and microwave semiconductor device, the latter has a property
of integration and is described here.
According to the working principle and function, microwave semiconductor
devices can be divided into microwave diodes and microwave transistors. In terms
of noise suppression of microwave at receiving signals, microwave diode possesses
good feature in noise reduction. Representative devices include mixer diode and
varactor. In microwave control device applications, microwave transistors play a
major role in the representative devices with enhanced metal-semiconductor field-
effect transistor (MESFET), junction gate field-effect transistor (JFET or JUGFET),
and high electron mobility transistor (HEMT), etc.
A diode can be used for Frequency Mixer or RF Mixer that utilizes the metal-
semiconductor contact principle. Under forward bias, when the work function of the
15 Radio Frequency IC Products 291

metal is greater than or equal to the work function of the n-type semiconductor,
carriers in the n-type semiconductor migrate into the metal to form a current. Since
the turn-on voltage is low, the series resistance is small, and the current is generated.
Similarly, under reverse bias, due to its higher reverse breakdown voltage, the
resistance is small, and a small current is generated. The main indicators of the
mixing diode are breakdown voltage, zero-bias junction capacitance, series resis-
tance, and noise figure [18].
Varactor diodes are mainly used in basic frequency conversion circuits such as
parametric amplification, mixing, and frequency multiplication. The original
varactor diode was fabricated from silicon and its cutoff frequency did not reach
100 GHz. Therefore, its low-noise parametric amplifier has a low operating band.
The rapid development of new GaAs materials has facilitated the updated iteration of
varactors. Varactor diodes can effectively control epitaxial layer concentration
distribution and interface steepness. The main parameters of varactors are break-
down voltage, varactor ratio, and cutoff frequency [19].
The depletion type of MESFET has been widely used, its current drive capability
is strong, and the circuit formed has a large logic swing; however, the device
consumes a large amount of power and the circuit is complicated, so the degree of
integration is limited.
The enhanced type of MESFET is just the opposite. Its simple circuit and
low-power consumption make the circuit with a low logic swing. The main factors
affecting the enhanced MESFET are the threshold voltage and the barrier forward
turn-on voltage. Enhanced MESFET performance indicators for enhanced
MESFETs include reliability power, output power, and breakdown voltage [20].
The junction field-effect transistor (JFET) consumes low power and has a large
turn-on voltage of the pn junction. For example, the turn-on voltage of the hetero-
junction FET can reach 1.4 V, so the output swing of the circuit is large. JFETs have
greater radiation tolerance than MESFETs. The disadvantage is that the pn junction
gate has a large edge capacitance, which is slower during ion migration than the
same size MESFET circuit. The main performance indicators of JFET are forward
current greater than or equal to 3.5A, reverse breakdown voltage greater than or
equal to 1700V, and transconductance greater than or equal to 0.52S [21].
High Electron Mobility Field-Effect Transistors (HEMTs) are fabricated from
semi-insulating GaAs substrates using MOCVD techniques to grow high-purity
GaAs and doped with multilayer structures such as Al, Ga, As, and GaAs. Since
the electron affinity in the narrow-bandgap GaAs is large, the free electrons in the
wide-bandgap AlGaAs layer transit to the AlGaAs boundary layer in the high-purity
GaAs to generate a two-dimensional electron gas. HEMT has better high-speed
performance in the circuit than MESFET, and the impurity scattering in high-purity
gallium arsenide is very weak, with high electron mobility. The main performance
indicators of HEMT are output power and frequency characteristics [22].
Future microwave devices will have better stability, thermal conductivity, heat
resistance, pressure resistance, and radiation resistance. Products of Microwave
Devices are commercially available [22].
292 B. Wang et al.

Millimeter Wave Devices

Millimeter Wave (mmW), which is also called extremely high frequency (EHF), has
a frequency band from 30 GHz to 300 GHz and wavelength of 10 mm–1 mm [23] by
ITU (International Telecommunication Union). The band of the mmW is subdivided
by IEEE into Ka-Band (26.5 GHz to 40 GHz), V-Band (40 GHz to 75 GHz), W-Band
(75 GHz to 110 GHz), and D-Band (110 GHz to 170 GHz), G-Band (140 to
220 GHz), H-Band (220 to 325 GHz), etc., while NATO has K-Band
(20–40 GHz), L-Band (40–60 GHz), M-Band (60–100 GHz) [24]. Due to its short
wavelength and narrow beam characteristics, the influence of weather variation on
mmW performance is limited, so mmW devices meet the requirements for
all-weather operation.
The mmW was originally proposed by Heinrich R. Hertz in 1889. In 1897,
scientists studied the transmission characteristics of 5 mm band mmW on iono-
spheric attenuation and rainwater scattering environment. The mmW technology
developed slowly due to high requirements for basic material properties and pro-
cessing techniques. In the 1960s, with the advancements of materials science and
processing techniques, 6 mm frequency band mmW was applied on radar system,
and 1 mm frequency band mmW was used for the radio telescope of astronomical
applications. Since the 1980s, advances in materials science and microelectronics
greatly promoted the research work of mmW technology, and new mmW devices
have been widely used in the fields such as radar communication and medical
applications.

1. Millimeter Wave Radar. Due to the short wavelength and the narrow beam of
millimeter wave, the mmW radar is often small and light. The mmW has strong
anti-interference ability when the climate changes, so that mmW devices can
meet the requirements for all-weather work. The mmW radar has the character-
istics as high resolution, long detection range, and stable performance, which
make it been widely used in precision guidance, intelligent driving, navigation,
and detection.
2. Millimeter Wave Satellite Communication. The mmW has a high carrier
frequency, which allows it to have a broadband signal to meet the requirements
of high-speed information transmission. By using its characteristics as short
wavelength and narrow beam, multibeam narrowband mmW antenna of strong
directivity can be realized, and its coverage area can be expanded by band
conversion. Due to the strong anti-interference ability of the mmW, the quality
of communication under poor weather conditions is also guaranteed by the mmW
antenna. Because the air in the outer space is thin, the mmW has very little energy
loss during the propagation in that environment, and only a small power is
required to realize long-distance communication. Based on the above character-
istics, mmW technology has been widely used in long-distance communication
satellites to ground or satellite to satellite systems.
3. Millimeter Wave Medical Treatments. The Eigen frequency of biological
tissues such as human body is in the frequency range of mmW. Therefore,
15 Radio Frequency IC Products 293

based on resonance, the mmW can produce a series of biological effects on

human biological tissues. For example, it promotes ion movements in the body;
changes the activity of proteins, amino acids, and enzymes; and regulates the
metabolism of cells; and so on. In recent years, the researches on tumor immunity,
endocrine system, and digestive system have been gradually carried out by using
mmW technology.

Due to its extremely low radiation, high resolution, and privacy protection, the
mmW is also applied on scanning imaging security gates. The mmW security gates
are one of the main research directions in the field of safety-check, and it is possible
to replace the X-ray security gates which currently widely used in subway stations,
airport, and railway stations.
The mmW technology plays an increasingly important role in people’s daily
activities. Devices based on mmW technology can realize ultra-high-speed wireless
data transmission by increasing spectrum bandwidth, which has become one of the
key technologies of 5G communication systems and has important market value.
System vendors who master the core technology of the mmW radar include Bosch,
Continental, and Delphi, etc. In terms of integrated devices that dominate the market,
S32R27 by NXP is used for radar control system, STRADA431 (24 GHz) and
STRADA770 (77 GHz) by STMicroelectronics are designed for medium/long-range
distance detection, and BGTx0 and RXN7740 by Infineon are RF front-end chips.

Terahertz Devices

Terahertz (THz) frequency ranges from 0.1 THz to 10 THz and wavelength ranges
from 0.03 mm to 3 mm; while for communications, ITU designated Terahertz ranges
to be 0.3 THz–3 THz, wavelengths of 1 mm–0.1 mm [25]. In electromagnetic
spectrum, the THz is between microwave and infrared, and has the advantages
such as wide spectrum, high signal-to-noise ratio, high coherence, and low photon
energy.
As early as 1896, scientists studied the electromagnetic waves of the THz band.
Because of the limit in materials and processing techniques, the lack of THz wave
source and high-sensitivity detectors made the research work progressing very
slowly. Since the 1980s, with the progress of materials science and the advance of
processing techniques, new impetus had been injected into the development of THz
technology and attracted attention of the world. With many applications using new
materials and new processes, significant progress has been made in THz wave
sources and THz devices.
The THz wave sources include both wideband THz sources and narrowband THz
sources. The broadband THz sources, which contain ultra-wide spectral components
of up to tens of THz, have a low radiation power and are currently used in
spectroscopy systems. The narrowband THz source is mainly used as a THz
oscillation source or a coherent THz source and has been applied in the fields such
as sub-millimeter wave oscillator and free electron laser.
294 B. Wang et al.

THz devices can be classified as passive and active components. The passive
components include transmission lines, filters, couplers, and antennas. The active
components include mixers, frequency multipliers, detectors, amplifiers, and oscil-
lators. THz technology can be widely used in the fields as astronomy, detection, and
communication. The THz application systems such as terahertz radio telescope, Thz
detection technology, and THz communication technology have been invented.

1. THz Radio Telescope. By studying the spectral characteristics of terahertz in

cosmic radiation, we can learn the composition of molecular clouds and explore
the origin of the universe. By analyzing the spectral information contained in the
scattering of atoms and molecules in cosmic rays, we can study the internal
mechanism of the formation of new cosmic galaxies. With the progress of THz
technology, the THz radio telescope becomes an important scientific means of
observing space and studying cosmic rays.
2. THz Detection Technology. THz detection technology mainly includes two
aspects: time-domain spectroscopy and transmission imaging. The time-domain
spectroscopy uses terahertz waves to illuminate objects. After passing through
object, transmitted and reflected waves affect the electric field of the THz, so
that measurement of the change of electric field strength can show the spectral
characteristics of the object irradiated by the THz. The structure and composi-
tion information of the object can be obtained by analysis of the spectral
properties of the material. This technology can be used for food and drug quality
regulation. Transmission imaging utilizes the penetration characteristics of the
THz wave. The THz wave has good penetrability for solid materials without
moisture but is less penetrating for living bodies that contain a large amount of
moisture. Based on this feature, THz imaging can scan through concrete to
detect the distribution and activities of human being in covered areas, such as
indoors or under ruins. This application has great value in anti-terrorism and
disaster rescue.
3. THz Communication Technology. Taking the THz wave as the carrier fre-
quency, the wireless data transmission speed can reach 10 GB/s. The working
environment of satellite communication system in universe is like vacuum. In that
condition, the propagation loss of THz wave is very small, so that THz
technology-based communication systems can greatly increase the data transmis-
sion speed, which reaches more than a thousand times of current ultra-wideband
technology. While wide commercial applications of THz technology are limited
by the short of high-quality terahertz signal sources and antennas, with continu-
ous emergence of new materials and processing technics, the researches on THz
devices develop rapidly and the THz communication has become an important
tendency of future communication systems.

THz technology has great value in the field of industrial monitoring and quality
control. In the field of nondestructive testing and medical imaging [26], the appli-
cation of THz technology largely promoted the growth of concurrent electronics
market.
15 Radio Frequency IC Products 295

Radio (Receiver) Integrated Circuit

Radio has three operation modes: Frequency Modulation (FM), Amplitude Modu-
lation (AM), and Shortwave (SW). The frequency range of FM broadcast is 76 MHz
to 108 MHz (88–108 MHz in China, 76–90 MHz in Japan). The frequency range of
AM broadcast is 530 kHz to 1600 kHz. SW generally adopts amplitude modulation
technique, and its frequency range is usually between 1.6 MHz and 30 MHz. The
AM has a long transmission distance, but because it is sensible to weather variation,
it is used for provincial radio stations. Many countries use SW for worldwide
broadcasting. In earlier 1920s, LW (Long-wave) broadcast was used. LW generally
indicates that the wavelength of carrier frequency is longer than 1000 m (which is
equivalent to a frequency lower than 300 kHz).
The integrated circuit or chip used in a radio receiver refers to integrate on a same
substrate both antenna and audio processing module, and full radio set function is
achieved by a single chip. Radio chip generally provides functions such as frequency
tuning, band selection, volume control, and stereo processing (digital-to-analog
conversion). The radio chip has a variety of digital configurations. Some radio
chips use an external microcontroller (MCU) to configure the tuning and receiving
modes of FM/AM/SW signals. Some radio chips integrated full receiver and control
system that processes FM/AM/SW signals directly without the need of an
external MCU.
In 1958, Jack S. Kilby developed the world’s first IC. Over the next 30 years,
modules based on IC gradually replaced radio set circuits that are made of discrete
transistor components, significantly increasing system integration. With the progress
of microelectronics technology, digital signal processing (DSP) techniques became
applicable for all-digital radio solution. In 2006, Si Labs introduced Si473 X-series
radio chips, the world’s first single-chip radio set, supporting short-wave, medium-
wave, long-wave, and very high-frequency bands of the radio system.
Radio receivers include traditional AM/FM/SW radios, home theater receivers,
for example to support AC-3/7.1 audio channels of 100 W each channel, other radio
types are HAM and amateur radios [27]. Receiver ICs [28] at large are suitable for
TVs, radios, GPS devices, cellphones, wireless devices, and many other applica-
tions; while radio receiver ICs are specifically for radios, and focused on SDR
(software-defined radio) technology in twenty-first century [29].

Navigation Receiver IC

A navigation receiver integrated circuit (IC) receives radio signals transmitted by

satellites in space, thereby enabling to provide all-weather three-dimensional coor-
dinates, speed, and time information to users for all locations on the Earth’s surface
or near-Earth space.
At present, there are four global navigation satellite systems (GNSS) [30]: the
Global Positioning System (GPS) of United States, the Global Navigation Satellite
296 B. Wang et al.

System (GLONASS) of Russian, the Galileo satellite navigation system (Galileo) of

European, and the BeiDou navigation satellite system (BDS) of China.
Satellite navigation chips are widely used in land-sea-air applications. In land
applications, the chips are applied in fields including atmospheric physical observa-
tion, vehicle navigation, engineering survey, resource exploration, crustal motion
monitoring, municipal planning and disaster relief. In marine applications, the chips
are applied in fields including cargo dispatching, ship navigation, marine rescue,
hydrological surveying, and offshore platform positioning. In aerospace applica-
tions, the chips are applied in fields including aircraft navigation, missile guidance,
aerial remote sensing, low-orbit satellite orbit determination, and aviation rescue.
The satellite navigation chip is the core device of satellite navigation industry.
The satellite navigation chip can be classified into two categories: front-end RF
signal processing chip and back-end baseband data processing chip. As high-level
system integration is requiring, a single-chip navigation system that integrates both
front-end RF signal processing and back-end baseband digital signal processing
becomes the target for both industry and research [31].
In a satellite navigation chip, such as in a typical GPS receiver, there are several
key components, including the antenna, LNA (low-noise amplifier), SAW (surface
acoustic wave) filter, LDO (low-dropout regulator), TCXO (Temperature Compen-
sated Crystal Oscillator), and GPS RF/receiver [32]. The fully integrated GNSS
(GPS, Galileo, GLONASS, and BeiDou) receiver is commercially available [33, 34].
As of August 2019, there are 31 operational satellites in the GPS constellation.
The BDS consists of five geostationary orbit satellites and 30 nongeostationary orbit
satellites. By November 2016, there are already 23 satellites working in the BDS. In
2012, the BDS had achieved in covering the Asia Pacific region. The BDS plans to
realize global coverage around 2020.

Wireless Fidelity Products

Wireless network products are devices that use wireless local area network (WLAN)
for data transmission. They work in local area, such as household, schools, and
offices. In area covered by wireless local network, users can remain connected while
keep moving. Wireless Fidelity (Wi-Fi) is one of wireless technologies that widely
applied. Wi-Fi is a short-range wireless communication technology, which follows
IEEE 802.11 standard [35] that provides a unique IP address for all devices
connected in, and build a wireless network through IP addresses for data communi-
cation. The working frequencies of Wi-Fi devices have two bands at 2.4 GHz and
5 GHz, supporting a data rate from 1 Mbps to 150 Mbps, covering an effective
communication distance from 30 to 100 m.
The Wi-Fi technology was invented by Australian Commonwealth Scientific and
Industrial Research Organization (CSIRO) in the 1990s and patented in the United
States in 1996. In 1999, IEEE officially confirmed Wi-Fi technology as the IEEE
802.11 standard. The carrier frequency of Wi-Fi is 2.4 GHz or 5 GHz, which belongs
to Industrial, Scientific, and Medical (ISM) band that defined by International
15 Radio Frequency IC Products 297

Telecommunications Union (ITU). The band is free to use, without the need for a
telecom operation license. Compared to other short-range wireless communication
technologies such as Bluetooth (2.4 GHz to 2.485 GHz) and ZigBee (main 2.4 GHz
to 2.484 GHz), the Wi-Fi provides a higher transmission rate. The Wi-Fi technology
is the main way for users to obtain wireless network services and has been widely
used in mobile devices.
At present, the main Wi-Fi chip [36] providers include Broadcom, Texas Instru-
ments (TI), Marvell, Qualcomm, Ralink, and Realtek. Among them, Broadcom,
Marvell, and TI have mature technology and good performance of their products,
they have formed a full industrial chain made on Wi-Fi chips. Ralink and Realtek
provide Wi-Fi chips to dominate the market of low-end routers. As the high-power
consumption of Wi-Fi chips limits its application in Internet of Things (IoT),
low-power Wi-Fi chips are always a focus in industry.
Independent Wi-Fi chips only provide the function of connecting and transmitting
signals, and a separate processor is necessary for transport protocol processing.
Therefore, a complete wireless connection technology solution contains both the
Wi-Fi chip and an external microcontroller (MCU) [37], which increases system
cost. Driven by the huge demand for IoT applications, a SoC chip integrating Wi-Fi,
Bluetooth, and MCU becomes the latest technology trend. On the other hand, based
on the IEEE 802.11n standard, 600 Mbps data transmission rate of the earlier Wi-Fi
chip does not meet the requirements for large amount data transmission demanded
by newly emerging IoT applications. In 2012, the IEEE 802.11 ac standard is
promoted, which allowing 1 Gb/s wireless data transmission speed on the 5 GHz
frequency band. The Wi-Fi chips that meet the IEEE 802.11 ac standard become the
main choice for wireless router products.

Bluetooth Products

Bluetooth is a point-to-point short-range wireless data transmission technology,

which was firstly studied by Ericsson in 1994. Bluetooth uses spread spectrum
communication technology based on frequency hopping. Its frequency range is
from 2.4 to 2.485 GHz, which belongs to Industrial, Scientific, and Medical (ISM)
band that defined by International Telecommunications Union (ITU). This band is
free to use without applying for a telecom operation license. The communication
distance of Bluetooth is classified as Class A and Class B. The Class A type has a
communication distance about 20 to 30 m, but its power consumption is too large to
fulfill the requirements of personal communication products. The Class B type has a
communication distance about 5 to 10 m, and it is widely used in consumer
electronics as its power consumption reaches a very low level.
According to different application scenarios, Bluetooth released different ver-
sions; Bluetooth 1.1 meets IEEE 802.15.1 standard [38]. Bluetooth 1.1/1.2 works in
simplex mode, with a data transmission rate about 748 to 810 kbit/s. Bluetooth 2.0
works in duplex mode and improves data transmission rate, which is about 1.8 to
2.1 Mbit/s. Bluetooth 3.0 is designed for high-speed applications and its data
298 B. Wang et al.

transmission rate reaches up to 24 Mbit/s. Bluetooth 4.0 (Bluetooth Smart) integrates

the classic Bluetooth, the high-speed Bluetooth, and Bluetooth Low Energy (BLE),
and largely applied in mobile products because of its low-power dissipation charac-
teristics. Bluetooth 4.0 reaches a data transmission rate up to 25 Mbit/s. Bluetooth
5.0 was released in June 2016, supporting a 255-Byte data packet to improve
transmission efficiency. Bluetooth 5.0 [39] reaches a maximum data transmission
rate of 50 Mbit/s, and its signal coverage area is also significantly improved.
Bluetooth 5.1 has been released in January 2019.
Bluetooth products are now widely used in wireless interconnection of mobile
wireless products such as computers, mobile phones, printers, digital cameras,
headsets, keyboards, computer mouse, etc. Since 2013, the rapid development of
smartphones and products related, such as tablets and wearable devices; drove an
explosive growth of Bluetooth chips. The largest supplier of the Bluetooth chips in
the world is Cambridge Silicon Radio (CSR), which was acquired by Qualcomm in
August 2015.
There are three main aspects for the Bluetooth development: (1) Develop
Bluetooth networking capabilities. To build a low-power Internet-of-Things (IoT)
system by connecting smart home systems and wearable devices based on
low-power Bluetooth technology. (2) To integrate Bluetooth devices with sensors,
making the sensors intelligent by sending data collected by the sensors directly to
cloud for processing and feedback through the Bluetooth devices. (3) To establish
Bluetooth-based mobile products for indoor positioning.

ZigBee Products

ZigBee is a low-power short-range wireless communication technology. ZigBee is

based on IEEE 802.15.4-2006 – IEEE Standard [40] and has three carrier frequency
ranges. The frequency range of 2.4 to 2.484 GHz is the main one, the one of
902–928 MHz is allowed in North America and the one of 868.0–868.6 MHz is
also used in Europe.
ZigBee Alliance. ZigBee was first proposed in 1998 and the IEEE 802.15.4
standard was set in 2003. ZigBee is developed and managed by ZigBee Alliance
[41], which was established in 2001 as a nonprofit organization of top international
semiconductor manufacturers, technology vendors, and worldwide end-users. The
first version, ZigBee V1.0, was released by the ZigBee Alliance in 2004. In 2006,
ZigBee 2006 was launched with optimization of system architecture. In 2007 and
2009, ZigBee PRO and ZigBee RF4CE were introduced successively, the system
becomes more flexible and easier to use by remote control.
Features of ZigBee. ZigBee terminal can be self-connected to form a ZigBee
network for communication. The coverage of the ZigBee network is extendable by
using different topologies such as star, patch, and mesh. ZigBee is designed for low
data rate applications, while it has the advantages as low standby power, short
latency, and high capacity. The power dissipation of ZigBee devices is lower than
the one based on Bluetooth, and ZigBee is one of the lowest power consumptions
15 Radio Frequency IC Products 299

among all short-range communication technologies. The maximum transmission

distance of ZigBee between two neighboring nodes is 10–100 m. For communica-
tion of two nodes which are farther, the range can be extended by routing between
adjacent nodes. To meet technical requirements of different applications, ZigBee
provides three data rates, which are 250 kbit/s for 2.4 GHz, 40 kbit/s for 915 MHz,
and 20 kbit/s for 868 MHz respectively.
ZigBee Products. The mainstream ZigBee chips in market are CC243X
and CC253X series from Texas Instruments, MC1321X and MC1322X series
from Freescale, EMBER series from STMicroelectronics (ST), and JN516x
series from NXP. These products integrate both RF front-end and protocol stack
on a single chip, largely improving the integration of ZigBee system.
ZigBee technology has been widely used in various fields such as industrial
control, agricultural automation, and medical device control. In a sensor information
collection network based on ZigBee, data acquisition is automatic and then all data
are sent to back-end system for big data analysis and processing, providing an
important technical way for industrial control and strategy. In agricultural automa-
tion, ZigBee-based sensor network can provide automatic and intelligent precision
network production by comprehensive collection and analysis of the information of
crop moisture, soil nutrient, and climate. In medical applications, ZigBee-based
sensor network is used to connect various medical monitoring devices for real-
time continuously monitoring on vital signs information as blood pressure, body
temperature, and heart rate, enabling the medical monitoring system more
intelligent.

Radio Frequency Identification Products

Radio Frequency Identification (RFID) is a wireless communication technology that

enables wireless data transmission by noncontact ways, which is either magnetic
coupling or electric transmission by RF, to identify specific targets. The RFID
technology does not need to have a mechanical or optical connection between
identification system and target, so that it is easy to use with fast recognition
speed. The RFID devices have the characteristics as simple to use, long service
life, and high safety. The RFID is one of the core technologies of Internet of Things
(IoT) and it is now widely used in business automation tools, transportation man-
agement, and logistics.
RFID devices are classified into two kinds: passive devices and active devices.
(1) The passive RFID device has no power supply. There is generally an energy
storage coil inside for energy supply which is sent by external terminals through
electromagnetic coupling. When the energy received reaches its driven threshold, the
circuit of the passive RFID device turns on and exchanges information with outside
identification system by backscattering modulation. Limited by energy available, the
passive RFID device has generally a short recognition range and a low data trans-
mission rate. (2) The active RFID device contains a miniature battery or an internal
power supply, and it generally works in a very low-power standby mode. As there is
300 B. Wang et al.

a power supply inside, the active RFID device has a faster respond speed. In working
mode, the active RFID device exchanges information with the outside identification
system by means of radio frequency communication, which provides a large area of
recognition and a high data transmission rate [42].
RFID tags such as pass cards, tickets, and access cards work in 13.56 MHz. The
RFID tags are widely used in automatic access control system, providing an effective
identification process which greatly simplifies passage recognition procedure and
significantly improves system efficiency. Traditional manual toll collection system
for highway booth and parking lots has a low-efficient and can cause road conges-
tion. Electronic Toll Collection (ETC) system operating in 5.8 GHz that enables
remote data exchange by installing an On-Board Unit (OBU), which is an active
RFID tags, on vehicles. The OBU exchanges data with the toll booth via wireless
communication, highway toll collection is carried out in a background settlement
way, which does not need to stop the car at the highway entrance or exit, greatly
improving the efficiency of vehicle traffic management. Applying the RFID tags on
warehouse goods not only enables intelligent automatic management of goods
entering and leaving but also provides real-time monitoring of stock. In freightage,
it is also possible to realize remote intelligent monitoring on transportation path and
environment through the RFID tags installed on goods, largely improving logistics
automation.

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facturers.html. Accessed 20 Feb 2020
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15. P. Liu, Design and Implement of FIR Digital Filter Based on FPGA, MSc Thesis (Northwestern
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16. C. Wei, A Study of Key Technology of New-Type Microwave Filter, PhD Dissertation (Univer-
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20. P. Gupta, P. Kaushik, Comparative analysis of GaAs MESFET with different dimensions, in
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receiver-types.php. Accessed 20 Feb 2020
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radio_receiver_ics. Accessed 20 Feb 2020
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next-design-easy. Accessed 20 Feb 2020
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Wilmington, DE, USA, 2017)
Products of Power Devices
16
Xinnan Lin, Zheng Gong, and Jesse Jen-Chung Lou

Contents
Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Power Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
PiN Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Unipolar Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Fast Recovery Diode (FRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Power BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Insulated Gate Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Wide-Bandgap Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Superjunction Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Gate Turn-Off Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Integrated Gate-Commutated Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Emitter Turn-Off Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
MOS-Controlled Thyristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Abstract
Power devices are typically used in applications where high voltage, large
current, and high frequency are requirements. For example, power devices are
required in high-voltage transmission, power electronic equipment, electric

X. Lin
Electronic and Computer Engineering, Peking University, Shenzhen, China
Z. Gong
Tunghai University, Taiwan, China
J. J.-C. Lou (*)
School of Software and Microelectronics, Peking University, Beijing, China
Institute of Microelectronics, Peking University, Beijing, China
e-mail: jesselou@ss.pku.edu.cn

© Publishing House of Electronics Industry 2024 303

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_16
304 X. Lin et al.

vehicles, and in locomotives, etc. As silicon-based materials are approaching their

performance limit, high bandgap materials, such as gallium nitride (GaN) and
silicon carbide (SiC) are becoming mature and entering the application market.
Power devices include power diode, power BJT, power MOSFET, insulated gate
bipolar transistor (IGBT), super junction thyristor, gate turn-off thyristor (GTO),
insulated gate-commutated thyristor (IGCT), emitter turn-off thyristor (ETO),
MOS controlled thyristor (MCT), etc. These devices are briefly described in
this chapter with their basic structures, working principles, and mechanisms.

Keywords
Power device · IGBT · GTO · IGCT · ETO · MCT

Power Devices

Power devices, usually regarded as power electronic devices, are semiconductor

devices specifically designed for power processing. Power devices potentially can
support high voltages (from tens of volts to thousands of volts) and pass large
currents (up to several thousand amperes). They are widely applied in high-voltage
power systems, such as transformer substation, energy storage devices, and power
electronic equipment for the control and manage of power distribution [1, 2].
The most common power devices are power metal-oxide semiconductor field-
effect transistor (MOSFET), thyristor, Triode for Alternating Current (TRAC), Gate
Turn-Off (GTO), Insulated Gate Bipolar Transistor (IGBT), Integrated Gate-
Commutated Thyristor (IGCT), Emitter Turn-off (ETO) MOS controlled transistor,
MOS Controlled Thyristor (MCT). The early power devices are mainly large power
diodes and thyristor, etc., usually applied on industrial and electrical systems. With
the rapid development of power MOSFET and other new power device such as
IGBT, power devices have found more and more applications.
There are several ways to classify power devices.
Power devices can be classified into two types depending on the switching
characteristics. ① Semi-controlled devices. The signal of gate can only control
the device to conduct but not to turn off, such as SCR. ② Full-controlled devices.
The signal of gate can control both turn-on and -off, such as bipolar transistor, IGBT,
IGCT, ETO Thyristor, MCT, and GTO Thyristor, etc.
The control type of power devices includes gate control and base control.
Therefore, power devices can be divided into two types. ① Current-controlled
devices: The control signal of the gate is the current flowing in or out, such as SCR.
② Voltage-controlled devices: The control signal of the gate is voltage; the current
consumption is small, such as IGBT.
Power devices can be classified into three types depending on the conductive
carriers. ① Unipolar devices: Only one type of carrier participates in conduction,
such as MOSFET. ② Bipolar devices: Electrons and holes participate in
16 Products of Power Devices 305

conduction, such as BJT. ③ Hybrid devices: Devices are composed of unipolar

devices and bipolar devices, such as IGBT.
Technically, power devices are developing into the direction of improving fast
recovery performance, reducing turn-on resistance, improving current control capa-
bility, increasing rated blocking voltage, improving temperature resistance, and
reducing power consumption.
With the gradual maturity of silicon-based power devices and process, their
performance has gradually approached material limit, materials with higher per-
formance limit should be adopted to make a breakthrough. The wide-bandgap
semiconductor materials such as gallium nitride (GaN), silicon carbide (SiC), and
so on, have the advantage of high critical electric field strength, high electron
saturation rate, high temperature resistance, radiation resistance, etc. Power
devices based on wide-bandgap semiconductor materials have also entered the
growing market.
GaN is mainly used in power semiconductors for power amplification, rectifica-
tion, and high-frequency switching. Its market is growing rapidly in the 300 V-1 kV
medium voltage power electronics. In addition, the demand for high-efficiency
medium- and high-voltage inverter in the energy-saving industry will also accelerate
the growth of the GaN power semiconductor market. The technology of growing
GaN thin films on sapphire substrates by MOCVD has matured in the LED industry.
Therefore, in the emerging power electronics market, the development of technology
for fabricating power devices by forming GaN-on-Si structures on large-sized silicon
substrates by MOCVD has great industrial potential.
The blocking voltage of SiC is much higher than that of GaN, power MOS, and
Si-IGBT. It is suitable for power electronics with high voltage (higher than 1 kV) and
high current. The main market is in railway traffic and high-voltage power grid. The
life cycle is a major factor to consider. In addition, the United States Cree company
also has mass production on microwave devices of GaN-on-SiC structure.

Power Diode

Power Diode is a discrete power semiconductor device with a much wider range of
voltage and current applications than typical small signal diodes. It can be used for
rectification, clamping, transient voltage suppression, freewheeling, absorption,
modulation, conversion, etc. Power diodes are divided into two types: PiN (P-intrin-
sic-N) diodes and single-pole Schottky Barrier Diodes (SBD).

PiN Diode

The PiN diode is a current-controlled device, a minority carrier, with low input
impedance and a large driving power. There are minority carriers stored near the pn
junction when turn-on, resulting in slower switching speed of the device. Si-based
306 X. Lin et al.

Fig. 16.1 Schematic of PiN diode structure and carrier concentration

PiN diodes typically operate at less than 1 kHz. Schematic of structure and carrier
concentration of the PiN diode are shown as Fig. 16.1, adding a specific thickness
low-doped n-type drift region (or p-type drift region) between the heavily doped p+
layer and the n+ layer as a voltage resistance layer.
When a forward bias voltage is applied to the PiN diode, a large number of
minority carriers are injected into the drift region to produce a conductance modu-
lation effect, which reduces the on-state resistance and voltage, thereby greatly
reducing the on-state power consumption.
In the reverse bias, the space charge region of the p+n junction mainly extends to
the low-doped n-type drift region, and the reverse blocking voltage is absorbed by
the depletion region of the n-type drift region, so that the PiN diode can block very
high reverse voltage with small leakage current. Usually the maximum reverse
operating voltage is 2/3 times the avalanche breakdown voltage.
In the forward biasing, the p+ region injects a large number of holes into the n-type
drift region, and the n+ region also injects a large number of electrons into the
n-type drift region.
The nonequilibrium minority concentration is much higher than the original
implanted doping in the n-type drift region, as resulting in a decrease in on-state
resistance and increase in on-state current for good electrical conduction. At this
time, the large on-state current is not limited by the low doping and thickness of the
n-type drift region [1, 3].
Reducing the thickness of the drift region of the PiN diode results in a punch-
through structure, and the thinner drift region reduces the stored charge in the
on-state and increases the turn-off speed. Deep level recombination centers can be
introduced into the Si forbidden band by diffusing gold (Ag), platinum (Pt), proton
or electron irradiation, which can reduce the minority carrier lifetime and shorten the
reverse recovery time, thus increase the turn-off speed.
The wide-bandgap silicon carbide (SiC) PiN diode not only have a higher
breakdown voltage, but also a thinner drift region structure can reduce the reverse
recovery current and increase turn-off speed, so it can operate at large current and
high blocking voltage (greater than 10 kV).
16 Products of Power Devices 307

Unipolar Schottky Diode

The Schottky contact barrier formed between the metal and the silicon-based
semiconductor can produce rectification, but the barrier height is lower than pn
junction. Therefore, the general small-signal Schottky diode has a lower forward
voltage drop and a lower reverse breakdown voltage, with larger reverse leakage
current as shown in Fig. 16.2.
Adding a low-doping n
drift region to the Schottky diode forms a power
Schottky diode structure consisting of a Schottky junction, n
drift region, and an
n+ cathode region. The on-state voltage drop is determined by the metal semicon-
ductor interface voltage, n
drift region resistor, and ohm voltage drop at the
substrate. Since the unipolar Schottky diode is majority carrier device with no
carrier storage and conductance modulation effects, rather it has fast switching and
low on-state voltage drop, so the power consumption at high frequencies is low.
At reverse bias, the blocking voltage is determined by the width of the n
drift
region. Theoretically, the largest electric field strength occurs at the metal-
semiconductor contact, where the breakdown occurs when the electric field strength
is equal to the critical electric field strength of the semiconductor. However,
the breakdown voltage of the reverse blocking is limited by the edge breakdown
of the metal electrode, so the edge termination technique shall be used to increase the
breakdown voltage of the power Schottky diode. Generally, the breakdown voltage
of the Si-based Schottky diode is operated at less than 200 V, so the Si-based
Schottky device is more suitable for high-frequency applications (i.e., not for high
current and high-voltage applications). The wide-band SiC Schottky Barrier Diode
(SiC-SBD) has a breakdown voltage of more than 3 kV, it is suitable for operating at
higher voltage and power level. The Si-IGBT+SiC-SBD module unit composed of
Si-based IGBT can greatly reduce the power consumption.
The leakage current of a power Schottky diode includes current generated by
a space charge in the depletion region, a diffusion current generated by carriers
in the neutral region and a hot electron emission current generated at the

Fig. 16.2 Schematic of

power Schottky barrier diode
(SBD)
308 X. Lin et al.

metal-semiconductor contact. The thermal electron emission current is domi-

nated by temperature and Schottky contact barrier. Since the Schottky contact
barrier height is relatively small, the leakage current is dominated by the thermal
electron emission current. The use of a relatively large Schottky contact barrier
can reduce leakage current and reduce power dissipation at the blocking state,
while avoiding the Thermal Runway and allowing the power Schottky diode
operating at higher ambient temperatures.
Power diodes are the first-generation power semiconductor devices that can be
used independently or used for freewheeling and fault energy absorption for all
power semiconductor devices. Modern power semiconductor devices such as IGBT
require at least one or two power diodes for their freewheeling and energy
absorption.

Fast Recovery Diode (FRD)

The power diode for rectification must have a low forward voltage drop to increase
the on-state current and reduce the on-state power consumption, also it should have a
high breakdown voltage, but the requirement for reverse recovery time is not high.
Switching power diodes require higher switching speed, so the reverse recovery time
must be shortened, and on-state voltages can be reduced. For fast recovery diodes
(FRD), the free-flow power diodes must have fast recovery speed and low on-state,
at the same time have a high softness (also called a recovery coefficient, i.e., tf/td, the
ratio of the current fall time tf and the delay time td during reverse bias) to ensure the
operational reliability of the power electronic system.
The recovery speed of power diodes can be improved by diffusion of gold,
platinum or irradiation. Power diodes diffused with gold or platinum not only have
larger turn-off leakage current, but also have higher peak voltage of conduction, so
the switching power consumption is larger.
The turn-off leakage current of the electron irradiation power diode is low, but the
too large reverse recovery peak current is not easy to achieve soft recovery, thus,
resulting in large switching power consumption. The proton-irradiated power diode
has a lower reverse recovery peak current, so it is easy to achieve soft recovery; the
switching power consumption is lower. The position of the irradiation overlaps with
the p+n junction region of the PiN power diode will increase the high-temperature
leakage current of the device and deteriorate the breakdown characteristics of the
diode.
The Field Shielded Anode (FSA) diode with anode region composed of a thin p+
region and a slightly thicker low-doped p region forming a PiN power diode of
p+pn
n+ structure can improve the breakdown characteristics. With proper
low-energy irradiation, the defect region containing a highly recombination center
can be only located in the thin p+ region without overlapping with the space charge
region of the pn junction, reducing the anode injection efficiency make reverse
recovery speed more faster, and also reduce the high-temperature leakage current,
improve the high-temperature breakdown voltage of the power diode [4].
16 Products of Power Devices 309

Changing the anode or cathode structure of the diode can also improve the
recovery speed of the high-power diode and reduce the switching power consump-
tion. Reducing the doping concentration of the anode and reducing its thickness can
reduce the minority sub-injection concentration in the on-state. Although the
on-state characteristics of the device are deteriorated, a faster reverse recovery
characteristic can be obtained, which can be used in switching and freewheeling
applications to reduce switching power consumption. The structure of the Self-
adjusting p+ Emitter Efficiency Diode (SPEED) is shown in the Fig. 16.3, a highly
doped p+ region is formed in the low-doped p-anode region by ion implantation [5].
At low-current density, the implantation efficiency of the pn junction is low, so
the on-state voltage drop is determined by the low forward voltage drop pn
n+
junction; at high current density, the high injection of the p+pn
junction produces
the conductance modulation effect which causes the diode’s voltage drop to be
determined by the p+ pn-n+ portion of the forward voltage drop. Since the SPEED
structure has a small change in forward voltage drop at high current density, it can
improve the device’s Surge Current capability and has a high reverse recovery speed
to serve as a typical fast recovery diode.
In addition, as shown in Fig. 16.4, the combination of PiN diode and Schottky
diode in parallel (Merged PiN and Schottky, MPS) can improve the blocking voltage
of Schottky diode and reduce the forward voltage drop [6]. The MPS diode is a fast
recovery diode, and it has advantages of both PiN and Schottky diodes.
The PiN diode does not conduct at low-current density, but when the current
density is increased, the p region will inject a large number of holes into the n
drift
region to produce a conductance modulation effect, causing the forward voltage to
drop and allowing a large current flow through a metal-semiconductor contact. The
conduction mechanism of the MPS diode changes with the gradual increase of the
applied forward voltage, and the unipolar operation state dominated by the initial
Schottky junction is converted into the bipolar operation state dominated by the pn
junction. When the MPS diode in reverse biased, the pn junction space charge region
expands into a single piece and shields the Schottky junction, so that the Schottky

Fig. 16.3 Schematic of the

self-adjusting p+ emitter
efficiency diode (SPEED)
310 X. Lin et al.

Fig. 16.4 Structure of MPS diode and work principle

junction no longer withstands the applied reverse bias voltage, while the barrier of
the reverse bias pn junction is subjected to the external reverse bias voltage to
improve the breakdown voltage of MPS diode. The MPS diode is a standard fast
recovery diode which has a bias voltage characteristic of withstand voltage and fast
recovery.
The main application of FRD is to combine with switching devices (such as GTO
thyristors, IGCT, IGBT, etc.) to convert DC signals and AC signals. Taking IGBT as
an example, IGBT can improve the utilization efficiency of power, and FRD can be
used as an auxiliary device for IGBT in reverse bias operation, which can increase
the stability and reliability of the system.

Thyristor

Thyristor, also known as Silicon-Controlled Rectifier (SCR), is a three-terminal

device with a pnpn four-level structure. Thyristor is capable of both forward
blocking and reverse blocking and applying a small gate current can trigger it to
enter the conducting state from the forward blocking state and maintain stable
conduction characteristics. When in the on-state, SCR can be regarded as a
conducting state PiN rectifier diode. The rated current of a single Power SCR has
reached 5000 A and the rated voltage can reach 8000 V, which means that the power
can reach 40 MW. Multiple Power SCRs in series can withstand more than 100 kV to
meet the needs of high-voltage power transmission. SCR can operate in a stable state
of high current and low voltage, or high voltage and low current. It has the
advantages of low-power consumption and high efficiency, which make it suitable
for AC power supply circuits and commonly used device in high-power electronic
systems. A variety of power electronics such as gate turn-off (GTO) thyristor and
integrated gate-commutated thyristor (IGCT) have been derived from SCR.
An n+pn
p+ thyristor is consisted of three pn junctions, J1, J2, and J3, as shown in
Fig. 16.5 [7]. When a negative voltage is applied to the anode of the thyristor, J1 and
J3 are reverse biased and J2 is forward biased so the thyristor enters the reverse
16 Products of Power Devices 311

Fig. 16.5 Circuit symbol, doping density, and structure of SCR

Fig. 16.6 Schematic of SCR in the forward blocking state

blocking state. Due to the high-doping concentration on both sides of J3, it can only
withstand lower voltage and therefore the negative voltage applied to the anode is
mainly withstood by J1. The doping concentration and thickness of the n
drift
region determine the reverse blocking voltage value of the Power SCR and a similar
base open bipolar transistor is formed between J1 and J2. The breakdown voltage of
the SCR is determined by the breakdown voltage of J1 junction in the base open pnp
bipolar transistor, but not the avalanche breakdown voltage of the pn junction. When
a positive voltage is applied to the anode, which is mainly withstood by the n
drift
region, J1 and J3 are forward biased and J2 is reverse biased so the thyristor goes into
the forward blocking state. The forward blocking voltage is determined by that the
breakdown voltage of J2 junction in the base open npn bipolar transistor, but not the
avalanche breakdown voltage of the pn junction [3].
The schematic of SCR in the forward blocking state is shown in Fig. 16.6. As
shown in the figure, the base of the npn transistor is connected to the collector of the
pnp transistor, and the base of the pnp transistor is connected to the collector of the
312 X. Lin et al.

npn transistor. In the forward blocking state, applying a small gate current IG
increases the base current IB2 of the npn transistor and the current gain, thus making
IC2 larger. Because IC2 is the base current IB1 of the pnp transistor, the increasing IB1
then amplifies IC1 of the pnp transistor and further a bigger IB2 is obtained. This
positive feedback forces the transistors into saturation region so that the three
junctions are all forward biased, at which point the SCR is conducting. Once the
SCR enters the on-state, even if the external gate current IG is cut off, the positive
feedback can still maintain the current flow.
The characteristic I-V curve of the Power SCR is shown in Fig. 16.7. A positive
voltage UAK applied across the SCR anode-cathode will make it enter the forward
blocking state. Though no gate trigger current (IG ¼ 0), when UAK is increased to
Breakover Voltage UBO, transition conduction will also occur, making SCR like a
diode. This type of pnpn two-side structure device (no gate) becomes a Breakover
Diode (BOD). The BOD can be used as an overvoltage protection device in
circuits. A gate trigger current IG applied to the SCR in the forward blocking
state can cause the transition conductance at a lower UAK. Therefore, it is available
to use IG to control the conductance timing of the SCR. A larger IG will lower the
transition voltage and lead SCR to conduction in advance. After the SCR is turned
on, the current IA does not change with IG. Even if the IG is lowered or removed,
the SCR can still maintain the conduction state through positive feedback. Cur-
rently, SCR works in a stable high current and low voltage state with low con-
sumption. Only the anode current IA is lower than the Holding Current IH, the SCR
will return to the blocking state. A negative voltage UAK across the SCR anode-
cathode will make it enter the reverse blocking state. By optimizing the width and
doping concentration of the p-base and the n
drift region, it is accessible to
increase the reverse blocking voltage, lower the leakage current and operational
power consumption as well as maintain the stable working state of SCR under high
voltage and small current.

Fig. 16.7 Characteristic I-V

curve of power SCR
16 Products of Power Devices 313

Power BJT

The traditional bipolar transistor is a current-driven amplifier, and the analysis of its
signal amplification characteristic is mainly based on small injection current. That
means, when the transistor is working in the common-emitter state, a small base
current can be input to control the collector current at the output end and obtain a
large power gain. Power bipolar junction transistors (Power BJT) work in the same
way as traditional bipolar transistors for signal amplification, but it can withstand
high voltage in the off-state. Therefore, a thick lightly doped n
drift region is added
between the p
base region and the n+ collector to block high voltage. When
conducting, it is in the state of large current injection. Large current injection in
the base and the collector regions will reduce the current gain of the Power BJT, so
the control circuit needs to provide a large current to drive the Power BJT, and the
design of the control circuit is more complicated and costly. In addition, the current
amplification factor and characteristic frequency of Power BJT decrease rapidly with
the increase of current. The increasing on-state voltage drop due to large resistance in
the n
drift region, as well as the storage charge injection and extraction during the
on and off processes all result in high-power consumption of the Power BJT. Though
the Darlington Configuration multistage power bipolar transistors can increase
current gain, the on-state voltage drop and power consumption increase dramatically,
thus increasing power consumption. At present, the blocking voltage of power
bipolar transistor can reach 1.8 kV, and the control current has reached 800 A [3].
The structure of the npn Power BJT is shown in Fig. 16.8, in which the n+
diffusion layer is the emitter, the p diffusion layer is the base, the n
epitaxial layer is
the drift region, and the n+ substrate is the collector. Like the function of the n
drift
region in a PiN device, the capability to withstand voltage of a Power BJT is
determined by the doping concentration and thickness of the n
drift region.
When a large current is injected into the base, it generates voltage drop in the base
region due to base resistance, causing the bias voltage of the central part of the n+p
junction between the emitter and base to be lower than that of the edge area, so the
emitter and collector current density is uneven, and the emitter edge close to the base

Fig. 16.8 Structure of npn power BJT

314 X. Lin et al.

Fig. 16.9 The design layout of npn power BJT

contact has a larger emitter current density. This is known as Emitter Current
Crowding. The Emitter Current Crowding can cause a sharp decrease of current
gain and also affect the power consumption of the Power BJT during on and off.
Therefore, as shown in Fig. 16.9, in the layout of the Power BJT, the interdigital base
is around the interdigital emitter to form a symmetrical Interdigitated Finger Geom-
etry, for not only reducing the Emitter Current Crowding effect of emitter current,
but also enhancing the heat dissipation capability of the device.
A Current Overshoot of the collector current IC will occur when a Power BJT
turns on and a Voltage Overshoot of the collector voltage UC will occur when it turns
off. The large current and voltage caused by these overshoot phenomena will
increase the power consumption of the Power BJT and the probability of destructive
device failure. When the Power BJT operates in the positive active region of the
characteristic curve, the emitter current with uneven current density distribution will
form a local thermal fluctuation on the emitter junction. The part with a higher
current density in the local area of the emitter junction has a higher temperature, so
that the Built-in Potential of the pn junction in this region decreases with the increase
of temperature, which promotes more current to be injected into the region and
increases the dissipation power. Therefore, the local temperature further rises, and
hot spots are generated inside the transistor due to positive thermal feedback on the
emitter junction.
The high temperature generated by the hot spots will sharply reduce the Built-in
Potential of the pn junction depletion region and short-circuit the collector, and the
transistor will enter the thermal low voltage and large current secondary breakdown
state. The transistor can be restored to work by adding a current-limiting protection
device to the external circuit. If the current protection device is not added, the
temperature of hot spots will rapidly rise and damage the material composition
and device structure, resulting in permanent damage to the power bipolar transistor.
In addition, in the case of high voltage and large current forward bias, the collector
current rise will lower the potential barrier of the p base and n
drift region and the
maximum electric field intensity will move to the n
/n+ junction, which produces
16 Products of Power Devices 315

avalanche collision ionization near it. Then the transistor enters the forward bias low
voltage and large current secondary breakdown state and is prone to destructive
failure.
Now when the power bipolar transistor is turned off, it is reverse biased. The
collector current will be immediately concentrated in the central region of the
emitter, making the current density in this region increase by more than ten times.
As the collector voltage reaches the peak, the transistor is in the reverse bias state of
high voltage and large current, and the electric field peak at this time appears at the
interface of the n
drift region and the n+ substrate. Electrons move toward the
collector at a saturation speed; this lowers the voltage of the collector junction J1,
increases the collector current, and leads to a reverse bias avalanche breakdown with
damages in the device. Because this breakdown is caused by that the peak electric
field moves from the J2 junction to the n
/n+ junction, resulting in the avalanche
region of the n
/n+ junction injecting holes into the collector region and causing the
low-voltage avalanche ionization effect, it is called reverse bias secondary break-
down. Introducing a buffer layer with a slightly higher doping concentration
between the n
drift region and the n+ substrate, or increasing the junction depth
at the edge of the strip emitter can reduce the peak electric field intensity at the
interface, so as to avoid the avalanche breakdown at low voltage.
The technology of power bipolar transistors is mature, but due to small current
gain and low input impedance, Power BJT has been gradually replaced by IGBT
with better performance for high-voltage applications.

Power MOSFET

Power metal-oxide semiconductor field-effect transistor (Power MOSFET) is con-

sidered as an ideal switching device because of its high input impedance, fast
switching speed, and negative temperature coefficient (the current decreases with
temperature increase). The Power MOSFET can be divided into Vertical Double-
diffused MOSFET (VDMOS) and Lateral Double-diffused MOSFET (LDMOS).
The source and drain of the vertical device are fabricated on the top and bottom
and on both sides of the wafer. Because current flows vertically through the wafer,
vertical devices are not suitable for ICs, and are typically encapsulated as discrete
devices that can withstand large currents. The structure of traditional VDMOS is
shown in Fig. 16.10. Ultra-high voltage devices (above 600 V) require an epitaxial
layer thickness of about 100 μm, and the on-state resistance is large. The structure of
the trench gate MOSFET is shown in Fig. 16.11. The trench gate MOSFET has a
higher channel density and a lower on-state resistance. Backside Grinding technol-
ogy can be used to grind the wafer thickness to less than 100 μm, which helps to
reduce the internal resistance of the trench gate MOSFET [3].
The structure of LDMOS is shown in Fig. 16.12. If the manufacturing process can
provide Shallow Trench Isolation (STI) structure, then STI can be added near the
trench in the drift region to enhance LDMOS’s capability to withstand voltage, as
shown in Fig. 16.13. LDMOS can be combined with integrated circuits. The device
316 X. Lin et al.

Fig. 16.10 Structure of

traditional VDMOS

Fig. 16.11 Structure of

trenched gate MOSFET

shown in Fig. 16.13 has a thickness of about 10 μm and can withstand voltage of
100–200 V. Combined with low-voltage control circuit and protection circuit; it can
be made into an intelligent power IC and a display drive circuit.
Ultra-high voltage LDMOS capable of withstanding voltage over 600 V requires
thick and long drift region (close to 100 μm). In 1979, Appels and Vaes proposed that
device characteristics can be optimized by employing a thin epitaxial layer and
depleting it completely into a space-charge region to get Reduced Surface Field
(RESURF) [8]. The schematic of device depletion in drift region is shown in
Fig. 16.14.
16 Products of Power Devices 317

Fig. 16.12 Structure of LDMOS

Fig. 16.13 Schematic of LDMOS with STI structure

Fig. 16.14 Schematic of LDMOS with thin epitaxial layer RESURF structure resulting in a
depleting drift region
318 X. Lin et al.

Fig. 16.15 Schematic of LDMOS with dual RESURF structure

Fig. 16.16 Schematic of LDMOS with ternary RESURF structure

This concept was followed by the development of multiple RESURF devices, as

shown in Figs. 16.15 and 16.16 [9, 10].
If a lateral ultra-high voltage device is integrated into an intelligent power IC, the
upper limit of its current is affected by the packaging process, usually about 2A.
The structure of the Super Junction (or superjunction) and the trench gate can be
fabricated in LDMOS. Similar device structures can also be fabricated by the SOI
process, as shown in Fig. 16.17.

Insulated Gate Bipolar Transistor

Insulated Gate Bipolar Transistor (IGBT) was invented by B.J. Baliga [11]. This
device solves the problem of large on-resistance of power MOSFETs in high-voltage
applications. The manufacturing process of IGBT has gradually matured since the
production in 1986. IGBTs are available in vertical (suitable as discrete devices of
high voltage and high current) and lateral (suitable for integration with ICs).
16 Products of Power Devices 319

Fig. 16.17 Structure of SOI LDMOS with superjunction drift region

Fig. 16.18 Vertical IGBT

structure diagram and
equivalent circuit

The vertical type device is shown in Fig. 16.18. It is formed by four layers of
alternating npnp semiconductors. The structure of the gate is the same as that of
VDMOS. However, the n+ drain of VDMOS is changed to p+ structure. When the
gate voltage control channel is turned on, the emitter electrons are injected into the
drain of the MOS structure via the channel. This electron current forms the base
current of the vertical pnp transistor, triggering the pnp transistor to turn on (see
Fig. 16.18a), leading the collector to inject holes to the upper emitter. The IGBT
amplifies the current of the VDMOS with a pnp transistor (the gain is β times), so
the on-current is larger than that of the VDMOS, i.e., the on-resistance is smaller.
When the gate voltage is turned off, the electron current of the MOS channel
disappears and turns off the pnp transistor. The switching of the entire device is
controlled by the gate voltage, but the IGBT device is a bipolar device. The holes
stored in the drift region need to be recombined as the reverse recovery of diodes.
Therefore, the operating frequency of IGBTs is usually lower than that of
MOSFETs. The central rectangular frame area in Fig. 16.18b is a parasitic thyristor
structure. Once this parasitic thyristor is turned on, the device current cannot be
turned off even if the gate voltage is turned off, and the gate will lose control. This
is the latch-up of IGBT which is like the CMOS latch-up effect. The parasitic
320 X. Lin et al.

thyristor operation must be suppressed in the device design to make IGBT work
like a transistor [3].
In accordance with the order of the structure and technique improvement, the
evolution of IGBTs is as follows.

1. Planar Punch-Through IGBT (PT-IGBT) appeared in 1988. The conduction

mechanism of the IGBT is different from that of the MOSFET, which can reduce
the on-resistance and solve the contradiction between the blocking voltage and
resistance. However, the main disadvantage is that the epitaxial layer acts as a
drift region, and the higher collector injection efficiency results in a larger
switching loss and a lower withstand voltage.
2. Improved Planar Punch-Through IGBT (Improved PT-IGBT) appeared in
1990. Compared with PT-IGBT, the electric field suspension technique is applied
in the improved structure, and the buffer layer with a doping concentration lower
than that of the heavily doped p+ region is used to cut off the electric field in the
buffer layer, which is advantageous for thinning the thickness of the base region
and alleviating the contradiction between withstand voltage and resistance, as
shown in Fig. 16.19.
3. Trench IGBT appeared in 1992. The direction of the channel changes from
surface parallel to vertical in the body (as shown in Fig. 16.20), which reduces
the influence of surface defects on the withstand voltage and reduces the device
area, so that the device can withstand a larger on-current per unit area. Both static
power and dynamic power have been greatly improved. A disadvantage of the
trench structure is that too dense current at the gate affects the short circuit
capability of the device.
4. Planar Nonpunch-Through IGBT (NPT-IGBT) was introduced in 1997. The
epitaxial layer of the traditional planar penetrating device is thin, and the electric
field intensity in the drift region is trapezoidal. The epitaxial layer of the

Fig. 16.19 Schematic of

improved planar punch-
through IGBT structure
16 Products of Power Devices 321

Fig. 16.20 Schematic

diagram of trench IGBT
structure

Fig. 16.21 Schematic diagrams of various vertical IGBT structures

conventional planar feedthrough device is thin, as shown in Fig. 16.21a. The

thickness of the overall device is large, and p+ substrate accounts for most of the
thickness.
Planar nonpunch-through IGBT uses a thinner n-type substrate, and the
electric field intensity in the drift region changes in a triangle shape. As
shown in Fig. 16.21b, the doping concentration of the collector region is
controlled by ion implantation. Thickness of the overall device is smaller, and
the doping concentration of the control collector region can reduce the carrier
injection efficiency of the collector. There is no need to use irradiation tech-
niques or doping gold and platinum to reduce carrier lifetime, optimizing the
322 X. Lin et al.

trade-off between on-state voltage drop and turn-off power. At the same time,
the base of the parasitic npn transistor becomes thicker, which can reduce the
current gain and has a positive temperature coefficient, which overcomes the
shortcomings of the conventional IGBT and is beneficial to the parallel opera-
tion of the device.
5. Planar Field-Stop IGBT (FS-IGBT) appeared in 2001 (see Fig. 16.21c). In order
to solve the problem that NPT-IGBT is difficult to be applied to high-voltage
places, FS-IGBT adds an n-type electric field cutoff layer with higher doping
concentration than the drift region at the bottom of the drift region, which is used
to cut off the electric field and reduce the injection efficiency of the collector.
Under the same withstand voltage conditions, the chip thickness required for the
FS-IGBT structure is reduced by 1/3 compared with the NPT-IGBT structure, and
there is no need to reduce the carrier lifetime.
6. Trench-Gate Field-Stop IGBT (TG FS-IGBT) was introduced in 2003 (see
Fig. 16.21d). TG FS-IGBT combines the advantages of the field stop layer and
the trench gate, and has become a mainstream.

If a portion of the collector p+ layer is changed to n+, the portion forms a

reverse-biased diode and is connected in parallel with the original IGBT. This
device is called a reverse-conducting IGBT (RC-IGBT) (see Fig. 16.22). There is
no need to connect an external parallel diode in the circuit system. The advan-
tages of RC-IGBTs are savings in package cost, smaller size, and improved
switching speed.
The Lateral IGBT (L-IGBT) structure is similar to the LDMOS except that the n+
drain is changed to the p+ structure, as shown in Fig. 16.23. L-IGBTs with a
withstand voltage of 200 V or less, the current increase is not greater than that of
LDMOS, but it is subject to the risk of latch-up and high-temperature instability. The
length of the L-IGBT with a blocking voltage of 600 V or more is greater than the

Fig. 16.22 Schematic of RC-IGBT structure

16 Products of Power Devices 323

Fig. 16.23 Schematic diagram of lateral IGBT structure

Fig. 16.24 Schematic

diagram of lateral SOI-IGBT
structure

thickness, and the horizontal electric field strength at the time of conduction may be
smaller than the vertical electric field strength, so that holes injected from the
collector are easily diffused into the substrate to form a leakage current. Therefore,
the research on L-IGBTs is more focusing on silicon-on-insulator (SOI) structures,
as shown in Fig. 16.24.

Wide-Bandgap Semiconductor Devices

In the design of the power device, the ratio of the breakdown and the Specific
On-State Resistance (unit: V/Ω cm2) can be used as the evaluation index. The higher
the value, the better is the characteristics of the device. The on-state characteristic
324 X. Lin et al.

resistance is defined as the device’s on-resistance multiplied by its top view area. The
on-resistance value determines the power loss and the breakdown voltage determines
the blocking voltage when the device is turned off. Theoretical derivation shows that
for the parallel electrode pn junction (one-dimensional electric field), the on-state
characteristic resistance of the ideal drift region is [3]

4BV2
Ron-ideal ¼
es μn E3C

where BV is the breakdown voltage; εs is the dielectric constant of the semicon-

ductor; μn is the electron mobility; Ec is the critical electric field strength causing the
2
breakdown. Ron-ideal ¼ e4BVμ E3
in the denominator is generally named as the Baliga’s
s n C

Figure of Merit (BFOM) of the power device. This is a sign of the influence of
semiconductor material properties on the resistance of the drift region. It can be seen
from the above equation that in a conventional one-dimensional electric field power
device, the on-state resistance is proportional to the square of the breakdown voltage
if the breakdown voltage is increased by a factor of two, then the on-state resistance
is increased by a factor of four.
Wide-bandgap semiconductors generally refer to silicon carbide (SiC), and
gallian nitride (GaN). Common parameters of semiconductor materials are shown
in Table 16.1.
If Baliga’s Figure of Merit of silicon, BFOM(Si), is 1, then BFOM(GaAs) is 15.6,
BFOM(SiC) is 528, and BFOM(GaN) is 718. At the same breakdown voltage, the
on-state characteristic resistance of a wide-bandgap semiconductor device is approx-
imately two-thousandths of the resistance of a silicon device.
A line graph as shown in Fig. 16.25 is drawn according to the formula at the
beginning of the section and the data of Table 16.1, wherein the line corresponding
to silicon is called the silicon limit. Researchers often plot the on-state characteristic
resistance and breakdown voltage of their products on a table to examine the gap
between their products and theoretical limits. Under a one-dimensional electric field,
when the drift region of the power device is parallel to the electrode, the relationship
between the Ron-sp and the breakdown voltage of the wide-bandgap semiconductor is
far below the silicon limit.

Table 16.1 Table of common parameters of semiconductor materials

Parameter Si GaAs 4H-SiC GaN
Eg/eV 1.12 1.43 3.26 3.50
μn/(cm2/(V  s)) 1400 8500 900 1250
μp/(cm2/(V  s)) 600 400 100 200
EC/(V/cm) 0.3  106 0.4  106 3.0  106 3.0  106
vgal/(cm/s) 1.0  107 2.0  107 2.7  107 2.7  107
εS 11.8 12.8 9.7 9.5
Note: The values will vary under different conditions.
16 Products of Power Devices 325

Fig. 16.25 Relationship

between Ron-sp and
breakdown voltage of
different semiconductors

Fig. 16.26 Comparison

between superjunction
structure and traditional
structure

Superjunction Thyristor

The super junction (or superjunction) of semiconductor power devices was invented
in 1993 by Xingbi Chen, University of Electronic Science and Technology of China,
the basic structure is shown in Fig. 16.26a [12]. The VDMOSFET with the super-
junction structure as the drift region is shown in Fig. 16.27. The theoretical basis is
that when the doping concentration of the n
region and the p
region is equal, and
the volume is also equal, the positive and negative charges are completely canceled,
which is equivalent to a semiconductor with extremely low impurity. Essentially, the
thickness of the drift region can be much smaller than the thickness of a conventional
device, and the on-state resistance is much smaller. The 600 V VDMOSFET with
superjunction has a drift region thickness of approximately 20 μm and an
on-resistance of 20% of a conventional 600 V device.
326 X. Lin et al.

Fig. 16.27 VDMOSFET

with superjunction structure
as drift region

Since the built-in electric fields of the n
region and the p
region are horizontal,
when a voltage is applied to the device (vertical direction); a two-dimensional
electric field is formed in the drift region. Theoretical derivation shows that the
relationship between the on-state characteristic resistance and the breakdown voltage
of this type of device is

2BVp
Ron-sp ¼
eS μn E2C

where p is the sum of the width of n
region and p
region [3]. The relationship
between the Ron-sp and the breakdown voltage of the superjunction device is shown
in Fig. 16.28. Because of the multidimensional electric field, its characteristics have
exceeded the silicon limit of the one-dimensional electric field, but still not as wide-
bandgap devices.
The superjunction can be used for both the drift region of a vertical IGBT and the
drift region of a lateral device. The lateral thyristor structure with superjunction drift
region is shown in Fig. 16.29.

Gate Turn-Off Thyristor

The current amplification factor and on-state characteristics of bipolar power tran-
sistors decrease rapidly with the increase of voltage level, thus inhibiting the
development of bipolar power transistors in applications with voltage higher than
2 kV, such as electric locomotives. In DC circuits, the need to design thyristor
structures so that gate signals can be used to control the opening and closing of
thyristors promotes the development of gate turn-off (GTO) thyristors. The turn-off
of GTO thyristor is achieved by applying a large reverse current. The gate current
must be large enough to eliminate the charge stored in the p-base region and to stop
the internal transistor coupling to turn off the current [3]. Such devices have an upper
16 Products of Power Devices 327

Fig. 16.28 Diagram of the relationship between Ron-sp of superjunction device and breakdown
voltage

Fig. 16.29 Lateral thyristor

structure with superjunction
drift region

current limit called the maximum switchable current or the maximum controllable
current. When the current exceeds this limit and a larger back-gate current is applied
to turn off the device, it will lead to the p-type base region to conduct with the n+
cathode and fail to turn off the current. The maximum switchable current density of
GTO thyristor is about 1000 A/cm2, and the maximum turn-off gain (the ratio of the
device current to the reverse gate current) is about 5.
The structure and electric field distribution of a symmetric GTO transistor are
shown in Fig. 16.30. Although similar to the traditional thyristor structure, the GTO
structure does not include cathode short connection. In the case of forward bias, the
328 X. Lin et al.

Fig. 16.30 Structure and electric field distribution of a symmetrical GTO thyristor

Fig. 16.31 Structure and electric field distribution of an asymmetric GTO thyristor

voltage drop is across the p-type base/n-type base junction. The forward blocking
capability is determined by the breakdown voltage of the transistor npn with base
region open circuit, which is consistent with the traditional thyristor. In reverse bias,
the voltage drop is mainly concentrated across the p+ anode-n base junction.
Because GTO thyristor is used in DC circuit, its reverse blocking capability does
not need to be as strong as its forward blocking capability. The structure and electric
field distribution of asymmetric GTO thyristors are shown in Fig. 16.31. An n-buffer
layer is added to the n-base region adjacent to the p+ anode region, as shown in
Fig. 16.31a. The doping concentration of the n-buffer layer is much higher than that
of the lightly doped portion in the n-base region. The trapezoidal electric field
distribution of an asymmetric GTO thyristor is shown in Fig. 16.31b. To obtain
16 Products of Power Devices 329

the same forward blocking voltage, the net thickness of the n-base region in the
asymmetric GTO thyristor is smaller than that of the n-base region required for the
symmetric GTO thyristor, which will reduce the on-state voltage. At the same time,
the n-buffer layer also reduces the current amplification factor of the pnp transistor,
which can increase the turn-off gain of GTO thyristor. The n-buffer layer is usually
shorted to the anode to reduce the turn-off time.
GTO thyristor can turn off the current in the DC power circuit, so GTO thyristor
has been used to control the drive current in the motor drive equipment of the electric
locomotive. These new generations of motor drive equipment are widely used in
high speed rail transport systems.

Integrated Gate-Commutated Thyristor

Integrated gate-commutated thyristor (IGCT) is a power semiconductor electronic

device for switching currents in industrial equipment, which was jointly developed
by Mitsubishi and ABB. The basic structure of IGCT is shown in Fig. 16.32. IGCT is
similar to GTO thyristor, but there are multiple gates in parallel.
IGCT can be controlled to turn on and off by the gate signal, has lower conduction
loss than GTO thyristor, and can withstand higher voltage rise rates, making a buffer
unnecessary for most applications.
In IGCT, the switching-off current is larger than the anode current due to the
parallel connection of multiple gates, which shortens the time for eliminating a few
carriers completely and makes the IGCT device switching-off faster. Also, the
inductance and resistance connected to the gate driving circuit become lower
because of the parallel connection of the gates [13]. Compared to GTO thyristors,
an IGCT has faster turn-off time, so it can work at frequencies up to several kHz in a
short period of time.

Fig. 16.32 Basic structure

of IGCT
330 X. Lin et al.

Fig. 16.33 Structure

comparison between GTO and
S-IGCT

IGCT can be fabricated into devices with or without reverse blocking capability.
However, due to the need for a long and low-doped drift region to improve the
reverse blocking ability, it will increase the forward voltage drop. IGCT capable of
preventing reverse voltage is called symmetrical IGCT (S-IGCT), and its structure is
in analogous to the electric field distribution and GTO thyristor, as shown in
Fig. 16.33. Normally, the reverse blocking voltage rating of S-IGCT is the same as
that of forward blocking voltage rating. A typical application for S-IGCT is a current
source inverter.
The IGCT, which cannot block the reverse voltage, is called asymmetric IGCT
(A-IGCT). It usually has a reverse breakdown voltage of several tens of volts.
However, the forward voltage drop is lower than that of S-IGCT since the drift
region is shortened by the addition of the n-type buffer layer. A-IGCT is used in
parallel application of reverse conducting diode (e.g., in a voltage source inverter) or
in the absence of reverse voltage (e.g., in a switching power supply or DC traction
chopper).
If the p+ collector is partially changed to an n+ region, the portion becomes a
reverse conducting diode in parallel with the IGCT. Asymmetric IGCT fabricated
with reverse conducting diode in the same package is called RC-IGCT, which is an
IGCT used for reverse conducting.
IGCT is mainly used in variable-frequency inverters, drives, and tractions, for
example, in a motor-driven towing vehicle.

Emitter Turn-Off Thyristor

Emitter Turn-Off (ETO) thyristor has the ability to block high voltages and high
currents of the gate-off thyristor and the advantages of easy control of the MOS gate.
Other features include high-voltage current rectification capability and device
16 Products of Power Devices 331

Fig. 16.34 Structure and circuit symbol of ETO thyristor

current sensing capability. The structural schematic diagram and circuit symbol of
ETO thyristor are shown in Fig. 16.34.
As shown in Fig. 16.34, VQG acts as a gate switch and is connected to gate 1. ETO
thyristor is a power device consisting of an emitter switch, that is, a low-voltage
MOSFET (VQG is a pMOSFET, VQB is an nMOSFET) and a GTO thyristor in series.
A positive voltage is applied on gate 2 and gate 3 to turn on the device. At this point,
VQG is turned off, VQB is turned on, and the cathode voltage is applied to the GTO
thyristor by VQB to turn on the GTO thyristor. When negative voltage is applied on
gate 2 and gate 3, the device is turned off. At this time, VQB is turned off and VQG is
turned on, and the current of GTO thyristor flows to the cathode through the gate
1 and VQG. Since the current from the anode flows only through the pnp transistor
without flowing through the first pn junction J1, the positive feedback loop of the
GTO thyristor is destroyed, causing the device to turn off [14].
In open pnp mode, turning off npn transistor is the key to achieving high speed
and large cutoff current capability. ETO thyristors use anode current to provide
shutdown energy. Compared with IGCT technology, ETO thyristors greatly save the
driving power required for high-frequency operation. Both turn-on and turn-off are
controlled by the gate voltage of low-voltage MOSFET.

MOS-Controlled Thyristor

MOS-controlled thyristor (MCT) is a power device combining a bipolar power

transistor and a MOS power transistor. The two MOS gates are mainly used to
control the conduction current of the thyristor to obtain better turn-off characteristics
[15, 16]. As shown in Fig. 16.35a, one MOS is used to turn on the device and the
other is used to turn off the thyristor. MCT not only provides the working charac-
teristics of bipolar technology and MOS technology, but also provides a suitable
332 X. Lin et al.

Fig. 16.35 MCT structure and equivalent circuit diagram

alternative for existing power devices. MCT is a new kind of composite device that
combines the high-power handling capability of thyristors with the ease of control
and high speed of MOS gate devices [17].
MCT technology is compatible with IC technology as illustrated in Fig. 16.35a
with one of the cells and Fig. 16.35b its equivalent circuit. A small MCT has about
10,000 cells. As seen by the equivalent circuit, the gates of the two MOSFETs are
connected to the gate (G) of the MCT. When the gate voltage is biased positive with
respect to the cathode, the nMOSFET is turned on (the pMOSFET is off) and the
current flows from the anode into the base of the npn transistor to turn the device
on. When the device is turned on, the voltage of the anode is only slightly higher than
the cathode voltage. At this time, if the gate voltage is negative relative to the anode,
the pMOSFET is turned on, and the current flows directly to the anode through the
pMOSFET without passing through the emitter junction of the pnp transistor. Then
the positive feedback of the thyristor is closed due to being destroyed. If there is only
one MOSFET in the power device that triggers the turn-on thyristor without the
MOSFET that turns off the thyristor, the device is called a MOS-gated thyristor
(MGT).
The advantages of MCT: ① High voltage and high current; ② Low on-state
voltage drop (1/3 of IGBT, about 1.1 V); ③ Extremely high di/dt and dv/dt tolerance
(di/dt ¼ 2000 A/μs, dv/dt ¼ 20,000 V/μs); ④ High switching frequency, low power
consumption; ⑤ High operating temperature (above 200  C); ⑥ Simple gate drive
circuit; ⑦ Device is not closed broken and damaged.
A Power BJT has the ability to pass high currents and withstand high voltages.
The strong conductivity modulation effect by the high current injection can lead the
BJT at a lower on-state voltage drop, so the conduction power consumption is lower.
BJT power devices are minority carrier transport devices with long minority carrier
16 Products of Power Devices 333

storage time, resulting in slower switching speed of the devices; and because they are
current control devices, the matched drive circuits are relatively complex.
In contrast, MOS power devices are based on majority carriers, so the switching
speed is very fast. In addition, the input impedance of MOS power device is
capacitive with high impedance, and the switching of the device is controlled by
voltage, so the design and manufacture of driving circuit are very simple. Especially
when operating at low frequencies, compared with the BJT power device, there will
be faster switching speed. The MOS power device has a temperature coefficient of
positive resistivity, and since there is no phenomenon of conductivity modulation,
the MOS power device has a large on-resistance Rds at a high voltage.
As MCT is a BJT-MOS composite device that combines the advantages of BJT
power devices and MOS power devices in operation, it is suitable for low frequency,
high voltage, and high power applications. Its voltage blocking capability can reach
10 kV. However, the energy consumption during switching transient limits the
maximum operating frequency of MCT structure (less than 100 kHz).
Compared with the structure of GTO device, the advantage of MCT structure is
that the gate control circuit matching its MOS gate structure is relatively simple, and
because the shunt path is short, the anode voltage of MCT can begin to rise
immediately after the gate voltage reaches the negative gate power supply voltage,
so the charging interval during the shutdown process is shorter. Compared with
IGBT, MCT has smaller on-state voltage drop and better power loss curve, but lacks
a forward-biased full-working area, so it is difficult to replace IGBT.

References
1. C. Wang, New Devices of Power Semiconductor and Its Manufacturing Technology (China
Machine Press, 2015). ISBN 9787111475729
2. Power Devices. https://en.wikipedia.org/wiki/Power_semiconductor_device. Accessed
21 Feb 2020
3. B. Jayant Baliga, Ch. 5, P-i-N rectifiers, in Fundamentals of Power Semiconductor Devices
(Springer, Raleigh, NC, USA, 2008), pp. 203–276
4. S. Matthias, J. Vobecky, C. Corvasce, et al., Improved recovery of fast power diodes with self-
adjusting p emitter efficiency. Proc. ISPSD 88–91 (2011)
5. H. Schlangenotto, J. Serafin, F. Sawitzki, et al., Improved recovery of fast power diodes with
self-adjusting p emitter efficiency. IEEE Electron Device Lett. 10(7), 322–324 (1989)
6. B. Jayant Baliga, Ch. 4, Schottky rectifiers, in Fundamental of Power Semiconductor Devices
(Springer, Raleigh, NC, USA, 2008), pp. 167–200
7. K. K. Ng, Complete Guide to Semiconductor Devices, 2nd edn. (Wiley, New York, NY, USA,
2002)
8. J.A. Appels, H.M.J. Vaes, HV thin layer devices (RESURF devices), Proceedings of the
International Electron Devices Meeting (1979), pp. 238–241
9. M.M. De Souza, E.M. Sankara Narayanan, Double RESURF technology for HVICs. Electron.
Lett. 32, 1092–1093 (1996)
10. M. Qiao, Y. Li, X. Zhou, et al., A 700-V junction-isolated triple RESURF LDMOS with n-type
layer. IEEE Electron Device Lett. 7(35), 774–776 (2014)
11. B. Jayant Baliga, Enhancement and depletion mode vertical channel MOS-gated thyristors.
Electron. Lett. 15, 645–647 (1979)
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12. X. Chen, Semiconductor Power Devices with Alternating Conductivity Type High-Voltage
Break Down Regions, US Patent, 5216275 (1993)
13. Integrated gate commutated thyristors. https://en.wikipedia.org/wiki/Integrated_gate-commu
tated_thyristor. Accessed 21 Feb 2020
14. B. Zhang, A.Q. Huang, Y. Liu, et al. C. IEEE Conference Record of the 2002 IEEE Industry
Applications Conference (2002), pp. 559–563
15. V.A.K. Temple: J. IEEE Electron Device Meeting, Abstract 10.7:282–285 (1984)
16. M.K. Kazimierczuk, N. Thirunarayan, B.T. Nguyen, et al., R/OL. AIP Conf. Proc. 271,
459–468 (1993). https://doi.org/10.1063/1.43187
17. B. Jayant Baliga, Advanced High Voltage Power Device Concepts (Springer, Raleigh, NC,
USA, 2011)
Products of Optoelectronic Devices
17
Yizhe Sun, Wen Yu, Letao Zhang, and Shengdong Zhang

Contents
Optoelectronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Avalanche Photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Organic Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Active Matrix Organic Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Micro Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Quantum Dot Light-Emitting Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Thin-Film Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Laser Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Photomultiplier Tube (PMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Infrared Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Optical Communication Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

Abstract
The optoelectronic devices refer to those functional devices, whose operation
principles are based on photon-electron or electron-photon conversion effects,
e.g., photovoltaic, photoconductive, and photoelectron emission effects.
According to the working mechanism and applications, these optoelectronic
devices are mainly classified into three categories. The first is photodetector or
photoelectric receiver. The second is the electroluminescent device that realizes
the conversion of electrical signal to optical signal. The third is the solar cells that
convert solar energy into electricity and storage. The basic structures and working
principles of these devices are briefly described in this chapter.

Y. Sun · W. Yu · L. Zhang · S. Zhang (*)

Electronic and Computer Engineering, Peking University, Shenzhen, China
e-mail: zhangsd@pku.edu.cn

© Publishing House of Electronics Industry 2024 335

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_17
336 Y. Sun et al.

Keywords
Photon-Electron Effect · Electron-Photon Effect · Photodetector · Electro-
Luminance · Solar Cell

Optoelectronic Devices

The optoelectronic devices refer to those functional devices with photon-electro

(or electro-photon) conversion effect as the working principle. As early as 1873,
Willoughby Smith [1] discovered the photoelectric phenomena of semiconductor
selenium (Se), 74 years before the invention of transistor in 1947. This led to the
application of selenium photovoltaic cells. However, due to the limited knowledge at
that time, the development of optoelectronic devices was relatively slow. In 1887,
Heinrich R. Hertz, a German physicist, observed the escape of electrons from the
surface of an object under light radiation in his electromagnetic wave experiments,
thus this revealed the physical basis of optoelectronic devices – the photoelectric
effect. In 1916, Albert Einstein perfected the basic principle of photon-object
interaction based on quantum theory, presenting the essence of photoelectric effect
to the world; because of this, he won the Nobel Prize in physics 1921. After the
1930s, the research on the physical properties of semiconductor, especially the
optical properties of semiconductor, has further consolidated the physical basis of
optoelectronic devices.
Photoelectric effect is divided into photovoltaic effect, photoconductive effect,
and photoelectron emission effect. According to the difference of working mecha-
nism and application, optoelectronic devices are mainly classified into three
categories.

1. The first category includes photodetectors or photoelectric receivers, such as

Avalanche Photodiodes (APDs), which are widely used in sensing, detection,
and communication fields today. Under radiation conditions, the electrical prop-
erties of these devices can be changed, so that the detected optical signals can be
converted into electrical signals, and the required information can be obtained
through the analysis results of electrical signals.
2. The second kind of device realizes the conversion of electrical signal to optical
signal, namely electroluminescent device, Light-Emitting Diode (LED), and
Laser Diode (LD) are typical examples. LED have many advantages, such as
long life, low cost, wide spectrum range, etc., and they are widely used in display
and lighting fields. LD has narrow spectra and strong directivity, they are widely
used in large-capacity, long-distance optical fiber communication systems, and
optoelectronic integrated circuits.
3. The third kind of devices, typically represented by photovoltaic devices (PV) or
commonly known as solar cells, can convert light energy into electricity and store
it. They can directly convert solar energy into electricity with high efficiency,
providing permanent power with low operating cost.
17 Products of Optoelectronic Devices 337

Nowadays, optoelectronic devices have penetrated every corner of society and

life, such as remote sensing, guidance, infrared detection, medical detection, mobile
phone, camera, display, and so on. Their applications have expanded from military
defense to civilian products, with their corresponding industrial structure and scale
increasingly large. At the same time, a variety of high-performance optoelectronic
devices will continue to emerge with continuous discovery of new technologies,
materials, principles, and applications.

Photodiodes

Photodiodes (PDs) are usually composed of a pn junction that generates photocur-

rents under incident light. I-V characteristics of PD are shown in Fig. 17.1. Under
reverse bias, the current is small in dark. The dark current, which is called reverse
saturation current, maintains its level before it reaches reverse breakdown voltage.
Under illumination, electron-hole pairs (EHPs) are generated in the semiconductor.
Since EHPs remain inside the semiconductor, this is called the internal photoelectric
effect. Under bias condition, the electron and holes generated in the pn depletion
region rapidly drift toward the opposite direction of polarity, whereas the EHPs
within a diffusion length to the depletion area enter the depletion area through
diffusion and drift mechanism, which also generates photocurrent. Since there is
no electric field in the area far away from the depletion area, the EHPs generated
there cannot contribute as photocurrent and generally disappear by recombination.
The greater the intensity of the illumination, the more EHPs are generated, and the
larger the reverse current is formed, as illustrated in Fig. 17.1.
In the manufacturing process, to improve the light absorption efficiency, the area
of the pn junction should be larger. Since most light is absorbed at the surface, the
position of the pn junction should be as close to the surface as possible. High-quality
semiconductor materials with low defects are necessary to form photodiodes with

Fig. 17.1 The I-V properties

of photodiodes
338 Y. Sun et al.

low dark current. Therefore, the rapid development of semiconductor epitaxial

growth technology plays an important role in improving the performance of photo-
diode detectors by eliminating defects in epi-layer.
Due to the advantages of small size, low cost, good linearity, wide response in
spectral range (190 nm to 1100 nm), low noise, high reliability, long life, and low
voltage power supply, silicon pn photodiode plays an important role in optical
communication, camera, video equipment, and photodetection. However, pn photo-
diodes still suffer from disadvantages such as low sensitivity, insufficient detectivity,
and slow response. The emergence of PiN (p-i-n bipolar) photodiodes can solve
these problems. Photodiodes have a wide range of applications and commercial
values in ultraviolet (UV) detection, visible light detection, infrared (IR) detection,
and X-ray imaging. Different materials are suitable for certain detections, depending
on their band gap width. High-quality germanium (Ge) single crystal materials are
widely used around the area of near infrared (NIR) detection because of their high
sensitivity. This detector generally needs to be cooled to 77 K to reduce the dark
current, which increases the cost and limits its applications. With the continuous
development of Ge technology on Si substrates, the process cost of Ge photodiodes
has been greatly reduced, and its application has been extended to the area of optical
communications [2].
Due to their wide linear dynamic range, photodiodes are commonly used as
optical power meters in the market, which can detect light with various wavelength.
If a narrow-band semiconductor photodiode is used to detect ultraviolet light, it is
necessary to use a filter to block visible light. Meanwhile, it requires cooling to
reduce the dark current. If wide-band semiconductor photodiodes are adopted, the
above problems do not exist, but suitable substrate with advanced epitaxial growth
technology is required. In medical X-ray imaging technology, photodiodes can be
used in the direct or indirect detections. In the case of indirect detection, X-rays are
usually absorbed by a thick layer of scintillator material and then converted to visible
or ultraviolet light, which is detected by photodiode devices.

Avalanche Photodiode

Avalanche Photodiode (APD) is a photodiode with a high-current amplification gain.

As shown in Fig. 17.2, under reverse bias, the electric field in the depletion region
increases with the increase of the applied voltage, and the drifting speed and kinetic
energy of the carrier in the depletion area also increase accordingly. When the kinetic
energies of electrons or holes reach a certain level, collision ionization occurs [3].
That is, electrons or holes with high energy colliding with the lattice, which break
their chemical bonds, creating new electronic-hole pairs, and the new electron-hole
pairs continue to accelerate under the electric field and collide with the lattice again.
This process forms positive feedback and continues, resulting in an effect that is
similar to the avalanche, which brings a photoelectric response with high internal
gain. The main difference between APDs and ordinary photodiodes is that after the
17 Products of Optoelectronic Devices 339

Fig. 17.2 (a) Structure of

avalanche photodiodes. (b)
The distribution of electric
field

semiconductor absorbs one photon, it creates more than one pair of electron and
hole, i.e., the quantum efficiency is greater than 1. The multiplication factor M is
used to measure its photoelectric gain, which is defined as:

i
M¼ ,
i0
where i is the output current, i0 is the original current before avalanche effect takes
place.
In order to ensure a uniform multiplication of carriers throughout the whole
photosensitive area, the semiconductor material must have no defects and the
interface must be smooth. To obtain low-noise avalanche photodiodes, the rate of
ionization between electrons and holes should be large. Silicon has a high ionization
rate ratio (≈20), so it is an ideal APD material. However, most III-V semiconductors,
such as indium gallium phosphate (InGaAsP), have an ionization rate ratio of
approximately 1. Usually by adopting a super-lattice structure, the III-V semicon-
ductor ionization rate ratio can be improved to achieve a low-noise avalanche
photodiode [4].
In terms of photodetection, the detection of long wavelength photons, such as
infrared, mainly uses narrow-band semiconductors such as germanium, indium
gallium arsenic (InGaAs), and mercury cadmium telluride (HgCdTe). Polycrys-
talline silicon carbide materials (4H-SiC) with a band gap of 3.36 eV are widely
adopted for UV detection that is close to visible blindness. Compared with gallium
nitride (GaN), SiC is relatively more mature for manufacturing; it has superior
thermal stability and high dissociation rate ratio [5]. In recent years, avalanche
photodiodes have been increasingly applied in commercial, military, and scientific
research applications. Compared with PiN photodiodes, APDs can detect light with
lower intensity and can meet the demands of long-range optical communication and
340 Y. Sun et al.

optical path testing; nonetheless, they require more stringent requirements for bias
and temperature stability.
Because of its high sensitivity and fast response, APD has attracted lots of
attention around the area of photon counter in recent years. Photomultiplier tube
(PMT), which is a vacuum-based device, was first applied to photon counter. The
appearance of APD devices has turned solid single-photon detectors into reality.
Silicon-based single-photon APDs can achieve high-efficiency, low-noise visible
photon counter. However, due to the lack of ideal IR absorption materials, the current
performance of IR photon counter is not as good as that of visible photon
counters [6].

Light-Emitting Diode

Light-Emitting Diode (LED) is a diode that emits specific wavelength of light by the
recombination of electrons and holes. The common white light is composed of red,
green, and blue lights. The energy of radiated photons, i.e., wavelength of the light,
is determined by the bandgap of the semiconductor. Therefore, the development of
LED is mainly focused on materials with various bandgap. Nick Holonyak from the
American General Electric Laboratory fabricated GaAsP-based red LED for the first
time in 1962 [7]. The GaP-based green LED was fabricated and reported in 1968 [8].
However, the white light could not be obtained due to the technical difficulty of
fabricating blue LED before 1990. At the beginning of 1990s, the LED technology
achieved a breakthrough, the blue LED was successfully fabricated [9] by Shuji
Nakamura, Isamu Akasaki, and Hiroshi Amano, who won Nobel prize in physics
2014. Nowadays, LEDs have been widely applied in house lighting, pilot lighting,
back light of liquid crystal display (LCD), and so on.
The physical principle of LED is shown in Fig. 17.3. When the p-type and n-type
semiconductors are brought together, the holes in p-type or the electrons in n-type
semiconductor material will diffuse toward the other side because of the concentra-
tion gradient. A space charge area is thus formed at the interface, leading to the drift
of the holes or electrons against the diffusion direction as well. Diffusion and drift
current will be finally balanced. If a positive voltage is applied to the p-type material,
the built-in electric field will be weakened, leading to increased diffusion current.
The outcome is large amount of electrons and holes will be recombined, resulting in
light emission.
The structure of a LED is far more complicated than the one shown in Fig. 17.4.
This is because luminous efficiency of a simple pn structure is quite low; or even
worse, the efficiency will further reduce with increased injected current. Taking blue
LED case for example, a practical device structure is shown in Fig. 17.4: a Multiple
Quantum Well (MQW) is inserted between p-GaN and n-GaN to improve the
combination efficiency of electron-hole pairs. Besides, to achieve better luminous
efficiency, p(n)-type AlGaN will be introduced between the MQW and the p(n)-type
GaN so to further confine the injected electrons and holes.
17 Products of Optoelectronic Devices 341

Fig. 17.3 Schematic of LED

Fig. 17.4 Structure of

blue LED
342 Y. Sun et al.

Organic Light-Emitting Diode

An organic light-Emitting diode (OLED) is a light-emitting diode (LED) device

based on organic semiconductors. The discovery of OLED can be traced back to the
observation of the phenomenon of light emission of organic materials biased at a
high voltage in the 1950s [10]. In 1983, Ching W. Tang et al. fabricated a hetero-
junction OLED and proposed a method for manufacturing small-molecule organic
phosphorescent emitting layers [11, 12]. Since then, the OLED research boom has
been kicked off. In 1990, the discovery of electroluminescence of polyphenylene
vinylene (PPV) further promoted the research of polymer OLED [13]. In 1998, the
discovery of phosphorescent materials greatly improved the quantum efficiency of
OLED devices [14], which led to a breakthrough in the research of polymer OLED.
Nowadays, phosphorescent OLED has become the basic technology for energy-
saving light sources and low-power flat panel displays (FPDs).
A typical small molecule OLED device has two layers of organic materials
located between the anode and cathode as shown in Fig. 17.5. When an OLED is
forward biased, holes in Hole Transport Layer (HTL) and electrons in Electron
Transport Layer (ETL) transport to the interface of HTL and ETL and accumulate
at the interface. An exciton is formed after recombination of an electron and a hole.
When excitons return to the ground-state energy level, they release photons. Shown

Fig. 17.5 Schematics of small molecule OLED: (a) structure; (b) energy band

Fig. 17.6 Schematic of

polymer OLED
17 Products of Optoelectronic Devices 343

in Fig. 17.6 is the schematic of a single-layer polymer OLED. Under forward bias,
electrons and holes recombine after transporting in the polymer layer, and then
excitons are formed.
As a new type of energy-saving light source, OLED lighting meets the standard of
green lighting. A major advantage of OLEDs is that they can be produced using a
thin film deposition process. In addition, OLED lighting is surface-emitting light
source, so that a more uniform illumination effect can be achieved. Companies such
as LG in Korea, Sumitomo Chemical in Japan, and Philips in the Netherlands have
exhibited products related to OLED light sources. In the next few years, OLED
lighting products may usher in rapid development. However, OLEDs still have lower
luminous efficiency, and the lifetime of the shortest-lived blue OLEDs in
RGB-OLED is estimated to be about 10,000 h. With the development of technology
and the improvement of material properties, blue OLEDs are expected to meet the
life expectancy of 40,000 h.
Another important application of OLEDs is for flat panel display. Compared with
traditional LCD displays, OLED display panels do not require a backlight and can be
thinner, more energy saving, and portable. In addition, flexible and curved display
can be realized. In recent years, with the extensive applications of OLED panels in
smart phones, televisions, and other fields, OLED market is rapidly developing. For
instance, the current displays for big three of Virtual Reality (VR) products are Sony
PlayStation VR, Oculus Rift, and HTC Vive displays all adopt OLED technology.
Since the OLED requires current driving, the driving device, that is the thin-film
transistor (TFT), is required to have high field-effect mobility. The field-effect
mobility of the current mainstream amorphous-silicon TFTs cannot meet the require-
ments of OLED displays. Although the polysilicon TFTs have higher mobility, they
mainly are limited in small-sized panels due to the poor large-area uniformity.
Besides, the metal oxide TFT technology can meet the requirements of OLED
displays.

Active Matrix Organic Light-Emitting Diode

The active matrix organic light-emitting diode (AMOLED) display is a rising

display technology. The active matrix (AM) and organic light-emitting diode
(OLED) respectively refer to active matrix addressing technology, and organic-
based electroluminescent device. Compared with the incumbent liquid crystal dis-
play (LCD), AMOLED technology possesses significant advantages, such as faster
response, higher contrast ratio, wider viewing angle, capability of
low-temperatures(40  C) operation, etc. As a promising candidate of future dis-
plays with great potential and broad market prospects, AMOLED display features
are well broadcasted [15].
Each pixel of AMOLED consists of two thin-film transistors (TFTs) respectively
for addressing and driving the OLED. The TFT circuits are prepared on the glass
substrate to form AM, and the OLED is prepared on top of or next to the TFTs.
Unlike the voltage-driving LCD, the brightness of current-driving OLED is directly
344 Y. Sun et al.

Fig. 17.7 Comparison of light-emitting principle between TFT-LCD and AMOLED

determined by the current of driving TFT. Therefore, the pixel circuit needs a TFT
gating circuit of switching function and also a TFT drive circuit to provide current
for OLED.
Figure 17.7 shows the schematic cross sections of TFT-LCD and AMOLED.
Since the liquid crystal does not have self-luminous capability, a backlight is
necessary in the TFT-LCD. For AMOLED, three separate stacks of red, green, and
blue electroluminescent materials work together to form a true color. In addition,
without additional backlight source, the self-luminous AMOLED display is more
energy efficient and thinner [16, 17]. Two kinds of AMOLED luminescent structures
are comparatively illustrated in Fig. 17.8. In the bottom emission structure, the pixel
circuits cannot become effective display region, resulting in a low aperture ratio. In
contrast, since the OLED in top emission structure can cover all pixel regions, a high
aperture ratio can be readily achieved, thus enabling this structure the focus of
display research.
For the current smartphone market, there are a considerable number of products
equipped with AMOLED screen with a continuously rising market share. In the
fields of wearable devices and virtual reality, AMOLED screen shows great pros-
pects due to its thinness, flexibility, and low-power consumption [18].
17 Products of Optoelectronic Devices 345

Fig. 17.8 Two luminescent structures of the AMOLED

Micro Light-Emitting Diode

Micro Light-Emitting Diode (MicroLED), also known as micro-LED, mLED or

μLED [19], is a miniaturizing and matrixing technology of Light-Emitting Diode
(LED). Specifically, it enables the integration of the originally large LED onto the
chip by using the micromachining technology, forming a high-density pixel matrix
with the pixel pitch reduced from millimeter level to micrometer level and each pixel
independently addressed and lightened.
Since 1990s, the liquid crystal display (LCD) technology has become the focus of
display industry, with the LED panels emerging as backlights. At the beginning of
twenty-first century, the LCD backlight module based on white LED technology has
thoroughly replaced the traditional cold cathode tube (CRT) backlight module in a
short time; and it has been extensively applied to all kinds of display products.
However, LCD is not a self-emissive display technology, which leads to a low
photoelectric efficiency. In addition, the color saturation provided by white LED is
still not as good as that of tricolor LED; and its outdoor contrast is low as seriously
affecting the visual effect. In order to overcome these problems, another display
technology that is directly implemented with three primary colored LEDs as self-
emissive pixels has gradually attracted people’s attention, as referred to as “Micro-
LED” display technology. With the continuous improvement of the production
technology, Sony Corporation demonstrated a 55-inch FHD “Crystal LED Display”
prototype in 2012, by using Surface-Mount Technology (SMT) or Chip on Board
technology (COB) to mount LED chips onto the circuit boards. As many as 6.2
million LED chips greatly improved the display resolution with contrast ratio as high
as one million to one; and even the slow response, inflicting LCD on criticism, could
346 Y. Sun et al.

Fig. 17.9 Comparison of basic structures of the display technology of TFT-LCD, OLED, and
MicroLED

be solved. However, the commercial mass production of MicroLED is still hindered

by many problems, such as technique and cost challenges.
MicroLED is essentially a pn junction diode. When the pn junction is in
conducting state under forward bias, the working current promotes the recombina-
tion of electron-hole pairs in luminescent layer, thereby emitting desired monochro-
matic light. MicroLED has a high color saturation and a full width at half-maximum
(FWHM) around 20 nm. Besides, benefited from its self-emissive nature, MicroLED
has simple structure with reasonable high extraction efficiency, low power consump-
tion, and high brightness (>1000 nits, 1 nit ¼ 1 cd/m2).
The fabrication of MicroLED display starts with the miniaturization of LED
structure and further matrixing of these devices by adopting thin-film technology.
Then, the LED arrays are transferred to the backplane, consisting of bottom elec-
trodes and transistors. The protective layer and top electrode are then implemented
with physical deposition process, followed by the final packaging of top substrate. In
Fig. 17.9, the basic structures of Thin-Film Transistor Liquid Crystal Display
(TFT-LCD), Organic Light-Emitting Diode (OLED), and MicroLED are compared.

Quantum Dot Light-Emitting Diode

Quantum Dot Light-Emitting Diode (QLED) is an LED technology using Quantum

Dots (QDs) as fluorescent emitters. Quantum dots are quasi-zero-dimension nano-
materials, which can be fabricated by solution process. The emission spectra of QDs
depend on the crystal size, so OLED lighting has good spectral tunability. In
addition, QDs have excellent material properties such as wide color gamut, high
saturation, good stability, etc. At present, QLED has become a vital research
direction in the display field, e.g., most leading panel manufacturers have launched
R&D programs for QLED commercialization.
In 1994, Armand P. Alivisatos’ team at UC Berkeley first reported their research
on QLED [20]. Since the concept of QLED was proposed, researchers have explored
new materials and device structures. As a result, the device performance of QLED
17 Products of Optoelectronic Devices 347

has been improved rapidly and the performance gap between QLED and OLED has
been gradually narrowed. Nowadays, the external quantum efficiency of red QLED
has exceeded 20%, its lifetime has exceeded 100,000 h, and its full-width at half-
maximum (FWHM) is less than 30 nm. The device performance of green or blue
QLED is very close to or even exceeds that of phosphorescent OLED. In 2011,
Samsung Electronics made a prototype of a 4-inch full-color active-matrix QLED
(AMQLED) display using organic and inorganic layers as electron and hole trans-
port layers of the QLED, respectively. Not long after that, QD Vision (merged with
Samsung in 2016) also released a 4-inch full-color AMQLED panel. AMQLED has
advantages in display quality and manufacturing cost, which has attracted extensive
attention in the display industry. Currently, there is still a long way for QLED to
realize its commercialization and some important technical problems need to be
further addressed and improved, such as efficiency of blue light, device stability,
cadmium-free QDs, fabrication process, and panel development [21, 22].
QLED is one of the self-emissive devices. Its device configuration and operating
mechanism are not very different from OLED. Direct charge injection is the core
operation mechanism of QLED. As shown in Fig. 17.10, in a typical planar structure,
electrons and holes are injected into the emitting layer through electron transporting
layer and hole transporting layer, respectively, and then excitons are generated inside
of QDs, realizing electroluminescence via radiative recombination. Compared with
present mainstream liquid crystal display (LCD) technology, the energy loss during
optical conversion is avoided for the electroluminescent QLED device. Meanwhile,
the display screen can be made lighter and thinner since QLED is a self-emitting
device, which does not require additional backlight unit. Besides, many functional
layers used in QLED can be fabricated by solution process, which helps reducing the
cost of mass production.

Fig. 17.10 Schematic structure and working mechanism of QLED lighting

348 Y. Sun et al.

Thin-Film Transistor

Thin-film transistor (TFT) is a three-terminal active semiconductor device, which

falls into the category of field-effect transistor (FET). The basic structure of a TFT is
shown in Fig. 17.11. TFTs can be divided into two types according to their
structures, bottom-gate structure, and top-gate structure. The operation states of
TFTs are controlled by the gate voltage. The gate voltage regulates the conductivity
of the active layer by field effect, to decide the on and off states of the device. The
voltage difference between the source and drain electrodes results in a lateral electric
field in the active layer, which determines the current in the active layer when the
device is turned on.
TFT technology has been investigated and developed for decades. As early as
1934, Julius Lilienfeld proposed the concept of field effect device [23]; and the first
TFT device was successfully realized in 1962 [24]. TFTs with amorphous silicon
(a-Si) as the active layer appeared in 1979. Since then, amorphous-silicon (a-Si) TFT
has been the mainstream technology of TFT-LCD displays. Polysilicon TFT
appeared in 1980s [25], but it was not until the maturity of low-temperature poly-
Si (LTPS) technology in the 1990s that realizing poly-Si TFT panels on glass
substrates. After 2000, the development of AMOLED displays enabled poly-Si
TFT technology to be really applied in industry. In 2004, indium-gallium-zinc
oxide (InGaZnO, IGZO), an oxide semiconductor material with amorphous struc-
ture, was first reported as the active layer of a TFT. The device showed excellent
electrical characteristics. After that, metal oxide TFT technology represented by
IGZO became a hot research topic. At present, among TFT technologies, a-Si TFT
and LTPS TFT have achieved large-scale mass production, while a small number of
products based on IGZO TFT backplane technology are also available in the market.
In general, with the continuous development of display technology and applications,
the traditional a-Si TFT technology can no longer meet the requirements of the next-
generation advanced displays. Instead, poly-Si TFT and metal oxide TFT technology
will gradually be the mainstream TFT technology.
One of the main applications for TFTs is to work as the driving and switching
devices of active matrix displays, which are the core components in display tech-
nology. In addition, TFT technology has promising application prospect in photo-
electric detection field. In 2003, ZnO TFT optical detection characteristics were

Fig. 17.11 Schematic diagram of a typical TFT structure

17 Products of Optoelectronic Devices 349

Fig. 17.12 ZnO TFT photoelectric detector [26]

reported by H. S. Bae et al. from Yonsei University of Korea. The structure

schematic of the ZnO TFT is shown in Fig. 17.12 [26]. From Fig. 17.11b, the
electrical characteristics of the ZnO TFT are not sensitive to red light illumination,
while they are very sensitive to incident light with a wavelength shorter than that of
green light. When the photon energy of the incident light is less than the forbidden
band width of ZnO, photons will excite the electrically neutral oxygen vacancy in the
forbidden band to form photo-generated current. When the photon energy of the
incident light is greater than the forbidden band width of ZnO, photons will directly
excite electrons from the valence band to the conduction band so as to generate
electron-hole pairs, resulting in a larger photo-generated current. Besides, the sig-
nificant changes of device characteristics under ultraviolet (UV) ray irradiation show
the application potential of metal oxide TFTs in detecting UV.
Another application of TFTs in photoelectric detection is X-ray detection. The
detection of X-rays can be divided into direct detection and indirect detection. For
indirect detection, the scintillator material absorbs X-rays and emits visible light, and
then hydrogenated amorphous silicon TFT or oxide TFT can convert this optical
signal into electrical signal to realize the detection to X-rays.

Laser Diode

Laser diode (LD) is a semiconductor diode device that achieves stimulated emission
by injection pumping. The direct bandgap semiconductor is used as optical gain
medium, which produces optical gain by recombining electrons and holes injected
from a pn junction, and then a positive feedback is generated through the resonant
cavity within the device, thereby realizing laser emission.
In 1962, two US research groups at GE and IBM almost simultaneously [27]
developed a gallium arsenide (GaAs) homojunction laser diode which achieved
stimulated emission successfully at a temperature of 77 K. In the following decade,
the laser diodes based on heterojunctions were also studied systematically [28]. In
350 Y. Sun et al.

1980s, the emergence of quantum well theory opened a new world for the develop-
ment of laser diode. The output power of laser diodes based on quantum well
structure has been significantly improved. The laser diode plays an irreplaceable
role in many fields. In addition, various complicated device structures have been
designed to increase the gain of active region and further develop toward the
direction of high power. Among them, the stripe structure reduces the threshold
current of the device and significantly improves the output power and reliability of
the device. In recent decades, with continuous efforts of researchers, laser diodes
already have the advantages of small size, high efficiency, and high reliability.
The device structure diagram of LD is shown in Fig. 17.13. The photoactive
semiconductor material is located between the p-junction and n-junction. Both end
surfaces of the photoactive semiconductor material are perpendicular to the pn
junction surface, which have a light reflection effect after polishing, thereby forming
an optical resonant cavity. The other two less smooth sides can eliminate the laser
outside the main direction [29]. The working principle of LD relies on the stimulated
emission. In order to make the excited light output from the device, it is necessary to
achieve the inversion of carrier number and reach a certain threshold. When the
injection current is sufficient, the distribution of carriers will change and even
be contrary to the distribution of thermal equilibrium, that is, the number of carriers
are reversed. Since a small number of photons generated by spontaneous emission
are reflected by end faces of resonant cavity, induced radiation is generated, resulting
in positive feedback of frequency selective resonant, and the medium has gain.
When the number of carriers are reversed to a certain extent (threshold) and the
gain is greater than the loss within the active medium, the pn junction can emit laser
with a good spectral line [30].
At present, LDs found wide applications in optical communications industry. LDs
are also widely used in scientific testing equipment, such as spectrometer, interfer-
ometer, etc. Despite the industrialization of traditional LDs, new materials that can
replace III-V groups and the application of LD in emerging fields are still being
explored. Therefore, LD is likely to bring more surprises for us in future.

Fig. 17.13 The device

structure diagram of LD
17 Products of Optoelectronic Devices 351

Photomultiplier Tube (PMT)

Photomultiplier Tube (PMT), also short named Photomultiplier, can convert ultra-
low optical signals into electrical signals, and amplify (and multiply) the electrical
signals. PMTs play an extremely important role in the field of ultra-low light
detection. PMT was invented in 1930s [31] and has evolved with a wide variety of
applications. In 1990s, a silicon photomultiplier (SiPM) was invented and widely
applied to high energy physics, nuclear medicine, and other fields.
The detection principle of PMT is shown in Fig. 17.14, which is based on external
photoelectric effect and secondary electron emission theory [31]. Photons generate
electrons by excitation at the cathode; these electrons are then accelerated by electric
field in vacuum under the applied voltage at the focusing electrode and enter the
multiplication tube. These electrons can excite more electrons in the tube with
multiple dynode stages; the detected signal is finally amplified and measured at the
anode. PMTs can multiply the current produced by incident light by as much as
100 million times or 108 (i.e., 160 dB) in multiple dynode stages and can enable (for
example) individual photon to be detected with low incident flux of photons. The
internal structure of SiPM is shown in Fig. 17.15. Its basic unit consists of an
avalanche photo diode (APD) and a resistor. Many such units are connected in
parallel to form a plane array [32]. Under reverse bias, the photon-induced APD
produces an avalanche effect and outputs an instantaneous current pulse, which
finally superimposes the pulses generated by each basic unit and shows output by a
common terminal. Typical gain factor of a SiPM is in the range of 105–107.

Fig. 17.14 The schematic of

detection principle of vacuum
PMT (end-window type)

Fig. 17.15 Schematic of the

internal structure of SiPM
352 Y. Sun et al.

Photomultiplier tubes (PMT) are widely used in many fields, including electron-
ics, astronomy, aviation, space research, medical treatment, metallurgy, and chem-
ical industry. They can detect optical signals in different bands. SiPMs are mainly
used in the fields of high energy physics and nuclear medicine. In recent years,
SiPMs have been developed rapidly in the field of nuclear medicine and are used to
detect ultra-low light. Although PMT has been relatively mature and widely used in
various fields, the manufacturing technology of PMT is still evolving as driven by
higher measurement accuracy, more complex environment, modularization, integra-
tion, etc. Specifically, the optimization of photocathode manufacturing process is
critical for improving quantum efficiency for good detection sensitivity. The appli-
cation of new composite materials in the cathode can expand the detection range of
PMT to shorter wavelengths, such as X-rays. Those new techniques with on-going
developing of new PMT systems aim at better gain level, dynamic range, and time
characteristics. Furthermore, the development of new type of composite device
structures combining PMT and SiPM is also promoting the advancement of photo-
multiplier tubes.

Infrared Devices

Infrared (IR) devices can perform certain functions by using characteristics of

infrared light, such as IR radiation and IR detection.
IR radiator can emit coherent or incoherent IR radiation signal. Coherent IR
radiator or so-called IR lasers can produce a very high IR spectral intensity in a small
bandwidth, which is expected to be widely used in the fields of space optical
communication and optical fiber communication systems, high-sensitivity gas sen-
sor, high-resolution spectra, etc. Thus, the first lead salt IR laser was developed in
1964 [33]. At present, the band coverage of IR lasers made of IV-VI materials, such
as PbSe or PbTe ranges 3–30 μm; required to work below 200 K in general for
applications in high-resolution spectra.
IR lasers made of III-V materials and poly-compounds such as HgCdTe [34] have
also appeared in recent years. Relevant researches now are mainly focused on
improving the output power and operating temperature of lasers, including improv-
ing the working temperature of devices by using strain, quantum well, and super-
lattice and other energy band structure technologies. In addition, the concept of
realizing IR laser through quantum well sub-band transitions was first proposed in
1971, and its light-emitting comes from the electron transitions among the discrete
sub-bands on the conduction band (or valence band) energy level in semiconductor
heterojunction. Such quantum cascade lasers were presented in 1994. It produces
laser transition by using the separation of energy levels in quantum wells, and the
active layer of device consists of many quantum wells in cascade, so that a single
electron is able to generate multiple photons. At present, quantum cascade lasers
have good performance in increased output power level and operating temperature.
17 Products of Optoelectronic Devices 353

Incoherent IR radiators usually adopt diode structures. When the diode is in

forward bias, holes and electrons are injected into p region and n region respectively,
and then recombination occurs to generate IR radiation; when the diode is in reverse
bias, the carrier concentration of the light-emitting active layer decreases and the
blackbody radiation of the device is turned off, thus enabling it to have the charac-
teristics – lower than the background IR radiation. Therefore, such diode structured
IR light-emitting device has the capability of simulating a temperature to be lower
than or higher than the surrounding environment and can be used as a reference
radiation source for calibrating IR thermal imagers.
IR detectors obtain the required information by converting the received IR
radiation into other physical quantities. This can be traced back to the seventeenth
century when Wilhelm Herschel discovered the radiation other than visible red band
by using a mercury thermometer. Since then, many detectors [35] and thermometers
all were using thermal effect for detection. Thermal detectors have the advantages of
working at room temperature and low cost, but they are not sensitive enough and
slow in response, thus photon detectors were invented, widely researched and
quickly developed.
Photon detectors use photoelectric effect, which are very sensitive and have quick
response, but required usually to work at low temperature. When using photon
detectors, the incident IR radiation is absorbed by the semiconductor material,
making its free carrier concentration change, thus the detection is realized by
measuring this change. So far, various semiconductor photon detectors have been
developed, which realized highly sensitive detection in the whole infrared spectrum
range. Among many detector materials, HgCdTe semiconductor is the most
performance-excellent material. GaAs/GaAlAs multiquantum well detectors have
been developed rapidly in recent years. Due to the adoption of mature GaAs
technology, very uniform large arrays can be obtained.
At present, IR detectors have been widely used in both industrial and scientific
fields, such as remote temperature sensors, spectrometers, and IR imaging systems.
Of course, military application is the most important driving force for IR detection
technology research. Using IR detection technology can realize long-distance
detection and tracking of targets, passive night vision, and visual enhancement in
smoke environment. IR detectors have experienced a development process from
single-element, multielement, linear array to starring focal plane devices. At
present, IR detectors with an array size of more than 1024  1024 have appeared.
In addition, two-color or multiband uncooled detectors were also being developed
continuously.

Optical Communication Devices

Optical communication is a kind of communication way carried by light wave. In

comparison with traditional electrical communication, optical communication has a
number of advantages such as large throughput, high carrier frequency, and low
354 Y. Sun et al.

Fig. 17.16 Schematic of

optical communication
process

transmission loss. The optical communication devices could be classified by their

function into several categories: light source, carrier (optical fiber), repeater, etc.
Optical communication is realized as shown in Fig. 17.16. Firstly, the optical
signal is modulated from input electrical signal by optical transmitter and transferred
in optical fiber. The transmission loss in the telecommunication wavelength of the
optical fiber normally 1550 nm is quite low; but the accumulated loss by long
distance must be considered and the optical repeater is required to amplify the signal
during transmission. Here are two kinds of optical repeater such as optical-electrical-
optical and direct optical fiber amplifier. Then the optical receiver, including optical
detector and amplifier circuit, realizes optical-electrical signal transformation and
sends the electrical signal back to the electrical receiver.
Optical source is the key of optical communication devices. LED is an incoherent
light source with weak intensity and bad monochromaticity, and it is normally used
in low speed and short-distance communication system. In comparison, semicon-
ductor lasers can be used in optical communication due to its small size, efficient
coupling, and quick response.
Fiber is the carrier of optical signal. Fibers should be carefully designed at the
specific wavelength, and compatible with other communication devices. With state-
of-the-art fiber fabrication technique, novel fibers such as flexible polymer fiber [36]
and large bandwidth semiconductor fiber [37] are developed recently.
The simplest optical amplifier mechanism is population inversion in two level
system of resonant optical pump [38]. The core of erbium-doped fiber amplifier
(EDFA) is an erbium-doped optical fiber. When the fiber is pumped with a laser at a
wavelength of 980 nm or 1480 nm, an optical gain for EDFA in the 1550 nm region
can be produced.
Besides the devices mentioned above, there are many auxiliary passive devices in
optical communication system, such as coupler, wavelength division multiplexer,
optical switch, and modulator. With the rapid development of science and technol-
ogy, more devices are expected to further improve the capacity of optical
communication.
17 Products of Optoelectronic Devices 355

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Products of Sensors and MEMS
18
Yu-Fei Han, Yun-Zhuo Sun, Mingjiang Wang, Qiang Liu, and
Ran Tao

Contents
Sensors and MEMS Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Resistance Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Capacitance Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Inductance Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Piezoelectric Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Hall Effect Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Pressure Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
MEMS Inertial Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
RF MEMS Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Microfluidics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
MEMS Magnetic Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Infrared Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Charge-Coupled Device (CCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
CMOS Image Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Fingerprint Recognition Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Touch Controller IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Bio-MEMS IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Abstract
MEMS stands for micro-electro-mechanical system, generally integrated with
microsensors, microprocessors, and micromechanical structures. Based on min-
iaturization technology, MEMS sensors, actuators, and microsystems, such as
Y.-F. Han · Y.-Z. Sun · M. Wang (*)
Harbin Institute of Technology, Shenzhen, China
e-mail: mjwang@hit.edu.cn
Q. Liu
Shanghai Institute of Microsystem and Information Technology, Shanghai, China
R. Tao
Synopsys, Shanghai, China

© Publishing House of Electronics Industry 2024 357

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_18
358 Y.-F. Han et al.

pressure sensors, inertial sensors, RF components and modules, micro-opto-

electro-mechanical system (MOEMS), image sensors, biochemical and biomed-
ical systems, energy harvesters, have been developed. They are widely used in
auto industry, internet of things (IoT), smart phone, health care-related industry,
etc. Several MEMS sensors are discussed in this chapter. Their progresses of
technology, basic structures, and main applications are briefly described.

Keywords
Sensor · Actuator · MEMS · Microsystem · MOEMS

Sensors and MEMS Devices

Sensor is a kind of subsystem that is used for detecting surrounding events or

measuring physical parameters and converting them into signals, which can be
read by other electronic instruments. According to the detected physical parameters,
sensors could be classified as pressure sensor, displacement sensor, speed sensor,
temperature sensor, flow sensor, gas sensor, etc. Based on the working principles,
sensors can be categorized as resistance sensors, capacitance sensors, inductive
sensors, pressure-resistance sensors, photoelectric sensors, etc.
The development of sensors has lasted for a long time and the first sensor, a
thermocouple, was invented by German physicist Thomas J. Seebeck in 1821 [1]. In
recent years, sensors are widely adopted in industry to enhance the production
efficiency. For example, in manufacturing processes, key parameters such as tem-
perature, pressure, liquid level, and flow rate are continuously monitored by sensors,
which help to control various production status in real-time through the central
control room. This application significantly promotes the development of sensors.
Meanwhile, driven by the development of semiconductor technology and industry,
sensing technologies are also continuously updated, with new types of sensors such
as pn-junction temperature sensor, integrated temperature sensor, and
semiconductor-based thermocouple sensor, infrared sensor, microwave sensor,
acoustic sensor emerging. Nowadays, various kinds of sensors are widely adopted
in industry, environment protection, ocean exploration, bioengineering, medical
diagnosis, etc.
MEMS (Micro-Electrical-Mechanical Systems, or micro electrical mechanical
systems) are kind of micro device or system that generally integrated with micro-
sensors, microactuators, and micromechanical structures. In 1960s, Bell Labs and
Honeywell research center had developed the first silicon-diaphragm pressure sensor
and strain gauge [2]. In 1979, Angell and Roylance developed piezoresistive micro-
accelerometers. In 1993, Analog Devices developed the first fully integrated silicon
microaccelerometer using surface micromachining technology. MEMS has com-
bined the advantages of electrical systems in collecting data and processing and
the superiority of mechanical system in operating and controlling [3]. Through
18 Products of Sensors and MEMS 359

miniaturization technology, several novel components or systems with special func-

tions were developed, which is based on various subjects including microelectronics,
material science, mechanics, and chemistry. When considering the specific applica-
tions, MEMS devices can be further grouped as sensing MEMS, biology MEMS,
optical MEMS, and RF (radio frequency) MEMS. There are various MEMS
manufacturing techniques, including the traditional photolithography, etching, thin
film depositing, micromachining of both silicon and other materials, precision
machining, etc.
Compared with traditional sensors, MEMS (systems or devices) have the char-
acteristics of miniaturization, high integrated density, and easy to be mass-produced.
Common MEMS devices include microphone, accelerometer, gyroscope, magnetic
sensor, bulk acoustic wave (BAW) filter, pressure sensor, fingerprint sensor, distance
sensor, circumstance optical sensor, etc. Each MEMS device is an independent small
system. The main application fields of MEMS are shown in Fig. 18.1; and the main
application scope of MEMS actuators is displayed in Fig. 18.2.
At present, MEMS sensors are widely used in auto industry, especially in the
ADAS (advanced driver-assistance systems). To realize intelligent driving assistance
through processing the information collected by various sensors, ADAS combines
different sensing technologies with various sensors such as camera, radar, laser, and
ultrasonic to detect light, heat, pressure, etc.

Fig. 18.1 Main application fields of MEMS sensors

Fig. 18.2 Main application fields of MEMS actuators

360 Y.-F. Han et al.

Resistance Sensor

Resistive sensors convert physical nonelectrical change into a corresponding resistance

change and recorded by the detection circuit. Resistive sensors for temperature detection
are also referred to as temperature sensors (see Sect. “Temperature Sensor”).
Resistive sensors include potentiometer sensor, gas-sensitive and humidity-sensitive
sensors, and resistance strain sensor. (1) A potentiometer sensor is a sensor that converts
mechanical displacement into corresponding resistance and voltage changes.
(2) Gas-sensitive and humidity-sensitive resistance sensors [4] are sensors that use
materials sensitive to small content of gases or water from humidity and convert into
resistance and voltage changes. (3) The resistance strain sensor commonly applies a
force to deform the materials such as a wire, a foil or a semiconductor and thereby
generates a resistance change, and then detects and outputs in the form of voltages or
currents. For example, a circular cross section of wire with an initial resistance value

R ¼ ρ  ðL=AÞ

where ρ is the resistivity of the wire, L the wire length, and A the cross-sectional area.
When the wire is stretched by the force F, the length of the wire changes, and its area
and resistivity change accordingly. The relative change rate of the resistance value is
as follows:

ΔR
¼ K0 e
R
where, K0 is the sensitivity coefficient of a single wire; ε is the axial relative strain
which is equal to ΔL/L. When ΔR/R is measured and K0 is known, the strain value ε
of the wire can be obtained. The resistance strain sensor is based on wide variety of
materials. For example, weighing scale and resistive touch screen generally use
Indium Tin Oxides (ITO) materials, which have weak conductivity, good light
transmittance, and transparency. Resistive touch screens currently have four-wire,
five-wire, eight-wire, etc., but the reliability of such resistive touch screens is not
high. Long-term pressing can cause deformation of the upper layer of ITO, causing
damage to the device and affecting the lifetime of the whole machine.
Resistance sensors have been long in development time and wide range of
applications [5, 6]. At present, combined with MEMS technology, resistance sensors
will continue to play an important role in fields such as power electronics, rail transit,
medical education, and military.

Capacitance Sensor

Capacitance sensor is a kind of sensor that measures the change of physical param-
eters through the change of dielectric capacitance [7, 8]. The core portion of the
capacitance sensor includes two electrodes, an insulator, and a substrate. The
relationship between capacitance of the sensor and other parameters is as follows:
18 Products of Sensors and MEMS 361

eSb er e0 Sb
C¼ ¼
δ δ
where C is the capacitance, ε denotes the dielectric constant of the dielectric material
between plates, Sb is the area covered by the upper and lower plates corresponding to
each other, δ is the average distance between the plates, the ε0 is the dielectric
constant of vacuum, and the εr is the relative dielectric constant. When the dielectric
medium is air, we have ε ¼ 1.
There are three types of capacitance sensors, namely, capacitive sensor with
variable pole distance, variable area, and variable dielectric. (1) The capacitance
sensor with variable pole distance is obtained by measuring the capacitance due to
the variation of the length between the two capacitive plates. Variable pole capac-
itance sensors measure subtle movements and some changes in length caused by
stress or vibration. When such sensors are used to measure amplitude, distance, and
metal surfaces, unilateral capacitive sensors are usually used. (2) The area-variation
capacitance sensor exploits the area variation between two plates to obtain the
measurement results. The area-variation capacitance sensor is usually used to mea-
sure angular displacement and certain linear displacement. Compared with the
dielectric-variation capacitance sensor, this type of sensor has a larger measurement
range. (3) Dielectric-variation capacitance sensor uses the permittivity change of
dielectric material between two plates. Dielectric-variation capacitance sensors are
often used to measure material level and many dielectric characteristics.
Capacitance sensor can be used to measure the amount of water, pressure, sound
intensity, angle, liquid level, density, vibration, displacement, thickness and humid-
ity, and other physical parameters. Therefore, it is very suitable to measure the
rotation precision for precise shafts, high-frequency vibration, and amplitude of a
series of mechanical quantities.
In recent years, capacitance sensors are used in capacitive touch screen as well as
in fingerprint recognition products. Capacitive touch screen includes surface touch
screen and projection touch screen. The surface touch screen uses single-point
control, while the projection touch screen uses multipoint control. For the surface
capacitive touch screen, when the x direction is electrified and the y direction is not,
an electric field is formed along the x direction and a potential change is formed
along the x direction. The x coordinate corresponds to the potential. The coordinate
information of this potential point can be calculated by detecting the current change
corresponding to this potential point. At present, projective multipoint touch screen
is generally improved by interpolation algorithm.
MEMS-based sensor is an important research field of current sensors. It is
compatible with IC process, integrating the sensitive micromechanical sensor chip
and the corresponding interface circuit on the same silicon wafer. To use the
characteristics of IC manufacturing, it can be mass manufactured to reduce the
cost. Also, it has good repeatability and consistency, high sensitivity, and resolution.
MEMS capacitance sensor combines the advantages of capacitance sensor and
MEMS sensor. With the gradual improvement of MEMS technology level, the
sensor capacitance becomes smaller and smaller, and the change of sensor capaci-
tance caused by external physical parameter is even smaller. MEMS capacitance
362 Y.-F. Han et al.

sensors, and the pressure, inertia, and other kinds of MEMS sensors based on MEMS
capacitance changes have become hot topics in the field of sensors. With the
development of material technology, and semiconductor technologies, the category
of capacitance sensors are increasing, and their applications become wider.

Inductance Sensor

Inductance sensors are based on the principle of self-inductance. The measured

change of self-inductance is converted to an electronic output signal of a measure-
ment circuit [9].
The coil self-inductance L of inductive sensor is defined as

N2
L¼
Rm
where N is the number of turns of the coil; Rm is the total reluctance of magnetic
circuit. Since the air gap thickness δ is small, it can be assumed that the air gap
magnetic field distribution is uniform, so the total magnetic resistance is

li 2δ
Rm ¼ þ
ui Si u0 S
where li is the length of the magnetizer; Si is the cross-sectional area of each segment
of the magnetizer; δ is the thickness of the air gap; ui is the permeability of the
magnetizer; u0 is the vacuum permeability; S is the air gap cross-sectional area.
Substituting Rm into the first formula, one get

li 2δ
L ¼ N2 = þ
ui S i u0 S

After the basic material and the structure of the sensor are confirmed, when δ is
unchanged, and S is the only external variable, this type of sensor is called variable-
section inductive sensor. When S remains unchanged, this type of sensor is called a
variable-air gap inductive sensor. When a cylindrical armature is added into the coil
to change the amount of self-inductance, this type of sensor is called a spiral tube
inductive sensor.
The air gap type inductive sensors have the advantages of high sensitivity and
good linearity, and can be used in most environments. The cross-section type uses
the change of the magnetic cross-sectional area to produce a self-inductance change,
which has the advantage of linearity, though some nonlinear errors may occur in
actual use. The solenoid type inductive sensor is an air gap sensor. The shape and
size of the coil bobbin are required to be constant during manufacture, and the coil is
wound uniformly.
18 Products of Sensors and MEMS 363

The conductance sensor products [10] have the advantages of simple structure,
strong anti-interference ability, less strict requirement on working environment,
good reliability and stability, etc., so they are widely used in various fields such as
semiconductor IC production, automated machinery production, and product quality
inspection.

Piezoelectric Sensor

Piezoelectric sensor is a kind of self-powered sensor made of piezoelectric materials

[11, 12]. Piezoelectric effect refers to the phenomenon of electric charge on the
surface of piezoelectric material when it is subjected to external force.
According to the characteristics of piezoelectric materials, there are positive or
inverse piezoelectric effects. There are many kinds of piezoelectric materials. Quartz
crystal and piezoelectric ceramics are widely used in industry. Dextrorotatory quartz
crystal structure is shown in Fig. 18.3. It has the strongest piezoelectric effect on the
edge plane perpendicular to the X-axis, which is called the electrical axis. Under the
conditions with electric field, the mechanical deformation in the y-axis direction
perpendicular to the opposite side of the hexagon is the largest, so the y-axis is called
the mechanical axis. However, there is no piezoelectric effect in the z-axis direction,
which is called the neutral axis.
The piezoelectric equation represents the relationship between stress electrical
displacement and strain tensor of electric field strength in a piezoelectric body. The
electric charge generated on the corresponding surface of the piezoelectric compo-
nent, when it is subjected to a certain external force F in a certain direction. The
electric charge Q can be expressed as follows:

Q¼Fd

where d is the piezoelectric constant.

Fig. 18.3 Dextrorotatory

quartz crystal
364 Y.-F. Han et al.

Piezoelectric sensors are widely used in automotive engines, automatic ignition

devices for gas stoves, piezoelectric loudspeakers, and many kinds of ultrasonic
generators. Gravity sensors have become an important part of the smartphones.
Gravity sensor attaches a weight to a piezoelectric piece and calculates the horizontal
direction by measuring the voltage generated in both directions. Gravity sensors can
be used to achieve automatically switching the phone between landscape and vertical
screens. In some game devices such as balanced ball, racing, etc., gravity sensors are
used for interactive control.
The main disadvantage of piezoelectric sensor is the high output impedance,
which requires the use of low capacitance and low-noise cables, and no static output
[13]. Due to its reliability, sensitivity, high signal-to-noise ratio, and characteristics
of spontaneous electricity and reversibility, piezoelectric sensors have been
expanded their applications in the market.

Temperature Sensor

Temperature sensor, also known as thermal sensor, is a sensor device that converts
the measured temperature-related physical parameter into a charge or voltage vari-
ation. There are many physical properties related to temperature, which can be
selected according to the different temperature-sensitive areas [14].
Temperature sensors used on the market are mainly thermometers, resistance
sensors, thermocouples, thermistors (or thermal resistors), etc. When the temperature
of the measured object is relatively high, the noncontact thermal sensor is generally
used for measurement; when temperature of the measured object is relatively low, it
is generally measured using thermocouples or semiconductor and metal resistance
sensors; when it is near normal temperature, and the measurement is generally
performed using a semiconductor thermal sensor or thermistor [15]. Contemporary
advanced temperature sensors can be designed with SoC, where the microcontroller
unit (MCU) sends commands to the sensor through the data bus (I2C) for temper-
ature sensing. The measured data (ambient temperature, target temperature, etc.) by
the infrared temperature sensor are stored in RAM. To obtain a high-precision
temperature signal (output voltage), the temperature sensor circuit is usually
implemented by a base-emitter voltage multiplying circuit including constant current
sources, bipolar transistors, and resistors. The base current error compensation
circuit can also compensate the base current of the bipolar transistor flowing through
the resistor. Temperature sensors are widely used in air conditioner systems, refrig-
erators, rice cookers, servers, PCs, mobile phones, and other products. In the past a
few years, with the rapid development of microelectronics and MEMS technology,
MEMS sensors have demonstrated advantages of smaller size, lighter weight, and
smaller inherent heat capacity compared with traditional sensors. MEMS tempera-
ture sensors are gradually replacing traditional temperature sensors.
In recent years, sensor technology has rapidly advanced toward high reliability,
high precision, high resolution, high security, intelligence, and contactless.
18 Products of Sensors and MEMS 365

Hall Effect Sensor

Hall Effect sensor refers to sensor devices that convert the change of nonelectrical
and nonmagnetic physical parameters into the change of electrical parameter by the
Hall Effect and then collects, amplifies, and outputs the change of electrical param-
eter. Hall Effect was discovered by A. H. Hall in 1879 [16], the working principle of
Hall Effect sensor [17] is shown in Fig. 18.4a.
Hall Effect voltage, UH, can be expressed as follows:

U H ¼ RH IB=d,

where RH is the Hall coefficient whose value is determined by the wafer material,
B is magnetic induction intensity gauss, G (1G ¼ 1  104 T), d is the thickness of
Hall module, and I is the current passing through the wafer, which is called excitation
current.
The basic structure diagram of Hall Effect sensor is shown in Fig. 18.4b. A pair of
electrodes is installed on each side of the semiconductor substrate.
Along the direction of current, so called excitation electrodes A and B are
connected to excitation voltage to generate the excitation current. Electrons or
holes of excitation current move and then deflect under the influence of Lorentz
force. The electric voltmeter connects electrodes C and D to measure the Hall
voltage generated inside the semiconductor, so it is called Hall electrode.
Hall Effect sensor can be used to measure pressure, strain, mechanical vibrations,
acceleration, microdisplacement, magnetic induction intensity, active power, reac-
tive power, phase, current, voltage, surface roughness, rotating speed, and other
parameters. Hall Effect sensors are widely used in, such as multiplier, divider, and
square calculator, gyrator composed of modulation and demodulation, triangular
wave generator, contactless sender, synchronous transmission devices, etc.
Hall sensors have been widely used in market, e.g., the smart clamshell phones.
When the cover is closed, the phone goes into hibernation; as the cover is opened, the
phone is awakened with no buttons pressed during the process.

Fig. 18.4 The Hall sensor: its working principle (a) and the basic structure diagram (b)
366 Y.-F. Han et al.

Besides, Hall Effect sensor has many advantages, such as long lifetime and small
body weight, can realize brushless electronic and noiseless. It is expected that soon,
it will be further used in variety of applications such as automotive electronics and
electronic communications.

Pressure Sensor

Pressure sensor is a device, module, or subsystem for measuring pressure force and
transforming it into electrical signal. In 1938, E. E. Simmons of the California
Institute of Technology designed a paper-based bonded wire resistance strain
gauge. In 1969, Hans W. Keller designed, and mass-produced semiconductor pres-
sure sensors based on silicon using IC technology [18].
Pressure sensor is classified into three types according to different reference
pressure: gauge pressure sensor, absolute pressure sensor and differential pressure
sensor. Gauge pressure sensor can measure the reference atmospheric pressure,
absolute Pressure sensor is for measuring the reference vacuum pressure, and
differential pressure sensor is used to detect the difference of pressure at the two
measuring ends.
According to the switching speed when measuring the pressure signal, pressure
sensor is sorted as static pressure sensor and dynamic pressure sensor. Static pressure
sensor is suitable for static and quasi-static pressure measurements with varying
frequency within tens of Hz. Dynamic pressure sensor is appropriate for measuring
pressure signal with rapid variations. The general operating parameters of dynamic
pressure sensor are frequency response characteristics, intrinsic frequency, and
response time. According to different working mechanisms, dynamic pressure
sensors are mainly classified as two types: Si piezoresistive sensor and piezoelectric
sensor. In the same way, (quasi) static pressure sensors are sorted as Si piezoresistive
sensor, piezoelectric sensor, Si capacitance sensor, metal capacitance sensor, ceramic
capacitance sensor, Si resonant sensor, quartz crystal resonant sensor, sputtered thin
film strain sensor, etc.
According to the operating ambient temperature, pressure sensors are divided as
high-temperature pressure sensors and normal temperature pressure sensors. High-
temperature pressure sensors generally operated at temperatures above 130  C.
High-temperature pressure sensors are further divided as sputtered thin film
high-temperature pressure sensor, SOI high-temperature pressure sensor [19],
Si-sapphire-based high-temperature pressure sensor, and piezoelectric high-
temperature pressure sensor. Piezoelectric high-temperature pressure sensor can
operate up to 175  C. SOI high-temperature pressure sensor and Si-sapphire-based
high-temperature pressure sensor can operate at temperatures above 350  C [20].
According to the operating mechanism, pressure sensors are sorted as capacitive
pressure sensor, piezoresistive pressure sensor, and resonant pressure sensor. Among
them, Si capacitance pressure sensor, Si piezoresistive pressure sensor, and Si
resonant pressure sensor are with very low-test error around 0.01% [21]. Si resonant
pressure sensor can convert the variation of pressure into a resonant frequency shift
18 Products of Sensors and MEMS 367

of the Si resonant beam, and this shift corresponds to the varied pressure value. Si
resonant pressure has two working modes, including electrostatic excitation and
electromagnetic excitation. Si resonant pressure sensor is appropriate for high-
accuracy pressure sensing.
At present, Si semiconductor pressure sensor is widely adopted for its significant
advantages, such as high performance, low cost, and wide applications. The weight
of this sensor can be even less than 0.01 g, and its measuring range varies from
several thousand Pa to several hundreds of MPa.
The main development direction of pressure sensors is to be with high accuracy,
high-temperature resistance, and high integrated density. The monolithic integration
technology of pressure sensors has been developed for more than 20 years. However,
the present products are still focused on low-range, medium-precision applications,
mainly adopted by automotive industry and civilian use. There is still lack of
fundamental breakthrough in high-temperature applications.

MEMS Inertial Sensor

MEMS inertial sensor is fabricated with MEMS technology, and it can indepen-
dently measure the azimuth, attitude, velocity, acceleration, and other motion
parameters of the vehicle in a reference coordinate. MEMS inertial sensor mainly
includes MEMS accelerometers and MEMS gyros (gyroscope). According to the
operating mechanism, MEMS accelerometers are sorted as piezoresistive type,
capacitive type, resonant type, tunnel-current type, and thermal-convection type.
MEMS gyros are usually Coriolis vibrating gyros (CVGs). They are divided as
vibration type and rotation type according to different excitation modes. The vibra-
tion exciting modes mainly include hemisphere type, tuning-fork type, and frame
type. The gyro rotation is mainly excited by a dynamic tuning gyro.
Piezoresistive accelerometer is the first MEMS inertial device. In 1962, a
piezoresistive accelerometer adopted with butterfly-shaped semiconductor strain
gauge was produced to detect vibration and shock. In 1968, the 2266 series accel-
erometer with a diffused semiconductor strain gauge was developed, whose
detecting range reached 2  104 g (g is gravitational acceleration, 1 g ¼ 9.8 m/s2).
In April 1974, the 7070 series accelerometer was emerged with a range of 1  105 g,
where the key component piezoresistive strain gauge was fabricated with a bulk
silicon release process. In 1983, the 7270A series accelerometer was produced with a
detecting range of 2  105 g and a resonant frequency of 1.2 MHz [22].
Modern capacitive accelerometers are mainly produced with surface silicon
processes and simultaneously integrated with large-scale electronic circuits. ADI’s
ADXL50 is the first monolithic integrated capacitive MEMS accelerometer that
widely used in automotive airbags [23]. In theory, resonant accelerometer has a
better measurement accuracy and is convenient for digital signal processing. In
2005, the stability and repeatability of resonant accelerometer reached a resolution
of below 1  106 g, and it had been installed in the inertial navigation of strategic
missiles.
368 Y.-F. Han et al.

Fig. 18.5 The hinge structure of the piezoresistive accelerometer [24]

The hinge structure of the piezoresistive accelerometer is shown in Fig. 18.5.

In 1960s, miniaturized gyros had emerged, such as vibrating spring gyros, tuned
tuning fork gyros, and dynamic gyros, and they were emerged in MEMS fields in
1990s. In 1990, tuning fork MEMS gyroscope with piezoelectric vibration compo-
nent and piezoresistive detecting function was realized. In 1994, vibrating frame
gyro with a glass-silicon structure was developed. In 1997, all-silicon vibrating disc
gyroscope was developed. In 2008, MEMS rotating gyros appeared. In 2014, the
bias stability of silicon-based vibrating disc resonator gyroscope reached 0.1 deg/h
[25], which could be applied to inertial navigation.

RF MEMS Switch

Radio frequency (RF) microelectromechanical system switch is one of the most

important devices in the field of MEMS. The first RF MEMS switch is proposed and
manufactured by Peterson of IBM R&D Center in 1979 [26]. The switching perfor-
mances of the first RF MEMS switch were poor as fabrication technology was
immature at that time. With the continuous improvement of the MEMS process,
RF MEMS switch has been developed rapidly. Figure 18.6 shows the basic structure
of an RF MEMS switch. By applying a voltage between the driving electrode and the
fixed electrode, electrostatic force will be generated between these two electrodes.
The generated electrostatic force drives the driving electrode moving toward the
fixed electrode until the movable contact-point in the middle of the silicon beam
contacts the fixed contact point, which means turning-on of the switch and
conducting of the signal line. If the voltage is removed, the electrostatic attraction
disappears, and the movable contact points are automatically separated from the
18 Products of Sensors and MEMS 369

Fig. 18.6 Basic structure of

RF MEMS switch

fixed contact points of the signal lines by the elastic restoring force of the silicon
beam, thus the signal lines are disconnected.
RF MEMS switches have better switching performance, compared with the
conventional switches. Many new functional modules can be formed by integrating
with various components and greatly expand the applications of RF MEMS switches
[27]. RF MEMS switch has the advantages of low-power consumption, high isola-
tion, low insertion loss, high linearity and small size in wireless communication
system, national defense radar system, automobile radar, satellite communication
system, etc. For the commercialization of RF MEMS switches, the practical issues
include low reliability, high cost, difficult packaging, and high operating voltage. In
2009, Omron of Japan launched a high-reliability RF-MEMS dual-bit selection
switch [28] with market success. With the progress of technology, other RF
MEMS products will gradually become mature. Currently, many enterprises in the
United States, France, Germany, Korea, and China, are actively promoting the
research and development of RF MEMS switch.

Microfluidics

Microfluidics refers to the technology of measuring, manipulating or operating fluid

with feature size of submillimeter or even micrometer in microchannels. The system
can process or manipulate small amounts of fluidics (109 to 1018 L ) [29]. The
microfluidics technology has been generally considered to be derived from capillary
electrophoresis and fluid injection analysis in analytical chemistry. In 1990, A. Manz
and H. M. Widmer of the Central Institute of Analytical Research in Basel, Swit-
zerland, for the first time proposed the concept of utilizing micromachining methods
to achieve miniaturized total chemical analysis system in the journal “Sensors and
Actuators, Chemistry” [30], which is recognized as the naissance of microfluidics.
370 Y.-F. Han et al.

Compared with previous analysis systems, the main problem caused by the
reduction in size of microfluidics is that the domination is either surface character-
istics or diffusion characteristics [31]. When the surface characteristics dominate, the
microfluidics chip can increase the target molecular capture amount on the wall
thanks to the large surface area, thereby improving the detection sensitivity or
reaction efficiency. At the same time, the large surface area also makes the non-
specific adsorption of the microfluidics serious, and even leads to corresponding
reaction failure, so functional modification or passivation of the surface becomes a
key to microfluidics. When the diffusion characteristics dominate, the microfluidics
chip can realize the separation of substances based on diffusion principle through
careful geometry design. At the same time, since the material exchange at the
microscale can only rely on diffusion, it lacks efficient mass transport methods.
Therefore, microfluidics has not yet fully matured today mainly due to main
challenges of high-efficiency on-chip mixing method.
The structure of a typical microfluidics chip is shown in Fig. 18.7. The basic
functional units include the inlet (connecting external reaction liquid or sample), the
microchannel (fluid transport structure, space for function realization), the functional
structure (providing function, such as temperature control), and the outlet
(connecting external reservoir or waste liquid pool). In addition, to achieve multi-
functional integration, some microfluidics systems need to integrate micropumps,
microvalves, and other functional units with the microchannels.
In recent years, many microfluidics technologies based on surface-driven and
centrifugal-driven have great potential applications [32] because of their simple
and easy implementation of liquid-driven. The most mature and commercially
successful microfluidics chips include the MEMS inkjet printer and the MEMS
microfluidic pump.

Fig. 18.7 Structure of a

typical microfluidic chip
(continuous flow polymerase
chain reaction chip) [2]
18 Products of Sensors and MEMS 371

MEMS Magnetic Sensor

Magnetic Field Sensor, also known as Magnetometer, is a sensor that measures the
magnetic induction and direction of the environment. At present, the main MEMS
magnetometers [33] include magnetoresistive magnetometers, fluxgate magnetom-
eters, Hall Effect magnetometers, tunnel-effect magnetometers, resonant Lorentz
magnetometers, etc.

1. Fluxgate magnetometer includes an iron core that made of a soft magnetic

material with high magnetic permeability. In the case of simultaneous alternating
and constant magnetic fields, the voltage induced by the detecting coil wound on
the iron core contains even harmonic components, especially the second har-
monic; the harmonic voltage is positively correlated with the magnetic field
strength. Therefore, the magnetic field strength can be detected by measuring
the harmonic voltage of the detection coil.
2. Hall Effect magnetometers are based on the Hall Effect. A conductor is placed in
a magnetic field and energized, the magnetic field produces a lateral force on the
electrons in the conductor, thereby creating a voltage difference across the
conductor, and measuring the voltage difference yields the strength of the mag-
netic field [34]. The Hall Effect magnetometer is characterized as small probe
size, high sensitivity, and good linearity.
3. Magnetoresistive magnetometers are available in both semiconductor magneto-
resistive and thin film magnetoresistive types. A semiconductor magnetoresistive
magnetometer is a sensor that measures the strength and direction of a magnetic
field using materials such as InSb or GaAs, it is based on the fact that the
semiconductor material changes its resistance affected by a magnetic field. The
thin film magnetoresistive magnetometer is made of NiFe or NiCo alloy, and it
works based on the anisotropic magnetoresistance effect of the thin film magne-
toresistive material.
4. Tunnel-effect magnetometer has a deep cavity structure with a thin film and a
silicon tip (Si-tip). The electrostatic force is used to pull the film to a distance of
1 nm from the Si-tip, and a microampere tunneling current is generated between
the film and the Si-tip under the bias voltage. The film has a coil structure in
which an alternating current is applied. Under the action of the magnetic field, a
Lorentz force is generated in the coil to cause the film to vibrate up and down.
When the distance between the film and the Si-tip changes with the vibration of
the film, the value of the tunneling current will also change, and the intensity of
the external magnetic field can be obtained by measuring the change of tunneling
current.
5. Resonant Lorentz force magnetometer has an excitation coil on its structure. The
excitation coil that is connected to the alternating current is subjected to an
alternating Lorentz force in the magnetic field so that its structure results in a
resonant state, and the strength of the external magnetic field can be obtained
372 Y.-F. Han et al.

indirectly by measuring the magnitude of vibration amplitude of the structure.

When the current frequency is consistent with the natural oscillation frequency of
the torsion beam, the system will resonate, at which point the output amplitude
reaches a maximum and is proportional to the strength of the external magnetic
field. Most Lorentz force magnetometers measure amplitude by piezoresistive or
capacitive sensing methods. Since the MEMS resonant structure has a high Q
value, hence the sensitivity of the magnetometer is high [35]. Moreover, such
magnetometers do not require magnetic materials, and the processing process is
relatively simple, and the yield is relatively high.

In general, magnetic field detection is one of the important directions in the field
of MEMS sensing. In recent years, the related MEMS magnetometer technology has
been promoted with the emergence and development of new concepts such as atomic
magnetometers. At the same time, MEMS micromachining methods have greatly
reduced the size of magnetometers and reduced the cost, and this leads to broader
applications.

Infrared Sensor

Infrared (IR) sensor is a sensor system for IR radiation detection, also known as IR
detector. According to the operating temperature, the IR detectors are divided into
cooled and uncooled types; according to theory of operation, the IR detectors are
divided into photoelectric effect and thermal effect types.
Cooled IR detectors are usually image based on photoelectric effect. Most used
photodiode materials include HgCdTe, InSb, InGaAs, and InP quantum well
(InPQW). Cooled IR detectors usually work in Dewar for higher signal-to-noise
ratio and resolution. However, cooled IR image systems are complex, which have
higher power consumption, larger volume, and mass, and more expensive.
Uncooled IR detectors [36] are usually image based on thermal effect, which
means the detector temperature changes with heating due to IR radiation. The typical
uncooled infrared detectors include pyroelectric, microbolometer, thermal diode,
thermopile, etc. The uncooled IR detector can work at room temperature, with the
characteristics of low cost, low-power consumption, small volume, small mass, and
fast start. With the development of technology, the performance of uncooled IR
detector has gradually caught up with that of cooled IR detector. Nowadays,
uncooled IR detectors are widely used in thermal image sight, missile guidance,
vehicle vision system, security monitoring, fire rescue, electric power monitoring,
forest fire monitoring, and other fields.
Resistive microbolometer is the mainstream technology of uncooled IR detectors.
According to the materials used, the resistive microbolometer can be divided into
vanadium oxide (VOX), amorphous silicon (a-Si), and other types. Honeywell in
USA was the first company to successfully develop a microbolometer IR detector
based on vanadium oxide. CEA-LETI in France was the first to successfully develop
18 Products of Sensors and MEMS 373

a microbolometer IR detector based on a-Si, which is currently produced by ULIS

and Lynred in France [37].
The readout circuit of uncooled IR detector is very important. The readout circuit
array is connected to the sensor array; the analog signal according to IR radiation is
selected, amplified, corrected, and converted to the digital signal. Finally, the desired
thermal image can be achieved through the digital signal process. Advanced tech-
nologies such as TEC-less analog front-end, on-chip nonuniformity correction, and
digital process can further improve detector performance; reduce system’s power
consumption and cost. Nowadays, the minimum noise equivalent temperature dif-
ference (NETD) can be achieved as low as 20 mK, and the pixel pitch can be as small
as 12 μm. The array size is also expanded to 1280  1024, and the maximum frame
frequency can be up to 100 Hz. In 2015, Raytheon [38] demonstrated a thermal
imaging camera with 12 μm pitch of 206  156 pixels uncooled IR detector, which
can be used in mobile terminals such as iPhone. With the further reduction in size
and cost, infrared thermal imaging technology is expected to be widely used in
automotive electronics, drones, mobile phones, and other mobile intelligent
terminals.

Charge-Coupled Device (CCD)

Charge-Coupled Device (CCD) is a semiconductor device arranged in sequence by

the basic units of MOS capacitors. When a voltage is applied to a MOS capacitor
unit, the charge in the capacitor unit can be transferred to the neighboring unit
sequentially. Image sensor is a successful application of CCD. The working principle
of CCD is that, firstly the charge generated by the photoelectric effect is collected in
a region called the photosensitive region, and then it is transferred to an area where
the charge can be read and processed, and finally the signal is output through the
peripheral circuit for subsequent transmission and processing [39].
The CCD was invented in 1969 by Willard S. Boyle and George E. Smith of Bell
Labs [40]. Since 1980s, Sony gradually became the largest supplier of CCD.
Electron Multiplying CCD (EMCCD) adds a gain register between the read register
and the output amplifier, which causes the electron to “impact ionization effect”
during the transfer process, generating new electrons and realizing electron multi-
plication. The signal-to-noise ratio of EMCCD has been greatly improved, especially
suitable for low-light conditions such as single-photon detection, live cell micro-
scopic observation, and fluorescence for imaging in cell [41].
Early CCD operated in frontal illumination mode; that the incident light came
from the front, through the polysilicon (poly-Si) electrodes and dielectric layers
and was absorbed inside of the semiconductor material in the chip to produce
electron-hole pairs. Since the incident photons pass through the poly-Si which
strongly absorbs the short-wavelength light, it will result in a loss of incident
light intensity and then lead to a decrease in the quantum efficiency of the CCD.
With the improved back-illuminated CCD, light enters from the back side of the
chip instead of passing through the poly-Si electrode, thereby improving the
374 Y.-F. Han et al.

quantum efficiency of the CCD. Back-illuminated CCD can achieve target imag-
ing under low-light conditions and has a wide range of applications in aerospace
fields such as target detection, positioning and navigation, resource exploration,
and environmental monitoring [42].
Time Delay Integration (TDI) CCD is an array structure that works in a line scan.
It supports high response sensitivity for light, high signal-to-noise ratio, erasable
image shift, and selectable TDI levels to control exposure time. It is the core device
for image acquisition and target recognition of space borne and airborne rem-
ote sensing cameras [43]. At present, most of the world’s remote sensing cameras
in the aerospace industry use TDI CCDs.
Compared with vacuum camera tubes, pyroelectric tubes, and silicon camera
tubes, CCD has the advantages of small size, small weight, low-power consumption,
long working lifetime, high sensitivity, wide spectral response range, large dynamic
range, and global shutter imaging. CCD was a revolutionary breakthrough in the
field of image sensors [43] and it was once widely used in civil markets such as
security surveillance and digital cameras but gradually replaced by the newer
technology of CMOS Image Sensor (CIS) technology. Currently, CCD is still widely
used in certain special applications such as military, aerospace, and astronomical
observation.

CMOS Image Sensor

CMOS image sensor (CIS) comprises of photodiodes and MOSFET amplifiers. In

1968, P. J. Nobel from Plessey created a passive-pixel sensor (PPS) based on MOS
device [44]. Began in 1992 with a proto-type CMOS active-pixel sensor (APS),
NASA Jet Propulsion Laboratory (JPL) successfully manufactured CMOS APS in
1999 [45], which integrated an amplifier in each pixel unit. Later, JPL spun out a new
company, Photobit, which is specialized in commercialization of CIS technology.
Structurally, CIS mainly consists of photodetector, photocurrent readout circuit,
timing pulse generator, A/D converter, and on-chip digital image processing circuit.
CIS has the advantages of low cost and low-power consumption in virtue of its high
degree of integration and single power supply. The basic working principle of CIS is
depicted in the Fig. 18.8. The pixel cells are arranged in a two-dimensional array in
X and Y directions, each of which could be selected by an address decoder in X and
Y directions, respectively. The column amplifier magnifies the output signal of each
column pixels. Then the magnified signal is sent to A/D converter through the
MOSFET switch. After A/D converter, the digital signal is readout by interface
circuit. The key parameters for CIS performance evaluation are spectral range,
external quantum efficiency (EQE), noise, fill factor, output characteristics and
dynamic range, modulation transfer function (MTF), etc.
Due to the relatively well accumulation of technology in the field of CCD image
sensor, Sony Corp. of Japan developed and commercialized the backside illuminated
(BSI) CIS. This is a 3D stacked CIS technology achieved by placing the active-pixel
sensor unit on top of the semiconductor silicon layer while all other peripheral
18 Products of Sensors and MEMS 375

Fig. 18.8 Basic working

principle of a CIS diagram

analog and digital signal processing circuits are placed at the bottom of the silicon
layer, interconnected by through silicon via (TSV) technology. The BSI topology
greatly improves the photoelectric sensing, signal processing, and overall image
sensing of CIS. OmniVision (merged by Ingenic Semiconductor in 2016) also
launched BIS CIS products with more than 20 million pixels in corporation of
foundry manufacturing at TSMC, HLMC, and XMC. The OmniVision OV6948 is
a BSI sensor with 200  200 pixels; that measured 0.575 mm  0.575 mm to be the
smallest by Guinness World Record [46].
CIS has been widely used in various mobile and consumer electronic systems,
including smart phones and personal computers. Also, it has found wide applications
in the fields of security monitoring, industrial electronics, medical electronics, etc.

Fingerprint Recognition Chip

The Fingerprint Recognition Chip or sensor is used for fingerprint recognition. The
fingerprint identification process includes fingerprint image acquisition, information
processing, matching, and judgment of the collected images. Fingerprint recognition
technology involves a wide range of disciplines, especially for the feature processing
of fingerprint images, which requires the use of mathematical morphology and
wavelet analysis and other disciplines [47]. Pattern recognition and machine learning
algorithms are normally used for fingerprint image matching and recognition.
The fingerprint identification system mainly includes fingerprint sensor and
fingerprint recognition algorithm processing module. For applications with special
function or large amounts of memory, additional peripheral memory modules are
also required. The new fingerprint processing and authentication chip integrates
fingerprint recognition accelerator components, as well as RAM or Flash with
certain capacity.
Fingerprint sensors are usually available in four scanner types: optical, capacitive
or CMOS, ultrasonic, and thermal scanner. (1) Optical: The principle of optical
fingerprint sensors uses refraction and reflection of light, which is, different optical
images produced by the texture of the fingerprint. Therefore, once the fingers are
contaminated with dust or water stains, they will exhibit different characteristics
376 Y.-F. Han et al.

under the light source. However, using a certified fingerprint and fabricate a fake
hand model, it can “deceive” the recognition system. (2) Capacitive: The capacitive
fingerprint sensor utilizes the principle of capacitance charge and discharge, which
has the ability to detect electric charge changing between the capacitance plates, the
changes of charge are recorded and formed into different fingerprint images
according to certain rules. For some contaminated fingers, the charge collection of
sensors will be affected because of the impurities or water stains on the fingerprint, in
these cases, fingers are usually not well recognized. From the user experience, if the
finger has water, or the hand is dirty, the device in use cannot be unlocked.
(3) Ultrasonic: The ultrasonic fingerprint sensors are based on the principle of
medical ultrasound. Those sensors can produce two-dimensional images of finger-
prints, and even recognize the 3D features of fingerprints. Acoustic waves are
generated by a piezoelectric transducer, and the high-frequency sound waves pene-
trate the epidermal layer of the skin to image the superficial tissue under the skin.
Therefore, the ultrasonic sensor does not have a high requirement for the cleanliness
of the fingers and whether the skin of the epidermis is damaged. (4) Thermal: This
type of scanner can sense the temperature differences on the contact surface, in
between fingerprint ridges and valleys. So far, all fingerprint scanners are susceptible
to be fooled by some techniques, such as (a) photographing fingerprints;
(b) processing the photographs using special software; and (c) printing fingerprint
replicas using a 3D printer.
Fingerprint image is the main object in the fingerprint identification process. The
main steps of collection and discrimination are as follows: (1) Fingerprint image
acquisition. (2) Fingerprint image compression. The fingerprint data collected by the
sensor are very large. To reduce the load on the memory, the data need to be
compressed. The main methods include JPEG, Wavelet Scalar Quantization
(WSQ), and Embedded Zerotree Wavelet (EZW) algorithms. (3) Preprocessing of
fingerprint images [48]. The fingerprint image directly obtained by the sensor has a
lot of noise, and the preprocessing is very necessary before the feature recognition.
(4) Fingerprint area detection. Locate the area to be measured. (5) Fingerprint
classification. The main classification method is based on the pattern and texture.
(6) Feature extraction. The main concentrated area of the fingerprint characteristics is
determined by the coordinates of certain patterns. In the coordinate system, details
such as the initial point, the trend, and the position of the last intersection of the line
are marked. (7) Fingerprint comparison. The first step is to match roughly and
classify according to the pattern; the second step is to match the image accurately
based on detailed information; the third step is to judge whether the fingerprint is
matched according to the similarity, if the fingerprint is not in the fingerprint library,
it will not be authorized.
Fingerprint recognition technology is widely used in various fields such as
employee attendance system, mobile phone and laptop unlocking system, security
payment system. Capacitive fingerprint recognition chip is normally used in mobile
phone designing. Meanwhile, traditional optical fingerprint recognition sensors are
18 Products of Sensors and MEMS 377

widely used in other occasion like collection fingerprint information for second
generation ID card, the fingerprint identification of customs clearance.
The main trend of the fingerprint recognition sensor is to improve the recognition
rate of the fingerprint and improve the recognition and unlocking speed of the
fingerprint at the same time.

Touch Controller IC

Touch controller IC refers to the chip that can integrate and complete single-point or
multipoint touch technology, which has many characteristics. (1) The traditional
touch module contains mechanical buttons; that shorten their lifetime after frequent
use. The touch control chip is based on touch technology and works in a touch
manner, thus greatly extending the service lifetime; (2) Touch operation interface is
smooth and beautiful; (3) The sensitivity of the touch screen is flexible and adjust-
able, which can be adjusted by changing the value of its built-in reference capaci-
tance; (4) The built-in capacitor has its own unique characteristics, such as heat
insulation performance, moisture-proof performance, and so on [1]. It is because of
its excellent characteristics that the touch control chip is not affected by temperature,
humidity, and other environmental factors.
Capacitive touch control chip is the main type of touch control chip [49] at
present. When the user touches the chip with fingers or other body part, the effective
cross-sectional area or spacing of the capacitor changes slightly, causing the capac-
itance value to change. There is a built-in reference capacitor in the touch chip. As
the chip is touched, the input capacitor changes that leading to the variation of
electrical signal. This signal is amplified by the analog amplifier circuit and then
output.
At present, R&D companies of touch control chips in Europe and the United
States, such as Atmel (acquired by Microchip in 2016) [50], Cypress [51], Synaptic
[52], etc. are far ahead in technology. These enterprises have accumulated a lot of
good technical experiences in the long-term R&D, which effectively reduces the
noise of the chip and improves the sensitivity, stability, and resolution of the chip. In
the touch controller IC industry, AMOLED products are characterized by accurate
positioning and long service lifetime.
Touch controller IC is faced with the challenges of precise positioning of touch
point, low energy consumption, long lifetime, and other technologies. At present,
gesture touch is becoming a new direction of touch controller IC development. The
gesture touch controller IC not only needs to accurately locate the coordinate of the
touch point, but also needs to accurately identify the gesture and record the swing
track of the gesture, which requires the touch chip to transform the data processing
ability from one dimension to three dimensions. In the short-term, the application
field of touch controller IC will continue to expand in intelligent home, such as
intelligent access control, intelligent ventilation system, intelligent safe, etc.
378 Y.-F. Han et al.

Bio-MEMS IC

The biochip is used in sensing biological information, including macromolecules

such as proteins, antibodies, nucleic acids, and the whole cells, etc. The biochip is
different from an electronic chip because the surface of electronic chip integrates
electronic units while the biochip surface is the antenna array [53].
Currently, there is no classification standard for biochips. In general, there are
three types of BioChips: DNA microarray, microfluidic chip, and protein microarray.
The general classification includes two approaches. One approach is based on the
mode of interaction, and another one is based on the types of biological samples, for
example, biochips can be classified as gene chip, protein chip, cell chip, laboratory
chip, etc. According to the interaction mode, biochips can be sorted to passive or
active. The passive biochip itself contains no power supply and is inactive until the
signal is applied. It will only collect signals during the experimental steps with high
parallelism and occupies a large proportion in the current biochip market. The basic
structure of a passive chip consists of three parts: electronic chip, transducer, and
prober. Biological information can be read and recorded through this general archi-
tecture. The active biochip highly integrates experimental steps of biological signal
analysis and can complete the detection and analysis by one-step reaction. So, the
active mode has high efficiency and simple operation [54].
Biochips are mainly used for molecular composition analysis and medical appli-
cations. Molecular composition analysis is mainly for detection of various biological
macromolecules, such as nucleic acid, protein, and antibody, etc. The most widely
application is for the sequencing analysis of DNA (Deoxyribonucleic Acid) and
RNA (Ribonucleic Acid) [55]. There are three major molecular composition detec-
tion methods including fluorescence disclosure, grid method, and microdeposition
method. Fluorescence method reads the information by the energy intensity of
fluorescence reaction. The grid method is a two-dimensional method. The polymer
material in the chip and the detected object are interacted. Through reading the
molecular chain information of polymer material, biological information of detected
subjects will be directly obtained. The grid method has the disadvantage of poor
repeatability and lower sensitivity. In the microdeposition process, it is first to depose
a macromolecule layer on the detected material surface, and then analyze the
material through the surface topography of deposition. Atomic force microscope
(AFM) is often used for the surface morphology detection with certain requirements
on surface characterization, contact angle of deposition, and the amount of the
detected material [54, 55].
In medical field, biochips are mainly used for diagnosing diseases and screening
drugs. Through collecting the genome information of normal people, building up the
standard gene map, comparing the patient’s DNA or RNA sequence to normal
sample, the DNA map information of the lesion will be obtained. Therefore, the
database of lesion DNA map information can be established. DNA lesion database
can be used as an important means of disease diagnosis, especially for early cancer, it
has great significance. With biochips, the body’s response to a variety of different
18 Products of Sensors and MEMS 379

drugs also could be detected. It is an important method for drug screening and
targeted material screening [56].
Bio-MEMS IC is for the purpose of biological medical diagnosis or biological
information analysis. It is a micron scale device which includes sensors, actuator,
and mechanical structures. Its main applications include the identification and
analysis for biological information, medical diagnosis, tissue cell engineering,
medical injection, and surgical assistance, etc. [57].
Bio-MEMS has similar application for identifying and analyzing biological
information to the biochip technology. The difference is that mechanical structures
of MEMS can better integrate functions for information detection and analyses. For
examples, silicon beam or diaphragm can be used for selectively detecting the
surface free energy of biological surface; the electrical signal variation, such as
resistance and capacitance, can directly reflect biological information. Thus, the
medicine diagnosis using the biological MEMS has advantages of quick response
and more automation. Microinjectors made of GaN can complete the injection
without touching human skin or nerves, to achieve destruction free of cell tissues
and painless sensation [57].

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Applications of IC Products in Consumer,
Computer, and Communication Electronics 19
Yieji Zhu, Hui Liu, Yongxin Liu, Guoqiang Li, and Shengming Zhou

Contents
Electronic Games and Toys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Home Appliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Consumer Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Smart Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Application in Internet of Things . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Smart Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Smart City . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Personal Computer, Desktop, and Their Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Supercomputers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Mobile Phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Data Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Networking and Communication Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Telecommunication Core Network and Access Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Unified Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Y. Zhu · H. Liu
Huaqiang Electronic Industry Research Institute, Shenzhen, China
Y. Liu
Shenzhen Institute of Micro-nano IC and System Application, Shenzhen, China
G. Li
Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd., Shanghai, China
Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, China
ICWise Market Information Consulting (Shanghai) Co., Ltd., Shanghai, China
S. Zhou (*)
Southern University of Science and Technology, Shenzhen, China
e-mail: zhousm@sustech.edu.cn

© Publishing House of Electronics Industry 2024 383

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_19
384 Y. Zhu et al.

Abstract
This chapter introduces the main applications of IC products in the fields of
consumer electronics, computers, and communications. The context contains a
total of 14 entries, covering the IC products used in daily consumer and home
electronics (e.g., electronic games and electronic toys), home appliances, per-
sonal consumer electronics and peripherals, various smart cars, concurrent Inter-
net of Things (IoT) applications, smart homes, and smart cities. The second
category includes personal computers, office workstations and external equip-
ment, and high-end supercomputers. The third category of communication prod-
ucts encapsulate mobile phones, data centers, network communication
equipment, wireless communication core network and access networks, and
future integrated or unified communication fields.

Keywords
Consumer electronics · Computers · Smart cities · IoT · Network

Electronic Games and Toys

There are a couple of game machine manufacturers in the world. Nintendo Corpo-
ration, founded in 1889 in Japan, is a television game developer and machine
manufacturer [1]. Microsoft entered the home game market at the end of 2001, its
product Xbox [2] is a part of Microsoft’s strategy map, and its positioning is not only
a game machine, but also a home Internet platform connecting game players.
Microsoft’s subsequent Xbox 360 and Xbox One have also been successful.
Sony’s home television game machine PlayStation (e.g., PS4) has become one of
the most famous home game machines [3].
Japan Nintendo is the pioneer of electronic video games. In the television era,
Nintendo launched a variety of game products with advanced ideas and game
technology (such as Nintendo Wii), developed a number of classic games, and
established the dominant position in game industry.
The major semiconductor chips used in these above-listed common electronic
game machines and toys are voice chip, microcontroller unit (MCU), sensor chip,
and so on, while the high-end game machines of Microsoft, Nintendo, and Sony
adopt higher performance application processors (APs) and graphic processor units
(GPUs). (1) Voice chip converts analog voice signal into digital signal by sampling
and stores it into chip’s ROM. If necessary, it can also recover the digital voice signal
in ROM to analog voice signal to fulfill man-machine interaction. (2) Microcontroller
(unit) can simplify design and fulfill diversified functions and can meet application
requirements. At present, microcontroller has been widely used in electronic toys.
(3) In modern toy products, sensors with different functions are often used to
empower toy with some intelligent functions.
In the video game console of a Sony PlayStation, various IC components can be
found, including R3000A CPU by MIPS, Geometry Transfer Engine (GTE)
19 Applications of IC Products in Consumer, Computer, and Communication. . . 385

coprocessor, motion decoder (MDEC), system control coprocessor, memory

(DRAM and ROM) chips, GPU by Toshiba, sound processing unit (SPU), I/O,
and peripherals [4].
With the development of artificial intelligence (AI) and robotics technology,
interactive robot and entertainment robot with AI function gradually become acces-
sories in people’s daily lives, and game machine will meet prosperous future.

Home Appliances

Home appliances are divided into white goods and black goods, which entered general
families in the late stage of the second industrial revolution. (1) White goods generally
refer to those appliances which can help people to reduce labor intensity, replace some
housework, or improve the quality of life, its appearance color is mainly white [5]. The
typical white goods consist of air conditioner, washing machine, refrigerator, and other
common home appliances (electric heater, Hoover, air cleaner, humidifier, electric fan,
etc.), as well as emerging sweeping robot and health monitoring appliances, such as
weighing scale, PM25 detector, baby monitoring intelligent camera, sphygmomanom-
eter, blood glucose meter, etc. As a new category of white goods, living appliances and
health monitoring appliances continuously come to market. Sometimes brown goods is
used as a synonym for white goods. (2) Black goods are generally referred to those
home appliances for communication and entertainment. Typical products of black goods
include TV set, video camera recorder, VCD/DVD/BluRay players, set-top box (STB),
Hi-Fi entertaining equipment and home theater system, etc.
At present, the main manufacturers of home appliance are Philips, Sony, Toshiba,
Siemens, Samsung, and so on. China has become a global manufacturing center of
home appliances in the world, and there are many world-class great enterprises of
home appliance with revenue of more than RMB 100 billion, such as Haier, GREE
[6], and Midea [7].
The wave of digital, networking, and intelligence originated from personal
computers, and then extended to personal digital products and cellphones. Now it
has extended to home appliances, it changed products’ function and form of home
appliances, and even customers’ habit. For example, cable TV, satellite TV, and
Internet TV have basically replaced or been replacing the traditional TV set and
DVD/BluRay players, and become the main source of home video content. TV set is
getting more and more powerful in the performance, storage, and network connec-
tion, which integrated lots of functions besides multimedia, interactive on-demand
services, game, education, shopping, etc. The new generation of intelligent speaker
integrates voice interaction and artificial intelligence (AI).
White goods is also getting intelligent and networking, which integrates with
stronger data collecting, processing, storage, and communication functions. It is a
general trend that black goods and white goods and communication devices will be
integrated with each other. For example, Xiaomi’s water purifier, rice cooker,
sweeping robot, and air cleaner can be remotely controlled by wireless network;
Haier has launched a network fridge with camera and display screen, which can issue
386 Y. Zhu et al.

orders to shop, and even automatically issue order according to the consumption
status of items in the fridge in the future.
The main chips used in traditional white goods are microcontroller unit (MCU),
motor driving chip and power management unit (PMU), etc. In the era of the Internet
of Things (IoT), white goods will use a number of application processors (APs),
wireless connectivity chips, diversified sensors, and high-density memory chip. For
example, current sweeping robot has embedded with MCU, Wi-Fi chip, and a variety
of sensors. The main chips in black goods consist of display driving chip, display
control chip, multimedia processor chip, PMU, etc.

Consumer Electronics

Consumer electronics show (CES) started in 1967 in Chicago. In 1998 CES became
an annual event where developers showcase their new technology and innovations,
in Las Vegas in January [8, 9].
Consumer electronic products can be divided into personal consumer elec-
tronic product and household consumer electronic product. Due to the different
level of consumption and technology, there are different types of personal
consumer electronic product in different time periods. In 1970, the very first
VCR (video cassette recorder) was presented to the world; in 1978 the first home
computers were present at CES; in 1996, the very first DVD (digital versatile
disc) was showing off.
For the general public, at the early stage the representative products were
radio, Walkman, home video game machine, and so on. At the later stage the
representative products consist of MP3/MP4 player, digital still camera, and
digital video recorder.
Since 2010, with the increasingly powerful video entertainment function inte-
grated in smartphone, the unit shipment of both traditional personal video entertain-
ment products and digital products of photography and videography had declined,
and then transformed to more specialized and subdivided market. The popularity of
smartphone has brought in new types of smart wearable products, such as smart
watch, smart ring, motion camera, motion healthy tracker, and virtual reality
(VR) glasses. The development trend of smart wearable products is becoming
more intelligent, networking, miniaturizing, specializing, and diversified.
The new generation of smart watch has combined with Bluetooth headphone, and
integrated with multifunctional modules, such as sport records (such as runner
records and calorie consumption data), health (such as heart rate monitor and sleep
monitor), entertainment (such as radio and high-quality songs), communication
(such as using embedded SIM card), and other functions together.
The main chips used in personal audio and video entertainment products
consist of multimedia processor chip, audio codec chip, memory chip, and
power management ICs. The main chips used in photographic products include
CMOS image sensor (CIS) chip, image digital signal processor (DSP) chip, touch
19 Applications of IC Products in Consumer, Computer, and Communication. . . 387

controller chip, display control chip, and power management IC. The main chips
used in the new smart wearable product include sensors, controller, and processor
chip, wireless connectivity (Wi-Fi or Bluetooth) chip, and power management
IC. Due to tough requirement of wearable products in cost, dimension, and power
consumption, many functional chips are designed to be integrated and/or pack-
aged into one chip as system-in-package (SiP) product.

Smart Card

Smart card, also known as IC Card, is the general name of all kinds of cards
embedded with semiconductor chips. Compared with traditional cards with a mag-
netic stripe, the main advantages of smart cards are large data storage capacity,
strong anticounterfeiting ability, antimagnetic, durable, and store digital key, digital
certificate, or fingerprint information, with high security and reliability. One of the
most common smart cards is the credit card, which is 85.5 mm  54 mm in length 
width and 1 mm in thickness.
According to the contacting mode, smart cards can be divided into contact
smart cards and noncontact smart cards. Contact smart card is a chip card that
communicates the IC inside the card with the external reading device through
contacts. Typical products are such as subscriber identity module (SIM) cards in
mobile phones. The working principle of the contactless smart card is that the
reader/writer sends out fixed-frequency electromagnetic waves with the same
frequency as the LC series resonant circuit in the card, and the contactless smart
card, resonates. By accumulating capacitive charges, the circuit of the contactless
smart card provides working voltage and current, and then realizes the data
operation in the card.
After years of development, smart cards are widely used in many applications,
such as communication, financial services, urban management, health culture, public
transport, and intelligent security. According to the applications, smart cards can be
divided into e-government cards, financial telecommunications cards, and other
cards, as shown in Fig. 19.1.
Smart card industry in China began to develop in the 1990s and has formed a
complete industrial chain in security standards and industrialization in the field of
e-government, such as second-generation identity cards, and achieved a domestic
milestone.
Financial smart cards deal with finance business, the cards must meet the secure
regulations and standards. The secure regulations of international financial cards
include the certification of Common Criteria (CC) for Information Technology
Security Evaluation [10] and the certification of EMV standards [11]. The EMV
standards are initiated by Europay, MasterCard, and Visa (EMV), and joined later by
Japan Credit Bureau card (JCB), American Express, China UnionPay, and Discover.
CC certification is defined by Common Criteria Recognition Arrangement (CCRA),
there are 26 member countries by 2016 [10].
388 Y. Zhu et al.

Fig. 19.1 Classification of smart card applications

Application in Internet of Things

When Internet of Things (IoT) was first proposed, it specially indicates the sensor
network depending on the radio frequency identification (RFID) technology. In
1999, Massachusetts Institute of Technology (MIT) first proposed the concept of,
and coined the term, IoT, and the opinion that everything can be interconnected via a
network and expounded the basic meaning of IoT [12]. The International Telecom-
munication Union (ITU) issued “ITU Internet Report 2005: IoT” on the World
Summit on Information Society held in 2005, which extended the connotation and
extension of IoT [13, 14].
The architecture of IoT is shown in Fig. 19.2.
IoT involves data collection, data processing, and data transmission. There are
four technologies related to IoT. (1) The first technology is radio frequency identi-
fication (RFID) technology. If an object is interconnected or is connected to Internet,
it first has an identifiable address. The RFID is the mainstream technology with
bright prospect in identification. (2) The second technology is the sensor technology.
After an object is identified and is connected to the network, the analog information
perceived by sensors shall be converted to digital signals, which will be provided to
local or remote computing center for processing. (3) The third technology is the
embedded technology. Some sensors will process information locally in some
applications and then valuable data are uploaded. The IoT terminal will operate for
a long period. Therefore, local embedded processors shall satisfy strict power
19 Applications of IC Products in Consumer, Computer, and Communication. . . 389

Fig. 19.2 Architecture of IoT [13]

consumption, cost, and performance requirements. (4) The fourth technology is the
radio communication technology. The radio communication technology of the IoT is
divided into two categories, including short-distance communication technologies
(e.g., ZigBee, Wi-Fi, Bluetooth, and Z-Wave) and LPWAN (low-power wide-area
network). LPWAN can be further divided into two types. The first type includes
technologies such as LoRa and SigFox without authorized frequency spectrum.
Another type includes 2G/3G/4G cellular communication technologies working in
authorized frequency spectrum such as EC-GSM, LTE Cat-M, and NB-IoT.
The IoT application chips include RFID label chip, MEMS sensor, wireless
connection chip, and MCU. The RFID system is composed of the transmission
terminal and receiving terminal. Generally, the radio communication technology is
used to identify a target and read/write related data. RFID label is used as a
transmitter. Each label includes unique electronic code to identify target objects.
RFID labels can be divided into low-frequency (LF) radio frequency card working at
125 kHz and 134.2 kHz frequency, high-frequency (HF) radio frequency card
working at 13.56 MHz, and ultrahigh frequency (UHF) radio frequency card work-
ing at 433 MHz, 915 MHz, 2.45 GHz, and 5.8 GHz [15]. RFID labels can also be
divided as read-only card, read/write card, and CPU card. The RFID chips are
composed of RF/analog front end, MCU core, and memory.

Smart Home

The IC application in smart home concept aims to serve for convenient, comfortable,
secure, healthy, and energy-saving living experiences by using advanced technolo-
gies for daily life, e.g., IoT, cloud computing, mobile Internet, and big data [16].
Smart home is the basic units of a smart city.
390 Y. Zhu et al.

Smart furniture interconnects home electrical appliances and home devices via
communication technologies (e.g., Bluetooth, Wi-Fi, ZigBee, PLC, etc.), then it
connects to the Internet via home gateway, and finally smart furniture can be
controlled via smartphones and the Internet.
The smart home concept is expanded from the smart furniture, which intends to
improve consumer’s home experiences via services and with truly useful home
information. In practice, the smart home application is designed to solve the elderly’s
chronic disease management and emergency call via smart medical treatment,
improve home air quality via smart air management, and reduce home energy
expense via smart energy management. The smart furniture controls and instructs
the hardware in a smart home. Smart home and smart furniture can realize control
and automation of multiple systems, e.g., lighting, heat collection, ventilation,
air-conditioner (smart environmental control) and security, and home appliances
(e.g., washer, dryer, oven, refrigerator, and icebox). The main electronic hub com-
ponents in a smart home can be composed of bedroom, kitchen, bathroom, nursery,
living room, garage, and backyard or garden, etc.
A smart home is the minimal unit of a smart city. With the home service as the
core, the smart home provides services with hardware to improve consumer’s home
life experiences as the root foothold. Main participants of the smart home industry
include Internet companies, real estate companies, smart home platform companies
(integrated solution provider), service providers, hardware manufacturers, chip
manufacturers, software manufacturers, operational integrators, etc.
The smart home is an integrated system with multiple hardware and diversified IC
chips [17], such as sensors (temperature, humidity, smoke, hazard gas sensor, etc.),
communication (Wi-Fi, Bluetooth, ZigBee, PLC, etc.) chips, embedded processor
chips (MCU and AP), power management chips (PMU), etc.

Smart City

The smart city targets to integrate ICT (information and communication technology)
and IoT (Internet of Things) together and to become more intelligent and efficient
operations and management [18].
A smart city includes concepts of peace city, smart traffic, smart e-government,
smart home, smart medical treatment, smart education, smart building, smart energy,
smart city governance, smart logistics, smart tourism, smart water, and smart rubbish
management system. Therefore, it is a complicated, interconnected, interactive, and
integrated system. The fundamental technologies needed in a smart city include
software and hardware of IoT, cloud computing, big data, information security, and
mobile application, as shown in Fig. 19.3. No doubt, a smart city will utilize ICs in
wide spectrum for diversified state-of-art technologies for supervision, control, and
analysis, in various applications.
The smart city industry is projected to be a $400 billion market by 2020, with
600 cities worldwide. These cities are expected to generate 60% of the world’s GDP
by 2025 [19]. The technology behind the smart city is IoT, which is a network of
19 Applications of IC Products in Consumer, Computer, and Communication. . . 391

Fig. 19.3 Fundamental architecture of smart city industry

physical connected devices, like vehicles or home appliances, which enable these
“things” to connect and exchange data [20].
The IC products for IoT related and used in the smart city can be classified into
several categories, such as for energy saving, transportation, data handling, infra-
structure, and mobility.

Personal Computer, Desktop, and Their Peripherals

There are three major types of personal computers (PCs), namely desktop computer,
laptop or notebook computer, and tablet computer. (1) Desktop computer is the most
traditional product, its host computer and display monitor are relatively independent
and bulky, so that they are on desk. (2) Compared with desktop computer, laptop or
notebook computer has smaller size, lighter weight, more portable for carry-on at
traveling, and suitable for mobile operation [21]. The development trend of note-
book computer is to be ultralight and ultrathin. (3) Tablet has better portability,
replacing keyboard with touch screen, and users can input with fingers or handwrit-
ing pen [22]. The IC in tablet is either the ARM architecture or 86 architecture. The
representative tablet based on ARM architecture is Apple iPad and Android tablet,
which are closer to smartphone; the representative tablet based on 86 architecture
is Microsoft’s Surface, which is closer to notebook computer.
The main ICs used in desktop and notebook computer consist of CPU, North
Bridge chip, South Bridge chip, memories, I/O, and other peripherals. CPU chip is
the core chip of personal computer. North Bridge chip is one of the most important
chips on PC motherboard, also known as the main bridge. North Bridge chip is in
charge of connecting high-speed devices such as DRAM and video graphics card. It
is nearest to the CPU for close communication with the CPU. South Bridge chip is
another important chip in the motherboard chipset, mainly for communication
among I/O buses. South Bridge chip does not directly connect with CPU, but
through North Bridge chip. It is generally far away from CPU for easy layout. In
392 Y. Zhu et al.

addition, there is dynamic random-access memory (DRAM), which is a large-scale

IC that can access, read/write, data at any time, and consists of many memory cells.
To expand memory size easily, several DRAM chips are soldered on the DRAM bar
together. Computer manufacturers write data into read only memory (ROM), users
cannot usually modify the data in ROM, and these data will not lose even if the
power of computer is turned off. ROM is usually used to store the basic input/output
system (BIOS) information of the computer.
The computer’s peripheral devices [23] are the joint name of input/output devices
of computer system. It can be divided into input devices, output devices, input/
output interface, and external memory, including display monitor, keyboard, mouse,
printer, scanner, mobile storage, etc.
The major chips used in computer peripheral devices are touch controller chip,
modem chip, flash memory chip, and so on. Touch screen is an electronic product
that fulfills human-computer interaction through touch controller chip. At present,
capacitive touch screen is widely used. Its basic principle is that the touch of human
finger will change the capacitor value of the corresponding position of touch screen,
the corresponding position can be identified and obtained by its algorithm, and the
corresponding operation can be called by application software. Modem chip gener-
ally consists of three hardware modules: controller, data pump, and data processor.
Nowadays, most of peripheral devices still generally use NOR flash memory chips
for code storage, while data storage products such as U-disk and SSD solid-state
hard disk have fully used NAND flash memory chips.
The professionals in semiconductor, IT, and scientific research industries still
widely use workstation for conventional working equipment instead of PCs. The
features of the workstation are prominent performance, large size display screen,
clear image, and visual comfort [24]. The users of workstation are usually
interconnected through local area network (LAN), use multiuser operating system,
and call the shared software and data for analysis. Depending on the amount of staff,
the center of the LAN is often composed of one or more server farms.

Supercomputers

There are demand for computers with high performance in the areas of commerce,
industry, transportation, defense, etc., therefore servers, mainframe computers, and
supercomputers are widely used. Servers, mainframe computers, and supercom-
puters are high-performance computing devices. High-performance computing is
measured by the number of floating-point operations per second (FLOPS), as
replacing the unit of MIPS (million instructions per second) used by general-purpose
computers. In 2015, supercomputers can hit the capacity record of PFLOPS (Peta
FLOPS). Previously there were two supercomputers run on Unix, to date, all of the
top 500 supercomputers are operating on Linux system.
Servers are commonly available [25] today as they are typically used by compa-
nies and governments to serve many customers simultaneously over the network.
The server has many advantages in terms of reliability, scalability, and
19 Applications of IC Products in Consumer, Computer, and Communication. . . 393

manageability, and it is usually required that the server has capabilities of high-
throughput computing and multitask computing. Mainframe computers use special-
ized instruction sets, operating systems, and application software to handle the
application tasks of large organizations, such as census, industrial, and consumer
statistics, enterprise resource planning, and other large-scale data processing tasks.
A supercomputer is a huge computer system that is mainly used to undertake
strategic major scientific research, such as quantum mechanics, weather forecasting,
oil exploration, missile rockets, medical research, and so on. Supercomputers began
in the 1960s [26]. In 1983, China successfully developed a galaxy supercomputer
capable of more than 100 million operations per second. In 2004, Sugon entered the
world’s top 500 supercomputers [27] for the first time, ranking tenth. In 2010, the
Tianhe-1 supercomputer was completed in Tianjin, with its peak computing speed of
4700  1012 FLOPS and its continuous computing speed of 2566  1012 FLOPS,
ranking the first in the world. In 2013, Tianhe-2 was successfully developed, and was
ranked the sixth world supercomputer champion. In June 2016, it reached 54  1015
FLOPS, setting a new world record. In 2017, Sunway Taihulight is equipped with
40,960 SW26010 high-performance processors, ranking first in the world. In 2017,
the top 10 supercomputers are shown in Table 19.1, the top 2 and 3 supercomputers
all use Intel processors, the top 4 use AMD processors, and the top 5 use IBM
processors.

Mobile Phone

In April 3, 1973, Martin Cooper of Motorola used a mobile phone to place a very
first wireless phone call [28], the patent for DynaTAC (dynamic adaptive total area
coverage) was filed on October 27, 1973 (US patent No. 3,906,166). The mobile
phone measured 22.86 cm long, 12.7 cm deep, and 4.44 cm wide and weighed
1.1 kg. Ten years later, the first ever portable mobile phone in 1983 was commer-
cially released as the Motorola DynaTAC 8000X [29], it costed $4000! So far, the
development of mobile phones has gone through three stages: from feature phones
that can only make calls and provide short message service (SMS) to multimedia
phones that have added multimedia functions (such as video and music), and up to
now become the fully functional smartphones.
Various chips in a mobile phone can provide wireless WAN, wireless LAN, near-
field communication (NFC), and application processing functions. Currently, the
development is toward the direction of “integration,” “multicores,” “multifunc-
tions,” and “small size with low cost.” Important ICs in a mobile phone include
baseband (BB) chip, application processor (AP), RF chip, memory chip, sensor,
PMU, etc.; see Fig. 19.4.

1. Baseband chip: mainly used to process 2G/3G/4G multiple communication pro-

tocols, to modulate or demodulate baseband signals or radio (for example, audio
signal may have a baseband range from 20 Hz to 20 kHz). At present, there are
generally two schemes: one is put an application processor (AP) into the system
 394

Table 19.1 2017 Supercomputer top 10 ranking (49th annual) [27]

Maximum computation speed Maximum computing
Rank measured value/PFLOPS speed peak/PFLOPS Name Version Microprocessor Country and manufacturer
1 93.015 125.436 Shenwei MPP SW26010 Wuxi National Supercomputer
Taihuzhiguang Center, China
2 33.863 54.902 Tianhe-2 TH-IVB-FEP Xeon E5 Guangzhou Supercomputer
Center, China
3 19.590 25.326 Piz Daint Cray XC50 Xeon E5 Swiss Cray
Supercomputer center
4 17.590 27.113 Titan Cray XK7 Opteron ORNL, USA
5 17.173 20.133 Sequoia Blue gene A2 (Power) LLNL, USA
6 14.015 27.881 Cori Gray XC40 Xeon Phi Energy research, USA
7 13.555 24.914 Oakforest- Fujitsu Xeon Phi HPC Collaborating center, Japan
PACS
8 10.510 11.280 K Computer Fujitsu SPARC64 Institute for Advanced Research
in Computing Science, Japan
9 8.587 10.066 Mira Blue gene A2 (Power) America, ANL
10 8.101 11.079 Trinity Gray XC40 Xeon E5 America, LANL
Y. Zhu et al.
19 Applications of IC Products in Consumer, Computer, and Communication. . . 395

Fig. 19.4 Schematic diagram of mobile phone chip [1]

on chip (SoC), referred to as integration scheme, the representative manufacturers

are Qualcomm, MediaTek, SpreadTrum, and Huawei; the other uses a separate
modem baseband chip, the representative manufacturers are Qualcomm and Intel.
2. Application processor (AP): developed to process various functions (except
communication function) in a mobile phone, such as audio/video playing,
image processing, etc. Rapid development of AP has gone through from single
core to multicore, and from single function to multifunction; AP has evolved to
become a complex SoC in a mobile. As in 2018, popular AP enlisted are Apple
A13 Bionic [30], Qualcomm Snapdragon 855, Hisilicon Kirin 990, Samsung
Exynos 9825, etc.
3. RF Chip: used for amplification, frequency modulation, and transmit/receive RF
signals. There are a large number of RF chips used in mobile phones, including
power amplifiers, RF switches, and filters. The mainstream manufacturers are
Skyworks, Qorvo (merger of RFMD and TriQuint), Avago, and Anadigics.
4. Memory chip: The main types of memory chips are DRAM (dynamic random-
access memory) and NAND flash (data storage). The mainstream manufacturers
are Hynix, Samsung, etc.
5. Sensor: It is mainly used to collect various natural signals and then convert them
into electrical signals for application. There are a variety of sensors, including
accelerometers, electronic compass, gyroscope, proximity and ambient light chip,
camera, infrared sensor, fingerprint recognition chip, etc.
6. Power management chip: manage the power conversion, distribution, and detec-
tion. It mainly includes power management unit (PMU), low dropout regulator
(LDO), battery charging chip, wireless charging chip, overcurrent protection
chip, etc. Mainstream manufacturers include Microchip, ON Semiconductor,
ADI, MTK, Qualcomm, and Hisilicon.
396 Y. Zhu et al.

7. Driver chip: convert the digital signal from the baseband chip into the
corresponding analog voltage value, and drive the components to work, including
universal serial bus (USB) driver, liquid crystal display (LCD) driver, TouchPanel
(TP) driver, etc.

Data Center

Data center is the critical infrastructure of enterprise information which can help
enterprise to share and work together with the centralized data [31]. In general, a date
center includes computer system and associated equipment (communication system
and storage system), redundant data communication connections, environmental
control equipment, and many kinds of security devices such as servers, Internet
switches, storage device, UPS power, Internet monitor equipment, Kernel-based
virtual machine, server control, etc. Fig. 19.5 shows the structure of the data center.
With the development of big data and cloud computing, several models of cloud
service have been proposed [32], viz. infrastructure as a service (IaaS), platform as a
service (PaaS), software as a service (SaaS), etc. All the implementation will bring
up the new requirement for the HW/SW codesign technique of electronics industry
including high-performance CPU design, high-speed memory design, and high-
speed interface design.
The main chips used for data center are server chip and Internet switching chips.
(1) Server chip includes CPU and chipset. Chipset can be divided to North Bridge
and South Bridge chips according to their location in the board. Intel 86 is the

Fig. 19.5 Schematic of data center network

19 Applications of IC Products in Consumer, Computer, and Communication. . . 397

dominant CPU technical specification and standards for servers. Intel Xeon and
AMD Opteron are the typical CPU of sever chips and make up most of the server
CPU market. IBM POWER chips are mainly used for high-level market. Currently,
ARM is also trying to design CPU architecture for servers. AMD and Broadcom
have already designed chips on ARM architecture. (2) The performance of switch
always determines the degree of the intelligence and informatization of the
data center. The specific IC can improve the switching efficiency by switching
the data information in parallel from all the ports at the line with high speed,
which can achieve higher performance than traditional bridge switches. Cisco switch
takes in-house chips, and other switch uses the Broadcom chips. Top server manu-
facturers by market shares in 2018 include Dell, HPE, Inspur, Lenovo, and
IBM/Huawei/Cisco on par.

Networking and Communication Equipment

Communication net consists of transmission, switching, and terminal. Physically, it

is usually made up of networking communication equipment and transmission
medium, such as network cards, hub, switch, router, network line, RJ-45 connector,
etc. Networking and communication equipment [33] mainly include switches,
routers, servers, etc.
Broadly speaking, there are two types of switch, wide area network (WAN)
switches and local area network (LAN) switches. WAN switches are mainly used
in the telecommunication field and provide basic communication platform. LAN
switches are used in local area networks to connect terminal devices, such as PCs and
network printers. According to the network hierarchy, switches can be divided into
three types: access switch, convergence switch, and core switch, as shown in
Fig. 19.6.
The core chips of switches mainly include high-performance CPU, high-
performance network processor (NP), special ASIC, and high bandwidth interface
chips. The mainly used network switch chips are designed by Broadcom, Marvell,
and others. The high-end switches mostly use Broadcom switch chips. At present,
Hisilicon Semiconductor has successfully developed the Ethernet processor of the
switch for high-end applications in China.
Router is a data packet forwarding device working in the network layer, and its
typical function is data channel and control. The key technology of new generation
core and high-end router is network processor (NP) supporting multirouting pro-
tocols, which is usually composed of several high-performance CPUs and several
hardware coprocessors (in ASIC form).
Server refers to the equipment that runs the application software under the
network environment and provides users with shared information resources and
services. Servers consist of processors, hard disks, memory, system buses, etc.
They are customized for specific network applications, and usually are the center
of the network. They have the characteristics of high performance, high reliability,
high availability, high I/O throughput, large storage capacity, strong networking, and
398 Y. Zhu et al.

Fig. 19.6 Location of switches in network

network management capabilities. There are CPU chips, memory control chips, and
network interface chips in server solutions.
In today’s networking and communication equipment assembly, switchboard and
server are physically bulky; traditional installed switchboard has expanded its
function from merely telephone exchange to networking and telecommunication
instrument sets include routers and servers in the distribution and application [34].

Telecommunication Core Network and Access Network

The core network [35] is a main portion in a telecommunication network, which

offers numerous services to the customers who are interconnected by the access
network [36]. Stored program control (SPC) exchange is a very important milestone
in the development of telecommunication network, especially in digital SPC
exchange, which is a significant point that communication technology transits
from analog to digital. In the first place, central office (CO) is constructed by
exchange room, power room, and MDF (main distribution frame) room, and cables
are initially aggregated from MDF room to exchange room.
With the development of technology, new access technology is adopted such as
remote module, V5, and 450 MHz wireless loop; mobile communication
19 Applications of IC Products in Consumer, Computer, and Communication. . . 399

subsequently has been used; mobile switch centers (MSC) are setup in CO and a lot
of BSS (base system stations) are setup everywhere. At present, communication
network architecture is evolving from traditional circuit domain to flat IP domain.
The core network is named as IP multimedia subsystem (IMS), and communication
services generally include voice communication, broadband service, video service,
audio and video conference, multimedia service, etc.

1. Communication core network and access network based circuit switch mode
Circuit switching is characterized by communication from call setup, call
connection to call termination. The entire process requires exclusive user circuits,
trunk circuit, and TSI (time-slot interchanger). SPC is a core equipment in circuit
switch mode (CSM), it is an extremely complex telecom system, the architecture
of CSM design is modular, and through combination and stacking different
modules can provide more functions and capacity. SPC system is constructed
of central process unit, switch net, clock, trunk, signaling, as well as user and
power subsystem.
2. Soft switch
Character of soft switch is independent between call control module and media
bearer, it includes two function entities, call server (CS) and media gateway
(MG). Call server implements user register, user authentication/authorization,
call control, signaling, route, and final account functions. Media gateway pro-
vides user access and media resources. CS and MG are connected through IP
MAN or WAN; MG can be located in aggregation of residence community so
lengthy copper cable can be saved.
3. IP multimedia subsystem (IMS)
Character of IMS is IP and flat network. It includes fixed public switched
telephone network (PSTN) based CSM, 2G/2.5G (GSM/GPRS) mobile telecom
network, full IP 3G/4G mobile telecom network, and WLAN based Wi-Fi and
HFC (hybrid fiber coaxial) network–based cable modem.

Increasing number of ICs has been used in telecom equipment, in addition to

main chipset, CPU, memory, and flash; there are also PCI (peripheral component
interconnect) controller, USB controller, Ethernet controller, UART, power manage-
ment chip, TSI (time-slot interexchange), E1/T1 trunk interface, FPGA, user inter-
face ASIC and DSP, etc.

Unified Communication

Unified communications (UC) is a business and marketing concept describing the

integration of enterprise communication services [37] such as instant messaging
(chat), presence information, voice (including IP telephony), mobility features
(including extension mobility and single number reach), audio, web, and videocon-
ferencing, fixed-mobile convergence (FMC), desktop sharing, data sharing
400 Y. Zhu et al.

(including web connected electronic interactive whiteboards), call control, and

speech recognition.
With the booming development of communication services, short messaging
service (SMS), broadband, video, games, and Internet applications other than tradi-
tional voice services have become important services of communication networks.
These network services developed through the rapid growth of computer technology,
and have gradually generated to the form of content delivery/distribution network
(CDN), Internet protocol television (IPTV), Internet data center (IDC), and other
new infrastructure applications in communication field. Finally, those services have
increasingly become an important part of telecommunication network.
The main purpose of using content delivery/distribution network (CDN) technol-
ogy is to increase access speed, solving the problem in cross-domain interconnec-
tion, large capacity, and high concurrency of new services such as games and videos,
and to improve user experience. CDN initially appeared in around 2005, and it
gradually integrated the communication network with Internet, involving technolo-
gies such as domain name system (DNS), content store, dispatching and broadband
bearer networks. Currently, telecom operators and various Internet operators have
deployed CDNs. There are even some vendors that specialize in CDN operation
services [38] due to the huge demand.
With the rapid growth of video, games, and other communication services, CDN
is driving its business climax in the past decade. In addition to the acceleration on
telecom carrier network technology, CDN also uses many PC and storage technol-
ogies, especially for high-performance CPUs, high-speed communication buses, and
large-scale memory control chips that are supposed to of higher demands. In the
future, higher performance, reliability, and security are expected, and local area
network (LAN), ultrahigh speed fiber-optic communication, flash memory, and
control will become the key technologies.
The convergence of traditional telecommunication networks, broadcasting net-
works, and computer networks is a trend with the development of Internet protocol
(IP) technology. In the future, all digital communication facilities will support the
communication of all services including data, voice, and video. The typical repre-
sentative of tri-network integration [39] is network TV service. It uses broadband
network and a new generation of AV technology to integrate Internet, multimedia,
and communication technologies, providing home users with a variety of interactive
services such as digital TV. The usual IPTV system is a large-scale solution covering
set-top box devices, such as terminal set-top boxes, streaming media server CDNs,
content management systems (CMS), and encoders.
In recent years, smart homes have also promoted the rapid development of IPTV.
Home entertainment and communication solutions such as IPTV with the concept of
tri-network integration involve many converged technologies, such as AV codec,
storage and distribution, content security and protection, etc. That technology has
largely driven related IC industry to fast development. Among them, set-top box
chips, home gateway chips, digital certificate authority (CA), and digital rights
management (DRM) security chips have been widely used; typical chips such as
Hisilicon Hi3716, Hi3798, etc. were also used.
19 Applications of IC Products in Consumer, Computer, and Communication. . . 401

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Applications of IC Products in Automotive,
Industrial, and Medical Equipment 20
Quan Yan, Qiquan Zhang, Xin-An Wang, and Huan Liu

Contents
In-Vehicle Infotainment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Body Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Powertrain Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Automotive Active Safety System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
New Energy Vehicles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Advanced Driver-Assistance System (ADAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Rail Transit System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Smart Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Application of New Energy Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Medical Imaging Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Medical Electronic Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Medical Monitoring Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Medical Electronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Implanted Medical Electronic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Medical Robot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Abstract
ICs and electronic products in automobiles, industrial, and medical care are
closely related to people’s daily transportation, convenience, safety, and health.
The continuous advancement of products in these fields continues to improve

Q. Yan
Mentor Graphics, Shanghai, China
Q. Zhang
Harbin Institute of Technology, Shenzhen, China
X.-A. Wang (*)
Electronic and Computer Engineering, Peking University, Shenzhen, China
e-mail: wangxa@pkusz.edu.cn
H. Liu
Southern University of Science and Technology, Shenzhen, China

© Publishing House of Electronics Industry 2024 403

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_20
404 Q. Yan et al.

overall the quality of our life. ICs are playing an increasingly important role in the
performance improvement, cost reduction, feature enrichment, and humanization
of products in these fields and even play a decisive role in the transformational
success of certain types of products in a certain period. These are also areas where
the demand for ICs is steadily increasing.

Keywords
Automobiles · Industrial, medical care · Integrated circuits · Quality of life

In-Vehicle Infotainment

Automobiles are becoming intelligent and networked. As a means of transportation,

automobiles have also become a platform for people to entertain and access infor-
mation. In-Vehicle Infotainment (IVI) refers to vehicle systems designed to meet
drivers and passengers’ comfort, entertainment, and information needs [1]. IVI not
only controls it through vehicle-borne special processor, operating system, controller
local area network (LAN), and so on, but also connects the external world through
public 3G/4G and upcoming 5G mobile network, satellite navigation technology,
Wi-Fi, Bluetooth, and USB communication technology to realize mobile Internet
services.
IVI originated from automobile audio and video system, including radio, tape
player, and CD player. With the development of science and technology, the IVI has
integrated many functions and applications, such as audio and video broadcasting,
real-time road condition and navigation, voice control, security diagnosis, games,
e-mail, news and information, mobile phone interworking, and so on. In the future,
the IVI will be further integrated with functions such as automatic driving.
The increasing informationization of society has led to the increasing complexity
of IVI, such as supporting a variety of mobile operating systems. GENIVI Alliance
[2], a nonprofit organization, was established in 2009 to promote collaboration
between automobile manufacturers and software developers, share an open source
platform for the development of standard IVI, shorten the development cycle and the
process of listing, and stimulate the innovative potential of IVI.
IVI is not only a hardware component, but also a content service. It realizes
seamless information exchange between the inside and outside of the vehicle,
improves the safe interaction between drivers and the outside world, and integrates
many kinds of vehicle infotainment projects, e.g., Internet, multimedia, navigation,
and information.

Body Control Module

The Body Control Module (BCM) system is a general term used to monitor and
control the various electronic control unit-operating modules in the body and
electrical designs [3]. The BCM is analogous to the central nervous system in the
20 Applications of IC Products in Automotive, Industrial, and Medical Equipment 405

human body. The coordination of the human body is controlled by transmitting

signals, while the control module regulates the operation and coordination between
different parts of the car by using signals. The BCM controls a variety of automation
and comfort functions (Fig. 20.1) in addition to controlling power windows, power
mirrors, air conditioners, antitheft systems, central locks, and more (such as wiper
control, headlight control, relay control, etc.).
BCM is used to monitor and control vehicle body-related functions, as well as
Controller Area Network (CAN) and Local Interconnect Network (LIN) communi-
cation support. CAN [4] is a high-speed dual-line differential data bus, which
controls the communication between microcontroller and various electronic modules
in the vehicle. It is a message-based protocol originally used for multiple wires in
cars. LIN [5] is an inexpensive serial network protocol for communication between
vehicle components, which can effectively support remote applications in vehicle
networks. Because LIN is relatively slow, it is suitable for the electromechanical
nodes in the layered network in the car as supplement to CAN network.
At this stage, BCM demand is developed through the development of a central-
ized BCM governance structure, which can avoid the fragmentation that may occur
when BCM is developed by different business units. By centralizing, the various
components of the plan can be better integrated and aligned with overall business
goals of the organization.
The two main components of the BCM design are the control system and the
power system. Unlike traditional hardware control, microcontroller units (MCUs)
can be divided into hardware peripherals and software algorithms. The advantage of
the MCU is that it can realize self-diagnosis within the system, effectively improving
the robustness and reliability. The main load driver types for the central controller are
lighting and relay drivers. BCM systems are also sometimes required to supply
power to high-power loads, primarily through relays or relay drivers. Current
monitoring of distributed loads can be used for car battery charging and load
management. The power supply of the BCM is usually a 12 V or 24 V power supply
network, and the voltage can be adjusted as needed for DSP, memory, IC, etc. Since
the MCU needs to work when the car is not in operation, it must support the standby

Fig. 20.1 System

architecture of the Body
Control Module
406 Q. Yan et al.

mode of the MCU. At the same time, the car usually faces a higher-temperature
environment, and the power supply needs to have an over-temperature protection
function.
Common radio frequency identification (RFID) technology has also been widely
applied to engine antitheft lock systems and door and alarm systems. The frequency
of BCM is 315 MHz (US/Japan) or 433 MHz (Europe) to achieve high-frequency
transmission and reception; these frequencies are as well as used in remote control
and tire pressure monitoring systems (TPMS) [6].
The BCM is a very important part of the vehicle. With the development of
technology, more Active Body Control (ABC) templates are added into the system
design [7] and are connected with power control module and other functional
modules such as communication or sensing. This requires the BCM continuously
toward higher degree of integration and scalability, in order to meet the high-speed
development of automotive electronics industry.

Powertrain Control Module

Powertrain control module (PCM) used on motor vehicles [8] is considered the
“brain” of the engine control systems (ECS), which is also called the electronic
control unit (ECU). PCM controls the clutch’s disengagement and shifting action
and also controls the engine’s oil supply through other electronic devices, thus
realizing joint-control of powertrain (engine, clutch, transmission, etc.).
The subsystems of data sensing and ECU are the key components of PCM. Data-
sensing subsystems are primarily composed of various sensors. For example, each
sensor collects relevant parameters required for the shift action and passes the signal
to the ECU. The vehicle must be driven by following the driver’s intention. PCM
must correctly understand and realize the driver’s control [9]. The sensor senses the
changes of the control mechanism, such as the accelerator pedal, the brake pedal, and
the steering wheel angle, and understands the driver’s intention after analysis by the
ECU. In addition, other signals can be passed through switches and controllers.
As ECU is the heart of the control system [10], it changes the working state and
the shifting gear according to the driver’s intention based on the detected vehicle
running state signal. The main functions of the ECU include data acquisition, data
preprocessing, vehicle status recognition, driver operation intent recognition, shift
decision, and quality control, as well as fault diagnosis, output, display control, and
so on. ECUs today use high-performance 16-bit/32-bit microprocessor (MPU), and
even fully customized microprocessors, or microcontroller units (MCUs) to enhance
circuit functionality and improve control reliability.
Through sensor’s sampling, PCM receives the signal and sends it to the ECU; the
latter processes the data and sends the control signal to the actuator to realize
the control of the powertrain, adjust the working state of the powertrain, and ensure
the control of the vehicle.
20 Applications of IC Products in Automotive, Industrial, and Medical Equipment 407

PCM generally has three control modes: two-machine or multimachine control;

single ECU controls the engine and the transmission as a whole; and using a CAN
bus for overall control.

Automotive Active Safety System

Automotive safety system consists of automotive active safety system (AAS) and
passive safety system (PAS) [11]. Active safety system detects potential safety risks
on the road and takes actions actively to avoid hazards of potential collisions.
Passive safety system protects the driver and passengers from getting further harm
when the accident occurs; it composes of the general Global Outstanding Assess-
ment (GOA), seatbelts and seatbelts’ pretightening function, air bags, special made
safety window glasses, and steering column energy attraction device [12]. Thus,
such electronic system should be based on various special automotive ICs [13] with
high reliability and powerful functions.
Active safety system includes the following components.

1. Collision avoidance system (CAS), also known as Forward Collision Warning

System (FCW). CAS is used to avoid possible collision by detecting the forward
risky situation of automotive. Normally FCW is formed of part of radar system,
laser detector and electronic camera, etc. Radar system finds the risky situation
forwardly, and it includes transceiver RF circuits, ADC circuit, data-processing
CPU, and central control unit, warning display, and voice process circuits.
Laser-detector module assesses the risky level of automotive, and it includes
semiconductor laser, opto-electronic transceiver, fiber-optic transmission circuit,
data-processing CPU and central control unit, warning display, and voice
process circuit. Electronic camera module observes the complex road condition
and takes action to protect automotive in safety. It is comprised of CCD camera,
CCD image control unit, warning display, and voice-processing circuit [14].
2. Lane Departure Warning system (LDW). By comparing the position change of
moving automotive inside the lane, LDW system will issue a warning for
deviating behavior of automotive. Now it mainly uses image recognition tech-
nology to predicate lane departure behavior.
3. Electronic Stability Control system (ESC). Keep automotive in best stability
status by controlling driving force in unusual circumstance. ESC covers MCU
control unit and sensors for measuring the automotive track deviation, angular
velocity of the wheel, the steering angular offset, and hydraulic slowdown
control device.
4. Antilock Braking System (ABS). Protect brake system from lock mode and
make sure the driver still can control the driving direction under braking
condition [3]. ABS contains MCU, sensors with angular velocity of the wheel,
and hydraulic brake control units.
408 Q. Yan et al.

5. Electronic Brake-force Distribution system (EBD). Normally work with ABS

and reassign brake force to ensure driving safety. It covers sensor of wheel
speed, electronic control unit, and hydraulic actuator.
6. Traction Control System (TCS). When automotive braking or speeding up on
the road is having less friction force, TCS will adjust the output of wheel torque
to assure automotive in better control and driving direction stability status. As a
supplement of ABS, both TCS and ABS employ same control system, e.g.,
MCU, sensors with angular velocity of the wheel, and hydraulic brake control
units.
7. Emergency Brake Assist system (EBA). Help driver to reduce the braking
distance in emergency. It includes MCU, sensor, and control actuator.
8. Brake Override System (BOS). Ensure safe braking action by control gasoline
emission level.
9. Tire Pressure Monitoring System (TPMS). Monitor whether the tire pressure is
in normal range. It is made of pressure and temperature sensors, radio trans-
ceiver circuit, and display warning circuit.
10. Intelligent Parking Assist System (IPAS). Help driver to park safely. It covers
CCD camera, ultrasonic transceiver circuit, and image and voice warning
unit [4].

New Energy Vehicles

New energy vehicles (NEVs) refer to the vehicles that use nontraditional gasoline or
diesel fuel as power sources, which include pure battery electric vehicle (BEV), fuel
cell electric vehicle (FCEV), hybrid electric vehicle (HEV), and so on [15, 16].
ICs are more widely used in NEVs than in traditional cars. In addition to the well-
known In-Vehicle Infotainment (IVI) System, Body Control Module (BCM) Sys-
tem, Powertrain Control Module (PCM) System, Automotive Active Safety System
(AAS), and Advanced Driver-Assistance System, the Electronic Control System
(ECS) of NEV generally includes the Electric Motor Control System, the Vehicle
Control System, and the Battery Management System (BMS), the core of which is
the BMS [17, 18].
BMS is an important part of new energy vehicles; its main role is to improve the
utilization of batteries in new energy vehicles, balance battery power to maintain
battery consistency, extend battery life, and assess and monitor battery capacity
accurately. The core part of BMS consists of hardware circuits, underlying software
and application layer software. The current mainstream battery detection ICs in the
industry are mainly from Linear (LTC6803), ADI (A7280A), TI (BQ76PL536),
Maxim (Max1 1080), and so on.
In a BMS IC design for lithium (Li) battery cells, the primary function is to
maintain the cells working within the safe operation region. The BMS IC should be
ensured that when the voltage of the battery cells is lower than the rated voltage,
BMS IC must prohibit the cells from discharging. On the other hand, the charging
20 Applications of IC Products in Automotive, Industrial, and Medical Equipment 409

process should also be monitored and controlled. For example, to prevent battery
damage or reduced life span, sensors are used to monitor and control the status of the
battery, such that the battery is at a contact charging current at the beginning or at a
very low current toward the end of the charging process. Therefore, BMS IC design
can include both traditional MCU in combination with sensors or MEMS; the MCU
and MEMS can be integrated in a SiP for better performance.

Advanced Driver-Assistance System (ADAS)

Advanced Driver-Assistance System (ADAS) is a subset of the driver assistance

system for supporting the driver in their primary driving task. It can detect and
evaluate the environment of the vehicle by means of sensors, and then inform and
warn the driver, provide feedback on driver actions, increase comfort, and reduce the
workload by actively stabilizing or maneuvering the car [19].
ADAS can be characterized by all the following: (1) support the driver in the
primary driving task; (2) provide active support for lateral and/or longitudinal
control with or without warnings; (3) detect and evaluate the vehicle environment;
(4) use complex signal processing; (5) direct interaction between the driver and the
system. Adaptive Cruise Control (ACC), Lane Departure Warning System (LDWS),
Collision Avoidance System, Lane Change Assist, Automatic Parking System, and
Automatic Emergency Brake are all examples of ADAS [19].
In general, three types of chips are adopted in ADAS: (1) sensor chips including
video, radar, LiDAR, ultrasonic and infrared (IR), etc. ADASs require numerous
sensors to accurately determine situational assessment and action implementation.
For example, video sensors record the lane markings on the road. The record
information is transformed and sent to central media processor in real time. The
central media processor will evaluate if the vehicle drifts out of the lane and send out
warning message to display and operation command through CAN bus; (2) automo-
tive transceivers or data interface, such as radar transceiver, Dedicated Short Range
Communications (DSRC) transceiver, CAN/LIN transceivers, Ethernet, etc. These
chips are applied to form in-vehicle network for transferring detected information
from sensors to processors and sending control signals from processors to the
controllers. They can also be applied in communication between cars, infrastructure,
and vulnerable road users to increase driver safety. The built network must provide
dedicated secure safety channel operation to enable the secure communication of
safety message and other data in real time. In future, it will also be connected to
cloud service and help self-driving; and (3) microcontrollers and processors. Digital
Signal Controllers (DSCs), Digital Signal Processors (DSPs), and many application-
specific microcontrollers are responsible for processing, evaluating all the data sent
through network, and then generating control signal to support the driver. For
example, S32V vision processors from NXP are 32-bit MPUs offering an Image
Signal Processor (ISP) and power 3D Graphic Processor Unit (GPU) for ADAS.
410 Q. Yan et al.

SH7766 is similar image recognition SoC from Renesas with an SH-4A core, a
distortion compensation engine, and graphics and image recognition engines.
NXP semiconductors, Infineon Technologies, Renesas Electronics, and
STMicroelectronics are the main IC suppliers for automotive electronics; the prod-
ucts in future market would be more distributed after Intel, Qualcomm, and Nvidia
announced to engage in this field [20–22].

Rail Transit System

Rail Transit System includes variety of transportation systems: railway trains, high-
speed railways, and Maglev (magnetic levitation) trains, as well as trams (which runs
on tramway tracks along public urban streets), subways, light rail, intercity trains,
straddle monorail, new transit systems, etc. [23].
Urban rail transit system generally consists of rail route network, stations, running
vehicles, traction system, maintenance base, communication system, supply and
transformation system, station operation equipment, and the control and command
center that is responsible for the coordination of the whole transit system. The wide
application of all automation equipment in urban rail transit system has greatly
improved the operation efficiency of the transportation system. For example, the
automatic control equipment of the train can automatically command, track, dis-
patch, and drive the running train according to the actual situation. The automatic
management of power supply system in rail transit system can be used for remote
control and telemetry of the main transformer voltage station, the special substation
for electric traction power supply for tram, and the equipment system for voltage
reduction. Automatic environment monitoring system and fire alarm system can
automatically control the station environment and trigger alarm according to the
situation. The automatic ticket machine and ticket checking machine can replace
manual ticket selling and checking. Each automation system forms its own internal
network, which is coordinated and scheduled by the central control computer.
Insulated gate bipolar transistor (IGBT) modules are used as main electronic and
electric devices in high-speed railway, urban rail, and subway train systems [24–26].
The IGBT module in the auxiliary system can provide better DC/DC frequency
conversion voltage isolation and DC power supply, so it is widely used in traction
converters and various auxiliary converters as well as train air conditioning, venti-
lator, air compressor, battery charger, and lighting system.

Smart Grid

Smart Grid is an electrical network consisting of various intelligent instruments,

smart electrical equipment, and supplies of renewable energy and high-efficiency
energy. The first official definition comes from the Energy Independence and
Security Act, approved by the United States Congress in January 2007 (EISA-
2007) [27, 28].
20 Applications of IC Products in Automotive, Industrial, and Medical Equipment 411

Fig. 20.2 The schematic of smart grid

The schematic of components of smart grid is shown in Fig. 20.2.

In 2009, China State Grid Corporation proposed a project named “Strong Smart
Grid.” “Strong Smart Grid” is a modern grid with ultrahigh voltage (UHV) grid as
the backbone and supported by the communication platform. It covers all aspects of
power generation, transmission and transformation, distribution and dispatching,
and realizing the integration of “power flow, information flow and business flow.”
The project is planned and completed in three stages: 2009–2010, pilot stage,
planning and formulating standards of management and technology, development
of key technologies, and equipment modulation; 2011–2015, comprehensive con-
struction stage, speeding up the construction of ultrahigh voltage (UHV) power
grids, distribution networks of urban and rural; and 2016–2020, a unified “strong
smart grid” will be built in an all-round way [29].
The Smart Grid can quickly diagnose and determine solutions for a particular grid
outage or blackout. The related technologies include distributed intelligent agents
(control systems), analysis tools (software algorithms and high-speed computers),
and operation applications (Supervisory Control and Data Acquisition, SCADA),
substation automation, demand response, etc. Smart Grid has a huge demand for
power devices and high-voltage IC products. Various IC products such as PLC chips
can be used in controls, computers, power lines, and new technologies and equip-
ment [30, 31].

Application of New Energy Sources

New Energy Sources usually refer to renewable energy sources developed and
utilized by new technologies. Renewable energy refers to the energy collected
from renewable sources, such as solar, wind, tides, waves, and geothermal [32].
Renewable energy currently provides energy for four important areas: power
412 Q. Yan et al.

generation, air and water heating/cooling, transportation, and rural (off-grid) energy
services.
Solar power generation systems mainly include solar cell modules (arrays),
controllers, batteries, inverters, user-class loads, etc. [33]. According to the excita-
tion mode, the inverter can be divided into self-excited oscillation inverter and other-
excited inverter. The main function of the inverter is to invert the direct current
(DC) stored in the battery into an alternating current (AC). The inverter adopts a
Synchronized Pulse Width Modulation (SPWM) processor through a full-bridge
circuit. After modulation, filtering, and boosting, the alternating current that con-
forms the requirements of the state power market can be obtained for the end-users of
the system.
Wind power is a clean fuel source, sustainable and cost-effective; yet good wind
sites are often located in remote locations resulting in challenges of equipment
installation, facility management, and transmission of electricity. Tidal energy
uses the gravitational pull of the Earth and Moon to generate electricity; wave
energy uses the kinetic force of waves to produce electricity. Both wave and tidal
power can be extracted from the ocean to generate electricity, by spinning a turbine
similar as in hydroelectric dams or wind farms. Geothermal energy comes from deep
inside the earth, due to slow decay of radioactive particles inside the earth. By 2013,
more than 11,700 MW of large, utility-scale geothermal capacity was in operation
globally, with another 11,700 MW in planned capacity additions on the way [34].
Various semiconductor materials, sensors, and ICs are used in different new
energy systems such as photovoltaic (PV) system and large-scale grid-connected
power station systems. In solar power generation system, powerline communication
(PLC) chips can be used to acquire and transmit real-time, diagnostic data regarding
energy output of individual solar panels to the array controller and subsequently to a
solar farm control station, over the existing DC powerline [35].

Medical Imaging Equipment

More and more imaging technologies have been applied to the medical field with the
development of technology, helping doctors to better diagnose diseases, greatly
improving the intuitiveness and accuracy of diagnosis. Currently the primary imag-
ing technologies include Computed Tomography (CT), B-Scan UItrasonography,
and Magnetic Resonance Imaging (MRI).

1. Computed Tomography (CT): CT imaging, combination of computer-processing

technology and X-ray imaging, forms a tomographic image of a specific area of
the scanned object from different angles, so that the internal condition of the
object can be clearly seen without cutting it open destructively. CT is also known
as CAT (computed assisted tomography) scanning; the technology was invented
in 1972 by Allan Cormack of Tufts University and by Godfrey Hounsfield of EMI
Laboratories; and they were awarded the Nobel Prize in Physiology or Medicine
1979 [36].
20 Applications of IC Products in Automotive, Industrial, and Medical Equipment 413

Figure 20.3 shows the working principle of CT. A three-dimensional

(3D) image of the object interior being scanned can be generated through digital
image processing, which is derived from a series of two-dimensional (2D) X-ray
images generated by a rotating detector around a single axis. X-ray of CT is the
most common application for medical imaging, whose cross-sectional image can
be used for a variety of medical diagnoses.
Because there is a different obstruction of different body structures for X-Ray,
CT will produce a series of operational data to determine different body struc-
tures. Although imaging is presented in the form of a cross-section or axis,
namely, the configuration of the human body is presented in a vertical way,
with the current image-processing techniques, this exact series of data can be
used to reconstruct the cross-section and even display the body configuration in
3D. In addition to application in medical aspects, CT is also used in other fields,
such as nondestructive testing (NDT) of materials and archaeological
applications.
2. B-Scan Ultrasonography: B-type ultrasonic imager (B-ultrasound for short) is a
two-dimensional imaging system of high-frequency acoustic ranging from 1 to
18 MHz; its schematic diagram of working principle is shown below in Fig. 20.4.
The B-Scan technology was called Diasonography, invented in 1963 as the
world’s first obstetric ultrasound machine, for the examination of the unborn, by
Professor Ian Donald of the University of Glasgow, Scotland, UK. The first to
appear is actually A-Scan Ultrasound Bionmetry (also known as Amplitude
Scan), which is primarily used to measure the size of tumor. With the help of
B-ultrasound, detailed imaging of various organs can be clearly displayed on the

Fig. 20.3 Schematic diagram of CT working principle

Fig. 20.4 Schematic diagram of B-ultrasonography working principle

414 Q. Yan et al.

screen, to provide a visualized and reliable evidence for medical diagnosis; that is
why, currently the B-ultrasound technology has been widely used in examina-
tions such as obstetrics and gynecology examination, vascular disease examina-
tion, breast examination, thyroid examination, abdominal organs examination
(liver, kidney, and gallbladder), prostate examination, and so on [37]. There
comes one after another of new B-ultrasound technologies such as Color
B-ultrasound, three-dimensional B-ultrasound, and four-dimensional B-ultra-
sound with the development of imaging technologies, leading to much more
specific details in scanned images.
3. Magnetic Resonance Imaging (MRI) Scan: Raymond Damadian of State Uni-
versity of New York was first to perform a full body scan of a human being in
1977; Damadian invented the apparatus and method called nuclear magnetic
resonance (NMR) and now well known as magnetic resonance imaging [38].
The medical imaging technology with the application of radiology uses mag-
netic resonance image to obtain electromagnetic signals from the human body
and to reconstruct the information of it therefore to determine the physical
condition of the target.
It is proven that MRI is a highly universal imaging technology that can be used
not only for the medical field but also in the domains of strong magnetic fields,
radio waves, and so on. It is usually the hydrogen atoms that are used to generate
a detectable radio frequency (RF) signal which can be received by the antenna in
clinical research of MRI. The hydrogen atoms are known to be ranked among the
top of others in human body and other biological organisms, especially in water
molecules and fatty tissues. Out of this reason, the location of water and fat in the
human body can be clearly displayed by most MRI scans. On the basis of the
relaxation properties of hydrogen atoms, different tissues can be compared
through changing the parameters of the pulse sequence. The composition of the
MRI system is shown in Fig. 20.5.
The signal processing, control, and display applications through medical
imaging equipment have used a variety of IC products. In recent years, MRI
combined with analysis of Machine Learning results in demand of additional
ASIC design is a new trend.

Fig. 20.5 Composition of the MRI system

20 Applications of IC Products in Automotive, Industrial, and Medical Equipment 415

Medical Electronic Equipment

Traditional medical electronic equipment widely used in clinics may include X-ray
machine and generator, and electrocardiography (ECG).

1. X-ray generators: X-ray is a high-energy photon beam. Its wavelength is

extremely short, only 0.001–10 nm; its penetration ability is extremely strong.
When X-rays penetrate the human body, different tissues result in different
absorption rates for X-rays. Dense tissues, such as bones, absorb most of the
radiation, and the corresponding areas of the film are lighter in color. Soft tissues,
such as muscles, absorb less radiation, and these areas of the film are darker.
Therefore, the X-ray machine designed and produced based on the X-ray has
quickly become an important diagnostic tool in medical field, since its early time,
and is widely used in the diagnosis of diseases such as fractures and gastrointes-
tinal diseases [39].
German scientist Wilhelm Röntgen discovered X-ray on November 8, 1895;
thus, X-ray is often called Röntgen radiation. Today, in the field of X-ray
machine, digital radiography has the advantages of fast filming efficiency, low
radiation dose, high-quality imaging effect, etc., and the traditional film X-ray
machine was eliminated gradually. The digital X-ray machine system is mainly
divided into four parts: diagnostic bed, high-frequency inverter power supply,
console, and image-processing computer system.
2. Electrocardiography: Electrocardiography is the process of producing an electro-
cardiogram (ECG or EKG); electrocardiography instrument places electrodes on
the body surface and detects heart signals through these electrodes. These elec-
trodes detect small potential changes in the skin caused by the electrophysiolog-
ical pattern of depolarization and repolarization of the heart muscle during each
heartbeat. These electrodes are placed in the left leg, right wrist, left wrist, and
chest. At present, ECG have been widely used in the medical field and have an
irreplaceable position in cardiac testing projects.
ECG machines have a long history [40, 41]. In 1887, scientists recorded
electrical changes on the surface of the human skin caused by myocardial
beating during the beating of the human heart. This record is considered to be
the first electrocardiogram of human beings. In 1903, physiologist Willem
Einthoven invented the first electrocardiograph called the “string galvanometer”
at Leiden University. After a large number of clinical studies and animal
experiments, Einthoven proposed a relatively complete theoretical model,
linked the ECG signal to cardiac activity, and successfully interpreted the
ECG results. Einthoven won the Nobel Prize in Physiology or Medicine 1924.
The system structure of the ECG is shown in Fig. 20.6. ECG is a noninvasive,
painless test with quick results. The tests are often done in a doctor’s office, a
clinic, or a hospital room. They have become standard equipment in operating
rooms and ambulances [42].
416 Q. Yan et al.

Fig. 20.6 ECG machine system structure

Fig. 20.7 The typical system structure of the medical monitoring equipment

Medical Monitoring Equipment

Medical monitoring equipment can be an electronic device that can observe disease
condition or monitor some medical parameters in real time. Through continuous
monitoring of the patient’s vital signs, the medical staff can better make a correct
judgment of the patient’s physical condition and determine the appropriate
treatment plan.
According to the function, the medical monitoring equipment or devices can be
divided into bedside monitoring equipment (for directly connecting with the patient
in bed and monitoring patient’s condition in real time), discharge monitoring device
(which is relatively small, easy to carry around, and can collect the patient’s medical
information or data within a certain period of time), and central monitoring equip-
ment (which can simultaneously monitor multiple objects over a network) [43, 44].
The prototype of the medical monitoring equipment, formerly the oscilloscope in
the physics lab, appeared in the 1950s. After years of research and improvement, it
has been finally applied to clinical medicine. The typical system structure of the
medical monitoring equipment is shown in Fig. 20.7.
Preset sensors allow for the monitoring of a wide range of physiological param-
eters. After the biomedical signal is converted into an electrical signal by the
preprocessing module, it is processed and judged by the signal processing system,
including interference suppression, signal filtering, and amplification. The electrical
signal after the secondary processing can be visually displayed by the display device,
and then subjected to sampling, quantization, and various calculation and
20 Applications of IC Products in Automotive, Industrial, and Medical Equipment 417

consequent analysis, and the result is compared with the threshold set in the alarm
device. When there is a critical situation, the alarm device can automatically notify
the medical staff. In addition, the recording device can also archive the detected data,
so that the medical staff can understand the changes in the patient’s physical
condition. If some parameters need to be monitored, the built-in control system
enables real-time monitoring [45].
Based on various applications, there are home medical monitoring equipment,
hospital medical monitoring equipment, and patient medical monitoring equipment.

Medical Electronic Devices

There are many kinds of medical electronic devices. Three types are introduced here:
electronic sphygmomanometer, blood glucose meter, and pulse monitor.
Electronic sphygmomanometer is a medical device which is commonly used in
the household to measure blood pressure with modern electronic technology. The
electronic sphygmomanometer has some advantages such as simple operation and
self-tests at home. At present, wrist electronic sphygmomanometer is commonly
used as shown in Fig. 20.8. It is a fully automatic intelligent electronic device,
mainly including liquid crystal display screen, pneumatic pump and trachea, pres-
sure sensor, controller module, and so on. The controller module generally uses a
single chip as the control core, measures the air pressure through a pressure sensor,
determines the actual diastolic pressure and systolic pressure according to the
corresponding algorithm, and finally displays on the liquid crystal screen.
The electronic sphygmomanometer in the market today has realized network
management, which can transmit the measured data to the health management
platform through the network, and generate the corresponding physiological reports
for feedback to users; most of these sphygmomanometers are based on digital IC
technology [46]. The future development direction of electronic sphygmomanome-
ter is to improve the accuracy and portability, to facilitate more people to measure

Fig. 20.8 Wrist electronic

blood pressure monitor
418 Q. Yan et al.

blood pressure and prevent diseases anytime and anywhere, and more importantly, to
achieve continuous real-time blood pressure measurement without using a tradi-
tional balloon.
Blood glucose meter is an electronic device for measuring blood sugar,
especially for patients to detect blood sugar level and take correct measures to
prevent life-threatening issues. In 1970, Anton H. Clemens, of the Ames Reflec-
tance Meter (ARM) division of the Miles Laboratories in Indiana, developed the
first blood glucose meter and glucose self-monitoring system [47]. The blood
glucose meter has experienced five generations of development since it was
invented in 1968. Its basic principle has evolved from light reflection method
to electrochemical method which is widely used at present. Most modern blood
glucose meters are minimally invasive or noninvasive. They use a fixed bias to
stimulate the electrochemical reaction between the test paper and the blood to
obtain a current signal. Then the chip measures the current signal, and then
performs the operation and displays it as a digital output. Online data sharing,
dynamic blood glucose testing, and noninvasive blood glucose testing are the
main directions for the development of modern blood glucose meters. While
convenient to use, they will further improve measurement accuracy, stability, and
cost performance [48].
Pulse monitors can quickly detect diseases, especially cardiovascular diseases, by
real-time monitoring of pulse conditions, so as to achieve the goal of protecting
human health; there are variety of products to be chosen from in the market [49].
A pulse monitor is mainly composed of sensor, control unit, and display module. The
control unit mainly uses single chip to read sensor data, confirm and display
the number of pulses, and give prompts or warnings when abnormalities occur. At
present, pulse monitors are mostly integrated into other wearable devices, such as
sports bracelets. Besides pulse monitors, hand rings can also monitor ECG signals,
respiratory rate, and so on. In addition, pulse monitors are also the basis of other
physiological parameters measurements, such as blood oxygen measured by pulse
value to get blood glucose value, which illustrates the importance of pulse monitors.
In the future, pulse monitors need further development in expanding additional
functions.

Implanted Medical Electronic Devices

Typical implantable medical electronic devices [50] include cardiac pacemaker

(CPM) and implantable nerve stimulator (or neurostimulator).

1. Cardiac pacemaker: Cardiac pacemaker is an electronic therapeutic instrument

implanted in vivo to treat cardiac dysfunction caused by some arrhythmias. It is
powered by batteries inside the instrument. The pulse generator in the instrument
generates a pulse current of a certain frequency, which stimulates the myocardium
20 Applications of IC Products in Automotive, Industrial, and Medical Equipment 419

through electrodes, and restores the normal expansion and contraction of the
heart. In 1958, Arne Larsson (1915–2001) became the first to receive an implant-
able pacemaker, which completely or partially replaced the pacing function of the
heart itself. He had 26 devices during his life and campaigned for other patients
needing pacemakers [51]. With the development of technology, cardiac pace-
maker has been continuously optimized. It has experienced the fixed rate pace-
maker mode, on-demand pacemaker, atrial synchronous ventricular pacing,
atrioventricular sequence inhibition pacemaker, physiological pacemaker, and
other modes in the early 1960s.
Since the 1980s, with the application of pacing mode with physiological
pacing function, pacemakers with automatic control function have been devel-
oped rapidly. The emergence of digital pacemaker after the twenty-first cen-
tury has made great contributions to the collection of clinical samples of heart
disease and the research of treatment schemes. The basic components of
cardiac pacemaker are pulse generator, electrode, main control chip,
connecting wire, and battery. The function of pulse generator is to generate
electric pulses with fixed intensity and frequency. Now it is commonly
implemented in monolithic ICs. The role of electrodes is to transmit electrical
pulses to myocardium, to stimulate myocardial cells to achieve the purpose of
cardiac pacing, and then to sense the electrical signals of the heart and transmit
them to the control part of the pacemaker in order to adjust the parameters to
adapt to the physiological state. A similar implantable cardioverter-
defibrillator (ICD) is a small battery-powered device placed in patient’s
chest to monitor the heart rhythm and detect irregular heartbeats. An ICD
can deliver electric shocks via one or more wires connected to patient’s heart
to fix an abnormal heart rhythm [52].
2. Neurostimulator: The implantable nerve stimulator [53] or neurostimulator is an
electronic medical device installed on the body surface or in the body, for
example, Cochlear Implant, and the Food and Drug Administration of the United
States has authorized some implantable nerve stimulators to be used in clinical
treatment, mainly Spinal Cord Stimulation (SCS) for pain relief; Deep brain
stimulation (DBS) is mainly used in the treatment of Parkinson’s disease, tremor,
and dystonia; Vagus Nerve Stimulation (VNS) [53] is used to treat epilepsy and
depression; Sacral nerve stimulation (SNS) for the treatment of urinary
incontinence, etc.
In addition, the practice has proved that the implantable nerve stimulator can
treat more than 20 kinds of nerve or mental diseases, and the effect is well known.
The basic components of a neurostimulator are Implantable Pulse Generator
(IPG) and electrodes that are mounted on one or two lead(s). IPG generates
electrical pulses according to the parameters set by doctors, and the electrodes
are responsible for transmitting the electrical pulses to the target nerve [54]. If the
IPG and electrodes are far apart from the patient’s subcutaneous area, an extended
wire is needed for signal transfer.
420 Q. Yan et al.

Medical Robot

Medical robots are specialized robots used in the medical sciences to assist with
certain medical behaviors. Medical robots can be used in several medical and health
fields, such as assisting surgery, locating microinjury locations in the body, and
diagnosing and healing. It combines electronics, mechanics, and computer and
medical disciplines and is the result of multidisciplinary cross-integration, which
can greatly improve the efficiency of medical treatment.
At present, there are many types of medical robots [55], with various components
of doctor’s console, robotic arm system, imaging system, sensing system, commu-
nication system, data processing, and analysis system. These systems are mainly
composed of a core processor and image-processing chips, and the sensing system
includes MEMS medical sensors.
In 1990s, the California Radiation Medical Center developed the first surgical
robot PUMA 560 (Programmable Universal Machine for Assembly, or Programma-
ble Universal Manipulation Arm), which can assist doctors in neurosurgical biopsy
[56]. The emergence of the PUMA 560 opened a door for robots participating in the
medical field. After PUMA 560, medical robots with different functions and capa-
bilities have been developed according to different services and work contents. For
example, in minimally invasive surgery, the surgeon can perform minimally invasive
procedures by manipulating the surgical robot to improve efficiency and success rate
of the procedure. In the postoperative rehabilitation process or the daily life of
thedisabled groups, the rehabilitation robot can greatly reduce the work load of the
nursing staffs. Service robots mainly include drug delivery automation robots,
wheelchair robots, rescue robots, transfer robots, disinfection robots, nurse robots,
etc., which are mainly used to replace people with simple repetitiveness and
laborious work.
After nearly 30 years of development, medical robots have been continuously
improved and developed, and a relatively mature and complete medical robot system
has emerged. Among them, the typical representative is the da Vinci surgical robot
system developed by Intuitive Surgical of the United States, which is mainly
composed of a surgeon console, a robot arm, and an imaging system [57]. With
the rapid development of deep learning research in the era of artificial intelligence
(AI), medical robots for disease diagnosis will become the main area of future
research.

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Applications of IC Products in Aero-Mil
21
Gang Liu, Qiquan Zhang, Fang-Lin Yan, Yuewen He, and
Chuan Deng

Contents
Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Aircraft Flight Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Applications of ICs in Satellites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Military Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Electronic Warfare IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Missile Guidance and Control Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Infrared Night Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Avionics Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Airborne Early Warning Aircraft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Environmental Cognitive Sensors in Smart Robots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Robot Network Communication System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Intelligent Manufacturing Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Unmanned Aerial Vehicle System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Binocular Vision System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Virtual Reality/Augmented Reality/Mixed Reality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
AI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

G. Liu (*)
China Electronics Technology Group Corporation 14th Institute, Nanjing, China
e-mail: liugang@china-dsp.com
Q. Zhang
Harbin Institute of Technology, Shenzhen, China
F.-L. Yan
Shenzhen Yixingbiao Technology Co., Shenzhen, China
Y. He
Shenzhen Institute of Micro-nano IC and System Application, Shenzhen, China
C. Deng
National IC Design Shenzhen Industrial Centre, Shenzhen, China

© Publishing House of Electronics Industry 2024 423

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_21
424 G. Liu et al.

Abstract
The applications of aeronautics, astronautics, military equipment, and the
emerging areas strongly require reliable ICs, including power devices. For
example, the GaN/GaAs-based RF circuit modules play an irreplaceable role
in high-frequency applications, such as radar and electronic warfare ICs; a
variety of compound semiconductor-based circuits are the important payload
of the aircraft and spacecraft; the CMOS-based detectors expand the human
sight into the infrared spectral range; and the emerging applications of artifi-
cial intelligence are putting forward the demand of computing platform with
higher energy efficiency ratio, etc. This chapter introduces applications of ICs
in various critical environment and presents the important roles of power
devices in these fields.

Keywords
High power · High frequency · Compound semiconductor device · Emerging
applications

Radar

Radar (radio detection and ranging) is an electromagnetic system that transmits

electromagnetic signals, receives echoes from targets within its power coverage,
and extracts position and other information from the echoes for target detection,
target location, and target recognition [1]. The radar appeared in the mid to late
1930s. At that time, aircraft and ships were the main combat weapons of the warring
parties. Detecting the orientation of enemy aircraft and ships and guiding their own
aircraft for interception was an urgent task to perform. As the main means of
detection, radars emerged and played an important role in World War II (WWII).
After WWII, radar systems are still developed rapidly. In the military field, naviga-
tion, weapon guidance, battlefield reconnaissance, antimissile early warning radar
systems have emerged; in the civilian field, there are radar systems for port traffic
control, air traffic control, weather, and earth observation imaging. Today’s main-
stream radars can operate from a few megahertz (MHz) to millimeter waves (mmW)
and terahertz (THz). Phased array radar has become the mainstream system of
modern radar [2].
The general development trend of advanced radar in the future is: (1) multi-
functional integration: combined function of detection, communication, electronic
countermeasures, etc.; (2) intelligent processing: radar information processing in
relation to environment, target, and jamming; (3) functions defined by software:
open architecture, reconfigurable software for different radar systems; and
(4) system-on-chip (SoP): power amplifier, RF transceiver, and digital processing
system on chip. The distribution of typical digital phased-array radar [2] and its use
of IC are shown in Fig. 21.1.
21 Applications of IC Products in Aero-Mil 425

Fig. 21.1 Typical IC components and distribution in a digital phased-array radar

The ICs used in the radar system can be divided into four clusters, namely: power
devices cluster, radio frequency (RF) chips cluster, digital chips cluster, and an
optoelectronic chips cluster.

1) Power devices clusters: Microwave solid-state power devices have evolved from
the first-generation silicon bipolar transistors (BJT) to the second-generation
silicon MOS devices, the third-generation “wide bandgap” semiconductor mate-
rials for GaN, SiC power devices, and graphite semiconductor in the future [2].
Currently, solid-state high-power devices [3] are developing in the direction of
wide bandwidth, high power, high efficiency, high linearity, light weight, small
size, integration, and intelligence.
2) RF chips cluster: Radio frequency IC (RF IC) is mainly used in the transmit
channel and receive channel of the radar receiving system. It includes a low-noise
amplifier (LNA), mixer, gain controller, and other RF devices [3]. With the
development of digital technology, ADC, DAC, DDS, DDC, FPGA, and other
IC chips are widely used in digital receivers. The trend of RFIC is broadband,
digitalization, and high integration. RF system-on-chip (RF SoC), which inte-
grates RF front-end with digital baseband, will be widely used in phased array
radar for its high integration, low power consumption, and low cost.
426 G. Liu et al.

3) Digital chips cluster: Various kinds of chips, e.g., processors, FPGA, dedicated
ASIC, MCU, network switching, Flash, DDR, DC/DC, etc., are widely used in
radar array processing, signal processing, data processing, display, and control
subsystems. With the transition of radar array processing from high speed real-
time and synthetic processing to general cluster processing platform, the hetero-
geneous multicore and reconfigurable computing will be the mainstream of the
next generation processors. The development trend of protocol switching chips
and interface chips is toward wider switching bandwidth, lower switching delay,
and wider data transmission bandwidth.
4) Photoelectric chips cluster: In the current radar system, the transmit channel
controls data and timing signals, the data from thousands of receive channels,
and the digital processing platforms use optical fibers for data transmission and
exchange. Small-signal RF/microwave photonic link technology is being devel-
oped. The development trend is the full signal link from RF microwave signals to
digital signals. The digital radar based on all-photon technology will potentially
transcend traditional radar.

Aircraft Flight Control

Aircraft flight control (AFC) system is mainly used to stabilize and control the
centroid motion (lift, forward, left, and right) and angular motion (pitch, yaw, and
roll) of an aircraft. Aircraft generally refers to airplanes, but also includes airships,
balloons, helicopters and rotorcrafts, etc.
The AFC system and the aircraft constitute a closed loop, and the control and
stabilization of the aircraft are based on the feedback control principle. In the loop,
the controlled variables are the height of the flight, as well as its speed, lateral
deviation, and attitude angle; the controlling variables are the displacement of the
throttle rod and the deflection angle of the pneumatic control surface [4]. A typical
AFC system is shown in Fig. 21.2.

Fig. 21.2 A typical AFC system

21 Applications of IC Products in Aero-Mil 427

The AFC system was developed through two stages: manual control and auto-
matic control. (1) In the manual control stage, the pilot controls the throttle rod and
control surface through the mechanical system of the aircraft to control the attitude
and flight of the aircraft. In the automatic control stage, the aircraft is equipped with a
flight control system which manipulates the throttle rod and control surface, thus
controlling the aircraft flight automatically. In this process, the pilot is only required
to carry out necessary monitoring and does not control the aircraft directly. (2) Auto-
matic flight control system, also called advanced flight control system (AFCS), is the
core of the AFC system [5, 6]. The four stages of development represent the
development of the AFC system. In the first stage, AFC device developed from an
automatic stabilizer to autopilot; in the second stage, an autopilot developed into an
automatic control system; in the third stage, an adaptive flight automatic control
system appeared; and in the fourth stage, an integrated aviation system was devel-
oped. AFCS was formerly found only on high-performance aircraft. Currently, due
to advances in digital technology for aircraft, modern aircraft of any size may
have AFCS.
ICs and related components used in AFC system mainly include power supply
components, inertial guidance components, internal memory, I/O interfaces, clock
circuits, and interrupt controllers. With the rapid development of ICs, the structure of
the AFC system is becoming increasingly complex, and its functions are becoming
more and more comprehensive and powerful. The future development trend is to
integrate parameter control such as speed, track, and attitude with various functions
such as course keeping, automatic navigation, and terrain following/avoiding. These
new functions should involve more complex IC designs.

Applications of ICs in Satellites

The satellite is a celestial body that orbits a planet orbit and follows the closed orbit.
The rapid development of science and technology has led to the emergence of
artificial satellites. With the feature of high spatial location and wide coverage,
artificial satellites can achieve a variety of military and civil applications such as
communication, navigation, reconnaissance, broadcasting, observation, detection,
and space test [7]. After several decades of rapid development, the satellite platform
and payload are moving toward the trend of design generalization, function integra-
tion, object specialization, and processing intelligence. These trends require a high
integration of functions in satellite systems. With the increasing integration of ICs
and the use of new RF and power components, the quality of artificial satellites is
getting higher and higher, and the volume is becoming smaller and smaller. It is
possible to develop small satellites, microsatellites, nano-satellites, and even pico-
satellites. The common ICs for the satellite platform and payload are shown in
Fig. 21.3.
High-performance digital ICs include large-scale FPGAs, ASICs, CPUs, DSPs,
SRAMs, and PROMs, which are used for signal processing, process control, logic
operation, program, and data storage. Analog and RF circuits include amplifiers,
428 G. Liu et al.

Fig. 21.3 Common ICs used in the satellite platform and payload

filters, power management circuits, ADCs, DACs, phase-locked circuits, and

modem circuits. Analog ICs are widely used, and they are mainly used for RF signal
processing, analog-to-digital conversion, and control management. Hybrid ICs
mainly include hybrid integrated DC/DC converters, decoding drivers, voltage
drivers, voltage stabilizers, and bus transceivers. With the advancement of com-
pound semiconductor (GaAs, InP, and GaN) design and process technology, micro-
wave monolithic ICs (MMICs) have begun to be widely used in artificial satellite
loads. For example, the use of various types of chips, such as GaAs monolithic
amplifiers, monolithic mixers, monolithic phase shifters, and GaN power amplifiers,
has greatly improved the reliability and integration of satellite loads. ICs for satellite
applications should have aerospace reliability specifications for the corresponding
orbit and life requirements [8], such as total ionizing dose (TID), single event latch-
up (SEL), and memory single event upset (SEU).

Military Communications

Military communication is a kind of information transmission activity that the army

utilizes comprehensively various means of communication to achieve a certain
military purpose. It is also a basic means to ensure the command of the army. The
basic requirements of military communication differing from civil communication
are rapidity, confidentiality, reliability, and continuity.
There are many kinds of classification methods for military communication.
According to the different transmission media, it can be divided into wired and
wireless communication, among which wireless communication can be further
divided into microwave, scattering, laser, satellite and mobile communications,
etc. According to the types of services carried, it can be divided into voice, telegraph,
data and multimedia communication, etc. According to the requirements of
21 Applications of IC Products in Aero-Mil 429

communication support and the scope of contact, it can be divided into strategic,
campaign, and tactical communications, etc. According to the different types of
communication tasks, they can be divided into command, coordination, and logistics
support communications [9, 10].
Military communication system [11] refers to the communication and liaison
system established by using various military communication technologies to accom-
plish military tasks. Since the invention of telegraph in 1852 and telephone in 1876,
communication technology has become an indispensable carrier of communication
and command in the military field, bringing about significant changes in military
communications and supporting the development of military science and technol-
ogy. Since the World War II, especially after the 1960s, with the rapid development
of various wireless technologies, especially digital programmable switching tech-
nology and computer technology, wireless communication modes (e.g., microwave
communication, scattering communication), satellite communication and optical
fiber communication have been combined with wired communication modes (e.g.,
data communication network and computer network). A multilevel distributed
military communication network with core network, access network, and user
equipment as the main body has gradually formed. Since the end of the twentieth
century, driven by the continuous demand for space and ocean communications, the
multidimensional space-earth integrated communication system with a multi-
domain, multi-network system, multimode, and multiservice has been gradually
formed from space to underwater. The communication confidentiality, cognitive
performance, and anti-interference ability have been continuously enhanced.
The improvement of modularization, intellectualization, and miniaturization of
military communication equipment cannot be separated from the promotion of IC
applications. Especially since the 1980s, the progress and industrialization of micro-
electronics and semiconductor technology have greatly promoted the updating of
solid-state devices and large-scale ICs, which affect directly the form and presenta-
tion of military communication technology and military infrastructure.
The typical schematic block diagram of military communication system and
equipment is shown in Fig. 21.4. Military communication system has experienced
from the earliest use of discrete devices to build functional modules, to the large-
scale hierarchical use of ICs. It can be said that the development of microelectronics
technology and the performance of IC products determine the capability of military
communication system in terms of communication capacity, rate, coverage, and
safety and reliability. The main ICs used in military communication system include
central processing unit (CPU), digital signal processor (DSP), field programmable
gate array (FPGA), mass memory, high-speed interface circuit (HSIC), high-speed
and high-precision converter, etc.
At present, the realization of communication processing function based on
programmable system-on-chip (PSoC), also known as system-on-programmable
chip (SoPC), has become the mainstream. Storage, conversion, and interface circuits
are integrated together on the SoPC to form the single-chip baseband with pro-
cessing capability. Radio frequency discrete devices and connecting components are
highly integrated to realize integrated radio frequency chip so that the signal
430 G. Liu et al.

Fig. 21.4 Typical principle block diagram of military communication system and equipment

frequency conversion capability is formed. With the development of the third-

generation semiconductor technology, high-power density power devices and
power monolithic circuits have been realized, resulting in better signal transmission
capability.

Electronic Warfare IC

Electronic warfare (EW) is a collective term for the applications of using electro-
magnetic energy to determine, detect, weaken, or suppress the enemy military’s use
of the electromagnetic spectrum and protect its own applications.
In the early twentieth century, EW technology has been developed more than a
century since radio interference activity from British navy in the Mediterranean. In
the World War I [12], only the simple direction-finding techniques were used. In the
Vietnam War, new technologies of infrared (IR) and laser were used. In Gulf War and
Kosovo War, EW entered the era of systemic confrontation. In the twenty-first
century, EW is the main means of modern warfare and its importance has become
more prominent. With the development of EW to electromagnetic spectrum warfare,
networked collaboration, intelligent sensing, and precision attack will become the
new features of future EW [13, 14].
Since the appearance of EW, electronic devices have been an integral part of
EW equipment. In the early stages, from vacuum electronics to semiconductor
discrete devices, from advanced RF, microwave, millimeter (mm) wave, and
photonic devices to VLSI (very large-scale integration) ICs, these applications
have largely supported the equipment of EW. In fact, modern microelectronic IC
has become an important cornerstone of modern electronic information systems,
while EW equipment is more dependent on a variety of advanced ICs and devices.
Taking radar confrontation as an example, ultra-wideband (UWB), high-dynamic/
high-power RF systems, and broadband phased array systems require extensive
use of various advanced microwave and mmWave broadband IC, such as gallium
21 Applications of IC Products in Aero-Mil 431

arsenide (GaAs) with broadband performance, low-noise amplifiers, gallium

nitride (GaN) power amplifiers, and monolithic ICs (MMICs) such as switches
and phase shifters. UWB ICs that instantaneously cover RF, microwave, and
mmWave, such as UWB low-noise amplifiers (LNA), wideband frequency syn-
thesizers, UWB mixers, etc., are the essential components for UWB reconnais-
sance receiving systems. For example, UWB receivers developed by WJ
Corporation of the United States use many UWB microwave ICs, and their
operating frequencies cover all frequency bands from RF to mmWaves. Advanced
digital IC is another key component indispensable for wideband digital multi-beam
reconnaissance and jamming system, and it is the basic guarantee for the accurate
reconnaissance and interference function of EW equipment, including ADC, DAC,
FPGA, and ICs such as DSP, high-speed data memories, and high-speed interfaces.
Similarly, digital radio frequency memory (DRFM) implemented by the above IC
is recognized as a “radar buster” because of its ability to quickly store and
accurately replicate threat signals. In addition, new microwave photonic IC devices
with broadband advantages can greatly expand the spectrum adaptation range of
EW equipment and to create a new capability for EW.
With the development of nano-electronics, heterogeneous and three-dimensional
(3D) integration, integrated with antenna, RF, acquisition, signal processing, power
management, and control, it can achieve system-on-chip (SoC) integrated micro-
systems with multiple functions. It will become a new demand for the development
of EW, and it will also promote the rapid development of EW equipment towards
intelligence, networking, and miniaturization.

Missile Guidance and Control Systems

Missile guidance and control system is a system that applies various methods to
guide a missile to its predetermined target. It is composed of missile guidance and
missile attitude control systems. Missile guidance system includes a measuring
device and a calculating device. It measures the relative position or speed of a
missile and its target, calculates according to the predetermined guidance law, and
generates guidance signals to guide the missile to reach its target. Missile attitude
control system includes a sensing device, a calculating device, and an actuator. Its
main function is to ensure the stable flight of the missile accept the guidance signals
transmitted by the guidance system, control the flight attitude angle of the missile,
adjust its movement direction, and ensure the missile hits the target accurately
[15, 16]. The classification of missile guidance and control systems is shown in
Fig. 21.5.
The concept of the missile guidance and control system can be traced back to the
World War I (WWI), when airborne bombs were guided remotely to their targets. By
the end of WWII, the V-series missiles developed by Germany used a simple
guidance system for the first time. The V-1 missile was guided by autonomous
magnetic gyro and used mechanical controls. The V-2 missile was mainly controlled
by radio. The radio control, which is vulnerable to interference and requires
432 G. Liu et al.

Fig. 21.5 Classification of missile guidance systems and control systems

complicated equipment, is not suitable for modern warfare. Since 1950s, with the
continuous improvement of the accuracy of inertial instruments, as well as the rapid
development of error separation and compensation techniques and computer tech-
nology, the inertial guidance system becomes more popular and has been used by
ballistic missiles worldwide to improve their accuracy. During this period, other
guidance methods, such as infrared (IR) and laser guidance, have also developed. In
1970s and 1980s, the compound guidance method was used more widely, and the
missile hit accuracy was improved greatly. For example, the Trident II ballistic
missile developed by the United States used inertial and celestial guidance, and
achieved a hit accuracy deviation of 400 m, which was improved by an order of
magnitude than in 1950s and 1960s. Since the Gulf War in early 1990s, the precision
guidance system and responsive control system have been used widely, so the
missiles can now achieve extremely high hit accuracy and the combat effectiveness
has been improved.
ICs and related components used in missile guidance and control system
mainly include a CPU (central processing unit), DSPs (digital signal processors),
RF microwave devices, memory chips, IMUs (IR measurement units), FPGAs
(field programmable gate arrays), analog/digital converters, and digital/analog
converters. In 1962, Texas Instruments developed 22 sets of ICs for the US
Minuteman-I and Minuteman-II missiles, which was the first application of ICs
in missile guidance and control systems. At that time, only small-scale ICs were
used, namely simple diodes, transistor logic circuits, NOR/NAND circuits, trig-
ger circuits, etc. With the improvements of the missile guidance and control
performance requirements and the rapid development of ICs, and information
processing technology, medium-scale integrated (MSI) and large-scale integrated
(LSI) circuits are being used more widely. The guidance and control system of the
US MX missile used complementary metal-oxide semiconductor (CMOS) MSI
and LSI ICs. At present, as the third-generation semiconductor materials (e.g.,
GaN) are used more widely in ICs, the performance of missile guidance and
control systems will be further improved.
21 Applications of IC Products in Aero-Mil 433

Infrared Night Vision

Infrared (IR) night vision is based on photoelectric conversion or thermoelectric

conversion effect. It receives IR radiation from natural objects through a specific IR
detector, converts the IR radiation of the object into a weak electrical signal, and
performs signal processing through specific amplification and enhancement, and
finally the imaging display process to form image on display [17, 18]. Therefore, IR
night vision can also be called IR thermal imaging or IR night vision imaging.
Based on the wavelength distribution, the IR ray is in a wavelength region other
than the red wavelength, the wavelength of the IR ray is 0.76 μm to 1 mm, its short-
wave end is close to the visible light, the long-wave end is nearby to the millimeter
(mm) wave of the radio wave, and both of visible light and radio wave are the part of
electromagnetic spectrum [18].
According to the working mechanisms, IR detectors can be divided into heat
detectors and IR photon detectors. Heat detector is based on thermoelectric effect.
Under the action of the external bias signal of the detector, the processing circuit
converts the temperature of the detector or other physical behaviors caused by the
temperature to achieve the conversion between radiation signal of the object and
electrical signal, and to detect the IR radiation from objects. The heat detector has a
wide spectral response range for IR radiation, and it performs no significant wave-
length selectivity. IR photon detector is based on the absorption of the IR radiation of
the relevant band by the IR sensitive material, and the bound electrons in the material
are excited into conduction electrons, and processed by the subsequent circuit of the
detector, then form electrical signal, and finally the output. In order to successfully
reach the photoelectric conversion of IR radiation of the IR photon detector, the IR
radiation photon must meet certain energy requirements, so the IR photon detector
has wavelength selectivity to the IR radiation.
In order to realize high signal-to-noise ratio and high-resolution imaging require-
ments for IR night vision, it is necessary to finely process the weak electrical signals
generated by the IR radiation absorbed by the IR detector (such as analog domain or
digital domain preprocessing, amplification, etc.). Through the multiplex processing,
a signal output with specific format that is easily received and processed by the back
end processing circuit is created. Therefore, IR detector needs to be equipped with a
special IR low-temperature, low-noise amplifier (LNA) circuit to achieve high
signal-to-noise ratio amplification and driving of weak electrical signals generated
by IR sensitive elements.
As the pixel unit size of the IR detector array is further expanded, the sensitivity is
further improved, and the function is further increased, it is required to perform
signal processing such as high-gain and low-noise amplification on the weak
electrical signal generated by the IR radiation of the object received by the IR
detector array. Therefore, an application-specific IC with unique properties such as
low noise, low power consumption, and low temperature operation are required. The
circuit processes the weak electrical signal output by the IR detector array, mainly
including pixel level processing (input, integration, etc.), row and column amplifi-
cation and conversion (amplification, multiplexing, etc.), and detector array signal
434 G. Liu et al.

buffer output, etc., thereby forming analog signal output, or perform as a digital
signal output after analog/digital conversion. Such specific IC is called an IR focal-
plane readout IC [19].
The IR focal-plane readout circuit is a special IC that is typically designed and
fabricated by using standard complementary metal-oxide semiconductor (CMOS)
technology [20]. The block diagram of the infrared focal-plane readout circuit is
shown in Fig. 21.6. The interconnection of the IR focal-plane readout circuit and the
IR array chip is shown in Fig. 21.7. Generally, the IR focal-plane readout circuits use
the indium (In) column flip-chip interconnection method to realize the connection
with IR sensor photo-sensor array and the input of the weak signal, completing the
detection and signal output of the IR radiation signal, and finally achieve high-
performance IR night vision imaging by external signal and image processing.

Fig. 21.6 The block diagram of the infrared focal-plane readout circuit

Fig. 21.7 The block diagram

of the interconnection of the
IR focal-plane readout circuit
and the IR array chip
21 Applications of IC Products in Aero-Mil 435

The IR focal-plane readout circuit based on CMOS IC and process technology

integrates nonuniformity correction, scene-based parameter adaptive matching, and
digital enhancement processing on the chip, which will greatly enhance the IR night
vision imaging technology and performance of the equipment with high sensitivity,
high integration, high working frame rate, and full digitalization.

Avionics Instruments

Avionics instrument is the general term of all instruments on the aircraft which
provide relevant information for the pilot. The pilot controls the aircraft based on the
information from the avionics instruments. Avionics instruments [21] in turn dem-
onstrate the results of the pilot’s control. The classification of avionics instruments
are shown in Fig. 21.8.
The development of avionics instruments can be divided into four stages:
mechanical instruments, electrical instruments, electromechanical instruments, and
digital display instruments. (1) Mechanical instruments have single direct-reading
structures with each component, are mechanical, and can only measure a single
parameter. After 1930s, avionics instrument gradually developed into electrical
instrument. Different from mechanical instrument, the sensor and the indicator are
installed apart and connected through signal transmission. (2) Electrical instruments
use electrical transmission instead of mechanical drive as obvious advantages of
improved reaction speed, transmission distance, and accuracy, and reduced volume.
(3) Electromechanical instruments appeared after 1940s. The feedback principle is
used to ensure consistent input/output for improving sensitivity and accuracy.
(4) Aviation instrument has gradually developed into electronic display instrument
due to the rapid development of electronic information technology. Its basic

Fig. 21.8 Classification of

avionics instruments
436 G. Liu et al.

structural unit is a low-power servo system for signal conversion, calculation, and
transmission. At the same time, as the types and quantity of aviation equipment
increase, most aviation instruments are now integrated with display instruments.
ICs and devices used in aviation instrument mainly include microprocessor chips,
ADC, DAC, and various sensors concerning pressure, temperature, and inertia. Due
to the increasing demand for miniaturization, microelectromechanical system
(MEMS)-related technologies are being used more widely in the sensors applied in
aviation instrument [22].
The future development trend of aviation instruments is intelligence, network,
and openness. With the development of computer technology, the architecture of
distributed control system (DCS) [23] has been continuously improving. Digital and
open DCS will gradually be applied to aviation instruments. The traditional DC
analog signal transmission will be replaced by two-way digital communication in the
bus, and then intelligent transmitter and intelligent actuator will be applied. The
range and accuracy of aviation instruments will be greatly improved as well as
further improved reliability and usability. DCS is like supervisory control and data
acquisition (SCADA), but DCS tends to be used on large continuous process system
where high reliability and security are required.

Airborne Early Warning Aircraft

Airborne early warning (AEW) aircraft is a special mission aircraft equipped with
AEW radar [24, 25]. Its initial operational function was to compensate for the
low-altitude detection blind areas of ground or shipborne radar through its airborne
radar. As military demands increase and electronic technology and aviation technol-
ogy improve, modern AEW aircraft has been equipped with advanced airborne long-
range AEW radar to complete its mission of battlefield early warning and detection
tracking. It is also equipped with various electronic systems for communication
navigation, command and control, friend or foe identification, electronic reconnais-
sance, and electronic warfare, etc. It can not only detect and track various types of
invading air and sea targets at an early date but also guide and control allied war
crafts and other weapons. Modern early warning aircraft can be classified as land-
based fixed-wing AEW aircraft, ship-based fixed-wing early warning aircraft, ship-
based rotor-wing AEW aircraft, etc.
AEW aircraft first appeared by the end of World War II. After more than 70 years’
development, it has now developed to the third generation and is entitled “the Air
Commander,” which obviously shows its core status and importance in the combat
system. At present, the representative third-generation AEW aircraft in the world
mainly include the United States’ E-2D, Russia’s A-100, Israel’s G550
“Gulfstream,” and China’s KJ-2000 [25]. These AEW aircraft have the technical
characteristics of “networked, diversified, integrated and lightened,” and can unify
and manage comprehensively the resources based on the battlefield situation. They
can multiply the system combat effectiveness and have become the core strength of
modern information combat system.
21 Applications of IC Products in Aero-Mil 437

Mission electronic system is the foundation of AEW aircraft’s functions, and ICs
and related devices are the important parts of mission electronic system. For
example, CPU chip, digital signal processing chip, digital/analog conversion circuit,
radar raster scan display, memory, solid-state microwave power device, microwave
low-noise receiving circuit, microwave oscillator, and some special ICs form the
basis of electronic system’s functions. The solid-state microwave power device is
helpful to bring radar detection, communication navigation, electronic detection,
confrontation, and other electronic systems into all-solid state. Subsystems consisted
of microwave devices such as transmitter, receiver, antenna system, and display can
be used in radar, electronic warfare system, and communication system. In addition,
low-phase-noise microwave oscillator is one of the most important factors that affect
the radar range of electronic system.
As operational environments and operational needs change sharply, airborne
early warning aircraft’s position in the whole combat system and its technology
form will change drastically as well. System operational environment, which is
based on the information system, requires early warning aircraft to develop from
single platform combat to systematic confrontation. This puts forward new and
higher requirements to the electronics in AEW aircraft. At present, major IC tech-
nologies represented by nano-electronics, the third-generation semiconductors, and
integrated micro-systems enable electronic devices to develop towards miniaturiza-
tion and integration. With these new technologies and products, the AEW aircraft
can be further developed for reduced volume, weight, and energy consumption, as
well as more integration in functions.

Environmental Cognitive Sensors in Smart Robots

In practical application scenarios, smart robots need to recognize the surrounding

environment. Smart robots should not only be able to avoid obstacles through
environmental cognition but also can extract, understand, express, and reason
relevant environmental knowledge. Environmental cognition enables a smart robot
to have the ability to correct its own position and deduce relevant environmental
knowledge. The simultaneous localization and mapping system (SLAM), first pro-
posed by Smith, Self, and Cheeseman in 1986 [26–28], has been regarded by many
scholars as the key to truly realizing fully autonomous mobile robots. SLAM usually
refers to the acquisition, calculation, and fusion of various sensor data to generate
position, attitude position, and scene map information. SLAM is widely used in
service robots, unmanned aerial vehicles, and other fields, supporting the mobility
and interaction ability of robots and other systems. There are many kinds of robot
environmental cognitive sensors, among which lidar, vision sensor, and ultrasonic
sensor are widely used.
The laser radar can directly provide the distance information between the robot
body and the surrounding obstacles with fast measurement speed, high precision,
and small calculation. The laser radar ranging mainly has the pulse and phase types
of ranging. Pulse ranging can determine the distance between the laser radar ranging
438 G. Liu et al.

system and the target object by directly measuring the time of the laser pulse
transmitting back and forth from the laser radar ranging system to the target object.
Such sensors are expensive. By measuring the phase change of the continuously
modulated light wave when it propagates back and forth between the laser radar
ranging system and the target object, the time is indirectly measured. Therefore, it
can calculate the distance between the laser radar ranging system and the target
object. Such sensors are less expensive.
In the intelligent machine cognition system, the vision sensor provides the most
outside information to robots. With the rapid enhancement of CPU and GPU
capabilities and the improved performance of visual sensors, the high-precision
real-time visual perception technology has been advanced significantly. The research
on vision sensor mainly includes monocular camera, binocular or multi-eye camera,
and depth camera (RGB-D). In addition, there are special vision sensing methods
such as fisheye, panoramic, and so on. In general, to reduce the computational load
of visual image matching, the information measured by other inertial units can be
combined for fusion processing. Monocular camera is low cost, but its biggest
drawback is that it cannot accurately provide the depth information of the target
object. Binocular cameras can estimate depth information, thus eliminating the
disadvantages of monocular cameras. The configuration and calibration of binocular
or multi-lens cameras is complex, and the depth range is also limited by the camera’s
baseline length and image resolution. As a result, the calculation of depth calculation
is complicated, and the overall cost of the system is high. RGB-D camera is a
composite camera that uses structural light source to perform environmental irradi-
ation and uses consistent structural light geometric information to realize distance
resolution after imaging by plane array sensor. Its outstanding feature is that it can
directly give depth information, so it can provide more direct information than
monocular cameras and binocular cameras. However, most RGB-D cameras still
have some disadvantages, such as large distance measurement noise, limited field of
vision, and less measurement range [29].
Ultrasonic sensors are widely used in obstacle avoidance of mobile robots.
Ultrasonic sensors have many advantages. They can not only transmit in many
materials but also are less affected by the environment and have good directivity.
Therefore, mobile robots with ultrasonic sensors are widely used in many fields,
such as industry, biomedicine, and national defense.

Robot Network Communication System

With the development of science and technology, the application field of robotics is
expanding constantly. At the same time, higher requirements are put forward for the
reliability and stability of robotic data communication. Considering the multi-node,
distributed network, long distance communication, harsh environment, real-time
performance, and high reliability required by industrial communication, CAN,
EtherCAT, PROFINET, and ROBBUS have gradually become the main means of
robotic communication networks.
21 Applications of IC Products in Aero-Mil 439

The controller area network (CAN) is one of the most widely used industrial
fieldbuses [30]. Due to the high reliability and stability, it has been widely used in
industrial automation, ship, medical instrument, multi-sensor measurement and
control, and other fields. CAN controller is used to generate CAN communication
protocol frame and convert data frame into binary bit stream, which is transmitted to
CAN transceiver and sent out. In general, CAN controller integrates logic controller,
FIFO, and CAN protocol core controller.
Ethernet for control automation technology (EtherCAT) is an open architecture
fieldbus system based on existing Ethernet. EtherCAT industrial Ethernet has flex-
ible topological structure and low development cost, and its added real-time channel
makes data transmission more efficient and high speed. The implementation of
EtherCAT master station is relatively simple, requiring only a network interface
card or a network card integrated with the computer motherboard. EtherCAT master
stations are generally supported by real-time operating systems (RTOS) running on
platforms such as ARM/x86/ZYNQ. EtherCAT takes the communication mecha-
nism of “centralized frame” for reference in data frame processing. It extracts the
data related to the machine from the address of the station according to the field bus
memory management units (FMMU) and at the same time uploads the feedback data
to the address. EtherCAT extends the protocol support for CAN and serial commu-
nication servo system on the application layer protocol toward zero cost communi-
cation across the bus [31].
PROFINET (a portmanteau for Process Field Net) is an automatic bus standard
based on industrial Ethernet technology, which is widely used in motion control,
distributed automation, fault safety, network security, and other automation fields
[32]. According to application scenarios, PROFINET can be divided into PRO-
FINET component-based automation (PROFINET CBA) and PROFINET IO
(related to number of I/O points). PROFINET CBA is suitable for software-based
communication scenarios based on TCP/IP protocol, while PROFINET IO is suit-
able for application systems requiring real-time communication support, and the two
can coexist in a network at the same time. In order to meet the requirements of high
real-time applications in the robot field, PROFINET provides users with a real-time
data transmission channel. Under the real-time channel, PROFINET real-time
communication (RT) response time fell to 5–10 ms, and PROFINET isochronous
real-time (IRT) technology, under the condition of 100 nodes, lowered the typical
response time to 1 ms, able to meet the response requirements of high-speed motion
control systems [33].
The robotic communication bus (ROBBUS) is a standard proposed by China
machinery industry federation in June 2010 and organized by China institute of
automation. ROBBUS adopts several ISO11898-1:2003, ISO11898-4:2004, and
ISO11898-5:2007 standards associated with CAN [34]. The standard bus is designed
for low-cost, modular robots, is a masterless bus, with good real-time, expandability,
and strong anti-interference ability. It is suitable for the communication between
modules in the modular robot system and has multichannel property. The standard
specifies the data format and program specification of the communication bus in the
modular robot system, including protocol level, format definition, and workflow.
440 G. Liu et al.

Intelligent Manufacturing Systems

Intelligent manufacturing system (IMS) refers to an intelligent system that can

conduct a series of intelligent activities like human beings, such as inferring prob-
lems, analyzing problems, and making decisions in the manufacturing process [35].
IMS is designed to perform manufacturing processes with various components of
intelligent, flexibility, and the use of technical means (e.g., artificial intelligence
(AI) to learn and mimic human thinking activity), so that they can replace part of the
human’s mental work further for automatically adjust parameters in manufacturing
to achieve optimized conditions.
In 1980s, the United States put forward the concept of intelligent manufacturing,
which was highly concerned and valued by various countries and regions. All
countries and regions in the world have included intelligent manufacturing into the
future development plans of their countries or regions, successively launched spe-
cific R&D programs, increased investment in scientific research, and promoted
further implementation of intelligent manufacturing. Some important concerns in
IMS have been reviewed in a recent article [36].
With the rapid penetration of information technology (IT) into manufacturing,
modern industrial informatization has entered the stage of intelligent manufacturing.
Enterprises worldwide in various fields continue to speed up integrated innovation,
promote the continuous reform of production management and business model, and
form a series of new models, new forms of business, and new characteristics in the
field of intelligent manufacturing [37]. Industry 4.0 is a project proposed in 2011 by
the German government, aiming to improve the intelligence level of the manufactur-
ing industry, integrate the resources of customers and business partners in the
business and value process, and build a smart factory with adaptability and resource
efficiency. Industry 4.0 is based on the Internet and the Internet of Things (IoT)
system, from centralized control to distributed enhanced control mode, to establish a
highly flexible personalized and digital production mode of products and services.
The Industry 4.0 term also refers to the fourth industrial revolution, from intelligent
factory, intelligent production, intelligent logistics, new materials and smart tech-
nologies, logistics, etc. The Fourth Industrial Revolution are technologies and
systems such as artificial intelligence, machine learning, 3D printing, the Internet
of Things, virtual and augmented reality, big data, and mobile networks [38].

Unmanned Aerial Vehicle System

The unmanned aerial vehicle (UAV) is a kind of powered, unmanned aircraft, which
can fly autonomously or remotely, and can be used once or repeatedly. It is also
called “aerial robot” [39]. The UAV can fly in unmanned conditions by using radio
remote control equipment and self-equipped process control devices. At the same
time, it can complete complex flight missions and load tasks.
Frame components, flight control system and sensor equipment, data communi-
cation system, power supply system, launch and recovery system are indispensable
21 Applications of IC Products in Aero-Mil 441

Fig. 21.9 Unmanned aerial vehicle system framework and IC diagram for use

parts of the UAV system. The architecture of the UAV system and the IC used are
shown in Fig. 21.9.
The UAV flight controller mainly includes the UAV attitude measurement, sta-
bility control, airborne mission management, and fault-tolerant calculation modules.
The flight control system hardware includes GPS module, inertial measurement unit,
barometer and ultrasonic measurement module, embedded CPU, motor drive regu-
lator, communication equipment, etc. Currently, famous open source projects of
flight system include Paparazzi UAV project, Dronecode/PX4 project,
OpenDroneMap project, and Drone Journalism Lab.
The UAV data communication device is mainly responsible for performing the
remote control of the UAV and information transmission function of the airborne
sensor device data, including the digital radio station, picture transmission radio,
remote control and receiver, ground station system, etc. A typical communication
scenario for a drone is shown in Fig. 21.10 [40].
The UAV power drive device includes motors and electronic speed control (ESC).
ESC controls the speed and power of the motor or engine of UAV. At present, the
ESC of UAV in the market also has auxiliary functions such as starting protection,
battery protection, auxiliary braking, etc.
Sensor equipment carried by UAV is the necessary hardware equipment for UAV
to realize automatic detection, control, and stable flight. These sensors mainly
include vision sensor, IR sensor, ultrasonic sensor, millimeter wave (mmW) radar,
barometer, GPS/GLONASS, other positioning sensors, IMU and compass dual
redundancy sensors [41], etc. They can help UAV acquire real-time image, depth,
location, and other information during flight, construct 3D map around the aircraft,
and determine its own location.
The UAV battery management system is one of the core issues to optimize the
duration of UAV. It is mainly composed of instruction control chip, MOS tube,
battery management chip, and other devices, and combined with the
corresponding embedded software. At present, the main power management
442 G. Liu et al.

Fig. 21.10 A typical communication scenario for UAV

devices in the market include discrete power management chip (PMIC) and
integrated power management unit (PMU). For example, TI’s BQ30Z55 series
chips are commonly used in power management system of the UAV intelligent
lithium battery [42]; in addition, some well-known devices include power con-
troller IC (e.g., MC3377x system from NXP) and power monitor (e.g., ADM66xx
series from ADI) are also in adoption.

Binocular Vision System

Binocular vision system uses two cameras with different positions to shoot images
from different perspectives, calculates the matching relationship of the pixels one by
one through matching algorithm, and then obtains the depth information of the
object image according to the offset between the matching points, and then con-
structs the three-dimensional (3D) information of the image. Compared with some
existing 3D information acquisition methods, binocular vision technology requires
simple equipment, only ordinary cameras, and does not need to actively emit light,
which is conducive to reducing overall power consumption.
Binocular vision system technology includes binocular matching, visual posi-
tioning, depth map fusion, high-level applications, and other different levels
according to the implementation process [43]. Depth image acquisition based on
binocular matching is the basis of binocular vision system. In the scene with fixed
camera position, the depth map obtained by binocular matching can be directly used
for attitude recognition and other tasks and has important applications in the field of
human-computer interaction. In mobile platform scenarios, the location of the
camera is another basic task. Based on binocular vision technology, the motion
trajectory of the camera can be restored by time correlation of depth map sequence,
21 Applications of IC Products in Aero-Mil 443

and then used in autonomous navigation, 3D fusion, and other high-level applica-
tions. It has important applications for mobile robot platform [43].
At present, in the actual use of binocular vision technology system, the most
important problem is real-time capture and accuracy. Firstly, extracting 3D informa-
tion from binocular images is a complex algorithm problem, which is vulnerable to
nonideal factors, e.g., noise and occlusion in real scenes. In addition, the binocular
vision correlation algorithm has a high computational complexity, and the traditional
general-purpose processor cannot meet the requirements of real-time processing.
To solve the above problems, most of the research work only optimizes the
accuracy of the results from the algorithm level, which is based on general purpose
processors and cannot achieve real-time processing. To solve the real-time problem,
parallel computing is another hot research direction in this field.
The common parallel computing devices are FPGA (field programmable gate
array) and GPU (graphics processing unit). Among them, due to the high flexibility
of computing and storage structure, the FPGA can better meet the needs of parallel
image processing for high parallelism and high internal bandwidth [44], so it has
been widely used. The real-time processing of high-resolution images can consider
GPU parallel computing, which can effectively improve the speed of multitask
operation. Some progress has been made in these areas [45]. At present, products
in the market support 3D depth of field calculation, binocular image matching, and
visual positioning and related processing algorithms.

Virtual Reality/Augmented Reality/Mixed Reality

Today, these terms, VR (virtual reality), AR (augmented reality), MR (mixed

reality), and CR (cinematic reality), are no stranger to people. The VR visions that
are computer-generated are actually false; the AR is to enhance the reality; the real
world and the virtual world mixed together to produce a new visual environment in
real-time is MR; while CR is a pre-step producing a cinematic effect for MR.

1) Virtual reality (VR): Virtual reality (VR) refers to the use of a computer, which
generates a virtual environment. VR enable users to “invest” into the environ-
ment through a variety of dedicated devices and directly interact with that
specified environment. VR technology allows users to use human’s natural skills
to perform in the virtual world, while providing visual, hearing, touch, and other
intuitive and real-time natural perception. The current mainstream VR products
are HTC VIVE and Oculus Rift Headsets, which generate realistic 3D images
from software through high-performance computers and graphics processing unit
(GPU), and the illusory scenarios are finally displayed in VR glasses [46]. The
block diagram of HTC VIVE headsets display is shown in Fig. 21.11. Virtual
reality can be widely used in the games, education, entertainment, training,
travelling, designing and simulation training, etc.
2) Augmented reality (AR): Unlike the full immersive effect of virtual reality, AR is
dedicated to creating a world of virtual and real. It superimposes
444 G. Liu et al.

Fig. 21.11 The block diagram of HTC VIVE headsets

computer-generated objects onto real scenarios, providing users with a hybrid

scene of virtual information and real scenes through optical perspective helmet
displays, glasses, projectors and mobile phone screens, etc. Google has released
Google Project Glass AR glasses, while observing the surrounding environment,
the glasses can take the photos by sound control, obtaining environmental
information such as weather, location, etc., as well as access to the Internet and
emails checking. AR has a wide range of applications, such as assistance infor-
mation, traffic navigation, CAD interfaces supporting and training or learning
understanding enhancement. Several good AR glasses are listed for 2019 [47].
3) Mixed reality (MR): Mixed reality (MR) is designed to integrate the virtual world
with the real world. The wearable helmet display and other devices provide the
basic tools for immersive observation of mixed reality scenes, and the computer
provides virtual and real fusion scene that is compatible with user’s observation.
The generation of virtual and real fusion scenes is essentially the mutual embed-
ding of different spatiotemporal scenes, referring to geometric consistency and
illumination consistency. MR provides a natural interface for users to interact
with virtual world. By understanding human actions and behaviors, MR builds
the bridge between users and virtual worlds of reality, objectively providing
intuitive connection between virtual world and real world. In a world of virtual
and reality, human’s intelligence can understand the truth by observing the mixed
scenes of virtual and real, driving the virtual world on demand by natural
interactions, and obtaining scene or data feedback from computer. Finally, MR
achieves the immersive deep interaction between human and computer, and then
results to deep integration of machine intelligence and human intelligence. MR
involves both VR and AR technologies; some known companies in the world
may include Facebook, Microsoft, Google, Samsung, Sony, Nintendo, Huawei,
and others.
21 Applications of IC Products in Aero-Mil 445

AI System

Artificial intelligence (AI) is a discipline that studies, develops, and simulates

theories, methods, techniques, and applications of human intelligence. Research on
AI systems includes robotics, speech recognition, image recognition, natural lan-
guage processing, expert systems, etc. At present, ICs are widely used in AI systems.
For example, the MultiSense S7 sensor is used in the head of the Boston Atlas robot
for front view. In addition, in the field of deep learning, graphics processing units
(GPUs) use their unique parallel computing architecture to significantly reduce
model training time under big data samples, greatly saving development resources.
As a special processing chip tailored by TensorFlow, the 2016 deep learning
framework for deep learning, the tensor processing unit (TPU) has played an
important role in artificial intelligence projects. Companies such as IBM and
Samsung have also developed dedicated chips for AI. It can be said that the
development of AI and the development of ICs are the same, driven and promoted.
The overall schematic diagram of the AI computing system is shown in Fig. 21.12.
The graphics processor, also known as the display core, is a microprocessor that
performs image computing operations on personal computers, workstations, game
consoles, and some mobile devices. In 2006, NVIDIA and ATI (merged with AMD
in 2006) introduced the Compute Unified Device Architecture (CUDA) program-
ming environment and Close-To-Metal (CTM, originally called “Close-to-the-
Metal”) programming environment, respectively. As a new computing architecture,
CUDA enables GPU to quickly solve complex computing problems [48, 49].
TPU is a processor designed by Google for machine learning (ML). As the core
discipline of contemporary artificial intelligence, ML has spread throughout our
agenda. The high-performance source of TPU is its nonuniversal design logic
(quarterly single design principle), which uses dedicated logic circuits, single
work, and fast speed. With the same transistor capacity, the TPU can run more
operations per unit of time, resulting in smarter results by using more complex and
powerful machine learning algorithms. In real life, many applications in Google use
TPU and have achieved very good results, such as Google Street View and AlphaGo,
etc. In early 2019, Google announced TPU-based TensorFlow V2, which can run on
multiple CPUs and GPUs with CUDA, and on Google Cloud Platform [50].
In 2011, IBM first proposed the Artificial Brain Project, which aims to develop a
complete AI system to simulate human behavior. The system innovatively devel-
oped the advanced chip TureNorth that mimics the human brain neural network. In

Fig. 21.12 Overall schematic diagram of AI system

446 G. Liu et al.

this project, the IBM neuron is the basic processing unit, the size and stamp size are
equivalent, the power consumption is only 65 mW, but it integrates one million
spiking “neuron” circuits [51].
The biological signal processor is a dedicated processor equipped with a
bio-signal sensor that can receive and process human biological signals. These
new processors are still in their infancy and are only used in medical fields and
mobile wearable devices [52]. Bio-Processor, a bio-signal processor released by
Samsung at the 2016 CES conference, uses the latest bio-signal fusion technology.
The technology is based on enhanced data conversion resolution and wide-area
dynamic range to capture biological signals that are faint and easily disturbed.

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 Section III
Integrated Circuit Industrial Economy and
Investment
Zixue Ζhou, Yue Liu, Fangfang Li, Ying Cai, and Ke Feng

Introduction

As the IC industry has become an essential part of trades around the world, it has also
developed into an essential indicator for researchers to identify economic trends and
implications in this field. To reach this purpose, they need to understand not only the
market characteristics and capital composition but also the roles played by firms,
consumers, and the governments in the economy as demand increases.
This section presents the characteristics of IC market by analyzing the trends in
supply and demand based on macroeconomic theories, as well as the empirical
conclusion in the market. It also provides a set of tools for measuring firm perfor-
mance and explains their meanings to the economy.
There are four chapters in this section: Chap. ▶ 22 illustrates the development of
the IC market from the perspective of economics; Chap. ▶ 23 explains the capital
composition and market characteristics of IC industry, Chap. ▶ 24 collects essential
terms and concepts of corporate performance and demonstrates their implications on
investor’s decision, and finally, Chap. ▶ 25 introduces main investment methods
used in China’s IC industry.
Finally, we would like to express our sincere gratitude to the authors from diverse
backgrounds who have generously devoted their rich experience and unique per-
spectives to this section. We also feel grateful to the inspiring opinions from the
committee and the reviewers’ rigorous work.
Economic and Financial Theories Related
to IC Industry 22
Zixue Zhou, Fangfang Li, Yaoliang Qi, and Bojing Zheng

Contents
IC Industry and Macroeconomy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Effect of Scale Economies in the IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Economic View of Moore’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Scope Economy and Industrial Cluster in IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Blue Ocean and Red Ocean of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Globalization and Open Market for IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Global Value Chain and Smiling Curve of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Life Cycle of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Longtail Effect and Customized Products in IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Equity Valuation Model of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Principal-Agent System in IC Enterprise Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Capital Structure of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Abstract
Integrated circuits are the cornerstone of electronic information. There is a highly
positive correlation between IC industrial development and the macroeconomic
situation. IC is a global industry, which not only shows the cooperation of the
global value chain, but also reflects the competition among regions for the leading
power of industrial development. Both industrial clusters and scale effects have
displayed the role strong leaders may sustain. The winner-take-all phenomena
persist, while the blue ocean market and longtail effect have given start-ups a
chance for survival and development. In order to promote healthy competition
Z. Zhou
China Federation of Electronics and Information Industry, Beijing, China
F. Li
Publishing House of Electronics Industry Co., Ltd., Beijing, China
Y. Qi · B. Zheng (*)
Hua Capital Investment Management Co., Ltd., Beijing, China
e-mail: Bojing.Zheng@hua-capital.com

© Publishing House of Electronics Industry 2024 451

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_22
452 Z. Zhou et al.

among enterprises in different regions and scales, this chapter also discusses the
appropriate strategies of integrated circuit enterprises in financial and corporate
governance.

Keywords
Global value chain · Corporate governance · Industrial competition · Moore’s law

IC Industry and Macroeconomy

Digital integrated circuit (IC) industry is important for national strength, and there-
fore crucial in the political, economic, and military competition among nations. With
the rapid development of global informatization and knowledge economy, IC indus-
try has become closely related to the areas of national security, economy, society,
etc., and thus could contribute a lot to macroeconomy [1]. It is also noticeable that
the development of IC industry will also be affected by macroeconomy.
The IC was invented in 1958 and was first applied in the military field: Texas
Instruments provided computational IC solutions for the US Air Force and National
Aeronautics and Space Administration (NASA). Texas Instruments also developed
the world’s first IC-based computer for the US Air Force in 1961. Subsequently,
NASA and the US Air Force improved their intelligence by applying IC technology
to specific products.
The fast-growing IC started to gain attention from industry field in the 1970s and
has been widely used in the market for electronics and PCs since 1980s. From 1990,
the demand for communication chip brought by mobile phones has exploded, such
as systems evolved from global system for mobile communications (GSM), code
division multiple access (CDMA), and long-term evolution (LTE). All systems
mentioned above hold explicit demands for radio frequency (RF) chips, base band
processor chips, memory units, and power amplifier devices. Smart phones resulted
in more demands for IC products: sensors, logic circuits, and nonvolatile memory
are required in addition to the basic communication modules. IC is the fundamental
constituent of the Internet, the most effective factor of the economic structure in the
twenty-first century. The positive impact of IC on macroeconomy is as important as
that of other innovative technologies, but it has not been so critical until the IC
entered the private market. The rapid expansion of the IC industry has driven the
continuous growth of the global economy, which can be viewed from the correlation
between the fluctuation of IC industry and that of global macroeconomy (see
Fig. 22.1).
Though the proportion of the semiconductor industry in the macroeconomy is
gradually increasing, the absolute value remains small. The semiconductor industry
is the core of the information industry. In spite of fluctuations, the proportion kept
increasing from 0.194% in 1987 to more than 0.517% in 2020, as shown in Fig. 22.2.
The ratio of the global GDP in 2020 to that in 1987 was 5.01, while the ratio between
the sales volumes of semiconductor products in the same years was 13.35, which
22 Economic and Financial Theories Related to IC Industry 453

Fig. 22.1 Correlation between global semiconductor sales growth rate and global economic
growth rate in 1992–2021. (Note: the proportion of IC sales amount is the largest in total
semiconductor sales amount, which remains stable at about 80%. Source: World Semiconductor
Trade Statistics (WSTS) and World Bank)

was more than double the global GDP. The sales volume of the semiconductor
industry possesses the potential for rapid growth in the future. Overall, semiconduc-
tor industry will become an increasingly important role in macroeconomy.
Let’s look at the impact of macroeconomy on the IC industry. Fluctuations of IC
industry are more closely related to GDP fluctuations. The reason is that IC products
are not only alternative for each other, but also suitable for almost all fields [1]. IC
plays the role of multiplier in every practical field, promoting other industries and
enhancing national strength. The development of computers, household appliances,
new-coming intelligent devices, and wearable devices all depend largely on the
advancement and application of IC chips [2]. The demand for electronic products is
very flexible: consumers’ purchasing scale of smart phones, PCs, automobiles, and
many other mechanisms and services can make a huge influence on the global
electronic industry. When the economy boosts, so does the disposable income of
consumers, and they tend to consume electronic products and consequently drive the
growth of the semiconductor market and vice versa. The global GDP growth rate is
close to semiconductor market growth rate, as shown in Fig. 22.3. The correlation
454 Z. Zhou et al.

Fig. 22.2 Proportion of global semiconductor sales in the global economy in 1987–2020 (dotted
line is linear trend line). (Source: Statista)

Fig. 22.3 Correlation between global GDP growth rate and semiconductor industry growth rate.
(Source: IC Insights McClean Report 2017)

coefficient between global GDP growth rate and semiconductor market growth rate
has increased from 0.35 in 1980–1989 to 0.93 in 2010–2015 (the closer this value,
the higher the correlation is).
There was a typical historical example illustrating the relationship between the IC
industry and macroeconomy. From 1985–1990, the US share in the global semicon-
ductor market declined from 51.4% to 37.9%, while that of Japanese companies rose
from 39–50% [3], which made explicit influences on the annual growth rate of per
capita IC output value, per capita electronics industry, and per capita GNP. Japan’s
22 Economic and Financial Theories Related to IC Industry 455

performance in every field mentioned ended up with much better results than those
of the USA. However, in the late 1980s, the USA adopted a series of policies to
promote the development in the field of IC theory and practice, and finally regained
its leading position. So far, the US economy has maintained a high-speed growth, the
main reason is the innovation of information technology and the rapid development
of the industry, and the information industry is based on the integrated circuit
industry.
In the future, the rapid expansion of the emerging branching markets such as the
Internet of Things, artificial intelligence, and cloud computing will require large
quantities of IC chips with ultrastrong computing power, ultralarge storage capacity,
ultrafast transmission speed, and ultralow energy consumption. Thus, the IC industry
will continue to play the critical role in macroeconomy.

Effect of Scale Economies in the IC Industry

Effect of scale economies refers to that the larger the production scale, the lower the
average production cost. This effect also exists in the IC industry. In general, the
economy of scale in a certain industry is inversely proportional to the scale of
demand. The more unified the demands are, the more obvious the effect of scale
economies will be. On the contrary, the less unified the demands are, the less obvious
the scale economies will be. The economies of scale effect show different scales in
each industry sector of IC industry: this effect is larger in heavy-asset segments with
unified demand (e.g., IC manufacturing industry), while smaller in light-asset sectors
with longtail effect (e.g., IC design industry).
The heavy-asset sectors in IC industry require more and more investment in
equipment and research and development (R&D), which will eventually lead to the
concentration of production capacity. Enterprises must continuously improve their
production capacity to reduce the marginal cost of products so as to ensure that the
revenue can cover equipment expenses. The IC manufacturing industry is the most
obvious example. As the wafer size gets bigger and the manufacture process
becomes more advanced, the cost of equipment increases exponentially. Hence,
IC manufacturing corporations must continue to upgrade manufacture process
while expanding production capacity to form the scale advantage in the market
competition. The effect of scale economies is closely related to process standard-
ization and the broader application of products. In industrial sectors asking for
highly standardized processes and the products with broad application, enterprises
can improve their competitiveness by expanding production and reducing fixed
costs. In other words, the effect of scale economies is significant in the expansion
of market share.
The R&D expenditure of the world’s top 10 IC manufacturing enterprises in 2020
and 2021 is shown in Table 22.1. Among the top 10 IC manufacturing companies,
Intel, Samsung, and TSMC, for example, their R&D expenditure in 2021 reached
14.9 billion, 6.5 billion, and 4.4 billion US dollars, respectively. In 2021, the total
R&D expenditure of global IC manufacturing enterprises reached 81.5 billion US
456 Z. Zhou et al.

Table 22.1 The Expenditure of the world’s top 10 IC manufacturing enterprises in 2020 and 2021
Expenditures of top 10 semiconductor R&D
2021 R&D Rate of change 2020 R&D Rate of change
2020 Rank Company Exp ($M) (%) Exp ($M) (%)
1 Intel 14,941 10% 13,556 1.45%
2 Qualcomm 7176 20% 5977 10.73%
3 Samsung 6500 18% 5500 22.22%
4 Broadcom 4854
2% 4968 5.79%
5 Nvidia 5200 33% 3780 33.62%
6 TSMC 4410 19% 3720 25.72%
7 SK Hynix 3672 18% 3100 25.35%
8 MediaTek 3350 25% 2684 30.04%
9 Micron 2663 2% 2600 6.47%
10 AMD 2784 40% 1983 28.18%
Source: Chip Insights

dollars. Among them, the total R&D spending of the top 10 semiconductor compa-
nies in 2021 was 55.5 billion US dollars, up 15.7% from 2020. Intel’s R&D spending
accounted for 26.83% of the combined R&D spending of top 10 semiconductor
companies.
In 2021, 17 semiconductor companies spent more than 1 billion US dollars in
R&D, reaching a total of 67.5 billion US dollars, an increase of 16.3% over 2020.
The technical and monetary threshold of IC manufacturing technology will be higher
and higher, which makes the expenditure of IC industry gradually concentrated in
several technology-dominating monopoly enterprises. These monopoly enterprises
are willing to carry out a large amount of capital expenditure because they can gain
an advantage in market competition through high expenditure. In the highly capi-
talized IC industry with significant economies of scale, one must either catch up with
the market or go bankrupt.
The effect of scale economies of IC industry is clearly reflected on the concen-
tration of market. In the field of equipment, the top two companies occupy 40%
market, and the top 10 companies occupy about 70% market totally. Other compa-
nies can only compete for the remaining 30%, and the gross profit margin of the
companies is positively related to their market share. In the etching market, Lam
Research accounts for 47%; in the deposition market, Applied Materials accounts for
47%; and ASML accounts for 74% in the lithography market: the whole market is
almost monopolized by a leading enterprise [4].
The concentration of IC industry determines the number of enterprises, especially
in the field of IC manufacturing and memory. If blindly expanding, new enterprises
will not survive due to long-term losses. Therefore, governors can promote mergers
and acquisitions among enterprises in these fields to form one or two giant enter-
prises with compatibility in the international market. In areas where economies of
scale are relatively weak, governors can promote new ideas to help small and
medium-sized enterprises and provide solutions to diverse market demands.
22 Economic and Financial Theories Related to IC Industry 457

Economic View of Moore’s Law

Moore’s law, proposed by Intel cofounder Gordon Moore, is not a “law” of science
such as mathematics, physics, etc.: it is the prediction of the trend of the integrated
circuit industry. Based on the history of the integrated circuit industry, especially the
development history of Intel, Moore’ law can be summarized as the following: the
number of transistors on an integrated circuit chip that one can buy would double with
the same price every 18 to 24 months, as does the performance of an IC. It means that
the performance of IC at price of one dollar would double every 18 to 24 months [5].
Moore’s law demonstrates the speed of the development of technology. The
storage capacity of the DRAM – the main type of the memory devices – has
grown from the original 1kbit to 16Gbit (DDR4) and even 64Gbit (DDR5). Mean-
while, the microprocessor has been upgraded from the Intel 4004 to these processes
with multiple threads and multiple cores.
Moore’s law works when IC technology is still immature. The learning effect is
great, and the economic law of increasing marginal benefit stays at the dominant
place when IC technology still needs to be improved. When the IC technology
becomes mature, the traction effect of the technology will gradually disappear, and
the learning effect will decrease. Hence, the law of diminishing marginal utility will
come into play, and, accordingly, the Moore’s law will lose its effectiveness. Finally,
the IC industry will become a traditional industry like agriculture, which means that
the law of diminishing marginal utility of the traditional economics will work on IC
industry. As Brian Arthur said, “So we can usefully think of two economic regimes
or worlds: a mass-production world yielding products that essentially are congealed
resources with a little knowledge and operating according to Marshall’ s principles of
diminishing returns, and a knowledge-based world yielding products that are essen-
tially congealed knowledge with small amounts of resources and operating under
increasing returns.”
The information industry, developed according to the Moore’s law, is the main
engine of the modern economy. Moore’s law precisely describes the development of
technology economy of IC industry which is the core product of the electronic
information industry.
It is hard to say when Moore’s law would eventually reach its limit. Nevertheless,
it leaves us with the thought about the high-tech industry has guiding significance for
us to put forward the concept of market competition combining the technology
monopoly and the economic compatibility. From the perspective of the market,
Moore’s law demonstrates the regularity of the market competition in IC industry.
The competition mainly involves technology and human resources. The aim of these
competitions is to show the leadership in R&D of technology, the introduction of
preliminary customers, and the control of knowledge resources. The regularity of the
market competition includes both technological competition and economic compe-
tition. Of which, the technological regularity is that the industry can maximize the
amount of IC components on one chip with ultrafine line width through the innova-
tive utilization of the complicated technologies in IC industry such as layout design,
458 Z. Zhou et al.

materials, equipment, technique, detection, testing, etc. Thus, it can meet the
requirements of lighter, thinner, smaller, and mobile characteristics of the electronic
products, which is to optimize the performance and functions. The economic
regularity can be further classified into the investment regularity and the distribution
regularity, among which the former one means that in order to meet the prerequisites
for the traction effect of technological law, the investment scale is required to have
the features of high (investment amount), rapid (investment), continuous (invest-
ment), and large (increasing investment volume). In this way, achieving the techno-
logical leadership can be guaranteed. Similarly, the latter one indicates that in order
to meet the prerequisites of the traction effect of the law of technology and adapt to
the new mode of production, the IC industry needs to gather as many of the best
elites as possible, so as to maximize their revitalizing ability to the utmost extent.
The leading position of technology is manifested as a technology monopoly in the
market. To remain on the position of monopoly as long as possible, an enterprise or a
country must continuously increase investment and hence attract more and more
talents, resulting in strong economic compatibility. In turn, the superior economic
compatibility will support the monopolistic dominance and thus generate more profit
from the technological monopolies. The profit can be ploughed into the next
intensive round of competition, which would finally become a positive spiral
circulation [6].
The value of a technology may eventually run out. However, the economic
thoughts will never dry up. Moore’s law demonstrates the truth of the sustainable
innovation in an industry and society as a whole. The quintessence of Moore’s law is
the idea of market competition, which integrates the technological monopoly and the
economic competition. It is manifested by the entrepreneurship, innovation activi-
ties, and the pace of innovation. As long as the sustainable innovation remains, the
rule of increasing return will remain, which means Moore’ law will be not
going away.

Scope Economy and Industrial Cluster in IC Industry

Scope economy refers to the positive effects that different companies can achieve to
each other within a certain geographical range. The scope economy is more obvious
in high-tech industries that have a quantitative demand for infrastructure, which
makes the industry create a strong industrial agglomeration effect to a certain
location, and eventually forms corresponding industrial clusters. Industrial cluster
refers to a group of related enterprises and institutions in a specific field, concen-
trated in a certain geographical area, forming a flexible organic complex with the
complete structure of the industrial chain and comprehensive peripheral supporting
industrial system [7].
The development of the IC industry has shown the characteristics of scope
economy, forming various world famous IC industry clusters. By scope economy,
22 Economic and Financial Theories Related to IC Industry 459

enterprises in the cluster can enjoy basic resources within a certain geographical
range, including industrial supply chains, scientific research institutions, transporta-
tion infrastructure, and information platforms. Under such circumstances, the cluster
can attract more qualitative production factors. For example, Taiwan has formed
three major IC industrial clusters in the Hsinchu Science Park, the Central Science
Park, and the Southern Science Park. The IC wafer manufacturing industry is mainly
concentrated in the Hsinchu Science and Technology Park, where various supporting
subindustries of the wafer manufacturing industry are also concentrated. The chip
design industry is concentrated in the education center near Taipei because of its
technological orientation.
China’s mainland has formed three major IC industrial clusters in Beijing and
Tianjin area (around the Bohai Sea), the Yangtze River Delta, and the Pearl River
Delta. The industrial cluster distribution of integrated circuits in China is highly
consistent with the location of the economic center, and basically consistent with
the higher education center. In other words, the location choice of China’s IC
industry cluster is highly market oriented and capital oriented, which is closely
related to the reserves of scientific and technological talents. This phenomenon
also appears in countries with advanced IC industries, such as the USA, South
Korea, and Japan.
At present, due to the characteristics of integrated circuit industry itself, the
location of IC industry is more dispersed in different regions, but the main body
remains concentrated. This does not conflict with the characteristics of the scope
economy and industrial clusters. On the contrary, it indicates that the IC industry is
developing to maturity. In this situation, the resources in one region are insufficient
to support large-scale IC enterprises. Overall, the main markets of the IC industry are
still in North America, Europe, Japan, and Asia Pacific region. However, in order to
maximize profits and minimize cost of production factors, enterprises need to locate
their factories as close to the location of production factors and markets as possible.
Based on this trend, the production of the IC industry, although decentralized, is still
mainly concentrated in specific regions, such as China in recent years. While IC
industry gets improved, this feature will remain steady.

Blue Ocean and Red Ocean of IC Industry

While the Red Ocean represents all the industries that already exist today, namely the
known market space, the Blue Ocean refers to the industries that do not yet exist
now, that is, the unknown market space. In the Red Ocean, the boundaries of every
industry and the rules of competition are well known. As the market space becomes
more crowded, the prospects for profits and growth are dimming. In contrast, the
Blue Ocean denotes the market space that requires immediate exploration, indicating
the opportunity to create new demands and a high-profit growth. Although some of
the Blue Ocean is explored totally outside the boundaries of existing industries, most
460 Z. Zhou et al.

of the Blue Ocean is opened through extending the boundaries of existing industries
within the Red Ocean [8].
ICs are indispensable core components of electronic products, claiming an
extensive scope of applications. The degree of competition in these large down-
stream markets varies. There is no way to list all the markets individually based on
which is in the Red Ocean and which is in the Blue Ocean. Generally speaking, the
competitive strength/profitability depends on factors such as technical level, capital
level, and the number of competitive enterprises. An IC enterprise can hold down-
stream demands in its own hands and explore the Blue Ocean markets better by the
following ways.
Keep fingers on the pulse of the Blue Ocean market resulting from newly
emerging demands. Downstream demands for IC products are always continu-
ously escalating, and an important milestone in technology always means a
market opportunity for updating IC products. For example, Qualcomm, a fabless
enterprise, made a plan in advance for new generation patented communication
technology in the era of 2G mobile communication network. The patent barriers
made it impossible for every downstream enterprise to avoid the “great wall” of
patents that Qualcomm had built well beforehand, and Qualcomm seized the
opportunity to charge mobile phone enterprises high patent licensing fees.
Another example is ASML, an enterprise specializing in manufacturing photoli-
thography equipment. Taking advantage of the innovation opportunities of
193 nm immersion lithography technology, ASML preceded its rivals such as
Nikon and Canon in launching the equipment to meet the demands from down-
stream foundries and outperformed its peers in a short period of time. After that, it
took the lead in developing the EUV photolithography equipment through indus-
try chain mergers and acquisitions, achieving the position as the sole leader in the
field of wafer photolithography equipment. Like other industries, the IC industry
also follows the law that “first come, first served.” At present, there are many new
application markets for ICs, e.g., artificial intelligence, Internet of Things, and
wearable devices. If IC enterprises are able to seize on the newly emerging
demands from downstream markets, they will have more tremendous market
opportunities than their competitors [9].
Grasp the Blue Ocean market resulting from segmented demands. Even in a
similar and fiercely competitive market, there are segmented demands that are
difficult for general products to meet. These segmented demands may have special
application conditions and performance factors that require customized products to
meet. Once these segmented demands are satisfied, customer trust will always exist,
resulting in steady and considerable profits.
No matter what it says above, the capability of an enterprise in R&D is a
necessary factor. For a relatively long period of time in the past, China’s IC
enterprises in the R&D investment is insufficient, resulting in highly homogeneous
products and fierce price competition. Under such circumstances, China’s IC enter-
prises should keep an open mind, invest more talents and capital in research and
development, and achieve the industrial upgrading from capital advantage to tech-
nological advantage.
22 Economic and Financial Theories Related to IC Industry 461

Globalization and Open Market for IC Industry

The globalization and market opening of IC industry is a global industry. Its

development and production is a very complex and huge industry chain. When
developing IC industry, no country can shut its doors to do it. Opening up and
international cooperation are the mainstreams of the industry.

1) Development and production of IC products. The IC industry is a global vertical

division of labor. Every chip from design and production to sales will inevitably
experience a global division of labor. Take the baseband chip of Apple’s iPhone
as an example. It is licensed by ARM in the UK, designed in the USA,
manufactured in Taiwan and Korea, then packaged and tested in China, and
eventually sold around the world. The equipment and materials used in the
production of ICs are from the Netherlands, the USA, Japan, and other countries.
Through the global open division of labor and the cooperation of industrial chain
to achieve the optimal allocation of resources, all enterprise can concentrate on
their own advantages, constantly promote technological innovation, and optimize
the performance and cost of the chip as much as possible.
2) Marketing of IC products. The cost of IC chip product development is high, and
high investment will bring high risks. At the same time, IC wafer manufacturing
industry follows Moore’s law, and its product technology is evolving toward
higher integration, lower power consumption, and lower cost. Therefore, IC
products must be shipped on a large scale in order to share development costs
and earn profits. Only an open market facing the whole world can meet the
demand of sales scale of IC products to the greatest extent. ITA1 (Information
Technology Agreement 1), ITA2 (Information Technology Agreement 2), and
other information technology tax rate agreements reflect this from the demand
side. These agreements have eliminated tariff barriers for member countries to
enter the international market of ICs and promoted the development of trade in
the information technology industry.

Global Value Chain and Smiling Curve of IC Industry

Michael Porker first proposed the value chain theory in 1985 [10]. In the 1990s,
Zhenrong Shi, founder of Acer, put forth the “smiling curve” theory based on the
value chain, making the summary of the value growth principle in general
manufacturing industry chains: Generally speaking, R&D and marketing service
are located at the front end and the back end of an industry chain, respectively,
belonging to technical field and market field, with higher added values. Production
and manufacturing are in the middle part of the industry chain, having little influence
on the design and marketing of products, with lower added values [11].
Similarly, the IC industry has its own “smiling curve,” but its form is somewhat
different from the general manufacturing industries, as shown in Fig. 22.4.
462 Z. Zhou et al.

Fig. 22.4 The “smiling curve” of the value growth in the value chain of IC industry

The special smiling curve in the IC industry is plotted roughly in the order of
materials and equipment – design – manufacturing – packaging and testing – design.
As compared with the “smiling curve” in the general manufacturing industries, its
specific characteristics are mainly in the following aspects.
The design section appears at both ends of the smiling curve. In the IC industry, a
fabless design house develops the plan according to the demands from downstream
clients and connects with foundries as well as packaging and testing enterprises for
production. The IC products are eventually sold to clients also by the fabless, which
means that the design house is responsible for the design and marketing sections at
the same time.
The wafer manufacturing section has a higher added value. Foundries have well
mastered the core manufacturing technology in the IC industry, providing the main
impetus for the sustainable development of Moore’s law, with a strong technical
strength.
In fact, the theories about the smiling curve and the value chain point to the
reasons of the present situation why the work in the IC industry is shared interna-
tionally: since such sections as equipment, materials, and design in the industry
chain have higher added values while sections such as packaging and testing have
lower added values, in the context of globalization, major multinational factories
usually transfer the sections of low added values such as packaging and testing to
later-developed regions. To catch up with early-developed regions, most of the later-
developed regions start with undertaking the sections of low value-added industries,
gradually buildup industrial strength, and then upgrade to the sections of high value-
added industries.
The development history of China’s IC industry has proved the universal princi-
ple that an industry achieves the industrial upgrade along the “smiling curve.” For a
relatively long period of time in the past, due to the relatively low labor costs, China
was relatively standout in the packaging and testing section among the international
divisions of the IC industry. With continuous technical accumulations, as well as
constant capital and talent inputs, a number of outstanding fabless chipmakers and
foundries have emerged in China since 2000. The growth rate of design and
22 Economic and Financial Theories Related to IC Industry 463

manufacturing industries is far higher than that of packaging and testing industry,
and the proportion in the output value of IC industry has increased rapidly. Based on
the regular pattern in history and the current situation, China’s IC industry will
upgrade along the “smiling curve,” starting from the sections of lower added values
such as packaging and testing, gradually switching to the sections of higher added
values such as manufacturing and designing, and achieving a synergetic develop-
ment in the whole industry chain.

Life Cycle of IC Products

Raymond Vernon, professor at Harvard University, first proposed the theory of

product life cycle in the article “International Investment and International Trade
in the Product Life Cycle” in 1966. Product life cycle, that is, the entire process of a
new product from entering the market to being eliminated from the market, can be
divided into four stages: introduction stage, growth stage, maturity stage, and decline
stage [12].
At different stages of a product life cycle, sales, profit, purchasers, and market
competition all have different characteristics. For these characteristics, see
Table 22.2.
There are reasons for the periodic changes that happen in a product life cycle,
mainly including the upgrading of the product resulting from technological advance-
ments, as well as the continuous updating of the product caused by the constant
escalation of downstream demands.
IC products basically accord with the periodic characteristics suggested by the
theory of product life cycle, which is mainly reflected in the following two aspects.

1) Life cycle within a product

Among IC products, some have a long life, with their basic architectures and
design methods having not undergone any fundamental changes since their
invention. Due to technological upgrade, however, the performances of products
are continuously improved, and now have reached the targets that are imagined at

Table 22.2 Characteristics in different stages of product life cycle

Maturity
Stage Introduction Growth Early phase Later phase Decline
Sales Low Rapid Continuous Downward Down
growth tendency
Profit Small or High Peak Gradually Low or
negative declining negative
Purchasers Those with Relatively high Common Common Subsequent
curiosity in numbers people people users
Market Less Emerging Increasing Fierce Reduced
competition
464 Z. Zhou et al.

the time of invention. CPU and DRAM are the best typical examples of this type
of products.
2) Life cycle of a product form
As the downstream constantly makes new demands, the forms of IC products
will also continue evolving. For example, products such as system-on-chips,
neural network chips, GaAs/GaN chips, SiGe chips, and biochips have become
new development fields, and low power consumption is one of the most impor-
tant indexes for evaluating chips. During the evolution process, new products are
constantly developed to meet market demand, while being continuously replaced
with latest products. Due to the rapid changes in the market, the cycle of IC
products has been obviously shortened. Although mainstream products overlap
with accumulated nonmainstream ones in the market for a certain period of time,
many products are quickly eliminated. Generally speaking, the life cycle of the IC
products for industrial applications is somewhat longer than those used as
consumer goods.

Longtail Effect and Customized Products in IC Industry

The model of longtail effect is shown in Fig. 22.5.

The ordinate values corresponding to the main client base are relatively high, that
is, their individual purchases are relatively large, and the relevant abscissa values are
small, that is, their quantities are relatively small. The opposite is true of the longtail
client base, which corresponds to a lower ordinate value and a larger abscissa value,
that is, although individual clients make small purchases, the quantity of the client
base is large. This curve features a longtail, and, therefore, the condition represented
by this curve is called the “longtail effect.”
Similarly, there is a longtail effect in the IC industry, which is evident in industrial
customers for the following reasons: Industrial clients may have special

Fig. 22.5 The model of longtail effect

22 Economic and Financial Theories Related to IC Industry 465

requirements for working conditions, confidentiality, power consumption, and other

performance of IC products, and are generally willing to pay higher prices for
relevant products.
As their equipment/product has a relatively long updating cycle, e.g., machine
tools, instruments, and automotive front assemblies, industrial clients pay more
attention to the reliability and stability of ICs, tending toward long-term cooperation
with suppliers.
Industrial clients take their demand for equipment as the upper limits on the
quantities of the chips they can purchase, while individual clients make small
purchases. However, the quantity of industrial clients is large. Even though the
demand from individual clients is low in volume, the total volume of demand
from the industrial market is still significant.
In order to meet the specific requirements of longtail clients, it is always neces-
sary to provide these clients with customized products. The customized products
may differ from standard mass-produced products in terms of specification index,
quantity, color, smell, package, and logo.
In IC industry, a fabless enterprise or a design department in IDM directly links
with the market, and, therefore, the customization is mainly achieved in the design
phase by integrating all the required functions and by designing IC products
according to the requirements of clients. These products are not uniformly custom-
ized, which mainly depends on the scales of downstream clients as well as the
marketing strategy.
Although the customization of ICs is achieved mainly in the design phase, some
customized products still require a perfect combination of special materials and special
technological processes, because ICs are products of the combination of software and
hardware. For example, the power-amplifying chips in the communication base
stations have more strict requirements for performances on power intensity, working
frequency range, and high-temperature endurance, which are difficult for the conven-
tional GaAs materials to meet, requiring the use of the new generation material of
GaN. Because of its sensor part, MEMS needs the micromachining on silicon surface
to form a membrane settling on the surface of a silicon crystal, which is then partially
separated from the body of silicon before presenting a movable structure.
The higher the level of customization is, the better the overall profitability
is. Considering the cost of the tape-out, however, not every precise requirement
should entail a customized development. IC enterprises should carefully analyze the
requirements from clients, evaluate the purchasing abilities of clients, and strive to
reach a balancing point on the profitable level and profitable scale.

Equity Valuation Model of IC Enterprises

To evaluate the enterprise value accurately, the first step is to choose the correct
valuation model according to the basic characteristics of the enterprise. There are
two types of valuation models: absolute valuation model and relative valuation
model. The absolute model is based on the analysis of the historical statistics, current
466 Z. Zhou et al.

business measurements, and the prediction of future financial status to value the
enterprise, focusing on the intrinsic value of the target enterprise. Commonly used
methods are discounted cash flow (DCF), option pricing, etc. Relative model is to
compare the target enterprise with similar or related enterprises in terms of P/E ratio,
P/S ratio, P/B ratio, enterprise value multiples (EV/EBITDA), and other metrics to
estimate the value.
Here we introduce some commonly used methods for each model.

1) Absolute valuation model, DCF

The discounted cash flow (DCF) is considered to be the most comprehensive
valuation method. The assumption is that “the basic component of enterprise
value is the future cash flow discounted to present using the rate reflecting future
risks.” This method calculates the value of an asset as the sum of expected future
cash flows discounted to present value:

CF 1 CF 2 CF n
DCF ¼ þ þ⋯þ
ð1 þ r Þ 1
ð1 þ r Þ 2 ð1 þ r Þn

where CF is the cash flow for each term and r stands for weighted average cost of
capital (WACC).
It is almost impossible to estimate the cash flow of each future period;
therefore, a practical way is to estimate cash flows with a fixed growth rate or
viable rates based on reasonable assumptions. Integrated circuit enterprises,
especially design-oriented ones, usually grow rapidly in the beginning and then
enter a stable growth period, so that each period will need a different estimated
growth rate. It can be seen that this method is based on certain hypothetical
predictions which introduce errors and uncertainties. For integrated circuit com-
panies that are not established for a long time or those whose profit model is still
not stable, it is very likely that their historical financial reports are incomplete. In
this case, multiple methods need to be applied, and the relative valuation model is
used to jointly evaluate the enterprise.
2) Relative valuation model
i. P/E ratio:
The P/E ratio model evaluates IC enterprises according to the industry
average. This model links the value to the earning or net income of the
enterprise, which is fundamentally easy to understand. That is, the price per
share of the enterprise equals the earnings per share from its financial report,
multiplied by the industry P/E ratio from the average of comparable
enterprises:

Price per share ¼ r  Earnings per share

where r is the average P/E ratio from the industry, which is estimated by a list of
similar enterprises. Thus, we can calculate the value of the enterprise with the
estimated price per share.
22 Economic and Financial Theories Related to IC Industry 467

ii. Enterprise value multiple (EV/EBITDA):

The enterprise value multiple is also commonly used for the valuation in
the integrated circuit industry. It is a relative valuation method similar to the
P/E ratio introduced above, where the ratio is replaced by EV/EBITDA. The
numerator EV stands for the market value of all the capital invested in the
enterprise.

EV ¼ r  EBITDA,

where r is the average enterprise value multiple of the industry, and the EBITDA
stands for earnings before interest, tax, depreciation, and amortization.
iii. P/S ratio:
The price-to-sales ratio (P/S ratio) is also an effective valuation method
especially when profit is negative, similar to the P/E ratio method. By using
the industry average P/S ratio and the revenue per share of the target enter-
prise, we can get the estimated price per share as below.

Price per share ¼ r  Sales per share

where r is the industry average P/S ratio.

The advantage of the relative valuation model is simple and easy to use, but there
are caveats: First, no two enterprises are exactly the same, so “comparable” is more
of a subjective judgment which causes errors in estimation; second, each enterprise’s
valuation errors will be introduced and propagated into other enterprises’ estimation,
and thus multiplied to cause more substantial misjudgment of the whole market. To
reduce these impacts in the IC industry, the analyst needs to select comparative
enterprises with the same product types, the same application market, and similar
gross profit margins for reference. For IC manufacturing enterprises and packaging/
testing enterprises, reference enterprises with the same production scales and close
processing levels should be selected.
Enterprise values are relative in nature. No matter what method is used, it can
only be estimated and cannot be accurately calculated.
Here we take the major integrated circuit manufacturing companies as an example
in Table 22.3. By the end of 2018, the market value of TSMC has grown to US$191
billion (B), 10B less than Intel’s. The company had been growing steadily in the past
15 years before 2018 with an annual growth rate of 9% in free cash flow. If we
assume a free cash flow growth of 9% over 5 years, a 3% sustainable growth rate
after 5 years, and an average market return of 7%, we could calculate that the current
market value of TSMC is around $164B. It can be seen that the rapid growth has
brought strong expectations to the market, and its market value is still growing after
2018.
From the relative valuation in 2018, we use a rough average of 15 times P/E
value, 2 times P/S value, and 5 times EV/EBITDA value for TSMC, taking into
account three comparable companies: Intel, UMC, and SMIC. The valuation would
468 Z. Zhou et al.

Table 22.3 Comparison of major market performances of Intel, TSMC, UMC, and SMIC on
2018 year end and 2021 year end ($B)
Company Name Intel TSMC UMC SMIC
Listed exchange: NasdaqGS: TSEC:2303 TSCE:2330 SEHK:981
stock code INTC
Fiscal year 2018 2021 2018 2021 2018 2021 2018 2021
Market value 212.8 209.5 191.4 575.4 4.3 29.2 4.3 18.9
(@year end)
Enterprise value 226.6 215.1 172.9 561.7 4.3 26.7 6.8 20.5
Revenue 70.9 79.0 34.2 57.3 5.0 7.7 3.4 5.4
Operating 23.24 22.08 12.77 23.47 0.18 1.86 0.01 0.73
income
Net income 21.05 19.87 12.04 21.37 0.25 2.01 0.13 1.70
Net margin 29.7% 25.1% 35.2% 37.3% 5.1% 26.2% 13.1% 31.3%
FY EBITDA 32.87 33.87 22.97 38.47 1.89 3.48 1.13 2.50
P/E(x) 10.48 10.54 15.93 26.92 17.98 14.53 18.92 11.11
P/S(x) 3.10 2.65 5.60 10.05 0.94 3.80 1.30 3.47
EV/EBITDA(x) 6.90 6.35 7.50 14.60 2.29 7.68 6.04 8.19
Note: The exchange rate is based on the exchange rate of December 31, 2018, and December
31, 2021

be $180B, $68.4B, and $114.9B, respectively. We can see that the results vary in a
big range, which indicates different opinions from different valuation methods.
Thus, it is unlikely to make an accurate estimation of the valuation. But considering
that the market is definitely changing and introducing more opportunities and risks,
TSMC will definitely encounter more challenges if it wants to keep its growing
market value.
Mergers and acquisitions (Ms&As) have occurred quite frequently in the inte-
grated circuit industry. Rather than pursuing short-term interests and gains, both
parties in M&A seek long-term development plans, including supplementing
existing product ecosystems, opening up new markets, and enhancing competitive-
ness. Therefore, when evaluating the target companies or assets, the ultimate rule
behind various models and methods is that “valuation reflects future expectations.”
For example, Softbank acquired ARM for $32B. Although the transaction price
exceeded ARM’s market capitalization for 43% by then, and the price-to-earnings
ratio of the purchase was nearly 70 times, which was significantly higher than the
average price-to-earnings ratio of integrated circuit companies in the international
market; Softbank was still determined to make an offer. The reasons are not difficult
to find out – ARM’s net profit maintained a rapid growth of around 30% in the
five years before the acquisition (data from ARM’s 2012–2016 public financial
report); its free cash flow also had an annual growth rate of 16%. If the next decade
is the period that the Internet of Things will usher in a big outbreak as Softbank has
imagined, we can calculate ARM’s valuation: let’s assume that ARM’s cash flow
grows at 25% for 3 years, then 15% for 3 years, and then 3% for the years after that.
The average opportunity cost in the market is 7%. Based on DCF, its 2016 valuation
22 Economic and Financial Theories Related to IC Industry 469

should be $30.9B, which is roughly the amount of the deal announced. ARM’s
products are mainly intangible intellectual properties which can be copied and
disseminated indefinitely. The company never invests much in heavy assets from
the beginning. But the ARM ecosystem has a significant impact on the entire mobile
industry. From sensors to smartphones, servers, and IoT applications, ARM works
with more than 1400 companies including Qualcomm and TSMC, covering all
major chip markets around the world, forming up a broad industry alliance. All
these factors make ARM a perfect target for Softbank to invest in IoT with a light-
weight strategy. The acquisition of $32B is jointly achieved by the two parties after
considering the long-term development goals. The success of the transaction also
maximizes the benefits for both ARM and Softbank.
In summary, an accurate valuation cannot be achieved. But with multiple methods
combined, we can get a more comprehensive understanding of the market value. The
undergoing of an M&A between IC enterprises is usually the positive expectation of
both parties to maximize their long-term interests, not just short-term benefits.

Principal-Agent System in IC Enterprise Management

In the general corporate governance structure, there is a close relationship among the
shareholders’ meeting, the board of directors, the senior management, and the board
of supervisors. There are two levels of principal-agent relationships: the entrustment
of the shareholders’ meetings to the board of directors and the entrustment of the
board of directors to senior management. The board of directors is trusted and
entrusted by the shareholders’ meeting to be responsible for the property and
operation of the company as the business decision-maker. The board of directors
selects and appoints the managers of the company based on the ability of manage-
ment and profitability. Managers, especially general manager (GM) or chief execu-
tive officer (CEO), have management and agency rights to operate the company as
resolution agents of the board of directors. Management rights refer to the manage-
ment functions of managers on the internal affairs of the company. Agency rights
refer to the commercial agency rights of managers in and out of litigation.
The reasonable matching between board members and the formation of an
effective and complementary structure will help the board of directors to make
scientific decisions. Board members not only need to have rich experience in
company operations, relevant industry experience, and resources, but also need a
high strategic vision to invest and layout for the company’s long-term development.
As the company expands and its operations become more complex, the board needs
to listen to the opinions from more experts in technology, legal, and finance. These
experts can be internal directors of the company or independent directors who have
no relationship with the company. Taking the board of directors of Semiconductor
Manufacturing International Corporation (SMIC) as an example, according to its
2016 annual report released on April 27, 2017, SMIC’s board of directors is
composed of 13 members, each with their own expertise, forming an effective
complementarity. It includes chairman Zixue Zhou (economic expert, in-depth
470 Z. Zhou et al.

research on industrial economy, finance, and taxation, etc.), executive director Ciyun
Qiu (enterprise operation and management expert, IC industry technology expert),
executive director Yonggang Gao (financial management and industrial investment
expert), nonexecutive director Shanzhi Chen (communication industry expert),
nonexecutive director Jie Zhou (securities industry expert and investment expert),
nonexecutive director Kai Ren (industry investment management expert), non-
executive director Jun Lu (credit, industry investment, and fund investment expert),
independent nonexecutive director Guohua Tong (communication industry expert
and management science expert), independent nonexecutive director Liwu Chen
(venture capital expert), independent nonexecutive director William Tudor Brown
(IC design expert), independent nonexecutive director Yihua Zhou (cross-border
investment and trading expert), independent nonexecutive director Shangyi Jiang
(IC development and operation expert), and independent nonexecutive director
Jingsheng Cong (computer-aided design expert for IC and academic expert).
The IC industry is a typical knowledge-intensive, technology-intensive, talent-
intensive, and capital-intensive high-tech industry. These characteristics determine
that its development requires not only the continuous investment of large-scale
funds, but also the continuous accumulation and innovation of technology. The
dependence on talents is particularly prominent and higher requirements are placed
on the management of IC companies.
For example, the CEO of IC foundry company is required to have the capabilities
in technology, research and development, business development, plant operations,
and company management. The products produced by IC foundry are not common
commodities, so the CEO must understand the complex IC manufacturing process
system, the overall technical structure, and the frontier technological development
direction to face the increasing demands of customers and the pursuit and challenges
of competitors. The operation of the IC factory is the most advanced manufacturing
management in the world. The complexity of the process, the accuracy and stability
of the process technology, and the automation of the equipment are the highest in all
industries, requiring highly systematic management tools and management talents
with highly comprehensive abilities. It is difficult to be qualified for this job without
long-term experience in IC factory. IC foundry companies are capital-intensive
enterprises that require sustained capital expenditures to support their technology
research and development and capacity expansion, and management to make com-
prehensive investment considerations to achieve targets of corporate profits, devel-
opment, and long-term benefits for shareholders.
Therefore, the principal-agent management of an IC company requires the board
of directors and the shareholders’ meetings to first understand the characteristics of
the IC industry, and to select and hire senior management personnel with rich
industry experience and comprehensive capabilities. In the process of principal-
agent management, the board of directors and shareholders need to maintain close
communication with the management patiently, respect the professional opinions of
the management, and fully ensure that the professional managers can exert their
management capabilities.
22 Economic and Financial Theories Related to IC Industry 471

Capital Structure of IC Enterprises

Enterprises obtain funds through debt or giving up equity. This combination of

liabilities and equity is called capital structure. Liabilities generally include bonds,
long-term notes payable, and equity including common stock, preferred stock, etc.
The ratio of liabilities and equity reflects the risks of enterprises in a sense, so the “D/E
(debt/equity) ratio” has become an indicator that analysts take into consideration.
Due to the tax shield effect, liability will bring certain tax deduction and do not
affect the ownership of the enterprise. When interest rates are low, debt is more
comfortable to obtain, and enterprises pay less cost overall comparing to giving up
equity. However, the advantage of giving up equity is that, unlike debt, the fund in
exchange for the equity does not need to be paid back eventually. Besides, more debt
means higher risk, and it also means a higher return rate. On the whole, different
companies have different D/E ratios. The decision-makers of enterprises will con-
sider the costs and risks of various funds, and then explore the best D/E ratio based
on the actual situation of the industry characteristics to formulate the most suitable
strategy for their own development.
IC manufacturing companies need to maintain a strictly neutral position among
its customers to ensure their long-term stability and independent growth. Therefore,
its major shareholders cannot be its customers, nor can it make a significant equity
investment to any of the customer. In addition, integrated circuit manufacturing
companies are such capital-intensive companies that large-scale capital investment is
required in the initial stage to build plants and purchase equipment, which can last at
least 3–5 years to achieve an economic-scale effect. Such an enormous capital
demand determines that its capital structure must be composed of both debt and
equity. In the case of TSMC, with the increase in total assets over the years, the total
amount of debt has also increased, from the 430 million Taiwan dollars (TWD, about
USD14 million) in its early years to TWD625 billion in 2017 (about USD20 billion,
according to TSMC’s 1999–2017 public financial report).
On the other hand, integrated circuit manufacturing is also a talent-intensive
industry. Unlike integrated circuit design companies whose success could be
achieved by a smaller number of talented partners, the demand for the high-level
talent pool of the IC manufacturing industry is so large that almost no start-up teams
can meet the demand. Therefore, the success of an IC manufacturing enterprise is
sporadic.
In terms of IC design-oriented enterprises, they are more like software companies.
They require less capital at the beginning, and their capital structure is more flexible.
Therefore, the debt-to-equity ratios of different enterprises are quite different, which
are more related to the development goals. As long as they have sufficient solvency
and controlled risks, IC design start-ups will often focus on taking debt to support
R&D and product design, which will ensure that the company’s equity is in the
hands of the founding team. When a large fund is required for tape out or more
advanced process design, IC design start-ups often give up some equity in exchange
for cash. Because of this flexibility, China’s IC design start-ups have developed
rapidly over the past decade, and many outstanding enterprises have emerged.
472 Z. Zhou et al.

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Development Law and Development Index
of IC Industry 23
Tong Feng, Kai Zheng, and Kelu Hua

Contents
Developing Trend of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Business Characteristics of Memory IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Government Policies and IC Industry Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Investment and Growth of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Technomic Factors for IC Industry Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Changes in Total Investment and Market Scale of Worldwide Semiconductor Industry . . . . . . 483
CAPEX and R&D Expense of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
Entry Barriers of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Regional Migration of IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
IC Industry Investment and Industrial Ecology Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Relationship Between Investment and Technology Advancement in IC Industry . . . . . . . . . . . . . 493
Cost Structure Analysis of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Production Scale Optimization for IC Manufacturing Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Profit and Loss Characteristics of IC Manufacturing Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Shareholder Structure of IC Foundry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Prosperity Indicators of Statistics for IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Prosperity Indicators of Securities for IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

Abstract
This chapter provides useful guidance to investors by analyzing current trends
and potential directions of the IC industry. This chapter also includes core
information about investment in the industry, including investment scale, cost
structure, scale of return, barriers to entry, and associated risks. As newcomers in
the IC market, IC practitioners in China face high entry barriers and hence more

T. Feng · K. Zheng (*)

Semiconductor Manufacturing International Corporation, Beijing, China
e-mail: kevin_zheng@smics.com
K. Hua
Semiconductor Manufacturing International Corporation, Shanghai, China

© Publishing House of Electronics Industry 2024 473

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_23
474 T. Feng et al.

challenges and difficulties. Investors must be fully aware of this fact in their
decision-making process.

Keywords
Investment scale · Regional development · Monopoly · Barriers to entry · Cost
structure · Production of scale optimization · Prosperity indicators

Developing Trend of IC Industry

The development trend of IC Industry is a technology-intensive, capital-intensive,

and talent-intensive industry. In recent years, the IC industry presents the following
characteristics: Steady development, decreasing volatility, and slowing growth;
capital expenditure increases, the stronger the stronger pattern has been formed;
the shift of market and manufacturing focus to the Asia-Pacific region has been
accelerated; the R&D and manufacturing of high-end advanced technology based on
the continuous reduction of feature size is still the mainstream of progress in IC
manufacturing technology, but the rhythm of feature size reduction slows down;
market hotspots converge on mobile and intelligent areas.

1. Industrial Development Has Stabilized, Volatility Has Decreased, and Growth

Has Slowed Down

Over the past 15 years, the IC market has maintained overall growth, but due
to the impact of the economic crisis and the “silicon cycle,” the industrial
development has experienced significant fluctuations. For example, in 1999,
2002, and 2009, there were significant declines; since 2014, the development of
integrated circuit industry has stabilized and the fluctuation range has been
moderate, showing a steady upward trend. The global semiconductor market
grew at an average rate of 7.6% in 2000–2008, compared with 4.4% during
2009–2016, indicating a significant slowdown in growth. With the slow pace of
technological evolution and the dramatic increase of investment intensity, the
semiconductor market will continue to grow slowly in the coming years if there is
no particularly huge market demand.

2. Capital Expenditure Increases and the Stronger the Stronger Pattern Is Formed

The competitive market environment of IC industry requires more capital expen-

diture and R&D costs to scale up production scale and develop new technologies and
products. With the shrinkage of IC feature size, especially after entering the nano
(nanometer) era, the cost of high-end product research and development has
increased, the investment of IC production line is huge, and the investment return
cycle has become longer. Many enterprises have been unable to bear the burden of
large amounts of capital. Enterprise mergers and acquisitions occur frequently, and
23 Development Law and Development Index of IC Industry 475

industrial development is becoming more and more concentrated in some innovative

large enterprises. The pattern that corporate champion leads market is formed
gradually. The trend of “bigger and stronger” is obvious [1]. Statistics in 2016
showed that the top three fabless IC design companies, Qualcomm, Broadcom,
and Unicom, account for 40% of the global chip market share; the top five wafer
foundries, TSMC, GlobalFoundries, Unicom, Samsung, and SMIC account for 80%
of the global market share; the top three packaging and testing enterprises, such as
ASE Technology Holding Co., Ltd., Amkor Technology, Inc., and JCET Group Co.,
Ltd., account for 40% of the world’s packaging and testing market share.

3. Accelerating the Shift of the Focus of Integrated Circuit Market and Manufactur-
ing to the Asia-Pacific Region

In terms of market share, the Asia-Pacific region is the fastest growing region,
accounting for about 60% of the global market share, so there is a saying that “the
Asia-Pacific wins the world.” Especially with the rise of China’s electronic products
processing industry and the improvement of people’s consumption capacity, China
has gradually become the largest consumer market of electronic products in the
world. In terms of industrial structure, the manufacturing industry is increasingly
moving to the Asia-Pacific region. From 1985 to 2000, Asia’s expenditure on chip
expansion accounted for more than 70% of the world’s total. Especially after 2000,
the expansion of chip production mainly concentrated in China and South Korea.
Since 2014, Made-in-China 2025 and industrial funds in the field of integrated
circuits have greatly promoted the investment and construction of local govern-
ments, private capital, multinational corporations, and leading domestic enterprises
in China. From 2015 to 2016, 44 new and planned IC production lines have been
built in China, reaching the highest number in history.

4. The Rhythm of Feature Size Reduction Slows Down

At present, the industrial large-scale production of integrated circuit technology is

still a semiconductor technology based on silicon material. According to the current
development, it can be divided into three stages: the planar device process before
22 nm, the FinFET process at 14 nm/7 nm/5 nm/3 nm, and the GAA process below
3 nm, as shown in Fig. 23.1. There are different voices in the industry about the
development direction of integrated circuit technology in the future, but it is certain
that in the next few years, the silicon-based technology with feature size reduction as
the development route will still be the mainstream of integrated circuit manufactur-
ing technology; The rhythm of feature size reduction will slow down, and the

Fig. 23.1 Process

development stages of silicon
integrated circuit
476 T. Feng et al.

number of transistors on chips will be increased by two times. The cycle has been
extended to 30 months or longer (Moore’s law is about 18 months). However, due
to the parallel development of multi-generation new processes adopted by some
leading enterprises in the industry, new processes can still be delivered to the
market in accordance with the rhythm of Moore’s law. At present, Intel, TSMC,
Samsung, and other semiconductor giants have achieved 7 nm mass production.
Both TSMC and Samsung also have achieved mass production of 5 nm products
in 2020 and announce to implement the mass production of 3 nm products in
2022–2023. It should be noted that TSMC is still using FinFET process in the
3 nm process and plans to reuse GAA process at more advanced technological
nodes.

5. Market Hotspots Gathering to Mobile and Intelligent Fields

At present, the main application markets of integrated circuits are still computers,
communications, and consumer electronics. With the emergence and development of
new industries such as mobile internet, Internet of Things, cloud computing, big
data, artificial intelligence, and so on, the hotspot of future integrated circuit market
may shift to the above industries.
Looking at today’s information industry, its development trend presents three
characteristics: the Internet of everything, information explosion, and mobile use. In
the future, the fifth generation mobile communication will no longer be a commu-
nication concept in the traditional sense, but an extension and expansion on the basis
of the internet. Users can exchange and communicate information between any
items. Such Internet of everything has brought about a high expansion of informa-
tion, and the whole society has become an ocean of information. Terminal informa-
tion products are increasingly communicated through mobile networks. As an
important material carrier of the information industry, the integrated circuit industry
has three characteristics; “reducing the power consumption,” “narrowing the line
width and reducing the cost” emphasized by Moore’s law. In pursuit of higher speed
and lower cost, integrated circuit enterprises will focus more on meeting the low
power consumption requirements of products.

Business Characteristics of Memory IC Industry

Typical integrated circuit products include logic circuit, memory, processor, analog
circuit, and so on. In 2021, the sales of integrated circuit products amounted to
US$556 billion (B), of which memory sales amounted to US$154.8 B, accounting
for 27.8%. At present, half of the top 10 semiconductor companies in the world are
involved in the memory business. The development of the integrated circuit industry
often starts with memory. Japan and South Korea have surpassed the field of
integrated circuits through the development of memory.
23 Development Law and Development Index of IC Industry 477

1. The Memory Market Fluctuates Periodically

Since the invention of transistors in 1947, the integrated circuit industry has been
following Moore’s law. When the price remains unchanged, the number of transis-
tors per unit area can be roughly doubled every 18 months, and so can the perfor-
mance. In other words, the price of an integrated circuit with the same performance
drops by half every 18 months. However, the price of memory products is in a cycle
of rising and falling. Its periodicity is obviously stronger than the overall periodicity
of the semiconductor industry, showing a strong correlation with social GDP. Take
DRAM, a typical memory product, as an example, because of its special industrial
characteristics and large fluctuations in supply and demand, so the price has the
characteristics of long-term sharp ups and downs, and a large cycle will take place in
about 8 to 10 years. The market size and growth rate of DRAM from 1991 to 2016
are shown in Fig. 23.2. For example, in 1998, the industry supply exceeded demand,
and the industry suffered a large loss. In 2000, the internet technology bubble burst,
and the demand from the upstream integrated circuit market suddenly dropped, and
the price of single products dropped by more than 30%. In 2008, due to the impact of
the financial crisis, the overall market demand was weak and product prices
plummeted. The price of 16Gbit capacity DDR2 dropped more than 90% from $6
per unit in the fourth quarter of 2006 to $0.6 per unit in the first quarter of 2009.
Starting in 2012, the industry has witnessed a new round of growth driven by the
sustained growth of smartphones and the promising future of the Internet of
Things [2].
Memory is in great demand, with the characteristics of high standardization, a
single variety, suitable for IDM organization design, production, and sales of the
entire process. However, due to the difficulty of differentiating products, such
products are not enough to form enough customer stickiness and product premium,

Fig. 23.2 DRAM Market Scale and Growth Rate (1991–2016). (Data source: IC Insights)
478 T. Feng et al.

which leads to the fact that manufacturers can only compete on the technology
and industrial scale. When the industry is in an upstream cycle, manufacturers
constantly introduce new technologies to reduce the product feature size and
expand the factory capacity. While the industry is in a downward cycle, manu-
facturers continue to cut shipment prices to maintain market share. Factors such
as capacity expansion and technology iteration of memory manufacturers lead to
sharp fluctuations on the supply side of the market, resulting in a special cyclical
storm in the memory market.

2. The Memory Industry Has Formed an Oligopoly Structure

Because of the high technical difficulty and capital expenditure of memory

manufacturing, it needs a very high capacity scale and shipment volume to gain a
foothold in the market. At the same time, the market fluctuates enormously, often
in the environment of sharp falls and surges. In the downturn of the industry,
enterprises will incur huge loss, and small manufacturing enterprises become
unable to continue operating, leading to bankruptcy or acquisition by large
enterprises. At present, the global memory industry has entered a highly monop-
olistic era. In 2008, the top five memory chip companies in the world were
Samsung, SK Hynix, Micron, SanDisk, and Elpita (acquired by Micron in
2012), accounting for 75% of total revenue. By 2016, the top five global memory
chip companies were Samsung, Micron, SK Hynix, Toshiba, and SanDisk, with
total revenue accounting for 95%.

3. Mainstream Memory Enterprises Adopt IDM Development Model

There are few independent design enterprises in the memory industry, which
presents a completely different ecological situation from the logic circuit indus-
try. At present, most of the mainstream storage enterprises in the world adopt the
IDM development mode, which integrates design and manufacturing. For exam-
ple, Samsung, Micron, and SK Hynix all have their own wafer manufacturer and
back-end sealing and testing factory, and the industrial layout is relatively
perfect. There are three main reasons for this phenomenon. First, this is deter-
mined by the product characteristics of the memory. Memory is a highly stan-
dardized product, and the key is to improve the storage density. The difficulty of
manufacturing is that the coordination and communication between designers
and manufacturers must be very frequent, while memory enterprises often need to
strictly control the core technology and rarely outsourcing orders through OEM.
Secondly, with the improvement of technology level, the cost of memory pro-
duction line increases exponentially, and the development of new technology
needs a lot of manpower and financial support. Finally, the core competitiveness
of memory enterprises mainly lies in the large-scale production capacity with
high yield, and the profits of IDM enterprises are more concentrated than the
division of labor among three industries.
23 Development Law and Development Index of IC Industry 479

To sum up, the memory cycle follows Moore’s law economically, and is mainly
driven by the mainstream applications such as personal computers, smartphones,
Internet of Things, and so on. The capacity scale is mainly influenced by the
oligarchy operation mode of IDM. Besides, it incorporates the boom cycle of social
economy, which becomes a complex data model.

Government Policies and IC Industry Development

The IC industry serves different strategic functions from other industries, which
requires the government to formulate specific policies for IC industry. In the field of
national defense construction and national security, IC products can play an essential
role in areas like weapons, communications, and data storage in a large scale, and
hence enables the state to maintain sovereignty in wars. It can also indicate the core
compatibility of a nation in economic construction and national power area [3].
Based on what mentioned above, countries are very cautious about the exportation
and technology transfer related to the IC industry: they never treat the IC industry as
a completely market-oriented industry. Therefore, states always control the trade of
IC products restrictively. Under this circumstance, the development of the IC
industry in a country cannot merely rely on the market, especially the latecomer
countries. It is even more necessary for them to issue and implement policies to make
the healthy development of the industry.
The fiscal and taxation policies that the government can adopt include: changing
financial support from government, adjusting the scale of credit loans for commer-
cial finance; adopting relevant support policies for venture capital and private equity
fund markets, guiding investment focus on the IC industry; supporting setting up and
carrying out loan guarantee insurance and credit insurance business; establishing a
fiscal and tax preferential policy system to directly serve the IC industry, including
turnover tax, income tax and tariff, and depreciation policy applicable to IC enter-
prise accounting; establishing PPP (public-private partnership) mode to improve the
development of IC industry; and setting up a transfer payment project for the IC
industry.
The industrial policies that the government can use include: supporting alliances
cross industrial enterprises to help the establishment of an industrial chain ecology;
assisting to form patent pools in the IC industry, establishing and guiding intellectual
property strategic alliance, and promoting the use and protection of intellectual
property rights in IC field; establishing standards in major innovation areas of IC,
giving full play to technical standards and building an elite system in the IC industry
[4, 5].
Throughout the history of the global IC industry, government policies have
played an essential role. The new-coming countries use government policies to
catch up with the developed countries, while the developed countries use gov-
ernment policies to protect their advantages and dominance in international
competition. In South Korea, for example, in order to achieve economy growth
480 T. Feng et al.

policy, the government has issued policies mainly involving large enterprises. To
ensure the compatibility of large IC enterprises, the government not only pro-
vides special treatments in terms of financial and taxation policies for large IC
companies, but also provides preferential policies of low interest rates and low
exchange rates for large IC companies. The governors monitored the direction of
enterprise and even directly intervened in its activities. The government also
developed special policies to encourage cooperation between large enterprises
and SMEs (small and medium-size enterprises). The Korean Industry Association
has also played an important role while promoting Korean economy, trade, and
the development of large companies by providing member companies with
reliable information and services for foreign trade training in a timely manner.
The Korean government has also provided sufficient financial support for the
development of the company, which means the company has invested heavily in
research and development (R&D). This set of policies has laid the foundation for
the sustained growth of economy [6].

Investment and Growth of IC Industry

The IC industry has never been completely determined by the market. Government
support is common in its history. In the early stages of development, private capital
was generally reluctant to invest because of chronic losses. This requires the
government to play a leading role and continue to invest in this strategically
important industry, guide the private capital to gradually enter, and then gradually
exit after the industry returns to market leadership.
From the perspective of investment, the development of IC industry generally
needs to be carried out into three steps within 15–20 years.
The first step is based on government support. This stage needs to go through a
period of about 5–7 years of corporate losses. The government laid the foundation
for the healthy development of the industry and helped the company to survive the
survival period and gradually find a position in the market competition.
The second step is the combination of government and private capital. This stage
is about 5–7 years. It needs more private capital investment to support the industry
and cultivate one or two market players with international compatibility to make
corporations adapt to the rhythm of market competition.
The third step is based on the company and the government, but mainly on the
former. This stage is expected to last 5–7 years. In this stage, the state-owned capital
gradually exits, and private capital takes its place, which makes enterprises adapt to
the market completely, and finally makes a virtuous circulation.
To judge the growth stage of the company, we can refer to some economic
indicators, such as gross profit margin. These indicators can also be used to analyze
whether the industry should enter the next stage. In different stages, the government
invests different amount to achieve the best match between the government and
private capital, so as to achieve the best results.
23 Development Law and Development Index of IC Industry 481

Technomic Factors for IC Industry Evolution

Since the 1960s, the global IC industry has experienced three revolutions. The
economic reasons that drive the revolutions also drive the transformation of the
business mode of the IC industry. An analysis of these economic factors can provide
insight into the evolution of the IC industry and help us anticipate future trends in IC
business models. Every time the economic factors like market demand, capital
threshold, and degree of economic division change, IC companies begin to find
new entry points in the industry chain, which renews business model through
continuous corporation and distribution of labor. The revolution of the business
model of the IC industry is shown in Fig. 23.3 [7]. This section mainly analyzes the
economic reasons for the transformation of the business model of the IC industry and
the development trend of the future business model.
In general, there are three main economic reasons driving the transformation of
the IC industry business model: changes in market demand, restriction of capital
thresholds, and the further refinement of industrial labor redistribution. Each change
in the business is the result of the interaction of several reasons.
In 1970s, the IC industry was still in its infancy with relatively simple and small
market demand in scale. The industry’s funding threshold was relatively low, too. A
company could complete the design, manufacture, and packaging steps of IC
products by itself. Thus, most of the foreign IC companies adopted the Integrated
Device Manufacturer (IDM) mode. Since the 1980s, the demand for IC market
began to grow rapidly, and hence the demand for IC products has become more
diversified. Some integrated device manufacturers are unable to adapt to the rapid
change of market. In this context, the private equity fund helped a small group of

Fig. 23.3 Evolution of the business model of the IC industry

482 T. Feng et al.

experienced engineers set up a small IC design company to quickly design new

products to meet market demands – this is the Fabless model. Also, since integrated
device manufacturers have complex industry chains and long production periods, it
is easy to lose market opportunities if corporations are negligent or delayed in a
specific field. The Fabless model just made up for the weakness of integrated device
manufacturer model. After the invention of Fabless mode, the semiconductor indus-
try entered a new stage of the vertical distribution of labor [8].
The IC manufacturing industry is characterized by economies of scale. Large-
scale production can reduce the unit cost of product and thus enhance compatibility.
In the late 1980s and 1990s, as the process upgraded faster, the capital threshold for
manufacturing industry was constantly raised. Only a few manufacturers were able
to expand their productivity. The larger and more specialized the corporation was,
the more advantage it has in the market because of the economy of scale. The market
in Taiwan was so small that local enterprises must enter the international market. So
be the foundry mode (Foundry) and TSMC. The foundry mode lowered the thresh-
old of the design industry and promoted the prosperity of small and medium IC
design vendors, which mostly adopted the Fabless mode. The rapid development of
Fabless and foundries has promoted the prosperity of vertical distribution of labor.
Since then, the IC industry entered the era of international cooperation.
After the 1990s, the division of labor in the IC industry was further refined. In
pursuit of higher economic and industrial efficiency, most Fabless mode companies
used design company IP (Intellectual Property) to speed up the product design
process. It saves the company effort and shortens the time to market. During this
period, professional IP companies, represented by ARM (founded in 1990), had
emerged. EDA (Electronic Design Automation) tools in IC design had also been
greatly improved. EDA technology greatly improved the efficiency and operability
of circuit design and hence reduced the intensity of designing works. EDA compa-
nies continue to grow, and the competition is increasingly fierce. To help design
companies reduce verification time and accelerate the process of the product
appearing on the market, the three major EDA companies (Cadence, Synopsys,
and Mentor) are committed to develop hardware simulation tools and manage the
related market. The semiconductor industry hence entered an era of complete
distribution of labor according to their professions.
From the perspective of the historical trend, the distribution of labor can promote
efficiency in industries. Despite this, IDM vendors still exist. Throughout the global
semiconductor industry, IDM vendors including Intel, Samsung, SK Hynix, Micron,
Texas Instruments, Toshiba, and NXP are among the top 10 semiconductor manu-
facturers. The IDM mode needs to meet three prerequisites: First, they possess the
advantage on internal integrated resources, which requires a close cooperation
among IC design, manufacturing, and packaging and testing. Second, they have
technological advantages. Most IDM vendors have their own IP developing depart-
ments. After long-term technology research and experience accumulation, these
departments possess sufficient technical reserves, strong development capacity,
and leading position in technology. Finally, the product process is unreplaceable,
which means the procedure cannot be done by foundry, such as CPU and memory.
23 Development Law and Development Index of IC Industry 483

As the industry becomes more mature, the business mode is likely to change
further, while the integration of manufacture, design, and packaging and testing will
remain to exist. Based on the manufacture industry, the deep cooperation between IC
design and packaging and testing manufacturers can make all links in the industry
chain move quickly and hence improve industrial efficiency. In fact, both distribu-
tion of labor and integration are methods for industrial innovation. Every time the
distribution of labor and innovation of business mode can make progress on society.
After the distribution of labor, one corporation can focus on a certain field and
develop core technologies, and then integrate its resource based on its profession. By
this process, it may become indispensable in the industry.

Changes in Total Investment and Market Scale of Worldwide

Semiconductor Industry

Throughout the global semiconductor industry, the change of market scale shows a
cyclical fluctuation pattern of overall upward and individual year downward. The
investment of semiconductor industry is basically consistent with the changing trend
of global semiconductor industry market scale.

1. Global Semiconductor Industry Market Scale

The market size variation of the global semiconductor industry shows a cyclical
fluctuation pattern of overall increase and individual annual decline. As shown in
Fig. 23.4, the scale of semiconductor market grew nearly 100-fold from 1976 to
2021. Influenced by the financial crisis and the global economic environment, the

Fig. 23.4 The global semiconductor industry market scale changes (Data source: WSTS.)
484 T. Feng et al.

semiconductor market declined significantly in 1998, 2001, 2002, 2008–2009, and

2019. The figure above shows the compound annual growth rate (CAGR) from 1980
to 2021.

2. Investment Scale of Semiconductor Industry

Investment in semiconductor industry is mainly divided into two parts: Fixed

assets investment (i.e., capital expenditure), such as the expenditure of workshops,
clean rooms, equipment, and materials used by wafer factories for the production
line construction, the expenditure of purchasing servers and electronic design soft-
ware by design enterprises, and intangible assets investment (mainly R&D invest-
ment). That is, the development cost of advanced technology. Capital expenditure of
global semiconductor industry is slightly higher than R&D investment. For example,
in 2021, the capital expenditure of global semiconductor industry is 153.9 billion US
dollars (see Fig.23.5), and R&D investment is 71.4 billion US dollars. With the
expansion of the semiconductor market scale, the total investment and the proportion
of the semiconductor industry also show a growing trend. Similarly, affected by the
financial crisis, the fluctuations in 2002 and 2008–2009 went down, which is
basically consistent with the changing trend of the global semiconductor industry.
That is, when the market scale expands, the corresponding investment will occur. It
will also improve.

3. The First and the Second Countries Have Different Levels of Investment, with the
Latter Spending Slightly Less on Research and Development

As Moore’s Law reveals, the IC industry is developing rapidly at the rate of about
two generations of technology nodes. The investment scale of leading enterprises

Fig. 23.5 Capital Expenditure in the Global Semiconductor Industry. (Data source: IC Insights.)
23 Development Law and Development Index of IC Industry 485

(the first enterprise to complete the technological renewal, which is mostly the
first state-owned enterprise) is slightly higher than that of the follower enterprises
(those enterprises that have invested in the R&D of the technology after the
technology has been conquered by the leading enterprises are mostly technology
follower enterprises). This is mainly reflected in its R&D funding. The integrated
circuit industry has the characteristics of “one generation technology, one gen-
eration equipment, and one generation product.” Especially for advanced tech-
nologies, it is necessary to purchase new equipment and build new factories [9].
Therefore, for new technologies, there is little difference between the scale of
fixed assets investment required by leaders and technology followers. In terms of
investment scale of intangible assets (mainly R&D), leaders need to spend a lot of
manpower and material resources to plan research technology routes and find
new materials to promote the latest technology; while technology followers can
refer to research direction of leading enterprises to reduce R&D costs, as shown
in Fig. 23.6.

4. Later-Developing Countries Must Invest More than First-Developing Countries

to Achieve Technological Transcendence

The advancement of technology directly determines the rise and fall of enter-
prises. The new technology products that are updated first have higher profit
margins, and correspond to a large number of market demands, while the technology
followers are difficult to make profits. Due to the relative weak technological
foundation and the lack of professional talents and other factors, the latter countries
need to complete a higher amount of investment than the first countries in order to
achieve technological transcendence.

Fig. 23.6 Leader and follower R&D funding for different technology nodes (Data source: WSTS.)
486 T. Feng et al.

CAPEX and R&D Expense of IC Industry

The integrated circuit industry is highly capital-intensive and technology intensive.

Capital expenditure and technology R&D expenditure have become the two major
expenditures in the investment of integrated circuit industry.

1. Capital Expenditure

According to IC Insights, the capital expenditure of the semiconductor industry

reached 152.67 billion US dollars in 2021, up 38% from 2020. The top three are
Samsung, TSMC, and Intel. Samsung’s capital expenditure in 2021 was $38.1
billion, TSMC’s was $30 billion, and Intel’s was $20.3 billion. Memory manufactur-
ing and wafer substation factories have become the main capital expenditure,
accounting for 10 of the top 10 companies in capital expenditure. TI capital
expenditure is 2.5 billion US dollars, an annual increase of 279%, which is the
largest increase among the top 10 semiconductor enterprises.
The top 15 semiconductor companies listed in Table 23.1 had capital expenditure
of $134.7 billion in 2021, accounting for 88.2% of total capital expenditure. Memory
manufacturers and wafer factories dominated the mainstream position of capital
expenditure. Major memory factories accounted for 44.8% of total capital expendi-
ture in the semiconductor industry. The data of major wafer factories also reached
27.4%.

2. Technology R&D Expenditure

R&D investment is an important indicator reflecting the industry development

and enterprise competitiveness. According to statistics from IC Insights, the global
semiconductor industry’s R&D expenditure in 2021 totaled 71.4 billion US dollars,
as shown in Table 23.2. Unlike capital expenditure, design firms, together with IDM,
pure-play foundry, and memory companies, play a major role in R&D expenditure.
IC Insights statistics show that with the continuous advancement of integrated circuit
technology, the cost of new technology research and development is also increasing.
Take Intel as an example. Over the past two decades, the overall trend of R&D
expenditure as a proportion of revenue has increased, which was 16.4% in 2010, but
by 2021, the proportion has reached 21.3%.

3. Different Investment Structures in Different Sectors

From the perspective of economic return on investment, the integrated circuit

industry as a whole requires long-term and patient investment. However, the strate-
gic and economic duality of different links in IC industry is different, and the
investment structure of different links is slightly different. Integrated circuit design
industry belongs to the light assets sector. Although the cost of streaming and human
resources is increasing year by year, it still belongs to light investment compared
with manufacturing and packaging industries. Moreover, the production and sales
 23

Table 23.1 List of capital expenditures of semiconductor enterprises from 2020 to 2021
2020 2020-21 2020-21 Change 2021 Share
Rank Rank Company Region Foundry IDM 2020 2021 (%) (%)
1 1 Samsung Electronics South Korea • 27.40 38.11 39% 24.96%
2 2 TSMC China(Taiwan) • 17.07 29.96 76% 19.63%
3 3 Intel Americas • 14.45 20.33 41% 13.32%
5 4 SK hynix South Korea • 8.65 10.82 25% 7.09%
4 5 Micron Technology Americas • 9.02 10.56 17% 6.91%
6 6 SMIC China • 5.25 4.12
22% 2.70%
(Mainland)
7 7 YMTC China • 3.50 3.75 7% 2.46%
(Mainland)
8 8 CXMT China • 3.00 3.40 13% 2.23%
(Mainland)
19 9 Texas Instruments Americas • 0.65 2.46 279% 1.61%
12 10 Huahong Semi China • 1.80 2.38 32% 1.56%
(Mainland)
Development Law and Development Index of IC Industry

10 11 STMicroelectronics EMEA • 1.28 1.83 43% 1.20%

11 12 Kioxia (Toshiba Japan • 1.10 1.80 64% 1.18%
Memory)
20 13 GlobalFoundries Americas • 0.50 1.80 260% 1.18%
14 14 UMC China(Taiwan) • 1.00 1.72 72% 1.13%
13 15 Infineon Technologies EMEA • 1.08 1.61 49% 1.06%
Top 15 Companies’ Total ($Billion) 95.74 134.66 41% 88.20%
Total Worldwide Capital Spending ($Billion) 110.24 152.67 38%
Data source: Gartner.
487
 488

Table 23.2 2019–2021Semiconductor enterprises R&D expenditure list

2021 2020-21 Change 2021 Share
Rank Company Region Fabless Foundry IDM 2019 2020 2021 (%) (%)
1 Intel Americas • 13,362 13,556 15,190 12.05% 21.27%
2 QUALCOMM Americas • 5,398 5,975 7,176 20.10% 10.05%
3 SAMSUNG South Korea • 2,959 5,500 6,500 18.18% 9.10%
ELEC
4 BROADCOM Americas • 4,696 4,968 4,854
2.29% 6.80%
5 Nvdia Americas • 2,829 3,924 5,268 34.25% 7.38%
6 TSMC China • 3,048 3,895 4,504 15.64% 6.31%
(Taiwan)
7 SK HYNIX South Korea • 2,473 3,100 3,672 18.45% 5.14%
8 MediaTek China • 2,101 2,751 3,469 26.12% 4.86%
(Taiwan)
9 MICRON TECH Americas • 2,441 2,600 2,663 2.42% 3.73%
10 AMD Americas • 1,547 1,983 2,845 43.47% 3.98%
Top 15 Companies’ Total ($Million) 40,854 48,251 56,141 16.35% 78.63%
Total Worldwide Capital Spending ($Million) 56,300 68,400 71,400
T. Feng et al.
23 Development Law and Development Index of IC Industry 489

cycle of chips in the market is relatively short, the investment recovery is fast,
and the economic results can be quickly reflected. This kind of knowledge-based
product is very risky, not suitable for traditional investment and financing
methods, and difficult to obtain bank loans, thus only suitable for venture capital
(VC). In the mature period of industrial development, there is also a need for
sustained capital investment and other forms of capital intervention, such as
private equity (PE) funds. Integrated circuit manufacturing industry and feudal
testing industry belong to the heavy assets sector. The cost of plant construction
and equipment investment in the early stage is high, and the investment return
cycle is long. At the same time, driven by Moore’s law, its production lines and
technologies have been constantly improving, with the characteristics of “one
generation technology, one generation equipment, and one generation products.”
It requires not only a large amount of investment, but also needs sustained
investment. Therefore, from the beginning, it must be PE þ government + market
+ bank + other capital joint investment. The investment in manufacturing is
characterized by large investment, long-term investment, and high investment
barriers, and it is difficult and lack of confidence for private capital to enter. The
integrated circuit industry is the guarantee of national information security, which
is of great strategic significance, so it needs national investment funds to guide its
development.

Entry Barriers of IC Industry

Entry barriers are unfavorable factors that a new enterprise may encounter while
entering an industry. Entry barriers protect existing enterprises in the industry and
therefore become the first difficulty that newcomers must overcome. The IC industry
possesses high density of capital and technology. Hence, with the continuous
advancement of science and technology, the entry barriers are increasing. At present,
the entry barriers are mainly the following aspects.

1. Patent Barrier

In recent years, China’s IC industry has developed well, but the patent reserve
is low. American companies still dominate the list of companies with the largest
number of chip patents. For example, Intel and AMD have almost monopolized
the CPU market. Intel has established barriers on the entire business including
intellectual property, technology accumulation, scale cost, and software ecology,
which have never shown sign of decline. For another example, the patent pro-
tection term in the United States is 20 years. While the original patent of FPGA
design has not expired [10], companies involved in the FPGA industry must
develop products by themselves. Before the FPGA patents expired, there were no
FPGA companies in China. Hence, China’s FPGAs have fallen behind for at least
490 T. Feng et al.

20 years. In order to achieve the sustainable development of China’s IC industry,

Chinese enterprises must independently master the core technologies quickly.
Without core technology and focusing only on the expansion of the industry, it
will be easy for competitors to block themselves through patents in the future
competition. Therefore, entering the IC industry will face higher patent barriers.

2. Political Barriers

In the information era, information security has become the core field of political
and economic combats among countries. As the core of the information field, ICs are
of great strategic significance for ensuring national security. Thus, some newcomers
also need to overcome political barriers.

3. Technical Barriers

The IC industry is a typical technology-intensive industry. Therefore, if an IC

enterprise wants to grow, it must possess technical compatibility. Also, because of
the rapid metabolism of IC technology and products, IC companies are supposed to
possess ability for continuous revitalization and hence meet the changing market
demands. Besides, the manufacturing process of IC is complex, and the precision is
high. Therefore, to revitalize technology and manufacturing process, IC enterprise
needs to go through long-term, large-scale research and practice. With the develop-
ment of the packaging and testing industry, advanced packaging technology has
become the barrier for new entrants. For reasons above, new entrants also need to
take technical barriers into consideration.

4. Capital Barriers

The IC industry always needs large investment, but the investment returns are
slow while the risk is high. The existing capital barriers are mainly shown in two
aspects: First, the development of industry requires a large amount of capital
investment; second, the investment have a long return period and low return,
which means the investors need to wait for a long time. The IC manufacture industry
currently receives the largest investment in the whole manufacture industry. For
example, a 300 mm 14 nm production line requires the investment of up to 10 billion
US dollars: each process node needs to be invested continuously for at least 5 years
before it will yield revenue [11, 12]; Also, the IC design industry requires a large
amount of money for R&D employees, the imported equipment and technology, and
the R&D of products. Finally, the new packaging technology also requires huge
capital investment. Therefore, no matter which part the entrant prepares to partici-
pate in, it must consider that whether the capital investment can maintain various
expenditures or whether new entrants can take the financial risks themselves.
Therefore, the new entrant also needs to overcome capital barriers to enter into the
IC industry.
23 Development Law and Development Index of IC Industry 491

5. Human Resource Barrier

The IC industry is a high-tech industry. Admittedly, policies and funds are

indispensable factors, but the core factor for enterprises to become bigger and
stronger is technology, which depends on professional elites. At present, the pro-
fessionals in China’s IC industry are very scarce, unable to meet the need of the
industry. Therefore, for newcomers, human resource barriers are one of the major
problems they have to face. In the IC design industry, creative technical elites and
experienced managers can help enterprises improve efficiency and maintain their
leading position in technology field; in IC manufacturing industry, enterprises need
process technology R&D elites; in IC packaging and testing industry, the new
packaging and testing technology elites are essential for a company. No matter
how these elites are introduced, the cost and difficulty for bringing them is high.
Thus, human resource is also a restrictive barrier for newcomers to the industry.

Regional Migration of IC Industry

Where there is a market, there is the industry. From the 1960s to the present, the IC
industry has undergone three distinct regional evolvements as the market has
changed [13].
In the 1960s, the integrated circuit industry experienced its first regional evolu-
tion. The reason for this evolution is that the United States has a comparative
advantage in IC design, while Asia has a comparative advantage in labor costs. As
a result, the international division of labor and transfer of integrated circuit industry
began: the testing industry and packaging industry began to shift from the United
States to Asia. At present, China, Malaysia, and Korea are the main IC packaging
and testing bases in the world.
In the 1970s, there were barriers to trade in integrated circuits between Europe,
the United States, and Japan. The trade cost of exporting integrated circuits was very
high. American enterprises reduced the trade cost by establishing manufacturing
factories in Japan and Europe. At the end of 1980s, Taiwan IC foundry industry,
represented by TSMC, seized this historic opportunity, avoided the vicious compe-
tition dilemma of American and Japanese enterprises, and took a new path. It chose
to provide wafer manufacturing OEM for semiconductor companies in these coun-
tries, thus transforming competition into win-win cooperation and others. The
success of the national and regional semiconductor industry has led to the rapid
growth of wafer manufacturing agent business in Taiwan, China. Dedicated Foundry
TSMC has rewritten the business model of the semiconductor industry. After the
establishment of TSMC, integrated circuit manufacturing industry began to shift to
China. This is the second significant regional evolution of the integrated circuit
industry, in which the industrial transfer is mainly concentrated in the manufacturing
sector.
492 T. Feng et al.

The third regional evolution is mainly the transfer of integrated circuit design
industry, which aims to be closer to the local market and reduce risks. The design
industry began to shift from the United States to Japan and Europe in the 1970s, to
Taiwan and Singapore in the late 1980s, and to mainland China in the twenty-first
century. Many international chip companies, including Intel and Texas Instruments,
have established R&D centers in China, mainly engaged in the development of
system software and product solutions.
With the three regional evolutions of global integrated circuit industry, the market
demand, enterprise development, and investment structure of integrated circuit
industry have also undergone regional changes. We have observed the trend of its
evolution from the United States to Japan, to South Korea, and then to China.

IC Industry Investment and Industrial Ecology Development

Industrial ecology refers to the comprehensive environment in which industries are

in the process of development. Unlike the industrial chain, it is influenced by many
external factors, such as the national policy and regulation of the IC industry
economy and investment, the reformation of the mechanism system, the research
and development technology revitalization, and the investment and financing situa-
tion, etc. For the IC industry, industrial investment will greatly affect the construc-
tion of the IC industrial ecology. Reasonable investment and acquisitions will help to
build the IC industrial ecology. Blind investment or diversification of investment
will seriously damage to the industrial ecology.
For example, Taiwan had also invested heavily in the memory industry, but it has
not worked well. There are three main reasons: From the perspective of developing
mode, Taiwan adopted the foundry mode to develop memory enterprises, which
mostly failed in DRAM; from the perspective of technology, Taiwan DRAM
manufacturers relied too much on technology transplantation, which means a lack
of self-developed technology; in terms of the market, the enterprises’ performance in
the global memory market is not satisfactory, while past investments have made the
first two-third of Taiwan’s total production aimed in the storage industry, which
results in an over-supply situation. As a result, the prices of DRAM and NAND flash
memory have fallen a lot, which is unfavorable for Taiwan’s memory companies
[14]. In contrast, after the 1980s, the Korean government began to support the
DRAM industry, to be specific, the Samsung Semiconductor. The government
organized a DRAM R&D project jointly undertook by the official and unofficial
powers. The support from the government has strongly promoted the DRAM
industry and created a healthy industrial ecology. Moreover, when the global
semiconductor market was unfavorable and the DRAM industry was in a downturn,
Samsung has adopted a counter-cyclical investment strategy to double investment in
its R&D in self-developed technology to cultivate high-end elites and expand
production. This strategy makes it become one of the most advanced memory
manufacturers in the world [15].
23 Development Law and Development Index of IC Industry 493

In summary, every achievement requires a variety of factors. No strategy can be

easily replicated, so as the investment for the IC industry. It is helpful for the IC
industry to scientifically plan for the development of the IC industry and select
appropriate investing strategy by combining the characteristics of the nation, the
local place and enterprise itself. Appropriate strategy is conducive to the establish-
ment of the ecology with a virtuous circulation, which is of great significance to the
IC industry.

Relationship Between Investment and Technology Advancement

in IC Industry

The integrated circuit industry is a capital-intensive industry. Its investment charac-

teristics are large scale, high risk, and long return cycle [16]. With the progress of
integrated circuit technology and the increasing complexity of integrated circuit
technology, integrated circuit enterprises must keep up with the latest technology
and increase investment in R&D personnel, plant, and equipment. Therefore, the
production and R&D costs of integrated circuit are getting higher and higher, and the
scale of investment is getting larger and larger.

1. The Scale of Investment in IC Industry Increases with Technological Progress

For the semiconductor industry, technology is life. Only by mastering the most
advanced technology can we hold a place in the market. The progress of technology
nodes will increase capital expenditure and R&D expenditure. Take the integrated
circuit manufacturing industry as an example, with the reduction of feature size, each
new generation of technology, especially advanced technology, requires the
re-purchase of new equipment, which leads to the continuous expansion of invest-
ment scale. As can be seen from Table 23.3, after entering 32 nm, the investment cost
of each technology node is about 1.5–2 times that of the previous generation
technology, and it needs continuous high-intensity investment to build production
lines to form a strong scale advantage.

2. The IC Industry Has Not Only a High Investment Threshold, but Also a High
Investment Risk

Table 23.3 Estimates of wafer fab investment for different technological nodes
Technological nodes 90 nm/65 nm 32 nm/28 nm 22 nm/20 nm 16 nm/14nm
IP/EDA, etc. designer cost 15~20 60~70 100~150 200~300
($Million)
Capex ($Million) 2500~3000 3600~4500 4600~5700 5600~7000
R&D spending ($Million) 200~400 600~800 1000~1300 1700~2500
Monthly capacity 35000~50000
494 T. Feng et al.

With the increasing demand for investment scale in the IC industry, the invest-
ment risk is becoming greater and greater, thus, most IC enterprises are afraid to
upgrade their technology. As shown in Fig. 23.7, technology giants with strong
R&D teams can hardly support the continuation of technology. Only a few compa-
nies insist on investing in the latest technology.

3. The IC Industry Must Continuously Invest in the Development of Advanced

Technology

Although the expansion of investment scale and the existence of higher invest-
ment risks increase the difficulty of investment, integrated circuit technology is
bound to progress, and related enterprises need to invest in the development of the
latest technology. First, human society has entered the information age. New emerg-
ing industries such as artificial intelligence, Internet of Things, big data, and mobile
internet need more advanced integrated circuit products to support them. Market is
the foundation of enterprise survival. Driven by the market, technology must also
progress. Second, the integrated circuit industry has been following Moore’s law.
Once the new generation of technology breaks through, the price of the products of
the previous generation of technology nodes in the market will fall rapidly. The
non-hedging characteristics of information products prompt enterprises to transfer to
advanced technology. Third, the main share of future industrial growth still comes
from advanced technologies (see Fig. 23.8). In summary, the integrated circuit
industry must continuously invest in the development of advanced technologies.
.

Cost Structure Analysis of IC Products

The cost of integrated circuit products mainly includes manufacturing cost and
design management cost.

1. Manufacturing Cost

Each IC is manufactured through a series of steps including photolithography,

etching, ion implantation, metal deposition, interconnection, wafer testing and die
cutting, core packaging, and final grade testing. The cost of these processes is the
cost of IC manufacturing. The manufacturing cost can be divided into three parts:
chip cost, test cost, and packaging cost [17].

Chip Cost þ Packaging Cost þ Testing Cost

Manufacturing cost ¼
Yield
Chip cost can be understood as the cost allocated to the chip which formed
through the wafer cutting step. Generally, chip cost accounts for 50–60% of
manufacturing cost.
 23
Development Law and Development Index of IC Industry

Fig. 23.7 Worldwide Fab Facilities list within 130 nm ~ 3 nm technological nodes (including mass-produced and researching) (* Intel’s chips with 7 nm
process haven’t mass-produced in 2021, but the density of Intel chips with 10 nm process can be compared with TSMC’s and Samsung’s 7 nm products.)
495
 496

Fig. 23.8 2006–2025 Actual and projected turnover of the global pure-play foundry market for integrated circuits (Data source: Gartner)
T. Feng et al.
23 Development Law and Development Index of IC Industry 497

Chip costs can be simply calculated and expressed by the following formula:

Wafer cost
Chip cost ¼
number of chips per wafer ⁎ Yield

Packaging is to bond bare chips with substrates to form integrated circuit products
sold in the daily market. Packaging costs account for 30–40% of manufacturing cost.
The traditional packaging cost is proportional to the pin number and power con-
sumption of the chip. However, with the development of technology, the number of
pins is no longer the main reason to determine the packaging cost.
Each chip has to undergo a series of test steps to test its key characteristics, such
as the maximum frequency, power consumption, calorific value, etc., before it leaves
the factory. Usually, the test cost accounts for about 10–15% of the manufacturing
cost. The traditional test cost is proportional to the number of pins on the chip. With
the development of 3D packaging technology, the test cost will no longer follow
this rule.
In addition, enterprises that do not own their own intellectual property rights have
to pay licensing fees to the corresponding IP vendors for each produced wafer, which
usually accounts for about 5% of the manufacturing cost.

2. Design Management Cost

Design management cost is close to the manufacturing cost, which can be simply
divided into design R&D cost, management cost, and marketing cost. Design and
R&D costs include engineer’s manpower cost, EDA tool cost, third-party IP cost,
etc. Management cost refers to the expenses incurred by the administrative depart-
ments of enterprises to organize and manage production and operation activities,
such as wages and welfare, office expenses, posts and telecommunications expenses,
insurance premiums, and other expenses. Marketing cost refers to expenses related
to marketing activities. For integrated circuit enterprises, design and development
costs account for the highest proportion of design and management costs.
The development of integrated circuit industry cannot be separated from the
promotion of advanced technology, and advanced technology cannot be separated
from human control. The lack of high-end talents will restrict the development of
integrated circuit enterprises. It is particularly important to respect talents and give
full play to their advantages. Appropriately increasing the cost of design manage-
ment can attract and retain more excellent professional and technical personnel as
well as excellent management personnel who are familiar with the laws of industrial
development.

3. Variation of Product Cost of Different Technical Nodes

As predicted by Moore’s law, the core cost of the chip which achieves the same
function decreases after adopting advanced technology. For those high-density
chips, this downward trend is more obvious. For each generation of technology
498 T. Feng et al.

below 28 nm node, the decline rate of core costs tends to moderate. When the next
generation chips with complex functions come out, they will enter the era of high
price and high quality.

Production Scale Optimization for IC Manufacturing Industry

Integrated circuit manufacturing industry is an industry with slow investment

effect, high risk and obvious scale effect. Enterprises must invest heavily in the
research and development of new technologies to ensure competitiveness in the
market and to be able to withstand the risks brought by industrial cycle fluctua-
tions. Under the premise of insufficient supply in China’s integrated circuit
market, enterprises should estimate a minimum production scale, that is, mar-
ginal cost equals average cost. Then production is carried out to ensure that new
production lines can maintain a basic balance of revenue and expenditure without
losing money.
Today, compared with the 1970s, the investment capital required for the new
generation production lines has increased tens or even hundreds of times. At
present, the investment of 200 mm production line is more than 1 billion US
dollars [18]. The investment of 32 nm/28 nm production line of 300 mm is even
more than 5 billion US dollars, and the investment of 14 nm production line can
reach 10 billion US dollars [18]. For the integrated circuit manufacturing indus-
try, the expenditure of each production line can be roughly divided into two parts:
Variable Costs that increase or decrease with the change of production quantity,
such as the cost of consuming raw materials, patent fee, administrative expendi-
ture, sales expenditure, and technological research and development expenditure.
Fixed costs that are relatively independent of production, such as design costs,
construction costs, and equipment purchase costs. The larger the proportion of
fixed costs, the more the costs are spread over a larger number of products, and
the more marginal costs are lower than the average costs. On the contrary, the
difference between marginal cost and average cost is not significant, and the
impact of scale on revenue is relatively small.
The following is an example of a 28 nm production line with a maximum 300 mm
wafer capacity of 50,000 pieces. The fixed cost investment of the production line is
US$5 billion, depreciated by 7 years, and the depreciation cost of each wafer is about
US$1200 at full production. Assuming that $1200 accounts for about 50% of the
total cost (and the variable cost of a single wafer is also $1200), we can roughly
calculate the minimum production scale (calculated at a net return of 0) based on the
following formula [19, 20].

fixed cost investment

Chip price ¼ þ variable cost ⁎ ð1 þ net returnÞ
depreciation years ⁎ 12 ⁎ monthly copacity

For example, when a single wafer sells for $3600 in the market, its minimum
production scale is about 25,000 pieces per month. Under the above conditions,
23 Development Law and Development Index of IC Industry 499

Fig. 23.9 Analysis of quantity-cost-profit of production line model. Based on US$5B investment,
maximum 50,000 wafers (300 mm) per month is deduced

Fig. 23.9 shows the relationship between production scale and benefit. Because the
influence of different production scales on variable costs is ignored, the relationship
between production scale and benefit is linear. Through the above model, we can get
the reverse trend of wafer price and minimum production scale. That is to say, the
lower the price of a single wafer and the smaller the profit margin, the higher the
requirement of minimum production scale, the greater the pressure on factory
production. Figure 23.9 shows the Quantity-Cost-Profit of Production Line Model
based on an investment of $5 billion and a maximum monthly capacity of 50,000
pieces (diameter 300 mm).
500 T. Feng et al.

After reaching the minimum production scale, according to the law of

diminishing marginal returns, we can theoretically calculate an optimal produc-
tion scale. However, from a macro point of view, the supply of the entire Chinese
integrated circuit industry market is less than the demand, that is, the existing
semiconductor production line capacity has not yet met the market demand.
Therefore, it is not the marginal profit that determines the scale of production,
but the market capacity and whether the designed maximum production scale can
be reached. On this premise, the larger the scale, the higher the revenue will be.
Compared with the shortage of supply in China’s integrated circuit market, the
global integrated circuit industry should consider its strong monopoly characteris-
tics. According to the development experience of the global integrated circuit
industry in the past decades, the top companies often occupy the majority of market
share in the subdivision field, presenting the oligopoly development pattern of “the
bigger is the bigger.” According to the US Semiconductor Manufacturing: Industrial
Trends, Global Competition, and Federal Policy, the IC market is an imperfectly
competitive market, which will result in a special “optimal scale of production” [21].
That is, in this market, the price of products is higher than the average cost, and the
average cost is higher than the marginal cost. Monopoly firms can make economic
profits. However, because the overall market demand is limited, they cannot expand
production capacity indefinitely. At the same time, they need to consider the
competitive relationship with other monopoly firms, so they need to keep producing.
Quantity oligopoly games should continue to find the best scale of production.

Profit and Loss Characteristics of IC Manufacturing Industry

The integrated circuit manufacturing industry is a typical asset-heavy link in the

integrated circuit industry. It has the characteristics of slow investment, high risk,
and obvious scale effect. While enterprises continue to invest a lot of money in new
technology research and development to maintain market competitiveness, they also
need to bear the risks brought by industrial cycle fluctuations. Throughout the whole
IC manufacturing industry, due to the high depreciation caused by the high invest-
ment of assets in the early stage, its profit and loss is usually characterized by the
pressure of loss in the early stage. After 5–7 years of high depreciation and capacity
climbing period, its profitability gradually improves. The reasons for the profit and
loss characteristics are as follows.

1. Large Investment, Long Period of Return, and High Risk in Industry

Taking the production line construction as an example, the investment of 65 nm

production lines with a monthly capacity of 50,000 pieces of 300 mm is about
3 billion US dollars, and the investment of 32 nm/28 nm production lines is even
5 billion US dollars [16]. Besides the huge investment in the early stage, it will take a
long time to achieve large-scale production and generate benefits. In addition,
enterprises need to continue to invest a large number of R&D personnel and capital
23 Development Law and Development Index of IC Industry 501

to improve their technical expertise; otherwise, they will be gradually squeezed out
of the historical stage because of backward technology. The above two kinds of
investment are indispensable, which intensifies the investment risk.

2. Greater Depreciation and Amortization of Fixed Assets (Equipment, Plant

Construction)

Integrated circuit wafer manufacturing enterprises are typical asset-heavy enter-

prises, whose capital expenditure such as Depreciation and Amortization accounts
for a large proportion. Take the integrated circuit manufacturing company SMIC as
an example, referring to the Financial Statement of CITIC International in 2016, its
annual revenue is about 2.914 billion US dollars, the gross margin is about 850 mil-
lion US dollars, and its sales cost is 2.064 billion US dollars (depreciation and
amortization is 729 million US dollars), that is to say, 35.32% of its cost is
depreciation and amortization items.
Compared with asset-heavy enterprises such as integrated circuit manufacturing,
the impact of depreciation and amortization on fixed assets in light-asset companies
such as IC design companies is minimal. According to the financial report of
Broadcom in 2016, its annual revenue was about 13.24 billion US dollars, gross
profit was about 5.94 billion US dollars, and sales cost was 5.295 billion US dollars.
Among them, the depreciation and amortization amount was 763 million US dollars,
accounting for 14.4% of its sales cost, which is much lower than the depreciation and
amortization cost of IC manufacturer SMIC.
The capital expenditure of IC manufacturing enterprises mainly includes the expen-
diture of plant and equipment. Equipment expenditure generally accounts for 80% of
capital expenditure, while land, plant, and other expenditures account for about 10%.
In addition, fluctuations in product prices and sales may also affect the profit and
loss situation of wafer manufacturing enterprises. Non-hedging is a common feature
of electronic products. According to Moore’s law, advanced technology products of
integrated circuits are renewed every 2 years or so. The new technology products
that are updated first not only have a high profit margin, but also correspond to a
large amount of market demand. This huge market demand and corresponding profit
margin can make each manufacturer continuously expand the production capacity of
more advanced products during the industry’s upward cycle. However, with the
increased number of IC companies that have made technological breakthroughs, the
price of this kind of products will drop dramatically. Considering the market
competition factors, all but the most advanced companies in the industry have
very little profit margins.

Shareholder Structure of IC Foundry

IC foundry companies have their unique share-hold structure, that is, upstream
and downstream companies cannot hold a controlling stake in it. In the face of
all design enterprise customers, foundry companies must maintain their absolute
502 T. Feng et al.

independence in area of intellectual property. If an IC design company or a group

of industrial capital with a design department enters the foundry field,
this foundry field will lose customers because customers will doubt the
independence.
This also makes it hard for a specific capital to hold a large proportion of foundry
enterprises, especially a design enterprise or a group industrial capital with a design
department and vice versa. In order to ensure the intellectual property security of
design enterprises, the corporate governance (equity design) of the foundry enter-
prises is highly selective. Otherwise, foundry enterprises will lose their indepen-
dence in this industry mode, thus losing the market (customer), and eventually
diminish.
In addition to protecting the intellectual property rights of customers (design
companies), OEMs also pay great attention to the protection of their own intellectual
property rights in the case of founding factory offshore. At present, international
competitive IC companies have invested in wholly-owned enterprises in mainland
China, including Samsung and Intel. These companies adopt this model mainly
because they are worried about the loss of core technology and thus lose their
advantage in competition.
The protection of intellectual property rights from IC foundry enterprises can
be divided into three aspects: design companies, foundry companies, and indus-
trial chain partners. The intellectual property of customers and partners in the
industry chain is more important than that of others. Thus, to protect the intel-
lectual property of customers and industrial chain partners, foundry enterprises
must design their own shareholding structure to maintain their independence and
neutrality.

Prosperity Indicators of Statistics for IC Industry

In the study of the prosperity in IC industry, three statistical indicators are generally
used: B/B ratio, capacity utilization rate, and WSTS forecast. The B/B (book-to-bill)
ratio is used to survey the upstream purchasing situation of IC enterprises, serving as
an ex-ante indicator. The capacity utilization rate is for studying the equipment
utilization rate in IC enterprises, serving as an intermediate indicator. The WSTS
forecast is used to investigate the income purchased from IC enterprises by down-
stream clients, serving as an ex-post indicator. The interaction between the three
forms a system of statistical indicators to measure the prosperity of IC industry. The
B/B ratio is discussed in detail in Sect. 1.
The capacity utilization rate refers to the utilization efficiency of the produc-
tion equipment capacity in IC manufacturing enterprises. Due to that the cost of
equipment purchases accounts for a large proportion of the total investment in an
IC manufacturing enterprise, it will directly affect the productively beneficial
level of the manufacturing enterprise whether the equipment capacity can be fully
23 Development Law and Development Index of IC Industry 503

utilized. From a micro perspective, the capacity utilization rate reflects the busy
degree of the equipment in the manufacturing enterprise. From the macro point of
view, it indirectly reflects whether the downstream demand is high enough.
Generally speaking, a capacity utilization rate above 90% indicates the strong
downstream demand for the design of chips, and the industry is in a period of
prosperity, which typically prompts the manufacturing enterprise to build new
production lines.
WSTS collects and processes the monthly sales data from its member companies
to sort out and analyze them, while making predictions for the future. Since WSTS’
data is directly from each member enterprise, WSTS’ periodic statistics and forecast
is already beyond the scope of indirect indicators and are more similar to a large-
scale survey. With certain authority, it has become one of the statistical indicators to
judge the prosperity in global IC Industry.

Prosperity Indicators of Securities for IC Industry

Two indicators of securities, the PHLX Semiconductor Sector Index (SOX) and the
Taiwan Stock Exchange Semiconductor Index (TWSESCI), are typically used for
reference to assess prosperity of the IC industry.

1. SOX

SOX is one of the main indicators reflecting the prosperity of the global IC
industry, which is the stock price weighted option index. The SOX index was
established on December 1, 1993, and was listed for trading since September
7, 1994, under the option index symbol SOX. By the end of 2016, SOX was
composed of the stock prices of 23 companies primarily involved in manufacturing,
design, equipment, and distribution in the semiconductor industry. The list of
enterprises is shown Table 23.4.

2. TWSESCI

Similar to SOX in nature, TWSESCI is an industrial data indicator that reflects

stock prices and market value of semiconductor enterprises listed in Taiwan, based
on the change of stock prices. The indicator adopts June 29, 2007, as the base date
and 100 as the base index, and has been released since July 1, 2007.
IC giants listed in Taiwan include TSMC, MTK, ASE, UMC, and SPIL. The
stock prices for all semiconductor companies listed on Taiwan Stock Exchange are
included in TWSESCI’s assessment. Because the capacity of IC industry in Taiwan
ranks among the top in the world, TWSESCI, similar to SOX, is one of the important
reference indicators reflecting the prosperity of the regional IC industry and even the
global IC industry.
504 T. Feng et al.

Table 23.4 List of SOX enterprises

No. Securities Code Enterprise Name Chinese Name
1 SWKS Skyworks Solutions Inc. 思佳讯
2 AVCO Broadcom Limited 博通
3 ON On Semiconductor Corp 安森美
4 MXIM Maxim Integrated Products Inc. 美信
5 МСНР Microchip Technology Inc. 微芯
6 CREE Cree Incorporated 科锐
7 TSM Taiwan Semiconductor Manufacturing 台积电
8 LRCX Lam Research Corp 泛林
9 TXN Texas Instruments Inc. 德州仪器
10 MU Micron Technology Inc. 美光
11 INTC Intel Corp 英特尔
12 CAVM Cavium Networks Inc. -
13 TER Teradyne Inc. 泰瑞达
14 ADI Analog Devices Inc. 亚德诺
15 KLAC KLA-Tencor Corp 科天
16 AMAT Applied Materials Inc. 应用材料
17 ASML ASML Holdings 阿斯麦
18 LLTC Linear Technology Corp 凌力尔特
19 XLNX Xilinx Inc. 赛灵思
20 MRVL Marvell Technology Croup 美满
21 NXPI NXP Semiconductors 恩智浦
22 NVDA NVIDIA Corporation 英伟达
23 QCOM Qualcomm Inc. 髙通
Note: After Avago acquired Broadcom for a price of 37 billion US dollars, the newly formed parent
company was named Broadcom.

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9. Z. Zhou, Research on investment and financing of chinse IC Industry (Publishing House of
Electronics Industry, Beijing, 2015), pp. 7–24
10. F. Liu, A comparative study of patent systems in ASEAN countries. Intellectual Property 15(1),
51–57 (2015)
11. Z. Zhou, Promoting the accelerated development of IC industry with supply-side reform.
Review of Industrial Economics, 5–8 (2016). https://doi.org/10.19313/j.cnki.cn10-1223/f.
2016.01.001
12. Z. Zhou, analysis on the situation and development characteristics of IC industry. Review of
Industrial Economics 4, 5–9 (2014). https://doi.org/10.19313/j.cnki.cn10-1223/f.2014.06.001
13. Z. Zhou, Research on Investment and Financing of Chinse IC Industry (Publishing House of
Electronics Industry, Beijing, 2015), pp. 131–136
14. D. Mo, The dream of electronics memory in Taiwan broken, http://www.elecfan.com/article/90/
156/2017/0109471445.html?148394373. Accessed 01 09 2017
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com/content/17/0203/11/30123241_626174512.shtml. Accessed 02-03-2017
16. Z. Zhou, Research on investment and financing of chinse IC industry (Publishing House of
Electronics Industry, Beijing, 2015), pp. 61–73
17. Capital expenditures based on NAICS 3344 (semiconductors and other electronic component
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www_censusgov/programs-surveys/acms_html_ .Accessed. 03-15-2017
18. Z. Zhou, Research on Investment and Financing of Chinse IC Industry (Publishing House of
Electronics Industry, Beijing, 2015), pp. 61–64
19. M. He, Research on International Competitiveness of Integrated Circuit Industry in Mainland
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html. Accessed 03 15 2017
21. M.D. Platzer, G. J. Harrison, 2016. The U. S. automotive industry: National and state trends in
manufacturing employment. Washington, DC: Congressional Research Service [OL /666, press
release June 27.
Financial Management Practice
and Analysis of Enterprises 24
Ying Cai, Yuwen Xue, Yanlun Yan, and Jianyue Pan

Contents
Financial Statements and Analysis Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Balance Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Income Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Cash Flow Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Capital Expenditure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Shipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Market Share . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Product Category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Gross Margin Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Depreciation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
EBITDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Other Financial Indexes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
Price-to-Earnings Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Goodwill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Equity Incentive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Abstract
Common indexes, concepts, and indicators of financial management practices,
and analysis of enterprises, are introduced in this chapter. An overview is
presented to describe financial statement, the most important tool used to observe
and analyze the financial situation of a company. The key financial indexes
frequently used to study IC enterprises, like CAPEX, profit and earning, depre-
ciation, and R&D are discussed. Common concepts that will be used in IC
enterprises management reports or market reports are introduced, like shipment,

Y. Cai (*) · Y. Yan · J. Pan

Summitview Capital, Beijing, China
e-mail: caiying@summitviewcapital.com
Y. Xue
Zhongjing Industrial, Xi’an, China

© Publishing House of Electronics Industry 2024 507

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_24
508 Y. Cai et al.

ASP, market share, and product category. Three special topics are introduced:
Price-to-Earnings ratio is one of the most fundamental indicators to analyze
enterprise’s valuations; Goodwill frequently arises from mergers and acquisi-
tions; Equity incentive is an effective complement to a company’s salary system,
especially for IC enterprises.

Keywords
Financial statement · Profit · Depreciation · Market share · ASP · Price-to-
earnings · Equity incentive

Financial Statements and Analysis Methods

When we observe and analyze the financial situation of a company, the most
important tool is the company’s financial report, including financial statements and
related information disclosed at the same time (generally presented in notes). The
financial statements should include at least three major statements, these are Balance
Sheet, Income Statement or Profit and Loss Statement, and Cash Flow, which are
referred as “Three statements.” In some smaller companies or start-ups, the reporting
structure is simpler and sometimes does not include the cash flow statement. The
financial statements prepared by the enterprise that fully implements the enterprise
accounting standards shall also include the Statement of Stockholders Equity.

Balance Sheet

Balance sheet is an accounting statement that reflects a company’s financial situation

at a particular date. The purpose of a balance sheet prepared by a company is to
faithfully reflect the amount of assets, liabilities, and owner’s equity and its structure,
in order to help users evaluate the quality of corporate assets and short-term
solvency, long-term solvency, and profit distribution capacity. For IC enterprises,
special attention should be paid to items such as accounts receivable, inventory,
intangible assets, goodwill, accounts payable, short-term loans, and long-term loans.
In addition, as for IC manufacturing enterprises and packaging enterprises that invest
heavily in capital expenditures, more attention should also be paid to fixed assets,
projects under construction, long-term prepaid expenses, and other projects.

Income Statement

The income statement is an accounting statement that reflects the business results of
the company during a certain accounting period. The purpose of preparing the
income statement is to faithfully reflect the income made by the enterprise, the
expenses incurred, the gains and losses that should be included in the current profit,
24 Financial Management Practice and Analysis of Enterprises 509

and other comprehensive income and its structure, and to help users analyze and
evaluate the profitability, the composition, and the quality of the company [1]. For IC
companies, most should be concerned about operating income, operating costs,
operating expenses (selling expenses, general and administrative expenses, financial
expenses, as well as research and development expenses), operating profits, net
profits, as well as the proportion of various costs, expenses, and profits to revenue,
that is, gross profit margin, operating profit margin, net profit margin, etc.
The cost of research and development (R&D) is also a kind of operating expense.
In technology-intensive industry, IC companies generally invest more in R&D. R&D
expenditure directly reflects the investment of IC companies in technology, which
also provides the opportunities for IC companies to gain technology competitive
advantages in the future. According to the “Accounting Standards for Business
Enterprises” formulated by the Ministry of Finance of China: the expenditures of
R&D projects within an enterprise should be divided into the research phase and the
development phase. The expenditures in the research phase should be recorded in the
current profit and loss, that is, the income statement. When certain conditions are
met, the expenditure in the development phase can be recognized as intangible assets
and capitalized, which can be amortized through intangible assets without affecting
the current profit and loss [2]. At present, the processing of R&D expenses of
China’s corporate accounting standards has adopted the treatment methods of
International Financial Reporting Standards (IFRS). However, in the United States
Generally Accepted Accounting Principles (US GAAP) the R&D expenses are not
allowed to be capitalized and should be recorded in the R&D expenditure under the
operating expenses of income statement. Attention should be paid to the impact of
differences led by accounting standards in comparing R&D expenses and profitabil-
ity of IC companies among various countries.

Cash Flow Statement

The cash flow statement is an accounting statement that reflects the inflows and
outflows of the company’s cash and cash equivalents during a certain accounting
period. The purpose of preparing the cash flow statement is to faithfully reflect the
cash inflows and outflows of various activities of the company, and to classify three
activities of operation, investment, and financing according to their purposes, so as
to help users to evaluate the cash flow and capital turnover of the enterprise [1]. For
IC manufacturing enterprises and packaging enterprises, the depreciation of fixed
assets cannot be recognized as cash outflow, but under accrual basis and matching
principle, the acquisition costs of these assets should be reasonably amortized during
the beneficial period in which they are used, though with no cash actually paid. Same
as EDA tools and purchased IP, for IC design companies, they are generally
amortized as intangible assets with no cash outflows. Therefore, although the IC
enterprise may have a negative net profit in the income statement due to huge
depreciation and amortization expenses, its actual positive cash flow can still ensure
the company continues to operate normally.
510 Y. Cai et al.

In practice, the analysis of financial statements mainly adopts the financial ratio
method, comparative method, and factor analysis method. The financial ratio method
determines the ratio by comparing the relevant data of several important items on the
same financial statement to determine the ratio, which mainly evaluates the
company’s profitability, solvency, growth ability, and turnover ability. The compar-
ison method can be made with the company’s history (vertical comparison), with
similar companies (horizontal comparison), or by budget ratio (budget difference
analysis). The factor analysis rule is based on the mutual driving factors between the
indicators to quantitatively analyze the degree of mutual influence between the
factors. In addition, special attention should be paid to the notes (or appendixes)
section of the financial statements, where key factors and events affecting a specific
indicator are often disclosed, as well as many details of a company’s operations,
which are indispensable information sources about the company’s financial
situation.

Capital Expenditure

Capital Expenditure (CAPEX) refers to the expenditure incurred while purchasing or

upgrading physical assets such as equipment, factories, and production lines by the
enterprise to maintain current performance and develop new businesses. It also
reflects the management team’s opinions on the future market and the future
direction of development. Since the benefits brought by these expenditures will
last for several years, instead of being attributed to a single fiscal year, capital
expenditures need to be capitalized and divided into multiple financial statements
in the form of depreciation of fixed assets and amortization of intangible assets. The
Table 24.1 shows the comparison among capital expenditures, cash from operations,
and net income of mainstream integrated circuit enterprises in the most recent fiscal
year.
Overall, the pattern of capital expenditure is strongly related to the asset portfolio
IC enterprises:
For IC design enterprises, their fixed assets account for a relatively low propor-
tion, and the capital investment required for daily operation is also small. Their
capital expenditures concentrate in design-related fields such as tools and simulation
experiments. For example, Nvidia’s operating cash flow in 2021 was US$9.11
billion, and its net profit was US$9.75 billion. Its CAPEX was US$980 million,
accounting for 10.76% of total operating cash flow and accounting for 10% of net
profit.
For IC manufacturing enterprises, factory facilities and production equipment are
huge fixed assets. They require a massive amount of initial investment as well as
long-term follow up cash inflow for upgrade and expansion from time to time. Also,
maintenance, replacement, and relative facilities, as well as the training of workers
also consume a substantial amount of funds. Take TSMC as an example. In 2021,
operating cash flow was $40.13 billion; capital expenditures reached $30.28 billion,
that is, more than its full-year net profit.
24 Financial Management Practice and Analysis of Enterprises 511

Table 24.1 Comparison of capital expenditure, net profit, and total income of mainstream listed
Integrated Circuit Companies in 2021 ($B)
Cash from Net Capital Fiscal year
Classification Enterprise operations income expenditure end datea
IC design Qualcomm 10.54 9.04 1.89 9/26/2021
Broadcom 13.76 6.74 0.44 10/31/2021
Nvidia 9.11 9.75 0.98 1/30/2022
MTK 1.70 4.02 0.61 12/31/2021
AMD 3.52 3.16 0.30 12/25/2021
Integrated device Intel 29.99 19.87 20.33 12/25/2021
manufacturing TI 8.76 7.77 2.46 12/31/2021
Micron 12.47 5.86 10.03 2/9/2021
IC foundry TSMC 40.13 21.37 30.28 12/31/2021
SMIC 3.01 1.70 4.12 12/31/2021
UMC 3.26 2.01 1.73 12/31/2021
IC packaging and ASE 2.95 2.31 2.56 12/31/2021
testing Amkor 1.12 0.64 0.78 12/31/2021
Changdian 1.17 0.47 0.69 12/31/2021
Equipment Lam 3.10 4.61 0.55 6/26/2022
ASML 12.33 6.69 1.02 12/31/2021
AMAT 5.44 5.89 0.67 10/31/2021
Note: aThe exchange rate is the exchange rate at the end of the fiscal year

Table 24.2 Worldwide semiconductor capital spending and equipment spending forecast,
2016–2020 ($Million)
2016 2017 2018 2019 2020
Global semiconductor capital spending 679.9 699.4 736.1 783.6 758.0
Wafer-level manufacturing equipment 358.6 380.1 384.9 417.8 398.3
Wafer fab equipment 340.3 359.8 362.4 392.7 372.5
Wafer-level packaging and assembly equipment 18.3 20.3 22.5 25.1 25.7
Source: Gartner

In the short term, capital expenditures reflect the company’s plans for its business
development. Except for the equipment replacement and production line iteration for
maintaining the existing business, the company’s investment in developing new
products shows its vision and deployment for the future business. Generally, emerg-
ing enterprises will regard the CAPEX more significant than their net profit. Large,
established enterprises might also want to push up spending amount as they enter a
new business area, such as TSMC and SMIC in the above table.
Moreover, changes in capital expenditures can reflect future recessions or recov-
eries of the entire industry. For example, Table 24.2 showed Gartner’s January 2017
forecast for the global semiconductor industry’s overall capital expenditure by 2020.
Gartner believed that from the perspective of capital expenditure, the semiconductor
industry would remain its growth till 2019 and would decline in 2020. Basically,
512 Y. Cai et al.

Gartner’s previous report has shown a right trend of the global semiconductor
industry’s capital expenditures.
China’s IC industry is in a period of rapid development. This can be seen in the
growth of the Capital Expenditure of packaging and assembly enterprises over the
past 5 years, as shown in Table 24.3.

Shipment

Shipment (or sales volume) refers to the quantity of products that an enterprise sells
to its direct customers and agents (or intermediaries). Considering the factors of
inventory, the quantity of shipment may be larger or smaller than product’s output.
From a macro point of view, the global semiconductor product shipments reflect
the development trend of the whole industry in terms of the quantities of products.
According to IC Insights forecast in April 2021, global semiconductor unit
shipments will grow 13% in 2021 to 1135.3 billion (1.1353 trillion) units in
2021to set a new all-time annual record. It would mark the third time that semicon-
ductor units have surpassed one trillion units in a calendar year – the first time being
in 2018. Global semiconductor unit shipments include ICs and optoelectronics,
sensors, and discrete (O-S-D) devices. Starting with 32.6 billion units in 1978, the
compound annual growth rate for semiconductor units is forecast to be 8.2% through
2021. Given the cyclical and often volatile nature of the semiconductor industry, this
is a very impressive growth figure over 43 years for such a long period of rapid
growth coming from a virtuous circle formed by the interaction between the semi-
conductor industry’s technological development and global economic demand [3].
The strong CAGR also demonstrates that new market drivers continue to emerge,
driving the demand for more semiconductors (Fig. 24.1).
For IC design companies, IDMs, and packaging and testing companies, the
product form is the chip that has been cut and packaged, so the shipment is counted
by “units” (or “pieces”) of the chips. Generally, IC design companies ship on the
order of one million pieces, so the industry often uses KK (million) as the unit of
chip shipments. The analysis of the production unit and sales unit of GigaDevice in
2021 is shown in Table 24.4.
For IC foundry companies and package and testing companies that provide wafer
level packaging (WLP), their shipments are based on the number of wafers in units
of “pieces.” Wafers come in different sizes. The size number represents the diameter
of the wafer. Generally, when doing statistics, a wafer of one size can be converted to
another wafer size according to the proportion of the actual area of the wafer.
Commonly industry tends to convert to 200 mm wafers or 300 mm wafers as the
base unit.
Take TSMC as an example. The unit of shipments announced in the TSMC
annual report started to use 300 mm wafer as the benchmark from 2013, and other
wafer sizes will be converted to 300 mm equivalent wafers. Before 2013, the units
were based on 200 mm wafers. This change reflects the transition of TSMC’s main
production platform from 200 mm to 300 mm.
 24

Table 24.3 China’s major integrated circuit manufacturing and packaging and testing enterprise Capital Expenditure (RMB Million)
Company 2014 2015 2016 2017 2018 2019 2020 2021
SMIC 4050.7 7991.0 19144.4 14882.2 12436.6 13017.6 34436.3 26174.5
Hua Hong semiconductor 471.7 1181.1 1171.3 898.5 1580.7 6421.8 7098.3 5964.5
Jiangsu Changdian technology 1190.4 2363.5 4768.2 4284.1 4311.1 2803.6 3330.4 4358.2
Nantong Fujitsu microelectronics 663.7 1251.1 1561.5 1656.5 2230.8 2108.8 3630.0 6405.1
Huatian technology 599.5 897.4 1484.6 1800.1 1635.9 1955.7 3044.7 5535.0
Financial Management Practice and Analysis of Enterprises
513
514 Y. Cai et al.

Fig. 24.1 Global semiconductor unit shipment. (Source of data: IC Insights, April 7, 2021)

Table 24.4 Analysis of Main products Production Shipment Inventory

the production and sales of
Memory chip 3520.9 3288.3 337.3
GigaDevice in 2021 (Unit:
million/KK) Micro controller 474.0 394.5 89.5
Sensor 193.8 164.5 53.1
Data source: Annual report of GigaDevice in 2021

The average selling price (ASP) of a product can be calculated by dividing the
revenue of the product by the volume of shipments of the product, meanwhile a
company’s ASP can be calculated in this way too. Table 24.5 lists TSMC’s ASPs
from 2013 to 2021. TSMC maintained continuous growth of wafer ASP together
with the continuous growth of total shipment volume and wafer revenue. This
reflects the improvement of ASP brought by the higher proportion of wafers in the
advanced process of TSMC.
The vertical and horizontal comparison of ASP is an important reference to
analyze the overall IC market trend and the market position of a certain product or
a certain company.

Market Share

Market share is the percentage of total sales (or sales) that a particular entity accounts
for in a market. This index is used to describe the entity’s influence over the market
during a certain period of time.
From a global macro perspective, the market of integrated circuits can be divided
by regions to observe the industrial strength of different areas. Take the IC design as
an example. In 2021, the global IC design industry sales volume was 177.7 billion
US dollars, of which the US-based design companies had a market share of 68%; the
Taiwanese design companies had a market share of 21%. The fastest-growing market
share was in China, where it almost doubled compared to 2010. Table 24.6 shows the
market share of IC design in different countries/regions. Compared with 2010,
 24

Table 24.5 TSMC 2013–2021 shipment and ASP

Year 2013 2014 2015 2016 2017 2018 2019 2020 2021
Total shipment 6963 8263 8763 9606 10,449 10,752 10,068 12,398 14,179
Unit: convert to 300 mm equivalents in thousand
Wafer revenue 561 724 803 861 875 911 927 1178 1405
Unit: Billion NTD
Wafer ASP 80,526 87,583 91,624 89,649 83,784 84,756 92,105 95,052 99,111
Unit: NTD
Financial Management Practice and Analysis of Enterprises
515
516 Y. Cai et al.

Table 24.6 Market share Country/Region 2010 2021

in different regions of the
USA 69% 68%
global IC design industry [4]
China Taiwan 17% 21%
China Mainland 5% 9%
Japan 1% 1%
Europe 4% <1%
Other 4% <1%

Table 24.7 Top 10 analog IC suppliers of 2021 [5]

2021 Rank Company 2020 2021 % Change % Market share
1 Texas Instruments 10,886 14,050 29% 19%
2 Analog Devices 7722 9355 21% 12.7%
3 Skyworks Solutions 3970 5910 49% 8%
4 Infineon 3820 4800 26% 6.5%
5 ST 3259 3906 20% 5.3%
6 Qorvo 3182 3875 22% 5.2%
7 NXP 2466 3457 40% 4.7%
8 On Semi 1606 2115 32% 2.9%
9 Microchip 1520 1839 21% 2.5%
10 Renesas 890 1110 25% 1.5%

Europe’s market share in the global IC design industry has decreased, mainly
because the second-largest IC design company CSR got acquired by Qualcomm in
2015; and Lantiq, Germany’s third-largest IC design company, was merged by Intel
in 2015. Among the IC design companies in other regions, Singapore-based
Broadcom (formerly known as Avago) has become the world’s second-largest IC
design company through continuous mergers and acquisitions. It is now counted in
the US region, so the market share of “other regions” has reduced.
From an enterprise’s perspective, market share refers to the proportion of its
products sold in the market of the same products. Thus, the definition of scope
affects the result. For instance, if we consider all IC products as being in the same
market, then Intel’s CPU only take a small share; but if we only screen the personal
computer CPUs, then Intel’s CPU takes up to 80% of the market share.
Commonly, we analyze the market share of IC enterprises based on specific
market segments. Table 24.7 shows the top 10 enterprises’ market share in the
global analog IC market in 2021, according to IC Insights report. The analog IC
market is in a stable annual growth period. As a result, we do not see much changes
in rankings in recent years, except some enterprises’ growth might come mainly
from their mergers and acquisitions. The whole market size is $73.9 billion, and the
top 10 vendors accounting for 68% of the market share. With analog sales of $14.1
billion and 19% market share, Texas Instruments maintained its firm grip as the
world’s leading supplier of analog devices in 2021. TI’s 2021 analog sales increased
nearly $3.2 billion or 29% compared to 2020. In second place, the analog IC sales of
Analog Devices, Inc. (ADI) in 2021 increased 21% to $9.36 billion, accounting for
24 Financial Management Practice and Analysis of Enterprises 517

13% market share. Meanwhile, ADI completed its $28.0 billion acquisition of
Maxim Integrated products in August 2021. Ranked third in 2021 with analog
sales of $5.9 billion was Skyworks Solutions, whose 49% jump in revenue was
the largest percentage increase among the top analog suppliers in 2021. In July 2021,
Skyworks acquired the Infrastructure and Automotive business of Silicon Labora-
tories Inc. for $2.75 billion to accelerate its expansion into electric and hybrid
vehicles, industrial and motor control, 5G wireless infrastructure, optical data com-
munication, data center, and other applications. The three major IC suppliers in
Europe – Infineon, ST, and NXP – are all in the top 10 analog supplier in 2021.
Together, the three companies accounted for 16% of global market share.
Market share reflects the competitiveness of enterprises and increasing market
share is often one of the most important goals of business operations. As the industry
grows, enterprises that grow at the same rate as the total market maintain their market
share, whereas increased market share requires companies to grow faster. As can be
seen from the example above of the MCU market, in addition to increasing the sales
of products more quickly than the whole market, enterprises can also increase market
share by acquiring other businesses to achieve more significant share.
Driven by its huge domestic demand, China’s IC industry market share around
the world has proliferated. The industry grows with the development of the market.
China is now the world’s largest IC consumer market. Accompanying with it, the
total consumer market of electronic information products is moving toward the Asia-
Pacific region, with enterprises establishing and supply chains forming up in China,
South Korea, and India. Recently China has become the world’s largest smartphone
market, together with the boom of Huawei’s mobile chips taking account for more
and more market share. Although Huawei has made great efforts in product design
and development, being close to the supply chain, meeting local policy requirements
has also contributed to its rapid growth. At the same time, large overseas integrated
circuit manufacturers have carried out new plans in the Asia-Pacific region to seek
the advantage of being close. Examples include Samsung has invested 7 billion US
dollars in Xi’an High-tech Zone to build a memory chip project, and Hynix has been
investing in Wuxi since 2005.

Product Category

According to the statistical methods of the World Semiconductor Trade Statistics

(WSTS) Organization, the structure of semiconductor products can be divided into
IC, optoelectronic devices, sensors, and discrete devices (O-S-D) according to the
device types. ICs can be divided into analog IC and digital ICs. And digital ICs are
divided into processor, memory, and logic products, with each category continuing
to be subdivided. A summary of WSTS global semiconductor product structure and
its 2021 market size is shown in Fig. 24.2.
For IC design companies and IDM companies, their product structure generally
refers to a certain subdivision of chip categories. GigaDevice divides its products
into two main categories: memory chips and microcontrollers (see Table 24.4). In IC
518 Y. Cai et al.

Fig. 24.2 Global semiconductor product structure and its market size in 2021 (unit: billion US
dollars)

industry, there are companies specializing on a certain field, such as Intel in CPU,
Samsung, SK Hynix, and Micron in memory; there are also companies with a wide
range of product structure covering various areas, such as STMicroelectronics,
which have strong capabilities in sensors, analog IC, power devices, MCU, NFC,
etc. To analyze the market competitiveness of IC enterprises, we should not only pay
attention to the market share, technical capability, and future product plan of its main
product lines in the corresponding market segments, but also pay attention to the
synergies between different product lines.
For IC manufacturing foundry companies, usually their product structure is not
divided according to the chip types, but by the process types and process nodes. For
mainstream foundry companies, a wide range of process types and advanced process
nodes are key to their ability to capture customers. According to the process node,
SMIC’s product structure is shown in Fig. 24.3. Compared with 2010, 40/45 nm and
FinFET/28 nm products were added to the catalog, while the proportion of 65 nm
and products with more advanced process increased from 5% to 59.3% in 2021.
There are also some special-process foundry companies focusing on special process
areas involved with few mainstream foundries. In spite of small scales, they are
relatively stable, such as the WIN semiconductors in Taiwan on gallium arsenide
(GaAs) process have been profitable more than a decade.
For IC packaging and testing companies, their product structure is mainly divided
according to the type of package that can be provided. The types and capabilities of
package types that foundry companies can provide are the key to acquiring cus-
tomers. The product structure of Siliconware Precision Industries Co., Ltd. (SPIL,
merged by ASE in 2018) by packaging type is shown in Fig.24.4. In the first quarter
of 2017, the products of SPIL were divided into substrate-based packaging, lead
frame-based packaging, bumping and flip chip packaging and testing. The
24 Financial Management Practice and Analysis of Enterprises 519

Fig. 24.3 SMIC product structure by process node (2010 and 2021). (Source: 2010 and 2021
public financial reports of SMIC)

Fig. 24.4 Product structure of SPIL by package type (the fourth quarter of 2010 and 2017).
(Source: 2010 and 2017Q4 public financial reports of SPIL)

significant increase in bump and flip chip packaging compared with the fourth
quarter of 2010 was the result of meeting customer demands and adapting to the
development trend of packaging technology.

Gross Margin Rate

Gross margin rate is the percentage of gross profit to revenue (or sales).

Gross margin rate ¼ Gross profit=revenue  100%

¼ ðSales  Direct cost of salesÞ=sales  100%
520 Y. Cai et al.

In IC industry, gross profit margin is an important financial indicator, reflecting

the initial profitability of an IC company. It is the starting point for the net profit of an
IC company. For an IC company, to maintain a certain gross margin rate is very
important to achieve net profit. There are two ways for IC companies to increase
their gross margin rates. First, they can improve ASP (Average Selling Price) by
improving product competitiveness, such as improving product performance and
integrating new functions. Second, reduce the direct cost of products, either by
scaling up production to reduce the average fixed cost per product, or by reducing
raw material procurement costs and optimizing the supply chain to reduce variable
costs.
The level of gross margin rate is highly correlated with the industry in which the
company operates. In different segments of IC industry chain, the level of gross
margin rate varies. Essentially, the gross margin rate reflects the value-added part of
commodities after it has been converted to production. In other words, whichever
industry or segment has more added value, it will have higher gross margin rate. On
average, the sequence of gross margin rate of IC industry is ranked as followed: IC
design companies > IC manufacturing companies > IC packaging and testing
companies. As for the supporting segments, the IC equipment and materials industry
have high entry barriers and have been highly concentrated, so they have high gross
margin rate.
The gross margin rates of major IC companies in the world in FY2021 are shown
in Table 24.8. Although the gross margin rate is affected by the industries and
segments, there are still large differences in the gross margin rate among companies

Table 24.8 Gross margin rate of the world’s major IC companies in FY2021
Classification Enterprise GM% Fiscal year end date
Design Qualcomm 57.5% 9/26/2021
Broadcom 73.9% 10/31/2021
Nvidia 64.9% 1/30/2022
MTK 46.9% 12/31/2021
AMD 48.2% 12/25/2021
Integrated device manufacturing Intel 55.4% 12/25/2021
TI 67.5% 12/31/2021
Micron 37.8% 9/2/2021
Foundry TSMC 51.6% 12/31/2021
SMIC 30.8% 12/31/2021
UMC 33.8% 12/31/2021
Packaging and testing ASE 19.4% 12/31/2021
Amkor 20.0% 12/31/2021
Changdian 18.1% 12/31/2021
Equipment Lam 45.7% 6/26/2022
ASML 52.7% 12/31/2021
AMAT 47.4% 10/31/2021
Source of data: Public financial report of the companies listed in the table
24 Financial Management Practice and Analysis of Enterprises 521

in the same industry segment. Leading companies of an industry usually obtain

considerable profits of the industry, resulting to the lower gross margin rate of the
rest of the companies.
IC design companies with high sales revenues have large market share, and hence
have a great voice in product pricing. IC design companies with large sales revenue
have strong bargaining power to IC manufacturing, packaging, and testing, and a
lesser cost of design tools allocated to each product, so their ability to control
production costs is superior to small companies. Therefore, leading companies
with large sales revenues have higher gross margin rates.
The gross margin analysis of an IC company can be carried out based on business
sectors, products, customers, sales areas, etc., depending on the purpose of the
analysis and the information available. It also can be compared horizontally with
companies in the same industry, or vertically study the historical changes in gross
margin rate. In addition, the simple high gross margin rate is not enough to support
the sustainable development of an IC company, the company also needs to consider
the combination of the company’s shipment volume, sales revenue, product plan-
ning, research and development capabilities, and other factors.

Depreciation

Depreciation is an accounting method that reallocates the costs of a tangible asset

over its lifetime. Since a reasonable amount of fixed asset lasts more than one fiscal
year, when calculating the net profit of business activities, enterprises must correctly
quantify the costs and expenses generated by the business activities after the
depreciation. There are usually two types of depreciation methods: Straight-line
method and Accelerated method. The Straight-line method means that the depreci-
ation is charged for the same amount in each accounting period. Accelerated method
means that the initial charges are larger and will be reduced gradually.
The enterprise will select a different depreciation period for different types of
assets based on its own needs, and the final depreciation expense will be the
combination. For example, TSMC generally adopts straight-line depreciation
method. The depreciation life of ground facilities is more than 20 years; the
depreciation life of buildings is 5–20 years; the depreciation life of machines and
equipment is 2–5 years; the office equipment is depreciated in 3–15 years, and the
leased fixed assets are amortized in 20 years.
The integrated circuit wafer manufacturing is a high risk industry with typical
scale effect. Historically, one can find out that the leading companies in wafer
manufacturing have taken almost all the cake, showing a pattern of “Winner takes
all.” Newcomers must reach a particular business scale before they can generate
enough income to self-sustain. On the other hand, the integrated circuit wafer
manufacturers also need to be continuously updated. The equipment cannot go
beyond technology nodes. As a result, manufacturers have to constantly replace
old product lines with new ones to stay competitive. For each new fab built, the cost
could reach tens of billions of dollars, according to 5–10 years of depreciation. That
522 Y. Cai et al.

is, the average cost per second is around 25–50 dollars (with or without income). At
the end of the depreciation, equipment usually cannot be used anymore because the
market demand should have changed. If the new process nodes become the main-
stream, it is necessary to consider selling the old equipment in advance.
For the newly built integrated circuit wafer manufacturing enterprises, they have
to experience high depreciation pressure brought by the large-scale initial investment
in the first few years. Currently, the revenues still continued to struggle at low levels.
Thus, the company might suffer for net losses for several years. As the production
capacity is released over time and new market shares are obtained, a positive
production cycle begins to be maintained. As revenue increases, the proportion of
depreciation to revenue will decrease, yet it still depends on the enterprise’s subse-
quent investment of the business. In the case of SMIC as shown in Fig. 24.5, the
percentage of depreciation to operating revenue is quite high at the beginning of its
establishment, ranging from 46% to 72% between 2003 and 2009. In the past 9 years
(2013 to 2021), as SMIC’s operating revenue continued to rise, the major equipment
has also passed the depreciation period, and its depreciation accounted for 23–35%
of its operating revenue. The enterprise maintained the continuous profitability.
Some well-developed integrated circuit wafer manufacturers, after expansion to a
certain extent, almost no longer make any production capacity and technology
investment. Then, after all depreciation is completed, the depreciation part of the
cost becomes zero or a small number. At this time, the profit level of the enterprises
will be improved. However, in the long run, no capital expenditures will make the
company’s production capacity and technology stand still, and the competitiveness
of enterprises will gradually decline, which will eventually lead to the decline in
profits and even losses.
For intangible assets, their costs need to be systematically amortized to each
accounting period in their useful life span. Amortization shall begin on the date on
which the intangible assets are available for a period but no more than 20 years. The
method of amortization should reflect how the enterprise consumes the economic
benefits of intangible assets. If the method cannot be reliably determined, the
straight-line method is used. Amortization for each period should be recognized as

Fig. 24.5 Trends in SMIC’s depreciation rate (data from SMIC’s 2004–2021 annual report)
24 Financial Management Practice and Analysis of Enterprises 523

an expense unless other International Accounting Standards allow or require it to be

included in the carrying amount of other assets.

EBITDA

Before discussing Earnings Before Interest, Taxes, Depreciation, and Amortization

(EBITDA), the relevant indicator Earnings Before Interest and Tax (EBIT) needs to
be firstly explained. In general, EBIT is referred to the operating profit reflecting the
operating results of the company’s main business. Since the interest expense and tax
are excluded, the company’s operating results will not be affected by the amount of
liabilities in the capital structure nor the income tax. EBIT could be calculated as the
prime operating revenue minus operating costs and operating expenses. Deprecia-
tion and amortization directly related to product manufacturing are included in the
operating costs.
EBITDA is based on EBIT and then added to back depreciation and amortization.
The calculation formulas for EBIT and EBITDA are as follows:

EBIT ¼ ðRevenue  Operating CostÞ  Operating Expenses

¼ Net Profit þ Income Tax þ Interest Expense

EBITDA ¼ EBIT + depreciation expense + amortization expense

¼ Net Profit þ Income Tax þ Interest Expense þ Depreciation Expense

þ Amortization Expense

Compared to net profit, EBIT excludes the income tax, interest, and other
operating revenue, which is convenient to analyze and compare the profitability of
the main business of same type enterprises with different income tax rates and
different capital structures. EBIT is also more comparable than net profit, while the
profitability of companies’ main businesses is analyzed vertically.
Since depreciation and amortization are included in the cost of acquiring equip-
ment or intangible assets in the previous accounting period, rather than the cash
outflows in the current period, EBITDA avoids the impact of various depreciation
policies and deprecation abnormalities on the operating performance of different
enterprises while EBITDA further eliminates depreciation and amortization on the
basis of EBIT. It should be noted that EBITDA cannot simply be equated with
operating cash flow. Since EBITDA does not consider the impact of factors such as
changes in inventory and current accounts on cash flow, and the calculation of
EBITDA does not exclude items such as asset impairment losses and investment
income, there is a certain difference between EBITDA and the net cash flow
generated by operating activities. However, EBITDA could be considered as an
inaccurate surrogate indicator of the company’s net cash flow from operating
activities.
524 Y. Cai et al.

EBIT is an indicator to present the profitability of a company’s main business,

while EBITDA is an indicator of a company’s ability to generate cash flow from the
main business. EBIT and EBITDA are highly valued indicators in enterprise man-
agement, mergers and acquisitions, as well as in the secondary market. The calcu-
lation of profits can be consistent by eliminating some factors in calculating profits,
which is convenient for analysis and comparison.
Since the IC industry is a capital-intensive high-tech industry, the depreciation
brought by the construction of capital investment in manufacturing capacity, or the
amortization of intangible assets brought by using IP and EDA tools, will affect the
profit statements of IC companies at different stages. EBITDA can be used to
measure management performance more objectively over a period of time. For
example, comparing early-stage companies and mature companies with stable
depreciation and amortization, their EBIT or net profit levels may vary greatly. It
is impossible to determine whether the difference comes from operation manage-
ment or depreciation and amortization. At this time, the differences and real opera-
tional performance of two companies could be reflected by comparing EBITDA.
EBITDA is an important parameter for the acquirer to acquire and evaluate the
acquisition target. The acquirer will choose applicable tax rate calculation method
and new capital structure to calculate the acquiree’s financial status. It means the
depreciation and amortization will be excluded, and the merger will be replaced by
an estimate of the acquiring company’s future capital expenditure.
With the increase of investment and mergers and acquisitions in IC industry,
investors need to understand the characteristics of the industry chain in which the
investment target is located. The establishment of a financial model and the reason-
able estimation of profitability are the key basis for making investment decisions.
Taking the industry of IC manufacturing, which requires long-term and high-
intensity capital investment as an example, depreciation and amortization caused
by large-scale initial investment at the beginning of the establishment of the enter-
prise is very likely to cause negative EBIT and net profit. At this point, the cash flow
of business activities must be positive, and EBITDA is a visual indicator in this
respect. However, as a return for the long-term investment of the company’s
shareholders, the net profit of IC manufacturing companies is still a key indicator
of business operations after the intensive investment period.
EBIT and EBITDA of world’s major IC companies’ annual financial reports for
FY2021 are shown in Table 24.9.

Other Financial Indexes

Other financial indexes include several categories: (1) CAPEX and OPEX; (2) Net
Asset; (3) ROE; (4) Net Income; (5) GAAP and Non-GAAP, as discussed below.

1. Operating Expenses: the cost incurred by the company for normal business
operations, usually referred to as OPEX. In contrast to capital expenditure
(CAPEX), OPEX is the continuous or consumable expenditure of the running
24 Financial Management Practice and Analysis of Enterprises 525

Table 24.9 EBIT and EBITDA of world’s major IC companies from annual financial reports of
FY2021
EBIT/ EBITDA/
EBIT Operating EBITDA Operating Fiscal year
Classification Company Billion $ income Billion $ income end date
Design Qualcomm 9.79 29% 11.37 34% 2021/9/26
Broadcom 8.68 32% 14.72 54% 2021/10/31
Nvidia 10.04 37% 11.22 42% 2022/1/30
MTK 3.90 22% 4.25 24% 2021/12/31
AMD 3.65 22% 4.06 25% 2021/12/25
Integrated device Intel 22.08 28% 33.87 43% 2021/12/25
manufacturing TI 9.02 49% 9.92 54% 2021/12/31
Micron 6.80 25% 13.01 47% 2021/9/2
Foundry TSMC 23.47 41% 38.47 67% 2021/12/31
SMIC 0.73 13% 2.50 46% 2021/12/31
UMC 1.86 24% 3.48 45% 2021/12/31
Packaging and ASE 2.24 11% 4.12 20% 2021/12/31
testing Amkor 0.77 12% 1.33 22% 2021/12/31
Packaging and Changdian 0.48 10% 1.03 21% 2021/12/31
testing
Equipment Lam 5.38 31% 5.72 33% 2022/6/26
ASML 7.43 35% 7.95 38% 2021/12/31
AMT 7.26 31% 7.65 33% 2021/10/31
Note: Exchange rate using the rate at the end of the fiscal year
Source of data: Public financial report of the companies listed in the table

enterprise. For example, the expense of purchasing a photocopier is capital

expenditure (CAPEX), while the cost of paper, ink, electricity, and maintenance
is an operating expense (OPEX).
Operating expenses usually consist of two parts. The first part is Research and
Development Expenses (R&D). The second part is Selling, General, and Admin-
istrative expenses (SG&A). To take part in the fierce competition of the integrated
circuit industry, an enterprise could try hard with low product price to get more
market share. Another way is to get ahead in technology. The enterprise’s
Research & Development expense is an indicator that directly reflects its invest-
ment in technology. Table 24.10 showed the top enterprise’s R&D expenses in
2017. Compared with other industries, the R&D expenses of integrated circuit
companies are considerable both in absolute numbers and as a percentage of
revenue.
SG&A (Selling, General, and Administration) represents the sum of the
company’s major non-production expenses. Selling expenses include all direct
and indirect sales expenses, such as employee salary, advertising expenses, and
rental expenses. General expenses are the enterprise’s comprehensive operation
process. Administration expenses include salaries of administrative personnel and
related taxes and fees.
526 Y. Cai et al.

Table 24.10 2017 Global semiconductor enterprise R&D expenses ranking

17/16%
2017 Rank Company R&D expense($M) R&D/Sales(%) Change in R&D
1 Intel 13,098 21.2% 3%
2 Qualcomm 3450 20.2% 4%
3 Broadcom 3423 19.2% 4%
4 Samsung 3415 5.2% 19%
5 Toshiba 2670 20.0% 7%
6 TSMC 2656 8.3% 20%
7 MTK 1881 24.0% 9%
8 Micron 1802 7.5% 8%
9 Nvidia 1797 19.1% 23%
10 SK Hynix 1729 6.5% 14%
Top 10 Total 35,921 13.0% 6%
Source: IC Insights

2. Net Assets: The net value of the enterprise after deducting liabilities from the total
assets. It consists of two parts. One is the capital invested at the beginning of the
establishment of the enterprise. The other is the assets created during the opera-
tion. Net Asset is also called the owner’s equity. It represents the value of owner’s
property in the enterprise, including paid-in capital, provident fund (surplus
accumulation fund, capital reserve), undistributed profit, and so on.
3. ROE: The rate of Return on Common Stockholders’ Equity. ROE is the ratio of
net profit (after tax) to net assets, representing the return of the equity, which is
used to measure the profitability of the company’s capital and fund efficiency of a
company’s capital. It is commonly used as an indicator for enterprise valuations
in mergers and acquisitions.
4. Net Income Exclude Unusual Items: It refers to the profit value after deducting
non-recurring gains and losses from the net profit. Since non-recurring gains and
losses do not reflect the profitability of IC enterprise, it is a common practice to
exclude them. Ordinary non-recurring gains and losses include the sale of assets,
gains, and litigation losses.

Net Income Exclude Unusual Items ¼ Net Income  NR

Where NR stands for non-recurring gains and losses.

Non-recurring gains and losses are non-cyclical and difficult to predict. If the
amount is large, it will interfere with the analysis of the enterprise’s operations. For
example, some start-up IC design companies will occasionally sell the patent or
intellectual property for a substantial amount of revenue compared with their
primary business. Therefore, it is necessary to omit this income and then evaluate it.
5. GAAP items and Non-GAAP items: General Accepted Accounting Practice
(GAAP) is a set of fair standards recognized by the US Securities and Exchange
Commission for the accounting of the enterprise. Chinese IC companies adopt
24 Financial Management Practice and Analysis of Enterprises 527

these standards to meet the requirement for frequent international comparisons.

The GAAP indexes refer to the indexes in line with GAAP, which is the common
item in the official financial statements, including revenue, net profit, etc. How-
ever, in the actual operation, there are one-time and unconventional expenditures,
changes in tax rates and other factors that cause the standard financial indicators
to not reflect the overall profitability of the enterprise. Therefore, many enter-
prises and financial institutions use the so-called “Non-GAAP items” to adjust
and more accurately reflect the real state of the company’s operations. Daily
Non-GAAP items include EBITDA, Free Cash Flow (FCF), etc. The significance
of individual items is not apparent, but the combination of multiple indicators will
place IC enterprises in the entire industry for horizontal international comparison,
which will lead to more accurate judgments.

Price-to-Earnings Ratio

The Price/Earnings (P/E) ratio (unit: multiple) is the ratio of a stock’s price to its
earnings per share:

Price=Earnings Ratio ¼ Stock Price  Earnings Per Share

P/E ratio is one of the most fundamental indicators used to evaluate stocks and
enterprises. It reflects the market’s comprehensive estimation of the enterprise’s risk and
growth potential. If an investor captures the enterprise’s growth expectation better than
the market does, he/she can decide to buy or sell short of the enterprise’s stock
accordingly. The idea is, the lower the Price/Earnings ratio, the better the value for
investment is. However, the so-called “high” and “low” are relative concepts. There is
hardly a universal rule or reference book that tells the answer. In reality, investment
decisions are made based on the accumulation of long-term observation and comparison
with other entities in the market, and the risk of loss is also limited in a reasonable range.
The real-time P/E ratios are fluctuated greatly, reflecting a lot of market’s senti-
ment at real-time. However, the average value over a specific period will show the
enterprise’s value and market expectations more comprehensively. For example,
Qualcomm’s average annual P/E Ratio on the US stock market has risen from
15 times to more than 20 times since 2015, in line with the steady growth of its
business.
The P/E Ratio of Some Large Listed Integrated Circuit Enterprises is shown in
Table 24.11. Compared to Europe and North America, the integrated circuits sector
has higher average P/E ratio in China’s stock market. China’s IC industrialization has
just emerged. The expansion space is ample, and the upward trend is evident. In this
case, the Chinese market is very optimistic about the industry’s future. A group of
leading enterprises with pioneering spirit came to the front stage, leading the
progress of the whole industry and forming up an industry chain with considerable
scale. However, the profit cycle of integrated circuit enterprise is generally longer. In
addition, there are certain restrictions on the listing approval and board transfer of the
528 Y. Cai et al.

Table 24.11 P/E ratio of some large listed integrated circuit enterprises
Company Stock exchange market P/E (times)
ASML Amsterdam Euronext 53.5
Applied Materials NASDAQ 24.6
AMD 44.4
Broadcom 44.4
Intel 10.0
Lam Research 24.3
Micron 14.4
Nvidia 90.7
Qualcomm 23.2
Texas Instruments 24.2
Hangzhou Silan Microelectronics Shanghai Stock Exchange 96.0
Jiangsu Changdian Technology 19.9
Shenzhen Goodix 42.4
Nations Technologies Shenzhen Stock Exchange 115.8
Ingenic Semiconductor 91.9
United Microelectronics Taiwan Stock Exchange 17.7
TSMC 28.2
MediaTek 19.6
ASE Technology Holding 10.9
Source: S&P capital IQ platform data as of December 31, 2021

domestic A-share market, which pushes up the P/E ratio of already listed enterprises.
As the industry matures and the listing process accelerates, it is foreseeable that the
overall P/E ratio will gradually decline, and investors will return to rationality, and
the industry will enter a period of stable growth.

Goodwill

Goodwill is the capitalized value of a company’s intangible predictable future excess

profitability. In company value assessment, it is possible that the fair market value of
the company is higher than the sum of the tangible net assets of the company and the
evaluation value of the intangible assets. This part of the value is considered to be
derived from the objective goodwill of the company. There are many sources of
goodwill. Anything that can generate excess profits can be included in the scope,
such as the reputation of the company, the prestige of the company’s top manage-
ment, the superior geographical position, good customer relationship, good labor
relations, and broad market prospect of products, etc. Goodwill cannot exist inde-
pendently of the company, and its value can only be reflected when the company is
sold as a whole or integrated.
In corporate mergers and acquisitions, the excess earning value brought by
goodwill is the value paid by the acquiring company for the target company
24 Financial Management Practice and Analysis of Enterprises 529

exceeding the target’s book value. In fact, this “purchase premium” is usually formed
by various factors, such as the negotiating power of both parties, the fair value of the
expected synergy of the acquiring company, and the target company.
The value of goodwill disclosed in the balance sheets of major global IC
companies in 2021 is shown in Table 24.12. It can be found that companies with
high goodwill values are frequently involved in mergers and acquisitions, such as
Broadcom. In February 2016, Avago completed the acquisition of Broadcom with
US$28.758 billion and renamed the entire company to Broadcom. Its goodwill value
on the financial statement balance sheet published on April 30, 2017, was US$24.7
billion, of which US$23 billion came from the acquisition of Broadcom’s premium
and US$83 million from the 2015 acquisition of Emulex. On November 4, 2019,
Broadcom completed its acquisition of the Symantec Business, US$6.6 billion of the
total US$10.7 billion purchase price was allocated to goodwill.
There are several methods for dealing with goodwill in corporate mergers and
acquisitions:

1. It is recognized as an asset separately and amortized within its expected useful

life, either as a cost or as a write-off of retained earnings.
2. It shall be written off immediately at the time of the merger and deducted from the
retained earnings directly.
3. Goodwill is treated as a permanent asset and is not amortized unless there is
evidence that its value has continuously declined.

Table 24.12 Goodwill value of major global IC companies in 2021 financial reports
Goodwill
Industry segment Company Billion USD Report date
IC design Qualcomm 7.2 9/26/2021
Broadcom 43.5 10/31/2021
Nvidia 4.3 1/30/2022
MTK 2.4 12/31/2021
AMD 0.3 12/25/2021
IDM Intel 27.0 12/25/2021
TI 4.4 12/31/2021
Micron 1.2 9/2/2021
IC Foundry TSMC 0.2 12/31/2021
SMIC 0.0 12/31/2021
UMC 0.0 12/31/2021
IC package and testing ASE 1.9 12/31/2021
Amkor 0.0 12/31/2021
Changdian 0.3 12/31/2021
IC Manufacture Equipment Lam 1.5 6/26/2022
ASML 5.2 12/31/2021
AMAT 3.5 10/31/2021
Note: Exchange rate using the rate at the end of the fiscal year
Source of data: Public financial report of the companies listed in the table
530 Y. Cai et al.

Take the deal by Zhejiang Wansheng Co., Ltd., a company listed on the Shanghai
Stock Exchange, to issue new shares to purchase assets as an example. Based on the
adjustment of national industrial structure, the company has identified the IC indus-
try as the key direction of its strategic transformation. In May 2017, the company
announced the “Issuance of Shares to Purchase Assets and the Raising of Matching
Funds and Related Transaction Plan.” The company intended to issue new shares to
acquire 100% the shareholder’s shares of Jiang Xin Zhi Ben (Shanghai) Technology
Co., Ltd. from 7 shareholders including Jiaxing Haida and State Grand Fund. Jiang
Xin Zhi Ben has completed the acquisition of all shares of Analogix, a US company
in Silicon Valley. Therefore, Zhejiang Wansheng Co., Ltd. will indirectly hold 100%
of Analogix after the acquisition deal closes.
The transaction price of Wansheng to acquire Jiang Xin Zhi Ben is 3.75 billion
RMB, which is more than the net asset value of the underlying assets. According to
the “Accounting Standards for Enterprises,” the difference between the merger cost
and the fair value of the identifiable net assets of the underlying assets acquired in the
merger shall be recognized as goodwill. The goodwill is not amortized but is subject
to an impairment test at the end of future fiscal years. Once the impairment of
goodwill is calculated, it cannot be rolled back in future fiscal years. Therefore,
Wansheng has made the following risk warnings in the “Transaction Plan”: “If the
underlying assets do not perform as expected in the future, the goodwill formed by
this transaction will have a high risk of impairment. Investors should pay attention to
the risk of impairment of goodwill.”

Equity Incentive

Equity Incentive is a long-term incentive mechanism that gives target employees part
of the company’s equity under certain conditions to encourage and retain core talents.
In the long run, it serves as an incentive method that enables motivated employees to
further participate in company business decision, profit sharing, and risk taking as
shareholders. More than 80% of the top 500 companies in the world have implemented
the equity incentive system in their corporate management. There are many forms of
equity incentives, such as performance stocks, stock options, virtual stocks, restricted
stocks, and stock appreciation options. The common forms of equity incentives for
Chinese listed companies are restricted stocks and stock options.
For high-tech enterprises, equity incentive is an effective complement to the
company’s salary system.
Under the condition of achieving performance appraisal, giving the management
team and core employees corresponding incentives is an important measure to
ensure the stability of the company team and to attract talents. The target of equity
incentive is the core talents with strategic value to the company. It can be those who
master core technologies or control key business and resources.
The importance of talents is ranked the first in the production factors of the IC
industry. The capital can only be brought into play under the condition that an
24 Financial Management Practice and Analysis of Enterprises 531

Table 24.13 Qualcomm’s annual SBC expense unit: Million US dollar

2018 2019 2020 2021
financial financial financial financial
SBC expense year year year year
In: Cost of revenue 38.0 35.0 34.0 47.0
In: R&D expense 594.0 725.0 872.0 1234.0
In: SG&A (selling, general, and 251.0 277.0 306.0 389.0
administrative) expense
Total SBC expense 883.0 1037.0 1212.0 1670.0
Source of data: Public financial report of Qualcomm in 2018-2021

effective team is formed with all types of talents. Compared with the traditional
industries, IC industry has a wider incentive range which includes at least senior
management, key technical employees, and sales employees. For many start-up IC
design companies in China, talent is the key to survival and development.
Attracting and retaining talent largely depends on equity incentives. However,
Chinese company will face the issue that the number of incentive employees is
limited, and the equity incentive cost will affect company’s profitability if the
company plans to go public in China.
Since the essence of equity incentive is the remuneration paid by the company for
its employees’ services, the company should amortize the expenses incurred by
equity incentive to the years in which the employees provide services. The equity
incentive cost is included in the corresponding accounting subjects according to the
department of the employee and the type of service provided. If the employees
granted incentive equity are the executives of a listed company, the cost of equity
incentive is usually included in the management fee. If employees granted incentive
equity are in the production department, the cost of equity incentive should be
recorded in the corresponding production costs. In the notes to the annual report of
listed companies, the current period expenses, accumulated liabilities, and the fair
value of the equity instruments about the equity incentives will be disclosed. For
employees, equity incentives are salary remuneration and are subject to individual
income tax. For the company, it is the employment cost and can be deducted as a
pre-tax operating cost.
For example, as a high-tech research and development company, Qualcomm’s
annual stock-based compensation (SBC) expenses account for a large proportion of
its research and development expenses, as shown in Table 24.13.

References
1. The Chinese Institute of Certified Public Accountants, Accounting, (China Financial & Eco-
nomic Publishing House, Beijing, 2012)
2. Ministry of Finance of the People’s Republic of China, Accounting standards, (Economic
Science Press, Beijing, 2017)
532 Y. Cai et al.

3. IC Insights, Semiconductor units forecast to exceed 1 trillion devices again in 2021.

icinsights.com. https://www.icinsights.com/news/bulletins/Semiconductor-Units-Forecast-To-
Exceed-1-Trillion-Devices-Again-In-2021. Accessed 26 Nov 2022
4. IC Insights, Chinese companies hold only 4% of global IC market share. https://www.icinsights.
com/news/bulletins/Chinese-Companies-Hold-Only-4-Of-Global-IC-Marketshare/. Accessed
26 Nov 2022
5. J. Lin, IC Insights: Top 10 Analog IC suppliers for 2021, en.ctimes.com.tw, IC Insights: Top
10 Analog IC suppliers for 2021 – CTIMES news. Accessed 26 Nov 2022
Investment and Financing of IC Industry
25
Yingping Hu, Yang Liu, Ming Yin, and Cheng Zhang

Contents
Venture Capital and Private Equity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Major Financing Sources for IC Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Financing Sources for IC Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Investment Methods of Industry Funds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
China Integrated Circuit Investment Fund and Sino IC Capital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Government Investment Funds on IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
International IC R&D Investment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Mergers and Acquisitions in IC Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
IPO and Going Private . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Procedure of Venture Investment for IC Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Due Diligence in IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Asset Evaluation of IC Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Abstract
This chapter introduces the information about investment in the Chinese IC
industry, including main funding sources and investors, listed IC corporations,
and activities among Chinese IC firms in recent times. The main investors in
Chinese IC industry include domestic and foreign VC/PE, industry funds, and
national or local government investing programs. The chapter also provides a
brief description of the due diligence investigation and decision-making pro-
cedures when an investment in the IC industry is made.

Y. Hu · Y. Liu (*)
Hua Capital Management Co., Ltd., Beijing, China
e-mail: Yang.liu@hua-capital.com
M. Yin
Publishing House of Electronics Industry Co., Ltd., Beijing, China
C. Zhang
Zhihu Inc., Beijing, China

© Publishing House of Electronics Industry 2024 533

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_25
534 Y. Hu et al.

Keywords
Fund · Venture Capital · IPO · M&A · Due Diligence Investigation · Asset
Evaluation

Venture Capital and Private Equity

Venture capital (VC) is also known as venture capital funds, commonly referred to as
VC. It refers to a form of capital investing action that one invests funds raised
through the issuance of fund beneficiary bonds and commissioned by the special
investment management agency – fund management companies to the emerging
companies with potential compatibility (typically high-tech companies). Through
this capital management service, one can directly participate in the entrepreneurial
business startup process. The beneficiary of venture capital fund and the fund
management company share investment profit according to the agreement [1].
The concept of Private Equity (PE) derives from the private fund. According to
the direction of investment, private fund can be divided into private equity securities
investment funds and private equity funds. Private equity investment funds mainly
invest in stocks, bonds, warrants, etc. PE funds, on the other hand, invest mainly in
the equity or corporate bonds of unlisted companies. In the broad sense, PE refers to
the equity investment before the Initial Public Offering (IPO), that is, the investment
made by enterprises in the seed stage, the IPO stage, the development stage, the
expansion stage, the maturity stage, and the pre-IPO stage. In the narrow sense, PE
mainly refers to the private equity investment of mature enterprises that have formed
a certain scale and are generating stable cash flow, that is, it mainly refers to the
private equity investment in the later stage of VC [1]. In China, industrial investment
fund, equity investment fund, venture capital fund, merger and acquisition (M&A)
fund, and other non-securities investment funds are included in the private equity
investment fund. Due to the high risk and high return nature of high-tech industry,
VC/PE equity investment has become its main financing method. The main purpose
of VC/PE investment in high-tech industry is to obtain excessive returns. It also
promotes the development of high-tech industry to a large extent. With the estab-
lishment and promotion of China’s new third board and growth enterprise board, as
well as the improvement of the primary market, VC/PE exit methods are more
abundant, and the investment intention is also enhanced. In recent years, VC/PE
has developed rapidly in China. As of the end of 2020, the number of private equity
fund management institutions registered with the Asset Management Association of
China reached 14,986, the size of funds under management was about 11.64 trillion
yuan (RMB), the cumulative number of exit cases was 26,708, and the cumulative
withdrawal principal was 1475.767 billion yuan. With the establishment and pro-
motion of China’s New Third Board and ChiNext, and the improvement of the
primary market, VC/PE has more exit methods. Although the exit method is still
mainly based on agreement transfer, going public is the fastest-growing exit method.
The ratio of the withdrawal amount and the number of withdrawals in the open
25 Investment and Financing of IC Industry 535

market were 27.95% and 17.00%, respectively, which was a significant increase
from 16.94% and 12.98% in 2019. In 2020, according to the statistics of the actual
number of projects withdrawn in the year, the exit methods of Chinese private equity
fund projects are mainly agreement transfer (37.43%), corporate repurchase
(20.57%), open market (17.00%), others including liquidation, dividends of invested
companies, debt transfer, etc. (16.85%), financier repayment (6.93%), and overall
acquisition (1.22%) [2] (Fig. 25.1).
The venture capital fund in the modern sense originated from the United States
and played a significant role in promoting the emerging industries in the United
States after the World War II. Both Xerox and IBM have received strong support
from VC in their development process. In the 1980s, VC in United States began to
develop rapidly. The amount of VC investment increased from 2.5 billion US dollars
in 1979 to 600 billion US dollars in 1997. IC companies such as Intel and Apple have
received strong support from VC too [3]. However, with the maturity of the industry,
US VC now basically no longer invests in domestic IC companies, but transfers to
China instead. VC funds and private equity funds in the field of IC in China began to
be active, which greatly promoted the industry.
The development of the IC industry has its own characteristics, such as high cost,
long payback period, and high risk. If you prepare to invest to the IC industry, you
must master its industry characteristics. Insufficient capital has always been one of
the core issues that restrain the IC industry. To catch up with the globalization trend
and the characteristics of that the winner takes it all of the IC industry, there must be a
trend of industrial integration and mergers and acquisitions in the future. The main
body of IC enterprises must be small but strong. Traditional financial support
methods not only have certain problems, but also cannot support the IC industry

Fig. 25.1 2006–2021 China VC/PE fundraising situation. (Source: Zero2IPO Group)
536 Y. Hu et al.

that is costly and requires patience of investors. Hence, to support the whole
industry, one must take advantage of the effective market mechanism to foster and
introduce long-term institutional investors represented by VC/PE.

Major Financing Sources for IC Companies

The financing channels that IC enterprises can use include government investment,
bank loan, capital market, etc. These financing channels have the characteristics of
dynamic change, which is closely related to the maturity of the industry. Generally
speaking, the more mature the industry is, the lower the return provided for investors
while the lower the risk. Thus, the financing of the mature industry depends more on
bank loans and investment in the secondary capital market. The less mature the
industry is, the higher the risk and lower return will be. Therefore, the investment in
the primary capital market and the self-raised capital of enterprises will become the
main sources of financing. Throughout the history, the financing channels of IC
enterprises in most countries have experienced the change from government invest-
ment to VC/PE intervention and then to the secondary market while the industry
developed. It is also notable that since the IC industry in different countries is usually
at different stages, the main financing channel of IC enterprises in different countries
might be completely different. Besides, due to the different characteristics of differ-
ent industrial steps, the financing channels of each step also reveal different
characteristics.
Government investment includes not only direct channels like industrial invest-
ment fund to invest equity in enterprises but also indirect channels such as govern-
ment procurement, government policy loans, and government-backed syndicated
loans. The United States is the first country in the world developing the IC industry,
which started with the support of government procurement from NASA and the Air
Force. During the gulf war in the 1990s, precision-guided weapons backed by IC
technology were first used on a large scale by the US military. Government pro-
curement played an important role in the maturation of the US IC industry. On the
contrary, the Korean IC industry obviously relies on indirect financing channels of
government, because the capital ownership of Korean high-tech enterprises is
always the lowest among that of enterprise in developed countries [4]. Indirect
government financing is also often used to protect Korean IC companies from
cyclical downturns. For example, the asset-liability ratio of Samsung reached
223% in 1997. During the industrial recession in 2001, 2006, and 2007, the asset-
liability ratio of Samsung also increased significantly, as shown in Fig. 25.2.
There are many ways for IC enterprises to obtain equity financing. No matter how
the enterprise chooses listing, VC, or industrial investment funds, they can share
risks and solve the quantitative capital demand in the development of enterprises.
Thus, they can all be regarded as effective financing channels [5]. For example, in
China, a capital market is consisting of the Main Board, small and medium Enter-
prise Board, Growth Enterprise Market, and new over-the-counter (OTC) Market. IC
enterprises can freely choose suitable listing channels based on their own conditions.
25 Investment and Financing of IC Industry 537

Fig. 25.2 1997–2021 changes in the asset-liability ratio of Samsung. (Source: annual report of
Samsung from 1997 to 2021)

Corporate bonds, bank credit, and financial leasing are the main ways of debt
financing. Compared with equity financing, corporate bonds are superior to bank
credit in financing scale and duration, and superior to stock market financing in
financing cost. Companies that issue bonds for financing have more autonomy while
keeping the control of existing shareholders. Operating on debt is conducive to the
financial leverage. Due to the diversification of financing channels, the combination
of the proper use of debt financing and rational allocation of enterprise capital
structure can achieve the lowest financing cost and the best capital structure.
Financial leasing has low requirements on the credit status of enterprises, which is
suitable for the financing of strategic emerging enterprises in the initial stage. As an
innovative way of off-balance sheet financing, financial leasing will not lead to a
transfer of ownership or affect the credit status. It is in line with the requirements of
multi-channel financing for IC enterprises. The IC industry requires a large amount
of investment in the early stage, which can be appropriately reduced by the financial
leasing mode.

Financing Sources for IC Manufacturing

IC manufacture industry is heavy asset industry, which means that it has a great
demand for capital. No matter where the capital comes from, it means the same to
enterprises. But different investors have different demands. The basic pursuit of the
national IC industry investment fund (the national fund) is to improve China’s IC
industry as soon as possible through investment on the premise of reasonable
returns, which means “the unification of national strategy and market economy.”
This is the principle (mission) of the national fund. The behavior that the fund holder,
broker, or retail and trader on capital market buy the stock of IC companies is also a
538 Y. Hu et al.

kind of investment. No matter how long they hold the share, the goal is to gain the
biggest interest.
The independence and international nature of IC industry determines its capital
sources mainly in six categories.

1. Publicly raised public capital (listing): An IC company sells its shares to the
public to raise capital.
2. Private equity investment fund (PE): PE includes national equity investment
funds, such as national or other relevant national equity investment and govern-
ment guiding funds, and IC equity investment funds and related equity invest-
ment funds and guidance funds set up in various places. These funds are allocated
to support enterprises.
3. Self-accumulation of the enterprise. Enterprises can raise capital through surplus
reserves (after-tax profits). To raise capital through this way, IC enterprises are
required to have certain profitability and fast depreciation ability, which enables
them to accumulate capital by themselves after achieving high profit.
4. Employee Stock Ownership. Employee stock ownership is a long-term perfor-
mance reward plan that encourages employees to hold stocks and options of the
company.
5. Debt financing. Enterprises can borrow money through bank credit, debt financ-
ing, private credit, bond financing, commercial credit, leasing, etc. Debt financing
can improve the return rate of enterprise ownership funds. Since the IC manu-
facture industry needs large investment while it has a long return period, the
manufacturing enterprises choosing this mode should correctly evaluate their
own scale and repayment ability, and hence choose the right mode of debt
financing to minimize the financial risk.
6. Mergers and Acquisitions (Ms&As). In order to fulfill their strategic intention and
increase their market share, IC enterprises can carry out capital integration
through merger and acquisition. Mergers and acquisitions generally refer to
combining an enterprise with the purchaser’s enterprise by purchasing it. A
merger is a combination of two or more independent businesses to form a
business: usually, one dominant company absorbs other companies. Acquisition
refers to that one enterprise uses cash or issue of securities to buy the share or
assets of another enterprise, and hence acquire the ownership of all the assets of
the newly bought enterprise, or a certain asset, or the control of the latter.

Manufacture in IC industry possesses typical feature of economies of scale. In the

process of becoming bigger and stronger, shareholders from various aspects will be
affected by different demands of various capital owners and even cause intense
conflicts, which will seriously affect the development of enterprises. It is notable that
there are two types of forbidden investment for IC manufacturing enterprises: First,
industrial capital with upstream and downstream connections – it will affect the
independence of enterprises; second, the capital that solely controls other IC man-
ufacture enterprises – it will cause the separation of capital, talent, and market [6].
25 Investment and Financing of IC Industry 539

Investment Methods of Industry Funds

In order to promote the industry, cultivate advantageous enterprises, and obtain

returns, industrial funds need to adopt different investment methods. There are five
investing methods of industrial funds, as discussed below.

1. Direct capital increase

The industrial fund increases its investment and buys shares in an IC enterprise
for the enterprise’s mergers and acquisitions or independent R&D. When
the industry fund satisfies the withdrawal period requirement, it can transfer the
equity it holds in the company to other companies or sell the equity on the
secondary market.
2. Adopt “listed enterprises + PE” type industrial merger fund
“Listed enterprises + PE” mode can take two aspects for listed enterprises into
account. It has also been applied in various enterprises. This mode can greatly
enhance the merger and acquisition ability and reduce the capital pressure of
listed companies. A typical case for this mode is the acquisition of STATS
ChipPAC. In this case, the industrial fund joined forces with two listed compa-
nies, Jiangsu Changjiang Electronics Technology Co., Ltd. and SMIC, to help the
former acquire large international companies. In the total $780 million invest-
ment, $260 million comes from Long Telegram Technology, $100 million comes
from SMIC Subsidiary Core Electric Semiconductor, $300 million comes from
industrial funds ($140 million comes from the shareholder loan with convertible
share and the other $160 million comes from equity investment), the remaining
$120 million comes from the Bank of China Wuxi branch loan [7]. The industry
and capital are well combined: Industrial funds can use listed enterprises’ under-
standing of the industrial chain to reduce the information asymmetry in the
process of Ms&As and hence find investment targets. Also, when necessary,
they can directly transfer their equity to listed enterprises, which is a good method
to exit.
3. Merger and acquisition with enterprise consortium
The industrial fund and the IC enterprise shall reach a consensus on the relation-
ship, and jointly implement the external M&A project: the enterprise controls the
project, and the industrial fund participates. Under appropriate conditions, the
holding company shall acquire the equity held by the industrial fund by cash or
stock exchange.
4. With the joint stock enterprises set up a special investment fund
The industrial fund and holding company jointly set up special investing
sub-funds for equity investment in the field of IC as limited partner and general
partner. By doing this the partners can make full and flexible use of social
capital through fund holding; it is also suitable for the requirements of equity
investment and can regulate the investment behavior according to the market
requirements. In the future, the fund investors can exit with profit by IPO or
equity transfer.
540 Y. Hu et al.

5. Finance leasing companies shall be established to support manufacturing

enterprises
In order to promote IC industry, the industrial fund can encourage the upstream
and downstream enterprises to cooperate on investing and set up new enterprises.
The industrial fund can intervene in newly established enterprises by equity
investment to promote the cooperation between upstream and downstream enter-
prises. Besides, the industrial fund can purchase equipment for large-scale pro-
duction for the joint venture. The industrial fund may also establish or invest in
equipment leasing companies to lease equipment for large-scale production to IC
enterprises or joint ventures. Both parties shall sign a lease agreement and
promise to pay the rent on time.

China Integrated Circuit Investment Fund and Sino IC Capital

In June 2014, a government document, the “National Integrated Circuit Industry

Development Promotion Outline” was officially released and implemented, clearly
setting up a national industrial investment fund, and supporting the establishment of
local integrated circuit industry investment funds to encourage various types of
venture capital and equity investment funds to enter integrated circuit fields.
China Integrated Circuit Industry Investment Fund (CICIF) is a corporate private
equity investment fund mainly engaged in the equity investment business of the
integrated circuit industry. The fund manager of CICIF is Sino IC Capital (Sino IC).
The fund company was incorporated in Beijing on September 26, 2014. Its
business is to invest in integrated circuit chip manufacturing, taking into account
the chip design, packaging and testing, equipment, materials, and other industrial
links. The fund companies aimed to create good returns for shareholders in a period
of 10 years and can be extended for a maximum of 5 years, subject to the approval of
the shareholders’ meeting of the fund company. At present, the total share capital of
the fund company is 138.72 billion Yuan, which is jointly funded by 19 shareholders,
as shown in Table 25.1. Shareholders include enterprises in the central financial and
integrated circuit industry clusters, entities in the real economy, some financial
institutions, integrated circuit industry chain related enterprises, and some private
capital. Shareholders have clear financial returns to the fund and set a threshold for
the fund.
The fund company is a joint stock limited company established in accordance
with the “Company Law of the People’s Republic of China.” The shareholders’
meeting is the highest authority of the fund company. It exercises its powers in
accordance with the “Company Law of the People’s Republic of China” and the
“Articles of Association” of the fund company. The fund company has a board of
directors (the board), who are elected by the general meeting of shareholders, and the
board is responsible for the shareholders’ meeting. Senior management is appointed
by the board. The behaviors of fund companies are strictly in accordance with
Chinese laws and market rules, and the identity of employees is also transparent to
the market.
25 Investment and Financing of IC Industry 541

Table 25.1 China Integrated Circuit Investment Fund Co. Ltd. Shareholder Composition
Shareholder
Shareholder name type
Ministry of Finance of The People’s Republic of China Common stock
CDB Finance Co., Ltd. Common stock
Preferred stock
China National Tobacco Corporation Common stock
Preferred stock
Beijing E-Town International Investment & Development Co., Ltd. Common stock
China Mobile Communications Group Co., Ltd. Common stock
Preferred stock
Shanghai Guosheng (Group) Co., Ltd. Common stock
Wuhan Financial Holding (Group) Co., Ltd. Common stock
China Telecom Common stock
Preferred stock
China Unicom Common stock
Preferred stock
China Electronics Technology Group Corporation Common stock
China Electronics Corporation Common stock
Datang Telecom Technology Industry Holding Co., Ltd. Common stock
Sino IC Capital Common stock
Beijing Ziguang Communication Technology Group Co., Ltd. Common stock
Shanghai Wuyuefeng Pujiang Equity Investment Partnership (Limited Common stock
Partnership)
Cybernaut Investment Group Co., Ltd. Common stock
National Council for Social Security Fund, The People’s Republic of China Preferred stock
PICC Asset Management Company Limited Preferred stock
China Life Insurance (Group) Company Preferred stock

In accordance with the principle of separation of ownership and management

rights, the fund company entrusted Sino IC Capital as the sole manager of the fund.
The registered capital of Sino IC Capital was 1.2 billion Yuan, which was jointly
funded by 8 shareholders. CICIF and Sino IC Capital belong to the contractual
relationship of entrusted management. Sino IC Capital manages the investment
business of the fund and collects the management fee according to the agreement.
After the investment project exits and meets the threshold income of the fund
company’s shareholders, Sino IC Capital and the fund company shareholders share
the excess investment income according to the agreed ratio. At present, Sino IC
Capital’s shareholders include CDB Finance Co., Ltd., Saidi Industrial and Informa-
tion Technology Research Institute Co., Ltd., Beijing Saipinke Technology Co., Ltd.,
Yingfu Taike Venture Capital Co., Ltd., Suzhou Yuanhe Holdings Co., Ltd., China
Mobile Communications Group Co., Ltd., Beijing E-Town International Investment &
Development Co., Ltd., and Shanghai Digital Industry (Group) Co., Ltd.
The fund investment business adopts a market-based decision-making mecha-
nism, which mainly focuses on the growth of the project and is not subject to
government intervention. The enterprises invested by the fund do not distinguish
542 Y. Hu et al.

between ownership and domestic and foreign investment. The fund’s investment
projects will be withdrawn in a market-oriented manner after the expiration of the
fund company’s existence. Generally speaking, this fund is similar to other private
equity funds. Before investing, it mainly measures the technological innovation
level, profitability, corporate management team, market share, investment risk, and
other factors. The National Fund has made a total of 43 effective investment
decisions involving 35 enterprises by December 31, 2016. The guaranteed fund
reached 81.8 billion RMB and the actual fund reached 56.3 billion Yuan, accounting
for 59% and 41% of the total initial phase of the fund. The investment project covers
all aspects of the industrial chain such as integrated circuit design, manufacturing,
packaging and testing, equipment, materials, and ecological construction.

Government Investment Funds on IC

International Government Investment Fund is effective to promote IC industry and

thus widely used. It can not only make a huge influence on the market competition
and the value of a certain enterprise, but also the overall situation of the global IC
industry. Obviously, except the financing from the equity of industrial investment
funds, debt financing such as syndicated loans is available to promote the industry
too. In June 2014, “The Outline for Promoting the Development of the National
Integrated Circuit Industry” was officially issued and implemented, which clearly
proposed the establishment of a national industrial investment fund, supported the
establishment of local investment funds for the integrated circuit industry, and
encouraged all kinds of venture capital and equity investment funds from the society
to enter the integrated circuit field. Under the guidance of this document, the
National Integrated Circuit Industry Investment Fund was established in September
2014. Local government investment funds have also been established in Beijing,
Shanghai, Fujian, and other places. Both national and local funds have played an
important role in promoting the development of China’s IC industry. And unlike
China, few other countries focus on integrated circuits as an industry. Therefore, the
following funds do not focus on IC industry, but have significant influence on it
instead. In European and American IC industry, direct financing is used more by
market due to the feature of it being highly market oriented, hence the government
usually adopted indirect ways to support the industry. Conversely, Japan and South
Korea governments usually employ indirect financing channels to support the
industry. Therefore, all the following funds are government investment funds in
Southeast Asia and West Asia.
Singapore Temasek is a fund 100% owned by the Ministry of Finance of
Singapore. It is the most famous government investment fund in Singapore, whose
investment represents the will of the government. Prior to Temasek, the Economic
Development Board (EDB) and its financial resources had taken the same part in
Singapore’s IC industry. In 1991, EDB established the Singapore Microelectronics
Research Institute, which is mainly engaged in the R&D of value-added products in
the electronics industry related to microelectronics. From 1991 to 1994, EDB had
25 Investment and Financing of IC Industry 543

invested a total amount of more than 50 million US dollars to the Singapore

Microelectronics Research Institute. In 1991, Temasek began to take control of the
IC industry by acquiring 95% stake in Chartered Semiconductor Manufacturing
(CSM) and transformed it to a foundry. Chartered Semiconductor has also formed a
governance structure similar to Temasek: one of the seven members of the board of
directors is appointed by the government, and the other six are inside and outside
the company; the general manager is elected by the board of directors, and if the
performance of the company did not improve, the Ministry of Finance had the right
to remove the management team [8]. Prior to this, Chartered Semiconductor split out
of the design center Tri Tech, which was wholly owned by Singapore Technology
Venture Capital. In 1992, EDB and Tech Instruments, Canon and Hewlett-Packard
jointly invested on Tech Semiconductor, with a total amount of 325 million dollars.
EDB invested 26% and provided low-interest loans and tax incentives. This is also
the first storage and DRAM manufacturing company in Singapore. The huge success
of the investment has greatly improved Singapore’s foundry techniques. In 1995,
Temasek established STATS ChipPAC, a sister company of Chartered Semiconduc-
tor. Later, EDB also invested in Philips (later transferred its equity to NXP) and
TSMC’s joint venture project in Singapore (Systems on Silicon Manufacturing Co
Pte Ltd) [9]. So far, Singapore has established an IC industry chain system through
the government funds. However, because of the overcapacity of global IC industry
and the constant loss of enterprises since 2000, the Singapore government invest-
ment fund was considering withdrawing from the IC industry. In the 2008 financial
crisis, Temasek had to sell Chartered Semiconductor and Star Branch. In 2010,
Temasek sold a 62% stake in Chartered Semiconductor to its parent company,
Advanced Technology Investment Co (ATIC), for $2.424 billion. In 2014, Ion
Investment, a subsidiary of Temasek, sold its stake in Seoul Semiconductor for
$176 million ($242 million in 2009). In 2015, Temasek sold the Star Branch Jin
Peng, which has been the world’s fourth largest packaging and testing company, to
Jiangsu Changdian. At present, Temasek has basically withdrawn from the IC
industry.
The UAE government investing fund has increased its investment in the IC
industry in recent years. Its main investing institution is the Mubadala Develop-
ment Company established in 2002 by the government, and the Abu Dhabi
Advanced Technology Investment Corporation (which was wholly owned by the
former in 2011) established in 2008. At present, Mubadala Development Company
has a total size of US$63.5 billion. The investing target of the UAE government
investment fund in the field of IC is mainly AMD and the factory of GF in
New York. In 2009, the UAE government investment fund and AMD jointly
established GF, and then acquired AMD’s shares in the grid, making it a wholly
owned enterprise. After that, the company continued to grow through the merger of
Singapore Chartered Semiconductor and IBM Microelectronics Division. In 2016,
the UAE government investment fund invested $2 billion in the Core to develop its
7 nm process. Except the property above, the UAE government investing fund also
owns 8.1% of AMD shares. GF has invested and established its factory in China
in 2017.
544 Y. Hu et al.

Khazanah Nasional Berhad (KNB) was established in 1965 and is 100% owned
by the Malaysian Ministry of Finance. It currently has $32.5 billion in assets. The
treasury holdings have invested certain amount of money to the IC industry, but only
accounts for about 2% of its total assets. Its main investment is SilTerra, the world’s
15th-ranked foundry (sole proprietorship, established in 1995), and test equipment
manufacturer Aemulus (shared 15%). SilTerra’s overall financial situation is not
good: the accumulated loss in 2011–2014 has reached RM1.7 billion (about 380 mil-
lion US dollars); Aemulus has remained profitable.

International IC R&D Investment

Many successful IC R&D projects are supported and invested by the government.
Thus, the government’s support and investment have greatly helped the development
of the IC industry.
The Interuniversity Microelectronics Center (IMEC) is a non-profit organization
founded in 1984 by the Faradez Provincial Government of Belgium. Its purpose is to
combine the academic research strengths of universities in the Dutch-speaking
region and hence commit to the R&D of IC pioneer technology which in turn drives
the development of peripheral related technologies. In the beginning, due to the
limited budget of the Belgian government, only 62 million EUR were invested. In
2007, according to the agreement between IMEC and the government, the provincial
government of Faradez provided IMEC with a total of 210 million EUR in
2007–2011. In the past 5 years, the total budget of IMEC has exceeded 1.2 billion
EUR. Nearly 1 billion euros are all earned by research and development income.
IMEC’s R&D projects are closely combined with industry development, which
creates a unique business mode that cooperates with companies to jointly develop
and share results [10]. After 33 years, IMEC has become the most influential IC
technology R&D center in the world and has made great contribution to the world’s
IC industry.
Japan’s Very Large Scale Integration (VLSI) alliance is a typical case of an IC
investment project. With the help of this alliance, Japan surpassed the United States
in micro-process memory chips and began to replace the United States as the
monopoly in semiconductor industry. It continuously occupies more than half of
the global semiconductor market. In the process of industrial development, the
government has provided many subsidies to the alliance. From 1976 to 1979, the
government subsidies of VLSI Alliance were 29.1 billion Yuen, accounting for 40%
of the total funding of 73.7 billion Yuan. The R&D expenditure of the VLSI Alliance
generally accounts for 20% to 60% of the total R&D expenditure of the Japanese
semiconductor industry. Toshiba, Hitachi, and other IC companies have supported
the R&D of VLSI. According to the agreement, the R&D results are first used to
return government subsidies while enterprises can hold technical patents. In
1976–1979, the VLSI Alliance obtained more than 1000 patents, which greatly
supported Japanese companies to occupy the global market. In 1980, Japan success-
fully developed 64Kbit dynamic random-access memory, which was half a year
25 Investment and Financing of IC Industry 545

earlier than the United States; in the same year, it developed the 256Kbit DRAM,
which leads ahead the United States for 2 years. In 1985–1992, Japan became the
world’s largest semiconductor producer.
Based on the experience of Japan’s development, South Korea chooses to select
breakthroughs, introduce and absorb foreign technology, which finally result in
technological independence. The main reason for the results of the Korean IC
industry is still the government’s guidance and support. In 1981, the Korean
government officially adopted the Semiconductor Industry Comprehensive Devel-
opment Plan, which mainly developed four fields: ultra-large scale IC, computers,
communication equipment, and electronic components. In 1983, the Ministry of
Commerce and Industry published the Semiconductor Industry Breeding Plan and
invested 260 billion won in the next 4 years to establish a semiconductor production
basement. In 1986, the South Korea Semiconductor Consortium, which was founded
by 13 companies, invested 140 billion won in 3 years. The government and the
consortium each invested half of them to develop ultra-large-scale IC of 4 Mbit
DRAM or more. Since the 1990s, the Korean IC industry has risen rapidly, and
Korean companies are also far ahead in the global rankings.

Mergers and Acquisitions in IC Industry

Table 25.2 lists some of the mergers and acquisitions (Ms&As) events that have
happened in China’s semiconductor industry since 2009. It can be seen that, from
2003, Ms&As is an increasingly frequent occurrence in IC industry, while conve-
nient financing channels and strong capital strength also makes listed companies
become the initiators for most of Ms&As.
The reasons for the frequent occurrence of industrial mergers: on the one hand,
after 60 years of development, the trend toward industrial concentration is increas-
ingly obvious, and leading enterprises have obtained more market shares thanks to
their technical and capital advantages, squeezing other enterprises into smaller
market shares; on the other hand, with the emergence of new application fields
such as mobile Internet, Internet of Things, and cloud computing, semiconductor
technology will still continue evolving, but domestic IC industry is still a long
distance away from an internationally advanced level in terms of R&D of new
technologies, reserves of talents, and scales of production, and therefore, the exten-
sional development through Ms&As is one of the ideal approaches enabling domes-
tic enterprise to transcend barriers and rapidly increase competitiveness.
Firstly, external mergers completed by an IC enterprise can help achieve such
objectives as obtaining advanced technologies and improving production lines: in
the first place, it is to obtain the assets of the target enterprise with intellectual
property rights such as technologies and patents; in the second place, it is to join
hands with the technical team of the target enterprise and strengthen the ability for
research and development; in the third place, it is to use the target enterprise to
extend its own sales channels so as to produce a synergetic effect. For example, in
the case of TFDME buying out the two subsidiary companies of AMD Penang and
546 Y. Hu et al.

Table 25.2 Some of the events of mergers in China’s semiconductor industry since 2009
Time of
completion Buyer Seller
2009 Inspur Qimonda AG China R&D Center
2011 Good Ark Mingrui Optoelectronic
2013 Tsinghua Unigroup Spreadtrum Communications
Unigroup Guoxin Shenzhen State Microelectronics
Taiji Xinyihui Electronics
Huatian Technology Kunshanxitai
2014 Unigroup RDА
Goer Dynaudio Holding A/S
PDSTI Montage Technology
2015 Unigroup Guoxin Xi’an Huaxin
Huatian Technology FlipChip International LLC
Summitview Capital, Hua Capital, ISSI
E-Town Capital
Jaccapital NXP RF Power
Liyuan Info (A-share: 300184) DXY
2016 SMIC LFoundry
TFME AMD Suzhou, AMD Bingcheng
Hua Capital Omni Vision Technologies
Changjiang Electronics STATS ChipPAC
NAURA NMC
Liyuan Info Feat China
2016 Jaccapital NXР Standard products business
Chipone etc. iML
2017 Liyuan Info Wuhan Powertek
Shanhai Capital Analogix
Canyon bridge Imagination
2018 Wanye Enterprises Kingstone
2019 Huatian Technology Unisem
GTA Semiconductor ASMC
China Wafer Level CS Anteryon
Gigadevice Semiconductor SILEAD
PNC Process Systems Bandweaver
Will Semiconductor OmniVision Technologies,SuperPix
Wingtech Technology Nexperia
Primarius Technologies Platform Design Automation
2020 Ingenic Semiconductor ISSI
2021 Will Semiconductor Synaptics Mobile LCD TDDI
Business
Note: The M&A deals completed by the members of China Semiconductor Association and by
some of relevant listed companies for the purpose of holding a controlling number of shares should
be taken as the main source. The names of both buyer and seller are in short form. The mark
represents a case of privatization of US stocks
25 Investment and Financing of IC Industry 547

AMD Suzhou, AMD’s subsidiary companies have the world advanced large-scale
platform for high-end packaging process in mass production. The merger can not
only enable TFME, a domestically major packaging and testing enterprise, to reach
the world top level in the field of flip-chip packaging but more importantly, improve
its productivity and competitiveness in terms of high-end advanced packaging
process as well, so that it can provide customers at home and abroad with scalable
customized high-end packaging and testing services.
Secondly, through Ms&As, the optimization and consolidation of resources can
be achieved within the industry so as to produce a scale effect. The characteristics
of capital-intensive industries are especially obvious in the field of IC manufactur-
ing. The technological processes of manufacturing are continuously upgrading,
tending to require an investment of several billions or tens of billions of US dollars
and posing a huge challenge to the enterprises. Only the enterprises whose pro-
duction is on a considerable scale can achieve the goal of making profits. At
present, the development in China’s IC industry is characterized by low concen-
tration, modest corporate scale effects, serious homogeneous competition, and
discretely distributed resources unfavorable for a healthy industrial development.
Under such circumstances, Ms&As are an effective measure without doubt. For
example, in 2013, Huatian successfully bought 63.85% of the shares in
Kunshanxitai, rapidly increasing its capacity for advanced packaging process,
and enhancing its own competitiveness. At last, the Ms&As in the market in the
form of industrial cooperation can help achieve the goal of multiple wins. For
example, not only has the acquisition of STATS ChipPAC by JCET enabled
Changjiang Electronics to obtain advanced technologies and strengthened its
position as a domestically leading packaging and testing enterprise and an indus-
trial oligarch, the two enterprises also have strong complementary and synergetic
effects on each other in terms of market shares, capacities, and human resources,
able to enter high-end international market in the future and get closer to China’s
market and clients, improving global competitiveness. It is worth mentioning that
industrial parties such as the China Integrated Circuit Industry Investment Fund
and SMIC have been introduced to this acquisition, and this has great reference
value for domestic IC enterprise to explore the models of overseas Ms&As from
now on and for the cooperation between upstream and downstream enterprises in
the industrial chain.

IPO and Going Private

Initial Public Offering (IPO) is the process that a company to be listed offers shares
on a securities market to the public and raises funds for the first time, and requires the
issuer to issue shares to the public in a securities underwriting institution and to be
listed on a stock exchange after meeting necessary conditions and being approved by
or registered in a security regulatory agency, and thus the company becomes a listed
548 Y. Hu et al.

public company [11]. In China, the existing Securities Law specifies that public
offering of stock is the precondition for listing and transaction, so the two concepts,
IPO and listing, are closely connected and are always mixed up. Chinese A Share
market, Hong Kong stock market, and the US stock market are three IPO targeting
markets popular with Chinese IC enterprises.
Because IC industry is a typical capital-intensive industry, and there is a “winner-
take-all” phenomenon in the industry, enterprises whose market shares rank among
the finest have motive force to extend their scales to obtain more market shares. No
doubt listing is the ideal route for the development of an enterprise; with strong
“hematopoiesis capability,” enterprises can obtain powerful financial support
through more R&D input for endogenous growth or through merging for external
growth. For example, the case in which JCET acquired STATS ChipPAC fully
reflects the capital advantages of listed companies.
Whether enterprises listed in different places can obtain higher valuation is
related to their comprehensive capabilities and is subject to restriction of the market
growth space corresponding to development stages of different industries, especially
for the IC industry and even the whole semiconductor industry. With 60 years of
development, the semiconductor industry in the United States now has entered a
mature period from incubation stage and growth stage, and the growth slows down;
in China, huge population brings a vast market. And with perfect electronic product
design, perfect production and industry ecology and policy encouragement and
support, the semiconductor industry is now flourishing, and the market is growing
powerfully. Correspondingly, difference in the industrial development stage between
China and the United States is directly embodied through the valuation of individual
stocks of the semiconductor industry: higher price-earnings ratios (P/E ratios) of
relevant enterprises on A Share market reflect recognition for excellent development
trend of the IC industry at the growth stage. Certainly, difference in valuation
between the Chinese stock market and the US stock market is related to other
factors, such as the continuous high growth rate of Chinese economy in recent
years, unopened capital accounts in balance of international payments and listing
entry threshold of stock market higher than that of US stock market.
Going private of a listed company is a capital operation behavior to delist a listed
company and to make it become a nonpublic company. Going private sometime
occurs when the market value of a listed company is lower than its book value.
Some cases of going private are initiated to merge listed companies to realize industrial
integration. Going private also is initiated to transfer company stock to another market
to get a higher valuation level so as to obtain capital premium, and the stock market
value does not fall below the book value by this time. Going private is always
proposed by the management or majority shareholders (can also be initiated by
other investors) who buy the shares of the listed company from other shareholders
with cash or securities, then submit application for delisting to the exchange and then
complete delisting. Going private of a company is common on mature capital markets
in the United States and Hong Kong. However, the opportunity of being listed on
Chinese A Share market is rare and cases of going private are also rare in China.
25 Investment and Financing of IC Industry 549

IPO and going private are not contradictory and are both ways to obtain better
development opportunities for enterprises. Furthermore, many companies choose
to be listed again after going private. For example, ISSI was listed in Taiwan,
China, and the United States successively and then delisted through going private.
Sometimes, going private is also a link of industrial integration. For example,
Broadcom was acquired by Avago and thus was delisted from the NASDAQ
market in 2016.
From 2013 to 2016, some Chinese companies listed in the United States choose to
go private and seek to return A Share, some of which are IC enterprises. For
example, Spreadtrum and RDA were acquired by Tsinghua Unigroup in 2013 and
2014, and Montage Technology completed going private in 2014. Firstly, the IC
industry in the United States has entered its mature period, and investors in the
United States cannot completely understand the operation mode and value of
Chinese IC enterprises which are in the growth and rapid development period as
growth of the whole global market slows down, affecting valuation of enterprises.
Secondly, the increasingly mature domestic market and various auxiliary policies
provide convenient financing channels and policy environment for excellent IC
enterprises. US enterprises including OmniVision accepted the offer of going private
from Chinese financial groups, proving that Chinese efforts in promotion for devel-
opment of IC industry are being recognized by all parties.
From a point of view of historical experience, the reason why the IC industry in
the United States keeps flourishing is that the multi-layer capital market with
continuously emerging creative financing tools provides powerful support. There-
fore, Chinese IC enterprises should seek to be listed in appropriate time and places
and give exit channels for early venture investors, forming a virtuous cycle of
“investment-exit-reinvestment-reexit” for capital in the industry.

Procedure of Venture Investment for IC Companies

The concurrent IC industry in the electronic information field has huge demand for
venture capital, which covers various industrial links including design, manufactur-
ing, assembly and test, equipment, and materials. Venture investment in the IC
industry is featured with high level specialization, so during each investment
stage, professional teams are needed to promote the success rate. Generally, the
procedure of venture investment is shown as in Fig. 25.3.
During decision making for venture investment in an IC enterprise, its financial
and legal status, management experience, and operation status are taken into con-
sideration, and the target enterprise is subject to analysis according to some features
inside the industry. For details, see Table 25.3.
Venture investment in the IC industry always focuses on enterprises at the early
development stage, which determines the long period and high risk for investment.
In counties and regions with mature industries and capital markets, the main source
of venture capital is market-oriented institutional investors and enterprises. With
550 Y. Hu et al.

Fig. 25.3 Procedure of venture investment project

Table 25.3 Industrial features need to be evaluated for venture investment in the IC industry
Industrial features Corresponding concerns
Intelligence intensive Expertise and technical talents
Rapid technological development and leading technologies
Capital intensive High capital threshold, especially in such fields as manufacturing,
assembly and test, and equipment
High one-time capital input, for example, purchasing advanced
manufacturing equipment
Long input cycle Long R&D period for new technologies
Continuous input period for product R&D is usually calculated in
terms of years, for example, 1–3 years
Many chain links for promotion of products and customers
Coordination of Design, manufacturing, and assembly and test need excellent industrial
industrial chain coordination
Chips, components, and complete-machine manufacturing need
industrial coordination and cooperation
Complete-machine manufacturing, brand construction, and terminal
sales are closely tied to each other and form a chain
Global competition Global allocation of technical and management talents
Global sharing of supporting technologies, such as production process
Global purchase of equipment and materials
Global distribution of markets and customers
High industrial When a segment market develops to a certain extent, leading
concentration enterprises have greater market shares
The rate of margin of an enterprise and its market share has a positive
correlation

regard to the emerging Chinese IC industry, factors such as high entry threshold,
great demand for investment capital, long period, and obvious uncertainty make it
difficult for enterprises to obtain market-oriented capital. Therefore, government
funds first invest in the industry experimentally through establishment of guidance
funds and then lead private capital to following up, which can create excellent
investment and financing environment and promote development of the industry.
Venture capital institutions in the IC industry can provide capital and also high-
quality post-investment value-added service for target enterprises. Firstly, investment
25 Investment and Financing of IC Industry 551

Table 25.4 Some IC enterprises supported by venture capital and their investment institutions
Enterprise name Some institutions involved in venture investment (random order)
Spreadtrum Shanghai Industrial Holdings Limited, CSC Group, Lenovo Capital and
Incubator Group, Northern Light, New Enterprise Associates (NEA)
RDA Warburg Pincus, International Data Group (IDG)
SMIC Jade Bird Universal, Shanghai Industrial Holdings Limited, Goldman Sachs,
Walden International
GigaDevice TusHoldings, Zhonghai Venture Capital Investment, Westsummit Capital
Montage AsiaVest Partners, Intel Capital
Technology

teams can take advantage of their experience in technologies and management accu-
mulated in the industry to provide suggestions and help for development of enter-
prises; secondly, investment teams can help enterprises connect downstream,
upstream, other institutions, and social resources and build a cooperation network.
As an investment behavior, the final purpose of venture investment is to obtain
returns through project exit, and exit is the final link of the whole investment process.
The way of exit of venture investment mainly includes being listed and stock right
transfer. When an enterprise invested in is listed, venture capital institutions can
obtain considerable investment returns, and the enterprise invested in can also obtain
continuous financing capacity, which can be considered as an ideal way of exit. In
the market, such ways of exit as buying-back by original shareholders, purchased by
the management, M&A, and transferred to other institutions are also quite common.
For a part of IC enterprises supported by venture capital and their investment
institutions, see Table 25.4.

Due Diligence in IC Enterprises

Generally, an equity investment institution takes mainly three steps in making a

decision on the investment in an IC enterprise: the first step is to collect the
information about potential target enterprises according to the development in the
market and in IC enterprises, analyzing the investment values of the target enter-
prises in the light of the organization’s own concept of investment and selecting a
suitable enterprise from them before having the project registered and authorized; the
second step is to verify the investment feasibility and value certainty, carrying out
due diligence in the target enterprise, comprehensively studying the enterprise’s
operational status and the potential for development, evaluating the potential risks
from all aspects and producing a due diligence report; the third step is for
the investment committee to make a decision whether an investment should be
made or not according to the results from the due diligence. Among them, the due
diligence is a very important step – if it is found during the due diligence that
the target enterprise carries a potential uncontrollable huge risk or that a similar
situation exists, the investment committee may veto the project.
552 Y. Hu et al.

The due diligence (“DD” for short) is an investigation of a potential investment,

generally including but not limited to such aspects of the target enterprise as
business, finance, and legal affairs. The investment institution may engage an
external team, for example, the experts in the industry, accountants, lawyers,
etc., to take part together, and then a checklist for the due diligence needs to be
made. For the highly professional IC industry, it is necessary to fully take into
account all the factors at macro-to-micro levels in the industry and in the enter-
prise, such as the periodicity of the market for IC industry, fast technical and
product upgrading, effects of oligopoly in refined industrial segments, and the
technical barriers facing newcomers. After the checklist for the due diligence is
made, the team will collect the information about all the aspects step by step and
carry out a detailed analysis. In the light of the characteristics of IC industry,
Table 25.5 gives examples of some important items to be analyzed during the due
diligence.
In reality, there is no such enterprise that is perfect in every aspect. For the
enterprises at different developmental stages, the focus of the due diligence differs.
Generally speaking, by carrying out the due diligence, the investment institution’s
goal is to understand the enterprise in detail, and analyze the future growth potential
and competitiveness of the enterprise in the market according to the collected
information, so as to make a reasonable decision on investment.

Table 25.5 Examples of the items to be analyzed during the due diligence in IC industry
Industrial characteristics
Intelligence-intensive
Capital-intensive
With a long period of
investment return
With industry chain
synergy
In global competition
Industrial intensity
Examples of the items analyzed in due diligence
Background of the founder and the core team, professional ability
Core technology and reserve in the enterprise, IP autonomy
Competitiveness of core technology
Input into the R&D of new products
Financial health index (e.g., cash flow)
Ability of continuous operation and of addressing risks from the
market
History of financing and structure of equities
Return on investment in product (ROI)
Competitiveness of product in the market (e.g., placement in the
market, costs, average selling prices, gross margin)
Marketing and sales channel development ability (e.g., sales team)
Trend of industry transfer (e.g., “smiling curve”)
Upstream and downstream synergy, operational efficiency
Competitive landscape in refined market segments
Corporate governing structure (e.g., equity incentives mechanism
for the core team)
Global service support
Advanced tools and equipment
Target market segments and target client base
Developmental stages in refined market segments and competition
policies
Industrial strategic objective (e.g., industrial leader or oligarchy)
Operational execution index (e.g., gross margin, market share)
25 Investment and Financing of IC Industry 553

Asset Evaluation of IC Enterprises

For such purposes as operational management and asset transactions, enterprises

need to carry out asset evaluations, with the targets including real estate, chattels,
intangible assets, corporate values, asset losses or other economic rights, and
interests. The evaluations are generally conducted when such events take place
as transformation into shareholding systems, public offering, mergers and acqui-
sitions, mortgage loans on assets, external financing and equity transfer, and the
results of evaluations will serve as a frame of reference for the pricing of assets.
There are four basic approaches to evaluation, that is, income approach, cost
approach, market approach, and liquidation approach. Except the liquidation
approach that is applied in cases of bankruptcy, the other three approaches are
relatively applied in general use.
In terms of “Assets Evaluation Norms-Corporate Value,” the income approach is
a method of capitalizing or cashing in expected earnings so as to determine the value
of the target of evaluation [12]. The use of the income approach requires a compre-
hensive consideration about the previous operational condition of the target under
evaluation and the predictability of a future income, as well as reasonable assump-
tions about various factors in the impact on discount. The income approach is mostly
employed for evaluating the value of an enterprise as a whole but the result is prone
to the impact of subjective judgment or unforeseen elements.
The cost approach (called Asset-Based Approach in evaluation of corporate
values) is a process where the replacement costs of various assets to the targets
under evaluation are measured, calculated, added together, and reduced by the
factors in devaluation before the evaluated values come out. The cost approach
has a relatively large scope of application but is premised on whether the assets to the
targets under evaluation can be replaced, recognized, and evaluated, therefore
unsuitable for evaluating the targets with relatively much intangible assets as in
high-tech industries.
The market approach refers to the method of determining the values of the
targets under evaluation through the values of the benchmarks (e.g., consult and
follow listed companies or comparative cases of transactions), similar or compa-
rable to the targets under evaluation in an active and effective market of fair trade.
The above three approaches each have their own applicable conditions and
limitations, and should be flexibly applied according to conditions during actual
operation. In the asset evaluation of IC enterprises such as asset-light fabless ones
and those with heavy asset in the categories of materials and equipment as well as
pure-play foundries and packaging and testing enterprises, it is necessary to choose a
suitable approach to evaluation according to the characteristics in the properties of
the assets to different enterprises.
Apart from ledger assets, a typical fabless enterprise in the industry also owns
plenty of intangible resources including certifications, teams, services, and market-
ing resources, and the application of income approach can take into account more
comprehensively with intangible resources as well as the synergistic effect produced
between other assets within the enterprise, reflecting the value of the overall assets to
554 Y. Hu et al.

the enterprise in the future in terms of profitability. Therefore, in the evaluation of

such events as mergers and acquisitions that involve shareholders’ equities in an
enterprise in the category of design, the income approach is relatively used more
often. The cases of this type include Navinfo (stock code: 002405) buying out
AutoChips [13], Tongfang Guoxin (currently Unigroup Guoxin, stock code:
002049) buying out Shenzhen StateMicro Electronics, and so on [14].
The asset-based approach (cost approach) builds on corporate balance sheets,
separately evaluating the value of each asset, with the results serving as a
relatively highly objective basis and easy to be accepted by both the parties of
the seller and the buyer in such transactions as mergers and acquisitions. For
example, in the case of SevenStar Electronics (currently NAURA, stock code:
002371) buying out North Microelectronics, the evaluation company has adopted
the income approach and the asset-based approach. Given that China’s IC equip-
ment industry to which North Microelectronics belongs is still in its early stage of
development, it will take time for the industry as a whole to reach the interna-
tionally advanced level. Although the enterprise has a good potential for growth,
it is uncertain whether any technical breakthrough is made so as to establish a
core competitiveness and profitability. Therefore, in the final evaluation report,
the results from the evaluation of all the shareholders’ rights and interests with
the asset-based approach prevail [15].
If the target for evaluation has a certain number of comparable enterprises
(listed companies) in the capital market whose sizes, positions in the industry,
asset structures, and operational models are all similar to those of the target under
evaluation, the results delivered through the application of the market approach
and after certain corrections made to corporate developmental qualities and
corporate characteristics can reflect the judgment of the market on the general
value of the enterprise of the same type. For example, in the case of Jiangsu
Changjiang Electronics Technology (stock code: 600584) planning to buy out
Suzhou Long Telegram and New Investment, the evaluation company has chosen
the market approach and the income approach to evaluate all the shareholders’
rights and interests in Long Telegram and New Investment. Moreover, it is taken
into account that the market approach is based on the comparison of financial
operation and income status with comparable enterprises at the time of evalua-
tion, which can better reflect the value of a rational investment. Therefore, in the
final report, the results obtained with the market approach prevail [16].
In the stages of transaction, although the asset evaluation does not play a
decisive role, the results of the evaluation have great significance for reference.
With the rapid development in domestic IC industry, there are increasingly more
cases of mergers between and consolidation of enterprises. If the target enterprise
is comprehensively taken into account and a reasonable method is chosen to
comprehensively evaluate the value of the enterprise, it is helpful for a transaction
to proceed smoothly.
25 Investment and Financing of IC Industry 555

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Explor. 3, 76–79 (2002)
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net.cn/rsbd/scjs/201209/t20120914_59754.html
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December 30, 2011. Available: http://www.cas.org.cn/pgbz/pgzc/47398.htm
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the project for Navinfo to plan to buy out equities in AutoChips (Hefei), China Alliance
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plate¼szse&orgId¼9900012447&stockCode¼002405&announcementId¼1202325364&
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announcementTime¼2017-01-13
 Section IV
Integrated Circuit Production Lines
Richard Chang, Lei Jiang, Yibo Wang, and Yonghang Yu

Introduction

Integrated circuit (IC) is regarded as the “bread-and-butter” of modern industry with

technology level and manufacturing scale as the symbols of industrial competitive-
ness of national power. IC production lines and facilities have progressed rapidly
toward the “smart manufacturing” with full automation, artificial-intelligence (AI),
big-data analysis, etc.
This chapter covers the development history of IC production lines in China and
worldwide, as well as the knowledge related to the establishment of IC production
lines. The IC production line (or plant) is also commonly referred to as IC
manufacturing facility, wafer fabrication lines, or simply fab or Fab. It includes an
introduction of development history, site selection and methodology for environ-
ment impact assessment, design of IC production lines, clean room and air condition
systems, central gas and chemical supply systems and monitoring systems, plant
construction and management, energy saving and consumption reduction schemes,
hazardous chemicals management, waste water and solid material treatments, and
current status and trends of future IC production lines.
Development History of IC Production Lines
26
Janet Zeng

Contents
History of IC Production Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
History of IC Production Lines in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Abstract
This chapter overviews the development of IC production lines worldwide and
specifically the establishment of IC manufactures in mainland China. It started
with a few state-owned factories of discrete products and some institutions of
R&D and then gradually developed with the mass production capabilities by both
international-invested and domestic companies. Some of them are already among
the largest and most advanced IC factories in the world. Regarding the technology
nodes, as of 2020, there are two companies in China continuously investing on
the IC fabrication services at 14 nm technology node.

Keywords
Production line · Wafer · Fabrication · Mass production · Technology node

IC product lines have been continuously developing worldwide, starting from the
1960s, while in China it has a relative short history. Information for further reading is
found in references [1–4].

J. Zeng (*)
SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
e-mail: Janet.zeng@sienidm.com

© Publishing House of Electronics Industry 2024 559

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_26
560 J. Zeng

History of IC Production Lines

1960: H. H Loor and E. Castellani invented photolithography as an enabling

technology for modern IC production.
1963: F. Wanlass at Fairchild Semiconductor invented low-power circuit using
complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs).
1964: R Noyce at Fairchild Semiconductor invented planar IC technology. Soon
after, there were multiple semiconductor manufacturing lines established in the USA
using 1–200 (inches) of wafers.
1968: The first CMOS gate-array semiconductor product was manufactured by
Radio Corporation of America; Poly-Si replaced aluminum (Al) as the material of
gate electrode.
1970: Intel for the first time launched 1 Kb commercial Dynamic Random Access
Memory (DRAM) based on n-type MOS (nMOS) technology.
1971: Intel launched the very first microprocessor chip 4004.
1970s: Ion Implantation (II) technology, invented by W. Shockley and his
colleagues, began to be widely used in semiconductor manufacturing.
1980s: The USA started building 400 IC production lines. The low-power CMOS
technology with dual-doped poly-Si gate and self-aligned metal silicide process was
introduced and gradually became mainstream technology. The overall automation in
process equipment can greatly reduce the number of operators and also contamina-
tion to IC chips from operator’s handling. The IC production lines were maturing
gradually with wafer sizes available from 200 , 300 , 400 , and 5,00 to 150 mm and mainly
manual operations (e.g., wafer carrying, storing, loading/unloading to equipment,
executing processing recipes, etc.). To save operating costs and meet cleanliness
requirements, usually wall panels are used to separate areas between high and low
cleanliness.
1980s: 200 mm IC production lines using SMIF (Standard Mechanical Interface)
with microenvironment were established in operation. Chemical Process Polishing
(CMP) technology was invented and widely used for planarization to achieve the
required flatness in multilayer interconnection.
2000: In the beginning years, there were 300 mm IC production lines established
and in operation. Wafer cassettes with SMIF microenvironment became the main-
stream in IC production lines.
2007: Intel successfully adopted HKMG (high-k metal-gate) technology at 45 nm
technology node.
2011: Intel was first to manufacture FinFET devices at 22 nm technology node.
2020: The cylindrical gate-all-around (GAA) nanowire [1, 2], nano-sheet, and
3D-stacking transistor [3, 4] technologies are developing rapidly and expected to be
adopted at 5 nm node and beyond. See Table 26.1 for a summary of development
history of IC production lines.
26 Development History of IC Production Lines 561

Table 26.1 Development history of IC production lines

Year Wafer Company owns representative Representative Technology
built size IC manufacturing line products node
1958 0.7500 Texas Instrument Oscillator circuit About 100 μm
1964 1.2500 Fairchild p MOS integrated 25 μm
Semiconductor circuits
1968 200 RCA Double doped poly- 10 μm
Si gate CMOS
1971 300 Intel 1Kbit DRAM､4004 6 μm
microprocessor
1974 300 Intel 8080 microprocessor 5 μm
1980 400 Intel 8086/8088 3 μm
microprocessor
1982 500 Intel 286 microprocessor 15 μm
1985 150 mm Intel 386 microprocessor 1 μm
1989 200 mm Intel 486 DX CPU 800 nm
microprocessor
1993 200 mm Intel Pentium processor 600 nm
1995 200 mm Intel Pentium 350 nm
proprocessor
1997 200 mm Intel Pentium II processor 250 nm
1999 200 mm Intel Celeron processor 180 nm
2002 200 mm Intel Itanium 2, Pentium 4 130 nm
2003 300 mm Intel Pentium M Celeron 90 nm
M processor
2006 300 mm Intel Core 2/Celeron 65 nm
duoprocessor
2007 300 mm Intel Atom processor 45 nm
(HKMG)
2009 300 mm Intel Xeon 5600 series 32 nm
processor (HKMG)
2011 300 mm Intel Ivy Bridge processor 22 nm
(FinFET)
2014 300 mm Intel Broadwell-U 14 nm
processor (FinFET)
2017 300 mm Intel, Samsung, TSMC, and Cannonlake, System 10 nm
Global Foundries on (FinFET,
Chip (SoC) QWFET)
2018 300 mm Samsung, TSMC System on Chip 7 nm (FinFET)
(SoC) (estimated)
2020 300 mm Samsung, TSMC System on Chip 5 nm (GAA)
(SoC) (estimated)
562 J. Zeng

History of IC Production Lines in China

1960s: Many factories in China established semiconductor production lines using

domestic equipment for mostly discrete transistor products. Among those
established factories, there were better known ones, e.g., the 5th Shanghai Compo-
nents Factory, the 7th Shanghai Radio Factory, the 14th Shanghai Radio Factory, the
19th Shanghai Radio Factory, Suzhou Semiconductor Factory, Changzhou Semi-
conductor Factory, the 2nd, 3rd, 5th, 6th Beijing Device Factories, the 1st Semicon-
ductor Factory, and Xi’An 691 Factory of Ministry of Aviation.
1968: For the first time, ICs based on p-type MOS (pMOS) technology were
successfully developed in China by Shanghai 14th Radio Factory.
1970s: Yongchuan Semiconductor Research Academy, the 14th Shanghai Radio
Factory, and Beijing 878 Factory, all completed nMOS development and later
CMOS ICs that indicated the start of China’s development of CMOS.
1983: Wuxi Radio Components Factory (the 747 Factory) introduced a new
production line with 300 wafer from Toshiba Japan and operated in production. The
main products were IC components used in color and black-and-white televisions.
1988: Belling Microelectronic Manufacturing Company Shanghai which was
established on basis of the 14th Shanghai Radio Factory developed a new 400 IC
production line.
1988: Philips Semiconductor Shanghai was founded as a Sino-Dutch joint ven-
ture based on the 5th, the 7th, and the 19th Shanghai Components Factory with
licensed technologies. It established a new 500 production line.
1990: China Huajing Electronics Company performed the National Project 908 to
build a 150 mm IC production line.
1991: Shougang NEC Electronics Company established a 150 mm IC
production line.
1999: Shanghai Huahong NEC Electronics Company performed National Project
909 to establish a large-scale 200 mm IC production line with high automation level.
It adopted 0.35 μm technology for mass production of 64 Mb SDRAM.
2001: Semiconductor Manufacturing International Cooperation’s (SMIC) first
200 mm IC production line was in operation in Shanghai. It produced logic IC
chips with the most advanced 0.25 μm technology and also offered mask-making
services to clients. In the coming year, SMIC reached the goal of mass production for
0.18 μm logic IC chips that significantly boosted five technology nodes for China’s
IC production level. Currently, SMIC offers IC foundry service with CMOS tech-
nology from 0.35 um to 40 nm nodes. Nowadays, SMIC is recognized as one of the
most advanced foundries for IC manufacturing in China.
2003: Shanghai Hongli Semiconductor Manufacturing Corp. and Hejian
(Suzhou) Technology Company successively established 200 mm IC production
lines and are in operation.
2004: Taiwan Semiconductor Manufacturing Company (TSMC) and Advanced
Semiconductor Manufacturing Cor. (ASMC), Shanghai, started Fab construction
successively. TSMC is dedicated to foundry services for logic technology. ASMC is
26 Development History of IC Production Lines 563

dedicated to discrete power devices (e.g., Power MOS, power diodes, IGBT, SGE,
etc.)
2005: SMIC built China’s first 300 mm IC manufacturing line in Beijing and
provides IC foundry services with logic technology at 0.18 um, 90 nm, and 45 nm
nodes.
2006: Hynix (Wuxi) built a 300 mm IC production line for memory (DRAM and
Flash) products.
2007: 300 mm IC production line of SMIC (Shanghai) started in operation and in
mass production in 2008. It provides IC foundry services with logic technology at
45 nm and beyond.
2009: Wuhan Xinxin Semiconductor Manufacturing Company successfully
established a 300 mm IC production line offering foundry services of flash memory
and CMOS image sensor products.
2010: Shanghai Huali Microelectronics Corp. was founded and performed a main
improvement program for National Project 909 by establishing a 300 mm IC
production line with products in 90 nm/65 nm/45 nm technology nodes.

References
1. D. Xiao, G. Chen, R. Lee, et al., System and method for integrated circuits with cylindrical gate
structures, US, 8884363. Accessed 28 Sept 2010
2. D.Y. Xiao, M.H. Chi, D. Yuan, et al., A novel accumulation mode GAAC FinFET transistor:
Device analysis, 3D TCAD simulation and fabrication. ECS Trans. 18(1), 83–88 (2009)
3. S.B. Samavedam, J. Ryckaert, E. Beyne, K. Ronse, N. Horiguchi, Z. Tokei, I. Radu,
M.G. Bardon, M.H. Na, A. Spessot, S. Biesemans, Future logic scaling towards atomic channels
and deconstructed chips, in IEDM, (IEEE, San Francisco, 2020), pp. 1–10
4. A.K. Gundu, V. Kursun, 5-nm GAA transistor technology with 3-D stacked nanosheets. IEEE
Trans. Electron Dev. 69(3), 922 (2022)
Location and Environmental Impact
Assessment of IC Production Lines 27
Thomas Hsu

Contents
Guidelines for Selecting Locations for IC Production Plants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Environmental Evaluation of Air . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Environmental Evaluation of Surface Water . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Environmental Evaluation of Ground Water . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Environmental Evaluation of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Environmental Evaluation of Soil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Environment Risk Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Environmental Assessment Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Analysis of Contamination in IC Production Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
Contaminant and Treatment in IC Production Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Abstract
It is a complex process to properly assess the location and environmental impact
for the construction of an IC production line. The construction project should be
carefully planned under the guidelines of overall planning and regulations. This
chapter introduces all major factors of environment impact, including air, surface
water, ground water, noise, and soil. Then the environment impact can be
assessed by the four steps to identify impact factors, determine pollution factors,
set control requirements, and finally select specific indicators for testing and
evaluation. This chapter also lists common contaminants in mainstream IC
production processes with the control measurement for reference.

Keywords
Location selection · Environment assessment · Impact factors · Control
requirements · Contaminants

T. Hsu (*)
SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
e-mail: Thomas.hsu@sienidm.com

© Publishing House of Electronics Industry 2024 565

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_27
566 T. Hsu

The IC production lines with various equipment for manufacturing have significant
impacts on the surrounding environment. When selecting suitable locations for the
construction of IC production lines (or plants), many aspects shall be carefully
considered (e.g., the local environment, energy, city planning, etc.). There are
large volume of various chemicals, water, and gases used in IC manufacturing as
well as large amount of wastewater, gas, and solid waste produced. Therefore, it is
important to perform a thorough assessment of environmental impact before starting
a new project of IC production line.

Guidelines for Selecting Locations for IC Production Plants

According to “the Law of the People’s Republic of China on Urban and Rural
Planning,” the location of an IC production plant shall meet the development and
construction requirements of new urban areas with reasonable construction scale
and schedule. Municipal infrastructure and public service facilities shall be fully
utilized for not only strictly protecting natural resources and the ecological envi-
ronment but also displaying local characteristic features. According to “the Reg-
ulations on Site Selection Planning and Management of Construction Projects”
publicized by the State Planning Commission on August 23, 1991, the main basis
for site selection of construction projects are: (1) project proposals approval;
(2) coordination between construction projects and urban planning layout; (3) con-
nection and coordination between construction projects and urban transportation,
communications, energy, municipal administrations, and disaster prevention plan-
ning; (4) connection and coordination between supporting living facilities and
urban living and public facilities planning; and (5) potential pollution impact on
urban environment, and the coordination with the urban planning on environmen-
tal protection, including scenic spots, cultural relics, and historic sites. Relevant
guidelines and key points of selecting locations for IC production lines are shown
in Table 27.1.

Environmental Evaluation of Air

The environmental impact assessment of air predicts and evaluates the overall air
quality if the exhaust gas pollutants are discharged from the plant during construc-
tion and after in long-term operation. This assessment includes the investigation
and evaluation of the present air quality, demonstrates the feasibility of project
construction, proposes a location for the sewage outlet, formulates the production
management rules, and establishes the prevention and control measures for atmo-
spheric pollution. The permission to discharge pollutants from fixed sources can
provide a basis for meeting the required environmental air quality standards. The
investigation and evaluation of the present ambient air are based on the temporal
27 Location and Environmental Impact Assessment of IC Production Lines
Table 27.1 Guidelines and key points in selecting locations for IC production lines
Item
Environmental impact
Energy and resource supply
Hazardous chemical supply
and waste disposal
Pollution
Environmental hazards
Facility layout
Preexisting environmental
risks
567
Key points
Comprehensively consider two aspects: the impact of the
project on the neighboring and overall environment.
Ultrapurify water (UPW) is widely used in IC manufacturing,
which requires a comprehensive and in-depth analysis of the
water supply capacity and strategic location on the project site.
In water- or electricity-deficient areas, the feasibility of local
energy supply should be comprehensively and thoroughly
analyzed.
A large volume of hazardous chemicals are used in IC
manufacturing and a large volume of hazardous wastes are also
produced. Transportation and storage should be fully
considered, especially the safety protection measures and safety
distance of flammable, explosive, toxic, and harmful hazardous
chemicals
For IC projects where wastewater is directly discharged into
urban or park wastewater treatment plants, feasibility of the
treatment process, treatment capacity, and acceptance of the
project’s drainage water quality and quantity should be
considered. For projects where wastewater is directly
discharged into surface water, specific measures are needed to
ensure not increasing the load on the surrounding environment.
In addition, consider whether the local air pollution
concentration, noise level, and protection distance are up to
local standards, verify the living conditions of residents within
the protection distance, and implement company-wide
environmental safety protection measures and environmental
protection relocation programs Strict special emission limits for
air pollutants have been implemented in key areas under
environmental control in China, and the most feasible and
efficient pollution control technologies are required for
construction projects in order to achieve stricter emission levels
of pollutants.
Vibration effects on large-scale mechanical processing
enterprises, metro and other rail transit, corrosive gases in
large-scale metallurgical and chemical enterprises, etc., as they
all pose potential risks on the operation of an IC manufacturing
line.
Safe distance of exhaust gas emission from IC production line,
location and layout of CUB, environmental risks of chemical
depot within the facility, etc.
The investigation and evaluation on the environmental risks of
potential sites should include soil and groundwater properties.
Investigation and monitoring of soil environmental quality
should include at least two basic items: pH value and cation
exchange capacity. Nonmethane hydrocarbon (NMHC) and
characteristic pollution factors of toxic and harmful volatile
organic compounds, such as benzene, toluene, and xylene,
should be considered in the environmental air quality survey
and monitoring
568 T. Hsu

and spatial variation and distribution of the background value, while the impact
assessment is based on the temporal and spatial variation and distribution of the
concentration value superimposed with the background value and the maximum
predicted value of pollutants discharged from construction projects. The industry
standard “Technical Guidelines for Environmental Impact Assessment, Atmo-
spheric Environment” (HJ 22—2008) specifies the work grades, content, working
procedures, methods, and requirements of the atmospheric environmental impact
assessment as summarized below:

1. Confirm the criteria and scope of evaluation: According to HJ 22—2008, there

are three work grades for the assessment of atmospheric environmental impact as
shown in Table 27.2. The criterion for determining the work grade is to select 1–3
main pollutants and calculate the maximum ground mass concentration of each
pollutant as “Pi,” where i is the number of the selected pollutant. If the number of
pollutants is greater than one, choose the maximum P value (Pmax) and its
corresponding value of D10% (i.e., the furthest distance where the ground mass
concentration of pollutants reaches 10% of the standard limit). When there are
more than two pollution sources discharging the same pollutant in the same
project, the evaluation grade of each pollution source is determined separately,
and the highest one is taken as the evaluation grade of the project. The calculation
of Pi is as the following:

Ci
Pi ¼  100%
C0i
where Pi is the largest ground mass concentration of the “No i” pollutant (%); Ci
is the largest ground mass concentration of the “No i” pollutant (mg/m3) calcu-
lated by the model; and C0i is the environmental air mass concentration standard
of the “No i” pollutant (mg/m3).
2. Investigation and evaluation of environmental air quality: In order to under-
stand the ongoing status of pollutants discharged by construction projects, it is
necessary to investigate, monitor, and evaluate the preexisting and continuing
status of the air quality in the region where the construction projects are located.
HJ 22–2008 requires that the conventional pollutants and characteristic pollut-
ants (harmful and toxic substances) discharged from construction projects be
screened as monitoring parameters, e.g., nitrogen oxides (NOx), sulfuric acid
mist, fluoride, hydrogen chloride, chlorine (Cl), ammonia, nonmethane total
hydrocarbons, benzene, toluene, xylene, and so on. Generally, in the third grade

Table 27.2 The criteria of evaluation level

Work Grade Criteria
Grade I Pmin  80%, & D10%  5 km
Grade II Others
Grade III Pmax < 10% or D10% < the nearest distance between pollutants source and plant
boundary
27 Location and Environmental Impact Assessment of IC Production Lines 569

of assessment, there are 2–4 key points of evaluation, including the maximum
wind conditions in the dominant wind direction, the maximum ground concen-
tration of downwind emissions, the downwind ambient air sensitivity, and the
cross-wind ambient air sensitivity. If environmental air monitoring data of at
least 3 years are available and can meet the requirements of the impact assess-
ment of the project, the preexisting status assessment may not be necessary.
According to the results of the monitoring data, the single parameter pollution
index method is used to evaluate the present situation of environmental air
quality in the area of evaluation. When the pollution index Pi > 1, it shows that
the evaluation parameter in ambient air exceeds the standard pollution index
(Pi). The formula is as follows:

Ci
Pi ¼
Si
where Pi is the single factor pollution index of the “No i” pollutant; Ci is the
measured average mass concentration of the “No i” pollutant (mg/m3); Si is the
evaluation standard of the “No i” pollutant (mg/m3). With the calculated Pi, the
pollution level and variation trend as well as the existing environmental issues
and their causes can be analyzed for the area.
3. Impact prediction and evaluation: The atmospheric environmental impact
assessment shall be based on the corresponding evaluation parameters and criteria
(or target values). The work of impact prediction and evaluation mainly includes
the following five aspects. (1) collection, processing, and analysis of meteorolog-
ical observation data; (2) prediction of surface mass concentration, including
determination of prediction parameters, collection of surface meteorological data,
collection of high-altitude meteorological data, collection of topographic data,
determination of prediction models, preprocessing of forecast meteorological
data, and preprocessing of forecast points; (3) forecasting pollution source magni-
tude and frequency, including various scenario combinations; (4) prediction results
analysis, including maximum contribution values and impact assessment (hourly
and daily average concentration) under normal conditions, contribution values and
impact assessment at environmental sensitive areas under normal conditions, and
prediction of abnormal emission from projects; and (5) protection distance calcu-
lation of irregular emission. In summary, on the basis of the forecasting results and
evaluation of pollutant emission, the feasibility of the proposed project is concluded
and further suggestions for improvement are proposed.

Environmental Evaluation of Surface Water

In order to understand how the surface water quality is influenced by water

pollutant discharge from construction projects, it is necessary to investigate the
present condition and existing monitoring data; and if the data is insufficient, then
additional on-site sampling and monitoring is needed. The selection of water
570 T. Hsu

quality parameters mainly includes water temperature, pH value, dissolved oxygen

(DO), chemical oxygen demand (COD), and suspended solids (SS), such as
ammonia nitrogen, total nitrogen, fluoride, cyanide, anionic surfactant (sodium
alkylbenzene sulfonate), petroleum, total phosphorus, arsenic, chromium (hexa-
valent), copper, silver, nickel, tin, lead, zinc, manganese, etc. The standard index
method of single water quality is used to evaluate the present condition of surface
water quality.

1. The standard index method for general water quality parameters is:

ci,j
Si,j ¼
cSi
where Si,j is a unitized water quality parameter “i” at “j” sampling point; Ci,j is the
average measured concentration of water quality for parameter “i” at “j” sampling
point (mg/L); CSi is the evaluation standard of water quality parameter “i” (mg/L).
2. Standard index formula for calculating pH value,

7:0  pHj
pHO7:0, SpH,j ¼
7:0  pHsd
pHj  7:0
pH > 7:0, SpH,j ¼
pHsu  7:0

In the formulas, pHj is the measured value of pH at “j” sampling point; pHsd is the
lower limit of the evaluation standard of pH value; and pHsu is the upper limit of
the evaluation standard of pH value.
3. The standard index formula for Do is:

jDOf  DOjj
DOj PDOs , SDO, j ¼
DOf  DOs
DOj
DOj < DOs , SDO, j ¼ 10  9
DOs
468
DOf ¼
ð31:6 þ T Þ

where DOf is saturated dissolved oxygen concentration (mg/L); DOs is the

standard concentration of dissolved oxygen (mg/L); DOj is the dissolved
oxygen concentration (mg/L) at “j” sampling point; and T is the water tem-
perature ( C).
When the standard index of single water quality is greater than 1, it shows that
the water quality parameter is outside the bounds of the water quality standard;
then the specific items or multiples outside the standard shall be explained. The
requirements of surface water quality assessment scope, investigation period,
27 Location and Environmental Impact Assessment of IC Production Lines 571

sampling section, location, collection and treatment, water sample preservation

and analysis method, as well as evaluation criteria and content requirements are
all specified in the Technical Guidelines for Environmental Impact Assessment
(HJ/T23–93).

Environmental Evaluation of Ground Water

In order to understand the ongoing conditions of ground water (or groundwater)

environment at the site of the project, it is necessary to collect monitoring data of
the groundwater environment. Monitoring parameters include groundwater level,
pH value, total hardness, permanganate index, ammonia nitrogen, nitrate nitro-
gen, nitrite nitrogen, sulfate, total phosphorus, chloride, fluoride, cyanide, arse-
nic, iron, copper, zinc, lead, chromium (hexavalent), manganese, silver, tin,
nickel, total coliform bacteria, total bacterial count, etc. According to the statis-
tics of monitoring data, the single component evaluation method can be used to
evaluate the water quality according to the prescribed water quality classification
standards, or the standard index method can be used to evaluate the water quality.
The former explains the category of groundwater quality standard (GB/T
14848—2017) which belongs to the evaluation component. The latter adopts
the standard index method. Select whichever method is the best for the specific
situation. (1) The standard exponential expressions for general water quality
components are:

ci, j
Si, j ¼
cSi
where Si,j is the standard index of water quality component “i” at “j” point; ci,j is the
average measured concentration of water quality component “i” at “j” point (mg/L);
cSi is the evaluation standard of water quality component i (mg/L). (2) The standard
index formula for calculating pH value is as follows:

7:0  pHj
pHO7:0, SpH, j ¼
7:0  pHsd
pH j  7:0
pH > 7:0, SpH, j ¼
pHsu  7:0

where pHj is the measured value of pH at “j” sampling point; pHsd is the lower limit
of the evaluation standard of pH value; and pHsu is the upper limit of the evaluation
standard of pH value. When the index of individual evaluation criteria is greater than 1,
the water quality component is not within the bounds of the prescribed water
quality standards.
572 T. Hsu

The standard index method of groundwater quality evaluation generally adopts

the third class standard of “Groundwater Quality Standard” (GB/T 14848—2017).
The scope of groundwater quality evaluation, the location of groundwater, the
sampling of water quality, the frequency of monitoring, the requirements of deter-
mination methods, the evaluation criteria, and the requirements of evaluation con-
tents are all specified in the Technical Guidelines for Environmental Impact
Assessment (HJ610—2016).

Environmental Evaluation of Noise

In order to understand the acoustical environment quality at the project site

(or plant boundary) and sensitive areas, it is necessary to monitor the ongoing
acoustical environment status. According to the category of acoustic environment
functional areas within the evaluation scope and according to the “Acoustic
Environment Quality Standard” (GB 3096—2008), the method of meeting the
standards of monitoring points is evaluated. If the data are outside the bounds of
the standard, the number and distribution of data population shall be explained, and
the reasons shall be analyzed. Environmental noise monitoring method is specified
in “the Standard for Acoustic Environmental Quality” (GB 3096—2008). Require-
ments for monitoring sites, assessment scope, and evaluation contents are specified
in “Technical Guidelines for Environmental Impact Assessment” (HJ 24—2009).
There are many noise sources in the IC production lines, including chillers, fans,
pumps, cooling towers, and other power equipment. Based on the analysis of the
main noise sources of the proposed project, the noise level and its impact on the
surrounding environment during the production and long-term operation are pre-
dicted, analyzed, and evaluated.
For new projects, the contribution value of specified engineering noise is assumed
for the evaluation quantity, and the contribution value of factory boundary noise is
calculated by noise distance attenuation estimates according to the relevant param-
eters of project noise source and noise reduction measures. (1) Distance attenuation
mode of point source:

LA ðr Þ ¼ LA ðr 0 Þ  20lgðr=r 0 Þ

where r0、r is the distance (m) between the reference position and the predicted
point; LA (r) is the A sound level (dB) at the distance point source “r”; and LA(r0) is
the A sound level (dB) at the distance point source “r0.” (2) Multisource overlay
mode:

k
LP ¼ 10lg 100:1LPi
i¼1
27 Location and Environmental Impact Assessment of IC Production Lines 573

where k is the number of noise sources, LP is a synthetic sound level (dB (A) with
k attenuation values of noise sources, and LPi is the attenuation value of the distance
of the noise of the first noise source (dB(A)).
According to the predicted results, it is judged whether the noise at the factory
boundary can meet the requirements in the “Environmental Noise Emission Stan-
dard for Industrial Enterprises” (G 12348 – 2008). If the acoustical environmental
sensitive points are distributed in the evaluation range, the corresponding environ-
mental requirements in the “Acoustic Environmental Quality Standard” (GB 3096—
2008) can be judged by superimposing the monitoring values of the acoustical
environment status.

Environmental Evaluation of Soil

The main object of soil environmental assessment is the soil quality at the con-
struction site. In order to understand the preexisting status of soil quality at the site,
it is necessary to collect monitoring data of soil status or perform spot sampling and
monitoring. The monitoring includes the soil characteristics, the pollutants from
the proposed construction project, and the pollutants concerned by the local public
and environmental protection departments. Among them, moisture content, cation
exchange capacity, and pH values are the basic items to be measured. Additional
key control materials are also included: cadmium, chromium, mercury, lead,
copper, zinc, nickel, hexachlorocyclohexane (666), and DDT (di-p-chlorophenyl
trichloroethane). Sampling sites, sample collection, preparation, determination,
data processing, quality assurance, and quality control are performed in accordance
with the “Technical Specification for Soil Environmental Monitoring” (HJ/T
166—2004).
The environmental soil quality assessment method is the same as groundwater
quality assessment method. According to the statistics of monitoring data, single
component assessment method can be used to evaluate soil quality according to
classification criteria, or single pollution index and cumulative index methods can be
used to evaluate soil quality. The category of “soil environmental quality standard”
(GB 15618 – 1995) belonged to this component was explained by the single
component evaluation method. Choose the method best fitting the specifics of the
project and environment. The calculation formulas of single pollution index and
cumulative index methods are as follows: (1) individual pollution index of soil
pollutants denotes the measured values of soil pollutants/quality standard of
soil pollutants and (2) individual cumulative index of soil pollutants denotes the
measured values of soil pollutants/background values of pollutants. According to
the evaluation results, if there is no index outside the boundary of the standard, it can
be considered that the risk to human health of that evaluation index is acceptable,
and it can be preserved as historical data of the background value at the construction
site. If the soil at the construction site is polluted, the excessive pollutants will be
identified, and the risk assessment of the soil pollution will be initiated.
574 T. Hsu

Environment Risk Assessment

Project environmental risk assessment assesses the impact and damage to personal
safety and environment caused by predictable emergencies or accidents (generally
excluding man-made damage and natural disasters). These emergencies may cause
toxic, harmful, flammable, and explosive substances to leak, or new toxic and
harmful substances produced by emergencies during the construction and operation
of the project. The risk assessment will also put forward emergency prevention and
mitigation measures [1]. The purpose is to analyze and predict the potential risks of
construction projects.
A variety of special gases and chemicals are needed in the production of ICs.
Special gases can be divided into inert, corrosive, flammable/harmful, and alkanes.
Chemicals mainly include etching solutions, photoresist, degumming agent, devel-
oper and other mixed solutions, as well as hydrofluoric acid, nitric acid, hydrochloric
acid, sulfuric acid, and so on. These chemicals have certain environmental risks in
transportation, storage, and use. According to the “Technical Guidelines for Envi-
ronmental Risk Assessment of Construction Projects” (HJ/T 169 – 2004), the
working level of environmental risk assessment is divided into two levels, as
shown in Table 27.3.
Risk source analysis includes maximum credible accident analysis, probability
investigation of maximum credible accident risk, and determination of major acci-
dent source strength. According to the “Technical Guidelines for Environmental
Risk Assessment of Construction Projects” (HJ/T 169—2004), the abnormal model
is adopted to simulate and evaluate the leakage of major accident sources under the
condition of assumed serious and catastrophic accidents. Meanwhile, engineering
control measures, risk management measures, and accident emergency plans are
formulated. The flow chart of environmental risk assessment is shown in Fig. 27.1.

Environmental Assessment Factors

The assesment of environmental impact should firstly identify the environmental

impact factors (or parameters), determine the pollution factors, and put forward
control requirements through the analysis of process flow and pollution production

Table 27.3 Evaluation level (Level 1 and 2)

Highly toxic and General toxic Flammable and Explosive
dangerous hazardous flammable hazardous hazardous
substances substances substances substances
Major hazards Level 1 Level 2 Level 1 Level 1
Nonmajor Level 2 Level 2 Level 2 Level 2
hazard sources
Environmental Level 1 Level 1 Level 1 Level 1
sensitive areas
27 Location and Environmental Impact Assessment of IC Production Lines 575

Fig. 27.1 Flow chart of environmental risk assessment [1]

links, and finally select the factors for environmental impact to be tested and
evaluated for the project.

1) Identification of environmental impact factors: According to the “Guidelines

for Requirements and Use of Environmental Management Systems” (GB/T 2401
– 2016), environmental factors refer to the elements that interact with the
environment in an organization’s activities, products, and services. According
to the action attributes of the proposed project on environmental factors, envi-
ronmental impacts can be divided into favorable and unfavorable, long-term and
short-term, reversible and irreversible, direct and indirect, as well as cumulative
and noncumulative impacts. In environmental assessment, it is usually classified
according to the different acceptors in the categories of atmospheric and water
discharge, soil pollution, the use of raw materials, waste materials disposal, and
management. The main environmental impact factors of the construction project
during the construction period are construction dust, noise, and waste. The main
environmental impact factors after the construction period and in normal
576 T. Hsu

Table 27.4 Identification table of major factors of environmental impact in the operation period of
IC production lines [1]
Pollution factors
Environmental Waste Waste Solid Hazardous Hazardous
elements gas water Noise waste chemicals Storage waste
Atmosphere ● ● ●
Surface water ● ● ● ●
Ground water ● ● ● ●
Soil ● ● ● ● ●
Acoustic ●
environment
Environmental ● ● ● ● ●
risk

operation are hazardous waste materials and chemicals. The main environmental
impact factors during the operation period are shown in Table 27.4.
2) Pollution factors: The possible pollution factors (or parameters) are identified
and determined through the analysis of process flow and pollution production
links. Generally speaking, there are several kinds of pollution factors in the IC
industry. (a) Water pollutant control parameters: total 20 items including pH,
suspended solids (SS), chemical oxygen demand (COD), ammonia nitrogen, total
nitrogen, fluoride, total cyanide, anionic surfactant (LAS), petroleum, total phos-
phorus, total arsenic, hexavalent chromium, total chromium, total copper, total
silver, total nickel, total tin, total lead, total zinc, total manganese, etc. Among
them, the monitoring positions of total arsenic, hexavalent chromium, total
chromium, total lead, and total silver should be set at the outlet of the pollutant
pretreatment unit device. The monitoring location of other substances is set at the
total effluent outlet of the plant area. (b) Air pollutant control parameters: total
12 items, including hydrogen fluoride, hydrogen chloride, sulfuric acid mist,
nitrogen oxides, ammonia, chlorine, benzene, toluene, xylene, volatile organic
compounds (VOCs), tin and tin compounds, as well as lead and lead compounds.
Ammonia emission is implemented under “Odor Pollutant Discharge Standards”
(GB 14554 – 1993, while other control parameters shall implement the “Com-
prehensive Emission Standards for Atmospheric Pollutants” (GB16297 – 1996).
(c) Special toxicity exhaust gas control parameters: It is necessary to install point
treatment systems and control linkage systems on process equipment with special
toxic tail gas discharge and acidic or alkaline waste gas treatment systems for
further treatment and discharge. The main control parameters are HF, HCl,
Cl2, etc.
3) Screening of environmental impact assessment factors: The screening of
factors of environmental impact assessment is based on the main pollution
factors of construction project emissions, combined with the environmental
function requirements of the construction project location or the determined
27 Location and Environmental Impact Assessment of IC Production Lines 577

Table 27.5 Reference table for selecting factors for environmental impact assessment of IC
production line construction project [2]
Environmental
factors Evaluation factors
Atmospheric HF, HCl, H2SO4 (Fog), NOx, NH3, Cl2, benzene, toluene, xylene, VOCs
environment (total carbon), tin and tin compounds, lead and lead compounds, etc.
Surface water pH, SS, COD, ammonia nitrogen, total nitrogen, fluoride, total cyanide,
anionic surfactant (LAS), petroleum category, total phosphorus, total
arsenic, hexavalent chromium, total chromium, total copper, total silver,
total nickel, total tin, total lead, total zinc, total manganese, etc.
Acoustic Boundary (factory boundary, field boundary) noise, sensitive target noise
environment
Ground water pH, total hardness, permanganate index, sulfate, ammonia nitrogen,
nitrate, nitrite, chloride, fluoride, cyanide, arsenic, hexavalent chromium,
lead, silver, nickel, tin, copper, iron, zinc, manganese, total coliform
bacteria, total bacteria, etc.
Soil Arsenic, copper, lead, chromium, nickel, zinc and fluoride, etc.

environmental protection objectives. The selected assessment factors should be

able to reflect the main characteristics of environmental impact, the basic
situation of regional environment, the characteristics of construction projects,
and the characteristics of sewage discharge. Generally speaking, the environ-
mental impact assessment factors of IC production line construction projects are
shown in Table 27.5.

Analysis of Contamination in IC Production Line

There are various chemicals and gases used in the IC manufacturing. The chemicals
and gases commonly used in the main processing processes are listed in Table 27.6.
At the end of manufacturing process, most of these chemicals and gases will be
discharged into waste water or exhaust gas, except a small amount of chemicals or
physical reactions deposited on the wafer. According to the Handbook of Industrial
Pollution Source Production and Discharge Coefficient for the First National Pol-
lution Source Census (revised in 2010), the contents of relevant parts of IC industry
are listed in Table 27.7.

Contaminant and Treatment in IC Production Lines

IC products may have many production links, long process flows, many pollutant
discharge points, and complex pollutant components. The main types of waste gases
are toxic tail gases, acidic exhaust gases, alkaline exhaust gases, organic exhaust
gases, and soldering tin fumes. The main types of wastewater are ammonia-
578 T. Hsu

Table 27.6 Common chemicals and gases in IC production lines

Production
process Chemicals and gases
Wet clean HF/H2SO4/HNO3/HCl/NH3/H2O2/IPA/acetone/ethanol, etc.
Oxidation O2/TEOS
Gluing HMDS/PGMEA/PGME/2-EFA/EGMEA/MMP/DMAC/Methyl amyl
ketone/MEK/N-butyl acetate/xylene, etc.
Development TMAH/TEAH/Cyclohexanone, cyclopentanone, butanone, Xylene,
potassium hydroxide, etc.
Wet degumming Hydroquinone/SPM/NaOH/Acetone/IPA/EG/DMSO/MEA/NMP/BDG/
DGA/diethyl- lenediol amine/DMAC/HAD, etc.
Wet etch HF—NH4F/CH3COOH—NH4F/HF—HNO3—CH3COOH/H3PO4/
HNO3—H3PO4—CH3— COOH/H3PO4—HNO3—H2SO4—HF, etc.
Dry etch CF4/C2F6/C3F8/CHF3/CH2F2/BF3/SF6/BCl3/NF3/HF/HCl/HBr/Cl2/NO/
CHCl3/CCl2F2/O2/H2/CO2, etc.
Diffusion doping AsH3/B2H6/PH3/BBr3/BCl3/BF3/POCl3, etc.
Implant BF3/B2H6/AsH3/PH3/H2, etc.
CVD SiH4/SiH2Cl2/SiCl3/BF3/SiCl4/CF4/PH3/NO/N2O/NH3/HF/WF6/HCl/H2,
etc.
PVD SiH4/SiHCl3/SiH2Cl2/SiCl4/BCl3/TiCl4/WF6/TiF4/BF3/SF6/HF/HCl/HBr,
Ti/W/Mo/Cr/Pt/Ta/Co
Copper process Cu/CuSo4/H2So4/HCl/H2O4, etc.
CMP Dielectric Silica Polishing Agent-KOH/TMAH/NH3.H2O/C2H7NO, etc.
CMP
Metal Al2O3-CeO2-MnO-H2O2/Fe(NO3)3/C6H8O7/HF, etc.
CMP
Back thinning Silicon carbide grinding
Testing Silver glue/copper glue/solder paste (tin alloy + flux)/epoxy resin/N-methyl
pyrrolidone (NMP)/dimethylfuran (DMF)/bump metal materials (gold/tin/
titanium/chromium/nic- kel/tungsten/molybdenum/etc.)/electroplating bath
(gold/silver/tin/etc.)/CH4O3S/surfactant/HNO3/H2SO4/HCl/NaOH/IPA/
CH3COCH3, etc.

containing wastewater, fluorine-containing wastewater, grinding and scrubbing

wastewater, chemical polishing wastewater, copper-containing wastewater, and
heavy gold. These belong to wastewater, organic wastewater, acid and alkali waste-
water, etc. Main pollutants and their sources in IC production lines are shown in
Table 27.8. Referring to the “Design Code for Sewage Treatment and Reuse in
Chemical Industry” (GB 50684—2011), typical pollution control measures for IC
production lines are shown in Table 27.9.
IC or semiconductor manufacturing needs to deal with contamination monitoring
and analysis, further reading can be found [3].
 27

Table 27.7 Table of emission and discharge coefficient for IC manufacturing industry
Pollutant Pollution Terminal governance Emission
Product Raw material Process name Scale indicators Unit coefficient technology coefficient
Integrated circuit chip Silicon wafer, Integrated circuit 200 K Industrial t/piece- 345 Neutralization + 345
(200 mm) Wafers above) photoresist, etching chip manufacturing wastewater product chemical precipitation
solution volume
COD g/piece- 430 Neutralization + 135
product chemical precipitation
NH3-N g/piece- 90 Neutralization + 325
product chemical precipitation
total nitrogen g/piece- 90 Neutralization + 325
product chemical precipitation
Industrial m3/piece- 12650 Absorption + 12650
exhaust gas product adsorption method
volume
SO2 g/piece- 19 Absorption 025
product Direct combustion or 0225
catalytic reduction
NOx g/piece- 475 Absorption 95
product Direct combustion or 855
catalytic reduction
Location and Environmental Impact Assessment of IC Production Lines

Integrated circuit chip Silicon wafer, Integrated Circuit 200 K fluoride g/piece- 725 Absorption 18
(200 mm) (Wafers photoresist, etching Chip product Direct combustion or 162
above) solution Manufacturing catalytic reduction
(continued)
579
 580

Table 27.7 (continued)

Pollutant Pollution Terminal governance Emission
Product Raw material Process name Scale indicators Unit coefficient technology coefficient
H2SO4(fog) g/piece- 35 Absorption 58
product Direct combustion or 522
catalytic reduction
HCl g/piece- 100 Absorption 115
product Direct combustion or 1035
catalytic reduction
HW34 kg/piece- 17 – –
hazardous product
waste
waste acid
Integrated circuit chip Silicon wafer, Integrated circuit 200 K HW35 kg/piece- 045 – –
(200 mm) (Wafers photoresist, etching chip manufacturing hazardous product
above) solution waste
(Alkali waste)
HW42 kg/piece- 145 – –
hazardous product
waste
(waste organic
solvents)
Note: The coefficient of discharge and production of 200 mm wafers is shown in the table. If the disc is 300 mm, the output and discharge coefficient of the
discharged disc is equal to the output and discharge coefficient multiplied by 12 in the table. If the wafer is 200 mm or more regardless of specifications, the
output and discharge coefficient of the wafer is equal to the output and discharge coefficient of the wafer in the table
T. Hsu
27 Location and Environmental Impact Assessment of IC Production Lines 581

Table 27.8 Main pollutants in IC production lines and their main sources
Pollution source Major pollutants Major sources
Waste NH3-N Alkali, suspended solids, ETCH、CMP、AEX
water ammonia nitrogen, total nitrogen,
and fluoride
F Acid, alkali, suspension, ammonia ETCH, SEX (include POU)
nitrogen, total nitrogen, fluoride,
total phosphorus
Waste CMP Alkali, suspended solids, CMP
water ammonia nitrogen, total nitrogen,
and copper
CMP Alkali, suspended solids, and Back thinning and chip cutting
copper
Cu Acids, suspended solids, and ECD,CMP, TAB packaging
copper technology
solvent Acid, alkali, suspended matter, development and degumming
organic matter
Heavy Acid, alkali, suspension, copper, Metallized film etching,
metal zinc, silver, tin, lead, chromium, packaging pin electricity lating,
cyanide, total phosphorus, total bump plating, and etching
nitrogen, fluoride
Acid-base Acid, alkali, suspended matter, Degumming, etching, ultrapure
wastewater COD-Cr, NH3-N, total nitrogen, water station, washing tower,
petroleum, and anionic surfactant package flux cleaning, equipment
(LAS) maintenance, etc.
Waste toxicity Arsene, phosphane, borane, Oxidation, dry etching, diffusion,
gas silane, silicon tetrachloride, chemical vapor deposition, and
dichlorodihydrosilane, boron ion implantation
trichloride, boron trifluoride,
nitrogen trifluoride, carbon
tetrafluoride, ammonia, hydrogen
chloride, chlorine, hydrogen
bromide, and hydrogen fluoride
SEX Hydrogen fluoride, hydrogen Degumming, etching, copper
chloride, nitrogen oxides, sulfuric deposition, POU tail gas,
acid mist, and chlorine packaging, and electroplating
AEX ammonia Etch, CMP
VEX VOCs (Benzene, toluene, xylene, Coating, degumming, etching,
isopropanol, acetone, etc.) cleaning, and sealing
Solder Tin and lead Bumping and packaging
fume
582 T. Hsu

Table 27.9 Typical pollution control measures for IC production lines

Pollution source Governance measures
Waste NH3-N Steam (hot air) stripping + acid absorption, sodium hypochlorite
water oxidation, etc.
F Flocculation sedimentation method
CMP The effluent is fed into the neutralization pond and the final
discharge is up to the standard allowable volume. The effluent is fed
into the treatment system of ammonia-containing wastewater or
fluorine-containing wastewater
CMP Filtration, coagulation, and sedimentation
Cu Biochemical treatment and chemical oxidation
solvent Ion exchange resin treatment, electrolytic precipitation + ion
exchange resin treatment, chemical flocculation precipitation, etc.
heavy metal Ion exchange resin treatment, electrolytic precipitation + ion
exchange resin treatment, chemical flocculation precipitation, etc.
Acid-base Acid-base neutralization treatment
wastewater
Waste toxicity POU+central scrubbing tower. POU devices include combustion +
gas washing devices, countercurrent water elution/plasma-water
removal system, electrothermal oxidation/catalytic decomposition,
three-stage water washing, adsorption, high-temperature pyrolysis-
activated carbon adsorption washing
SEX Acid spray absorption method
AEX Alkali spray absorption method
VEX Water spray absorption + activated carbon adsorption, activated
carbon adsorption, Catalytic combustion, zeolite runner
concentration combustion and storage, thermal incineration (RTO),
regenerative catalytic combustion (RCO), condensation,
absorption, etc.
Solder fume Alkali spray absorption method, activated carbon fixed bed
adsorption method, high-density fiber filter (HEPA) +activated
carbon absorber (filter), and so on

References
1. State Environmental Protection, Administration Technical Guidelines for Environmental Risk
Assessment of Construction Projects: HJ/T169–2004 [5] (China Environmental Science Press,
Beijing, 2005)
2. Environmental Engineering Evaluation Center of the Ministry of Environmental Protection,
Environmental Impact Assessment of Metallurgical Machinery and Electricity (Environmental
Science Publishing in China, Beijing, 2012)
3. J.-L. Baltzinger, Bruno delahaye, contamination monitoring and analysis in semiconductor
manufacturing, in Semiconductor Technologies, (2010). https://doi.org/10.5772/8561
Designing IC Production Lines
28
T. C. Wang

Contents
Technology Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Investment and Expenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Buildings and Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Green Plant Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
Automated Material Handling Systems (AMHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Water Supply and Drainage Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Fire Safety System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Power Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Ultrapure Water System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Wastewater Treatment System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Facility Monitoring and Control Systems (FMCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Hook-Up System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Abstract
The key component in designing the IC production line is the manufacturing
equipment which is 70–80% of overall project investment. Meanwhile, the
required manufacturing equipment can vary significantly based on different
product categories and technologies. This chapter provides an overview of
essential aspects of designing a well-functional IC production line. It includes
main buildings and structures, green plant design concept, green building evalu-
ation and certification system, automated material handling system (AMHS),
water supply and drainage system, well-equipped and effective fire-fighting
systems, power systems, ultra-pure water system, wastewater treatment systems
for five different chemical-based wastewaters, facility monitoring and control
system (FMCS) for real-time status, and also the hook-up system connecting
manufacturing equipment with all required conditions.
T. C. Wang (*)
SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
e-mail: Tc.Wang@sienidm.com

© Publishing House of Electronics Industry 2024 583

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_28
584 T. C. Wang

Keywords
Manufacturing equipment · Green buildings · Automated material handling
system · Water supply · Fire-fighting system · Power supply · Ultrapure water
system · Waste-water treatment system · Facility monitoring and control system ·
Hook-up system

Technology Considerations

ICs can be classified into 2 main categories, that is, digital ICs and analog ICs.
Different IC products are designed and manufactured by different technologies; if
using line-width as a parameter, technology can be from the early 5 um node to the
latest under 7 nm process nodes; if using wafer substrate size as a measure,
technologies are mainly in 150 mm, 200 mm, 300 mm generations, and 450 mm
generations in the future. The investment amounts of a production line can be easily
from tens of millions up to billions of dollars with clean rooms of various sizes from
hundreds of square meters to several tens of thousands of square meters; therefore,
the selection of a suitable manufacturing process and equipment set is a key fab
design task. The design of production lines should be based on product types and
combination of products, maximum monthly capability, production cycles, invest-
ment capitals, and long-term development goals to decide processes and
corresponding equipment sets.
Regarding the production nodes at line-width of 0.13 μm and larger, they are
mainly in 150 mm and 200 mm fabs; while for line-width 90 nm and under, it is
mainly in 300 mm fabs. The processes of producing IC chips is very complicated, it
includes over 1000 steps, generally it can be divided into front-end and back-end
processes. The front-end-of-line (FEOL) process is used to form the active and
passive elements, including cleaning, thin film, photolithography, etching, ion
implantation, etc. The back-end-of-line (BEOL) process is used to interconnect IC
elements and form protection layers, including photolithography, etching, cleaning,
metallization, chemical mechanical polishing (CMP), etc. The mixing of the BEOL
and FEOL equipment shall be avoided to prevent metal contaminating and
degrading electric characteristics.
Regarding production lines with 100 mm and 150 mm wafer sizes, generally open
style fab is adopted. As the dust and air quality in the operating area affects device
characteristics and yields, the requirement of air cleanness is higher; thus the
operating area is normally separated from the equipment areas by wall panels.
Further, the use of SMIF (standard mechanical interface) boxes as clean micro
environment for device wafers is the main stream in 200 mm and 300 mm wafer
fabs. In early days, 200 mm wafer fabs were mainly manually operating the wafer
transportation, storage, and distribution; modern 200 mm and 300 mm wafer fabs
use automated material handling system (AMHS) [1] with merits of effective use of
clean space, lowering handling work for operators, and reducing human errors. In
some of the 300 mm wafer fabs, the wafer transfer system can be extended to
28 Designing IC Production Lines 585

different production areas by utilizing the overhead hoist transfer (OHT) and deliver
wafers to equipment side directly. Future AMHS system can further improve
production speed, cycle time, and responses to fab needs.
As the IC production technology develops further, the corresponding packaging
technologies also accelerated. Packaging not only provides interconnection of the IC
chips, but also provides mechanical and protection to the chips for normal operation
with stability and reliability.
Before the 1980s, the most popular packages were the drop-in-hole insertion with
TO and dual-in-line package (DIP) with process steps of sort testing, wafer thinning,
dicing, die attachment, cleaning, encapsulating, assembly, solder reflow, and final
test, etc. Since the 1990s, the ball-grid-array (BGA) packaging and chip-size-pack-
age (CSP) were developed rapidly with main types of BGA, CSP, Wafer Level Chip
Scale Package (WLCSP), and System in Package (SIP). The main process steps
include intermediate testing, thinning, scratching, adhesive, cleaning, plastic sealing,
assembly, reflow soldering, marking, testing, packaging, etc. Since the late 1990s,
packaging technology progressed to the era of 3D packaging of stacking multiple
chips through vertical thru-Si-via (TSV) with advantages of reduced package size
and weight and improved signal transmission speed and power. In recent years, 3D
packageing technology is maturing rapidly with technology advancement in coating,
photolithograph, sputtering, re-coating, electrio-plating, solder reflow, testing, mark-
ing, etc.

Investment and Expenses

Project investment refers to the total costs to complete and bring the proposed project
into operation, including project costs, costs of engineering construction, reserve
funds, interest in construction period and liquidity funds. (1) Project costs include
purchase and installation fee for production equipment and instruments (e.g., all
configuration fee, freight and miscellaneous expenses, installation fee), cost of
acquisition and installation of power facilities (e.g., clean room and general electro-
mechanical systems, ultrapure water and wastewater treatment, special gas supply
and distribution, chemical supply and distribution, high and low voltage variable
power distribution, uninterruptible power supply, emergency diesel power genera-
tion system, fire extinguish system, security system, other electromechanical sys-
tems, etc.), and construction fee (e.g., cost of building and outdoor works for plant
and ancillary facilities). The major portion of the project costs is the process
equipment/tools for about 70–80% of the total investment. (2) Other engineering
construction cost usually accounts for about 2% ~ 5% of the total investment and
includes many items (e.g., land requisition fee, construction unit management fee,
upfront consultation fee, environmental evaluation fee, occupational safety
pre-evaluation fee, occupational hazard pre-evaluation fee, social stability evaluation
fee, energy saving assessment fee, soil and water conservation program fee, radiation
protection evaluation fee, trial plan fee, consultation fee, survey and design fee,
project supervision fee, investment supervision fee, bidding agency fee, city
586 T. C. Wang

supporting fees, office facilities and training fees, various audit and testing fees,
engineering insurance premiums and trial production fees, etc.) (3) The reserve
funds usually account for 2% ~ 5% of the total investment and includes the reserve
funds for the basic and price increase. The basic reserve funds refer to a design
change, no increased costs due to resistance and recovery at the end of excavation
and acceptance at the time of acceptance of concealed works, etc. The reserve funds
for price increase refer to project cost changes due to the change of prices of labor,
materials, construction machinery, etc., during the construction period. (4) Interest in
the construction period usually accounts for about 1–2% of the total investment. It
refers to the interest occurring during the construction period in the fixed assets (e.g.,
the payment of bank loans, export credits, bonds and other borrowing interest and
financing costs incurred). (5) Liquidity usually accounts for about 2–5% of total
investment. It is generally calculated using a sub-detailed estimation method based
on the minimum turnaround days for accounts receivable, inventory, cash, and
accounts payable. For domestic projects, in accordance with bedding liquidity,
foreign and joint venture projects are calculated on the basis of full liquidity.

Buildings and Structures

An IC production line (or fab) mainly includes production plant and clean room,
power plants, office buildings, substations, raw material warehouses, hazardous
chemicals warehouses, bulk gas stations, and silane station, etc., as illustrated in
Fig. 28.1. (1) Production plant and clean room mainly layout the process equipment
and testing, experimental and other equipment in clean room, but also layout the new

Fig. 28.1 Diagram of building composition of IC production line

28 Designing IC Production Lines 587

air room, exhaust system, power supply and distribution, ultra-pure water and waste-
water treatment, and chemicals and special gas systems. (2) The building floor plane
and space layout shall be determined according to the planned manufacturing
technologies. As an example, a 300 mm wafer fab for 28 nm node, the maximum
production capacity is 35,000 wafers per month with clean room area of about
9000 m2 and building of 3 layers (local 4 layers). The main structure of the plant
should adopt a combination of reinforced concrete structure, steel structure or
2 structures with large space and large span column mesh, and should have the
performance of seismic, anti-micro vibration, fire prevention, sealing, waterproofing,
temperature deformation control, and uneven settlement. (3) Power plants mainly
layout those cooling tower system, cold/hot water unit, ultrapure water preparation
system, and wastewater treatment system. Because of the large load, the plant
structure should adopt reinforced concrete structure. (4) Office buildings are mainly
for the fab supporting, R&D, production management, administration, personnel,
safety departments, also for café, clinic, parking, and other auxiliary functions.
Office buildings are generally designed according to civil building norms and
usually connected with a fab and conveniently accessible by employees. (5) Power
substations are in an outside configuration and allocated per wafer fab capacity. The
inlet line of power supply and distribution systems may use voltage levels of 220 kV,
110 kV, 35 kV, and other voltage levels. (6) Raw material warehouse mainly stores
the Class B or C materials and others in production process. Hazardous chemicals
warehouse mainly stores class-A dangerous goods materials.

Green Plant Design

In China, the concept of green plant design starts from residential and public
buildings. The evaluation standard introduces the weight scoring method, which is
determined by the score of different provisions according to 8 indexes, for example,
land saving and sustainable development site, energy saving and energy utilization,
water saving and water resources utilization, use of material and materials resources,
outdoor environment and pollutant control [2], indoor environment and occupational
health, operation management, technological progress and innovation, etc. The
levels of green industrial buildings are “one star” (if score is rated less than 55 points
but not less than 10), “2 stars” (if between 55 and 70 points), and “3 stars” (if above
70 points).
Green building evaluation system is widely used in the design of green IC fabs
based on the Leadership in Energy and Environmental Design (LEED) building
Rating System for evaluation. LEED was developed by the United States Green
Construction Council and it is mainly based on the sustainability of sites, the use of
water resources, energy and atmospheric environment, materials and resources, the
quality of indoor environments, and the six indicators of innovative design. More
than 30 evaluation sub-keys are subdivided under these indicators. In LEED (V3.0)
the regional priority content is the reward score. LEED system for a total of
110 points, according to the total score, there are different levels, for example,
588 T. C. Wang

Table 28.1 LEED distribution of different certification systems

LEED-NC LEED-CS LEED-EB LEED-CI
Project points points points points
Sustainable Venues 0 ~ 26 0 ~ 28 0 ~ 26 0 ~ 21
Water Resources Utilization 0 ~ 10 0 ~ 10 0 ~ 14 0 ~ 11
Energy and Atmospheric 0 ~ 35 0 ~ 37 0 ~ 35 0 ~ 37
Environment
Use of Materials and Resources 0 ~ 14 0 ~ 13 0 ~ 10 0 ~ 14
Indoor Environmental Quality 0 ~ 15 0 ~ 12 0 ~ 15 0 ~ 17
Innovative Design 0~6
Regional Priority 0~4

Certified level (40 ~ 49 points), Silver level (50 ~ 59 points), Gold grade (60 ~ 79
points), and Platinum level (80 ~ 110 points) four levels. The score distribution of
LEED certification systems is illustrated in Table 28.1.

Automated Material Handling Systems (AMHS)

In conventional wafer fab, the handling of wafers and process materials is performed
by using trolleys and human handling. As the wafer size increases from 150 mm to
300 mm, the mass of fully loaded wafer box (Front Opening Unified Pod, FOUP) has
increased [3] to about 8.3 kg (somewhat too heavy for manual handling with safety
and reliability). Furthermore, the use of automated material handling system
(AMHS) [4–6] in the wafer fab becomes a trend with proven advantages in product
yields and cleanliness. The AMHS systems include the within process area (intra-
bay) and process intervals (inter-bay) handling systems. The operation system is also
composed of 2 parts. After continuous exploration and optimization, the AMHS
systems have developed to be fully automatic. The (intra-bay) handling systems refer
to the wafer handling systems between equipment, or between the equipment and
storage systems (Stocker) in the same production area (Bay), mainly through the air
truck (i.e., overhead hoist transports, OHT) for automatic wafer handling. The
process interval (inter-bay) handling systems mainly refer to the wafer handling
systems in between different production areas. During the pre-development period
of AMHS systems, the intra-bay handling systems are performed by OHT; while the
inter-bay process interval handling systems are performed by the air to and from the
transport vehicle (i.e., Overhead Shuttles, OHS). The storage systems (stocker) are
used for the storage of wafers, but also for the wafer handling within process area
and in-between process areas (i.e., as a bridge between the inter-bay and intra-bay
systems). The state-of-art AMHS system can perform wafer transport completely by
OHT (i.e., tool to tool mode) with the storage system only for storage, together with
the newly added storage space in the air (i.e., under track storage, UTS) also
providing storage space for wafers in fab. AMHS systems can save manpower,
reduce particles, maximize the use of clean room space, ensure efficient operation of
28 Designing IC Production Lines 589

wafer cassette management, automate production control system, shorten production

cycles, and improve capacity utilization of equipment.

Water Supply and Drainage Systems

The water supply and drainage system is the general name of the facilities that
provide clean water and remove sewage for the need of people’s living as well as
for production equipment. It mainly includes water treatment, drainage, rainwater
harvesting, and domestic sewage collection and treatment systems. IC production
lines also produce wastewater, and their treatment systems are described later
(see 10). (1) Water supply systems refer to the overall water intake, conveyance,
quality treatment, and distribution facilities. Water supply systems are divided into
domestic water supply and production water supply systems. Municipal tap (city)
water is used for domestic water supply. The domestic water tanks need to be
designed as 2 tanks to ensure the normal water supply during the annual cleaning
period. Recycled (or reclaimed) water shall be used as much as possible and
gradually replacing the use of city water. (2) Drainage systems refer to the
collection, transportation, water quality treatment, and discharge of drainage
facilities, mainly including domestic sewage drainage and air condition condensa-
tion drainage collection. Domestic sewage mainly includes toilet, laundry room,
hand washing, and kitchen drainage. Domestic sewage is discharged into the
domestic sewage treatment system. Air conditioning condensate is collected and
used as water for production. (3) Rainwater harvesting system refers to the roof and
road rainwater collected through rainwater pipelines into rainwater harvesting
ponds for storage. After filtration, it can be used for watering as green water.
(4) The main treatment objects of domestic sewage collection and treatment system
are ammonia nitrogen, phosphorus, biochemical oxygen demand (BOD), and
chemical oxygen demand (COD) in sewage. After treatment by biochemical
methods, the domestic sewage is discharged from the discharge port to the munic-
ipal sewage pipe network (if all these parameters meet the national environmental
emission standards), and finally into the municipal sewage treatment plant for
unified treatment and utilization.

Fire Safety System

Particularly, once a fire in fab occurs, it may be spreading fast and seriously
damaging many equipment in clean room as chain effects. Furthermore, it is
usually accompanied by explosion, toxic gas leakage, and so on. It is very difficult
to rescue and extinguish the fire. Therefore, well-equipped and effective
firefighting systems are essential for personnel and property safety: (1) Building
Fire Protection systems: It is composed of fire detection and alarm, fire control,
combustible gas detection and alarm, and electrical fire monitoring, together with
automatic fire extinguishing system, smoke prevention system, and fire separation
590 T. C. Wang

and other fire protection facilities to form a complete set of building fire protection
systems. When a fire hazard occurs, the building fire protection system can be the
first to make alarm and response, start the relevant fire control equipment, extin-
guish the initial fire and prevent the spread of fire, while giving personnel sufficient
time for evacuation and emergency response. (2) Fire water supply and fire
extinguishing facilities: They are set up in the buildings and facilities according
to fire resistance grade, the nature of use, fire hazard, and so on. The fire water
supply systems in IC production line generally include indoor and outdoor
hydrant, automatic sprinkler, water spray fire extinguishing systems, etc., to ensure
that the initial fire can be effectively curbed. All the fire water supply systems and
fire extinguishing facilities such as alarm valve sets, pipe fittings, nozzles, and
other key products should meet the domestic fire-related standards, and should
meet the international UL (Underwriter Laboratories Inc.) certification and FM
(Factory Mutual) Standards for certification. (3) Carbon dioxide gas fire
extinguishing system: It is mainly used in the IC plant where water supply is
not proper e.g. rooms for power distribution, computer, uninterruptible power
supply, waste solvent collection, etc.). For areas where people often work or
enter and leave, a non-toxic, harmless, low concentration of sevoflurane gas fire
extinguishing system is preferable. A collation of the common fire extinguishing
methods for IC plant is shown in Table 28.2. (4) Smoke prevention system: The
buildings should be equipped with the necessary anti-smoking or smoke exhaust
facilities to ensure the smooth evacuation and safe haven of personnel in the
building at the time of the fire, and the timely removal of toxic and harmful flue
gas and heat from the fire site to prevent further spreading of the fire for minimizing
the loss of fire. (5) Very early fire detection system: IC plant, clean room,
substation, computer room, and other important areas should be equipped with a
high sensitivity very early fire detection system. The fire detection equipment can
actively monitor and analyze air samples with smoke particles in early stage. If
smoke particles are detected, an immediate alert will be issued at a very early stage
to control the occurrence and spread of the fire. (6) Building fire prevention and
safety evacuation: Clean room fire resistance level should not be less than
2 grades. The ceiling material should be non-combustion body, its refractory
limit should not be less than 0.25 h. The straight distance from any point in the
plant to the nearest safe outlet shall be in accordance with the requirements in
Table 28.3. (7) Fire Emergency Broadcasting System: It includes emergency, fire
linkage, and general business broadcasting functions. After the fire, the fire control
room can make emergency broadcast to corresponding areas, play pre-recorded
voice/instructions, staffs can also make broadcast through microphones, remote
command fire extinguishing, and organization of personnel for safe evacuation.
Fire protection systems play an extremely important role for personnel and prop-
erty safety, and plans for regular maintenance and repair tests should be developed
to ensure the safe and effective operation of the system.
 28

Table 28.2 Common fire extinguishing methods for an IC production line

Carbon dioxide Automatic
Indoor Dry powder Carbon automatic fire water Water mist fire
fire Outdoor fire dioxide Fire extinguishing sprinkler extinguishing
Designing IC Production Lines

Zone name hydrant hydrant extinguisher extinguisher equipment equipment equipment

Outdoor √
Cleaning Room √ √ √
Central Power Station √ √ √
Cooling Tower √ √
Electrical Equipment Room √ √ √
Gas Supply Room √ √ √
Solvent Supply Room √ √ √ √
Waste Solvent Collection Room √ √ √
Chlorine hexafluoride Supply Depot √ √ √
Chemical Warehouse √
Silane Supply Station √
591
592 T. C. Wang

Table 28.3 Straight distance from any point in the plant to the nearest safe exit (unit: meter)
Production
Categories Refractory grade Single layer Multilayer Top Basement
A Primary and secondary 30 25 – –
B Primary and secondary 75 50 30 –
C Primary and secondary 80 60 40 30
C Level III 60 40 – –
D Primary and secondary Unlimited Unlimited 50 45
Level III 60 50 – –
Level four 50 – – –
E Primary and secondary Unlimited Unlimited 75 60
Level III 100 75 – –
Level four 60 – – –

Table 28.4 Power Load grading

Load
level Definition
Level I Level is consistent with one of the following:
(1) When the interruption of power supply will result in personal injury or death
(2) When the interruption of power supply will cause significant economic losses
(3) Interrupting power supply will affect the normal operation of important power
units
Level II Meets one of the following conditions:
(1) When the interruption of power supply will cause greater economic losses
(2) Interrupting power supply will affect the normal operation of more important
power units
Level III When the impact of power supply interruption does not belong to level I and level II
load, then it is level III power load

Power Systems

The power systems for IC production lines shall cover the following aspects:
(1) Load level: The power load should be graded according to the requirements
for the reliability of power supplies and the degree of impact on personal safety and
economic loss when power supply is interrupted as shown in Table 28.4. The electric
load grade of IC production room is generally more than load level 2, using 2 power
supplies. When there is a problem with the first power supply, the second power
supply can power the plant load through the contact switch as shown in Fig. 28.2.
(2) Voltage level: reasonable supply voltage should be determined according to the
local power grid structure and plant load capacity. Inlet power supply voltage has
220 kV, 110 kV, 35 kV, 10 kV, and so on. The low-voltage distribution design for IC
production line should meet the requirements of production process equipment and
power equipment. (3) Sulfur hexafluoride sealed combination electrical appli-
ances: The sulfur hexafluoride (SF6) gas insulation switch (GIS) is mainly used for
electrical circuits with voltage levels of “division” and “fit” 10 kV and above. The
28 Designing IC Production Lines 593

Fig. 28.2 Illustration of power system architecture in IC production lines

GIS switch is filled with SF6 gas for better insulation and arc extinguishing capa-
bility. (4) High voltage power transformer (oil immersion): IC production plant
generally uses oil-immersed power transformer to convert high voltage level to low
voltage level, and then from medium voltage cabinet to each sub-substation. The
main electrical protection of oil-immersed transformer is gas protection, longitudinal
differential protection, overcurrent protection, etc., and oil immersion transformer
has the function of on-load voltage regulation capability. (5) Closed automatic
switching switch: Under normal circumstances, the load is powered by municipal
electricity. When the municipal power outage, the load will automatically be
switched to the emergency power supply. When the municipal power is restored,
the load is automatically cut back to the municipal power supply, and then the
emergency power supply is off. Each closed-type automatic switching switch
(Closed Transition Transfer Switch, CTTS) should include a power switch unit
and a control module that is wired in the disk for complete automated operation.
The CTTS voltage is rated on both sides and is instantly connected within an allowed
range for constant electrical load (closed-circuit) switching. The maximum connec-
tion time is 100 ms. (6) Uninterruptible power supply (UPS) system: Some
devices have special requirements for power switching time, for example, the
municipal electricity and emergency power supply switching time needs to be in
millisecond (ms) level, and needs to set up the UPS system with power supply time
no less than 5 min. When a municipal power outage occurs and before the diesel
generator set starts, the plant is powered by UPS. Until the voltage of the diesel
generator set is stable or the municipal electricity returns back to normal power level,
594 T. C. Wang

the UPS stops supplying power. (7) Reactive power compensation and harmonic
control: The facility for IC production line, if not meeting the requirements of the
power supply environment, should select a reactive power compensation device to
change the power supply environment. The capacitor set should be in the substation.
Reactive power compensation device mainly includes main circuit breaker (or fuse
switch), automatic power factor regulator, electromagnetic contactor and fuse, dry
capacitor and 6% inductor, box and wiring, in-disk lighting, and control switch. If
the system harmonics exceed national standards or have an impact on downstream
equipment, it is necessary to implement active or passive filters to improve power
quality. (8) Lighting: The workplace should use general lighting, when the users
have different requirements for different areas within the same workplace, it is best
to use different illumination of the light source. When an area or a special object
needs to have strong illumination, it is best to use focused lighting. Ordinary lighting
should be used in normal workplaces or other auxiliary places without special needs.
Important places (e.g., clean rooms, substations, fire pumping stations, and fire
control rooms) should be guaranteed with adequate spare illumination in case of
emergency. Evacuation lights should be available in the evacuation paths to ensure
safe evacuation of personnel. (9) Grounding: It is a connection through a conductor
between the local ground and designated points of the power system, electrical
devices, or equipment. Grounding is divided into functional grounding, protective
grounding, electromagnetic compatibility grounding, building lightning grounding,
and so on.

Ultrapure Water System

Most processes in the production of IC require the use of ultrapure water (UPW) to
clean up contaminants in the production process. As UPW is in direct contact with
the wafers, trace impurities in UPW may contaminate the wafers. With the contin-
uous improvement of IC technology, the quality of UPW is increasingly higher. The
UPW process for an IC production line is illustrated in Fig. 28.3.

Fig. 28.3 Ultra-pure water (UPW) preparation process in semiconductor plant

28 Designing IC Production Lines 595

1. Pretreatment of UPW preparation: In order to make the treatment equipment

for UPW safe, efficient, and economical, it is necessary to preprocess the raw
waters, reduce the content of suspended matter, colloid, macromolecular organic
matter, and positive and negative ions in the original water, and adjust the water
temperature. Pretreatment is usually carried out by using multi-media filters or
ultrafiltration membranes, degasification towers or degassing membranes, ion
exchange resins, and activated carbon.
2. The initial preparation of UPW: The raw water after pretreatment, the
resistivity can reach more than 18.0 Mohm.cm. The preliminary preparation
of UPW mainly uses reverse osmosis (RO) and UV lamps to remove organic
matter from the aqueous, uses RO and ion exchange resin to remove positive
and negative ions and silica in water, and uses degasification film to remove
dissolved oxygen from water. UV lamps are used to sterilize before RO to
avoid microbial contamination of RO membranes.
3. UPW preparation of fine treatment: The initial preparation of pure water also
through fine treatment, the basic removal of impurity components, and eventually
made of UPW. Precision polishing treatment equipment mainly uses UV lamps to
remove organic matter and bacteria; the use of polishing resin to remove residual
ions; the use of ultrafiltration membrane removal of micro-particles; and the use
of plate heat exchanger to control the water temperature in 23  C  1  C. The
polishing resin needs to be replaced regularly in order to ensure the removal effect
of polishing resin. A filter is arranged before the ultrafiltration membrane in order
to ensure the safety of the ultrafiltration membrane. A degasification film can be
set up before the ultrafiltration membrane to remove the dissolved oxygen from
the water.
4. UPW index monitoring and analysis: In order to continuously supply high-
quality UPW, it must be monitored both online and offline with control
standards. Online real-time monitoring indicators have resistivity, particles,
total organic carbon, silica, dissolved oxygen, temperature, etc., as shown in
Table 28.5. Offline monitoring mainly uses the method of regular sampling,
the sample sent to the laboratory to detect the content of positive and negative
ions. Before sampling, the sampling bottle and pipeline should be guaranteed
to be clean and sampled according to sampling criteria.
5. The development trend and recovery rate of raw water supply of UPW:
Due to the lack of water resources, the use of high-quality recycled water is
an inevitable trend to replace tap water as the raw water for UPW. The water
resources utilization requirement of UPW process is also higher, and enter-
prises should build their own. The process of the wastewater recovery treat-
ment system, as illustrated in Fig. 28.4, utilizes activated carbon, RO
membrane, and others for removing organic, salt, etc., in recycled water,
and continuously recycle and reuse wastewater, to improve the recovery rate
and save tap water.
596 T. C. Wang

Table 28.5 Terminal water quality control table

Downtime
Target Downtime lower Control Control
Monitoring metrics value upper limit limit upper limit lower limit
Particle concentration of 0.00 1000.00 – 700.00 –
0 – 1 μm/pcs/l)
Total organic carbon 0.00 3.00 – 1.00 –
concentration/ppb
Silicon dioxide 0.00 2.00 – 0.50 –
concentration/ppb
Dissolved oxygen 0.00 3.00 – 2.00 –
concentration/ppb
Resistivity/MΩ
cm 18.20 – 17.50 – 18.00
Temperature/ C 23 24 22 23.5 22.5
9
Note: PCS/L is the number of particles per liter; ppb is 10

Fig. 28.4 Process of wastewater recovery treatment system

Wastewater Treatment System

Wastewater produced by IC production line can be divided into 5 categories:

ammonia-containing, fluorine-containing, copper-containing, grinding, and
acid-base wastewater. Ammonia-containing, fluorine (F)-containing, copper (Cu)-
containing, and grinding wastewater should be diverted into their respective treat-
ment systems, and finally into the neutralization treatment system after treatment. In
order to ensure the normal and stable operation of the wastewater treatment system,
an online monitoring system [7] is set up in the central control room to automatically
control the whole wastewater treatment system. After the treated wastewater meets
the discharge standards, it can be discharged from the outlet of the wastewater to the
municipal sewage pipe network and eventually into the municipal wastewater
treatment plant for further unified treatment and utilization. (1) Ammonia
wastewater treatment: The concentration of ammonia wastewater in IC production
line is high, and it is usually treated by stripping method. The treatment process is
illustrated in Fig. 28.5. (2) Treatment of F-containing wastewater: Lime or
calcium chloride flocculation precipitation is the most commonly used treatment
method for F-containing wastewater in IC production plant, and its treatment process
is illustrated in Fig. 28.6. (3) Cu-containing wastewater treatment: Cu-containing
wastewater is treated by adding complexing agent, coagulant, and separated from
28 Designing IC Production Lines 597

Fig. 28.5 Treatment process of ammonia-containing wastewater by stripping method

Fig. 28.6 Treatment process of fluorine-containing wastewater

precipitation, and then the sludge produced is compressed into cake and treated
outside. This technology is a conventional, mature, and reliable treatment pro-
cess, for meeting the discharge standard. (4) Grinding wastewater treatment:
The Grinding wastewater is often treated by flocculation and sedimentation
methods. After collecting and adjusting the pH value of grinding wastewater,
adding coagulant, mixing fully, discharging into the flocculation tank, adding
flocculants, the wastewater into the sedimentation tank, and the treated clarified
wastewater into the acid-alkali wastewater treatment system for neutralization,
the sludge produced is concentrated and dried and transported to the outside.
598 T. C. Wang

Fig. 28.7 Treatment process of acid-alkali wastewater

(5) Treatment of acid-alkali wastewater: acid-alkali wastewater is usually

treated by acid-alkali neutralization. The acid-alkali wastewater is neutralized
by adding liquid alkali (e.g., NaOH) and sulfuric acid (H 2SO4), and discharged
after meeting the standard of sewage nanotube. The treatment process of acid-
alkali wastewater is shown in Fig. 28.7.

Facility Monitoring and Control Systems (FMCS)

The main function of the plant facility monitoring and control system (FMCS) is that
it can continuously measure and collect data on the normal operation of various
centralized supply systems, so that the duty officer of fab facilities can monitor the
real-time status of all systems. In case of abnormalities, the duty officer can overhaul
and maintain the equipment at the earliest time. In order to facilitate the operation of
the relevant staff, all subsystems of the monitoring system in the screen style,
operation mode, and color definition, etc., are consistent. FMCS is described
below. (1) The basic hardware components of FMCS: Including database server,
system information collection equipment, alarm printing equipment, engineer base
station, and network facilities. The main function of the database server is to collect
the signal of the subsystem, so that users can compare the available information
according to the basic data analysis of these signals. The main function of the system
information collection equipment is to integrate the monitoring screen of the sub-
system into the computer of the Monitoring Center in order to achieve unified
monitoring of all the equipment. The engineer base station allows the engineer or
program writer to modify, develop, and debug without affecting operation of the
monitoring system. The function of the alarm printing device is to print out impor-
tant alerts for users to reference or cooperate with the program analysis software for
different stages of historical data analysis. (2) The main software components of
FMCS: Including 4 aspects of basic, base, application, and user software. The basic
software includes database management system software, engineering and monitor-
ing software, communication software, data banking software, graphical display
process visualization software, Ethernet connection communication software, etc.
The base software includes operating software, higher level computer communica-
tion software, and so on. The application software includes process data acquisition
software, abnormal condition alarm software, process measurement software for
28 Designing IC Production Lines 599

Fig. 28.8 Topology diagram of factory monitoring system network of an IC production fab

display and recording, monitoring and reporting management information software,

etc. The user software includes logic control software, equipment operation soft-
ware, and so on. (3) Network topology: Taking the factory monitoring system of an
IC production fab as an example, its network topology is illustrated in Fig. 28.8.
Intelligent FMCS is an important part of automation plant, including intelligent
inspection system, robot inspection system, intelligent maintenance system, fault
intelligent analysis system, knowledge base system, intelligent report system, per-
sonnel positioning system, and face recognition system.

Hook-Up System

The hook-up systems refer to the system connecting the production equipment with
all needed conditions (e.g., water, chemicals, gas, vacuum, electricity, etc.) from the
main central supply system with safety and stability for long-term normal operation.
Such “secondary piping” system can be divided by function, mainly including the
following parts. (1) Cooling water piping system: It is for normal operation of
equipment in clean room and auxiliary equipment to have cooling water with stable
temperature, pressure, and conductivity. Cooling water piping is configured
according to equipment requirements, connecting process and related ancillary
equipment from the main system reservation point to the plant and other supporting
areas. The connection between the cooling water pipeline and the equipment is
enclosed with water supply and return pipeline. Cooling water pipes are stainless
steel hard pipe and rubber high-pressure hose and other accessories generally using
sub-arc welding. (2) Vacuum piping system: The vacuum system can provide a
certain vacuum level for the use in equipment adsorption of wafers. The vacuum
piping system is configured according to the requirements of the equipment and is
600 T. C. Wang

connected from the main system reservation point to the equipment and related
ancillary equipment in the factory and other supporting areas. The vacuum piping
is all made up by high-density polyvinyl chloride (UPVC) hard tubes and fittings,
and the use of polyurethane (PU) or polyethylene (PE) hoses and connected to the
use point. The connection of the vacuum pipeline is generally bonded. (3) Water
pipeline system: Based on the equipment requirements, it is configured and
connected from the reserve point of the main system to the process equipment.
Tap water pipeline is made up of 304 stainless steel hard pipe and rubber high-
pressure hose, etc. It is usually welded by argon arc welding. (4) UPW piping
system: It is configured according to equipment requirements, from the main
system reservation point connected to the plant and other support areas. The
materials for UPW pipes and accessories are usually poly-vinylidene fluoride
(PVDF) and PTFE (PFA) material; valve selection of poly-vinylidene fluoride
(PVDF) diaphragm valve. The UPW pipeline connection is generally welded by
automatic hot melt welding machine. (5) Wastewater discharge piping system:
It is used in the IC production process to produce wastewater (e.g., ammonia
containing wastewater, fluorinated wastewater, Cu-containing wastewater, grind-
ing wastewater, acid and alkali wastewater, etc.) for classified discharge and
treatment. The discharge piping is equipped with different emission types
according to equipment requirements, connecting equipment, and related ancil-
lary equipment from the main system reservation point to the plant and other
supporting areas. (6) Gas piping system: Based on the needs of the process, it is
connected to the process equipment and related ancillary equipment in the plant
and other supporting areas from their respective cylinder cabinets, valve boxes, or
main system reservation points. The materials of the process gas piping system is
generally with the inner surface polishing treatment of stainless steel. The con-
nection of process gas pipeline generally adopts automatic trajectory argon pro-
tection welding. (7) Exhaust piping system: It is used for separating emissions
and treatment of various waste gases generated in the IC production. Piping varies
from the main system reservation point to the process equipment and related
ancillary equipment in the factory and other supporting areas. The connection of
the pipeline is generally made of flange connection. (8) Secondary power distri-
bution system: The power supply from the main system reservation point is
connected to the equipment. (9) Chemicals piping systems: It is for the distribu-
tion of chemicals and connected to process equipment and related ancillary
equipment from their respective chemical valve sets. Process chemical piping
materials are generally PTFE (PFA) inner tube or stainless steel inner tube.
(10) Equipment base: According to the load-bearing and vibration requirements,
IC production equipment need to be equipped with different types of equipment
bases. The basic equipment base can be divided into steel plate base frame, steel
structure base frame, cement frame, and elephant foot base frame.
28 Designing IC Production Lines 601

References
1. S.-L. Chung, M.D. Jeng, An overview of semiconductor fab automation systems, in 2003 IEEE
International Conference on Robotics and Automation (Cat. No.03CH37422), vol. 1, (Taipei,
2003), pp. 1050–1055. https://doi.org/10.1109/ROBOT.2003.1241731
2. C.C. Chien, C.N. Chang, J. Shyu, E. Hsiao, B.S. Tang, L.-K. Zhu, Innovative precise-
environment design and technology of removing the pollutant from a clean room, in 2013
e-Manufacturing & Design Collaboration Symposium (eMDC), Hsinchu, (2013), pp. 1–4.
https://doi.org/10.1109/eMDC.2013.6756037
3. Y. Kobayashi, S. Kobayashi, K. Tokunaga, K. Kato, T. Minami, Particle characteristics of
300-mm minienvironment (FOUP and LPU). IEEE Trans. Semicond. Manuf. 13(3),
259–263 (2000). https://doi.org/10.1109/66.857933
4. L. Aresi, S. Dauzère-Pérès, C. Yugma, M. Ndiaye, L. Rullière, AMHS vehicle management
policies in semiconductor manufacturing: A short review, in 2019 IEEE International Confer-
ence on Industrial Engineering and Systems Management (IESM), Shanghai, (2019), pp. 1–6.
https://doi.org/10.1109/IESM45758.2019.8948208
5. M. Haddadin, W. Moreno, Automated material handling systems: System of systems architecture
examination semiconductor manufacturing perspective, in 2021 32nd Annual SEMI Advanced
Semiconductor Manufacturing Conference (ASMC), Milpitas, CA, USA, (2021), pp. 1–6. https://
doi.org/10.1109/ASMC51741.2021.9435681
6. K. Lee, S. Song, D. Chang, S. Park, A new AMHS testbed for semiconductor manufacturing, in
2022 Winter Simulation Conference (WSC), Dermatol Sin, (2022), pp. 3318–3325. https://doi.
org/10.1109/WSC57314.2022.10015476
7. A. Jain, R. Bagherwal, Design and implementation of a smart solid waste monitoring and
collection system based on Internet of Things, in 2017 8th International Conference on Com-
puting, Communication and Networking Technologies (ICCCNT), Delhi, (2017), pp. 1–5. https://
doi.org/10.1109/ICCCNT.2017.8204165
Clean Room and Air Conditioning Systems
29
Deyuan Xiao

Contents
Clean Room System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Air Conditioning Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
Circulating and Cooling Water System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Vacuum System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Exhaust System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

Abstract
A qualified clean room environment has specific requirements for not only
particle control but also temperature, humidity, pressure, and oxygen levels
which are supplied and controlled by other essential systems. It includes air
conditioning systems, circulating and cooling water system, vacuum system,
and exhaust system. Together it provides necessary conditions for manufacturing
processes and normal operation. This chapter further gives the introduction with
flow charts of those systems.

Keywords
Clean room · Particles · Air conditioning system · Circulating and cooling water ·
Vacuum system · Exhaust system

D. Xiao (*)
SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
e-mail: Deyuan.Xiao@sienidm.com

© Publishing House of Electronics Industry 2024 603

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_29
604 D. Xiao

Clean Room System

The fabrication of integrated circuits (IC) must be performed in the clean room
environment. Clean room refers to a room, where the concentration of suspended
particles is controlled and its construction and use shall reduce the induction, generation,
and retention of particles in the room. Other indoor parameters such as temperature,
humidity, pressure, and oxygen level are also controlled according to special require-
ments. More advanced clean room designs are illustrated in references [1–3]. Following
is a brief introduction of the filtration system, airflow, static hazards, and preventive
measures of the clean room. (1) Clean room filtration system: The system can filter out
dust air particles by using the combination of high-efficiency and ultra-high-efficiency
filters with efficiency as high as 99.995%–99.999995%. The concentration of air
particles after filtering is controlled within the range of cleanroom grade requirements.
(2) Airflow in clean room: The personnel and production equipment in the clean room
can produce dust particles as a great hazard to the clean room environment, and it is
necessary to filter or discharge the dust through the airflow. According to the direction of
airflow, it can be divided as one-way flow (e.g., parallel airflow vertically or horizon-
tally), non-one-way flow (airflow mixed by fresh air supply into clean room with indoor
air), or mixed flow (airflow combined with one-way flow and non-one-way flow).
(3) Electrostatic hazards in clean rooms: The anti-static requirements in the clean
room are also stringent. The main hazards of static electricity to ICs are mainly in the
following 3 aspects. (a) Electrostatic adsorption: the electrostatic charge accumulated on
the product will absorb the dust in the air through electrostatic force and attach on the
product. (b) Electrostatic discharge: When the electrostatic charge accumulates to a high
enough potential, it will discharge through an adjacent conductive path and result in
device breakdown. c) Electrostatic interference: Electrostatic discharge may generate
radiation and interfere with adjacent devices (e.g., microprocessors, memories, etc.).
(4) Anti-static precautions in clean room: The anti-static control scheme may vary
depending on process areas. (a) Electrostatic protection of interior installations (elevated
floor, ceiling, partition, etc.). The primary anti-static measure of interior installations in a
clean room is grounding. As many materials used in production are insulators (e.g.,
quartz, glass, plastic, etc.), the static charge generated during production may be
removed through local grounding as a key anti-static scheme. (b) Electrostatic protection
by ion rods, ion fans, etc.: The ion generators, for example, ion rods and ion fans, can
generate positive and negative ions by ionizing particles in the air, and can neutralize the
charges accumulated on devices or objects, thereby eliminating static electricity.
According to the “Code for Design of Clean Workshops” (GB50073-2013), the integer
grade of air cleanliness in clean rooms is shown in Table 29.1.

Air Conditioning Systems

Air conditioning systems refer to the air handling systems which provide the
necessary environmental conditions for manufacturing processes or normal oper-
ation. In IC manufacturing plants, air conditioning systems can regulate and
29 Clean Room and Air Conditioning Systems 605

Table 29.1 Integer grade of air cleanliness in clean rooms

Maximum concentration limits for larger than or equal to required particle
Air cleanliness size/(pcs/m3)
grade (N) 0.1 μm 0.2 μm 0.3 μm 0.5 μm 1.0 μm 5.0 μm
1 10 2 – – – –
2 100 24 10 4
3 1000 237 102 35 8
4 10,000 2370 1020 352 83
5 100,000 23,700 10,200 3520 832 29
6 1,000,000 237,000 102,000 35,200 8320 293
7 – – – 352,000 83,200 2930
8 – – – 3,520,000 832,000 29,300
9 – – – 35,200 000 8,320,000 293,000
Note: According to different measurement methods, the effective number of concentration data at
different levels should not exceed 3 digits; pcs/m3 is the number of particles per cubic meter

Fig. 29.1 Air conditioning system structure of a typical IC Fab

control the temperature, humidity, and air flow speed in a room or space and
supply fresh air and remove dirty air. (1) The air conditioning system includes
filters, air scrubbers, coolers, fans, and heaters, as illustrated in Fig. 29.1. (2) The
selection, arrangement, and installation of filters in air conditioning boxes should
be carefully selected according to the air cleanliness level. The medium or high
efficiency filters shall be in the positive pressure section of air conditioning
boxes. (3) Humidity control in clean room is performed in 2 aspects. If the
external air is wet, then it is firstly cooled by air condition system to a point to
achieve dehumidification; and then the air is heated to the desired temperature
level. If the external air is too dry, then it is firstly heated, then passed through a
humidification system and then sent into the clean room. (4) The fresh air systems
(Fig. 29.2) with constant temperature and humidity after treatment is directed into
the return-wall of the clean room through air duct and mixed with the return air of
the clean room. The fresh air flow is formed in the clean room under the operation
of fan filter unit to circulate air throughout the clean room.
606 D. Xiao

Fig. 29.2 Illustration of a fresh air system in clean room

Circulating and Cooling Water System

In the manufacturing of ICs, wafers are processed through 100s of steps (unit
processes) with process equipment and tools in active operation and generating
heat during production and testing. The circulating and cooling water system
provides the needed cooling water in the production line for equipment and tools.
When the system is in operation, it needs to provide steady flow, pressure, and
temperature as well as good water quality for continuous and long-term opera-
tion. The flow chart of a typical system for circulating and cooling water is
illustrated in Fig. 29.3. The system includes a water tank (for water storage and
collecting return water and adding medicament to adjust water quality), water
pump (for enough pressure on cooling water to user side), heat exchanger (for
cooling water to exchange heat with ice water to ensure temperature stability of
cooling water supply), frequency converter (for maintaining stable outlet pres-
sure of the pump with variable frequency method), and the filter (for filtering out
impurities in the water to avoid blockage of equipment or tools).
29 Clean Room and Air Conditioning Systems 607

Fig. 29.3 Flow chart of a typical system for circulating and cooling water

The circulating and cooling water system can provide cooling water with stable
temperature and pressure, and continuously remove the heat generated by equipment
during IC production. Temperature stability is achieved by the turn-on of an ice
water valve on the side of heat exchanger based on temperature sensor, so that the
water supply temperature can be kept within the range as specified by the operation
of equipment. The main system can maintain stable pressure by using variable
frequency pump for achieving a stable cooling water supply for the end equipment.
At the same time, the circulating cooling water system shall keep stable pH value and
conductivity of the water within a certain range per the equipment specifications. If
the level of water in the storage tank decreases during the cycle, deionized (DI) water
will be added to ensure the stability of the circulating and cooling water system. If DI
water is not available, then the tap or city water can be used as emergency water
supply.

Vacuum System

In the production of ICs, the vacuum systems (see Fig. 29.4) are used to provide the
vacuum pressure and gas flow required by the production and testing equipment.
One practical example of the system is described here for references. The total flow
through vacuum ports in a vacuum system is determined by the equipment demand.
In general, several vacuum pumps are connected in parallel. (1) The vacuum
pressure at the point of use is 150 kPa (+50 kPa). (2) The pressure of the vacuum
pump is greater than 80 kPa (absolute value). (3) The vacuum pressure of the system
is 80–88 kPa. (4) The system is equipped with a vacuum buffer tank. (5) Cooling
water with a rotary bolt vacuum pump is used for cooling.
The system operation is briefly described here. The vacuum system extracts air
from the pipeline through a vacuum pump to maintain a certain pressure in the
chamber. The extracted gas is discharged into the atmosphere or exhaust system
608 D. Xiao

Fig. 29.4 Working flow diagram of a vacuum system

through the back-end of the vacuum pump. At the same time, the pressure at the end
of a single process needs to be constant, so the pressure of the main pipeline needs to
be constant in operation. The buffer tank is connected in parallel to the whole system
for the purpose of stabilizing the main pressure for a short time when a transient
disturbance occurs at the vacuum pump end. When the system is in operation, the
vacuum level is measured and continuously monitored by the air pressure sensor
outside the buffer tank and the output signal is sent to the centralized controller.
When the vacuum level is less than 80 kPa, the intake valve, ice water solenoid
valve, and vacuum pump are turned on until the vacuum level rises to the target
upper limit (greater than 88 kPa). When the vacuum level drops to the lower limit,
and if still declining in vacuum level, then additional vacuum pumps are turned on
until all the vacuum pumps are started. When the system vacuum reaches the upper
limit, the vacuum pumps are shut off.

Exhaust System

Many varieties of special gases and chemicals are used in IC production. The
reactions of various gases and chemicals in processes will produce toxic and harmful
by-products, which need to be effectively treated and carefully discharged after
meeting the emission standards to avoid impacts on environment and human society.
Classification and treatment of exhaust systems: (1) Exhaust system of general
gas: It refers to an exhaust system that removes waste heat from equipment by a fan
or ensuring a negative pressure environment inside the system. The general exhaust
does not contain toxic and harmful substances and is discharged directly into the
outdoor atmosphere without treatment. (2) Exhaust system of acid gas: It refers to an
exhaust system that is used to treat harmful acidic gases containing HCl, H2SO4, etc.,
through an acidic scrubber and discharged to the atmosphere through a fan. The
acidic scrubber neutralizes the harmful acidic gases with alkaline liquids and then
separates the liquid and the gases that meet the discharge standards through the fan.
Generally, the gas–liquid reverse absorption method is adopted, where the alkaline
liquid is sprayed down from the top of the tower in a fog (or in small droplets),
allowing the acidic gas to pass through the packed scrubber tower. This treatment
serves the purpose of cooling waste gas, regulating gas pH, and removing particles.
The exhaust gas is then treated in the defogging section and discharged into the
29 Clean Room and Air Conditioning Systems 609

atmosphere after meeting the environmental emission standards. (3) Exhaust system
of alkaline gas: It refers to an exhaust system that is used to treat harmful alkaline
gases containing NH3, etc., using an alkaline scrubber and discharged to the atmo-
sphere through a fan. The alkaline scrubber neutralizes harmful alkaline gases with
acidic liquids and then separates liquids and gases that meet discharge standards
through a fan. In general, the gas–liquid reverse absorption method is adopted,
where the acid liquid is sprayed down from the top of the tower in a fog (or in
small droplets), allowing the alkaline gas to pass through the packed scrubber tower.
This treatment serves the purpose of cooling waste gas, regulating gas pH, and
removing particles. The exhaust gas is then treated in the defogging section and
discharged into the atmosphere after meeting the environmental emission standards.
(4) Exhaust system of organic solvents: It refers to the exhaust system that is used to
treat harmful gases containing organic solvents such as benzene, acetone and
isopropanol by a zeolite runner and a combustion furnace. Generally, zeolite runners
are installed to absorb organic solvents and discharge into the atmosphere after
meeting the environmental emission standards. Organic solvents concentrated by
the runner are desorbed by hot air.
The wind pressure design includes the pressure specification of the fan to meet the
required pressure along the main pipe in the exhaust system. In the design process, it
is necessary to consider the pressure loss of the duct, the local pressure losses of the
duct fittings, tees, elbows, variable diameters, and air valves, the minimum wind
pressure requirement at the end user, and the pressure loss of the treatment equip-
ment. In the wind pressure design, it is also necessary to include a certain margin of
wind volume and pressure for the end user. The general reserved wind pressure of
the exhaust connection is 400 to 500 Pa, the wind pressure at the end of main
pipe is 700 to 800 Pa, and the wind pressure at the inlet header of the fan is
generally 1000 to 1300 Pa. In IC production, the negative pressure of the exhaust
system must be stable, avoiding excessive fluctuations to trigger an alarm, forced
shutdown, and even direct impact on wafer quality in production.

References
1. P. Thu, S.R. Andrei, M.L. Nikolai, Analysis of the air conditioning and filtration systems in clean
rooms, in 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic
Engineering (EIConRus), Moscow and St. Petersburg, Russia, (2018), pp. 1916–1919. https://
doi.org/10.1109/EIConRus.2018.8317483
2. V.I. Karakeyan, A.S. Riabyshenkov, M.A. Gundartcev, V.P. Sharaeva, N.R. Kharlamov, Struc-
tural and objective model for providing a given class of clean rooms for microelectronics, in 2021
International Seminar on Electron Devices Design and Production (SED), Prague, Czech
Republic, (2021), pp. 1–4. https://doi.org/10.1109/SED51197.2021.9444530
3. T. Ishiguro, T. Ro, Cleanroom design for Cu-CMP processes, in 2001 IEEE International
Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat.
No.01CH37203), San Jose, CA, USA, (2001), pp. 11–14. https://doi.org/10.1109/ISSM.2001.
962903
Central Gas and Chemical Supply Systems
30
Deyuan Xiao

Contents
Bulk Gas Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Special Gas Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Chemical Supply Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

Abstract
As the semiconductor industry continues to develop, the demand for ultra-pure
gases and chemicals also keeps growing. Generally, gases and chemicals supplies
can be outsourced to reliable third parties, but on-site central systems are also
very critical. This chapter presents the classification and applications of bulk
gases, special gases, and chemicals in a typical fab. It also introduces how to
monitor and control the chemicals and gas usages for different fabrication
processes of ICs.

Keywords
Bulk gases · Special gases · Purification · Chemicals · Monitoring and safety
protection

Bulk gas supply, special gas systems, and chemical supply systems are key aspects in
IC product lines. Recent new techniques for monitoring gas and chemicals are
shown in references [1–3].

D. Xiao (*)
SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
e-mail: Deyuan.Xiao@sienidm.com

© Publishing House of Electronics Industry 2024 611

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_30
612 D. Xiao

Bulk Gas Systems

Classification and application of bulk gases: Bulk gases are a generic term for
nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), and helium (He). (1) N2:
Nitrogen generator can separate N2 gas from air after compression, cooling, frac-
tionation, and vaporization. N2 is used for cleaning and diluting raw gas in equip-
ment, providing inert gas environment, and serving as a pressure source for chemical
transportation. (2) H2: H2 gas can be directly supplied from transport truck or
cylinders to the facility; it can provide a combustion medium for equipment and
serve as a reducing reaction gas. (3) O2: The vaporizer converts liquid oxygen into
gas. It serves as oxidizer for reaction chamber and also the O2 supply to the ozone
(O3) generator. (4) Ar: The vaporizer converts liquid Ar. It serves as the heat
conducting medium and inert gas environment for reaction chamber. (5) Helium
(He): The vaporizer converts liquid helium for cooling wafer chucks in process.
Bulk gas systems: (1) Gas-making station: It includes gas-making facilities,
compression storage facilities, filling facilities, auxiliary facilities, buildings, and
structures required for gas-making by relevant processes. The quality of output gas
of a typical gas station is shown in Tables 30.1 and 30.2. (2) Gas purification station:
It includes the building, structure, or room with purification devices of bulk gas, gas
filters, pipelines, and auxiliary facilities. The impurities of bulk gases in gas station
systems are adsorbed and filtered through a gas purifier and particulate filter,
generating high-purity bulk gases used by the process equipment. The quality of
output gas of a typical purification station is shown in Table 30.3. (3) Quality
and pressure control system: It is a system that collects and displays the quality,
flow, and pressure data of the supplied gas through a gas analyzer and data acqui-
sition and monitoring control system. The contents of gas impurity detection in a
typical control system are listed in Table 30.4. (4) High purity gas delivery system: It
refers to a delivery system from a bulk gas purification device (or station) to service
points needed for high purity gas.

Special Gas Systems

Special gases are indispensable raw materials and widely used in the production of
IC, liquid crystal panels, solar cells, and optical fibers. They are mainly used in
process steps in oxidation, doping, vapor deposition, diffusion, and other processes.
Special gases are generally classified as non-combustible, toxic, flammable, and
corrosive gases according to their properties. Each classification of special gasses is
placed in different chemical stations in the facility. Silane stations are generally set
up separately due to its spontaneous combustion. As the chlorine trifluoride (ClF3)
reacts with water, its storage rooms should also be set up separately. Low-pressure
gas is located on the 2nd floor of the clean room. Toxic, corrosive, flammable gasses,
and tail gas treatment devices are located in the corresponding areas.
A special gas delivery system includes pipelines and equipment that conveys
special gasses from cylinders at gas stations to valve distribution boxes in clean
 30

Table 30.1 Gas output quality of a typical gas station

Total
Water hydrocarbon Oxygen Hydrogen Carbon monoxide/ Nitrogen Argon Particle quantity of 0.1 μm
Gas type content/ppm content/ppm content/ppm content/ppm carbon dioxide/ppm content/ppm content/ppm size in diameter/(pcs/ft3)
Nitrogen
5
1
2
2
0.5 – –
10
Central Gas and Chemical Supply Systems

Hydrogen
5
0.5
2 –
0.1
5 –
10

Oxygen
3
25 –
1
0.5 – –
10
Argon
1
0.25
1
1
0.1
1 –
10
Helium
1
0.25
1
1
0.1
1 –
10
Note: ppm is 106; pcs/ft3 is the number of particles per cubic foot, 1ft3 ¼ 0.0283168 m3
613
 614

Table 30.2 Gas output quality of a typical purification station

Total
Water hydrocarbon Oxygen Hydrogen Carbon monoxide/carbon Nitrogen Argon Particle quantity of 0.1 μm
Gas type content/ppb content/ppb content/ppb content/ppb dioxide/ppb content/ppb content/ppb size in diameter/(pcs/ft3)
Nitrogen
1
1
1
1
1 – –
1
Hydrogen
1
1
1 –
1
1
1
1
Oxygen
1
1 –
1
1
1
1
1
Argon
1
1
1
1
1
1 –
1
Helium
1
1
1
1
1
1 –
1
Note: ppb is 109; pcs/ft3 is the number of particles per cubic foot, 1ft3 ¼ 0.0283168 m3
D. Xiao
 30

Table 30.3 Contents of gas impurity detection in a typical control system

Water Oxygen Methane Carbon Non-methane total hydrocarbon Hydrogen Carbon
Gas type content content content dioxide content content monoxide Particle
Nitrogen √ √ √ √ √ √ √ √
Central Gas and Chemical Supply Systems

Hydrogen √ √ √ √ √ – √ √
Oxygen √ – √ √ √ √ √ √
Argon √ √ √ √ √ √ √ √
Helium √ √ √ √ √ √ √ √
615
616 D. Xiao

Table 30.4 Monitoring and safety protection devices for special gas equipment in a typical fab
Sensor
Overflow Ultraviolet/ Smoke Temperature
Gas species protection device Spray infrared sensor sensor sensor
1% B2H6/H2 √ √ √ √ √
10%GeH4/H2 √ √ √ √ √
NH3 √ √ √
CH4
C3H6 √ √ √ √
CH3F √ √ √ √
CH2F2 √ √ √
1%GeH4/H2 √ √ √ √ √
SF6
CHF3
0.5%O2/He
1.2%He/N2
CF4
C4F8
100 ppmXe/
3.5%Ar/Ne
N2O
4%H2/N2
5%H2/He
CO2
30%O2/He
1.25%Kr/He
NO √ √ √
5%B2H6/N2 √ √ √ √ √
SiH2Cl2 (DSC) √ √
NF3 √ √ √
1%PH3/PH2 √ √ √ √ √
1%PH3/N2 √ √ √ √ √
CO √ √ √ √
Cl2 √ √ √
0.95%F2/3.5% √ √ √
Ar/Ne
0.9%F2/1.25% √ √ √
Kr/Ne
HCl √ √ √
HBr √ √ √
SO2 √
20%F2/N2 √
WF6 √
HF √
SiCl4 √
(continued)
30 Central Gas and Chemical Supply Systems 617

Table 30.4 (continued)

Sensor
Overflow Ultraviolet/ Smoke Temperature
Gas species protection device Spray infrared sensor sensor sensor
C4F6 √ √ √
C5F8 √
BCl3 √
SiH4 √ √ √ √ √
SiF4 √ √ √ √
C2H2 √ √ √ √
ClF3 √ √
Note: The types of special gasses commonly used in IC industry chain are listed in the table. Some
kinds of special gas supply equipment do not need monitoring or safety protection devices

rooms, and then to service points of process equipment in accordance with stable gas
flow and pressure in operation and safety requirements. Special gas delivery system
generally includes gas cabinet (GC), gas rack (GR), bulk special gas supply system
(BSGS), special gas mass supply system, mixer system, valve distribution box/panel
(VDB/VDP), and valve manifold box/panel (VMB/VMP).
A gas detector and information system includes gas detector system (GDS) and
gas information system (GIS). GDS includes gas detector, seismograph and local
alarm unit (LAU), etc. GIS includes remote input/output (RIO) panel, interchanger,
and communication module. The monitoring and safety protection devices for
special gas equipment adopted by a typical Fab are shown in Table 30.4.

Chemical Supply Systems

A chemical supply system is a general term for pipes and equipment that conveys
chemicals in warehouse storage to valve distribution boxes in clean rooms, and then
to service points of process equipment in accordance with stable flow and pressure in
operation and safety requirement. The distribution of chemicals used in various areas
of equipment in a typical fab is shown in Table 30.5.
The supply methods of chemical supply systems can be divided into nitrogen
pressure supply and pump supply. The nitrogen pressure chemical supply system
(Fig. 30.1) uses high purity nitrogen as power source and supplies chemicals to
process equipment with stable flow and high demand chemicals. The pump chemical
supply system (Fig. 30.2) is powered by a pump which supplies chemicals to process
equipment through the pressure of the pump. The chemical systems supplied by the
pump also need a regulator to stabilize the outlet pressure to provide stable and high
demand for chemicals.
The operational requirements for the chemical supply system: (1) Quality
control: Before the system is put into use, the quality test needs to be completed and
followed by thorough rinse with the chemicals to be delivered. UPW pipeline and
water guns are installed in each supply system for cleaning; N2 pipeline and water
618 D. Xiao

Table 30.5 Distribution of chemicals used in various areas of equipment in a typical fab
Process equipment area
Wet bench Reclaim CMP Lithography PVD Clean
Chemical name clean area area area area area area
Hydrofluoric acid √ √ √ √
Sulfuric acid √ √ √
Ammonia √ √
Developer solution √ √
Hydrogen peroxide √ √ √
Nitric acid √ √ √
Phosphoric acid √
Hydrochloric acid √ √
Benzodiazole √ √
Copper sulfate √
Citric acid √
5% hydrofluoric acid √
Diluent √ √
N-methyl-2-tetrahy √
dropyrrolidone
Isopropyl alcohol √ √ √
Polymer cleaning √
solution after etching
Photoresist remover √
Cyclopentanone √
Propylene glycol √
acetate monomethyl

Fig. 30.1 Diagram of nitrogen pressure chemical supply system

Fig. 30.2 Schematic diagram of the pump chemical supply system

guns are installed in each supply system for cleaning and drying; high-clean mate-
rials should be selected in chemical supply systems; sampling points should be set at
source and outlet for quality analysis sampling of each node. (2) Safety measures:
30 Central Gas and Chemical Supply Systems 619

①The different interfaces of the system are managed by various levels of authority
with usernames and passwords set separately. ②Hardware error-proof measures:
special connectors should be used in the chemical barrel trough to match the
equipment and prevent incorrect chemical supply and incompatible chemical
mixing. ③Software measures: The chemical barrel and tank with different chemical
types have different codes, matching with their respective equipment and confirmed
by scanner. ④Safety protection: The supply system can be shut down in an emer-
gency if there is leakage, fire, earthquake, or a manual alarm occurs. Leakage sensors
are installed in the valve box of the equipment. The pipeline is designed with double-
deck to prevent from danger from leakage; N2 purging design is installed in the
electric control area; the exhaust systems for chemicals with different types should
be plugged into exhaust systems with different types; each chemical room should be
equipped with a dedicated exhaust pipeline; components of the supply section
should be placed in a safe cabinet (e.g., the supply cabinets containing acid and
alkali chemicals are made of polypropylene, and those containing solvent chemicals
are often made of 304 stainless steel); high efficiency air filters and exhaust devices
should be installed.

References
1. F.-H. Chang, K.-C. Chang, H.-C. Wang, Intelligent explosion-proof gas monitoring and early
warning system with semiconductor plant as disaster prevention target, in 2022 17th Interna-
tional Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT),
Taipei, Taiwan, pp. 1–4 (2022). https://doi.org/10.1109/IMPACT56280.2022.9966677
2. H.-M. Cho, K.-H. Lee, P. Shim, A. Park, A chemical monitoring and prediction system in
semiconductor manufacturing process using Bigdata and AI techniques, in IEEE International
Conference on Artificial Intelligence in Information and Communication (ICAIIC), Jeju Island,
Korea (South), pp. 488–491 (2021). https://doi.org/10.1109/ICAIIC51459.2021.9415241
3. DOROTA OWCZAREK: Chemical Supply Chain: Challenges and Opportunities in the Era of
AI., https://nexocode.com/blog/posts/chemical-supply-chain-challenges-and-opportunities-in-
the-era-of-ai/ (2021). Accessed 16 July 2021
Construction and Management of IC
Production Lines 31
Shuying Wang

Contents
Organization and Responsibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Project Planning and Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
Project Bidding Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Government Approval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Construction Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Contract Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Schedule Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Quality Inspection (QI) and Quality Assurance (QA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Utilities Equipment Space Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Construction Safety Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Monitoring of Central Supply System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

Abstract
The construction and management of the IC production line is a series of complex
and systematic activities executed by the clearly defined responsible organiza-
tions. Before starting the construction, all the technical requirements, quality,
maintainability, and cost need to be carefully planned and designed. Then the
bidding of engineering projects shall be open, fair, and honest, and the construc-
tion must be performed strictly in accordance with national laws and local
regulations. This chapter introduces the major management concepts over the
whole construction project, respectively, such as construction management, con-
tract management, schedule control, quality and safety management, and the
finally monitoring of central supply systems. Since each construction and regu-
lation activity can have significant impact on the overall schedule and cost, it is
essential to plan in advance and manage strictly the entire construction project.

S. Wang (*)
SiEn (Qingdao) Integrated Circuit Corp, Qingdao University, Qingdao, China
e-mail: sy_w@qdu.edu.cn

© Publishing House of Electronics Industry 2024 621

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_31
622 S. Wang

Keywords
Project plan and design · Bidding · Regulation · Construction management ·
Contract · Schedule control · Quality management · Safety management

In order to construct IC production lines quickly, safely, and efficiently with good
quality of construction, the project management needs to be performed systemati-
cally. Mainly the basics of constructing IC production lines are described here with
more advanced techniques in references [1–3].

Organization and Responsibility

The project organization for the construction of IC production lines (or fabs) is a
collection of personnel and facilities with clear responsibilities, authority, and
interrelationships that implement or participate in project management. The project
organization level, members, and responsibilities of general IC fab construction
personnel are shown in Table 31.1. The organization structure commonly used in
general IC fab projects is shown in Fig. 31.1.
The project manager is the core management personnel of the project. The main
duties include (1) implement the relevant laws, regulations, guidelines, policies, and
compulsory standards of the national and local government; (2) strictly implement
the company’s management system and regulations; (3) safeguard the company’s
legitimate rights and interests; and (4) perform all aspects of the project, specifically
manage engineering planning and design, engineering technology, schedule control,
quality, and safety supervision. The project manager also comprehensively presides
over the project construction and management work on behalf of the company,

Table 31.1 Project organization level, members, and responsibilities of general IC fab construc-
tion personnel
Project
organization
level Project members Responsibility
Decision Project manager Planning and coordinating, control
group the overall situation, overall
command, decision-making
Management Person in charge of design, Division of labor management, work
group procurement, construction, etc. lead, coordination, synergy
Executive Members of the functional department Exclusive responsibility,
group such as technical engineer, quality implementation, front line command,
engineer, safety engineer, materials quality
engineer, and budget engineer
Operation Structural labor contractor, clean room, Cooperate, be responsible, obey the
group electromechanical, process support command, and concrete
system contractor, etc. implementation
31 Construction and Management of IC Production Lines 623

Fig. 31.1 The organization structure commonly used in general IC fab projects

assumes the contract performance responsibility, and is fully responsible for the final
audit of engineering materials and equipment of the project. The project manager is
also responsible for project payment, summary, and check according to contract as
well as responsible for the project completion inspection and acceptance of the series
of work.

Project Planning and Design

Project planning and design is an important stage before the construction of an IC

production line. Project planning and design should fully consider the technical
requirements, quality, maintainability, and cost. The results of planning and design
will directly affect the progress and economic benefits of the project. The main work
of project planning and design mainly includes the following. (1) Selection of the
624 S. Wang

planning and design company: According to the construction requirements, the

company shall work on the preliminary planning and design mainly including an
overall planning from the selection of the geographical location of the plant to the
layout of the building structure, equipment, and facilities of the plant. (2) Planning
and design work: Provide construction project planning and designs according to the
project schedule, which includes project planning, basic design, detailed design, etc.,
and finally complete the bidding documents of each system. (3) Schedule control:
According to the progress of the project, establish a control table based on bidding
document, including the project and organization name, contract number and name,
date of contract signing, commencement, completion, etc. for the follow-up and
control the progress of planning and design. (4) Review: The planning and design
company conducts project planning and design according to the project timeline and
completes the government approval and construction completion schedule. (5) Draw-
ings: The planning and design company will discuss and design the preliminary
drawings by coordinating the professional designers of civil construction, fire
protection, machinery, electricity, water treatment, gas, and chemicals, and the
users of related systems. Users in various fields of expertise consider the location
and size of the room based on the area and specifications of the equipment. The
planning and design company perform a second design with details of the space
management drawing of the factory. According to the second edition of the draw-
ings, the professionals coordinate the construction parties to review and further
revise the design and submit to the planning and design company for re-audit.
Finally, the planning and design company releases the final drawings.

Project Bidding Procedure

The bidding of engineering projects shall follow the principles of openness, fairness,
impartiality, and honesty. Neither any unit nor individual may turn a whole project
into parts that must be tendered according to law or circumvent the bidding in any
other way. The bidding shall be handled by the bidder in accordance with the law.
Neither any unit nor individual may illegally interfere with the bidding in any way.
The bidder is a legal person or other organization that proposes the construction
bidding project according to law and conducts the bidding. The construction projects
that must be bid according to law shall meet the following conditions before bidding.
(1) The bidder has been established by law; (2) the preliminary design and budget
estimate which should perform the approval procedures have been approved; (3) the
corresponding funds are supported or sources of funds have been made available;
(4) design drawings and technical materials required for bidding are prepared.
The general bidding process is as follows. (1) Preparation before bidding. Prepare
the project proposal (e.g., the project feasibility study report and application pro-
cedures for the construction project) and the prequalification and bidding documents
(e.g., the sale of prequalification documents, acceptance of prequalification applica-
tions of bidders, and prequalification of potential bidders). Then, release the pre-
qualification announcement and issue bidding documents and Q&A and addenda
31 Construction and Management of IC Production Lines 625

(e.g., the sale of bidding documents, on-site investigation of the project before the
bid opening, and the pre-bid meeting and addenda). (2) Receiving bid documents.
Receive bidder’s bid documents and bid bond, and ensure the sealing of bid
documents. (3) Extracting the evaluation experts. (4) Opening the bid. Specify the
time and place; check in the participants; check the sealing of bid documents; host
the bidding and record the opening process, and keep it on file for future reference.
(5) Review of bid documents. It includes the establishment of the bid evaluation
committee, the bid evaluation preparation, the preliminary evaluation, the detailed
evaluation, the issuance of the bid evaluation report, and the recommendation of the
winning bidder. (6) Finalizing the bid. (7) Issuing a notice of winning the bid for
construction project. (8) Contract negotiation and signing. (9) Refunding the
bid bond.

Government Approval

The construction of IC production lines must be performed strictly in accordance

with national and local laws and regulations. In the early construction stage as well
as the final acceptance stage of the project, all shall be subject to government
approval and through the corresponding procedures. Let’s take a typical example
to introduce the government approval items. (1) Early stage: After the intention of
the project is determined, it is necessary to conduct a feasibility study first. Then go
through the corresponding procedures in accordance with the construction formal-
ities, and start construction after obtaining the construction permit. (2) Construction
stage: Before piling, the local planning bureau should be required to carry out the
gray line acceptance. During the construction of the project, the local quality
supervision station shall supervise and inspect (by random inspection) the construc-
tion quality and acceptance (interspersed) of some sub-projects. (3) Completion and
acceptance stage: The project shall complete the engineering design document
requirements and the contents of the contract in accordance with the relevant
national and local laws and regulations and engineering construction standards.
After the construction unit has obtained the acceptance or permit documents for
construction quality, fire protection, planning, environmental protection, urban con-
struction, etc. issued by the relevant government departments (or its associated
agencies), the completion and acceptance of the project shall be organized, and the
“Construction Project Completion Acceptance Report” shall be completed. The
general process for handling engineering construction procedures is shown in
Table 31.2.

Construction Management

Construction management is to ensure that the construction contractor shall com-

plete the construction as planned, and the content and quality of the project are in
accordance with the contract terms, engineering drawings, and related laws and
626 S. Wang

Table 31.2 The general procedures for handling engineering construction projects
Competent department
Project phase and related (for institutional reform, for
Stage Number procedures reference only)
Early stage 1 Project intention, market Construction unit
research, and investment
opportunity analysis
2 Prepare a feasibility study report Construction unit or design
for the construction project unit entrusted by the
construction unit
2.1 Implementation of consultation Construction unit
schemes for water supply,
sewage, power supply, gas
supply, heat supply, and supply of
telecommunications sources
2.2 Prepare the environmental Institutions with EIA
assessment report qualifications
2.3 Obtain the energy pre-evaluation Local development and reform
report commission
2.4 Obtain soil and water Local environmental
conservation evaluation report protection bureau
Early stage 3 Submit the feasibility study Construction unit
report of the construction project
4 Receive the EIA report approval Local municipal or provincial
environmental protection
bureau/department
5 Fill in the “application form of Local land administration
opinions on site selection for
construction projects,” and issue
the “opinions on site selection for
construction projects”
6 Land survey and pile Qualified land survey and
determination report demarcation team
7 State-owned land use right Local land administration
certificate
7.1 Sign the “contract for assigning Local land administration
and transferring the right to use
state-owned land”
7.2 Pay deed tax (including land Local finance bureau
transfer fee)
8 Obtain approval for construction Local management committee
project
9 Issuance of construction land Local planning bureau
planning license
10 Entrust survey, design bidding, Local bidding office
handle survey, and design bid
award notification
11 Fill in the “Application Form for Construction unit
Planning and Design
Requirements of the Construction
(continued)
31 Construction and Management of IC Production Lines 627

Table 31.2 (continued)

Competent department
Project phase and related (for institutional reform, for
Stage Number procedures reference only)
Projects” and attach the
topographic map of the
Surveying and Mapping Institute
12 Issue planning and design Local planning bureau
requisition and approve design
scope drawing
13 Confirm the architectural design Construction unit
13.1 Design and survey units conduct Local planning commission
open bidding and tendering
13.2 Determine the design schemes Design unit
14 Survey and issue survey Survey unit
geological report
15 Prepare preliminary (expanded) Design unit
design texts according to
planning and design requirements
16 The government planning and Local planning bureau
construction departments
organize the preliminary
(expanded) scheme examination
and approval meeting and make
an approval reply
16.1 Planning department approval Planning department
16.2 Aseismatic department approval Aseismatic department
16.3 Fire department approval Fire department
16.4 Civil defense department Civil defense department
approval
16.5 Health department approval Health department
16.6 Labor protection department Labor protection department
approval
16.7 Environmental protection Environmental protection
department approval department
16.8 Water, electricity, gas, Related water, electricity, gas,
telecommunications sector and telecommunications sector
approval
16.9 Municipal, green, technical and Related government
security, traffic patrol, water, and departments
other departments for
consultation
Early stage 17 Construction drawing design Design unit
18 Construction drawing review Qualified review unit
18.1 Issue a construction drawing Qualified review unit
audit report
19 Issue of construction project Local planning bureau
planning permits
(continued)
628
Table 31.2 (continued)
Project phase and related
Stage Number procedures
19.1 Approval of fire design opinions
19.2 Approval of environmental
protection design comments
19.3 Approval of the opinions on the
review of civil air defense
20 Handling temporary water and
electricity for construction
21 Handling construction temporary
intersection
22 Entrust construction, supervise
Bidding, conduct construction,
supervise bid award notification
23 Sign construction contract
24 Filing government contracts
25 Issue the capital guarantee letter
and relevant certificates, and the
five parties sign the quality
lifelong responsibility letter
26 Quality and safety supervision
declaration, that is, handling
quality supervision registration
27 Verify and issue construction
permits
28 Registration of the use of bulk
cement and clay bricks
30 Road planning and red line piling
31 Entrust contractor lofting
Construction 1 Planning acceptance of gray line
stage 2 Supervision and inspection
(by random inspection) of the
construction quality and
acceptance (interspersed) of some
sub-projects
Completion 1 Project commissioning and
acceptance rectification
stage 2 Qualification certificate for water
supply, power supply, natural gas,
telecommunications, and
drainage construction
3 Filling the test run of
environmental protection
completion acceptance
4 Water quality test report (with
secondary supply)
S. Wang
Competent department
(for institutional reform, for
reference only)
Fire department
Environmental protection
department
Civil air defense department
Water company, power supply
bureau
Municipal office
Bidding office
Construction site of employer
Local construction bureau
Employer and contractor
Construction bureau
engineering safety and quality
supervision department
Construction bureau
Construction bureau
Surveying and Mapping
Institute
Contractor
Planning bureau
Quality supervision station
All participating units
Water company, power supply
bureau, natural gas company,
telecommunications bureau,
municipal office
Environmental protection
bureau
Health and quarantine bureau
(continued)
31 Construction and Management of IC Production Lines 629

Table 31.2 (continued)

Competent department
Project phase and related (for institutional reform, for
Stage Number procedures reference only)
5 Fire department complete Fire detachment
acceptance, and obtain “fire
acceptance opinions”
6 Completion acceptance of Greening office
greening supporting, obtaining
“filling certificate of completion
acceptance of greening
supporting”
7 Indoor environment test report Qualified environmental
testing agency
8 Review opinions on completion Construction bureau
settlement of wall materials
9 Review opinions on completion Construction bureau
settlement of bulk cement
10 Pre-acceptance of completion Archive center
data files, and obtain the “pre-
acceptance certificate of
completion data file center”
11 Organize completion acceptance Quality supervision center
12 Filling completion acceptance of Quality supervision center
quality supervision
13 Acceptance of environmental Environmental protection
protection department and bureau
obtaining “environmental
protection acceptance letter”
14 Submit the completion files of the Construction Committee
construction project and obtain
the “certificate of acceptance of
the completion data files”
15 Plan completion acceptance, and Planning bureau
obtain the “Certificate of
completion acceptance for
planning”
15.1 Planning measurement report for Qualified measuring unit
completion acceptance
19.116 Apply for real estate license Housing and Land
Administration
16.1 Real estate area mapping Qualified surveying and
mapping units
16.2 Handling property code Local land administration
confirmation
16.3 Payment of maintenance fund Maintenance fund
management office
630 S. Wang

regulations. The main functions of construction management include as follows:

①prepare a work plan in advance; ②set the target; ③use the organizational power
to command; ④supervise, inspect, and adjust the implementation of the plan;
⑤perform comprehensive and holistic coordination.
The common control procedures for construction management in the construction
process are as follows: (1) document control procedures; (2) recording, transferring,
and receiving control procedures; (3) laws and regulations and other requirements
control procedures; (4) resource management control procedures; (5) information
exchange and communication control procedures; (6) management review control
procedures; (7) design process control procedures; (8) procurement process control
procedures; (9) construction process control procedures; (10) general contracting
and project management control procedures; (11) monitoring and measuring equip-
ment control procedures; (12) environmental factor identification and evaluation
control procedures; (13) hazard source identification and risk assessment control
procedures; (14) environmental and occupational health and safety operational
control procedures; (15) emergency preparedness and response control procedures;
(16) monitoring and measurement control procedures; (17) internal audit control
procedures; (18) non-conforming product control procedures.

Contract Management

Contract management is the core of project management for the entire process of
construction. The main points are as follows. (1) Strengthen management awareness.
It is necessary to recognize the importance of contract management from the view
point of ideology, emphasizing on construction not only according to the drawings
but also the contract. (2) Clarify the contract management process and clarify the
corresponding workflow. (3) Establish a contract representation system. After the
signing of the contract, the contract management personnel must make the contract
representation to the project management personnel at all levels and the person in
charge of each working group, so that everyone is familiar with the main content of
the contract, various regulations and management procedures, and deeply under-
stand the contractor’s responsibility and the scope of works. (4) Establish a system of
responsibility distribution. The contract management personnel shall be responsible
for distributing the responsibility of various contract events into the working groups
or subcontractors so that they have a detailed understanding of their respective scope
of work and responsibilities. (5) Pay attention to the text analysis of the contract.
Both sides can negotiate on the relevant content before signing, but the contract has
legal effect after signing. Therefore, in order to avoid future disputes, it is necessary
to pay attention to the text analysis (i.e., the legitimacy and completeness of the
contract). (6) Pay attention to contract change management. Due to the frequent
changes of contract in engineering practice, it is required to strengthen the manage-
ment in the implementation of the project. All kinds of documents involved, such as
drawings, plans, technical notes, and specifications, should be recorded, collected,
31 Construction and Management of IC Production Lines 631

and organized, and the content of the changed parts should be reviewed and
analyzed.

Schedule Control

The schedule control refers to the formulation of detailed rules for the schedule
management according to the overall schedule of the project construction and the
actual situation of project implementation management. It also establishes a series of
management systems related to the control and guarantee of the construction sched-
ule, ensuring the smooth implementation of the construction schedule through
rigorous procedural operations and systematic guarantee. The construction schedule
shall be prepared according to the bidding documents, Q&A supplementary docu-
ments, bill of quantities, and other items. The construction sequence and require-
ments shall be consistent with the actual conditions, and each construction procedure
and area shall be reasonably determined to ensure that the overall schedule is
completed as scheduled. The schedule management items commonly used in the
construction of IC production line are the following: (1) schedule preparation and
review; (2) schedule accountability management; (3) deepen the design of schedule
management; (4) equipment delivery tracking; (5) equipment approach plan and
implementation; (6) schedule reporting system; (7) contingency schedule if failing to
complete the progress as scheduled; (8) construction progress assessment, rewards,
and punishments.
In order to ensure the realization of the construction schedule target and meet the
requirements of the duration of total and each node, the total duration should be
broken up into several control points according to the key lines and important
procedures in the schedule. The rationality of duration arrangement and resource
input should be analyzed in depth. So the completion of the total duration shall be
ensured by the realization of the control point targets. During the construction, it is
necessary to compare the planned budget output value with the actual output value
so as to judge the trend of the schedule and determine whether the progress of the
relevant sub-projects should be accelerated or postponed. Based on this, the progress
of each operation team shall be estimated, and the differences between the site
schedule and the overall schedule shall be revised. Finally, it is ensured by various
assurance measures related to the progress. The classification construction manage-
ment process commonly used in the construction of IC production line is shown in
Fig. 31.2.

Quality Inspection (QI) and Quality Assurance (QA)

The purpose of construction quality management is to ensure and improve the

overall quality of the project. A series of quality management organization systems
and methods are implemented to ensure the high engineering quality of each
construction process meeting the standards set by the engineering drawings design
632 S. Wang

Fig. 31.2 Schedule management process commonly used in the construction of IC production
lines

specifications and description. The quality management organization is a 3-level

management system and responsible for the quality inspection (QI). The manage-
ment system is led by the project manager, intermediately controlled by the project
technical director and deputy manager, and the quality director, and the professional
foreman and full-time quality inspector of each department. The system has organi-
zational guarantee and clear job responsibilities, and the quality of the project is
acceptable for supervision and inspection by the owner, the supervision unit, and the
government quality supervision institution. The organization structure commonly
used in the construction quality management is shown in Fig. 31.3. The quality
assurance (QA) procedures defined by the construction quality management orga-
nization are shown in Fig. 31.4.

Utilities Equipment Space Management

The purpose of utilities equipment space management is to rationally arrange the

vertical and horizontal public utilities equipment and the service routes of related
auxiliary pipelines, air ducts, and cable bridges in the factories on the premise of
ensuring the design concept, so as to avoid the obstructions between public equip-
ment and facilities in the construction and installation process and save the costs and
shorten the construction duration. Due to the large number of pipelines and compli-
cated spatial arrangement in the comprehensive power station, the entrance room of
each pipeline, the technology sandwich of the core area, pipe gallery, pipe rack, roof
31 Construction and Management of IC Production Lines 633

Fig. 31.3 Organization structure commonly used in construction quality management

Fig. 31.4 Quality assurance procedures

exhaust, and other areas, it is easy to see the situations such as space collision or
pipeline dislocation, etc. Therefore, Building Information Management (BIM) is
often adopted to integrate information in a unified platform. The general implemen-
tation steps of space management in the construction process of IC production line
are shown in Table 31.3.
634
Table 31.3 General implementation steps of space management in the construction process of the
IC production line
Specific work of space
Project stage management
Design stage Compile space management
related documents
Establish the design model based
on construction drawing
Conduct analysis of building
performance
Collision check
Comprehensive planning and
optimization of pipeline based on
design model
Construction Control the application situations
stage of BIM technology by contractor
Establish the model of depth
design
Comprehensive pipeline planning
and optimization during
construction
Coordination meeting of space
management
Deepen design drawing
Technology disclosure and on-site
verification of BIM
S. Wang
Brief description of content
BIM implementation template, BIM
implementation management manual and
process, BIM implementation
specifications
Establish models of building, structural
and electromechanical professional
according to full set of construction
drawings
Conduct project analysis, such as wind
environment simulation, sunshine analysis
simulation, and flow evacuation analysis
simulation
Conduct professional collision inspection
of buildings, structures, and
electromechanical systems
Conduct comprehensive pipeline
planning, optimize pipeline layout,
reasonably control the net height, and
provide the net height analysis report; key
control of the machine room
Plan, organize, control, and review the
BIM application of each contractor, and
guide the construction
Deepen site construction according to
construction drawing model, refine
equipment interface, add construction
details, and establish deepening design
model
Conduct comprehensive pipeline planning
based on deepening design model,
optimize pipeline layout, and issue
comprehensive pipeline report
Holding site coordination meetings based
on BIM model regularly to discuss
problems found in the models and
document solutions
After the comprehensive pipeline planning
based on the deepening design model, the
relevant construction drawing and
prefabrication drawing are issued, and the
statistical table of pipeline and equipment
engineering quantity is given
Carry out technical disclosure to the
construction unit according to the detailed
design drawings and models, and organize
the construction unit to conduct site
inspection of BIM
(continued)
31 Construction and Management of IC Production Lines 635

Table 31.3 (continued)

Specific work of space
Project stage management Brief description of content
Simulation of overall construction Carry out the dynamic simulation of
progress overall construction progress and local
construction node simulation according to
the main construction progress
Set up 3d construction log According to the actual construction
progress, combining with the real model,
record the real construction progress by 3d
dynamic; update the 3d log weekly or
monthly according to the site construction
log
Completion Establish completion model Establish a real and complete completion
stage model in order to provide an accurate basis
for the later operation and management
based on the three-dimensional model

Construction Safety Management

In order to ensure the construction safety of an IC production line, it is necessary to

establish sound rules and regulations, clarify the rights and obligations related to
safety matters, and conduct construction safety management. The general safety
management rules are as follows. (1) The general contractor for construction must
possess the registered capital stipulated by the State and meet the requirements of
professional and technical personnel, technical equipment, and conditions for safety
production. It must have all corresponding registered qualification certificates
according to law and contracted the project within the scope of its qualification
registration permission. (2) The project manager shall be fully responsible for the
safety work of the contracted projects according to law, establish and improve the
production safety responsibility system and the safety education and training system,
formulate safety production rules and regulations and operational procedures, ensure
the investment of funds required for safe production conditions, and conduct regular
and special inspections and keep safety records. (3) The person in charge of safety
must have corresponding professional qualifications, be responsible for the safe
construction of construction projects, ensure the effective use of safe production
costs, organize and formulate safe construction measures according to the charac-
teristics of the project to eliminate potential safety hazards, and report timely and
truthful safety production accidents. (4) The expenses required for a safe working
environment and safety measures included in the proposed project budget shall be
used for the procurement and renewal of construction safety protective equipment
and facilities, the implementation of safety measures, and the improvement of safe
production conditions and shall not be used for other purposes. (5) Establish the
corresponding safety management organization, with full-time safety production
management personnel. (6) Special operators (e.g., vertical transport machinery
636 S. Wang

operators, installation and disassembly workers, lifting signal workers, and

ascending erecting workers) must be trained in special safety operations in
accordance with the regulations of the relevant state departments and obtain
various operation qualification certificates before they can start work. (7) Before
the construction of the project, the technical person in charge of the project
management shall make detailed instructions on the technical requirements for
safe construction to the construction teams and the operators. (8) Obvious safety
warning signs shall be set at the entrance of the construction site, construction
cranes, temporary power facilities, scaffoldings, access passages, staircases,
elevator shafts, hole openings, and storage places of hazardous gas and liquid.
(9) The office at the construction site shall be set separately from the operation
area and maintain a safe distance. Special protective measures shall be taken to
prevent possible damage to adjacent buildings, structures, underground pipe-
lines, etc. due to construction. (10) Establish a fire safety responsibility system
at the construction site, determine the person in charge of fire safety, and
formulate various fire safety systems and operating procedures for fire, electric-
ity, and use of flammable and explosive materials. (11) Provide safety protective
equipment to the operators and inform them in writing of the operating pro-
cedures of dangerous positions and the hazards of illegal operations. (12) The
operators shall have the right to criticize, report, and sue the safety problems in
the operating conditions, procedures, and methods of the construction site, and
shall have the right to refuse command in violation of regulations and risky
operations. (13) Operators should abide by the mandatory standards, rules, and
regulations and operating procedures for safe construction, and use safety pro-
tective equipment and machinery properly. (14) All purchased and leased safety
protective equipment, machinery, construction equipment, and accessories shall
have production (manufacturing) licenses and product qualification certificates.
(15) Before the erection of construction lifting machinery and scaffolding, the
relevant departments or units shall be organized to conduct inspection and
acceptance.

Monitoring of Central Supply System

The central supply systems refer to stably transfers raw materials (e.g., gas and
chemicals) from the supply equipment to the technology production equipment in
order to meet the needs of the IC technology on the premise of fully guaranteeing
the technology and safety. In order to meet the requirements of production, the
state of the central supply system shall be tested before operation. Let’s introduce
the test of the central supply system. (1) Calibration: Use factory calibration,
whenever possible, and keep calibration records for verification. Before the system
is handed over, the constructor shall issue a valid calibration document for each
piece of equipment. The accuracy of equipment used for factory or on-site cali-
bration (if required) must be one level higher than that of the calibrated instrument,
31 Construction and Management of IC Production Lines 637

and the type should be indicated. (2) The factory tests: The contractor shall
explain the factory acceptance plan in writing. The test procedure includes a
detailed testing process, and all the tests should be conducted with the witness of
the owner or his client. These test states should be as close as possible to the
expected actual working states (including normal operation and system failure
conditions). (3) On-site acceptance tests: The site acceptance tests shall include
running acceptance, functional acceptance, and durability tests. (a) The running
acceptance tests. Each piece of equipment must be tested for running acceptance.
Before the trial run, the constructor must confirm that the parameters of each
equipment to be tested are consistent with the requirements and in good working
condition. The constructor should check that the instrument is installed correctly
and make adjustments appropriately. At least one document containing 5 levels
(0%, 25%, 50%, 75%, and 100%) must be prepared to confirm the calibration
status. The operating status of all systems in the failure and power down mode shall
be verified. Besides, it shall be also verified whether the system can returns to the
most recent control and monitoring mode established when it returns to normal and
powers on. The constructor shall submit a report in writing to inform the owner or
the client to certify that the installed system has been calibrated, tested, and
functional acceptance testing is available. (b) Functional acceptance tests. After
the successful completion of the running acceptance test and submission of the
written report by the constructor, as well as receiving the written permission from
the customer or the client, the functional acceptance test can be performed. The
constructor should check the site preparation conditions, check whether the site
conditions meet requirements of the power wiring and grounding, check the
installation of all equipment, use the running diagnostic program to verify whether
the system is running normally and whether a communication connection is
established between the system and the components, check whether all the inputs
and outputs are working normally, and check whether there is a normal commu-
nication signal between the system and the factory monitoring system.
(c) Durability tests. A specified durability test shall be performed by the construc-
tor to demonstrate the reliability of the system. Durability testing can only be
carried out when the constructor notifies the design unit, or the owner, in written
form that the trial run has been successfully completed, and the designated training
has been completed and the significant errors have been corrected. Durability test
must be performed 24 h a day for 7 days, and the operation status of system should
be consistent with the requirements. The constructor shall not carry out any
maintenance during the test unless authorized by the owner. If there is no failure
of the system during the test, the constructor can evaluate it directly after receiving
the written permission of the owner. After the successful completion of the
durability test, the constructor shall provide the test report and other documents
before the owner receives the system. If the test fails, the constructor shall analyze
the causes of the failures and repair it, then issue a written report to detail the nature
of each failure, the corrective actions, the results of the test, and recommend
whether the test continue at this point.
638 S. Wang

References
1. T. Wakuda, K. Nagata, M. Kojima, Construction of an energy-saving semiconductor plant, in
1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
(Cat. No.97CH36023), San Francisco, CA, USA, 1997, pp. P57–P60. https://doi.org/10.1109/
ISSM.1997.664623
2. O. Suenaga, S. Kobayashi, T. Ohmi, A proposal for energy saving in semiconductor fabs, in 1999
IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat
No.99CH36314). https://doi.org/10.1109/ISSM.1999.808784
3. A. Sinha, W.A.C. Fernando, Analysing and realising wireless mesh networks as a replacement
for lon based distributed control networks for clean room environment, in 2007 Canadian
Conference on Electrical and Computer Engineering, Vancouver, BC, Canada, 2007,
pp. 357–359. https://doi.org/10.1109/CCECE.2007.97
Hazardous Chemicals Management
32
Deyuan Xiao

Contents
Procurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Disposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

Abstract
This chapter gives a comprehensive explanation about the management of haz-
ardous chemicals in IC production lines. Hazardous chemicals are under specific
management systems following the state’s regulations. All five procedures of
procurement, transportation, storage, usage, and disposal of hazardous chemicals
require professional and licensed personnel with clear responsibilities. Safety
management, such as the education of safety and health information, marking
safety labels on special designed tools and equipment with compliant handling
methods, should be thoroughly implemented. Reliable hazardous chemical man-
agement needs close collaboration from the fab staffs and third-party suppliers;
it’s critical to carefully follow every procedure.

Keywords
Hazardous chemicals · Safety management · Procurement · Transportation ·
Storage · Usage · Disposal

D. Xiao (*)
SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
e-mail: Deyuan.Xiao@sienidm.com

© Publishing House of Electronics Industry 2024 639

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_32
640 D. Xiao

Management and handling of hazardous chemicals can be discussed in the following

five procedures, i.e., procurement, transportation, storage, usage, and disposal of
hazardous chemicals. More recent information of the hazardous chemical manage-
ment is in references [1–8].

Procurement

The procurement of hazardous chemicals shall be performed in accordance with the

following requirements: operating according to law; strictly implementing the
licensing and filing systems of the state for the management of hazardous chemicals;
and operating hazardous chemicals in strict accordance with the scope of business
licenses and modes of operation. (1) Purchase staffs or salesmen should participate
in training and learning of applicable laws, regulations and related knowledge of
hazardous chemicals and safety management, and pass the examinations to be
qualified. No person without a witness shall engage in the business of hazardous
chemicals. (2) Purchasers and salesmen should study the relevant management
system of hazardous chemicals purchasing and selling and other safety management
rules and regulations, and be familiar with the safety responsibilities, business
processes, and operating procedures. (3) The purchase and sale of hazardous
chemicals shall have a detailed account with detail information recorded, e.g.,
name of the supplier and purchaser, the variety, quality, quantity, and date of
purchase. Monthly review of purchasing and sales accounts of hazardous chemicals
is required to ensure that accounts, materials, and certificates (vouchers) are in place.
(4) Hazardous chemicals shall not be sold to production or business units and
individuals that have not obtained production or business licenses or completed
the formalities for filing. The quality, packaging, marking, and protection of hazard-
ous chemicals purchased and sold must conform to the national standards, rules, and
regulations for the purchase of chemicals. (5) The handling of hazardous chemicals
shall strictly implement the relevant management systems for handling and trans-
portation of hazardous chemicals. Shipping companies and workers shall be aware
of the physical and chemical characteristics and protection requirements of the
loaded and unloaded hazardous chemicals and shall wear and use appropriate
protective articles in accordance with regulations. (6) Purchasers, salesmen, and
transmitter should be aware of the physical and chemical characteristics, dangerous
categories, and grades of hazardous chemicals to be purchased and sold, as well as
the safe transport mode, safety protection requirements, and emergency measures.
(7) In case of loss or theft of hazardous chemicals in the course of business operation,
the leaders of the units, local safety supervision and management departments,
public security organizations, and health and environmental authorities shall be
notified immediately. (8) If illegal purchasing and selling of hazardous chemicals
are found in the course of business operation, they shall be stopped and checked
immediately and reported to the local safety supervision and management depart-
ments and public security organization.
32 Hazardous Chemicals Management 641

Transportation

The transportation of hazardous chemicals shall be carried out in accordance with the
following requirements. (1) It shall take necessary safety and protection measures in
accordance with the provisions of relevant laws, statutes, regulations, and the
requirements of national standards, as well as special requirements of specific
hazardous chemicals. (2) Containers used for chemical transport shall be
manufactured at designated sites by specialized production enterprises and shall be
used only after passing the appropriate tests and inspections. The quality inspection
department shall perform periodic or irregular inspection on the quality of the
containers produced by designated manufacturers in accordance with the regula-
tions. (3) Tanks or containers transporting hazardous chemicals must be sealed
tightly to withstand internal and external pressures under normal transportation
conditions and ensure that no leakage or rupture occurs due to changes in temper-
ature, humidity, or pressure in the transportation. (4) When hazardous chemicals are
transported by road, they must be equipped with escorts and under the supervision of
escorts at any time. They are not allowed to be overloaded or to enter areas where
vehicles transporting hazardous chemicals are forbidden; if absolutely necessary, the
local public security department must be notified in advance. Vehicles must abide by
the driving times and routes designated by the public security department. The areas
where vehicles transporting hazardous chemicals are prohibited shall be delimited by
the Public Security Department of the municipal government with districts and
prohibited areas clearly marked. When parking and special accommodation are
needed during the transportation of hazardous chemicals or normal transportation
is not possible, the report shall be submitted to the local public security department.
(5) Vehicles transporting hazardous chemicals should be special-purpose vehicles
with obvious signs and conform to the regulations of traffic management depart-
ments on vehicles and equipment: trailers and beds must be flat and intact, and the
surrounding panels must be firm; motor vehicle exhaust pipes must be equipped with
effective heat insulation and a device for extinguishing sparks, and circuit systems
should be equipped with devices to cut off the total power supply and isolate sparks.
The flag with the word “Dangerous Goods” in black and yellow background must be
hung in the left front of vehicles. According to the nature of the dangerous goods
loaded, it should be equipped with corresponding fire-fighting equipment and tools.
(6) Regularly inspect the radioactive contamination level of special transport vehi-
cles, equipment, moving tools, and protective equipment that transport radioactive
isotopes. When the amount of contamination exceeds the allowable level specified, it
shall not continue to be used. (7) Vehicles transporting containers, large cylinders,
movable containers, etc. must have effective fastening devices. (8) All kinds of
handling machinery and tools should have sufficient safety factors. Measures to
eliminate sparks must be taken when handling flammable and explosive dangerous
goods. (9) The hazardous chemicals that produce a dangerous reaction if in contact
with each other or with fire-fighting methods must have different fitting connectors
or the chemicals can’t be transported in the same vehicle or ship. (10) Flammable
642 D. Xiao

and explosive materials can’t be transported in cars and ships with iron bands and
bottoms. (11) Flammable goods with flash point below 28  C should be transported
at night when the temperature is lower than 28  C. (12) Vehicles transporting
hazardous chemicals should have fire and explosion-proof safety measures. (13) It
is forbidden for unrelated, or unlicensed, persons to take vehicles and other means of
transport for carrying hazardous chemicals. (14) For the transport of explosives and
hazardous chemicals requiring vouchers, they should have the “Permit to Transport
Explosives” or “Permit to Transport Hazardous Chemicals” issued by the public
security departments of prefectures, counties, and municipalities. (15) Hazardous
chemicals transported by air shall be carried out in accordance with the relevant
provisions of the Civil Aviation Department of the State Council.

Storage

The storage of hazardous chemicals should be carried out according to the following
requirements. (1) Hazardous chemicals must be stored in accordance with national
laws, regulations, and other relevant provisions. (2) Hazardous chemicals must be
stored in special hazardous chemicals warehouses approved by the public security
department. The hazardous chemicals stored in warehouses by distribution depart-
ments and storage quantity must be approved by the public security department.
Hazardous chemical storage warehouses shall not be set up at will without approval.
(3) Hazardous chemicals should be stored in the open air in accordance with the
safety requirements of fire prevention and explosion proof. Explosives, first-class
inflammable, wet burning, and highly toxic articles should not be stored in the open
air. (4) Warehouses storing hazardous chemicals must be equipped with technical
personnel with professional knowledge, and their warehouses and sites should be
managed by special personnel that must be equipped with reliable personal safety
protective equipment. (5) Hazardous chemicals stored should be clearly marked.
When two or more dangerous goods of different grades are stored in the same area,
they shall be marked according to the performance of the highest grade dangerous
goods. (6) There are three ways to store dangerous chemicals: segregated storage,
cut-off storage, detached storage. (7) Hazardous chemicals are stored in different
zones, categories, and warehouses according to its performance. All kinds of dan-
gerous goods shall not be mixed with prohibited materials for storage. (8) Smoking
and open fire are strictly prohibited in buildings and areas where hazardous
chemicals are stored. (9) No basement or other underground building is allowed
for storage of hazardous chemicals. Their fire-resistant grades, storage numbers,
occupied areas, evacuation requirements, and fire-resistant spacing shall conform to
the relevant provisions of the state. (10) Storage sites and building structures shall
not only comply with the relevant provisions of the state, but also consider the
impact on the surrounding environment and residents. (11) Lightning protection
equipment must be installed in buildings storing flammable and explosive hazardous
chemicals. (12) Ventilation equipment must be installed in buildings storing
32 Hazardous Chemicals Management 643

hazardous chemicals and shall pay attention to the protective measures of equip-
ment. (13) The ventilation and exhaust system for buildings that store hazardous
chemicals shall be equipped with grounding devices for eliminating static electricity.

Usage

The use of hazardous chemicals should be implemented in accordance with the

following requirements: (1) Chemicals used should be marked; and hazardous
chemicals should have safety labels and provide safety technical instructions to
operators. (2) When purchasing hazardous chemicals, the user must check the safety
labels on the package (or container). If the safety labels fall off or are damaged, they
shall be relabeled after checking and confirming. (3) When the chemicals purchased
by the user need to be transferred or sub-packed into other containers, their contents
shall be marked. For hazardous chemicals, safety labels should be attached to the
containers after transfer or sub-loading. Containers containing hazardous chemicals
should not change the original safety labels before being cleaned of all residual
materials. (4) Users shall regularly inspect and evaluate the hazards caused by
hazardous chemicals used in the workplace and file the results of inspection and
evaluation. The concentration of hazardous chemicals exposed to operators should
not be higher than the standards prescribed by the state; if there is no such regulation
available, the users shall use them in the case of ensuring safe operations. (5) Users
should eliminate, reduce, and control hazards caused by hazardous chemicals in the
workplace by the following methods: ① to select non-toxic or low-toxic chemical
substitutes; ② to select technologies that can eliminate or minimize hazards; ③ to
adopt engineering control measures that can eliminate or reduce hazards (e.g.,
isolation, sealing, etc.); ④ to adopt working institutions and hours that can reduce
or eliminate hazards; and ⑤ to adopt other labor safety and health measures. Users
should have first aid facilities in hazardous chemicals workplaces and provide
emergency treatment methods. (6) Users shall remove chemical wastes and wash
waste containers containing hazardous chemicals in accordance with relevant regu-
lations of the State. (7) The users shall mark the danger of the equipment for loading,
transporting, and storing dangerous chemicals in the form of color, sign, and label. (8)
Users shall publish safety and health information about hazardous chemicals to their
employees, educate them to identify safety labels, understand safety technical speci-
fications, master necessary emergency treatment methods and self-rescue measures,
and regularly educate and train them on the safe use of chemicals in the workplace.

Disposal

The disposal of hazardous chemicals should be performed in accordance with the

following requirements. (1) It is prohibited to store combustible waste in hazardous
chemicals storage areas. (2) Packaging containers that leak hazardous chemicals
644 D. Xiao

must be quickly transferred to safe areas. (3) All hazardous chemical wastes should
be stored in special labeled containers and transported to designated sites for waste
disposal. (4) According to the characteristics of hazardous chemicals, waste mate-
rials should be treated by chemical or physical methods. They should not be
discarded arbitrarily to prevent pollution of water sources and the environment. (5)
Waste disposal should be carried out according to the relevant operating rules and the
relevant personnel should accept the relevant business training. (6) Enterprises shall
develop disposal plans for hazardous chemical wastes and equipment that may be
generated and assess the occupational safety, health, and environmental impact of
this plan. (7) All disposal processes (e.g., sewage discharge, waste disposal, trans-
portation and landfill, and waste gas emptying) should ensure the safety and health of
the operators and the protection of the operating and the surrounding environment.
(8) Enterprises should set up waste disposal and storage sites with sufficient site
space to prevent waste containers from mixing in the normal processing and storage
sites. (9) Waste containers should be designed and selected with the following
considerations in mind: identification, structure, integrity, and protection. (10)
Appropriate personal protective equipment shall be provided to operators during
the disposal process and corresponding systems for the use, maintenance, and
management of them shall be formulated. (11) When the enterprise does not set up
waste treatment devices and supporting facilities in the workplace, it shall be
disposed by specialized agencies in accordance with relevant national laws, regula-
tions, and standards. (12) Separate work areas should be set up when waste is
disposed by incineration, chemical oxidation, neutralization, and other methods
whose design, construction, operation, and management shall meet the requirements
of relevant national laws and regulations. (13) The disposal of wastes and containers
should be subject to supervision and inspection by the environmental protection
administration department. The departments responsible for the supervision and
administration about safety of hazardous chemicals shall, upon receiving the reports,
promptly handle them according to laws. If the case does not fall within the
responsibility of the department concerned, it should be promptly transferred to
the relevant department for handling.

References
1. Acquisition of Hazardous Chemicals, https://www1.grc.nasa.gov/wp-content/uploads/
ohpm14.pdf
2. Chemical Management, https://www2.education.vic.gov.au/pal/chemical-management/proce
dure/5-procurement-dangerous-goods-and-hazardous-chemicals
3. Chemical Purchase, https://www.polyu.edu.hk/hso/our-services/chemical-purchase/
4. General Safety Considerations, https://www.uh.edu/ehs/labs/chemical-safety/procurement/
5. How to transport hazardous chemicals, https://www.royalchemical.com/blog/transporting-
hazardous-materials
32 Hazardous Chemicals Management 645

6. Rules for the Hazardous Chemicals Warehouse Storage in China Effective from July 1, 2023! https://
www.cirs-group.com/en/chemicals/gb-15603-2022-general-rules-for-the-hazardous-chemicals-ware
house-storage-released-effective-from-july-1-2023
7. Consumption of hazardous chemicals, https://www.eea.europa.eu/airs/2018/environment-and-
health/production-of-hazardous-chemicals
8. T.S.S. Dikshith, P.V. Diwan, Industrial guide to chemical and drug safety, Ch. 17, in Disposal of
hazardous chemicals, (18 April 2003). https://doi.org/10.1002/0471426075.ch17
Energy Savings and Development Trends
33
Deyuan Xiao and Janet Zeng

Contents
Energy Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Main Measures for Saving Energy and Reducing Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Current Status and Development Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Development Status and Opportunity in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

Abstract
This chapter discusses the types of energy used in the typical IC production lines
and some energy-saving methods for the reduction of power consumption.
Generally, electric energy consumption is the main part, while others, e.g., city
water, heat, natural gas, and air, are the secondary. To operate a cost-efficient fab,
there are a lot of proven energy-saving practices as listed in this chapter, e.g., the
optimization in air and water treatment, fab space design, and materials recycle as
well as reclaim. Further, as the applications from consumer-end developed
rapidly, the advanced IC production has increasingly progressed over recent
decades with automation, new equipment, and technologies. China will continu-
ously develop the capabilities in IC production and establish more advanced fabs
in fast pace with high efficiency and technology levels. It is much more than
massive capital investment, management experiences, and collaboration with
partners toward long-term success. As the strong competition internationally,
there will be more and faster development of IC production lines in future
AI/IoT era.

D. Xiao (*) · J. Zeng

SiEn (Qingdao) Integrated Circuits Corp, Qingdao, China
e-mail: Deyuan.Xiao@sienidm.com

© Publishing House of Electronics Industry 2024 647

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_33
648 D. Xiao and J. Zeng

Keywords
Energy consumption · Energy-saving · Optimized treatment · Recycle · 300 nm
wafer production line · Automation · Manufacturing capacity · Competitiveness ·
Uncertainty

In this chapter, the following subjects are discussed: (1) energy consumption,
(2) energy saving, (3) status and trends in fabs, and (4) development opportunities.
More information of the energy saving and development trend, for further reading, is
found in references [1–5].

Energy Consumption

The energy consumption of IC production lines can be estimated from the power
consumed by production equipment and supporting facilities as the majority of
the total energy consumption. The production equipment are those used in the
manufacturing, e.g., photolithography, thin-film, etching, ion implantation, ther-
mal annealing, chemical vapor deposition (CVD), etc. Supporting facility equip-
ment, on the other hand, includes air-condition system, ultra-pure DI water
system, cooling water system, cooling tower and water pump, waste water/gas/
chemical treatment systems, fresh air units, fan filter units (FFU), fans, bulk-gas
generation and purification, special gas and chemical delivery systems, etc. After
the primary energy consumption is calculated, then various analysis on the
energy consumption per wafer per technology node can be estimated for com-
parison, and indicators of energy saving can be made accordingly. An example of
estimation of energy consumption of a typical 300 mm wafer fab is shown in
Table 33.1 for references.

Main Measures for Saving Energy and Reducing Consumption

The main energy consumption in the IC production is electrical energy. At the same
time, secondary energy (e.g., tap water, heat, natural gas, compressed air, nitrogen,
oxygen, hydrogen, argon, and helium) is also consumed in the IC production. The
distribution of power consumption of a typical fab is shown in Fig. 33.1 for
references.
The main measures for energy saving and consumption reduction in IC produc-
tion are as follows. (1) Optimize fresh air treatment: reasonably reduce the air
supply and preheating temperature of fresh air fan and utilize the fresh air fan with
heat recovery. (2) Reduce the fresh air volume: reduce the exhaust volume of the
clean room and reasonably reduce the positive pressure of the clean room. (3)
33 Energy Savings and Development Trends 649

Table 33.1 Estimation of energy consumption of a typical 300 mm wafer fab

Serial Energy and types of energy-consuming
number working fluid Specifications Usage
1 Electrical power 208 V/380 V/ 67,000 kVA
480 V
2 Tap water – 10,000 m3/d
3 Ultra-pure water 18.2 Ω
cm, 12,647 m3/h
23  C
4 Process equipment cooling water (PCW) 16.5  C 6,857 m3/h
5 Cooling water at room temperature 32  C/37  C 27,000 m3/h
6 Natural For canteen 0.003 MPa 150 m3/h
gas For organic waste gas treatment 0.015 MPa 200 m3/h
systems
For point of use (POU) 0.1 MPa 300 m3/h
For boiler 0.03~0.09 MPa 3,520 m3/h
7 Compressed air >0.85 MPa 28,752 m3/h
8 High purity nitrogen 0.85 MPa 7,547 m3/h
9 Ultra-high purity nitrogen 0.85 MPa 12,789 m3/h
10 Ultra-high purity hydrogen 0.75 MPa 120 m3/h
11 Ultra-high purity oxygen 0.75 MPa 171 m3/h
12 Ultra-high purity argon gas 0.75 MPa 99 m3/h
13 Ultra-high purity helium 0.75 MPa 51 m3/h
Note: The data for items 7–13 are the gas volumes at the conditions of 0  C and 1 atm
(i.e., 101.325 kPa)

Fig. 33.1 Distribution of

power consumption of a
typical fab

Adjust the operating time of air conditioning system in the office buildings. In the
transitional season, increase the supply of fresh air as much as possible, and then
remove the heat of the room through the fresh air. (4) Reasonably layout the floor
to reduce power loss in power supply lines. (5) The clean room adopts micro-
650 D. Xiao and J. Zeng

environment control mode, i.e., areas with higher cleanliness level for more
critical operations and lower cleanliness level for less critical operations, so
that the energy consumption may be reduced significantly. (6) When using filter
units in production and supporting areas, it shall be properly allocated to reduce
the energy consumption of unnecessary filter units. (7) Reasonably assess the
requirements of each area and allocate according to the real need, avoiding
excessive energy consumption due to over-spec with unnecessary allocation.
(8) The energy consumption of a large clean room with constant temperature
can be reduced by using new thermal insulation materials in the outer wall of the
building to reduce the heat transfer between the indoor and outdoor environ-
ments. (9) Reduce power consumption through natural cooling of external envi-
ronment. (10) The cooling water of all equipment can be recycled with closed
loop system structure to save tap water consumption. (11) Collect rainwater in the
whole plant area for irrigation of the trees and grass on site. (12) Recycle high
purity cleaning water and DI water after cleaning Si wafer for scrubbing tower
and gardening purposes. (13) Utilize the residual pressure of municipal water
supply to supply tap water for reducing the use of pumps and electricity. (14) The
local drainage is collected, treated, and recycled. (15) Waste sulfuric acid recov-
ered from waste acid treatment stations can be used for sewage treatment systems
(e.g., adjust pH values). (16) Maintain power factor of power system to above
0.95 by non-power compensation device for reducing power loss in power
transformer and lines. (17) High efficiency and energy saving lamps are selected
for lighting system. Street lamps are powered by solar energy and controlled by
intelligent switch based on photo-electric principles. (18) Install illumination or
motion sensors near the window and inside the office to control the lamp switches
and save energy.

Current Status and Development Direction

There are about 100 IC fabs with 300 mm wafer size as of 2018 worldwide and with
additional 25 fabs by end of 2020. The number of 200 mm wafer fabs also increases
in 2018 and reaching to >210 by 2020. There may be slower growth in IC fabs due
to recent trade-war since 2019. In view of the nearly astronomical investment as well
as uncertain return-on-investment (ROI) and technical obstacles, the construction of
450 mm wafer fab was not actively developed as expected, and the pace of wafer fab
transition to 450 mm production line has slowed down significantly. According to
current development trends of global IC manufacturing, it’s expected that the
majority of IC manufacturing fabs still produce 300 mm wafers to maximize
the ROI.
At 10 nm node, Samsung, Intel, and TSMC are actively using multi-patterning
DUV lithography. At 7 nm node, Samsung, Intel, and TSMC all adopt EUV
lithography in production. Comparing with multi-patterning DUV, EUV is a lower
33 Energy Savings and Development Trends 651

cost lithography for 7 nm node and beyond as related to its shorter wavelength
(13.5 nm) for better resolution and single exposure for patterning. EUV lithographic
technology has advantages in better overlay accuracy and less masks and masking
steps (vs DUV’s multi-patterning) for high resolution and yield.
Most 300 mm IC production lines have Automated Material Handling System
(AMHS) with advantages of efficient use of clean room space, effective manage-
ment of wafers, and reduction of operators’ workload. In some 300 mm IC fabs,
handling system can be extended to various areas and transfer wafers to equipment
by overhead-hoist-transport (OHT). There are also fabs utilizing automatic guided
vehicle (AGV) for materials, parts, and semi-finished goods transferring.
Advanced IC manufacturing lines in the future will increase productivity and
competitiveness with the help of intelligent automation, including intelligent
control through equipment automation, intelligent knowledge management, reduc-
tion of costs and enhancement of standardization, improving operation efficiency
and product development cycles, and intelligent manufacturing through AI/IoT
technologies. Factory management process chart of modern smart IC fab is illus-
trated in Fig. 33.2.

Development Status and Opportunity in China

In the past 20 years, main-stream technologies in China’s IC production lines have

been developed from wafer size of 500 and 150 mm (for 0.5 μm node and above) to
200 mm (for 0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm, 0.11 μm, and 90 nm technology
nodes) and 300 mm (for 90 nm, 65 nm, 45 nm/40 nm, 28 nm, 14 nm, and 7 nm
technology nodes). Representative IC manufacturers have been increased, such as
SMIC, Shanghai Huali, Wuhan Xinxing, Huahong, China Resource Micro (CRMC),
and ASMC. Now SMIC’s technology level has matured to 14 nm/12 nm nodes at
2019. Huali Micro has been developing 28 nm/14 nm technology nodes as well as
evaluating FD-SOI technology. CRMC is in leading position in analog and high
voltage technologies. 2017 China major IC manufacturing lines are listed in
Table 33.2. China has become one of the countries/regions with the most IC
production lines as an indication of global IC industry transferring to China. It’s
estimated that until 2020, China’s IC manufacturing capacity will reach to
1100–1200 k/month. However, the recent trade war since 2019 between the USA
and China may add uncertainty to this trend.
At present, the construction of IC production lines appears increasingly larger and
complex. For production of logic circuit chips, the capacity of each new 300 mm IC
fab is more than 35,000 wafers per month (35 kW/month), while for production of
memory chips, the capacity is usually more than 100,000 wafers per month
(100 kW/month). When entering the 7 nm node and beyond, the introduction of
EUV will bring new challenges to automatic transport equipment, clean room
environment control, fire protection, environmental protection, and space
management.
 652

Fig. 33.2 Illustration of modern management of smart IC production line

D. Xiao and J. Zeng
33 Energy Savings and Development Trends 653

Table 33.2 Distribution table of 2017 China’s major IC manufacturing lines

Internal
identifier of
Wafer Serial manufacturing Production Technological
size/mm number Company name line capacity/(10 K/month) level
300 1 SMIC (Beijing) Fab4 3.5 90 nm, 65 nm
CMOS
B1/B2 3.5 each 65 nm, 40 nm, and
28 nm CMOS
2 SMIC (Shanghai) Fab8 1.0 90 nm, 65 nm,
40 nm, 28 nm
CMOS
3 Shanghai Huali Fab1 2.0 65 nm, 40 nm
Microelectronics CMOS
Corporation
4 Wuhan Xinxin 2.5 90 nm, 65 nm
Semiconductor CMOS and NAND
Manufacturing Flash
5 SK Hynix (Wuxi) Fab1 10.0 65 nm, 40 nm
DRAM
6 Fab2 6.0 90 nm, 30 nm
CMOS
7 Intel (Dalian) Fab68 6.0 65 nm CMOS
8 Samsung (Xi’an) - 10.0 20 + nm, 10 + nm
Flash
200 1 SMIC (Shanghai) Fab1 12.0 0.35 μm, 0.25 μm,
2 Fab2 0.18 μm, 0.13 μm,
0.11 μm CMOS
3 Fab3 3.0 0.13 μm, 0.11 μm
Cu interconnected
back-end technics
4 SMIC (Tianjin) Fab7 4.0 0.35 μm, 0.25 μm,
0.18 μm CMOS
5 TSMC (China) Fab1 11.0 0.25 μm, 0.18 μm,
0.13 μm CMOS
6 Shanghai Huahong Fab1 8.0 0.35 μm, 0.25 μm,
Semiconductor 0.18 μm,
0.13 μm, 0.11 μm
CMOS mix signal

7 Fab2 2.0
8 Fab3 5.0 0.35 μm, 0.25 μm,
0.18 μm,
0.13 μm, 0.11 μm,
90 nm CMOS
200 9 Hejian Technology Fab1 6.0 0.35 μm, 0.25 μm,
(Suzhou) 0.18 μm, 0.13 μm
CMOS
10 Fab2 4.0 0.13 μm CMOS
11 Shanghai Advanced Fab3 1.5 0.35 μm, 0.25 μm
Semiconductor CMOS mix signal
Manufacturing
Corporation
(continued)
654 D. Xiao and J. Zeng

Table 33.2 (continued)

Internal
identifier of
Wafer Serial manufacturing Production Technological
size/mm number Company name line capacity/(10 K/month) level
12 China Resource 6.0 0.35 μm, 0.25 μm,
Group-CSMC 0.18 μm,
(Wuxi) 0.13 μm, 0.11 μm
CMOS mix signal
13 Yude 3.0 0.35 μm, 0.25 μm,
Semiconductor 0.18 μm
(Chongqing) CMOS Mix signal
14 Chengxin Fab11 3.0 0.35μm, 0.25 μm,
(Acquired by Texas 0.18 μm
Instrument) CMOS mix signal
(Chengdu)
15 Jingchen 3.0 0.35 μm, 0.25 μm,
Semiconductor 0.18 μm CMOS
(Zhengzhou)
150 16 Xiyue Electronics 1.7 0.5 μm, 0.35 μm
(Xi’an) mix signal
17 Fujian Fushun 1.8 0.8 μm, 0.5 μm mix
(Fuzhou) signal
18 Leshan-Phoenix 3.0 0.5 μm bipolar
Semiconductor
(Leshan Sichuan)
19 Xiamen Jishun 6.0 0.5 μm, 0.35 μm
mix signal
20 Institute of 2.0 0.35 μm, 0.25 μm,
microelectronics, 0.18 μm CMOS
Chinese Academy
of Sciences
1 China Resource Fab1 6.0 0.5 μm, 0.35 μm
Group- CSMC BCD
(Wuxi)
2 China Resource Fab5 3.5 0.5 μm, 0.35 μm
Group-CSWC BCD
(Wuxi)
3 China Resource 5.0 1 2 μm, 0.8 μm
Group- Huajing analogy
Microelectronics
(Wuxi)
4 Shanghai Advanced Fab2 4.0 1 5 μm, 1.2 μm,
Semiconductor 0.8 μm,
Manufacturing 0.5 μm BCD
Corporation
5 Shanghai BCD 5.0 1.5 μm, 1.2 μm,
Semiconductor 0.8 μm,
Manufacturing 0.5 μm BCD
6 Shanghai Diodes 3.0 1 0 μm, 0.8 μm,
0.5 μm,
0.35 μm mix signal
(continued)
33 Energy Savings and Development Trends 655

Table 33.2 (continued)

Internal
identifier of
Wafer Serial manufacturing Production Technological
size/mm number Company name line capacity/(10 K/month) level
7 Wuxi KEC 3.0 1.5 μm, 1.2 μm,
0.8 μm,
0.5 μm BCD
8 Shougang NEC 3.0 1.0 μm, 0.8 μm,
(Beijing) 0.5 μm,
0.35 μm mix signal
150 9 Beijing Yandong 2.0 1.0 μm, 0.8 μm,
0.5 μm,
0.35 μm mix signal
10 Hangzhou Silan 3.0 1.0 μm, 0.8 μm,
0.5 μm,
0.35 μm mix signal
11 Hangzhou Li-On 1.5 0.8 μm, 0.5 μm,
Microelectronics 0.35 μm mix signal
12 BYD 3.0 0.8 μm, 0.5 μm
Semiconductor BCD
(Ningbo)
13 Jiangsu Dongguang 1.5 0.8 μm, 0.5 μm,
Electronics 0.35 μm mix signal
14 Zhuhai Nanke 3.0 0.5 μm, 0.35 μm
CMOS
15 Shenzhen 2.5 0.5 μm, 0.35 μm
Founder CMOS

References
1. Energy consumption WW.: https://www.iea.org/reports/key-world-energy-statistics-2021/final-
consumption
2. S.-C. Hu, and Chuah, Y.K.: Power consumption of semiconductor fabs in Taiwan. Energy 28 (8),
2003, Pages 895–907. https://www.sciencedirect.com/science/article/abs/pii/
S0360544203000082
3. Derbyshire, K.: Saving Energy in the Fab, 19 Nov 2015. https://semiengineering.com/saving-
energy-in-the-fab/
4. Lapedus, M.: China accelerates foundry, power semi efforts, 22 Nov 2021. https://
semiengineering.com/china-accelerates-foundry-power-semi-efforts/
5. Leopold, G.: China’s wafer capacity jumps. EETimes-ASIA, 21 Feb 2022. https://www.eetasia.
com/chinas-wafer-capacity-jumps/
 Section V
Integrated Circuit Design
Shaojun Wei, Xiaolang Yan, and Yuhua Cheng

Introduction

Integrated circuit design is an important part of integrated circuit (IC) industry and
also is the core of IC product innovation and technological progress. IC design
follows the basis and criteria of IC manufacturing to guide the development direction
of manufacturing technology and support the market demand of system manufac-
turers. In this chapter, the technical basis of IC design is firstly expounded, including
the design specifications, design processes, process design package (PDK),
customer-owned technology (COT), standard cell library, circuit diagram, input/
output, clock design, leakage current, power consumption, design simulation, func-
tional verification, place and route, as well as physical verification and layout
delivery. In addition, the categories including their characteristics, performance
indicators, design methods and development trend for digital ICs, analog ICs,
radio frequency (RF) ICs, and power ICs are introduced respectively. Furthermore,
processors, memories, system chips, and programmable logic circuits are taken as
design examples. Their applications, circuit composition, technical features, and
practical designs are introduced in detail. Finally, the electronic design automation
(EDA) methods are comprehensively analyzed, and various EDA tools involved in
IC design process are briefly introduced.
Overview of IC Design
34
Shouyi Yin

Contents
Overview of Global IC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Overview of IC Design in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Supporting Role of IC Design to System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Design and Technology Co-Optimization (DTCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

Abstract
This chapter introduces the development, business model, and market of the
global IC design industry. With the introduction of the development process in
various stages, it summarizes the development characteristics of China’s IC
design industry and the future of this industry. From the point of view of
microprocessors, memories, and other chip products, it expounds the supporting
role of integrated circuit design industry with respect to the computer industry,
and vice versa, the market guiding of the role of the computer industry to the IC
design industry. Finally, it is emphasized that IC manufacturing is the basis of
chip design and the need of co-development among design and manufacturing
teams.

Keywords
IC design industry · Business model · System support · DTCO

S. Yin (*)
Institute of Microelectronics, Tsinghua University, Beijing, China
e-mail: yinsy@tsinghua.edu.cn

© Publishing House of Electronics Industry 2024 659

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_34
660 S. Yin

Overview of Global IC Design

An IC design company is also known as a fabless design with no wafer fabrication

facility (or Fab) in the company [1]. IC design business is the main body or sector in
IC industry with the core business in IC design, technical support, and sales of
products. IC design companies do not own IC manufacturing facilities, instead,
engage with third party for wafer fabrication (or foundries) and packaging and
testing services. The sales revenue of the IC design is about 70% ~ 80% of the
total global semiconductor industry (or loosely referred to as IC industry).
The business model of IC design companies can be generally divided into three
types, i.e., “Design House,” “Design Services,” and “IP Vendor,” or combination as
in the following: (1) The “Design House” model is mostly adopted by design
companies by defining, developing, and designing IC products according to market
needs from end users or system companies. Design companies are the owners of
these IC products with revenue from product sales. (2) The “Design Services”
company design IC products per specs from their customers (end users or system),
and also provide services of wafer production, packaging, and testing, from third
parties. However, the ownership of the final product belongs to the customer, and the
design service company charges a fee for all technical services. (3) The “IP Vendor,”
also known as the Intellectual Property Core (IP Core) provider, is engaged in the
design and verification of certain important functional circuit modules (i.e., IP cores)
in the form as software codes (soft core) or fully verified layout and performance
(hard core). These IP cores can be licensed to other design companies (with fees and
loyalty) and readily merged into larger IC designs. Such IP vendors are also known
as chipless IC company. All the above business models may be combined together,
e.g., design companies may also provide design services, and most design service
companies also have the ability of providing IP cores.
Today’s IC design companies rely heavily on advanced IC design tools. Thus,
those companies that develop IC design tools, also referred to as Electronic Design
Automation (EDA) vendors, are included in the IC design business. EDA vendors
begin to provide not only EDA tools but also IC design services and IP cores in order
to effectively promote their EDA tools. Therefore, EDA vendors are also emerged as
a kind of fabless design companies.
With knowingly the business model of foundry was mature in packaging and
testing sectors, a new business model of IC wafer foundry gradually established in
mid-1980s. The design, wafer manufacturing, packaging, and test are interdependent
and also relatively independent in IC industry chain; this further accelerated the
design industry into fast track. After nearly 40 years of development, the design
industry is now an important sector in IC industry. According to relevant statistics in
2021 [2], the IC design industry has sales of about 30% of the global semiconductor
market. Among the top 10 semiconductor companies worldwide, five are IC design
companies. In terms of national and regional distribution, the USA has the world’s
largest and accounting for about 68% of global design sales; China’s design sales
account for 9%, and China Taiwan alone accounts for 21% of global design sales [2].
34 Overview of IC Design 661

Overview of IC Design in China

The establishment of Beijing IC Design Center in 1986 is the first milestone of

China’s IC design industry. After more than 30 years of development, the IC design
has become the backbone of China’s IC industry. In 2016, the sales of China’s IC
design exceeded the sales of packaging and testing for the first time and ranked on
top; furthermore, the sales of IC design in Mainland China surpassed Taiwan, China,
as the second largest IC design behind the USA from a global perspective. Currently
in 2019, there are more than 2000 fabless design companies in China.
There are three development stages of China’s IC design industry. The first stage
(from 1986 to 1999) was the period when the IC design environment was established
and continuously grown to a solid foundation. The characteristics of IC design in this
period are that only handful number of companies who started with basic designs
and made small revenues. However, these early-established design companies sur-
vived and grew as the backbone as a solid foundation for the rising of China’s IC
design industry. The second stage (from 2000 to 2010) was a period of rapid
development of IC design. The number of companies exceeded 100, and the top
sales exceeding CN¥100 million. The design technology level has approached the
advanced level to some extent globally. Some excellent companies landed in domes-
tic and foreign capital markets. By 2010, the sales revenue of IC design exceeded CN
¥50 billion. The main features of this period were the establishment of relatively
complete ecological environment and a significant increase in industrial scale. The
third stage (from 2011 to present) is a period for continuously growing of the IC
design industry with high quality for future. The number of design companies
exceeded 1000 in 2016, 1600 in 2018, and more than 2000 in 2019. The IC design
industrial is continuously growing rapidly in sales (e.g., more than CN¥160 billion in
2016) and expanding the portfolio of IC products with high-quality grade. Currently
in 2019, China’s IC design industry is achieving advanced design level internation-
ally with a few outstanding companies among the top 10 worldwide. The IC design
industry in China is continuously growing for future Artificial Intelligence (AI) and
Internet-of-things (IoT) AI/IoT era.
There are six characteristics in the overall development of China’s IC design
industry. (1) The first is the industry’s rapid growth. The sales volume of the design
industry has increased from about CN¥300 million in 1999 to CN¥164.4 billion in
2016 [3] and to CN¥1045.8 in 2021 [4] with average compound annual growth rate
of 45%. Though the annual growth rate in recent years remained above 20%, this
growth rate is unique and impressive. (2) The second is the continuously consoli-
dated industrial base. The popularization of the top-down design technology, the
control of the market, the improvement of product definition capabilities, the
continuous improvement of the industrial chain, and the accumulation of experience
of the talent team continue to consolidate the development foundation of China’s IC
design industry. (3) The third is the reasonable industrial layout. At present, China’s
IC design industry is located at three largest regions, i.e., the Yangtze River Delta
region (with Shanghai as the leader), the Pearl River Delta region (with Shenzhen as
662 S. Yin

the leader), and the Beijing-Tianjin-Bohai Rim region (with Beijing as the leader).
Currently, the development of IC design industry in China’s central and western
regions is also very strong, e.g., Xi’an, Wuhan, Changsha, Chongqing, and
Chengdu. (4) The fourth is a complete range of IC products, but lack of high-end
chips. Though cell phone ICs are among world’s leading level, but most other high-
end core chips are lacking, e.g., Central Processing Unit (CPU), Digital Signal
Processor (DSP), memory, Field Programmable Gate Array (FPGA), and so
on. (5) The fifth is the eye-catching performance of outstanding companies and
also the low industrial concentration in China. At present, two Chinese IC design
companies are among the top 10 worldwide, though the sales ratio of these two
accounts for less than 50% of the total China IC industry sales. Compared with that
of 80% sales ratio in the USA, the former sales ratio in China is significantly smaller
as an indicator of significantly smaller industrial concentration. (6) The sixth is the
huge talent gap. At present, the number of employees in the IC design industry is
close to 130,000; and it is estimated that the IC design industry will require a total of
300,000 employees by 2020 [5]. It is urgently in need of reforming the IC engineer-
ing education policy and training programs.
Due to very strong market demand, the development of China’s IC design
industry can be expected to be growing rapidly in future years and playing a critical
role in IC design. The development of China’s IC design industry will also contribute
to the progress of global IC design industry for the benefit of worldwide technology
progress.

Supporting Role of IC Design to System

The IC products mainly include microprocessors, system chips, memories and

application-specific ICs (ASICs), etc., which are the core components of the entire
electronic systems as illustrated in Fig. 34.1. The system chip is usually the main
micro-processor; and the entire specific functions of system are implemented by
external camera, screen, wireless communication components, input/output periph-
erals, etc.

Fig. 34.1 Common structure

of entire machine system
34 Overview of IC Design 663

Fig. 34.2 Intel 4004 Processor

Currently, the entire electronic system with specific functions is increasingly

complicated and powerful as related to the enhanced performance of components.
The microprocessor is the core portion of the entire system. In 1971, Intel developed
the world’s first microprocessor (Intel 4004, as shown in Fig. 34.2) with 2300
transistors integrated by using a process node of 10 μm and clock frequency of
108 kHz; its computing power is very limited. Currently at 2018, the microprocessor
has accommodated 10 nm CMOS technology node with 256 billion transistors
integrated on the chip; the computing power is greatly enhanced. In addition, another
core component of the entire system is the semiconductor memory with large
memory capacity and read/write speed which is greatly enhancing the performance
of the entire system. Since the birth of semiconductor memory, the global market has
reached tens of billions of dollars, and the market size in China has reached CN¥180
billion. The advancement of IC design capability not only enhances the functions
and performance of the entire electronic system, but also implies a huge impetus to
the IC market.
The system manufacturer (or system house) is the closest to the end user
applications in the IC industry chain. The connection between the entire system
and capability of IC components requires the IC design company to perform IC
design to meet detail requirements in system and technology for achieving the best
performance of entire system. As an important part of the electronic system industry,
the IC design companies must serve as the technical link between system
664 S. Yin

applications and IC manufacturing and actively supporting the development of

electronic systems with IC technology.
Currently, China’s IC design industry has established good qualities and capabil-
ities, with some achieved important accomplishments [6]. It is foreseeable that
China’s IC design industry will continue to grow and play an increasingly important
role in the future.

Design and Technology Co-Optimization (DTCO)

The IC industry is an industry closely collaborated by system manufacturers, circuit

design, wafer manufacturing, and process equipment and materials. The IC design
serves as a link between the wafer manufacturing and system applications. The IC
designers and wafer manufacturers should work closely toward a goal of design and
technology co-optimization (DTCO) [7].
The IC design industry is at the upstream of IC industry chain with heavy capital
and technology intensive. The IC design performs circuit designs of various chips
(IC products) according to the requirements from systems; the physical design
(layout) needs to follow design rules based on the requirements from the manufactur-
ing technology. The physical design of layout and routing is critical to achieve the
desired circuit speed, signal integrity, and minimum chip areas. With the assistance
of EDA tools, IC design solutions can be simulated and optimized to achieve the best
performance and yield of IC products.
The advances in manufacturing processes can also enhance the functional design
capability for IC designers by enabling them with more resources or process margins
on chip to achieve better performance and higher on-chip flexibility for
reconfigurable architecture. As far as the current situation is concerned, though the
level of China’s IC design is keeping up with the leading edge, China’s IC chip
manufacturing technology is quite lagging behind the leading edge by 2–3 nodes.
Therefore, in order to alleviate the demand of domestic importing of high-end ICs, it
is urgent to actively develop China’s IC manufacturing technology as one of the
major goals in the National IC Industry Development Promotion Outline [8].
In short, the IC manufacturing technology provides the basis for IC design. The
advancement of manufacturing process technology can strengthen the design capa-
bility; the advancement of IC design technology also leads to new development
directions for manufacturing process. Therefore, both the IC design and manufactur-
ing technology need to be progressed in parallel.

References
1. Fabless Company.: https://www.investopedia.com/terms/f/fablesscompany.asp. Accessed
29 May 2023
2. Sales of Top 10 IC Design Companies., https://www.eetasia.com/top-10-ic-design-companies-
post-2021-revenue-topping-100b/. Accessed: 28 Oct 2022
34 Overview of IC Design 665

3. Digitimes Research: China IC production value to rise 15% in 2016, https://www.digitimes.

com/news/a20160704PD204.html. Accessed 28 Oct 2022
4. China’s IC Sales in 2021, http://en.c114.com.cn/583/a1190738.html. Accessed 28 Oct 2022
5. Talent shortage hampers China’s IC sector., http://www.ecns.cn/news/sci-tech/2018-08-20/
detail-ifyxccrz0968595.shtml. Accessed 01 Oct 2022
6. S.J. Wei, From entirely machine to machine— on the survival mode of China’s integrated circuit
design companies. China’s High and New-Technology Enterprise 1, 30–32 (2019)
7. G. Yeric, B. Cline, S. Sinha, et al., The past present and future of design-technology co-opti-
mization, in Proc. IEEE 2013 Cust. Int. Circ. Conf. 22–25 Sept, (2013). https://doi.org/10.1109/
CICC.2013.6658476
8. X. Yu, Analysis of China’s integrated circuit chip manufacturing industry from the ratio of three
industries. Application of IC 10, 6–8 (2014)
Basics of Integrated Circuit Design
35
Cheng Huang, Qinsong Qian, Chao Chen, Wei Ge, and Jian Cao

Contents
Design Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Digital IC Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Analog IC Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Process Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Customer-Owned Tooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Standard Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Circuit Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Input/Output Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
IC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Design Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Placement and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Physical Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Tape-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Electrostatic Discharge Protection Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

Abstract
This section focuses on the IC design flow and the related process design kit
(PDK). The design flow mainly consists of design specifications, circuit sche-
matics, design functional simulation, functional verification, layout (placement
and routing, physical verification), and tape-out. The PDK from process

C. Huang · Q. Qian (*) · C. Chen · W. Ge

National ASIC System Engineering Center, Southeast University, Nanjing, China
e-mail: qianqinsong@seu.edu.cn
J. Cao
School of Software and Microelectronics, Peking University, Beijing, China

© Publishing House of Electronics Industry 2024 667

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_35
668 C. Huang et al.

manufacturers (foundries) includes the process manufacturing information and

the standard cell library (for semi-automatic digital circuit design process). The
quality of input/output (I/O) and clock network is an important factor affecting
the reliability of ICs. The scaling of CMOS technology leads to power/energy
consumption issues. Leakage current is one of the key indicators of nowadays
ICs; moreover, the emergence of customer-owned technology (COT) enables
design applications with optimized performance of power consumption, layout
area, and trade-offs of technical threshold and investment cost.

Keywords
Design flow · PDK · Circuit schematics · Simulation · Functional verification ·
Layout · Power consumption

Design Specifications

Design specifications are proposed to bind the designers to normalize their designs.
It is generally a type of combinational information such as the work principle of IC,
chip architecture, inputs/outputs, electronic characteristics, and programming inter-
faces of software. The design specification is often shown as documents, algorithms,
source codes, system schematics, and so on.
Work Principle is a theoretical description about the global and local functions
of the ICs. It is usually showed as mathematical formula, physical performance, state
machine, high level models of digital and analog-mixed signal circuits design, and
IPs to be embedded. The power, performance, and area (PPA) of the chip design is
generally specified.
Chip Architecture includes the software and hardware architecture of ICs. The
hardware architecture describes the standards about the embedded CPU, on-chip or
off-chip memory, algorithm accelerating engine, interrupt controller, system bus,
clocks, peripheral interfaces, and so on. The software architecture describes the
standards about the hardware abstraction layer, operating system, software commu-
nication protocol stacks, and application software definition. Chip Architecture is
often showed by top-down design diagrams to describe the internal modules and
their interfaces in the chip.
Input/Output defines the input and output signals of the target IC, the timing
sequence with respect to other chips, the clock pins (pads), power/ground pads, and
chip package specification and size.
Programming Interfaces of Software describes the definition of programmable
registers of chip, such as the address and meaning of registers, hardware peripheral
driver, the definitions of the interface functions of hardware abstraction layer,
scheduling strategy of operating system, memory distribution strategy, software
communication protocol stacks, and so on.
35 Basics of Integrated Circuit Design 669

Design Flow

The design flow in VLSI is the sequence of processes/steps involved in designing an

IC [1–4]. Because the design complexity increases significantly, the design flow can
be divided into several stages or steps. Usually, there are mainly two design flows,
which are the digital IC design flow and the analog IC design flow.

Digital IC Design Flow

The digital IC design flow mainly includes steps such as system design, logic design,
logic synthesis, physical design, physical verification and tape out, etc. As shown in
Fig. 35.1, the physical design can be divided into steps, such as data import,
floorplan, placement, clock tree synthesis and routing, etc. Iteration is necessary in
the digital IC design flow. For example, if the simulation results in physical design
cannot meet the specification, the digital IC has to be redesigned in the logic design
stage; if the resources cannot be satisfied in routing, the floorplan has to be repeated
for more appropriate outcome. Multiple iterations of design flow should be avoided
as much as possible in digital IC design.

Fig. 35.1 The digital IC design flow with the physical design divided into more steps
670 C. Huang et al.

The specification in the digital IC design flow is used to specify the functions and
performances of chip undertaken according to the requirement from the users. In the
step of logic design, the logic operations of the design that represent the specification
are derived and tested in Register Transfer Level (RTL) description using Hardware
Description Language (HDL). Logic synthesis is a process which turns the RTL
logic circuits into a design implementation in terms of logic gates. Meanwhile, the
latency of logic gates, area, and power consumption are optimized in this process.
Physical design is based on a gate-level netlist which is the end result of the logic
synthesis. At this step, circuit representations of the components (devices and
interconnects) in the design are converted into geometric representations of shapes.
This geometric representation is called IC layout.
Physical design is usually split into data import, floorplan, placement, clock tree
synthesis, and routing. In the step of data import, the netlist generated in the logic
synthesis, the script containing the timing constraints, and the libraries provided by
the foundry are imported into the EDA tool environment. The floorplan is a process
of placing input, output, macros, and core modules in the chip. The placement is a
process of placing standard cells automatically according to data import files. In the
step of clock tree synthesis, buffers and inverters are inserted along the clock path to
balance the skew and minimize the delay. Routing is a process of adding wires
automatically to properly connect the placed components while obeying all design
rules. The physical verification is a process whereby the layout of IC is verified via
EDA software tools to ensure correct electrical and logical functionality and man-
ufacturability. Verification involves design rule check (DRC), layout versus sche-
matic (LVS) and XOR (exclusive OR) check, antenna checks, and electrical rule
check (ERC). The tape out is the final design step for IC before they are sent for
manufacturing.

Analog IC Design Flow

Different from the digital ICs, the design flow of analog IC mainly includes stages
such as specification, circuit design, layout design, layout verification, and tape out,
as shown in Fig. 35.2.
In the step of circuit design, analog circuit is designed by transistors directly
according to the specification. Meanwhile, the function and performance of the
analog circuit is verified with EDA tools, such as SPICE simulator. The layout

Fig. 35.2 Analog IC design flow

35 Basics of Integrated Circuit Design 671

design is a process drawing the geometric representation of analog circuit according

to the design rules. The layout verification is a process before tape out, and it uses
EDA tools to verify the layout design of IC, which also involves DRC, LVS,
ERC, etc.
With the continuous improvement of integration, the cost and cycle of IC design
have dominated the cost and cycle of product, especially VLSI products. The EDA
tools have become the key of improvement in the IC design efficiency. The trends of
digital IC design include but not limit to system-level design, design for manufac-
turability (DFM), and design for yield (DFY). The EDA tools used in analog IC
show their trends in high level abstraction and new technology application, such as
deep learning.

Process Design Kit

Process design kit (PDK) is a set of process files which describes information related
to IC design and manufacturing process; it contains device information, process
information, physical rule information, and so on. PDK is the link between process
technology and design. PDK was first proposed by Cadence, and implemented in
analog circuit design platform Virtuoso based on SKILL language [5]. It usually
includes design symbol, device model (SPICE), parametric cell (PCell), technology
file, and physical verification rules document, as shown in Fig. 35.3.
Design symbol is the schematic symbol of the device; it covers the device’s port
information typically, such as the source electrode, drain electrode, and gate elec-
trode of metal oxide semiconductor; the main parameters that affect the performance
of the device, e.g., the channel length and width; and number of fingers for layout.
Device model (SPICE) refers to the method of describing the voltage-current
relationship of devices (MOSFET, triode, and passive components) based on math-
ematical equation, equivalent circuit, and process data fitting, which provides sim-
ulation model files for chip designers and is the basis of transistor level simulation
verification. To meet the needs of different simulation tools, process design packages
usually contain HSPICE model, Spectre model, and sometimes other model(s).
Meanwhile, in order to accurately predict the distribution of chip performance
parameters, the device models include process corner analysis model and Monte
Carlo analysis model.
Parameterized Cell (PCell) is the core of the process design package. It is
written with SKILL language (based on popular artificial Lisp language) and is a
parameterized layout file that meets the inspection of layout rules and circuit layout
consistency. PCell avoids repeated creation of unit layout and simplifies mainte-
nance of unit layout, making layout design convenient and fast. For example, when
designers call CMOS parametric unit, device layout of different sizes can be
obtained only by modifying property parameters.
Technology File refers to the process used in layout design and verification
documents; it includes the process feature sizes, types of devices, GDSII design
data layer and process mapping, attribute definition of design data layers, design
672 C. Huang et al.

Fig. 35.3 Main components of process design kit (PDK)

rules, electrical rules, display color definition, automatic layout rules, and graphical
format definition. Sometimes technology file is also called process file in the
application field.
Physical Verification Rules File includes layout design process rules check
(DRC) file, circuit layout versus schematics (LVS) file, layout parasitic parameter
extraction (XRC) file, etc.

Customer-Owned Tooling

As the fabless design houses were seeking foundry business support model, some
integrated device manufacturers (IDM), who originally owned fab facility, have
transferred the part of their owned technology and related electronic design automa-
tion (EDA) technology to the foundry and EDA companies. This behavior supports
the processing and manufacturing of some special products in these companies that
35 Basics of Integrated Circuit Design 673

occur in the process of the transition from IDM to the foundry; therefore, the
customer-owned tooling (COT) model has been established. As the widespread
acceptance of foundry model, some large companies supported by foundry (such
as IBM and Qualcomm, etc.) have developed and formed a specific process tech-
nology for their own products in the advanced nodes, such as 65 nm, 40 nm, 28 nm,
and 14 nm technology, to support more optimized product manufacturing in perfor-
mance, consumption, and area. Hitherto, the COT is usually referred to the special
process platform based on the custom process, circuit IP, design flow, and method-
ology, which is provided by the foundry for some special customers (generally large
or giant company). The counterpart to COT is the alleged foundry-owned tooling
(FOT), namely, a standard or common platform providing for customer is developed
by foundry’s standard process and technique. The FOT emphasizes universality and
standardization and providing customers with standard processes, IP (including the
IP developed by third parties), and design process and methodologies (PDK) based
on the mainstream EDA tools.
Custom process: The FOT platform adopts the general process supplied by
foundry; its process specification fulfills the design demands in area, performance,
and consumption for most customers, but cannot satisfy the special process demands
of some special customers such as high-performance server CPU, high-end
smartphone SoC chip and high performance FPGA, etc., in high performance, low
consumption, or specific IC aspects in comparing with COT platform. In this
condition, some customers (generally large or giant company) often request for
COT (custom process), such as add transistors with more lower threshold to increase
speed performance, customize extremely high density SRAM bit cell to reduce the
area and cost of SRAM-dominated chip, and customize eDRAM bit cell to decrease
the consumption and area of memory.
Custom circuit IP: The IC design method supported by FOT platform generally
adopts the foundry provided circuit IP to design chips product, such as standard
cells, I/O cells, and SRAM. However, some IC enterprises often present the COT
requirements of adopting custom circuit IP considering different factors. For exam-
ple, the FPGA enterprise often customizes SRAM cell and LUT cell to satisfy the
FPGA product demand; some large companies often customize all the underlying
cells due to the convenience of product transplanting between different nodes; the
CPU company often customizes part of dynamic logic library to apply for high-
performance data path design. The entire COT platform generally adopts custom
circuit IP.
Custom design process, EDA tool, and design methodology: Under the FOT
platform support, the research and development of IC design method and process are
based on mainstream EDA tool which satisfies the demand for most customers’ IC
product design. However, the design method and process supported by COT plat-
form of some large companies are often developed based on the in-house EDA tool
to enhance the design efficiency and success rate. The current tendency is to use
mainstream commercial EDA tool in COT designing. The COT has some advan-
tages that can design products with more optimized performance, consumption and
area, but the disadvantages are that it has higher technology threshold and larger
674 C. Huang et al.

investment cost, so this technology is generally owned by large companies (such as

IBM and Qualcomm). The other characteristic of COT is that the process technology
owner can assign its process to different foundries for manufacturing, which can
acquire the competitive advantage in wafer manufacturing cost and spread risks.

Standard Cell Library

Standard cell library is the basis for modern large-scale digital IC design. It is a
collection of semi-customized circuit with a fixed-height and variable-width and
used as building blocks in IC design. Standard cell library includes combinatorial
logic cells, sequential logic cells, input/output (I/O) cells, and special cells. Combi-
national logic cells mainly comprise inverters, buffers, simple logic gate circuits,
and composite logic gate circuits. Sequential logic cells mainly comprise registers
and latches; memory cells fall into sequential cell type, they have different height
and width, and they do not belong to standards cells. I/O cells comprise input cells,
output cells, and input/output bidirectional cells. Special cells comprise delay cells,
layout filling cells, voltage clamping cells, etc.
In order to accommodate various designs and to optimize the performance, power
consumption, and area of the chip, the same type of cells in the cell library includes
different types of variants: (1) drive strength refers to the ability of the cell to drive a
larger cell or multiple cells (Fanout >1). Cells with different drive strength can be
selected according to the load during logic synthesis or place and route. (2) Double-
height or triple-height cells refer to the height of cells. At the beginning of the design,
cell library of high speed and/or high density and/or ultra-high density can be
selected according to the chip’s demand. (3) Transistor threshold refers to the
threshold voltage of transistors in the cell. Cells with high, normal, and/or low
threshold can be selected to balance the path delay and leakage current during the
place and route process or logic synthesis.
Standard cell library view refers to the cell model used by different EDA tools in
the design flow, including transistor netlist, symbol library, Verilog model, layout
model, timing (and) power library, and topology (FRAM) view. For example,
Fig. 35.4 is the cell library view of the inverter, wherein transistor netlist describes
connections between the cell transistors, the diodes, and the parasitic resistances and
capacitances for transistor-level simulation and physical verification. Symbol
library model describes the symbol pattern of cells for schematic diagram input.
Verilog model describes the function and input/output of the cells. Layout model
describes the layout level and the shape of standard cells for merging the whole
chip’s layout. Timing power library describes standard cell’s delay data, driving
strength, operating conditions, area, timing, and power for synthesis, and place and
route. Topology view describes the information required for cell’s physical design,
including PINs location and orientation. Standard cell library seamlessly interfaces
with EDA tools to effectively support the automated process of chip design.
35 Basics of Integrated Circuit Design 675

Fig. 35.4 Cell library view of the inverter

Circuit Schematics

The circuit schematic, also known as the schematic diagram, is a diagram of

components and their connections drawn using standardized symbols. It represents
the structure of various parts of the IC, component parameters, and so on. Early ICs
were all designed with circuit schematics. With the rapid expansion of the scale of
digital IC, most digital circuits have adopted more abstract and efficient hardware
description language design, while most analog circuits still maintain the traditional
schematic design style.
As the design scale of IC expands, the circuit schematic generally adopts hierar-
chical design, and several sub-schematic diagrams are included layer by layer. The
hierarchical design can simplify the schematic complexity and improve the read-
ability and maintainability of the schematic. According to the description level, it can
be generally divided into system layer, module layer, unit layer, and so on.
The circuit schematic is mainly composed of four parts: component symbol,
node, connection, and annotation. Symbol: Indicates components in the circuit,
e.g., resistors, capacitors, inductors, diodes, and transistors. The component symbol
remains the same number of pins as the actual component has one-to-one corre-
spondence. Schematic input software allows designers to use specialized or custom
component symbols, as well as generate schematic derived symbol for high-level
schematic to call. Node: Refers to the connection relationship between component
pins or wires. Each node in the circuit schematic has a unique network tag, also
676 C. Huang et al.

known as a network node. All component pins and wires connected to the same node
or labeled with the same node name are all connected to each other. Wire: Indicates
the electrical connection in the actual circuit. It can represent a single wire or a bus.
On the layout of the actual IC design, it refers to the interconnection of multiple
metal wires. In addition, the nodes or connections of the same network label indicate
that they are electrically connected even if there is no actual connection in the circuit
schematic. Annotation: Refers to all the text in the circuit diagram, often used to
mark the component name, parameters, schematic drawing information, design
instructions, and other information. Figure 35.5 is a typical IC schematic, in which
Fig. 35.5a is the top-level circuit schematic diagram, Fig. 35.5b is one of the
sub-circuit diagrams of Fig. 35.5a, and its layered nesting constitutes a hierarchical

Fig. 35.5 Hierarchical design schematic and main components. (a) Top circuit schematic,
(b) sub-circuit of “ENABLE” in (a)
35 Basics of Integrated Circuit Design 677

schematic design. In Fig. 35.5b, main parts such as component symbols, nodes,
wiring, and annotations constituting the circuit schematic are attached.

Input/Output Cells

The input/output (I/O) cells are the units which receive off-chip input, or send output
signal to drive the off-chip load in the IC. The connection of the I/O units and the
pins in the integrated circuit is shown in Fig. 35.6.
In logic view, a I/O has a connection “point” thus is called a “I/O pin”; typically
by adding a pair of drivers (p-driver to connect to Vdd, and n-driver to Vss) to a pad,
an I/O is now called “I/O cell” or “I/O pad.”
The I/O cells can be divided into analog I/O cells, digital I/O cells, and power
supply cells; according to the signal types, can be divided into input I/O cells, output
cells, and bidirectional cells. A standard bidirectional I/O cell generally includes an
input buffer, an output buffer, and an ESD protection circuit, whose design quality
affects the reliability of the integrated circuit.
Input buffer. The main function of the input buffer is to convert the input
electrical level. The types of the input buffer include the transmission gate, the
inverter, the non-inverting input buffer circuit, and the normal phase input buffer
circuit with feedback transistor. The transmission gate input circuit is controlled by
the enable signal and supplemented by a protection network. The inverter input
circuit consists of a CMOS inverter and a protection network for input inverting and
level shifting. The non-inverting input buffer circuit is composed of protection
network, level shifting circuit, and normal phase input driver. The normal phase
input buffer circuit with feedback transistor is mainly composed of two cascaded
inverters.
Output buffer. The main function of the output buffer is to improve the drive
capability of output signal, especially for large load, where the output driver should
provide a sufficiently large drive current to minimize the total delay of the buffer.
The design technique of the output buffer circuit includes the inverter chain and the

Fig. 35.6 Connection of

input/output units with pads in
integrated circuits
678 C. Huang et al.

Fig. 35.7 ESD protection circuit

MOS transistor with large ratio of width and length. In CMOS ICs, the inverter chain
composed of multi-stage inverters is commonly used as the output buffer circuit,
whose delay could be minimized by optimizing the number of the stages in inverter
chain and the inverter size. In addition, the transistor with comb-like (interdigitated)
structure and large ratio of width and length is advantageous for further reducing the
delay.
ESD (electrostatic discharge) protection circuit. The functions of ESD protec-
tion circuit can be divided into input protection, power protection, and full chip
protection, which prevent the instantaneous high pulse current generated by static
induction from damaging the chip, as shown in Fig. 35.7. The ESD protection circuit
at an output pad is generally made up of inverters with large-sized transistors. The
ESD protection circuit at input pad includes a dual diode protection circuit and a
vertical bipolar transistor protection circuit, which has the advantages of small area,
high driving current, and low clamping voltage. The power ESD protection circuit
can be implemented with a gate-grounded NMOS transistor or by a circuit that
detects ESD variations. The full-chip ESD protection circuit generally places a
power-to-ground ESD clamp protection circuit on each side of the chip.

IC Clock

The IC clock is a time reference of the digital circuit and its unit is in Hertz. It is a
periodic signal sampled and updated by the sequential logic circuit in the synchro-
nous circuit. The clock signal can be generated by a crystal oscillator, an RC
oscillator, or a phase-locked loop (PLL) circuit and transmitted to all timing units,
i.e., sequential gates (including registers, latches, etc.) through a clock distribution
network. The clock distribution network, also known as the clock tree, refers to the
35 Basics of Integrated Circuit Design 679

circuit that transmits clock signals from the source to all nodes or so-called clock tree
leafs.
The key metrics are clock jitter, clock skew, clock latency, and clock tree power.
Modern ICs are large in scale, and the clock tree power consumption of all timing
units is also increasing. In some high-performance processors, the clock tree power
consumption exceeds 30% of the total power consumption of the chip. The main
types of clock trees are (1) H tree, clock buffer layout similar to H type; (2) Fishbone
structure, clock buffer layout similar to fishbone shape; (3) Mesh structure, the clock
is driven by a clock driving unit around the circuit and is wired in a grid-like top
layer. In addition, there is a hybrid structure in which a plurality of structures is
combined.
The main indicators that characterize the clock are clock period, rise time, fall
time, duty cycle, clock latency, clock jitter, and clock skew. Clock Period, also
known as the oscillation period, is the reciprocal of the clock frequency. Due to the
setup time constraints of the timing logic, there is a minimum clock period con-
straint, which is the highest operating frequency at which the circuit can operate.
Rise Time and Fall Time refers to the conversion time of the clock edge. The rise
time is generally defined as the time required for the clock signal level to vary from
10% to 90% (or derated to 20%–80% or to 30%–70%). The fall time is similar. Duty
Cycle is the ratio of the high level of the clock to the clock period. Different types of
timing circuits have different clock duty requirements. Register-based designs have
no explicit requirements on clock duty cycle, and latch-based designs require higher
clock duty cycles. Clock Jitter is a random variation of the clock edge on a node.
There are two types of clock jitter: deterministic jitter and random jitter. Determin-
istic jitter can be divided into periodic jitter, data-dependent jitter, and duty cycle
jitter. Random jitter is unpredictable and irregular jitter caused by device noise,
power supply time-varying noise. Clock Latency is the average delay from the
clock source to the timing logic (registers, latches, etc.). The clock delay is affected
by the clock tree topology and the clock tree driver. Clock Skew is the clock edge
difference d ¼ ti–tj between any two timing logics i and j due to differences in the
transmission path, process variation, environmental effects, and signal load during
clock signal transmission (see Fig. 35.8). The clock skew can be divided into
positive deviation and negative deviation. When the clock routing direction is the
same as the data pipeline direction, the positive deviation is d > 0. Otherwise, the
deviation is negative.

Leakage Current

With the advancement of IC technology, the threshold voltage (Vt) of CMOS devices
is continuously decreasing, and the leakage current through transistor channel is
increasingly serious. Static power consumption is an important factor limiting
products standby time. The leakage current of a MOS device can be divided into
four parts: junction leakage (I1), subthreshold (Sub-Vt) leakage (I2), gate-induced
drain leakage (GIDL, I3), and gate oxide leakage (I4I4), as shown in Fig. 35.9.
680 C. Huang et al.

Fig. 35.8 Clock source, clock distribution network, and main clock signal parameters

Fig. 35.9 Main leakage current composition of MOSFET

Junction Leakage I1 refers to a small leakage current occurred in a p-n junction

at reverse bias, e.g., the junctions of source and drain and the substrate. The reverse
biased p-n junction leakage current includes the current generated by the bulk
diffusion and thermally generated carriers in the space charge region. The junction
leakage current is related to the bandgap of the semiconductor material, operating
temperature, and the area of the source and drain regions.
Subthreshold (Sub-Vt) Leakage I2 refers to the weak source-drain channel
current when the MOS device is in the off region (Vgs < Vth). At this time, the
MOS device is in a sub-Vt region or a weak inversion region. The sub-Vt leakage
current can be expressed as:
V gs V ds
I sub ¼ I s enkT =q 1  enkT =q ð1 þ λV ds Þ
35 Basics of Integrated Circuit Design 681

Where Is is the leakage current when Vgs ¼ 0, which is related to the carrier
mobility and the effective width of the transistor; n is the empirical parameter, which
is about 1.5. After the ideal MOS transistor enters the cut-off region, the channel
current should drop rapidly. For this purpose, a sub-Vt slope (or referred to as sub-Vt
swing) is defined as S ¼ n(kT/q)*ln(10). The physical meaning is that in order to
reduce sub-Vt leakage current by a factor of 10, the Vgs needs to be reduced by one S
value. The smaller the S, the closer the MOS transistor is to the ideal switch.
Gate-Induced Drain Leakage (GIDL) I3 refers to a current generated by band-
to-band tunneling (BTBT) effect of high-concentration carriers at reverse biased p-n
junction under the gate-drain overlap region as induced by the gate electrical field.
The tunneling current generated by GIDL is exacerbated by the increase in traps at
the Si/SiO2 interface under the gate-drain overlap region by plasma processing,
implant, etc.
Gate Oxide Leakage I4 refers to the current that leaks into the substrate through
the tunneling effect of the gate oxide layer. As the feature size of MOS devices
becomes smaller, the gate oxide layer becomes thinner and thinner (the equivalent
SiO2 thickness below 28 nm node is only 1.2 nm), and some electrons have an
opportunity to enter the substrate through the oxide layer due to direct tunneling
effects. Materials with high-k dielectric constants, such as hafnium (Hf) metal oxides
and zirconium (Zr) metal oxides (Hf-dioxide, Zr-dioxide), help to greatly reduce gate
oxide tunneling leakage current (by the physically thicker gate dielect at same
equivalent SiO2 thickness), so that the gate oxide leakage current can be ignored
in advanced CMOS node with high-k processes.
For the CMOS process, the sub-Vt leakage current is the major part of the
quiescent current. As the semiconductor device enters the nanometer era, the
sub-Vt leakage current deeply affects the IC design. The designer uses multiple
power domains, power gating, and multi-threshold CMOS (MTCMOS) to achieve
low-power designs.

Power Consumption

The power consumption of an IC usually refers to the energy consumed by the circuit
per unit time, that is, the power required for operating the circuit. The power
consumption of the IC at standby state is called standby power consumption,
which is especially important in systems at sleep mode for a long time, e.g., the
wearable devices. The maximum power consumption with all active circuits in
operation in a short time is called peak power consumption, which affects the system
encapsulation and heat dissipation. The average energy consumption of multiple
operating states over a long period of time is called average power consumption,
which determines the battery life for powering devices. As the pitch size of the IC
process is reduced to the nanometer level, the power consumption of the ICs has
become a key parameter as its operation speed and area size, which directly affects
the reliability of the ICs, the chip package and heat dissipation cost, the battery life
682 C. Huang et al.

time of portable system, etc. Thus, low-power technology has become one of the
driving forces of the development of IC technology.
At present, the CMOS process is the dominant process for VLSI, and its power
consumption is mainly composed of dynamic power and static power.
Dynamic Power refers to the power consumption as required by the logic
operation for switching the node states. This power consumption consists of two
parts. One part is used for charging and discharging the load capacitance (including
the interconnect capacitance and the transistor parasitic capacitance). It is also
known as AC switching power consumption and can be expressed as:

P¼ f clk Ci V 2DD ai
i

where VDD is the supply voltage, Ci is the node equivalent capacitance, αi is the node
switching activity factor, and fclk is the clock frequency. The second part is the short
circuit power consumption, which is caused by the momentary short-circuit current
through the p-type and n-type MOS during the gate bias transition. The short-circuit
power consumption is related to the output load and the flip speed of the circuit node.
The power loss of static CMOS circuits is dominated by the dynamic power
consumption.
Static Power refers to the power consumed by the IC at standby mode. For the
CMOS digital circuits, it is mainly caused by the leakage currents of the MOSFET,
including sub-Vt leakage current, gate induced drain leakage (GIDL) current, gate
oxide leakage current, and junction leakage current, in which the sub-Vt leakage
current is the main portion. For the analog ICs, the static power is generally resulted
from the operation bias current.
Low-power design technology is now one of the mainstream technologies for
large-scale digital IC design. The widely used technologies include Clock Gating,
Power Gating, and Multi-threshold CMOS (MTCMOS) and sub-Vt or Near-
Threshold Circuit (NTC) design techniques.

Design Simulation

Design simulation is for predicting circuit behavior by EDA simulators before

fabrication. By mathematically modeling the circuit electrical characteristics, stim-
ulus is applied to observe the circuit’s response. The results are used to guide
designing and optimization. Circuit simulation can be classified into transistor
level simulation, gate level simulation, and register transfer level (RTL) simulation
according to the objects. Based on identical simulator kernel, pre-simulation and
post-simulation are used to simulate the schematic level and physical level,
respectively.
Transistor level simulation is based on establishing the netlist of circuit com-
ponents at transistor level which includes transistors, capacitors, resistors, and
inductors. The netlist is transformed into nodal equations and loop equations. The
35 Basics of Integrated Circuit Design 683

current and voltage of each node are solved after algorithmic convergence. For
facilitating circuit analysis, DC analysis, transient analysis, and small-signal analysis
are generally provided to obtain the gain, noise, frequency characteristics, delay, and
other circuit parameters.
Gate-level simulation is based on establishing the netlist of circuit components at
gate level which includes logic gates, flip-flops, and other components. The inter-
actions in the netlist can be transformed into Boolean equation, Truth Table, or
Karnaugh map. The nodal logic values are obtained by deducing the transmission of
the excitation signals along the circuit paths. In order to facilitate circuit analysis, the
simulator also provides system tasks, system functions, and other means to assist
simulation. Gate-level simulation is essentially event-driven. Each simulation cycle
processes one triggered event. Recalculation cycles terminates till steady state
appears. The event triggered simulation provides both design assistance and timing
checking. At the same circuit scale, the complexity of simulation is significantly
lower than that of transistor-level simulation.
Register Transfer Level (RTL) simulation is based on establishing the netlist of
circuit components at behavioral model level, which includes circuit registers,
arithmetic units, and other large-scale functional modules. These descriptions are
transformed into behavioral level models such as signal flow graph, truth table, finite
state machine, state graph, and state table. It is similar to gate-level analog deduction
of excitation signals to obtain the logic values of internal variables, so as to obtain
circuit behavior. Compared with gate-level simulation, RTL simulation is also based
on event-driven simulation method, but the abstraction level is higher and the
simulation efficiency is further improved (see Table 35.1).

Table 35.1 Comparison of design simulations

Simulation
level Objects Modeling Application
Transistor level Transistors Circuit Designing and optimization of analog
capacitors nodal circuits and digital standard cells
Resistors equations
Inductors Loop
equations
Gate-level Logic gates Boolean Function and system-level behavioral
Flip-flops equation verification of digital circuits
Logical Truth Table
components Karnaugh
map
Register Circuit registers Signal flow System behavior level design and
transfer level Arithmetic units diagram verification
(RTL) Large-scale Sequence
functional diagram
modules Truth table
Finite state
machine
State
diagram
684 C. Huang et al.

In the early days of IC development, circuit simulation mainly relies on manual

calculation, theoretical analysis, and experimental boards. In 1972, the University of
California, Berkeley, introduced the SPICE (Simulation Program with Integrated
Circuit Emphasis) simulation tool, which is the beginning of practical transistor-
level computer simulation replacing manual work. In the 1980s, the growth of
integration scale and the improvement of computer performance led to the emer-
gence of gate-level and RTL-level simulation tools. In recent years, with the
increasing complexity of mixed digital/analog circuits, some more efficient multi-
threaded parallel simulation accelerators such as APS (Advanced Parallel Simulator)
have become mature into practice, which significantly improves the design
efficiency.

Functional Verification

Functional verification is the task of verifying that design circuit conforms to

specification. Functional verification is a complex task which participates in many
stages of IC design flow. According to the approach of the verification, functional
verification can be separated as simulation verification, FPGA verification, and
formal verification.

1. Simulation verification is the act of proving the correctness of design circuit by

measuring the response after user-defined stimulus in EDA environment.
The simulation verification, which is performed at RTL, is called
pre-simulation. The simulation verification can also be performed after logic
synthesis, but the simulation result does not contain the information about the
delay interconnect. The post-simulation is performed after physical design, and it
can be used to verify the performance of design circuit more accurately.
2. FPGA verification is the act of proving the correctness of design circuit with
FPGA devices and FPGA supported tools, such as logic synthesis, floorplan, and
routing. Compared to the simulation verification, FPGA verification has the
advantage of fast verification speed, co-verification of hardware and software,
and other scenarios for long-term verification. But FPGA verification has the
challenge of observability for debugging.
3. Formal verification is the act of proving or disproving the correctness of
intended algorithms underlying a system with respect to a certain formal speci-
fication or property, using formal methods of mathematics. One approach of
formal verification is model checking, or property checking, which consists of a
systematically exhaustive exploration of the mathematical model. Another
approach of formal verification is equivalence check, which is commonly used
to formally prove that two representations of a circuit design exhibit exactly the
same behavior. The coverage of formal verification can achieve 100%, but it
cannot verify the performance of circuits.
35 Basics of Integrated Circuit Design 685

Fig. 35.10 Digital integrated circuit verification process

The verification of IC exists at many stages of design flow, as shown in

Fig. 35.10. In RTL design, the pre-simulation is used to verify consistency between
the design and requirement. In order to improve the efficiency of simulation, the
stimulus is usually described in behavior level. The test cases in simulation are used
as many as possible to search the defect of RTL design. FPGA is usually used in
verification of VLSI circuit design for regression and stress test. In synthesis and
physical design, simulation verification is used again to verify consistency between
the design and requirement. Meanwhile, formal verification is used to prove the
logical equivalence between netlists. After physical design, the post-simulation is
used to verify the correctness of circuit design by adding the delay of interconnect
with parasitic parameters into the netlist.

Placement and Routing

The placement and routing (or place and route) of digital circuits is automatically
done by software. For analog IC design, the requirements of placement and routing
are different from the digital IC design. The integration of analog circuits is small. As
a result of the analog signal, it is necessary to deeply consider the parasitic effects of
transistors, avoid the parasitic and coupling effects between placement and routing,
meanwhile, weight a series of parameters, such as the size of transistors. So the area
of the analog circuit is usually large, the placement and routing need to be done
686 C. Huang et al.

manually. The following is mainly to explain the automatic placement and routing of
digital circuits.
Placement, also known as cell placement, is the physical design of arranging the
location of each standard cell on the chip in a logical netlist and meeting the design
rules. The placement is usually judged by the method of routing congestion, static
timing, noise, and power analysis. The main indicators of the placement include
routing congestion degree; timing constraints (set-up time constraints and hold time
constraints); and maximum voltage drop in the chip. The main methods of placement
are usually divided into global placement and detailed placement. The global
placement uses the analytic algorithm and the image segmentation method, com-
bined with the geometric method of fast calculation. The detailed placement uses
optimization methods such as simulated annealing algorithm. The placement strat-
egy mainly includes the flat placement and the hierarchical placement. The former
place all units at one time; the later uses a bottom-up or top-down approach to
hierarchical placement.
Routing is the process of making interconnect configurations among components,
usually after the placement is completed. The principle of routing is to ensure the
correct connection among different components, meanwhile complying with certain
design rules. Routing should focus on eliminating routing congestion, optimizing
timing, reducing coupling effects, eliminating crosstalk, reducing power consump-
tion, ensuring signal integrity, preventing problems in manufacturing, i.e., design for
manufacturing (DFM), and improving yield (Yield Enhancement).
Routing process includes three steps: global routing and detailed routing. (1)
Global routing: it starts with a global plan for subsequent detailed routing. First, set
the goal of global routing, and then make specific plans according to the character-
istics of the design. For example, the design that needs routing can be a chip or a
large custom module. The shape of the chip can be square or rectangular. Global
routing should minimize the total length of the connection, distribute the routing
evenly, minimize critical path delays, complying timing rules, avoid crosstalk, and
keep the bus aggregated. (2) Detailed routing: the routing is among multiple layers of
metal that to meet the timing requirement and can automatically search for routing
errors and correct errors, or correct routing. Detailed routing must consider all the
rules involved (such as density requirements, avoiding crosstalk and parasitic
effects, etc.), automatically switch and comprehensively use multiple layers of
metal as routing. (3) Routing correction: there are three methods, i.e., automatic
correction, progressive correction, and local correction. In general, combined with
the actual situation, three correction methods are comprehensively utilized.

Physical Verification

Physical verification is used to check whether the designed layout meets the process
manufacturing specifications, electrical specifications, and consistence with circuit
schematics, including design rule checking (DRC), electrical rule checking (ERC),
35 Basics of Integrated Circuit Design 687

Fig. 35.11 Physical verification examples. (a) DRC verification, (b) ERC and LVS verification

and layout schematic consistency checking (LVS). A verification example is illus-

trated in Fig. 35.11.

1. DRC rules check whether the layout meets the design rules for manufacturing.
DRC rules specify the geometric size and spacing of different graphics in the
layout, so as to meet the requirements of mask accuracy and avoid manufacturing
risk. Examination items include minimum spacing between graphs, minimum
size requirements of graphs, size and spacing of through holes, minimum density
of poly-Si and metal, etc. DRC also includes Antenna Check (ANT) to avoid the
aggregation effect of free charges on gate oxide layer, which has a risk of the gate
oxygen lay breakdown during metal etching.
2. ERC rules check whether the layout meets the electrical rules. ERC tool searches
the layout for power supply, ground, and the connection between input/output
ports and internal circuits, finds out the following abnormal situations: shorted
power supply and ground, shorted output ports, suspended input/output ports,
suspended transistor ports, etc. Designers can locate and eliminate the electrical
risks according to the coordinates indicated by the ERC tools.
3. LVS checks the consistency between layout and schematic. The LVS tool
extracts the transistor level netlist of the layout and compares it with the sche-
matic netlist. The comparison process starts from the input/output ports. A
heuristic algorithm searches the connections of each component from transistor
level to the top level, seeking the minimum backtracking path associated with the
circuit. If a local matching is detected, the matched devices and nodes are marked
and identified. If not, the current searching path is terminated and restarts
searching process with another path. Finally, matching results are presented in
lists and graphics, and inconsistent locations and devices are reported.

In summary, as the scale of IC grows by Moore’s law, the number of layout

polygons of the whole chip is up to hundreds of millions. At the same time, the
number of design rules also increases rapidly with advanced nano-technology in
688 C. Huang et al.

developing. DRC rules of advanced technology are up to thousands at 2018, which

makes it imperative to improve the efficiency of physical verification. Among all the
algorithms, hierarchical physical verification is a promising method to meet both the
accuracy and efficiency.

Layout

A layout is a planar geometry representation of an IC which is the output of an IC

physical design, usually described in GDSII format or OASIS format. The layout
consists of multiple layout layers and follows certain design rules.
A layout layer refers to the layer that integrated circuit process module abstracts
and transforms into conceptualization. Typical layout layers include (1) substrate and
well layout layers, usually have p-type (for NMOS devices) and n-type (for PMOS
devices); (2) diffusion layout layers (n þ and p+), defining regions where transistors
are formed, also commonly referred to as the active region; (3) one or more
polysilicon layout layers, which are used to form the gate of the transistor (and
also used for interconnections); (4) multiple metal interconnect layers; (5) contact
holes and via layouts, used to provide layer-to-layer connections. A layout is a
combination of multiple polygons, each of which belongs to a certain layout layer.
Design rules are the rules that must be followed by layout layers specified by
semiconductor manufacturing plants. Design rules define the minimum size of a
graphic in a layout layer, the minimum spacing between graphics in the same layer,
and the minimum spacing between multiple layout layers. The design rules for
different processes are usually different. Only the layouts that comply with the
design rules can ensure that the actually produced IC have predetermined functions
and can be mass-produced. Typical design rules include active-to-active-area dis-
tance, well-to-well distance, transistor minimum channel length, minimum metal
width, metal-to-metal spacing, metal current density, ESD, and I/O design rules and
antenna efficiency rules.
Typical layout examples of NMOS and PMOS devices with a 40 nm linewidth
process are shown in Fig. 35.12; the main layout layers are listed, including poly-Si,
active region, via, etc. The main layout design rules are shown in Table 35.2.

Tape-out

Tape-out is the process of delivering layout data and project documents to fabrication
plants after layout design and verification. Early layout GDSII data is stored on tape,
so this data transfer process is named Tape-out. Project documents include basic
project information, manufacturing information, and layout information. Based on
layout data and project documents, mask graphics is made and wafer manufacturing
begins.
The storage formats of layout files are GDSII and OASIS. The basic data structure
of the layout file is module, each of which is composed of several geometric figures
35 Basics of Integrated Circuit Design 689

Fig. 35.12 Typical layout examples of NMOS and PMOS devices at 40 nm process node

Table 35.2 Main layout design rules

No. Description Design rules(nm)
1 Minimum width of transistor channel 40
2 Minimum width to N+/P+ active 80
3 Minimum width between via and metal edge 25
4 Minimum spacing between vias 80
5 Minimum spacing between metals 70
6 Minimum spacing between active 80

named graphic elements. Graphic element is composed of 16 bits data blocks, which
define layer information such as data type, coordinates, line type, width, angle,
polygon type, scaling ratio, coordinates, row and column number, etc.
The project information mainly includes application, process information, layout
data information, IP usage statement, and related information of process design
package (PDK).
Manufacturing information describes process specifications, including supply
voltage, transistor types, number and thickness of metal layers, usage of special
devices, and mode and quantity of chip delivery.
Layout information describes the information of all layers in the layout file,
mainly including layer design number and layer mask number. The fabrication
plant generates the mask graphics after a certain mapping algorithm.
After the layout data and the above documents transferred, the mask factory maps
the layout data to mask graphics by several means: (a) direct mapping, i.e., the layout
layer and the photolithographic layer are identical, such as the metal layer; (b) logical
operation, through certain logical operation, multiple layout layers are used to
generate the required photolithographic layout. For example, n-diffusion region
and p-diffusion region are complementary in the layout data. Therefore,
n-diffusion lithography layers can be obtained logically from p-diffusion layers.
690 C. Huang et al.

(c) Graphic scaling, i.e., the injection layer mask of transistor gate is amplified from
poly-Si layer. Mask data includes not only circuit graphics but also some auxiliary
graphics needed in chip manufacturing, such as version identification, photolithog-
raphy alignment markers, exposure information markers, slicing graphics, and
optical alignment marking graphics.

Electrostatic Discharge Protection Design

Electrostatic discharge (ESD) is a physical transfer process of electric charge

between different potentials. When the ESD current flows through the core of
integrated circuit (IC), it may cause irreversible physical damage to IC. The ESD
protection circuit can effectively prevent the damage to IC under ESD current. The
current curves vs. time in ESD models are shown in Fig. 35.13.
The ESD models mainly include human body model (HBM), machine model
(MM), and charged device model (CDM) [6]. (1) HBM is a transfer process of
electric charge between the human body with static electricity and chips. The feature
of model includes long duration of time which may cause physical damage to IC due
to overheating. (2) MM event is a transfer process of electric charge in which the
metal with static electricity is in contact with the pin of IC. The static charge in the
metal discharges through the pins of IC, and the peak of the transient current can
reach ampere level, leading to failure of IC due to overheating. (3) CDM event is a
transfer process of electric charge between IC with static electricity and
low-resistance objects. The rise time and duration of CDM event are short, which
often causes the overvoltage on IC pins and breakdown of gate oxide.
ESD stress is a transient event of high current in a short period of time; the
relevant ESD protection circuit can be triggered under the high current event.
Further, ESD protection circuits should have the following features: (1) The ESD
protection circuit should have fast triggering speed under ESD stress to ensure the

Fig. 35.13 Transient

currents of different ESD
models
35 Basics of Integrated Circuit Design 691

safety of gate oxide inside IC under high transient overshoots. (2) The robustness of
ESD protection circuit must be high enough to ensure that the protection circuit itself
is not physically damaged under high energy ESD stress. (3) The clamping voltage
of the ESD protection circuit should be low enough to ensure that the IC core is not
physically damaged under ESD stress. (4) The ESD protection circuit should not
influence the normal operation of the chip. In addition, the leakage of the ESD
protection circuit should be low enough to have latch-up immunity and the protec-
tion circuit should not be triggered by the normal operation signal of IC.
The design of the ESD protection circuit is different from that of the conventional
IC design involving multiple stages from design to manufacturing. The optimization
of the ESD protection circuit should start from three aspects of process, device, and
circuit. The complexity is mainly due to the high current and voltage behaviors of
semiconductor devices under ESD stress, which cannot be predicted by conventional
IC simulation tools and models. Therefore, ESD design of protection circuit usually
requires designers have a deep understanding of ESD characteristics and skills to
establish the corresponding ESD models based on these understanding.
ESD testing of IC requires a set of equipment that is independent of conventional
IC functional testing. Transmission line pulse (TLP) is often used to verify the
performance of the ESD protection circuit. In addition, for HBM and CDM events,
the industry also has the mature test standards and corresponding equipment to
characterize the performance of ESD protection circuits.

References
1. M.J.S. Smith, Application-specific integrated circuit (Addison-Wesley Publishing Company,
Menlo Park, CA, USA, 1997)
2. D. Jansen et al., The electronic design automation handbook (Springer, 2003), pp. 398–420.
https://doi.org/10.1007/978-0-387-73543-6, ISBN 978–14–020-7502-5
3. C.-Z. Chen, X. Ai, G.X. Wang, Physical implementation of digital IC design (Science Press,
Beijing, 2008) (Chinese book series 2 of 5, ISBN 978-7-03-022031-8)
4. A. Kahng et al., VLSI physical design: from graph partitioning to timing closure (Springer,
2011), p. 10. https://doi.org/10.1007/978-90-481-9591-6, ISBN 978-90-481-9590-9
5. J. Ferguson, The process design kit: protecting design know-how. semiconductor engineering,
deep insights for the tech industry. Posted 08 Nov 2018. https://semiengineering.com/the-
process-design-kit-protecting-design-know-how/
6. D.Y. Hu, C.-Z. Chen, Reliability aspects of advanced IC technology with ESD and anti-radiation
capabilities. ECS Trans. 60(1), 1185–1190 (2014)
Digital Integrated Circuit Design
36
Jun Yang, Peng Cao, Weiwei Shan, Longning Qi, and Xinning Liu

Contents
Digital IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Hardware Description Language (HDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Circuit Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Floor Planning and Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
High-Level Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Hardware Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

Abstract
This chapter introduces the classification, design methods, and main features of
digital ICs. Circuit partitioning is a valuable method to reduce the complexity of
VLSI design, in which hardware description language (HDL) is used to model the
concurrent execution process of hardware circuits, including Verilog and VHDL.
High-level synthesis (HLS) transforms the behavioral-level description into cir-
cuit structure descriptions under certain constraints. Following the logic synthesis
that transforms the register transfer level (RTL) description into the gate-level
structure description, various methods are used to implement and verify a digital
IC design, such as formal verification, the mathematical method to analyze circuit
behavior to find circuit functional error, timing analysis to ensure the normal
operation of the circuit including setup and hold time constraints, floor planning
to place the main modules of the design to meet requirements for die size, as well
as timing closure and routing. In addition, design for testability (DFT) is used to

J. Yang (*) · P. Cao · W. Shan · L. Qi · X. Liu

National ASIC System Engineering Center, Southeast University, Nanjing, China
e-mail: dragon@seu.edu.cn

© Publishing House of Electronics Industry 2024 693

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_36
694 J. Yang et al.

detect chip manufacturing defects by inserting extra units without changing the
circuit function, and the hardware emulation uses dedicated hardware to perform
circuit functions for the circuit function verification, etc.

Keywords
Digital integrated circuits (ICs) · Circuit partitioning · Hardware description
language · High-level synthesis · Logic synthesis · Formal verification · Timing
analysis · Floor planning · Hardware emulation

Digital IC

Digital ICs are digital logic circuits based on Boolean algebra for processing digital
signals. In 1960s, Gordon Moore foresaw that the number of transistors integrated on
a single chip will grow exponentially over time, and this concept was later called
Moore’s Law. After 1970, digital ICs were mostly designed with CMOS devices.
The integration has been continuously improved through the scaling of process
technology. Its complexity has been doubled in about 1–2 years and has reached
more than 1 billion transistors per chip.
Logic gates used in digital ICs are divided into two categories: combinational
logic and sequential logic circuits, as shown in Fig. 36.1. The output of a combi-
natorial logic circuit is the function of its input at any time, and it is independent of
the previous working state of circuit. The typical combinational logic circuits include
inverter, NAND gate, NOR gate, multiplexer, etc. The sequential logic circuit means
that the output at any time depends not only on the input at that time but also on the
precious state of the circuit. Typical sequential logic circuits include latches, flip-
flops, etc.; however, the memory circuit belongs to the sequential logic.
Digital ICs can also be classified into two types: synchronous and asynchronous
circuits. Synchronous circuits mean that all sequential logic units are driven by a
single homologous clock. Any path satisfies the setup time and hold time constraints.
The highest working frequency is limited by the longest delay path, which is called
critical path. An asynchronous circuit is a type of circuit in which the sequential logic
circuit is clock-free or driven by a nonhomologous clock, and its circuit performance
(throughput) is limited by its circuit delay. Figure 36.2a shows a typical synchronous

Fig. 36.1 Combinational logic and sequential logic in digital circuits

36 Digital Integrated Circuit Design 695

Fig. 36.2 (a) Synchronous circuit and (b) self-timed asynchronous circuit

circuit. The logic functions F1, F2, and F3 are implemented in three steps, and its
highest frequency is limited by the maximum values of tpF1, tpF2, and tpF3. The
circuit can also be designed in an asynchronous way, as shown in Fig. 36.2b. Each
logic function is completed by handshake logic HS communication, startup, and
identification.
According to the logic implementation, CMOS digital circuits can be classified
into static and dynamic CMOS circuits. The static CMOS circuit is connected to the
power supply or ground through a low-resistance path, thereby achieving logic high
and logic low. Typical static circuits are: CMOS logic, proportional logic, and
transfer tube logic. Dynamic CMOS circuits maintain logic “1” or logic “0” by the
charge held on the parasitic capacitance. The static circuit has better stability but has
the disadvantages of large layout area and large latency. The dynamic circuit delay is
ideally only 50% of the static CMOS circuit, but it has the problem of poor anti-noise
ability and large power consumption.
The digital circuit design method can be divided into two categories: semi-custom
design based on standard cells and full-custom design based on transistors. Semi-
custom design is widely used in electronic design automation tool to improve design
efficiency. Full-custom circuit design is common in circuits such as processor cores
and high-speed serial bus interfaces that require high performance and power
consumption.
696 J. Yang et al.

The main indicators of digital IC include: design cost, performance, power

consumption, and stability. Design cost refers to the sum of chip design and
processing cost, packaging cost, and test cost; Performance refers to the throughput
of digital integrated circuits that can handle digital signals. It is often replaced by the
operating frequency when the architecture is determined. Power consumption refers
to the sum of dynamic power and static power consumed by digital ICs. Stability is
the ability of the circuit resisting to noise and to process fluctuations.

Hardware Description Language (HDL)

Hardware description language (HDL) is used to model the concurrent execution

process of hardware circuits, mainly including Verilog HDL (often shortened as
Verilog) and VHDL, which were developed in the mid-1980s and adopted as IEEE
standards. These two HDLs were used early for large-scale digital circuit verification
and later used for register transfer level (RTL) design and logic synthesis.
HDL can support multiple description levels of hardware circuits, including the
behavior level, the register transfer level (RTL), and the logic gate level. The
behavioral level is a description of the hardware mathematical model. The sequential
statement describes the circuit function but does not involve any timing information.
The RTL describes the description of the register structure in the circuit and the data
transfer between the registers. The RTL model can describe the timing information
of the hardware circuits on the clock cycle precision. The logic gate level model
describes the various logic gate units and the switch connection structures between
these logic gates. The logic gate level model can visually indicate the basic logical
network structure of the circuits.
HDL uses a structured, hierarchical modeling approach. For example, a new
module structure can be described by describing the instantiation of individual
devices and the connections between these devices. The device here can be either
a built-in gate in most HDLs, such as an AND/OR gate, a user-defined unit, or a unit
provided by a third party. The HDL supports a variety of variables, including wires,
registers, and parameters. The HDL supports continuous assignment and process
assignment. Continuous assignment is often used for combinatorial logic modeling.
Process assignments can be divided into blocking assignments and non-blocking
assignments. Blocking assignments block the execution of statements in subsequent
code, and non-blocking assignments do not block the execution of subsequent code.
Process assignment can model both combinational logic and sequential logic. HDL
supports a variety of delay models, including lumped RC delay models, distributed
RC delay models, and pin-to-pin path delay models.
The HDL uses an event-driven mechanism, that is, the simulation of the circuit is
organized by events in the PROCESS. PROCESS is an independently executed unit
in HDL. A digital circuit system described in HDL is composed of several PRO-
CESSes. When the value of any variable in a PROCESS is changed, a new update-
event is generated. As new update-events are triggered, PROCESSes that are
sensitive to them will be executed once. The execution of a PROCESS is an
36 Digital Integrated Circuit Design 697

Fig. 36.3 HDL simulation mechanism

evaluation-event. As shown in Fig. 36.3, during the simulation of the hardware

circuit, the system simulation time will be divided into many discrete time slices. In
each time slice, based on the update-event of the previous time slice, the evaluation-
event for all related processes in current time slice will be executed, and then this
operation will also generate new update-event. The evaluation-event and update-
event trigger each other to simulate the hardware circuits. In addition, PROCESS can
be activated and suspended. When an activated PROCESS is running, all other
PROCESSes will be suspended. Through the above event-driven and PROCESS
management mechanisms, HDL can simulate the concurrent operation of hardware
circuits.
HDL has greatly promoted the development of digital IC design automation
technology. In order to adapt to more design requirements, the HDL is also being
continuously updated. For example, HDL has extended the support for digital-
analog hybrid circuit modeling, verification extension, and system-level modeling.

Circuit Partitioning

Circuit partitioning partitions the circuits into two or more disjoint subsets according
to constraints so as to improve EDA software effect. The object of circuit
partitioning is generally a circuit composed of macro cells or standard cells to reduce
the complexity of the VLSI design and enhance the readability of the partitioned
circuits, leading to the area optimization and the line length optimization during
place and route. Circuit partitioning typically requires the area of each subset to be
approximately equal and needs to minimize the number of interconnects between
subsets. Since circuit partitioning belongs to the non-poly (NP, nondeterministic
polynomial time) problem, how to find the approximate optimal solution within a
698 J. Yang et al.

Fig. 36.4 Schematic diagram of circuit partitioning

relatively small time complexity is the goal of the design partitioning. The schematic
diagram of circuit partitioning is depicted in Fig. 36.4.
The constraints of circuit partitioning are usually the upper and lower bounds of
the total circuit area and the area of the subsets as well as the corresponding main
objective functions, including: (1) minimal cut, which means the minimization of the
total number of interconnections cut by the subsets; (2) minimal delay, which means
the minimization of the maximum delay of all paths from the input to the output of
the subsets; and (3) minimization of the maximum subdomain degree, that is, the
maximum number of interconnections cut by the subsets must be lower than a
certain upper limit bound. The above objective functions ensure that the circuit
does not cut the critical path with large delay, the number of interconnections
between the subsets is smallest, and the interconnection density is as even as
possible.
According to the basis of circuit partitioning, the algorithms of circuit partitioning
can be divided into constructive and iterative improving algorithms. The construc-
tive algorithm starts from an empty set and gradually increases the number of cells
to establish the partitions, which includes the clustering algorithm, the group migra-
tion algorithm, and the line network cutting model. The iterative improving
algorithm starts from a random initial subset and iterates the modification of the
partition result to comply with constraints, which includes the simulated annealing
algorithm, the spectral segmentation algorithm, and the genetic algorithm.
According to the principle of algorithm, the algorithms of circuit partitioning can
be divided into mobile, analytical geometry, combinatorial mathematical, and clus-
tering algorithms. The mobile algorithm usually adopts the method of exchanging
36 Digital Integrated Circuit Design 699

or moving partial cells to improve the solution and gradually obtains the optimal
solution of the algorithm, such as the group migration algorithm, the simulated
annealing algorithm and the hybrid genetic algorithm. The most representative
analytical method is the eigenvector method. The combinatorial mathematical
method considers the effect of the shape and length of the module on delay, which
leads to more accurate delay estimation, and is suitable for delay-driven partition,
such as the network flow method, the mathematical programming method, and the
set coverage method. The clustering algorithm includes the proportional cutting
algorithm, the random walking method, the multilevel hierarchical algorithm, and
so on.

Floor Planning and Placement

Floor planning is a graphical representation of an IC’s main modules in a pilot

layout, which is the premise of cell placement and route. During floor planning, the
shape or position of modules and the position of the external connection pins are
optimized by establishing a mathematical model under certain geometric constraints.
The geometric constraint of floor planning is caused by the special placement
requirements of some modules, as shown in Fig. 36.5. It mainly includes: (1) Wire
bonding, which is usually around the chip. The input and output devices should be as
close as possible to it. (2) High-speed macros, usually high-speed circuits (such as
high-speed cache, multipliers, barrel shifters, and arithmetic logic units), which
should be clustered together to avoid excessive data paths. (3) Hard IP, which usually
requires special layout locations, such as signal routing not allowed above the IP.
The main objectives of the floor planning optimization algorithm are: (1) deter-
mining the die size; (2) ensuring timing closure; and (3) meeting the routing

Fig. 36.5 The geometric constraint of floor planning

700 J. Yang et al.

requirements. Module shape optimization is unique to the floor planning phase and
can be viewed as a floor planning constraint problem with soft parameters. The
algorithm mainly includes: (1) Floorplan sizing algorithms, which can change the
aspect ratio of the module in polynomial time to find the minimum layout area.
(2) Cluster-growth algorithms, in which the blocks are iteratively added. The clusters
are merged horizontally, vertically, or diagonally. The next block position and
direction are placed to optimize the layout objective function. (3) Simulated
annealing algorithms, which seek continuous improvement of the objective function
solution starting from any initial solution. (4) Integrated floor planning algorithms,
which map floor planning problems into a set of equations, where the variables
represent the position of the block.
The research on floor planning notation has experienced great development since
the 1980s to the mid-to-late 1990s and up to now. There have been many represen-
tations or codes (such as fast sequence pair algorithms) that represent various
topological types and corresponding algorithm (such as Hamiltonian path graph
algorithm). With the improvement of IC performance, the constrained floor planning
(such as layered design, IP core reuse, and connection optimization) has become a
hot research topic in the physical design of very large scale IC.

High-Level Synthesis

High-level synthesis (HLS), also known as behavior-level synthesis (BLS), is a

method and process for transforming a circuit-level or behavior-level description
into a circuit structure description under certain constraints. High-level synthesis can
greatly optimize the circuit architecture and improve the design quality, whose
process is shown in Fig. 36.6 including compiling, transformation, scheduling,
allocation, controller synthesis, result generation, etc., where compiling and trans-
formation determine the compatibility and convenience while scheduling and dis-
tribution determine the performance and cost of the design.
Compiling and Transformation. The compiling and transformation process
converts the description of the behavioral characterization to an intermediate repre-
sentation format, where the description of the behavioral characterization is written
by the hardware description language (HDL) and the intermediate representation
format generally adopts the syntax analysis diagram. The syntax analysis diagram
typically contains the data stream and the control flow, including the abstract
operations and their properties (operation type, commutability of operands, etc.),
the control dependencies of operations (execution order), the data dependencies
(input data and output data for operations), and so on.
Scheduling and Allocation. This process features the transformation from the
behavioral description to structural description. The scheduling process assigns the
operations to the control steps with the goal of minimizing a given objective function
while satisfying the constraints, including the total required number of control steps,
latency, power consumption, and the amount of hardware resources. The allocation
process is to allocate the operations to the corresponding functional unit for
36 Digital Integrated Circuit Design 701

Fig. 36.6 High-level

synthesis

operation, to assign variables to registers, with the goal of minimizing the hardware
resources such as functional units, storage units, and data transmission paths.
Controller Synthesis. The controller synthesis process provides the required
driven signals to the data path through the controller, and the controller can be
implemented with hard-wired logic or firmware.
The development of the hierarchical synthesis technology experienced three
periods. In the first period (from early 1980s to early 1990s), the basic concepts of
HLS were proposed by academic institutions. In the second period (from early 1990s
to the beginning of the twenty-first century), EDA companies began to release the
tentative commercial tools, mostly applying behavioral HDL as the input language.
In the third period (from the beginning of the twenty-first century to present), many
EDA companies and academic institutions have promoted HLS technology moving
toward commercial applications. At present, HLS tools are still far from practical
applications with problems facing, e.g., effective search methods for design space,
division of large-scale circuits, problems related to IPs, and influence of placing on
delay.

Logic Synthesis

Logic synthesis is the process by which register-transfer level (RTL) circuit descrip-
tions are transformed into gate-level descriptions (i.e., logic gate-level netlist) to
meet design objectives and constraints. Generally, logic synthesis includes three
702 J. Yang et al.

Fig. 36.7 Procedure of logic synthesis

stages [1]: logic translation, logic optimization, and mapping, see Fig. 36.7.
According to the constraints and strategies set by the designer, the performance,
area, and power consumption of the circuit are optimized. The netlist of logic
synthesis output is the input to the physical synthesis. Logic translation is to
translate RTL descriptions of digital circuits into non-optimized netlists, i.e., logic
equations, based on standard cell libraries independent of the process. Logic opti-
mization is to reorganize and optimize netlist according to the constraints of design
objectives. The process needs to satisfy three kinds of synthesis constraints simul-
taneously, i.e., environment constraints, design rule constraints, and logic optimiza-
tion constraints. Environment constraints describe the external environment, such as
temperature, voltage, drive, and load where the circuit works. Design rule constraints
describe the maximum transition time, maximum fan-out, and minimum/maximum
capacitance allowed by the circuit. Logic optimization constraints include timing
constraints and area constraints. The former limits clock networks, timing paths,
critical path delays, and asynchronous logic timing, while the latter limits the
maximum number of logic units. Complex circuits can adopt top-down and
bottom-up logic optimization strategies. The former optimizes the top module
together with all its sub-modules and sets constraints for the top module. The latter
adopts the idea of divide and conquer, and sets constraints from the bottom; then the
sub-modules are integrated and optimized one by one, layer by layer up to the top
module. Mapping is to select logic unit instances from target process cell libraries to
implement a process-dependent logic netlist, based on the constraints of time
sequence and area of design objectives, and the logic relationship, unit
36 Digital Integrated Circuit Design 703

characteristics, and parameters of delay, power consumption, and area of logic units
provided by target cell library under corresponding processes.
The history of logic synthesis can be traced back to the manual use of Karnaugh
map to achieve circuit logic simplification, but not until the mid-to-late 1980s, the
theory and method of logic synthesis developed and matured. In the 1990s, a
comprehensive tool for commercial automation logic was formed [2]. With the
development of process nodes, the optimization effect of logic synthesis has become
the main factor affecting the feasibility of the physical design. The logic synthesis
needs to consider more physical effects when using advanced process node.

Timing Analysis

Timing analysis is the methodology that checks if circuits meet the timing closure
consisting of setup time constraints and hold time constraints. Timing analysis, as the
foundation that guarantees regular circuits, can be categorized into dynamic timing
analysis (DTA) [3] and static timing analysis (STA) from the perspective of analyt-
ical methodology [4].
Figure 36.8 shows the typical path of synchronous circuits. In the ideal condition,
the clocks of Register D1 and Register D2 have the same period and phase. Gener-
ally, synchronous circuits require the well-built input data for Register D2 before the
rising edge of the next clock. This is called the setup time constraint.

T > tc
q þ tlogic þ tsetup

Here, T is the synchronous clock period; tc–q is the maximum propagation delay
of Register D1; tlogic is the maximum delay that signals pass through combinational
circuits; tsetup is the setup time of Register D2 and decides the maximum of the
combinational logic delay, tlogic. Synchronous circuits also require the input data of
D2 to hold on for some time so as to write them into D2 correctly. This is called the
hold time constraint.

thold < tc
q,cd þ t log ic,cd

Fig. 36.8 Timing paths and timing parameters

704 J. Yang et al.

Here, thold is the hold time of D2; tc–q,cd is the minimum delay of D1 (also named
contamination delay); tlogic,cd is the minimum delay that signals pass through
combinational circuits and decides the minimum of the combinational logic delay,
tlogic.
In terms of stimulus, timing analysis includes dynamic timing analysis and static
timing analysis. Based on cell delay and interconnect delay back-annotated by
physical parasitic parameters, dynamic timing analysis synchronously checks logic
setup time and hold time stimulated by a set of verification vectors during the
dynamical function simulation. Static timing analysis, independent of verification
vectors, successively analyzes all the paths within circuits and verifies if the path
delay meets both setup time and hold time constraints, on the basis of cell and
interconnect delay models defined in standard cell libraries. Static timing analysis
takes advantages of fast speed and high coverage but may cause pessimistic analysis
due to its weakness at path authenticity judgments. Alternatively, dynamic timing
analysis takes the disadvantages of slow speed and low coverage but can achieve
high accuracy.
Timing closure is the process of iteratively executing timing analysis at different
design stages in order to gradually approximate timing constraints of the design.
Timing closure is mainly affected by factors of interconnect delay. At the stage of the
logic synthesis, interconnect workloads-based interconnect delay prediction leads to
the low accuracy. At the stage of the placement, Manhattan distances between cells-
based interconnect delay prediction generates the higher accuracy. At the stage of
routing, real routes-based interconnect delay prediction can result in the highest
accuracy. According to the interconnect delay at different stages, circuits can meet
the timing constraints by methods of modifying driven intensities of cells, adjusting
the places of cells, inserting/deleting buffers, and so on.
With the rapid development of semiconductor technology, process variations
(threshold voltage variations and channel length variations) and environment vari-
ations (voltage and temperature variations) during manufacturing have more and
more significant effects on circuits delay. Traditional static timing analysis based on
process corners has difficulties in characterizing the effects caused by process and
environment variations. Statistical static timing analysis (SSTA) based on random
variables characterizing circuits delay can analyze the timing constraints of synchro-
nous circuits more accurately than traditional static timing analysis.

Formal Verification

Formal verification refers to a static verification method of analyzing circuit behavior

by mathematical method and finding out the fault of circuit function. Formal
verification does not require stimulus and circuit simulation, and has greater com-
pleteness than simulations. Formal validation can be divided into two categories:
equivalence checking and attribute checking.
Equivalence checking verifies that the circuit is functionally consistent at dif-
ferent stages. For example, verification of RTL (register-transfer level) design and
36 Digital Integrated Circuit Design 705

Fig. 36.9 Logical equivalence between different netlists

gate-level netlist, synthesis netlist, and post-layout netlist. Equivalence checking

also can be used in the process of scanning chain rearrangement, clock tree synthesis,
etc. It has been integrated into the standard IC design flow. Equivalence checking
compares the functional consistency of the two models by traversing all possible
inputs. When contrasting, circuits are typically converted to regular expressions. The
two circuits in the following image have the same regular expression, see Fig. 36.9.
Although the circuit structures are different, their functions are equivalent.
Property checking, also known as model checking, checks whether the circuit
meets the property specification by mathematically searching. Property checking
generally takes the circuit model, coverage point, assertion, and circuit constraints as
inputs and checks all possible states of the circuit in the constrained environment for
the assertion. The failure of property checking indicates that a circuit function error
is found, and the tool outputs the counterexample. Property checking covers all
possibilities of logic and requires a large memory space, which limiting the size of
the circuit to be validated.

Design for Testability

The design-for-testability (DFT) is a circuit or method that is inserted in the chip

without changing the function of the original circuit, implementing detection and
testing of chip manufacturing defects and saving test cost. In the early stage of IC
development, functional testing was the mainstay. However, with the increasing of
circuit scale, functional testing is more and more difficult to cover the defects of the
chip. For this reason, DFT and structural testing for fault models become the
mainstream. The DFT focuses on improving the controllability and observability
of the circuit. Controllability is a measure of the difficulty of target faults or defects.
Observability is a measure of the difficulty or fault that can be observed by the test
equipment.
Fault model is the core of the DFT, which refers to the circuit defects and are
abstracted as logical errors affecting the test vector generation. There are “stuck-at-
706 J. Yang et al.

0” fault, “stuck-at-1” fault, coupling fault, bridging fault, and other fault models. The
main indicators for measuring the DFT are fault coverage and hardware overhead.
Fault coverage refers to the percentage of faults that have been tested. Generally, the
coverage must be at least 95%. The hardware overhead refers to the proportion of the
testability logic area inserted to the total area of the chip.
According to the type of the circuit, the DFT can be divided into digital logic
DFT, memory DFT, and mixed signal DFT.

1. Digital logic DFT mainly includes scan test, LBIST (logic built-in self-testing),
and boundary scan test (BST). Among them, the LBIST uses random vectors to
test the logic circuit, which has the advantages of short test time and low test cost.
The linear feedback shift register is generally used to generate the test vectors.
The boundary scan test adds the shift registers to the inputs and outputs of the
chip, to form a boundary scan chain. It is commonly used for chip interconnect
testing. IEEE1149.1-1990 is used to the boundary scan test. Scan test is the
structured test method. The register of the circuit to be tested is replaced with a
scan register, connected as a scan chain, and the test data is moved into/out of the
circuit through the scan chain. As shown in Fig. 36.10, the SE signal is set high
firstly, the scan chain is in shift mode, and the test vector is shifted to scan register
through the SI port; then the SE signal is set low, the scan chain is in the capture
mode, and the response of the combined circuit is captured by the scan register;
the SE signal is set high at last, the scan chain is shift mode, and the test result is
output of the chip through the SO port.

Fig. 36.10 The schematic and timing of scan test

36 Digital Integrated Circuit Design 707

2. Memory DFT mostly uses MBIST (memory built-in self-testing), which

includes test vector generator and test response comparator. The test vector
generator generates test data, address, and read/write control signals according
to the test algorithm. The test response comparator compares the test data of the
memory with the expected data. If the data is inconsistent, there is a fault in the
memory. The test algorithms include March C, checkerboard, and so on. In order
to cope with the increasingly serious memory yield problem, the memory self-
repair technology becomes more and more important.
3. Mixed-signal DFT is often combined with the functional test and performance
test, unlike with the structured DFT. Taking the PLL testing as an example, the
on-chip clock jitter test circuit can be integrated to replace the off-chip ATE
solution.

Hardware Emulation

A hardware emulator is an electronic system that maps a digital circuit into a gate
level netlist or a Boolean unit of operations and performs a circuit function with
special hardware to quickly complete functional verification. The scale of digital
circuit increases with Moore’s law, and the software simulator is difficult to complete
the massive verification work in a short period of time for the very large-scale chips.
The hardware simulator can significantly shorten the verification time, with cycle-
level accurate results, high simulation speed, and full debugging visibility. The
acceleration mechanism, key parameters, and application of emulators are explained
below.
Acceleration Mechanism of Emulator: Unlike a software simulator that relies
on general CPU to simulate the circuits, hardware emulators map circuits to logical
units of customized field programmable gate arrays (FPGA) or dedicated Boolean
processor arrays. The execution hardware of the hardware emulator has the basic
circuit structure such as logic operation unit and memory, and their functions are
consistent with the actual circuit, which can realize the logic function corresponding
to the circuit, and the execution speed is 1–4 orders of magnitude faster than the
software simulation speed. Both the customized programmable FPGAs and Boolean
processors provide a circuit-based debug interface with the same debug visibility as
the software simulator.
Main Parameters of Emulator: (1) Capacity, including the logical gate capacity,
the memory capacity, and the number of input and output ports. Capacity determines
the maximum mappable circuit size, and the circuit will be divided and mapped to
the software simulator and hardware emulator co-simulation when the circuit scale
exceeds the hardware emulator capacity. (2) Simulation speed, the number of clock
cycles per second. Simulation speed is independent of circuit size, determined by the
hardware structure of the hardware emulator. (3) Parallelism, the number of users or
the number of threads that perform simulations at the same time.
708 J. Yang et al.

Applications of Emulator: Hardware emulators are mainly used for the follow-
ing applications: (1) regression testing and stress testing, such as large-scale ran-
domness verification; (2) hardware and software co-verification, such as the co-work
of system on a chip and embedded operating system; and (3) other complex
verification, such as complex software protocol stack and video codec circuit.
For comparison of simulators and emulators, see Table 36.1.
In addition to expand capacity and increase simulation speed, hardware emulators
begin to support multiuser in computing center mode (see Fig. 36.11). The latest
hardware emulator can handle more than 2000 parallel jobs at the same time, with a
maximum capacity of 9.2 billion logic gates.

Table 36.1 Comparison of simulators and emulators

Computing Computing Simulation Representative
Simulation mode hardware unit speed (cycle/s) products
Software simulator X86 CPU CPU core <1 K Cadence
Incisive/NC-
Sim
Synopsys VCS
Mentor Questa
Hardware emulator based Customized Hardware 100 K–4 M Cadence
on Boolean processor processor Boolean Palladium
unit
Hardware emulator based Customized FPGA unit 500 K– M Mentor Veloce
on customized FPGAs FPGA

Fig. 36.11 Computing

center hardware emulator
(Cadence Palladium)
36 Digital Integrated Circuit Design 709

References
1. V. Taraate, Advanced HDL synthesis and SOC prototyping: RTL design using Verilog (Springer,
2019)
2. P. Kurup, T. Abbasi, Logic synthesis using synopsys, 2nd edn. (Springer, 2012)
3. C.-Z. Chen, X. Ai, G.X. Wang, Physical implementation of digital IC design (Science Press,
Beijing, 2008)., (Chinese book series 2 of 5, ISBN 978-7-03-022031-8)
4. A. Kahng et al., VLSI physical design: from graph partitioning to timing closure (Springer,
2011), p. 10. https://doi.org/10.1007/978-90-481-9591-6, ISBN 978-90-481-9590-9
Analog Integrated Circuit Design
37
Yuhua Cheng, Song Ma, Lele Jiang, Long Zhao, and Bao Li

Contents
Analog IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Operation Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Bandgap Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Analog-to-Digital Convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Characteristic Parameters of Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Analog-to-Digital Converter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Characteristic Parameters of Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Digital-to-Analog Converter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

Abstract
Analog IC is an integrated circuit consisting of passive components (e.g., resis-
tors, capacitors, inductors) and active devices (e.g., diodes and transistors) to
generate, amplify, filter, operate, convert, transmit, or process analog signals. The
main basic units of analog ICs include single-stage amplifiers, filters, feedback
circuits, current mirror circuits, etc. An advanced analog IC design topic can be
extended to analog-mixed signal (AMS) that is remained for further reading.
The basic unit circuits include bandgap reference circuits, operational ampli-
fiers, filters, analog-to-digital converters, and digital-to-analog converters. The
design of analog IC involves multiple factors and requires a trade-off between
factors such as speed, power consumption, gain, accuracy, power supply voltage,

Y. Cheng
Institute of Microelectronics, Peking University, Beijing, China
S. Ma · L. Jiang (*) · L. Zhao · B. Li
Shanghai Research Institute of Microelectronics, Peking University, Shanghai, China
e-mail: jiangll@shrime-pku.org.cn

© Publishing House of Electronics Industry 2024 711

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_37
712 Y. Cheng et al.

and so on. Also, it is very important to consider the influence of noise, crosstalk,
temperature, and other interferences on the circuit performance when performing
the analog circuit design.

Keywords
Bandgap reference design · Operational amplifier · Filter design · Analog-to-
digital converter · Digital-to-analog converter

Analog IC

Analog IC [1, 2] is an integrated circuit consisting of passive components (e.g.,

resistors, capacitors, inductors) and active devices (e.g., diodes and transistors) to
generate, amplify, filter, operate, convert, transmit, or process analog signals.
The basic units of analog IC include single-stage amplifiers, filters, feedback
circuits, current mirror circuits, voltage reference circuits, etc. The basic unit circuits
form high-level unit circuits, such as operational amplifiers (OA), comparators,
oscillators, and mixers, and even higher-level unit circuits, such as switched capac-
itor circuits, phase-locked loops (PLL), analog-to-digital converters (ADC), digital-
to-analog (DAC) converters, etc.
Traditionally, analog circuits mainly refer to the circuits based on operational
amplifiers. With the increasing complexity of circuit structure and practical applica-
tion, analog ICs are developed on the basis of discrete components theory and digital
IC technology, which makes some digital-analog hybrid circuits, such as digital-to-
analog converters, also be classified into the category of analog ICs. According to
the response relationship between the output and input signals, analog ICs can be
divided into linear IC and non-linear IC. The component parameters of linear ICs do
not vary with voltage or current, and the relationship between the input and output
signals can be expressed by a linear function. The output waveform is similar and
proportional to the input signal waveform. The component parameters of non-linear
ICs are related to voltage or current, and the response of the output signal to input
signal is non-linear.
The design of analog IC involves multiple factors and requires a tradeoff between
factors of speed, power consumption, gain, accuracy, power supply voltage, and so
on. At the same time, the analog signal is easily distorted by external influences
during transmission, so it is necessary to consider the influence of noise, crosstalk,
temperature, and other interferences on the circuit performance.
The design process flow of analog ICs mainly includes schematic input,
pre-layout simulation, layout design, design rule check (DRC), layout versus sche-
matic (LVS), parasitic parameter extraction, post-layout simulation, check for ESD/
latch-up/electrical migration issues, tape out, etc. According to the above process,
the designer first completes the circuit design based on the circuit function and then
completes the pre-simulation of the circuit function under the corner conditions of
process (P), power supply voltage (V), and temperature (T), i.e., the PVT corner
37 Analog Integrated Circuit Design 713

conditions. Next, according to the designed circuits, the designer completes in order
the layout design, process design rule checking, layout circuit consistency checking,
and parasitic parameter extraction. Using the extracted circuit files containing
parasitic parameters, the designer carries out the post-simulation to complete the
check for ESD/latch-up/electrical migration issues and modifies or redesigns the
layout as required. Finally, the layout file is generated as the final GDSII file and
handed to foundry for tape out.

Operation Amplifier Design

Operational amplifier, referred to as “op-amp,” is a circuit module with a very high

amplification ratio. It is a basic circuit unit in analog and digital-analog hybrid
circuits that can realize various functions from DC bias generation to filtering and
signal amplification [3].
The circuit symbol of the operational amplifier is shown in Fig. 37.1. It has two
input terminals, in-phase input (+) and opposite-phase(
) input, and one output.
Here, “in-phase” and “opposite-phase” refer to the phase relationship between the
input voltage and the output voltage of the operational amplifier. The symbol
represents the direction of signal transmission from left (input) to right (output).
When the input signal is imported by the in-phase terminal, the output signal has the
same phase with the input signal. When the input signal is imported by the opposite-
phase terminal, the output signal has the opposite phase to the input signal. The
circuit structure of a typical operational amplifier is shown in Fig. 37.2.

Fig. 37.1 Circuit symbols of

operational amplifiers

Fig. 37.2 Circuit structure of

a typical operational amplifier
714 Y. Cheng et al.

Fig. 37.3 Operational

amplifier voltage transfer
curve

The functional relationship between the output voltage uo and the difference
voltage uP
uN between the in-phase input and opposite-phase input terminals is
shown in Fig. 37.3, which is called the voltage transmission characteristic of the
operational amplifier, as follows:

uo ¼ f ðuP
uN Þ

Operational amplifier has two working regions: linear and non-linear. When the
operational amplifier operates in the linear region:

uo ¼ Aop ðuP
uN Þ

where the gradient of the curve Aop is the voltage amplification factor. Since the
object of operation amplifier is the differential mode signal, it is also referred to as
the differential mode open-loop amplification factor. When the operational amplifier
works in the non-linear region, the operational amplifier is equivalent to a compar-
ator. If the voltage at the in-phase input is larger, the output of the operational
amplifier is close to the positive supply voltage; if the voltage at the opposite-
phase input is larger, the output of the operational amplifier is close to the negative
supply voltage. The key performance parameters of operational amplifier include
voltage gain, bandwidth, input offset, input impedance, maximum input voltage, and
common mode rejection ratio.
According to performance and application requirements, operational amplifiers
can be divided into general-purpose operational amplifiers, low-power operational
amplifiers, precision operational amplifiers, high input impedance operational ampli-
fiers, broadband operational amplifiers and high-voltage operational amplifiers, etc.
From the point of circuit design, operational amplifier is generally composed of an
input stage, an intermediate stage, an output stage, and a bias circuit. The key of
operational amplifier design is to optimize the parameters of speed, voltage gain,
bandwidth, and power consumption based on the system application requirements.
37 Analog Integrated Circuit Design 715

Designers need a tradeoff consideration of many aspects in the overall design and
choose the appropriate circuit structure, device size, and bias voltage according
to the specification. Operational amplifier design often uses a dual cascode structure
to increase the gain by increasing the output impedance, the differential output to
improve the common mode rejection ratio and the power supply rejection ratio, and
the frequency compensation to achieve the phase margin to meet the requirements.
Operational amplifiers will continue to play a role in future IC design and system
applications and will play an important role in supporting future technological
development.

Bandgap Reference Design

Bandgap reference (bandgap) is a classic circuit structure unit that generates DC

voltage and current with a certain relationship with temperature. The working
principle of bandgap reference voltage source is to add the PN junction voltage
UBE with a negative temperature coefficient and the resistance voltage UT with a
positive temperature coefficient with appropriate weights, so that the temperature
coefficients of both sides can offset each other, and therefore obtaining the reference
voltage with a zero temperature coefficient. A practical circuit structure for realizing
the principle of bandgap reference voltage source is shown in Fig. 37.4.
The traditional bandgap reference voltage source can output a relatively accurate
voltage and has good power supply rejection characteristics, but its supply voltage is
high (>3 V), and the reference output range is limited (>1.2 V). When the power
supply is below 1.2 V, the traditional bandgap voltage reference has been unable to
meet the requirements. In addition, in the current circuit design process, MOS
transistors inevitably have secondary effects (mainly channel length modulation
effect and volume effect); therefore, to obtain a more accurate reference voltage,
additional circuits are needed for improving the power supply voltage rejection
ability and broaden the output range of the reference voltage.
The key performance parameters of bandgap reference circuit include tempera-
ture drift coefficient, power supply voltage rejection ratio, output noise, power
consumption, accuracy, sensitivity, etc. Temperature drift coefficient (TDC) reflects

Fig. 37.4 Structure of a basic

bandgap voltage reference
circuit
716 Y. Cheng et al.

the temperature-dependent offset of the output voltage of the bandgap reference

voltage source. Power supply rejection ratio (PSRR) is an important parameter to
measure the power noise rejection ability. For reference voltage source, the physical
meaning is the change of output voltage when the power supply voltage changes.
Output noise is a performance indicator to measure the noise at the output terminal of
bandgap reference voltage source. The output noise of the reference voltage source
circuit may significantly affect the performance of the low noise circuit. Power
consumption is used to measure the current consumed by the bandgap reference
circuit under normal working conditions. Accuracy refers to the relative or absolute
error between the actual output voltage and the nominal value voltage of the
reference voltage source. Sensitivity is defined as the ratio of the change rate of
the output voltage to that of the power supply voltage, which is used to evaluate the
voltage stabilization characteristics of the reference voltage source. The lower the
sensitivity, the better is the stability of the reference voltage source.
In the design of high-precision bandgap reference circuit, except for using current
mirror and voltage negative feedback technology to improve PSRR, chopping
modulation technology is also used to effectively reduce errors caused by opera-
tional amplifier offset voltage in reference voltage source, and trimming technology
is used to adjust resistance value to achieve accurate temperature compensation;
therefore, the accuracy of reference voltage source are improved. In order to reduce
the influence of power supply voltage fluctuation on reference voltage, cascode
structure and high gain feedback loop are common circuit design techniques for
mirror phase current source of the bandgap circuit. In addition, attention should be
paid to the matching and symmetry between the devices in layout design, especially
the symmetry between MOSFETs which constitute current mirrors, so as to ensure
the consistency of the surrounding environment as much as possible.

Filter Design

In IC design, filter circuit unit is used to select the frequency of the signal, and only
the signal components in a specific frequency range are allowed to pass normally,
while the signal components beyond the specific frequency range are effectively
filtered out.
There are several ways to classify filters. According to the processed signal, it can
be divided into analog filter and digital filter. According to the components of the
circuit, it can be divided into passive filter and active filter. According to the filter
frequency selection range and filter nature, it can be divided into low-pass, high pass,
bandpass, and band-stop filters. According to different frequency response func-
tions, it can be divided into Bessel filter, Chebyshev filter, Butterworth filter,
Gaussian filter, and so on.
In practical application, the choice of filters is determined mainly by the fre-
quency selectivity of the filter. A low-pass filter (LPF) allows low frequency
components below the signal cutoff frequency fc to pass through, while components
above the cutoff frequency are attenuated. A high-pass filter (HPF), contrary to the
37 Analog Integrated Circuit Design 717

low-pass filter (LPF), allows high frequency components above the signal cutoff
frequency fc to pass through, while components below the cutoff frequency fc are
attenuated. A bandpass filter (BPF) allows a signal in a certain frequency band
( fc1  fc  fc2) to pass through, while components below or above that frequency
band are attenuated. A band-stop filter (BSF, also known as band-elimination, band-
reject, or notch filters), in contrast to a bandpass filter, allows signal components with
frequencies below fc1 or above fc2 to pass through, while frequency components
between fc1 and fc2 are attenuated. The actual amplitude-frequency characteristics of
these four types of filters are shown in Fig. 37.5. Low-pass filter and high-pass filter
are the two most basic forms of filters, and the other filters can be composed of these
two types of filters. For example, the series connection of low-pass filter and high-
pass filter is a bandpass filter, and the parallel connection is a band-stop filter.
The basic parameters of the filter include gain, cutoff frequency, center frequency,
passband bandwidth, quality factor, and out-of-band rejection. Gain, also known as
passband amplification factor, is the ratio of the output voltage to the input voltage in
the passband. In the amplitude-frequency characteristic curve shown in Fig. 37.5, A0
represents the gain of the filter. The frequency corresponding to the amplitude of
0.707 A0 is called the cutoff frequency of the filter. 0.707 A0 corresponds to a
3 dB
point in logarithmic coordinates, that is, the cutoff frequency is a frequency value
corresponding to the amplitude that is attenuated by 3 dB relative to A0. For
bandpass filters, center frequency f0 ¼ ( fc21 þ fc2)/2. The frequency width of the
signal that the filter can pass is called the filter bandwidth, e.g., the range between the
up and down cutoff frequencies is the bandpass filter bandwidth or the
3 dB

Fig. 37.5 Amplitude-frequency characteristics of four filters

718 Y. Cheng et al.

bandwidth. The quality factor of the filter, also known as the cutoff characteristic
coefficient of the filter, is the ratio of the voltage amplification factor to the bandpass
amplification factor when the frequency is equal to the resonant frequency (natural
frequency) of the filter. Out-of-band rejection is the amount of attenuation beyond
the bandpass frequency range of the filter, characterizing the filter suppression of
frequency components outside the bandwidth.
The filter design is to search a suitable transfer function to meet the required
specifications. After determining the filter type according to the system application
requirements, based on the selected filter type (active or passive, digital or analog,
etc.), the mathematical characteristics of the filter response need to be carefully
analyzed, and then the linear circuit or non-linear circuit is selected according to the
circuit parameter, and the optimum design of the pre-distortion circuit, impedance
conversion circuit, amplitude equalization circuit, delay equalization circuit, wave-
form generation and conversion circuit, feedback amplification and large signal
output amplification circuit, power amplification, voltage feedback, and current
feedback amplifier are made. Filter design is critical in some IC chips, especially
in IC designs for wireless communication system applications and is a key analog
module unit in IC design.

Analog-to-Digital Convertor

Analog-to-digital converter (ADC) or conversion circuit is an IC that converts an

analog input signal whose amplitude varies continuously with time into a digital
output signal that is discrete in both time and amplitude. The input analog signal of
A/D conversion circuit will usually be compared with the standard value and then
converted into discrete signal expressed by a multi-bit binary value. In general, for
N-bit resolution ADC, the output range of binary data is 0–2N
1, with a total of 2N
discrete values. For example, an ADC with 6-bit resolution can encode an analog
signal into 64 different discrete values (as 26 ¼ 64). Any analog-to-digital conver-
sion circuit needs a reference value (reference voltage or current) as the standard of
conversion, and the output digital signal indicates the magnitude of the input signal
relative to the reference value.
Analog-to-digital conversion includes four processes of sampling, hold, quanti-
zation, and coding. Sampling is the conversion of a time-continuously varying
analog signal into a time-discrete sampled signal through a series of equally spaced
sampling pulses as shown in Fig. 37.6. The sampling theorem (known as Nyquist-
Shannon theorem) was proposed by American telecommunication engineer
H. Nyquist of Bell Labs in 1928 [4]. It explains the relationship between sampling
frequency and signal frequency and thus establishes the connection between analog
signal and digital signal. The sampling theorem is the basis for discretization of
continuous signal. To digitalize a sampled output signal, the instantaneous analog
signal from the sampled output needs to be held for a period of time as the hold
process. During the hold time, quantization and coding are performed, and then the
next sampling is started. Quantization, also known as amplitude quantization, is
37 Analog Integrated Circuit Design 719

Fig. 37.6 Sampling process

for A/D conversion

processing the signals that are discrete in time after sampling in order to make them
also discrete in amplitude. For example, the amplitude range of the signal is evenly
divided into N equal parts, each of which corresponds to an output value, and the
sampled discrete signal amplitude is respectively divided into the part closest to its
value; thus the signal is discretized in amplitude. Commonly quantization methods
include rounding quantization and truncation quantization. Quantization will inev-
itably introduce quantization error. Quantization error is the difference between the
equivalent analog value of the output signal and the analog value of the actual input
signal. The encoding process is to encode the quantized signal into a specific digital
code output. The usual encoding methods include natural binary encoding and
binary complement encoding.

Characteristic Parameters of Analog-to-Digital Converter

The main characteristic parameters of the ADC include the static characteristic
parameters and dynamic characteristic parameters.

1. Static characteristic parameters. (1) Analog Resolution: The minimum analog

increment of the digital code change corresponding to the least significant bit
(LSB). (2) Offset: Output drift under zero input conditions. (3) Gain Error (GE):
The error of the gradient of the transmission characteristic curve. This parameter
defines the deviation of the gradient of the A/D converter from the ideal value.
(4) Differential Non-Linearity (DNL): The difference between the actual conver-
sion step width of the A/D converter and the width of its ideal conversion step Δ.
Assuming that Xk is the jump point between adjacent codes k
1 and k, then the
width of binary code k is Δr(k) ¼ Xkþ1
Xk; thus the differential non-linearity is
defined as:

Δr ðkÞ
Δ
DNLðkÞ ¼
Δ
720 Y. Cheng et al.

(5) Integral Non-linearity (INL): Used to measure the deviation of the actual
conversion curve from the ideal interpolation curve. Another definition is to measure
the deviation of the actual conversion curve from the endpoint fitting curve. Con-
sidering the endpoint fitting curve, the integral non-linearity is defined as:

k
INL ¼ ð1 þ GEÞ DNLðiÞ
i¼1

where GE is the gain error.

2. Dynamic characteristic parameters. (1) Signal-to-Noise Ratio (SNR): The ratio

of signal power to total noise power. (2) Signal-to-Noise-and-Distortion Ratio
(SINAD or SNDR): Similar to the definition of SNR, but it also includes the
non-linear distortion term produced by the sine wave input. The signal-to-noise-
and-distortion ratio is the ratio of the signal power and the sum of harmonic
components plus noise (except DC). (3) Dynamic Range (DR): The value of the
input signal when SNR or SINAD is 0 dB. (4) Effective Number of Bits (ENOB):
SINAD expressed in bits. The relationship between SINAD and ENOB in dB is
as follows:

ENOB ¼ ðSINADdb
1:76Þ=6:02

(5) Total Spurious Distortion (TSD): The square root of the sum of the squares of
the spurious components in the ADC output spectrum. (6) Spurious Free Dynamic
Range (SFDR): The ratio of the root mean square of the signal amplitude to the root
mean square of the largest spurious spectral component in the first Nyquist interval.
(7) Effective Resolution Bandwidth (ERBW): The analog input frequency when
SINAD drops by 3 dB versus a low-frequency. (8) Figure of Merits (FoM): A
parameter evaluating the power consumption of an ADC. FoM has a variety of
definitions, and a common definition is

Power
FoM ¼
2ENOB  2  ERBW
Study of ADC testing shows that dynamic parameters are not sensitive to the
number of samples or the number of input periods but are sensitive to the input signal
amplitude; they can also exhibit significant variations against static errors.

Analog-to-Digital Converter Design

Typical ADC include dual-integrated ADCs, sigma-delta (Σ-Δ) ADCs, successive

approximation (SAR) ADCs, pipelined ADCs, Flash ADCs, etc.
37 Analog Integrated Circuit Design 721

Dual-integrated ADC is an indirect ADC. It integrates the input sampled signal

and the reference voltage twice to obtain a time interval proportional to the input
signal. At the same time, the counter is used to count the standard clock pulse. The
count value of the counter is the digital output amount of ADC. In the specific
circuit, the offset of the op-amp and comparator is an important performance limiting
factor, which needs to be eliminated by automatic zero adjustment.
Σ-Δ ADC is also called the oversampled ADC. It consists of a Σ-Δ modulator and
a digital filter connected to the modulator. It is especially suitable for applications
such as audio signal processing, biomedical signal acquisition, and other require-
ments such as low-frequency, high-precision, and analog-to-digital conversion. Its
high-precision conversion comes from two main technologies, oversampling tech-
nology and noise shaping technology. Oversampling techniques turn the signal
bandwidth into a fraction of the Nyquist frequency, so the quantization noise is
spread over a wider range of frequencies. The noise shaping technique reduces the
in-band noise and further improves the signal-to-noise ratio within the frequency
band of interest by changing the noise transfer function. The quantization noise
within a larger range of band beyond the band of interest can be eliminated using
digital techniques.
SAR ADC is a direct ADC. It generates a series of comparator voltages, com-
paring the comparator voltage with the input voltage one by one from high to low,
and performing analog-to-digital conversion in a gradual approximation. SAR ADC
can use capacitor networks and charge redistribution methods to theoretically
achieve lower power consumption. SAR ADC is a medium-speed ADC device. In
recent years, a variety of new technologies, especially the use of asynchronous
operation, have continuously improved the conversion rate of SAR ADC.
Pipelined ADC, also known as the sub-area ADC, consists of cascaded similar-
structure low-precision ADC circuits and can provide medium-speed, high-resolu-
tion analog-to-digital conversion. Since each level of the pipelined ADC has its own
sample/hold circuit, as long as the sampling conversion is completed in some level
and the result is input to the next level, the current level circuit can be released to
process the next sampling. Therefore, the pipeline operation improves the conver-
sion speed. For pipelined ADC, the most stringent requirements lie in the input
sample-and-hold circuit and the first few levels of the pipeline. The error of the DAC
will modify the margin of the entire LSB part, thereby affecting the linearity of the
entire ADC. Therefore, the accuracy of the pre-stage DAC must be higher than the
INL required by the ADC to ensure the linearity of the overall response.
Flash ADC is also referred to as scintillation ADC. The input signal is sampled
and compared with multiple reference voltages at the same time; therefore, the
conversion speed is fast. It is a direct ADC. Flash ADC has several limitations as
noted below. First, an N-bit Flash ADC requires 2N–1 comparator. With the increase
of resolution N, the circuit area and power consumption will be greatly increased.
Second, too many comparators will reduce the input bandwidth. Third, since the
resistor string divides the reference voltage into multiple sections to access the
comparator, it is necessary for the comparator to ensure a sufficiently small offset
and similar delay over a wide common mode input range. Fourth, the mismatch of
722 Y. Cheng et al.

the resistor string brings errors in every comparator level, which affects the linearity
of the ADC. Fifth, the comparator’s kickback noise causes the instability of the
comparator input.
In addition to the single-channel ADC type mentioned above, multiple single-
channel ADCs can be integrated using time interleaved (TI) method to greatly
increase the sampling rate. The basic principle of TI ADC is to control the sampling
and conversion of each channel ADC at different times by the phase difference of the
clock. In theory, the sampling rate of the system can be infinitely increased by
increasing the number of the ADC channels. However, TI ADC faces various design
challenges during implementation. The first is to design a wideband sample-and-
hold circuit with sufficient linearity, which requires a comprehensive tradeoff con-
sideration of on-resistance, mismatch, parasitic, signal-coupled interference, power
consumption, and so on. Second, the clock jitter is demanding, even at femtosecond
(fs) levels. Therefore, the distribution and design of the clock will consume a lot of
power and make higher demands on noise and power supply stability. Again, there
are mismatch errors between multiple parallel channels, including offset error, gain
error, sampling time error, and bandwidth error. These errors vary with process,
voltage, and temperature (PVT), which may cause recurring errors after calibration,
thus reliable and efficient calibration algorithms and implementation circuits are
needed. Finally, when TI ADC and digital signal processor (DSP) are integrated on
the same chip to perform ADC calibration and other digital signal processing, it will
cause noise coupling from digital circuits to analog circuits, reduce the performance
of the entire ADC, and make the noise design of the ADC more difficult.

Characteristic Parameters of Digital-to-Analog Converter

Digital-to-analog converter (DAC) is a circuit unit that converts an input digital

signal (both time and amplitude are discrete) into an analog signal (amplitude varies
continuously with time). DAC is widely used in signal processing, navigation,
communication, and measurement. In recent development, the performance of
DAC has been continuously improved and developed in different directions. High-
precision, high-speed DAC plays a necessary key role in different application fields.
The characteristic parameters of DAC can be divided into static parameters and
dynamic parameters. In high-precision applications such as audio signal processing,
static performance is the focus of attention, while in high-speed applications such as
wireless communication, dynamic performance is the focus of attention.

1. Main static parameters. (1) Offset Error: The deviation of the actual output of
DAC from the ideal zero output at zero input. This is an inherent error which can
be easily compensated. (2) Gain Error: The deviation of the gain of the actual
transfer function of DAC from the gain of the ideal transfer function, expressed as
a percentage. Gain errors can usually be corrected by adjusting the full scale of
the actual DAC. (3) Differential Non-linearity (DNL): The difference between the
actual analog step size of DAC and the ideal analog step size (i.e., 1 LSB)
37 Analog Integrated Circuit Design 723

between two adjacent input codes. Generally, the DNL is needed to be in the
range of +/
0.5 LSB. Otherwise, the DAC will be non-monotonic, which will
affect the conversion performance. (4) Integral Non-linearity (INL): The differ-
ence between the actual transfer function curve of DAC and the ideal transfer
function curve on each input code.
2. Main dynamic parameters. (1) Signal-to-Noise Ratio (SNR): The ratio of the
signal (single-frequency sinusoidal) output power to the total noise power of the
quantized noise in the Nyquist bandwidth plus the noise caused by the circuit.
The SNR of an ideal DAC reflects the level of quantization noise, which is the
inherent characteristic of the digital signal that is input to the DAC after sample
quantization and processing. However, the actual DAC also causes harmonic
distortion (HD) due to its own non-linearity. These harmonic distortion energies
are often much larger than those of the noise floor. (2) Spurious-Free Dynamic
Range (SFDR): Since SNR characterizes the overall noise performance of DAC,
it does not reflect well the relationship between signal energy and local harmonics
and thus the characteristics of the DAC. Therefore, a spurious-free dynamic range
is introduced to better characterize the dynamic performance of a DAC with
non-linearity. SFDR is defined as the ratio of the signal power to the maximum
clutter power when a single-frequency sine wave signal is input. (3) Total Har-
monic Distortion (THD): In order to reflect the non-linearity of DAC, it is also
necessary to analyze harmonic distortion in the required frequency band. THD
represents the ratio of the sum of harmonic distortion power to the fundamental
signal power. (4) Signal-to-Noise-and-Distortion Ratio (SNDR): Since the actual
DAC has non-linear harmonics, not only the noise but also the harmonics should
be considered when evaluating its dynamic linearity influences. Similar to the
definition of SNR, SNDR is defined as the ratio of signal power to noise and the
sum of all harmonic powers in the band. (5) Effective Number of Bits (ENOB):
The SNR of an ideal DAC is determined by the number of resolution bits, N, but
because the actual DAC has the non-linear factors, it is more suitable to use
SNDR to evaluate the dynamic characteristics. To measure the deviation of the
actual DAC from the ideal DAC caused by harmonic distortion, the effective
number of bits is introduced to reflect the linearity of the DAC.

Digital-to-Analog Converter Design

The main function of DAC is to complete the transformation from digital signal to
analog signal. The whole conversion involved is the key to affect the performance of
DAC.

1. Nyquist DAC. Nyquist DAC is mainly divided into resistive DAC, capacitive
DAC, and current DAC. (1) Resistance DAC mainly includes resistance dividing
type and R-2R weight type. (2) Capacitive DAC consists of a binary capacitive
network and a voltage amplifier. The switching network uses capacitors; therefore
there is no static current, and thus the power consumption is low. In addition, in
724 Y. Cheng et al.

CMOS process, a capacitance can achieve higher matching accuracy than a

resistance; therefore, the resolution of capacitive DAC can be further improved.
However, due to the large capacitance at the summation node, the time constant is
large, and the capacitive DAC is not suitable for high-speed applications. The
resistive and capacitive DACs mentioned above cannot drive external loads
directly and need buffer or conversion circuit to get the final voltage or current
output signal; therefore, these DACs will be limited by the bandwidth of buffer
and cannot achieve high conversion rate. (3) Current-mode DAC is a more
appropriate choice for high-speed applications, such as wireless communications.
Current-mode DAC realizes the function of current by adding direct connection
with the node of current source and then directly connecting the added current
with the load resistance to generate the required output voltage without additional
buffer driver. Moreover, the current directly drives the load to form the output
voltage; therefore, it can achieve a high working speed.
Current-mode DAC is mainly divided into binary weight structure DAC,
thermometer decoding structure DAC, and segmented decoding structure DAC.
(1) The weight of each switch-controlled current source of the binary weight
structure DAC is incremented by a factor of two, and the input binary code is used
to control the on and off of the corresponding current source. The increase of
current weight in this structure is generated by duplicating the unit current source,
and the input signal works directly on the current source switch without addi-
tional complicated circuit decoding, which greatly reduces the chip area and
power consumption. The increase of the resolution of the binary weight structure
DAC makes the current source weight increase exponentially. On the one hand,
the larger differential non-linearity (DNL) caused by the matching error of the
current source affects its static characteristics. On the other hand, the larger burr
introduced when the control signal switches at high speed affects its dynamic
performance. (2) The current source array of the thermometer decoding structure
DAC consists of a series of currents with equal weights. This switching mode
effectively avoids the influence of large burrs introduced during the switching
process on the dynamic performance. However, with the increase of the resolu-
tion bits of DAC, the number of switches increases exponentially, which dramat-
ically increases the complexity of the circuit of thermometer decoding structure,
resulting in larger area and power consumption. (3) Combining the advantages
and disadvantages of binary weight structure DAC and thermometer decoding
structure DAC, the segmented decoding structure DAC is a tradeoff between
performance and circuit complexity. It is divided into two parts: MSB and LSB.
Let N be the number of DAC bits, the MSB part of M bit is translated into
thermometer code, and the remaining LSB part of N-M bit is still binary code. The
DAC includes a decoder that can convert M-bit binary signal into 2M
1 bit
thermometer code. The high-bit current source is realized by the thermometer
decoding structure, and the unit current value is IT. The low-level current source is
realized by binary weight structure, and the unit current value is I. This kind of
DAC type can obtain the best compromise between area and circuit complexity
37 Analog Integrated Circuit Design 725

while achieving good static and dynamic performances. Therefore, most high-
precision or high-speed current-mode DACs are segmented decoding structures.
2. Oversampling DAC. Oversampling DAC, as another type of DAC that is
different from Nyquist DAC, is often used in high precision applications such
as audio signal processing. Oversampling DAC can achieve high resolution by
using oversampling technology and noise shaping technology similar to ADC.
The difference from over-sampled ADC is that for over-sampled ADC, over-
sampling is done in analog domain, and continuous time input is converted to the
form of sampled data somewhere, while for over-sampled DAC, oversampling is
done in digital domain to produce digital results, which is then converted into
continuous time analog signal by a lower-bit DAC and a reconstructed filter.

References
1. B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill, 2001)
2. J. Chen, M. Henrie, M.F. Mar, Nizic, M., Mixed-Signal Methodology Guide, Cadence/lulu.com
(ISBN 978-1300-035206), 2012. (Also in Chinese, Chen, C.-Z., He, L.N., Li, Z.Q. and Ai, X.:
Science Press, ISBN 978-7-03-041959-0, 2015)
3. L.N. He, Y. Wang, Analog IC Design and Simulation (Science Press, Beijing, 2022) (Chinese
book series 3 of 5, ISBN 978-7-03-021427-0)
4. H. Nyquist, Certain topics in telegraph transmission theory. Trans. A.I.E.E. 47(2),
617–644 (1928) Reprint: Proc. IEEE, 90(2), 280–305 (2002)
RF Integrated Circuit Design
38
Pengcheng Xiao, Yumei Huang, Wei Li, Na Yan, and Xiaoyang Zeng

Contents
Radio Frequency Integrated Circuit (RFIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Microwave and Millimeter Wave Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Software Defined Radio (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Radio Frequency Transceiver Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
Low Noise Amplifier (LNA) Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Mixer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Frequency Synthesizer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Radio Frequency Power Amplifier (RF PA) Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Radio Frequency Switch Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Digital Radio Frequency Integrated Circuit (RFIC) Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

Abstract
The radio frequency (RF) usually ranges from 300 kHz to 30 GHz. The RF circuit
can perform RF signals which are filtered, amplified, frequency-converted, and
modulated. The circuit for processing such as demodulation is an RF circuit. A
radio frequency integrated circuit (RFIC) usually consists of basic functional
circuits, e.g., low noise amplifiers, filters, mixers, frequency synthesizers, and
power amplifiers. The RF transmitting and receiving system constitutes a carrier
channel for transmitting and receiving signals of wireless systems, e.g., wireless
communication, radar detection, television broadcasting, navigation, and the like.
To support the ever-increasing levels of SoC integration with the low-cost
requirement, the RFIC design has been moving to the advanced CMOS process
nodes. Digital RF technology can transform the continuous-time analog RF
functionality into digitally intensive or even all-digital implementations.

P. Xiao · Y. Huang · W. Li · N. Yan · X. Zeng (*)

School of Microelectronics, Fudan University, Shanghai, China
e-mail: xyzeng@fudan.edu.cn

© Publishing House of Electronics Industry 2024 727

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_38
728 P. Xiao et al.

Keywords
RFIC · MMIC · SDR · LNA · Mixer · PLL · PA · RF switch · Digital RFIC

Radio Frequency Integrated Circuit (RFIC)

Radio frequency (RF) refers to a high-frequency electromagnetic signal that can be

radiated into or received from a space through an antenna. The frequency range is
usually between 300 kHz and 30 GHz. The RF signals need to be processed by
signal filtering, power amplification, frequency-conversion, and modulation by
using RF circuits or integrated to ICs referred to as RF integrated circuit (RFIC) [1].
Radio frequency ICs usually consist of basic functional circuits such as low noise
amplifiers (LNA), filters, mixers, frequency synthesizers, and power amplifiers. The
radio frequency transmitting and receiving system constitutes a carrier channel for
transmitting and receiving signals of wireless systems such as wireless communica-
tion, radar detection, television broadcasting, navigation, etc. The baseband section
implements signal filtering and digital-to-analog/analog-to-digital conversion, as
well as digital signal processing. Figure 38.1 illustrates a block diagram of a typical
RF system.
The salient features of the signals processed by the RFIC include the following:
(1) the signal frequency is high. (2) There is a certain bandwidth as generally much
smaller than the carrier frequency. (3) The signal received by the antenna is very
weak, and the transmitted signal radiated from the antenna is very strong, usually
5–10 orders of magnitude larger than the received signal. These characteristics make
the design of RFICs very different from other types of circuits.

Fig. 38.1 Typical RF system structure

38 RF Integrated Circuit Design 729

The early RFICs were mainly based on GaAs. In 1976, the first GaAs RF IC was
developed [2]. Since then, the GaAs process has been rapidly developed, and there
are also some shortcomings: (1) low yield; (2) relatively small wafer size, low
mechanical strength, and easy to break; (3) poor heat dissipation; and (4) incompat-
ible with Si process. After the 1980s, SiGe materials became into being, which made
up for the shortcomings of GaAs. In 1987, SiGe heterojunction bipolar transistor
(HBT) was first reported; and in 1994, SiGe HBT with a cutoff frequency higher than
100 GHz was developed. After that, SiGe HBT has established the role in RFIC. In
recent years, GaN, as a wide bandgap semiconductor material, has high electron
mobility, high band gap, and high breakdown field strength. At the same time, the
power density can reach more than 5 times that of GaAs, which can significantly
increase the output power.
After reducing system size and cost, GaN RF power devices have entered into a
practical stage. Since the 1990s, with the continuous scaling of CMOS technology
and the development of circuit design methodology, the CMOS technology has
become the mainstream for RFICs with the GaAs and SiGe processes mainly for
RF power amplifiers.
RFICs have been widely used in wireless communication, RF identification
(RFID), navigation, radar, and other systems. Especially in the past 10 years, the
development and popularization of personal mobile communication has promoted
the rapid progress of RFICs. With the continued development of personal mobile
communications, the Internet of Things (IoT), and semiconductor materials and
processes, RFICs will be moving forward toward low cost, low power, large
bandwidth, high speed, and support for multi-mode, multi-band, reconfigurable,
the development of baseband monolithic integration, and other directions.

Microwave and Millimeter Wave Integrated Circuit

Generally, the microwave frequency is from 300 MHz to 3000GHz, and the
corresponding electromagnetic wavelength from 1 m to 0.1 mm. It can be further
divided into four bands, i.e., decimeter wave (wavelength range 1 m-100 mm),
centimeter wave (wavelength range 100 mm–10 mm), millimeter wave (wavelength
range 10 mm–1 mm), and sub-millimeter wave (wavelength range 1 mm–0.1 mm).
Bands below 30 GHz overlap with RF bands, commonly referred to as RF bands;
bands above 300 GHz are known as sub-millimeter waves and also commonly
referred to as terahertz (THz) bands. The microwave band usually refers to the
frequency range of 30 GHz to 300 GHz as microwave millimeter wave.
The microwave (μm) and millimeter (mm) wave IC refers to an IC operating in
the μm and mm wave band, which has functions of amplification, mixing, filtering,
etc. The design of μm and mm wave IC requires a more accurate component model
and even requires three-dimensional (3D) electromagnetic field analysis and
calculations.
Microwave and millimeter wave ICs include bandpass filters, low noise ampli-
fiers, power amplifiers, main amplifiers, preamplifiers, mixers, frequency
730 P. Xiao et al.

Fig. 38.2 Typical microwave and millimeter wave integrated circuit system structure

synthesizers, and frequency multipliers. The μm and mm wave transceiver system

and the RF transceiver system are similar in system structure, but the operating
frequency is higher, the bandwidth is larger, and the circuit design is more difficult.
The μm and mm wave ICs can be divided into hybrid μm and mm wave ICs and
monolithic μm and mm wave ICs according to the implementation form. Figure 38.2
is a system block diagram of a typical μm and mm wave IC.
Hybrid μm and mm wave ICs are used on dielectric substrate materials (such as
alumina ceramics, quartz, sapphire, etc.), thick film processes (such as low temper-
ature/high temperature sintering process, printing process, etc.), or thin film pro-
cesses (such as sputtering process, electroplating process, etc.) Prepare circuit
topology diagrams of various functions, and then install components or chips of
various discrete package forms to corresponding positions to form a certain function
of μm and mm wave ICs.
Monolithic μm and mm wave ICs are used to fabricate microwave active and
passive devices on semiconductor substrates (such as Si, SiGe, GaAs, etc.) using
semiconductor processes, as well as various functional circuits with high integration,
high reliability, low cost, and other characteristics.
GaAs has the characteristics of high electron mobility and good noise perfor-
mance. The GaAs process was the mainstream process of μm and mm wave ICs. At
the same time, the CMOS with SiGe HBT is also a common process for the μm and
mm wave IC with higher gain, speed, better noise performance, and lower cost than
GaAs process. In recent years, CMOS technology has been continuously improved
and met the speed requirements of μm and mm wave ICs higher than the 100 GHz
band, which also makes it possible to integrate the RF front end and the digital
baseband in a wireless system. The monolithic μm and mm wave ICs based on
CMOS process have entered a stage of rapid development.
In the early days, microwave circuits and other devices such as tubes and
klystrons were used. With the development of semiconductor technology,
38 RF Integrated Circuit Design 731

solid-state microwave devices including heterojunction bipolar transistors (HBT),

varactors, and field-effect transistors (FET) have been widely used. Subsequently,
the system increasingly complex, working frequency is increasing, the consistency
of discrete devices is difficult to meet system requirements. In 1976, the develop-
ment of 7–12 GHz microwave ICs using GaAs technology opened a new era in this
field, using GaAs or InP process. Microwave and millimeter wave ICs are widely
used in satellite communications, radar, and the like. After 2000, the United States,
Japan, South Korea, and other countries have opened the 57GHz ~ 64GHz frequency
band, and Europe opened the 77GHz frequency band, further promoting the research
of single-chip μm and mm wave ICs based on CMOS technology.
At present, the spectrum resources below the 10 GHz band are depleted, and the
μm and mm wave band can provide more unallocated spectrum resources. There-
fore, the working frequency band of the wireless system will gradually develop to
the high frequency band of the microwave above 60 GHz. The advancement of
process technology has provided technical support for this development. The speed
of CMOS technology is continuously improved. Combined with its high integration
characteristics, CMOS process technology for μm and mm wave ICs will develop
faster.

Software Defined Radio (SDR)

Software-defined radio (SDR) is a wireless communication technology. The wireless

communication system, originally composed with amplifier, mixer, and filter, will be
replaced by software, digital circuits, and embedded system, so that the system
parameters are easily configured for different requirements. The SDR here refers
to an integrated software-defined wireless transceiver. Its basic idea is to directly
convert the RF signals using analog-to-digital converter (ADC) and digital-to-analog
converter (DAC). Figure 38.3 illustrates a block diagram of an integrated software-
defined radio transceiver system.
Software-defined radio (SDR) has a strong flexibility. It can configure and
reconstruct RF and IF analog circuits, expand the functions by digital modules,
and update circuit designs as process technology evolves.
Software-defined radio requires the high performance on analog-to-digital con-
verters (ADCs) in terms of dynamic range, sampling rate, etc. At present, it is
difficult to fully implement an ideal software-defined radio transceiver chip. The
most reported SDR transceiver chip is a reconfigurable transceiver chip, where the
performance of each analog/RF module can be configured through digital circuits in
order to realize multi-mode multi-band transceivers and the optimization of the RF
specification is realized by adjusting parameters. At the same time, another realiza-
tion scheme is based on the narrowband adjustable filter or mixer for lowering the
carrier frequency of RF signal and reducing the performance requirements of analog-
to-digital converter (ADC). With the continuous development of IC manufacturing
technology and design skills, fully software-defined transceiver chips will be real-
ized in the near future.
732 P. Xiao et al.

Fig. 38.3 Transceiver system

Software-defined radio (SDR) is different from cognitive radio (CR). The main
difference is that CR has the ability of learning and perception. It can select the
appropriate spectrum according to the existing communication channels, so as to
limit and reduce the occurrence of conflicts and improve communication efficiency.

Radio Frequency Transceiver Design

In a wireless system, an RF transceiver is used to process RF signals, and it is

generally composed of RF front end and baseband circuits. The RF front-end serves
to amplify the RF signal, and up/down convert the signal spectrum, etc. The
baseband circuits usually include an analog baseband circuit for amplifying, filter-
ing, and converting the signal and a digital baseband circuit for performing digital
signal processing, etc.
The existing receiver architecture usually includes a super-heterodyne receiver, a
zero intermediate frequency receiver, a low intermediate frequency receiver, a digital
intermediate frequency receiver, etc. Among them, the super-heterodyne architecture
has a signal image interference problem and requires an RF image suppression filter;
and it is less suitable for chip integration. The zero intermediate frequency architec-
ture can perform directly down-convert the RF signal to the DC point without RF
image signal interference, and it is more suitable for chip integration. Figure 38.4
illustrates a block diagram of a configurable narrowband zero IF receiver system.
The transmitter converts the digital baseband signal into an analog signal through
digital-to-analog conversion (DAC) and transmits the signal after filtering, spectrum
shifting, and power amplification. The existing transmitter architecture mainly includes
a direct conversion transmitter, an all-digital transmitter, a polar modulation transmitter,
etc. Figure 38.5 is a block diagram of a commonly zero-IF transmitter system.
38 RF Integrated Circuit Design 733

Fig. 38.4 Configurable narrowband zero IF receiver system block diagram

Fig. 38.5 Zero IF transmitter system block diagram

At present, RF transceivers are widely used in the fields of mobile wireless

communication, navigation, and data/audio/image data wireless transmission.

Low Noise Amplifier (LNA) Design

Among a receiver path in a wireless communication system, low noise amplifiers

(LNAs) are the first amplifiers that can amplify the weak RF signal received from the
RX antenna [3]. The overall performance includes noise fig. (NF), gain, input
impedance match, stability, and so on.

1. Noise Fig. (NF): NF of LNAs dominates the noise performance of the whole
receiver. The definition of NF is

SNRin
NF ¼ 10lg ðdBÞ,
SNRout
where SNRin is the ratio of signal to noise at the input and SNRout the ratio of
signal to noise at the output.
734 P. Xiao et al.

2. Gain: LNAs must have certain gain to suppress the noise contribution of subse-
quent stages, especially the noise from the mixer. In modern RF design, the gain
of LNAs usually means the voltage gain. Among S-parameters (scattering param-
eters), S21 is used to measure its amplifying ability. In a receiver system design,
LNA gain has some effect on the linearity of the receiver.
3. Input Impedance Matching: From the maximum power transmission point of
view, it is necessary to consider the impedance matching between the LNA and
the antenna. The performance of impedance matching is measured by S11 and also
can be expressed by “return loss” which is given by

2
Z in  Rs
Γ¼ ,
Z in þ Rs

where Zin is the LNA input impedance and Rs is the signal impedance. After
matching, the LNA is designed for a 50 Ω resistive impedance.
4. Stability: because the LNA must interface with the “outside” world, it necessarily
remains stable for all source impedances at all frequencies. The parameter K is
used to characterize the stability of LNAs:

1 þ jΔj2  jS11 j2  jS22 j2

Κ¼ ,
2 jS21 S12 j

where Δ ¼ S11S22  S12S21 and S11, S22, S12, and S21 are the S-parameters of a
two-port network. If Δ < 1 and K > 1, the circuit is unconditionally stable.

So far, there are mainly three types of LNA topologies. (1) Cascode common-
source (CS) with source inductive degeneration; this kind of LNAs is suitable for
narrow-band RF receiver. (2) Cascode common-gate (CG) topology, it is widely
used in wide-band receiver. (3) Noise-Cancelling LNAs, noise-cancelling techniques
can be adopted in both common-source and common-gate topologies, which can
result in good noise performance as well as wideband feature.
With the development of portable devices, low power consumption has become
an important requirement for RF transceiver IC. For good trade-off among noise
performance, input impedance matching and power consumption, an extra capacitor
can be added between the gate and the source of the input transistor inside the CS
LNA to optimize the noise and impedance matching performances under certain
power consumption.

Mixer Design

The channel bandwidth of wireless communication is usually very narrow (such as

GSM system, whose channel bandwidth is only 200 kHz), and the receiver usually
converts the signal from the RF band to the lower or intermediate frequency
38 RF Integrated Circuit Design 735

(LF) band and then performs channel filtering. The circuit that completes the band
conversion is the mixer. A wireless communication transceiver system usually
includes the down-mixer in the receiver and the up-mixer in the transmitter.
The main performance parameters of the mixer are as follows: (1) Noise, the
noise figure of the mixer is related to the architecture of the receiver or transmitter.
For IF receivers, the mixer noise is called single-sideband (SSB) noise; for zero-IF
receivers, the mixer noise is called double-sideband (DSB) noise. Ideally, single-
sideband noise is 3 dB higher than double-sideband noise. (2) Linearity: Linearity is
often measured by the third-order intercept point (IP3) and the second-order inter-
cept point (IP2). The gain of the low-noise amplifier has a large effect on the noise
and linearity of the mixer. (3) Gain: The ratio of the effective value of the interme-
diate frequency output voltage to the effective value of the RF input voltage, that is,
the conversion voltage ratio, also known as the conversion gain. A mixer with a
certain gain helps to suppress the noise of the subsequent stage circuit in the
receiving channel, and the design pressure of the power amplifier can be alleviated
in the transmitting channel.
At present, the mixer mainly has two structures: (1) A passive mixer with no
amplification effect only serves as a switch. The voltage-type zero-crossing passive
mixer has a gain of about 4 dB, and the non-zero-crossing passive mixer has a gain
of about +1.48 dB. Current-type passive mixers have better noise and linearity
performance than voltage types. (2) The active mixer converts the RF voltage into
a current through a first-level common source FET; the local clock signal controls the
switching transistor to output current; the down-converted intermediate/base fre-
quency current is converted into a voltage signal through the load. Active mixers
have higher gain than passive mixers. At the same time, due to the parasitic
capacitance effect, the feedthrough effect between the various ports of the mixer
needs to be emphasized in the design to enhance the isolation performance.

Frequency Synthesizer Design

The frequency synthesizer is a circuit used to generate the high-resolution and high-
stability clock signal by synthesis methods. At present, there are three main
implementations, i.e., the direct frequency synthesis, phase-locked loop (PLL)-
based synthesis, and direct digital synthesis. The PLL-based synthesizer is the
most common one today, which features high integration, low cost, high
performance, etc.
The primary characteristics of a frequency synthesizer contains tuning range,
frequency resolution, phase noise, and so on; the details are as follows: (1) Tuning
range, the output frequency ranges from minimum to maximum; (2) frequency
resolution, the minimum gap between two adjacent output frequencies; (3) switching
time, the time necessary for the loop to settle, when the output frequency is switched
from one to another; (4) phase noise, the ratio of noise power in 1 Hz bandwidth at a
certain frequency offset to carrier power; and (5) spurious tone, the undesired
discrete spectral component with a magnitude obviously higher than the noise floor.
736 P. Xiao et al.

Fig. 38.6 Sigma-delta fractional-N frequency synthesizer

The PLL-based frequency synthesizer includes the integer-N synthesizer and

fractional-N synthesizer. By adjusting the integer division factor, the former out-
puts a frequency that is an integer-N multiple of the reference frequency. While the
latter yields a frequency that is a fractional-N multiple of the reference frequency
by dynamically changing the division ratio, thus it is creating a fractional division
factor on average. To reduce the fractional spur of the fractional-N synthesizer,
nowadays the sigma-delta fractional-N frequency synthesizer has become a criti-
cally important architecture owing to the noise shaping function of the sigma-delta
technique. As shown in Fig. 38.6, the classical sigma-delta fractional-N frequency
synthesizer consists of a phase-frequency detector (PFD), charge pump (CP), loop
filter, voltage-controlled oscillator (VCO), programmable divider, sigma-delta
modulator, etc.
With the continuous progresses in IC technologies, novel techniques and circuit
topologies, such as all-digital PLL (ADPLL), multiplying delay-locked loop
(MDLL), injection-locked oscillator (ILO), sub-sampling phase detector (SSPD),
and so on, are advanced with enhanced performance in flexibility and portability of
the frequency synthesizer. Due to the rapid progress of the wireless communications
and radar technologies, the frequency synthesizers are developed toward higher
output frequency, larger tuning range, lower phase noise, lower power consumption,
and higher integration.

Radio Frequency Power Amplifier (RF PA) Design

A RF power amplifier (RF PA) is an amplifying circuit that increases the power level
of RF signal within a certain power range. It directly affects the performance of the
RF transmitting channel.
The main characteristics of an RF power amplifier are as follows:

1. Output Power: Total power of RF signal at load, which is output from RF power
amplifier, is named as output power, usually expressed in dBm. The dBm is the
logarithm of the RF signal power relative to 1 mW. The conversion
relationship is:
38 RF Integrated Circuit Design 737

PðmWÞ
PdBm ¼ 10lg ¼ 10lgPðmWÞ:
1mW
2. Efficiency: Efficiency is one of the key specifications of RF power amplifier. It is
usually characterized by two methods. One is the drain efficiency, which is
described as the percentage of output power to DC power, i.e.

Pout
η¼  100%
PDC
The other is power-added efficiency (PAE), which is described as the percentage
of power and increased power to DC power, i.e.

Pout  Pin
PAE ¼  100%
PDC
3. Linearity: Nonlinear distortion generated by RF power amplifier is expressed in
both amplitude and phase. Linearity is usually expressed by 1 dB compression
point and third-order intercept point.
4. Stability: Stability of RF power amplifier is determined by the S-parameters of RF
amplifier. When

1 þ jΔj2  jS11 j2  jS22 j2

K¼ >1
2jS21 jjS12 j

and Δ ¼ S11 S22  S12 S21 < 1, the RF power amplifier is unconditionally stable.

There are two types of RF power amplifiers, i.e., linear power amplifier (conven-
tional PA) and switching-mode power amplifier.
According to the different conduction angles of transistors, linear power ampli-
fiers are classified into Class A, Class B, Class AB, and Class C amplifiers,
respectively. The conduction angle of Class A amplifier is 360 with the efficiency
of less than 50%. The conduction angle of Class B amplifier is 180 with a higher
efficiency than that of Class A amplifier, but a poor linearity which shows a
crossover distortion. The conduction angle of the Class AB amplifier is between
180 and 360 with two-transistor push-pull method to avoid crossover distortion. It
has a better linearity and higher efficiency. The conduction angle of Class C
amplifier is less than 180 with the efficiency higher than Class A and Class B
amplifiers.
Switching-mode power amplifier is a kind of high-efficiency power amplifiers
whose transistors operate in switching mode. It can be classified into Class D,
Class E, and Class F amplifiers, respectively. Ideally, the voltage drop is 0 when
the switch is turned on, the resistance is infinite when the switch is turned off, and the
theoretical efficiency can reach 100%. Practically, the distortion of the switching
power amplifier is much larger resulting in serious restricts on its application.
Therefore, how to improve its linearity is drawing more attentions.
738 P. Xiao et al.

To date, RF power amplifiers are designed and manufactured using three main
processes: GaAs, SiGe, and RF CMOS. RF power amplifier in GaAs process is
mainly suitable for high power output applications and widely used in wireless
communication area. SiGe process is compatible with Si CMOS process, which is
helpful to realize integration of RF power amplifier and RF IC. RF CMOS process
can help realize higher integration and lower cost, but the performance of CMOS RF
power amplifiers is still behind GaAs ones; thus, currently, RF CMOS process is
mainly used for Bluetooth and Zigbee applications. In recent years, GaN has
received more and more attentions as a new type of material for manufacturing
high-power RF power amplifiers.

Radio Frequency Switch Design

The RF switch is a RF component that can conduct and cut off the RF signal path. Its
performance is mainly characterized by parameters such as isolation, operating
bandwidth, insertion loss, switching time, power capacity, input standing wave
ratio, and lifetime. A variety of different switch configurations can be constructed
depending on the switch selection path. Figure 38.7 shows three typical switch
configurations, including single pole single throw (SPST), single pole double
throw (SPDT), and single pole multiple throw (SPMT).
RF switches can be divided into electromechanical RF switches, solid state RF
switches, and micro-machined (MEMS) RF switches.
The electromechanical RF switch realizes the on/off control of the RF signal path
through the RF relay. It has the characteristics of low insertion loss, high isolation,
good antistatic discharge performance, and large power capacity, but its volume is
large, the speed is slow, and the life is short. And it is difficult to integrate with RF
circuits, mainly used in instrumentation, high-power multi-beam antenna
systems, etc.
Solid-state RF switches include diode RF switches and FET RF switches. The
diode RF switch is a two-port device. It is equivalent to a linear resistor for the RF
signal. The resistance is determined by the DC offset. When the bias is positive, the
impedance is small and the switch is turned on. When the reverse bias is applied, the
circuit is cut off and the impedance is large. The FET RF switch is a three-port device
that is controlled by the gate, including GaAs p-HEMT RF switch and CMOS RF
switch. Compared with the diode RF switch, the FET RF switch has a simple bias
circuit and easy integration.

Fig. 38.7 Schematic diagram

of the typical form of the RF
switch
38 RF Integrated Circuit Design 739

MEMS RF switches are divided into two basic types: capacitive and contact.
The capacitive switch uses an air bridge structure to adjust the capacitance to turn the
switch on and off. The contact switch uses a cantilever structure to control
the cantilever contact and disconnection state through an applied voltage to realize
the RF switch. MEMS RF switches have the characteristics of low insertion loss,
good linearity, and large bandwidth. At the same time, due to the conduction and
cutoff through micro-mechanical structure, the switching time is longer and the
service life is shorter.
In the specific application, according to the installation form, the RF switches can
be categorized into parallel switch, series switch and hybrid switch; while according
to the functions, RF switches can be categorized into on/off switch (single pole
single throw) and selection switch (single pole and multiple throw).
In early wireless communication and radar systems, electromechanical RF
switches were used, which were bulky and slow. In the early 1960s, diode RF
switches began used as RF transceivers and phase shifters, which effectively
improved the size and speed of RF switches, and became the mainstream technology
for replacing electromechanical RF switches. They are still used in systems such as
phased array radars. Around 1980, GaAs p-HEMT-based FET RF switches gradu-
ally replaced diode RF switches in low- and mid-power applications. In the late
1990s, with the development of CMOS technology, CMOS RF switch research and
development received more attention. In 2007, Infineon developed CMOS SOI RF
switch products. MEMS RF switches began to be researched around 2000. Due to
their unique advantages, the development prospects have been optimistic. However,
due to the problems of packaging and reliability, they have not been completely
solved.
Due to system integration with CMOS RF circuits and baseband circuits, the
CMOS RF switches will be more commonly used in RF system chips. MEMS RF
switches with process compatible with CMOS will be continuously developed. For
high power applications, GaAs p-HEMT RF switches and diode RF switches are still
used for a period of time.

Digital Radio Frequency Integrated Circuit (RFIC) Design

To support the ever-increasing levels of SoC integration and low cost required by the
consumer market, the RF circuit design has been progressed with the advanced
scaled CMOS nodes; at the same time, the traditional RFIC design methodology also
faces new challenges. Around the year of 2000, digital RF technology was advanced
forward, which transformed the continuous-time analog RF functionality into digi-
tally intensive or even all-digital implementations. Since the emergence of “digital
RF,” there has been discussion whether the RF transceiver can be implemented
all-digitally. The performance of some analog RF circuits, e.g., LNAs, off-chip
filters, and PA, can be improved or replaced by using digital aids; however they
are limited by the requirements for linearity, power consumption, interference
suppression, and the CMOS technology.
740 P. Xiao et al.

Frequency synthesizer is an RFIC that can be realized almost all-digitally. An

all-digital phase-locked loop (ADPLL) with system diagram illustrated in Fig. 38.8
includes digitally controlled oscillator (DCO), phase detection, loop filter, and
frequency control circuit. DCO generates the desired high frequency, and its function
is similar to that of VCO in traditional frequency synthesizer. Phase detection mainly
consisted of time-digital converter (TDC) and high speed counter, and its output is
compared with the control words, processed by loop filter and then the control words
for DCO are generated. The negative feedback loop exists inside the PLL which
maintain a stable output frequency of DCO.
Figure 38.9 illustrates an all-digital quadrature RF transmitter, in which both
front-end baseband and back-end PA are implemented digitally. In order to suppress

Fig. 38.8 System diagram of all-digital phase looked loop

Fig. 38.9 System diagram of all-digital quadrature transmitter

38 RF Integrated Circuit Design 741

Fig. 38.10 System diagram of digital RF receiver

far-out noise and repetition spectrum, the pre-distorted baseband signal is

up-sampled twice to a certain frequency. A two dimensional digital pre-distortion
(DPD) and look-up table (LUT) are developed in the digital front-end (DFE) to
restore digital power amplifier (DPA) linearity.
Figure 38.10 shows a digital receiver suitable for WiMAX (Worldwide Interop-
erability for Microwave Access), including Gm amplifier, sampling mixer and two
stages switch capacitor discrete-time filters and so on. For the consideration of noises
and out-of-band interference suppression, low noise amplifier (LNA) and surface
acoustic wave (SAW) are still implemented in the analog way.

References
1. T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edn. (Cambridge
University Press, 2012)
2. I.J. Bahl, Fundamentals of RF and Microwave Transistor Amplifiers (John Wiley & Sons, New
Jersey, 2009), pp. 1–16
3. Z.Q. Li, Z.G. Wang, RF IC and System Design (Science Press, Beijing, 2014) (Chinese book
series 4 of 5, ISBN 978-7-03-042254-5)
Power Integrated Circuit
39
Tianshen Tang, Hao Ni, and Xiaoyan Liu

Contents
Power Device and BCD Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Smart Power Integrated Circuit (SPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
Power Management Integrated Circuits (PMIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Energy Harvesting and Transformation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
AC/DC Converter and Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
DC/DC Converter and Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754

Abstract
This chapter dedicates to the introduction of the power integrated circuit (PIC),
including: (1) power device and BCD processes; (2) the definition of smart power
integrated circuit (SPIC); (3) power management integrated circuit (PMIC)
together with their circuit structures, development trends, and challenges;
(4) energy harvesting and transformation control concepts; (5) AC/DC converter
and driver; and finally (6) DC/DC converter and driver circuit structures.

Keywords
Power integrated circuit · Smart power integrated circuit · Power management
integrated circuits · Energy harvesting · Switch control · AC/DC converter and
driver · DC/DC converter and driver

T. Tang
Leapfive Technology Co., Ltd., Guangdong, China
H. Ni (*)
Semiconductor Manufacture International Corporation, Shanghai, China
e-mail: hao_ni@smics.com
X. Liu
Silicon Storage Technology Inc. (SST), Shanghai, China
Institute of Microelectronics, Peking University, Beijing, China

© Publishing House of Electronics Industry 2024 743

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_39
744 T. Tang et al.

Power Device and BCD Process

Power devices are devices for power processing. According to the difference of their
carriers, power devices can be classified into bipolar and unipolar devices, including
power diode, giant transistor (GTR), thyristor, gate turn-off transistor (GTO), and
insulated gate bipolar transistor (IGBT). A representative device of the unipolar type
devices is the double-diffused MOSFET (DMOS). Based on the differences of the
materials, devices can be categorized into silicon-based and wide bandgap
material–based groups, e.g., silicon carbide (SiC) and gallium nitride (GaN) [1].
Other power devices are introduced in detail in Chap. 6. We briefly introduce IGBT,
DMOS, and wideband devices in this chapter.
Formed by the bipolar junction transistor (BJT) and the metal oxide silicon field
effect transistor (MOSFET), an IGBT transistor is a composite fully controlled by
voltage-driven device. It is characterized by its high input impedance, low conduc-
tion voltage, and domination in the market of medium voltage systems above 600 V.
DMOS device is of dual-diffusion type, i.e., it is doped twice at the source and
drain regions, with high concentration at first time and low concentration at the other
time. Compared with IGBT, DMOS device has higher switching frequency. Based
on the device structures, the devices can be classified into vertical double-diffused
MOSFET (VDMOS) and lateral double-diffused MOSFET (LDMOS). VDMOS is a
voltage-controlled device. Due to its poor compatibility with CMOS devices, its
development is slow. On the other hand, LDMOS has good compatibility with
CMOS devices, hence it has been widely used in RF power circuits.
The wide bandgap materials SiC and GaN have the characteristics of wide
bandgap width, high saturation drift velocity, and high critical breakdown electric
field, which are ideal materials for manufacturing high-power, high-frequency, high-
voltage, high-temperature, and radiation-resistant electronic devices [2]. As the
improvement of SiC single-crystal growth technology and GaN epitaxial technol-
ogy, the development and application of wide bandgap power devices are pro-
gressing rapidly [2, 3]. Wide bandgap material power devices are mainly used for
discrete devices. Since 2009, GaN driven integration trend has become a hot topic
industry wide [4].
Before the 1980s, the bipolar process was the mainstream process for manufactur-
ing power devices, and bipolar devices had characteristics of high accuracy and low
integration. In comparison, CMOS devices had features of high integration, low
power consumption, and simple logic control. Therefore, the integration of bipolar-
CMOS can complement the merits of the two technologies with each other. On the
other hand, DMOS devices can provide high power without DC drive, and are
compatible with CMOS technology. Moreover, its advantages of fast switching
speed, high input impedance, good thermal stability, and strong reliability make it
widely used in high-speed switches. Hence, BCD (bipolar-CMOS -DMOS) tech-
nology emerged. BCD technology refers to the integration of the bipolar, CMOS,
DMOS, resistor, capacitor, and other devices on the same process platform. The
advantages of three types of active devices, namely the high precision of bipolar
devices, the high degree of integration of CMOS devices, and the high power
39 Power Integrated Circuit 745

processing capacity of DMOS devices, are combined in the BCD process, making
BCD process widely used.

Smart Power Integrated Circuit (SPIC)

Integrating high-voltage power devices, control circuits, protection circuits, detec-

tion and diagnosis circuits, peripheral interface circuits, and signal processing
circuits on to the same chip forms power integrated circuit (PIC) [4]. Compared to
discrete devices, PIC has more advantages in reliability, stability, power consump-
tion, volume, weight, and cost. In the past, the power IC is usually divided into high-
voltage power IC and intelligent power IC groups [5]. The chips integrating 200 V
and above power devices and control circuits are called high-voltage power inte-
grated circuits [1]. However, with the continuous development of PIC, it is difficult
to distinguish them in terms of working voltage and device structure, so they are now
collectively referred to as smart power integrated circuits (SPIC). In the late 1970s,
intelligent power integration technology emerged. BJT and GTO were popular
power devices at that time. However, their requirement for large driving current
and sophisticated control circuit structure limited the development and progress of
power integrated circuits at that time. In the 1980s, gate-controlled power devices,
such as power MOS and IGBT, appeared. Such gate-controlled devices have the
characteristics of high input impedance and low driving power consumption [5],
solving the problem of large driving current required by previous devices. However,
the complicated system structure design and high process cost still limit the appli-
cation scope of PIC in that era. Since the 1990s, as the continuous improvement of
PIC design and technology, the cost-performance ratio has been gradually improved;
it has led to its application in automotive electronics, flat panel display, motor drive,
motor control, power management, and other aspects.
Power control, sensing and protection, and intelligent interface are the three main
functional modules of SPIC [1]. The power control module consists of switching
power devices and driving circuits, which are mainly used for terminal power
processing. The sensing protection circuit is mainly used to protect various abnormal
situations, such as overcurrent, overvoltage, undervoltage, overtemperature, short
circuit, and open circuit, to improve the stability and service life of the chip [1]. The
intelligent interface circuit is implemented by logic CMOS, which is mainly used to
process instructions and control the response of power devices, and meanwhile
transmit the working status, load information, and other detected information back
to the system. As the development of BCD technology, interface circuits can
integrate storage modules, RF modules, microcontroller unit (MCU) and other
multifunctional modules onto a chip, which results in the broad adoption of such
power devices in portable structures and intelligent applications, such as wearable
devices, medical devices, wireless transmission, and Internet of Things (IoT) [6].
From the perspective of the development trend of power semiconductor devices
and integration technologies, the primary technical challenges at present are making
power devices more energy efficient, higher working frequency, and higher working
746 T. Tang et al.

voltage range, and optimizing and improving integration technologies with respect
to the scale of integration, intelligence, and reliability [1].
Therefore, the main research tasks of PIC might include the following subjects:
developing BCD technology with higher voltage, power, and density for higher yield
and lower cost [1]; exploring novel device structures with lower power consumption
and suitable for denser integration; developing more efficient PIC control methods;
developing PIC devices operating stably at high temperature; and developing hori-
zontal power devices with self-protection feature and being controlled by high-
current high-speed MOS transistors. The critical object for PIC development is to
integrate low-voltage circuit with multiple high-voltage power devices on to the
same silicon die or a device module so that it has system functions and realizes the
integration of the monolithic power system [1].

Power Management Integrated Circuits (PMIC)

The major functions of PMIC are to transform, distribute, monitor, and manage other
electric energy. Having the advantages of convenient to use, low cost, small size,
excellent performance, and high reliability [7], PMIC is widely used in mobile
phone, computer, consumer electronic products, power supply, charger, and other
applications.
According to the differences of internal structures, PMIC is mainly classified into
linear voltage regulators, charge pumps, and switching voltage regulators as com-
pared in Table 39.1.
A linear regulator controls the transistor working in the linear region [7] via
comparing to the reference voltage to the voltage generated by the resistance voltage
divider [7], so that the input voltage is regulated by the transistor in the linear region,
producing the output voltage required by the application. The characteristics of the
linear regulator are: the transmission transistor works in the linear region, without an
on-off jump, limited to step-down conversion. Linear regulators mainly include
traditional linear regulators and low dropout (LDO) regulators [7]. The traditional
linear regulators use BJT as power transistors and adopt the following mode of
source; on the other hand, the LDO regulators use mainly PMOS transistors and
adopt the mode of the common source connection. The basic structure of LDO is
shown in Fig. 39.1.

Table 39.1 Comparison of voltage management circuits

Parameter Linear voltage regulators Charge pumps Switching voltage regulators
Regulation type Buck Buck, boost Buck, boost
Noise level Low Medium High
Efficiency Low Medium High
Power capability Medium Medium High
EMI level Low Medium High
39 Power Integrated Circuit 747

Fig. 39.1 The basic structure

of LDO

Fig. 39.2 Dickson pump

circuit structure

The following specifications need to be considered in the design of LDO:

difference voltage between the input-output voltages, maximum/minimum load
currents, linearity/load instantaneous voltage response, transient recovery time,
zero/pole, phase margin, and static operating point [7].
The charge pump, also known as switched capacitor regulator, provides voltage
conversion using capacitor and several switches [7]. Unlike linear regulators, the
charge pump can produce an output voltage higher than or less than the input
voltage; the regulator can be used as a booster or step-down regulator [7]. In the
design of the charge pump, the on-off is usually realized by MOS transistors, whose
size is related to the switching frequency. The higher the frequency is, the wider the
channel width of these transistors. However, with the increase of transistor size,
dynamic power consumption also increases due to the increase of gate oxygen
capacitance [7]. Therefore, a trade-off between the switching frequency and
the energy efficiency of the switching capacitor regulator needs to be made [7].
Figure 39.2 shows a typical Dickson pump structure, in which PMOS transistors M1,
M2, M3, and MOUT are on and off transistors, and CT1, CT2, CTN, and CSTORE are
charge storage capacitors, of which special attention should be paid to BULK
connections.
Switching regulator (SWR) is widely used in power management systems for its
high efficiency, high driving capability, and adjustable output voltage. Switch
regulators are characterized by the facts that the switch must be fully switched on
or off for any given cycle [7]; the regulator must be equipped with one or more
similar inductive and capacitive energy storage elements [7]; the regulator has
multiple topological structures (buck, boost, buck-boost, etc.); and the efficiency
of SWR is almost 100% when the circuit elements are ideal ones. The switching
748 T. Tang et al.

voltage regulator adopts a negative feedback control loop, as shown in Fig. 39.3. The
block diagram in the figure is pulse width modulation (PWM), which can be replaced
with pulse frequency modulation (PFM), phase control (PWM-PFM), and other
methods.
According to the differences in energy storage modes, SWR can be classified into
two categories. The first category is nonisolating switch voltage stabilizer, which
uses inductance to store energy and has no isolation between output power and input
power [7]. Its advantages are its simple structure, low cost, and wide range of output
voltage regulation. Its basic structure is shown in Fig. 39.4 [8]. The second category
is isolation SWR. The basic structure is shown in Fig. 39.5 [8]. It uses a transformer
to store energy and achieve the physical isolation between the input and output ends.
The advantage of isolated SWR is that it reduces the mutual interference between the
output power supply and the input power supply, and improves the antinoise ability.
Noise and ripple suppression are two key factors to be considered in PMIC
design. The noise is usually the sharp pulse produced by the turning on or off the
transistors. The fluctuation of DC stable voltage usually causes ripples [9].

Fig. 39.3 Block diagram of

voltage regulator of switch
power supply

Fig. 39.4 Nonisolated

switch voltage regulator
structures

Fig. 39.5 Isolated SWR: forward/back topology comparison

39 Power Integrated Circuit 749

As the development of information technology, the market demands for high

performance, low power consumption, portable, and other devices are increasing,
which promotes the growth of PMIC [9]. At the same time, due to the continuous
improvement of integrated circuit design capability and increasing maturity of
process, PMIC begins to advance toward miniaturization and intelligence, high-
energy efficiency and precision, low power consumption and low working
voltage, etc.

Energy Harvesting and Transformation Control

Energy harvesting is to obtain energy from the environment through energy

harvesting technology. In essence, through photovoltaic, thermoelectric, piezoelec-
tric, electromagnetic, and other effects, the energy existing in a broad range in the
environment, such as light energy, thermal energy, wind energy, mechanical energy,
and so on, is transformed into electrical energy that can be used [10]. The core
meaning of energy harvesting is that it can provide energy continuously without
consuming additional fuel and materials [10].
Energy levels generated by different energy sources are shown in Fig. 39.6.
Currently, there are three important energy sources that can be used for energy
harvesting: electromagnetic radiant energy, thermal energy, and mechanical
energy [10].
Electromagnetic radiant energy includes solar energy and radiofrequency radiant
energy. Solar energy conversion into electricity, namely photovoltaic power gener-
ation, is a mature large-scale energy collection technology [10]. Radiofrequency
radiation can be the power supply for all kinds of radiofrequency identification
(RFID) card and transmit information, has been widely used in public transport,
identification [10], etc.
A switch control circuit consists of two parts, voltage regulation and protection.
The heat energy that can be collected mainly includes temperature gradient and heat
flow [10]. The basic principle of thermoelectric batteries or thermoelectric generators
is to use the thermoelectric effect to convert heat energy into electricity through
temperature difference [10]. However, thermal gradients greater than 10  C at small

Fig. 39.6 Energy levels of different energy sources

750 T. Tang et al.

sizes (e.g., 1 cm3) are hard found [10]. As a result, the low efficiency of the micro-
thermoelectric generator limits its application range.
Mechanical energy includes all the energy produced by vibration, shaking,
rotation, etc. There are three types of vibration collectors: electrostatic, piezoelectric,
and electromagnetic [10]. The working principle of an electrostatic collector is
mainly based on variable capacitance, which changes the distance or relative area
between the plates through external mechanical vibration, so as to change the
capacitance, and then convert the vibration energy into electric energy [10]. The
piezoelectric collector works through the piezoelectric effect of piezoelectric mate-
rials [10]. When mechanical stress is applied to the piezoelectric material, charges
are generated on the two plates of the material. On the contrary, when a voltage is
applied to the two plates of the piezoelectric material, the material will generate
internal mechanical stress [10]. The electromagnetic collector works on the basis of
Faraday’s law of electromagnetic induction. A relative movement of the permanent
magnet and the coil to each other results in induced voltage in the coil [10].
The following basic requirements need to be considered. The modulator is a
closed-loop system. To meet the required stability of the output voltage, the gain of
the control circuit loop must be sufficiently high, so to assure the input voltage, load
and temperature changes maintained in a certain range. Other requirements of
dynamic response speed and range, etc. also need to be considered [7]. This requires
the use of multiple feedback techniques and appropriate calibration circuits. In
addition, soft start and overcurrent protection, as well as overvoltage protection
functions should also be considered [7]. If necessary, the feedback input needs to be
isolated from the output of the control circuit.
Fig. 39.7 is a schematic diagram of the traditional series transformation control
system. The first stage converts the collected energy into DC energy for storage
through AC/DC and DC/DC regulators, and the second stage converts the stored
energy to the load by a DC/DC regulator, providing stable working voltage and
current. Because the input energy is converted two times, the energy conversion
efficiency is low [7].
Fig. 39.8 is a schematic diagram of the parallel transformation control system.
The primary path of the parallel structure directly converts the energy through the
AC/DC and DC/DC voltage regulator to load, work voltage is generated at load. The
slave path transforms the redundant energy into DC energy for storage and provides
the DC energy to load side through DC/DC voltage converter when needed. This is

Fig. 39.7 Schematic diagram

of series energy transformation
control system
39 Power Integrated Circuit 751

Fig. 39.8 Schematic diagram

of parallel energy transfor-
mation control system

why the parallel transformation can improve the power conversion efficiency while
keeping the energy storage function at the same time [7].

AC/DC Converter and Driver

The energy harvested is usually alternate current (AC) signal, so the signal must be
converted to direct current (DC) signal before it can be utilized or stored.
AC/DC converter converts the AC signal into DC. It is bidirectional in power
transportation [11]. In AC to DC transformation where the current flows from source
to the load, it is called rectification; in DC to AC transformation, where the current
flows from the load to the power supply, it is called active conversion [11]. After
50/60 Hz AC current is inputted into AC/DC regulator, it needs to be rectified and
filtered; high frequency, high voltage, and large current of filtering limit the progress
of AC/DC regulator to be modularized [11].
There are two types of AC/DC regulator, one-stage regulator and two-stage
regulator. The two-stage power supply consists of power factor correction (PFC)
and DC/DC regulator, as shown in Fig. 39.9a. The PFC control and output voltage
regulator are separated, and there is a capacitor for energy storage between the two
stages. The two-stage power supply is widely used in high-power applications for its
high reliability, while the energy efficiency is not high. The one-stage power supply
is shown in Fig. 39.9b, which also includes PFC and DC/DC voltage regulator, but
combined together there is no energy storage capacitor between them. The one-stage
power supply has high energy efficiency but low reliability [12]. In industry, the
two-stage AC/DC architecture is mature and standardized technology from both
aspects of design and manufacturing. While the modularization progress of
one-stage AC/DC architecture is limited due to complex technical and fabrication
problems [13].
A rectifier converts AC signal to D. There are mainly three types of rectifiers,
half-wave rectifier, full-wave rectifier, and bridge rectifier. Among them, the bridge
rectifier is the most commonly used. The bridge rectifier uses four rectifier diodes.
752 T. Tang et al.

Fig. 39.9 Two-stage and one-stage AC/DC topology

Fig. 39.10 Two-stage AC/DC voltage regulator circuit structure

Fig. 39.11 Single-stage HB-LED driver circuit structure diagram

Connecting D1, D2, D3, and D4 as shown in Fig. 39.10 is a full-wave rectifier [12].
After an AC power supply passes through the rectifier, the output needs to be
reshaped by a PFC to maximize the active power absorbed by the load [13]. The
PFC structure is shown in the middle of Fig. 39.10, which generally consists of an
inductor LR, a diode D5, and a power switch S1, followed by an energy storage
capacitor Cs. DC/DC regulator architecture will be discussed in detail in Section 6.
High-brightness light emitting diode (HB–LED) driver bases on high-efficiency
AC/DC voltage regulator. Because of its long operation lifetime, green environmen-
tal protection, high luminous efficiency, and flexibility of color mixing and dimming
control, HB-LED is widely used in homes, offices, and street lighting [14]. The
single-stage HB-LED driver circuit structure is shown in Fig. 39.11 [14]. Besides the
39 Power Integrated Circuit 753

first stage an AC/DC rectifier, the whole circuitry consists of power switches S1 and
S2, inductors L1 and L2, magnetic coils N1 and N2, diodes D5–D8, and energy
storage capacitor.

DC/DC Converter and Driver

In a power system, firstly an AC/DC is used to convert AC signal into DC signal.

Then a DC/DC is needed to convert the obtained DC signal to the specific DC
voltage required by each circuit module in the subsystem. Advanced power man-
agement techniques generally adopt multiple on-chip voltage domains to effectively
leverage the balance between latency and power consumption [7]. The system frame
structure of DC/DC regulator is shown in Fig. 39.12. Output Uo of DC/DC voltage
regulator with input Uin are multiplied by k, where k is the gain factor. There are
three basic types of DC/DC: buck, boost, and buck-boost.
The three basic topologies of DC/DC are shown in Fig. 39.13. Figure 39.13a is a
buck regulator; Fig. 39.13b is a boost regulator; and Fig. 39.13c is a buck-boost
regulator, which is a combination of buck and boost. All the three architectures are
composed of switches S1 and S2, inductor L, and capacitor COUT.
A driver circuit is located between the main circuit and the control circuit, which
is mainly used to amplify the signal of the control circuit so as to drive power devices
[7]. After receiving the input signal, the drive circuit converts the signal voltage level
to control the switching on or off of the power device according to the control target
requirements. For example, for a semicontrolled device, the circuit only provides a
turn-on control signal; for fully controlled devices, it is necessary to provide two
different control signals, namely on and off, as well as electrical isolation [7].

Fig. 39.12 Block diagram of

DC/DC voltage regulator

Fig. 39.13 Basic topologies of DC/DC

754 T. Tang et al.

Fig. 39.14 Gate driver

circuit diagram

Fig. 39.15 Boost gate driver

structure based on DC/DC
voltage regulator

Gate driver is the interface circuit between the microprocessor (MCU) and power
switch (IGBT, MOSFET) [15]. The schematic diagram of a gate driver is shown in
Fig. 39.14 [15]. It consists of diode Don/Doff, RG, on/RG, off, and the power transistor.
In recent years, because the utilization of gate/source capacitor for energy storage
can improve the efficiency of Gate Driver, Resonant Gate Drivers (RGD) [16]
technology has been widely studied. However, the complexity of RGD architecture
makes it difficult to control [16]. Accordingly, bidirectional gate driver (BGD)
comes out. A DC/DC regulator based boost gate driver structure is shown in
Fig. 39.15; it consists of three small size transistors M1, M2, M3, energy storage
components Cs and Ls, and power transistor Mp. Gate of Mp is driven by the gate
driver circuit [17].

References
1. S. Weifeng et al., Status and prospect of development of power semiconductor devices and
power integration technology [C]. Science China Inf. Sci. 42(12), 1616–1630 (2012)
2. Z. Bo et al., Gallium nitride power semiconductor device technology [C], research and progress.
Solid State Electron. 30(1), 1 (2010)
3. H.-S. Choi, Improvement of turn-off energy loss (Eoff) variations by low Mg doping in p-GaN
gate power devices. IET J Mag. 53(3), 196–198 (2017)
4. Z. Bo, L. Xiaodong, L. Zhaoji, Electric Field Optimization Technology of Power Semicon-
ductor Devices (University of Electronic Science and Technology Press, Chengdu, Sichuan,
China, 2016)
5. H. Hui et al., The Theory and Design of Power Integrated Circuit Technology (Zhejiang
University Press, Hangzhou, Zhejiang, China, 2011)
6. T.-K. Chien, Low-power MCU with embedded ReRAM buffers as sensor hub for IoT applica-
tions, [J]. IEEE J. Emerg. Selected Topics Circuits Syst. 6(2), 1 (2016)
39 Power Integrated Circuit 755

7. K.-H. Chen, Power Management Techniques for Integrated Circuit Design (Wiley, Singapore,
2016)
8. C. Xin, Study on high frequency and high voltage pulse for electric dust removal, Ph.D.
Dissertation (Dept. Environ. Sci., Anhui U. of Sci. & Tech., Huinan, Anhui, China, 2014)
9. Satoshi, Fundamental study of influence of ripple noise from DC–DC converter on spurious
noise of wireless portable equipment [J]. IEEE J. Mag. 31, 2111–2119 (2016)
10. W. Peihong, Research on micro-electromagnetic vibration energy collector based on MEMS
technology (Shanghai Jiaotong University, Shanghai, China, 2010), pp. 1–8
11. E. Salman, High Performance Integrated Circuit Design [ISBN: 978–0071635769], 2012
12. C. Li, X. David, A family of enhanced ZCS single-stage single-phase isolated AC-DC converter
for high power high voltage DC supply. IEEE Trans Ind Electron. 64(5), 3629–3639 (2017)
13. S. Nigsch, J. Marquart, K. Schenk, Low Cost High Density AC-DC Converter for LED Lighting
Application (PCIM Europe, Nuremberg, Germany, 2016)
14. I. Castro et al., Single-stage AC/DC dual inductor BCM current-fed push-pull for hb-led
lighting applications [C], in Energy Conversion Congress & Exposition, (2017), pp. 1–8
15. P.K. Prasobhu et al., Gate driver for the active thermal control of a DC/DC GaN-based converter
[J], in Energy Conversion Congress & Exposition, (2017), pp. 1–8
16. Z. Zhang, A high-frequency dual-channel isolated resonant gate driver with low gate drive loss
for ZVS full-bridge converters [J]. IEEE Trans. Power Electron. 29(6), 3077–3090 (2014)
17. Y. Juzheng, Gate-drive circuit with efficient energy recovery based on DC/DC converter
[J]. Electron. Lett. 52(11), 952–954 (2016)
Design of Processors
40
Xiaolang Yan, Jianyi Meng, and Zhijian Chen

Contents
Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
Instruction Set Architecture (ISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
Data Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
Multiple Instruction Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Single Instruction Multiple Data (SIMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Multithreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
Multicore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
Manycore Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Memory Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Graphics Processing Unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

Abstract
Central processor unit (CPU) is considered as the pearl on the crown of IC
industry. It is an important driving force of Moore’s law in the past decades.
This chapter starts with the introduction of some basic concept of the processor,
e.g., instruction set architecture (ISA), data path, control logic, coprocessor,
pipeline, multi-issue, single instruction multiple data, multithread, multicore,
manycore, memory architecture. It also introduces several common types of
processor, e.g., digital signal processor (DSP) and graphics processor unit (GPU).

X. Yan · Z. Chen (*)

Institute of VLSI, Zhejiang University, Hangzhou, China
e-mail: chenzj@vlsi.zju.edu.cn
J. Meng
Department of Microelectronics, Fudan University, Shanghai, China

© Publishing House of Electronics Industry 2024 757

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_40
758 X. Yan et al.

Keywords
Processor · Instruction set architecture (ISA) · Pipeline · Multicore · Memory
architecture

Processors

The processor is a very large scale integrated (VLSI) circuit, and is the core chip
responsible for computation and controlling. The most commonly used processor is
the central processing unit (CPU), whose main functions are to interpret and execute
computer instructions, perform data operations, or control peripherals. As shown in
Fig. 40.1, CPU, memory, and I/O device are three core components of an electronic
computer.
The instruction system is a basic technology applied to the design of processors,
which defines the interface between software and hardware, and also determines the
application ecosystem of processors. The hardware components of a processor
include datapath and control logic; and the fundamental operation of a processor is
made up of four (4) basic steps, i.e., instruction fetching, decoding, execution, and
write back. In order to improve the computing capability of processors, the instruc-
tions are usually executed in a pipelined manner. Technologies were adopted to
improve the instruction- and data-level parallelism of the processors over multi-issue
technology and single instruction multidata technology. In order to improve the
parallel processing capability at the transaction level, most of current processors
adopt a multicore architecture, that is, a chip contains multiple processing cores.
Manycore processors are specialist multicore processors designed for high degree of
parallelism. In addition, different forms of processors such as digital signal pro-
cessors (DSP) and graphics processing unit (GPU) have also been developed for
specific applications. With the development of IC technology and the continuous
scaling of technology, the leakage current of transistors has gradually increased, and
the power consumption density per unit area has been continuously increased.
Therefore, the reduction of power consumption has become a major challenge in
the design of processors, which is called “Power Wall” problem. Besides, the

Fig. 40.1 Core components of traditional computer and CPU chip

40 Design of Processors 759

processor’s processing capability is heavily dependent on the memory speed, but the
increase in memory speed cannot keep up with the increase in processor speed. Thus,
memory has become a limitation to the performance of processors, which is called
“Memory Wall” problem.
The processors may be divided into five categories as per applications, i.e.,
supercomputer processors, server processors, desktop PC processors, mobile smart
terminal processors, and embedded system processors. Each of the above areas has
established its own ecosystem of software and hardware. (1) The supercomputer
processors mainly include x86 processors of Intel and AMD, POWER and PowerPC
processors of IBM as well as SPARC processors of Fujitsu. NVIDIA’s GPUs and
Intel’s PHI accelerators have also been applied to the supercomputers. Chinese
supercomputer processors include Sunway processors researched and developed
by Shanghai High-performance IC Design Center and FeiTeng processors by
National University of Defense Technology, which have been respectively applied
to “TaihuLight” and “Tianhe” series of supercomputers. (2) The server processors
focus on computing capability of a single chip. Currently, such server processors
mainly include POWER processors of IBM and x86 processors of Intel/AMD. In
recent years, ARM has been also endeavoring to develop server processors. (3) The
desktop PC processors pay more attention to computing capability and cost, and are
now dominated by x86 processors of Intel and AMD. Shanghai Zhaoxin Semicon-
ductor Co., Ltd. in China has secured the ability to develop x86 processors. (4) The
mobile intelligent terminal processors, also called application processors (AP), are
widely applied to smartphones, tablet PCs, and smart TVs, which focus on energy
efficiency, and are now mainly dominated by ARM. International companies
engaged in developing AP based on ARM architecture include Qualcomm,
Samsung, and the like, while Chinese companies engaged in R&D of such pro-
cessors include Hisilicon, Unisoc, MediaTek, Datang Semiconductor, and the like.
(5) Embedded processors are widely applied to a variety of embedded systems as
microprocessors and microcontrollers. Such processors are diverse in forms and
usually embedded in the form of SoC, whose processing capability differs depending
on market demands, and have such technical features as low cost and low power
consumption. The international mainstream embedded processors are CPUs based
on ARM, MIPS, Tensilica, and SPARC architectures. Chinese mainstream embed-
ded processors are CK series of CPUs developed by Hangzhou C-SKY Micro-
systems and CPU products developed by Suzhou Guoxin through introduction of
certain technologies from Motorola and IBM PowerPC.
The 4004 processor launched by Intel in 1971 was the first processor in the world.
After more than four decades of development, the processors have evolved from
4 bits to 64 bits, with their frequency from MHz to GHz, and their structure from
single-stream structure to multithread structure and their architecture from single-
core architecture to multicore and manycore architectures. The processor technolo-
gies based on Von Neumann architecture appears maturing. The development
tendency of such traditional processors based on Von Neumann architecture is
mainly to develop more efficient processor products in combination with more
advanced technologies. Quantum computer is a research focus in computer field in
760 X. Yan et al.

recent years, and is a new generation of high speed computer based on the laws of
quantum mechanics. Thanks to multibit parallel processing capabilities of quantum,
quantum computers will contribute to huge improvements in computing capability.
Recently, the new processor architecture for brain-like computation has gradually
entered the public’s field of vision and has drawn a widely public attention by virtue
of its higher processing efficiency than that of Von Neumann architecture based
processors in such fields as deep learning of artificial intelligence, and is expected to
achieve important applications.

Instruction Set Architecture (ISA)

Instructions are machine languages that can be read and understood by the pro-
cessors, and can define a sequence of commands understood and executable by
computer hardware, and are ultimately run on the processors. The instruction set,
also called instruction system, is the interface between software and hardware, and
includes not only all commands supported by the processor, but also a sequence of
specifications necessary for complete operation of a processor such as instruction
format, operand type, addressing mode, programming model, memory architecture,
interrupts, and exceptions. Different processor hardware may be designed for the
same instruction system. The instruction set architecture (ISA) determines the
ecosystem of the upper application software. The more plentiful the application
software ecosystem is, the more developers will enrich the application software
ecosystem. The instruction set architecture is often referred to as the instruction
architecture. In designing a processor, the unity of instruction architecture is con-
ductive to the accumulation of software ecological resources. Processor designers
can design processor hardware with different performance based on the same
instruction architecture so as to achieve software compatibility during constant
hardware upgrades as shown in Fig. 40.2. All desktop processors manufactured by
Intel are compatible with x86 instruction set.

Fig. 40.2 Software compatibility and hardware optimization based on the same instruction
architecture
40 Design of Processors 761

Basic instructions of processors usually include three basic categories, i.e., data
processing, arithmetic operations, and program flow control. (1) The main functions
of data processing instructions are to transmit and prepare for operands and com-
puting results. (2) The main functions of arithmetic instructions are to perform data
operations, including arithmetic, logic, bit operations, comparisons, etc. (3) The
main functions of program flow control instructions are to implement the jump of
the program, and typical control flow instructions include branch instructions, jump
instructions, and the like. The instruction format refers to the binary description of
the instruction and is also known as the machine code. Usually, a machine code
includes several typical fields, i.e., operation code fields, operand fields, and imme-
diate fields. Operand fields are used to indicate the data width of the operand during
the computing process. Currently, the common operand widths are 8 bit, 16 bit,
32 bit, and 64 bit, which correspond with character, short integer, integer (single
precision floating point) and long integer (double precision floating point), respec-
tively, in C language. The maximum operand (data) width supported by the proces-
sor hardware is also typically defined as the processor’s processing width. For
example, a processor that supports the computing of up to 64-bit operand is often
referred to as a “64-bit processor.” The programming model is a general term for all
the hardware resources that software designers have an access during interaction
with hardware, and usually includes general-purpose register resources, control
register resources, interrupts and exceptions, storage space resources, and the like.
The common instruction systems include complex instruction set computer
(CISC) and reduced instruction set computer (RISC), which are often referred to
as complex instruction set and reduced instruction set, respectively. The CISC
processor is characterized by its powerful single instruction, which can contain
multiple operations. In addition, the instruction length of the CISC processor, as a
variable length instruction system, is usually not fixed. In the past, instructions were
usually designed to conduct complex operations due to high storage costs, and such
processors usually adopted CISC architectures. The RISC processor is characterized
by its simple function of a single instruction, which generally contains one operation
only, simplified design of processor hardware, and optimization of compiler. The
RISC processor has a fixed instruction length. The current mainstream x86 archi-
tecture is based on CISC instruction system with strong computing capabilities and
sound compatibility and has been widely applied in such fields as supercomputers,
servers, and personal computers. The ARM architecture is based on RISC instruction
system with better energy efficiency and low hardware design cost, and is widely
used in the embedded field.
After nearly four decades of development, the instruction systems supporting the
basic functions of the processor have been matured. A variety of instruction archi-
tectures have established monopoly in the segments of applications. The instruction
systems will be developed further in future by integrating more specific instructions
for new applications. Intel has added multimedia, virtualization, and security-related
extended instruction sets to x86, and AMD has added a new instruction architecture
for 3D and heterogeneous computation. Besides, ARM has also added
corresponding extension instructions as to multimedia, security, graphics, etc. for
762 X. Yan et al.

the embedded field. In the future, x86 instruction architecture is expected to continue
to enjoy market dominance in such fields as high-performance computation, servers,
and desktops; the ARM and other RISC architectures will continuously dominate in
the mobile phone and embedded systems with low power and low cost.

Datapath

Datapath, also known as data channel, is one of core circuits of a processor and is
responsible for data storage, transmission, computation, etc. Characterized by its
regular circuit structure and single function, it is usually a critical path in propagation
delay in processor circuits, i.e., the bottleneck to improve processor frequency. The
datapath performs data operations under the control of the control logic, as shown in
Fig. 40.3. The common datapath consists of memory (instruction memory and data
memory), register file, arithmetic and logic unit (ALU), multiplier and divider
(MD) unit, floating-point unit (FPU), and load store unit (LSU).
Instruction memory and data memory are memory units in a processor that store
instructions and data, respectively. The instruction memory includes read only
memory (ROM), flash memory (NAND, NOR), static random access memory
(SRAM), and dynamic random access memory (DRAM). The data memory requires
real-time read/write operations, and is usually embedded in the form of SRAM
and DRAM.
The register file, as the main datapath of a processor, is used to store the operands
during execution and the result written back after execution. The register file is a
high-speed memory unit implemented by registers or flip-flop-based circuit to cache
the most frequently used data during program execution.
The arithmetic and logic unit (ALU) is a circuit intended for arithmetic and logic
operations and is the most basic in a processor. Starting with an 8-bit microprocessor,
the ALU is an important part of the processors. Modern CPUs, DSPs, GPUs, and
other types of processors all contain different types of ALUs.
The multiplier and divider unit (MD) is the execution unit responsible for
multiplication and division. In modern processors, unsigned and signed multiplier

Fig. 40.3 Datapath and control logic

40 Design of Processors 763

and divider operations are generally implemented in instruction set, which will be
executed uniformly within the multiplier and divider unit. In terms of circuit
implementation, the multiplier and divider unit includes a multiplier and a divider.
The multiplier is the critical path of a processor. In order to speed up the computing,
the Booth structure, also known as the Booth’s multiplier, is usually adopted.
The floating-point unit (FPU) is a dedicated module that handles floating-point
operations in a processor. Floating-point numbers provide a larger range of values
and higher data precision than integers. In terms of the type of operation supported,
the floating-point unit mainly implements the operations specified in the IEEE-754
protocol, including addition, subtraction, multiplication, multiplication and accumu-
lation, division and square, comparison, data format conversion, and the like. The
circuit scale and design complexity of floating-point units are higher than those of
other datapath units.
The load-store unit (LSU) is a hardware module responsible for data exchange
between the processor and the data memory (outside the processor). The data from
memory needs to be accessible during the running of the processor, that is, to execute
load instruction and obtain data from the memory and put such data into the
processor, and to execute storage instruction and put the data in the processor to
the memory outside the processor. If the data cache is implemented in the processor,
the load-store unit is also responsible for data access and interaction with the cache.
Usually, the static random access memory (SRAM) is adopted for the cache. Given
the cost constraints, at present, high-performance CPUs are usually designed with a
cache of up to 16 MB, and embedded CPUs are usually designed with a cache of up
to 64 KB.
The main technical indicator of datapath processing capability is the width of
arithmetical data. The first commercial processor, the Intel 4004, was 4 bit, and the
subsequent Intel 8008 was 8 bit, and later, the processor evolved from x86 architec-
ture to 32-bit architecture, and is now 64 bit. Current supercomputing, server, and
desktop processors are 64-bit and 32-bit compatible. The mobile application pro-
cessor has been 32 bit for a long term before entering the 64-bit era around 2015.
Given the continued decrease of costs and power consumption of transistors, current
embedded processors are gradually evolving from 8-bit/16-bit data width to 32-bit
data width.

Control Logic

The control logic is a circuit via which a processor receives the commands from the
software program to control the operation of datapath components. The control logic
can be understood as a combination of finite-state machine circuits with high
complexity. The main components in control logic consists of decoder, branch
predictor (BP), out-of-order execution (OoOE), interrupt controller (INTC), and
power management unit (PMU) (see Fig. 40.3).
The decoder is a control unit responsible for instruction decoding in a processor.
All the information required for the current instruction operations can be obtained
764 X. Yan et al.

through decoding, including the instruction operation type, the source operand
address, the target operand address, the immediate value, and the like.
The branch predictor or branch prediction (BP) unit is a control unit that accel-
erates the processing of branch instructions in a processor. Whether the conditional
branch instruction will jump is unknown until the execution phase, which substan-
tially affects the effective prefetching of the instruction. In terms of implementation,
the low-end processor performs static branch prediction, and the mid-to-high end
processor performs dynamic branch prediction. Compared to static branch predic-
tion, dynamic branch prediction is more accurate, while hardware costs and com-
plexity are also greater.
The out-of-order execution (OoOE) technology refers to a mechanism which
allows instructions in high-end processors not to be executed in strict accordance
with the order in a program. In a high-end processor, instructions in can execute
ahead of the previous instructions and then generate computing result. The out-of-
order execution is a complex control process under which the execution breaks the
order of instruction programming. The processor hardware filters and executes the
instructions that satisfy the execution conditions, avoiding blocking execution of
subsequent instructions due to a particular instruction, and improving the operation
load and performance of the processor.
The interrupt controller (INTC) is a control circuit in a processor responsible for
peripheral interrupt requests and used to interrupt the execution of the current
program of the processor, and allow the processor to process the specified interrup-
tion handler. Generally, modern processors implement precision interrupt tech-
niques, that is, to respond to interrupt requests after an instruction has been
completed.
The power management unit (PMU) is a module in a processor responsible for the
operating states of each module, such as power supply, standby, and full-speed
operation. The instructions of the processor are designed to implement power
management instructions so as to allow the software to program the processor into
different low-power consumption states. The processor is also designed to achieve
different levels of low-power consumption states, allowing the processor and chip to
enter different power consumption states.
Advanced control methods can effectively speed up the processor’s processing
capability, but the design complexity is also greatly increased. An important indica-
tor to measure the complexity of control logic is the number of pipeline stages. In the
early days when IC technology could not keep up with the development of computer
architecture, the designers increased the throughput of the processor by deepening
the pipeline; however, the irregular jumps of deep pipeline structure during program
execution resulted in the reduced processing efficiency of pipeline and the sharp
rising of design complexity. As the feature size of IC technology shrinks, over-
emphasis on main frequency will lead to a sharp rising in switching power con-
sumption. The dominant design focus is to improve the processor’s performance and
energy efficiency by simplifying the pipeline structure using reasonable main
frequency.
40 Design of Processors 765

Coprocessor

The coprocessor, as an extension unit of a processor, is usually an acceleration circuit

which is specially designed for the tasks that the processor cannot perform directly or
efficiently. Generally, the coprocessor and the processor are relatively independent
of each other and are connected and communicated via a common bus. In a narrow
sense, the coprocessors are some acceleration components inside the processor. In a
broad sense, the coprocessors are acceleration components that are loosely coupled
outside the processor. The narrowly defined coprocessor is basically driven by the
processor which executes certain instructions; the broadly defined coprocessor is
located around the processor, closer to the ASIC, and is driven by the processor
which is configured with a coprocessor.
The most common coprocessor is floating-point coprocessor. Most processors
have extended the floating-point operations via a coprocessor, as shown in Fig. 40.4.
The ARM processor implements the vector floating-point (VFP) unit via a copro-
cessor and supports vector floating-point operations. The Phi coprocessor developed
by Intel supports multicore floating-point parallel operations via a chip. The main
processor and the Phi coprocessor are interconnected and communicated via PCI-E
protocol.
In recent years, FPGA-based coprocessor architectures have gradually been
recognized. Many chip designers have adopted the architecture of hard core or soft
core CPU+FPGA coprocessor. In 2010, Xilinx pioneered the provision of the ARM
Cortex A9 processor and FPGA scalable processing platform, and later introduced
the Zynq-7000 series of programmable processors. In 2015, Intel acquired the FPGA
giant, Altera Corporation, at a price of US$16.7 Billion to develop an architecture
that integrates CPU and FPGA. In 2016, Intel introduced the architecture of x86
processor +FPGA, which can boost performance by up to 20 times. Accelerating a
small number of hotspot programs through FPGAs and constant reliance of most
serial programs on x86 architecture processors help to enhance the overall compet-
itiveness of Intel processors.
The coprocessor is a technical approach to targeted extension of a processor for
the application domain. The general idea of the evolution of coprocessor technology
is to design a dedicated coprocessor for a particular domain. In recent years, the deep
integration of processors and FPGAs has become an important idea of coprocessor

Fig. 40.4 An extended

architecture of a typical
floating-point coprocessor
766 X. Yan et al.

evolution. The architecture of CPU+FPGA has been actively developed for appli-
cations in information security, artificial intelligence, deep learning, etc.

Data Processing Pipeline

The data processing pipeline is a design technique that boosts the processor’s
computational throughput. The working principle of pipeline technique is to divide
the execution process of instructions into multiple stages such as instruction fetch,
decoding, execution, data access, and write back. At the same time, multiple
instructions are executed in parallel in a processor, and the execution results of
each stage are temporarily saved in the pipeline registers, as shown in Fig. 40.5. The
total performance of a processor is calculated as follows: total performance of a
processor ¼ IPC  frequency, where, the instruction-per-cycle (IPC) means the
number of instructions that can be executed during each cycle and the frequency
means the number of cycles operated per second. Given that the pipeline technique
has greatly increased the frequency of the processor, it is very effective in boosting
the processor performance (throughput).
Regardless of effectively increased processor frequency, the pipeline technique
brings about a stream of hardware hazards that affect the processor’s IPC optimiza-
tion. The following three types of hazards are mainly taken into account in designing
the pipeline.

1. Structure hazards: A structure hazard is caused by multiple requests accessing the

same physical component. Given that a physical component can only be acces-
sible by one request at a given point in time, other requests will be quiescent at
that point in time. A typical example is that the cache will be accessible for the
fetch stage and the data access stage at the same time, causing a structure hazard
to the cache. The most typical way to resolve structure hazards is to reproduce
multiple pieces of hardware resources.

Fig. 40.5 The task of executing instructions is divided into multiple stages for parallel execution
via pipeline technique
40 Design of Processors 767

2. Control hazards: A control hazard is caused by a branch instruction which

changes the program’s sequential execution. When the conditional branch is in
the fetch stage, the jump instructions and the target address of such jump are not
clarified. At this time, the pipeline will stop prefetching instruction until the
branch instruction is properly executed and the branch jump direction and target
address are obtained. Branch prediction is the main method to resolve control
hazards in the pipeline, which predicts the jump direction of the branch and
initiates instruction prefetching in advance.
3. Data hazards: A data hazard occurs when there is a subsequent instruction
between the instructions that require the operand or result of the previous
instructions that have not been completed, which is also called true correlation.
The true correlation of data means that the previous instructions have not yet
written the result back to the register file when a subsequent instruction enters the
execution phase. The basic method for resolving data hazards is the data forward
technique, which forwards the computing results directly from the execution unit.

The pipeline technique is an important method for the processors to exploit

instruction-level parallelism. Deep pipeline helps to increase the processor’s main
frequency, but at the expense of increased cost, power consumption, and design
complexity. At present, the pipeline depth of high-performance processors is no
longer deepened, and the development focus is directed at improving the IPC. To
conduct a larger scale of out-of-order (OoO) execution and exploit the parallelism of
more instructions, the development of high-performance pipelines is directed. In
terms of low-power-consumption processors, the pipeline is designed to be as short
as possible for reducing power consumption and circuit cost.

Multiple Instruction Issue

Multiple instruction issue refers to the mechanism by which multiple instructions

are issued for execution in a pipeline during a single clock cycle. Traditionally, the
issue and execution of a single instruction in a single clock cycle is called a scalar
architecture. A multiple instruction issue architecture is a processor architecture
whereby hardware supports the issue and execution of multiple instructions in
parallel. Compared to single-issue processors, multiple-issue architectures can
better exploit instruction-level parallelism of the processors and are therefore
widely used in designing modern high-performance processors. Common
multiple-issue processor architectures include such two major categories as super-
scalar architecture and the very long instruction word (VLIW) architecture, as
shown in Fig. 40.6.
The superscalar architecture has a high fetching bandwidth, and the fetching unit
supports prefetching of multiple instructions during a particular cycle, thereby
ensuring that sufficient instructions are available for the subsequent execution
units. The superscalar architecture also has a wide data processing path, and can
execute multiple instructions in parallel during one cycle, which means that multiple
768 X. Yan et al.

Fig. 40.6 Difference between the superscalar architecture (a) and the very long instruction word
(VLIW) architecture (b)

copies of the hardware are required for the instruction decoding unit, the read port of
the register file, the instruction issue unit, etc., and the hardware cost is high. Given
the data dependency of the program, etc., the execution bandwidth of the superscalar
processor is not as wide as possible, but an optimal solution of performance and cost
is available, which generally provides an issue width of 2–4.
The very long instruction word (VLIW) architecture is a technology whereby a
class of processor hardware implements multiple issues in cooperation with a
compiler. The VLIW technique executes instructions in the form of instruction
packets. An instruction packet contains multiple instructions. The processor hard-
ware acquires and executes an instruction packet during each clock cycle. The main
features of the VLIW technique are stated as follows: Certain requirements are
imposed on the format of the instruction packet, that is, the instruction packet
must be encapsulated according to a certain format; the compiler solves, completely
or partially, the pipeline hazards, and solves various correlation hazards by sched-
uling or inserting a no-operation instruction. Due to the support of the compiler, the
hardware is designed in a relatively simple fashion. However, this technique requires
the cooperation of software and hardware, so the parallelism and flexibility of
software programming are not friendly enough.
In the actual design, the general-purpose processor is more inclined to adopt
super-scalar technique, because the backward compatibility of the software should
be considered, and each new generation of processors must enable the “old”
application software accumulated in the ecosystem to function well on new archi-
tecture processors, i.e., software corresponding to the hardware should be transpar-
ent; the VLIW technique is more used by digital signal processors, because digital
signal processing usually have better data parallelism and lower requirements on
compatibility are imposed for segmentation fields.
40 Design of Processors 769

Single Instruction Multiple Data (SIMD)

The single instruction multiple data (SIMD) is a computer structure that processes
multiple data in a single instruction under the Flynn’s classification. The hardware
structure of single instruction multiple data (SIMD) is shown in Fig. 40.7. SIMD
technology is mainly used in the applications of data processing with uniform data
processing algorithm and good data parallelism. A typical computing scenario is an
image algorithm that processes each pixel or block as per the same algorithm, and via
which many pixels and blocks are processed in parallel. Given that matrix-like
operations are widely used in such fields as audio/video, image, and signal pro-
cessing, under which the processed object programs are the same, and the only
difference is the processing of parallel data, SIMD technology is generally adopted
in designing acceleration instructions for these applications.
Key issues involved in SIMD include data operation width, element width, and
operation type. (1) The data operation width means the maximum data width that the
instruction can operate, which directly determines the throughput of the SIMD
operation; (2) the element width means the width of the element operation in the
SIMD, which is basically depending on the application and the data width to be
processed; (3) operation type means that the operation should support the SIMD
operation, and different requirements on the width should be imposed on different
precisions. Taking the Intel processor as an example, Intel implemented the SSE
instruction set for video and audio acceleration. These instructions are designed
according to the SIMD method, and each instruction can operate 128-bit wide data.
In terms of element width, considering that the basic element width in the video and
image fields is byte, and the basic element width in the audio field is half-word, and
the basic element width in both the high-precision signal processing field and the
floating-point field is words, the element width of SSE can support byte/half-word/
word operation. An SSE instruction can operate up to 16 bytes in parallel in
conjunction with data operation width and element width. In terms of operation
type, the SSE instruction implements typical data operations such as multiplication,

Fig. 40.7 Hardware structure

of single instruction
multiple data
770 X. Yan et al.

multiplication and accumulation, shifting, and logic operations. ARM’s Neon tech-
nology also implements the SIMD architecture, whose data operation width is also
128 bit, with the specific operation type similar to that of Intel.
The evolution of SIMD technology is directed at the acceleration of application-
specific algorithmic capabilities. Applications with uniform algorithm structure
and good data parallelism tend to be implemented in SIMD processors or
coprocessors.

Multithreading

Thread is the smallest program fragment in the program execution stream and the
smallest unit that the operating system can schedule. Threads are included in the
process and are the actual units of operation of the process, so threads can be
regarded as sequential control flow with certain functions running on the processor.
The difference between a thread and a process lies in the followings: separate
memory spaces are available between two processes, while the threads of the same
process run in a shared memory space, each of which has its own separate execution
stack and program counters to execute the context. A hardware-backed multi-
threaded processor refers to a processor that can run multiple threads in parallel
simultaneously. A processor that adopts hardware multithreading technology allows
the hardware to directly schedule other thread instructions that are already ready to
enter the execution unit to perform operations in the event of a blocked thread,
thereby improving the utilization of the datapath, and improving the overall through-
put of multiple threads running.
The simultaneous multithreading (SMT) provides a technique to run multiple
instructions from different threads in a particular clock cycle. Based on a super-
scalar processor, SMT is a product generated by extending the ability of the
superscalar processor to execute multiple instructions simultaneously into a multi-
threaded scenario. SMT further enhances the limited instruction parallelism of a
single thread on the premise of spanning multiple threads, making full use of
superscalar pipeline hardware resources. SMT needs to increase the hardware
resources for recording the thread numbers of different running instructions in all
stages of the pipeline and related control logic, and also needs to expand the
resources shared by the threads such as on-chip cache and translation look-side
buffer (TLB), and alleviate the hazards between the threads. Typical processors
that have adopted SMT include Sun’s UltraSPARC T2, Intel’s Pentium 4 Xeon,
and Core i7. A schematic diagram of multiple threads running on different logical
cores is shown in Fig. 40.8.
The merit of single-core multithreading technology is that multiple independent
threads can share the storage and execution units of the processor, which costs less
than multicore hardware. The drawback of single-core multithreading technology is
that the multithreaded control logic is designed in a complex manner and has poor
40 Design of Processors 771

Fig. 40.8 Schematic diagram

of multiple threads running on
different logical cores

scalability, e.g., the cores of a processor should be redesigned so as to scale from

thread 2 to thread 4. In recent years, with the continuous advancement of technology,
hardware cost is no longer a major contradiction, and the low-cost value of multi-
threading technology is gradually decreasing. Multicore is widely used by virtue of
its good scalability and lower difficulty. It has become a trend that multithreading are
replaced by multicore.

Multicore

The multicore processor is an arithmetic component consisting of two or more

(generally no more than 32) independent processor units (also called “cores”),
each of which may work independently in the same manner as a traditional single-
core processor does. The fact that multiple processors read and execute instructions
of multiple programs in parallel can speed up the parallel computation of multiple
independent programs. The multicore processor is a kind of task-level parallel
processing technology that emerged due to the bottlenecks of improving the
instruction-level parallelism of single-core processors.
The multicore processor has separate cache units (L1 cache) and an external
storage unit (L2 cache and internal memory) shared by the processors via a bus. The
main problem faced by multicore processors based on shared storage architecture
(see Fig. 40.9) is the maintenance of data consistency, that is, when a local cache of a
processor is modified during operation, the same address segment data in the local
cache of other processors are not modified, resulting in data inconsistencies among
the processors.
772 X. Yan et al.

Fig. 40.9 Schematic diagram of a multicore processor based on shared storage architecture

Such data consistency issue is addressed by a dedicated cache coherency protocol

designed for multicore processors. Most multicore processor systems currently adopt
a “snooping” based coherency protocol, whose main principle is that all local caches
would observe the data updates occurring on the bus through the internal bus in real
time, and check and update the local cache on the corresponding address once an
update to shared storage is detected. A common snooping protocol is the MESI
(modified, exclusive, shared, and invalid) protocol, which designs four states for
multiple cache units. When a cache update occurs, the state change of the cache
segment will be broadcast to other processors.
If the computing cores inside a multicore processor are identical and completely
equal, such processor is called homogeneous multicore processor. In terms of a
homogeneous multicore architecture, its system is completed by repeatedly
implementing a basic computing unit, and designing a unified management com-
munication interface, shared storage, etc. If the computing cores inside a multicore
processor are not identical, such processor is called heterogeneous multicore pro-
cessor. Common computing core categories include CPU, GPU, DSP, ASIC, FPGA,
and so on. Heterogeneous multicore processor can be expressed as “CPU+other
processors.” Currently, the common heterogeneous multicore processors appear in
embedded multicore processors, such as CPU+GPU of AMD, Apple, Qualcomm,
Samsung, Huawei, and other companies.
With the explosive growth of high-performance parallel computing demands in
such fields as cloud computing, computer vision, machine learning, and VR/AR, the
energy efficiency of heterogeneous multicore processors is higher than that of
homogeneous multicore processors thanks to its introduction of other energy-
efficient computing units such as GPUs, DSPs, and hardware accelerators, which
directs the development of high-performance computing. CPU+FPGA developed by
Intel through acquisition of Altera Corporation and AMD’s new architecture APU
that incorporates CPU+GPU fall to the categories of heterogeneous computing.
40 Design of Processors 773

Manycore Processors

The manycore processor is a kind of multicore processor designed to meet the needs
of large-scale parallel computing, whose internal core number usually ranges from
tens to thousands or more, as shown in Fig. 40.10. Compared with multicore pro-
cessors, manycore processors seek for higher explicit parallelism and energy-
efficiency ratios, and tend to adopt a simpler processor core and increase the routing
nodes used for communication of each processor node, so as to realize good
scalability. Although the single-core performance is not so high, the parallelism of
program tasks is greatly increased because of extra processor cores, which enables
the manycore processors to achieve better overall system performance.
Manycore processors are generally built on a network-on-chip (NoC) to enable
direct point-to-point inter-core communication. The network-on-chip can optimize
the partitioning and sharing mechanism of the global interconnection for which
communication costs can be greatly reduced and communication efficiency
improved compared with those of the multicore architecture based on global bus
synchronization and shared memory communication. The hardware performance of
manycore processors can reach the Tera-FLOPS (floating-point operations per
second, TFLOPS) level, but in practical use it is a huge challenge to software
programming to determine how to achieve the task partitioning of the target software
and map the divided subtasks to the corresponding processor nodes to fully exploit
the potential of each processor. The results of the 16-core and 24-core manycore
processors researched and developed by a team from Fudan University in China
have been published at the International Solid-State Circuits Conference (ISSCC).
At present, the programing models applicable to manycore processors mainly
include message passing interface (MPI), open computing language (OpenCL),
partitioned global address space (PGAS), actor model, open multiprocessing
(OpenMP), etc.
In 2017, the world’s fastest “Sunway TaihuLight” supercomputer adopts a total of
40,906 SW26010 processors, with a total of processor cores of 10,649,600. Future
trends of manycore processors include automated parallel compilation techniques,

Fig. 40.10 Schematic diagram of a manycore processor

774 X. Yan et al.

operating system research, high reliability, testability, on-chip synchronization

mechanisms, data sharing and allocation strategies, configurable attributes, and
massive thread management, and application fields of manycore processors include
biocomputing, network security, signal processing, network packet processing,
graphics processing, machine learning, etc.

Memory Hierarchy

Memory is a hardware that holds the data and is a basic component of the Von
Neumann architecture-based computer that is tightly coupled to the processor. High-
capacity high-speed memory provides the basis for processor performance. How-
ever, during the development of modern ICs, the development of memory has lagged
behind the development of processors for a long time. Depending on the trade-offs
among speed, capacity, and price, multihierarchy storage architectures are often
employed in modern computers. In light of the storage access latency, the multi-
hierarchy storage architecture is divided into different levels of memory hierarchy, as
shown in Fig. 40.11. The lower the level of memory hierarchy (logically closer to the
processor) is, the smaller the access latency and the higher the unit cost; therefore,
the designed memory capacity is relatively small. The higher the level of memory
hierarchy (logically farther from the processor) is, the larger the access latency and
the lower the unit cost; thus, it is proper to store large-capacity data not frequently
used into higher levels of memory hierarchy.
The registers are located inside the processor and typically each register holds one
or two words (generally, 32 bits or 64 bits). The caches are also located inside the
processor and are set to reduce the cost of access to main memory (access time and
power consumption), and to store frequently accessed instructions or data. The
caches can be divided into instruction cache and data cache, and can be further

Fig. 40.11 Memory hierarchy

40 Design of Processors 775

divided into more hierarchies according to the architecture needs, such as the first
level cache (L1) and the second level cache (L2). The main memory is referred to as
MM, and is a memory that the CPU can directly access, that is, the CPU can directly
read the corresponding instructions and data in the MM for computing.
The MM is usually composed of random access memory (RAM). Given the
volatility of some particular types of RAM, all data of main memory will be lost in
the event of any power outage. The access time of the MM is usually a few
nanoseconds or tens of nanoseconds, which needs to be directly or indirectly
connected to the CPU through a memory bus, including an address bus and a
data bus.
The local secondary memory, also known as external memory, is a kind of
auxiliary memory, which the CPU cannot directly access. Given that such memory
is usually nonvolatile, its data will not be lost after power failure. The auxiliary
memory can meet the cost-effective large-capacity storage requirements because its
unit price is cheaper than that of main memory by more than two orders of
magnitude. Generally, disks are used as the auxiliary memory, whose access latency
is in the millisecond range.
In the future, the performance of each storage subsystem will continue to be
optimized, e.g., the solid-state drives (SSDs), eliminating the seek operation of
mechanical hard disk drives of common auxiliary memories, and contributing to
extremely low random read latency. In the meanwhile, new types of memories such
as phase change memory (PCRAM, PCM, and PRAM), resistive memory (ReRAM
or RRAM), and magnetic memory (MRAM) are also emerging. These new memo-
ries are expected to be used in the embedded fields, and will change the architecture
of embedded system because they are nonvolatile and executable. Currently, these
technologies have not fundamentally solved the problems of read/write speed and
cost. Therefore, multimedia hybrid storage systems and integrated management are
expected to become a major development direction in terms of data storage system.

Digital Signal Processor (DSP)

The digital signal processor (DSP) is a dedicated processor designed to optimize

digital signal processing (DSP) algorithms, and is commonly used to measure, filter,
compress, or otherwise dispose of real-time continuous analog signals. A typical
DSP architecture diagram is shown in Fig. 40.12. DSP algorithms require a large
number of repeated arithmetic operations on the data over a short period of time. For
example, the continuous time domain signals of the audio and video sensors are
continuously converted into frequency domain digital signals, which, after quanti-
zation and other processing, are transmitted, and finally inversely transformed back
into the time domain signals.
Usually, stringent requirements on latency are imposed on the DSP application,
which means that the processor must complete the signal processing task within a
fixed time limit. The DSP architecture is specifically designed for DSP optimization
to contrapuntally provide low-cost, high-performance, and low-latency computing
776 X. Yan et al.

Fig. 40.12 Typical DSP architecture diagram

capability. DSPs usually have application-oriented features, so it is difficult to get

support from general-purpose compilation tools. The programs of DSPs often exist
in library files in the form of assembly. DSP needs to process a large amount of data
streams, so its storage architecture must be designed to acquire multiple instructions
or data at the same time. DSPs often store the data and instructions in parallel, with
multiple data buses. In addition, it is more dependent on the use of DMA because the
DSP program needs to be specially optimized for the cache so as to further reduce the
latency. Given that a large latency occurs to operating systems mapped with virtual
memory during process switching, DSPs usually do not support virtual memory or
virtual memory protection.
The technical development trend of DSPs includes: (1) core instruction parallel
capability will be further enhanced, and the single instruction multiple data (SIMD)
and the very long instruction word (VLIW) will dominate in the next generation of
high-performance DSP; (2) multicore DSP solutions are becoming more common in
some high-performance applications; (3) both fixed-point and floating-point com-
putations are supported; (4) digital signal controllers (DSCs), also known as single-
chip DSPs, can be integrated with more functions and interfaces through advanced
technologies to reduce overall board cost and power consumption and reduce the
size; and (5) the convergence of DSP and MCU becomes a trend, the micro-
controllers are versatile with low cost but weak digital signal processing capability,
incorporating DSP expansion helps simplify design and reduce cost and power
consumption.

Graphics Processing Unit (GPU)

The graphics processing unit (GPU), also known as the vision processor or display
chip in the past, is a microprocessor intended to process graphics and image on
personal computers, workstations, game consoles, and mobile devices. The graphics
processor converts the display information required by the computer system and
ultimately transmits the same to the display. Therefore, the graphics processor is one
of the important devices for “human-computer interaction.”
40 Design of Processors 777

What makes a difference in designing the graphics processor is data parallelism,

for which such technologies as single instruction multiple data (SIMD) or single
instruction multiple thread (SIMT) at the instruction level and multicore at the
architecture level are often adopted. SIMD packs multiple data elements to process
a single instruction, which accelerates the processing of vector data, but fails to
handle branches efficiently. SIMT is an improvement of SIMD technology that
allows a set of independent threads running simultaneously to share instructions
and allows each thread to have a different branch. Graphics processors often contain
dozens or even hundreds of stream multiprocessors (SMs), each of which contains
dozens of thread processors (TPs). NVIDIA’s TITAN X GPU in 2015 has 3584
processing cores. Graphics processors need to be designed with high-bandwidth
on-chip memory devices so as to take full advantage of the computing capabilities of
these processors.
As big data, cloud computing, and machine learning spring up, the scale of data
processing is becoming larger and larger. A widespread attention has been drawn to
the application of GPUs to the development of general-purpose GPU (GPGPU)
computation. The widely used GPGPU platforms cover OpenCL, OpenGL, CUDA,
etc. The open computing language (OpenCL) is an open and free standard for
parallel programing of general-purpose computing in heterogeneous systems. The
open graphics library (OpenGL) defines a cross-platform and cross-language high-
performance graphical program interface. The compute unified device architecture
(CUDA) defines a general-purpose parallel computing architecture. CUDA imple-
ments parallel programming by dividing the tasks that require a lot of computation
into multiple levels. Firstly, CUDA divides the tasks into task blocks, and then
divides the task blocks into finer-grained CUDA threads, and finally assigns these
threads to the processing cores in the GPU for execution.
GPUs not only play an important role in the traditional image processing field, but
also drive the development of high-performance computing and artificial intelligence
(AI) by virtue of its extremely high data throughput. Such companies as Google,
Baidu, and Facebook have successfully built AI (with deep learning) platforms by
using GPU clusters as the infrastructure. Google’s AlphaGo artificial intelligence
platform successfully defeated the world champion Lee Sedol in March 2016, and
AlphaGo’s upgrade Master achieved a 60:0 victory in a game against human in early
2017. With the deepening of research, GPUs will play a more important role in such
applications as scientific computing, artificial intelligence, and autonomous driving.

Further Reading
1. J.G. Xu, Wang W.W.: System Architecture of Microprocessor (Science Press, Beijing, 2008)
(Chinese book series 5 of 5, ISBN 978-7-03-022807-9)
2. D.A. Patterson, A. Waterman, The RISC-V Reader: An Open Architecture Atlas (Strawberry
Canyon, Berkeley, CA, USA, 2017)
3. D.A. Patterson, J.L. Hennessy, Computer Organization and Design RISC-V Edition: The Hard-
ware Software Interface, The Morgan Kaufmann Series in Computer Architecture and Design,
2nd edn. (Morgan Kaufmann, Cambridge, MA, USA, 2020)
Memory Design
41
Fujun Bai, Xiaowei Han, and Liyang Pan

Contents
Memory Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
Memory Cell and Periphery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
3D NAND Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
FeRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
STT-MRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
ReRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
PCRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

Abstract
Semiconductor memories are digital electronic semiconductor devices used for
the digital information storage of program code and data. As the demand keeps
growing, new memory technologies are continuously introduced and the existing
technologies are further developed. A variety of semiconductor memories are in
development with different concepts of memory cells for various applications.
There are two main categories of memories, i.e., volatile memory (VM) and
nonvolatile memory (NVM). VM needs to be provided power constantly to retain
data, such as static random access memory (SRAM), which uses several transis-
tors per memory cell, and dynamic random access memory (DRAM), which uses
a single transistor and a capacitor per cell. In contrast, NVM retrieves stored

F. Bai · X. Han (*)

Xi’an UniIC Semiconductors Co., Ltd, Xi’an, Shaanxi, China
e-mail: xiaowei.han@unisemicon.com
L. Pan
Institute of Microelectronics, Tsinghua University, Beijing, China

© Publishing House of Electronics Industry 2024 779

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_41
780 F. Bai et al.

information even after the power goes down. Examples of NVM include read-
only memory (ROM), flash memory with floating gate MOS transistor per cell,
and several emerging memories, such as ferroelectric RAM (FeRAM), spin
transfer torque magnetoresistive RAM (STT-MRAM), resistive RAM (RRAM),
and phase change RAM (PCM).
Semiconductor memories are available in various forms: IP for system-on-
chip, discrete components for assembly, memory cards, and solid-state hard
drives. Usually a semiconductor memory works with memory controller, which
bridges memories and corresponding host computers, and also manages the
operation of memories accordingly.

Keywords
Semiconductor memory · Memory controller · SRAM, DRAM · Flash · 3D
NAND · FeRAM · MRAM · RRAM · PCM

Memory Categories

Semiconductor memory devices are widely used in electronic systems such as

computers to store program code and data in information technology. They store
and retrieve data according to the address specified. Compared with traditional
magnetic memory, semiconductor memory devices (briefly as Memory) have the
advantages of small size, good performance, and low power consumption. Memory
types are as shown in Fig. 41.1.
According to the status of data maintenance after power supply termination, we
can divide the memory into two categories: volatile memory and nonvolatile mem-
ory. Volatile memory includes static random access memory (SRAM) and dynamic

Fig. 41.1 Memory categories

41 Memory Design 781

Table 41.1 Comparison of mainstream memories

Types Capacity Speed Power consumption Cost Volatile
SRAM Low High High High Volatile
DRAM High Read: Medium Medium Low Volatile
Write: Medium
NOR flash Low Read: Medium Medium Medium Nonvolatile
Write: Low
NAND flash High Low Medium Low Nonvolatile

random access memory (DRAM). Nonvolatile memory includes not only read-only
memory (ROM), programmable ROM (PROM), erasable programmable ROM
(EPROM), and flash, but also some emerging memories, such as ferroelectric
RAM (FeRAM or FRAM), magnetoresistive RAM (MRAM), resistive RAM
(ReRAM or RRAM), and phase change RAM (PCRAM or PCM).
Memories are divided into read only memory (ROM) and read/write memory
(RWM) according to their functions. ROM permanently holds its content, which can
only be read and cannot be altered. RWM, which provides both read and write
functions, can be divided into random access memory (RAM), sequential access
memory (SAM), and content-addressable memory (CAM) according to different
access modes. RAM supports random order access, while SAM accesses data
sequentially, such as FIFO (first-in first-out), LIFO (last-in first-out, used as stacks),
and shift registers. Instead of looking for data by address, CAM returns address
where data matches the given keyword.
There are many kinds of memories with various capacity, speed, power consump-
tion, cost, and volatility, as shown in Table 41.1. SRAM, which has fast access speed
and small storage capacity, usually is used as processors’ cache for instructions and
data. DRAM has lower access speed but higher density, so that it is often used as
main memory. Flash, which is nonvolatile and of the largest storage capacity, is often
used to store system programs and files. NOR flash is superior to NAND flash in
read/write speed, hence is mainly used for program storage. While NAND flash is
used for data storage, because of the extremely low cost per storage unit.

Memory Cell and Periphery Circuit

A memory chip consists of memory cell array, row decoder, column decoder, and
sense amplifier, as shown in Fig. 41.2.
Memory cell, which stores one or more bits of binary code “0” or “1,” is the basic
storage unit and can be accessed with the assistant of periphery circuits. For
example, the classical 6 T SRAM memory cell consists of six transistors, which
forms two invertors with input to output connected to each other to latch data.
DRAM memory cell is a 1T1C (one-transistor and one-capacitor) structure, of
which the amount of charge in capacitor represents the states of “0” and “1” if
with or without charge. Flash memory cell uses different cell transistor’s threshold
782 F. Bai et al.

Fig. 41.2 Memory structure

Fig. 41.3 Repair scheme in memory

voltage to represent different states. Floating gate transistor is commonly used as

flash memory cell.
Memory cells can be organized to form a cell array. For example, a cell array
consists of 2p memory blocks (p is the width of block addresses), each of which
contains 2n words (n represents the width of word addresses in each storage block).
Each word is a group of data written to or read from the cell array at the same time
with m bit word width. The memory capacity is 2p+n+m bits in total. Memory can
achieve large capacity by using longer word lines and bit lines, but parasitic
capacitance and resistance of long word lines and bit lines will slow down memory
access speed. Therefore, cell array designers need to make a trade-off between
capacity and performance. Optimizing array organization and partition, the word
lines and bit lines in a memory block can balance both speed and capacity.
Redundant array is added to the normal array to improve yield. When the normal
array fails, the redundant rows, columns, or words in the redundant array can be used
to replace the faulty ones in normal array. For example, as shown in Fig. 41.3, a
redundant array contains two redundant rows (SR0 and SR1), two redundant
41 Memory Design 783

columns (SC0 and SC1), and two redundant words (SB0 and SB1). When the word
E in column C3 and row R2 of normal array is wrong, the redundant row SR0 can be
used to replace the row R2 directly, or the redundant column SC0 can be used to
replace the column C3, or the redundant word SB1 can be used to replace the word E
directly. Generally, redundant rows and columns are used to repair row and column
defects, and redundant words are used to repair single-bit error. The size of redun-
dant array increases together with normal array. During memory design, it is
mandatory to analyze the size of the redundant array needed according to the type
and probability of memory array fault, so as to achieve the goal of using the least
redundant units to greatly improve product yield.
Row decoder controls word line (WL) activation according to input row address.
Each active WL selects a row of memory cell. Perpendicular to WL, cells located in
the same column but in different rows are connected to the input/output circuit via bit
line (BL). Row addresses Ak to An-1 can control 2n-k WLs through row decoder. A0
to Ak-1 is column address, which is input to column decoder, meaning that there are
2k words per WL. Column decoder selects one word out of the total 2k words for
operation. Row decoder and column decoder have an important impact on the speed
and power consumption of memory. Generally, they are closely placed to the
memory array, and fit to the pitch of one or more cells.
Sense amplifier (SA) is the core part of memory readout circuit. SA, which is
essentially an analog circuit, detects the weak signals on BL and amplifies into a
signal with larger output swing. SA can not only compensate for the limited output
drive ability of memory cell and speed up read operations, but also reduce the signal
swing on BL so that the power consumption due to BL charge and discharge is
greatly saved. According to the intrinsic characteristics of memory cell and the
architecture of the memory array, different types of SAs are implemented. Differen-
tial voltage amplifier is the most common SA in memory.
Error correction coding (ECC) is widely used in memories and controllers, see
Fig. 41.4. It detects and corrects data errors to improve memory reliability. In order

Fig. 41.4 Memory with embedded ECC

784 F. Bai et al.

to support ECC, an additional memory array is added to store parity bits. ECC circuit
can be embedded into either controller or memory. Once embedded into memory,
ECC makes the memory to be able to self-repair. DRAM with embedded ECC is not
only compatible with standard DRAM interface, but also has high reliability and
yield. On the contrary, some memories only provide additional parity bits, and ECC
algorithm is processed by controller. For example, NAND flash reserves storage
space for ECC parity bits which are used in conjunction with ECC circuits in flash
controller to enhance endurance of NAND flash significantly.

Memory Controller

Memory controller serves as a bridge between memory and CPU. Memory control-
lers derive from different memory specifications, such as controllers especially for
DRAM and controllers for flash.
In computer system, memory controllers are needed to exchange data between
CPU and memory. It determines the maximum memory capacity, the number of
memory block (bank), the type and speed of memory, the data depth and width, and
other important parameters. The overall performance of computer systems is highly
dependent on controller’s performance. At present, memory controllers are generally
integrated in CPU. The disadvantage is that the adaptability is poor, but the advan-
tage is that the data latency is squeezed to achieve higher system performance. Fully
buffered DIMM (FB-DIMM) is developed to further release the constraints of
memory performance on the overall system performance, through adding an
advanced memory buffer (AMB), the communications between controller and
memories are high-speed, multichannel, serial, and point to point.
Unlike DRAM controllers, flash controllers are not only responsible for the
communication between CPU and flash, but also for the management of flash,
including bad block management, wear leveling, and so on. The endurance of
flash is limited. Through wear leveling technique, flash controller records the
usage of whole flash memory space, so that the rewrite data can be written to
different address in the flash memory each time, rather than to the same address all
the time. Ideally, wear leveling technique ensures that all physical addresses of flash
have been used evenly before reusing. By making maximum use of all flash cells, the
entire life of the whole flash memory is extended.
However, the flash memory will wear out as the number of cycling increases. The
bad blocks in flash memory gradually increase due to the fact that failed cells
become more and more. Bad block management is introduced and marks the spotted
bad blocks. Flash controller builds a bad block table by reading bad block marks.
The blocks listed in the bad block table will not be accessed and replaced by a good
block by address remapping. From the users’ point of view, although the capacity of
flash memory reduced a little, the memory can still work before the number of bad
block reaches the preset limitation.
Aside from stand-alone controller, eMMC (embedded multimedia card), which
packages the flash controller and flash memory together, is widely used, especially in
41 Memory Design 785

Fig. 41.5 ECC principles in

memory controller

mobile phones and tablets at present. It provides a standard interface and manages
flash memory as well, so that users can focus only on their own product development
and do not need to deal with flash compatibility and management issues to shorten
the time to market and reduce cost.
Many memory controller supports error correction code (ECC) technology, which
can detect and correct data errors to improve reliability. Memory only needs to
provide additional parity bit storage capacity. The advantage of integrating ECC
function to controller is that the algorithm is not hardened in the memory and
therefore more flexible for controller designers, while the disadvantage is that it is
hard to exploit the best memory performance. As shown in Fig. 41.5, D (k) is the
original k bit data, data C (n, k), which is n bits, is generated by ECC encoding with
parity bits appended. And then controller writes the memory with C (n, k), which
may be read out as C0 (n, k). If the number of erroneous bits in C0 does not exceed the
error correction ability of controller ECC algorithm, the corrected data Q(k) ¼ D(k)
is obtained by ECC decoding. Otherwise, it may not be corrected or even detected.
Since the Hamming code can only correct one-bit error, ECC codes which can
correct two- or more-bit errors are gradually adopted with the increase of memory
error rate. At present, BCH codes, RS codes, LDPC codes are the mainstream
algorithm in use.

SRAM

SRAM (static random access memory) has become an indispensable member of

semiconductor memory family due to its low power consumption and high-speed
performance. SRAM cell uses bistable latching circuitry to store each bit. Compared
with DRAM, SRAM has fast access speed, and the data can be held permanently
without refreshing as long as the power is constantly on. SRAM cell usually uses six
transistors, thus it results in complex design and low density.
SRAM can be divided into asynchronous SRAM and synchronous SRAM
according to the interface. Asynchronous SRAM has no clock signal, and its access
786 F. Bai et al.

is triggered by the change of command signal or address signal such as chip

selection, write enable, etc. All access to synchronous SRAM is initiated at the
rising/falling edge of clock. Address, data input, and other control signals are all
related to clock. SRAM has two different types of application: discrete component
and embedded IP. As stand-alone component, discrete SRAM is mainly used in
communication systems, high-speed networks, and so on. Embedded SRAM is used
as cache, register heap, lookup table, etc. in SoC due to its compatibility with
standard CMOS process. SRAM compilers are designed to generate SRAM
instances automatically. SRAM compiler can generate files such as layout, netlist,
and timing model, according to user-defined SRAM parameters.
SRAM cell has different schematics, including 6 T and 8 T structures, as shown in
Fig. 41.6. The most commonly used 6 T SRAM memory cell contains a pair of cross-
coupled inverters to hold data and a pair of access transistors to read and write. When
writing, WL is opened, and data is written to node Q through a pair of complemen-
tary bit lines BL and BL. When reading out, the BL and BL are pre-charged and then
floated by the pre-charged control signal PREB. When WL is raised for read
operation, sense amplifiers (SA) is opened to amplify the voltage difference between
bit line BL and BL and then the data is sent to the output circuit.
SRAM cell design is one of the most challenging works of SRAM design.
While minimizing area occupation, SRAM designers should balance cell static
noise margin, readability, and writeability at the same time. For example, the
cross-coupled inverters should be strong to overcome read noise but weak to flip
during write operation. Usually semiconductor manufactories provide SRAM
cells, which are carefully tuned for specific processes. SRAM designers choose
cells of area, speed, or power enhancement to meet their products’ specification
(Fig. 41.7).
Pseudo-SRAM (PSRAM), whose cell is 1T þ 1C as DRAM-like cell, works with
a SRAM-like interface. The cell refresh is done internally by PSRAM itself, so it is
not necessary to use complicated controller like DRAM. Meanwhile, PSRAM is of
higher capacity than SRAM and is suitable for products with certain cache capacity
requirements.

Fig. 41.6 SRAM cells with six transistors (6 T) and eight transistors (8 T)
41 Memory Design 787

Fig. 41.7 SRAM read operation diagram

DRAM

Dynamic random access memory (DRAM) uses 1T1C (i.e., one access transistor and
one storage capacitor) to store a bit as a charge in the cell capacitor. This allows
DRAM to reach very high density. But the disadvantage is that since it stores data as
charge which leaks, therefore the charge needs to be read and rewritten again every
few milliseconds (known as refresh).
The DRAM cell is illustrated in Fig. 41.8. The storage capacitor is charged for “1”
and discharged for “0.” During read operation, the bit line BL is pre-charged first,
and then the word line WL is active. A charge share between BL parasitic capacitor
CBL and the storage capacitor Ccell occurs and changes the voltage of pre-charged
BL. If BL voltage increases after the charge share, the read-out data will be “1.” The
read-out data will be “0” on the contrary. Since the storage capacitance is usually one
to two orders of magnitude smaller than the parasitic capacitance of the bit line, the
voltage variation due to charge share is as small as around 200 mV. It is necessary to
increase the storage capacitance to enlarge the BL voltage variation and also the life
time of storage content as charge. Although more capacitance can reduce DRAM
soft errors, it comes at the expense of more area. In order to achieve higher DRAM
memory cell density and lower cost per bit, the DRAM technology is constantly
scaled down in size. DRAM requires special manufacturing process to maintain the
performance of memory cells. Stacking capacitor technology, which indicates that
788 F. Bai et al.

Fig. 41.8 DRAM memory cell array

Fig. 41.9 DRAM process development trend chart

capacitors are stacked on top of access transistors, is widely used at present. The
large storage capacitors are realized by stacking multilayer materials. In addition,
trench capacitor technology etches deep holes in the substrate, using its side wall and
Si substrate as the capacitor electrode. By extending DRAM cell into a three-
dimensional structure, the area of a single DRAM memory cell reaches 6F2
(where F is the process feature size) and beyond. The development trend of
DRAM process is shown in Fig. 41.9.
Generally, a DRAM core block consists of cell array, sense amplifier (SA), and
word line driver. Its performance and area are fundamental for the whole DRAM
chip. In the cell array, the cells in a row share the identical word line, and the cells in
a column connect to the same bit line. The basic operation of DRAM storage array is
shown in Fig. 41.10. Sense amplifier adopts differential voltage structure,
connecting to a pair of complementary bit line (BL and BLB). SA is responsible
for amplifying small voltage difference on bit line while reading data and rewriting
cell when writing data. Word line driver controls the switch of word line. DRAM
core block supports four basic operations: ACT, WR, RD, and PRE. All cells
connected to the same word line (called a page) are activated at the same time in
activation operation (ACT). When the word line is opened, the bit line voltage will
41 Memory Design 789

Fig. 41.10 Basic operation of DRAM cell array

rise slightly if the selected cell stores “1,” and will decrease if the cell is “0.”
Meanwhile, the charge in cell has been damaged due to charge sharing. After waiting
for the voltage difference on the bit line to stabilize, the sense amplifier starts to
amplify the BL voltage difference to the full swing and hold the data for further
operations. Since the word line is still open, the sense amplifier will rewrite the cell
and restores the original data (called refresh). After ACT operation, a page of data is
loaded to SA and can perform read and write randomly. Write (WR) and read
(RD) operation access SAs according to column address; RD operation reads out
data from the corresponding column of the active page from SA, while WR
operation writes data to SA by write driver and then to the cell by the SA. Pre-charge
(PRE) operation closes the active page, including word line and SA, and pre-charge
all bit lines for next ACT operation. DRAM designers need to optimize the circuit
and layout design of this core area. It is important to study the DRAM core block by
running simulation and reliability analysis to determine the physical width of word
lines, bit lines, and data lines.
Despite the continuous progress of technology, the access speed of DRAM core
block has not been significantly improved from the beginning. DRAM interface can
be doubled by data prefetching in core and high-speed data path and high-speed
interface design. A series of DRAM products are derived: SDRAM (synchronous
dynamic random access memory), DDR SDRAM (double data rate synchronous
dynamic random access memory), or simply DDR. Later generations of DDR are
DDR2, DDR3, DDR4, and the most advanced DDR5 planned in 2019.

Flash Memory

Flash memory or flash is a kind of nonvolatile memory (NVM), in which the

threshold voltage (UT) of memory cell represents the data in storage. Floating gate
transistor is one of the main technologies used in flash cell, as shown in Fig. 41.11.
The amount of charges stored on the floating gate determines the VT of cell. Program
(PGM) operation injects electrons into the floating gate through quantum tunneling
to increase the cell VT, representing the logic “0.” On the contrary, erase (ERS)
operation removes the electrons out of the floating gate, so that the cell VT is reduced
to represent logic “1.”
790 F. Bai et al.

Fig. 41.11 Flash cell

structure

Fig. 41.12 Array structure of NOR and NAND flash memories

According to the differences of array structure, there are two types of flash: NOR
flash and NAND flash, as illustrated in Fig. 41.12. NOR flash cells are connected in
parallel in array, while NAND flash cells are connected in series. Due to the parallel
connection, NOR can realize fast random read operation at the cost of larger array
area than NAND flash, and it is mostly used for code storage. In NAND flash array,
the contact between serial cells (called a string) can be removed so that the average
area of a single cell is close to 4F2 (where F is the process feature size) and more
compact than NOR flash. Many NAND flash strings constitute a cell block. The
erase operation of NAND flash is performed by block, while read and program
operations are performed by page. NAND flash is very suitable for big data storage,
such as in smart phones, digital cameras, MP3, and other electronic products. Solid-
state drive (SSD), which is a substitute for hard disk, use multiple NAND flash to
41 Memory Design 791

Fig. 41.13 Threshold voltage UT distribution of SLC and MLC

build up a high-volume storage device with the advantages of shock resistance, fast
speed, noise-free, and low-power consumption.
According to the number of bits stored in a single cell, flash is divided into single-
level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), and so on. The VT
distribution of SLC and MLC are shown in Fig. 41.13. An SLC flash cell stores only
one bit. In order to achieve higher storage density, the threshold voltage of flash cell
is programmed into multiple levels to store more than one-bit data. At present, MLC
(storing 2 bits per cell) and TLC (storing 3 bits per cell) can lower the cost per bit of
flash further.
It depends on the accuracy of the UT to be programmed and detected that how
many bits a flash cell can store. The UT of flash cell can be identified by applying
different voltages on corresponding word line. Therefore the bit line discharge
current flowing through flash cell (ICELL) is different. The UT value can be judged
by sensing the ICELL current value. A NAND flash cell current sensing circuit is
demonstrated in Fig. 41.14. First, the node UOUT is pre-charged to UDD, and the bit
line is charged through the transistor MN. Because the gate voltage of MN is U1, the
bit line is charged to the voltage U1UTHN. Then MN closes and the node UOUT
stops charging. When the string in cell array is opened, the bit line starts to discharge,
and the gate voltage of the selected cell in string is UREAD. Finally, the MN gate
voltage is U2. If UBL < U2UTHN, MN is turned on and UOUT is pulled to a low
level, indicating the threshold voltage of cell UT < UREAD; otherwise, when MN is
turned off, UOUT keeps a high level, indicating the UT > UREAD. The accuracy of U1,
U2, and UREAD voltages directly determines the accuracy of cell threshold voltage
detection. It is necessary to carefully design the voltage generation circuit.
Retention time, which indicates how long flash cell can maintain the data, is one
of the most important features about flash reliability. Actually, the charge on the
floating gate will gradually leak out due to defects in the insulating layer around
floating gate. Manufacturers usually guarantee a retention time of 10 years. Endur-
ance is another important feature of flash. The cell program-erase cycle time is
limited due to several reasons: First, the cell gate oxide will be gradually damaged
after high-voltage operations. Second, the coupling interference between adjacent
floating gates becomes more serious as the process feature size is shrinking. The
792 F. Bai et al.

Fig. 41.14 NAND flash cell current sensing circuit

typical value of SLC endurance is about 100,000 cycles, and that of MLC can be
10,000 cycles or even lower. Charge trap flash cells, which eliminate the coupling
interference between neighbor cells, can improve the cell endurance by technology
invention and make it possible to keep on shrinking flash process down to 1x nm. On
the other hand, the flash chip design can also contribute to maximum the flash
endurance by adjusting the voltage and time length of high-voltage operation,
introducing verification and prohibition programming mechanism, etc.

3D NAND Flash Memory

Compared with traditional flash memory of planar NAND (also known as 2D NAND),
3D NAND flash Memory, whose memory string is three dimensional, can greatly
improve capacity and reduce cost. 2D NAND has encountered reliability and perfor-
mance issues when process is scaled down to less than 1x nm, see Fig. 41.15.
In contrast, 3D NAND uses new ideas to solve this problem. It stacks more layers
on relatively old processes. This technology not only improves capacity but also
ensures performance and reliability. Figure 41.16 is a schematic of a 3D NAND
array circuit, which stacks the memory cells in the direction perpendicular to the
silicon wafer, thus greatly increasing cell density on silicon wafer. SSL (string select
line) determines the selection of one of the multiple cells connected to the same BL;
CSL (common source line) is the common ground of the whole array cells, the
41 Memory Design 793

Fig. 41.15 NAND flash process trend

Fig. 41.16 3D NAND array

current flows from array cell via BL to CSL when in read operation; while GSL
(ground select line) decides if the memory array series is conducting to ground.
3D NAND stacking can be divided into three types: simple stack, vertical
channel, and vertical gate. The memory cells use floating gate (FG) or charge trap
flash (CTF) technique. Compared with FG, CTF is more reliable, smaller, and more
794 F. Bai et al.

Fig. 41.17 3D NAND cross-section

suitable for 3D NAND. A 3D NAND using vertical channel structure based on CTF
is shown in Fig. 41.17. The insulator dielectric layer surrounds the polycrystalline
silicon channel, and the control gate surrounds the insulator dielectric layer. This
design increases the physical area of charge storage, eliminates the coupling inter-
ference between cells, and improves the cell performance and reliability. The stack
layer number of 3D NAND is increasing with the technological progress. The
stacking layer of 3D NAND has increased from 24 layers to 48 and 64 layers in
2016 and 2017, and further increased to 96 and 128 layers in 2018 and 2019; the
MLC 3D NAND can reach up to 128 Gb, TLC can be up to 256 Gb or more.
Combined with multichip stacking and wire bonding technology, flash component
with higher capacity can be realized.
3D NAND is one of the most popular technologies in memory industry. As the
demand for storage is increasing and the cost per bit of 3D NAND is decreasing, the
solid-state hard disk market using 3D NAND is gradually replacing the traditional
mechanical hard disk. At present, Samsung, Toshiba, Hynix, and Micron have
produced their own 3D NAND. In addition, with the support of the National
Integrated Circuit Fund, Yantz Memory Technology (YMT) at Wuhan China has
also developed 64-layers 3D NAND flash memory with the new Xtacking™ tech-
nology in 2019.

FeRAM

Ferroelectric random access memory (FeRAM or FRAM) is a storage technology

based on “programmable ferroelectric capacitor.” FeRAM usually adopts 1T1C cell
structure, as shown in Fig. 41.18. The difference between ferroelectric capacitor and
41 Memory Design 795

Fig. 41.18 FeRAM 1T1C cell and sensing principle

Fig. 41.19 FeRAM program principle

general capacitor is a crystalline ferroelectric crystal film deposited in the middle of

the two electrode plates. The position of central atom in the ferroelectric crystal
represents the polarity of the direction of polarization for digital data “0” or “1.”
As shown in Fig. 41.19, when an electric field is applied to the ferroelectric
crystal, the central atom moves under the action of the electric field. When the
electric field is removed from the crystal, the central atom remains in its position with
a stable polarization state. The read operation is to apply a known electric field to the
memory cell, the central atom will not move, when its position is in the place as if
applied electric field would move it to; on the other hand, the central atom would
796 F. Bai et al.

crosses the high-energy level of the middle layer to another position, it will flip into
another stable polarization state, which results in an electric pulse. The contents of
the memory cell can be detected by comparing the electric pulse with a reference
voltage. Because the read operation causes the state of the memory cell to change,
the memory using the ferroelectric film capacitance effect is destructive read out
(DRO) FeRAM. So a write recovery circuit is needed to keep original data after each
read operation. The voltage-mode SA (VSA) is used for sensing data out, as shown
in Fig. 41.18. First BL is pre-charged to 0, then WL is activated to VDD þ VTH (VTH
is the threshold voltage of transistor), and the plate line (PL) is applied with voltage
VDD. When the stored data is 0, CFE ¼ C0, BL voltage becomes V0 ¼ VDD *
[C0/(C0 þ CBL)]; when the stored data is 1, CFE ¼ C1, the BL voltage becomes V1 ¼
VDD*[C1/(C1 þ CBL)], and finally SA is enabled and compared with the reference
potential Vref ¼ (V0 þ V1)/2 to read the data out. WL voltage is maintained until
BL voltage is written back to the memory cell.
There is also a nondestructive read out (NDRO) FeRAM using metal ferroelectric
semiconductor FET (MFSFET) as memory cell which replaces the gate dielectric
layer with a ferroelectric thin film in conventional MOS field effect transistor. The
state of the semiconductor surface is modulated by the polarization state of the
ferroelectric thin film, thereby modulating the conduction state between source and
drain of the transistor to distinguish between digital levels of “0” and “1.” The
polarization state of the ferroelectric thin film will not change during read operation,
thus the stored cell data is reserved.
The advantages of FeRAM are fast speed, low power consumption, several orders
of magnitude higher read and write cycles than EEPROM and flash memory, and it is
nonvolatile, so it is especially suitable for embedded applications, such as in
industrial control and automation, measurement equipment, financial terminals,
and medical wearable devices. Although companies like Ramtron and Fujitsu have
already introduced embedded and stand-alone FeRAM commercial products, they
are limited by high manufacturing cost and poor scalability, and the highest density
of FeRAM is still in the Mb range.

STT-MRAM

Spin transfer torque (STT) magnetoresistive random access memory (MRAM) is a

new type of MRAM technology. Spin-polarized current causes the magnetization
direction of ferromagnetic materials to be reversed, thereby changing the magneto-
resistance. As shown in Fig. 41.20, STT-MRAM storage medium is a magnetic
tunnel junction (MTJ) consisting of three-layer structure: free magnetic layer, barrier
layer, and fixed layer. The stored data is determined by the magnetization direction
of the upper and lower layers of the film. If the magnetization direction is in parallel,
it exhibits a low-resistance state, which represents “1”; otherwise, it exhibits a high-
resistance state, which represents “0.”
41 Memory Design 797

Fig. 41.20 STT-MRAM 1 T-1MTJ cell structure

For the conventional MRAM, the magnetic field generated by the current passing
through the word line and the bit line changes the magnetization direction of the
magnetic film. Since the coercive field is relatively constant, a higher current density
is required when the size of the memory cell is reduced, which makes it difficult to
reduce the size of MRAM. STT-MRAM solves this problem using the current-
induced magnetic switching (CIMS) effect, that is, the spin-polarized current per-
pendicular to the plane of the ferromagnetic layer causes the magnetization of the
ferromagnetic layer to reverse. As current flows from the free layer to the fixed layer,
spin-polarized electrons flow from the fixed layer to the free layer. When the spin-
polarized current is large enough (e.g., beyond the critical current), the device
resistance changes accordingly, to reverse the magnetization direction of the free
layer to be parallel with the fixed layer. The R-I characteristic of this nanomagnetic
multilayer structure based on the CIMS effect is bistable, so the STT-MRAM is
realized by the current-induced magnetic switching (CIMS) effect in MTJ. MTJ has
in-plane MTJ with a magnetic torque parallel to the silicon surface, and another one
more optimized for reducing the write current, perpendicular MTJ with a magnetic
torque to vertical to the surface, is expected to extend below 10 nm.
Unlike the traditional memories, emerging memories such as STT-MRAM,
RRAM, and PRAM typically use a current mode SA (CSA), as shown in
Fig. 41.21. The CSA will limit read margin and speed because of read disturb.
When reading, firstly BL is clamped to URD (URD ¼ Uclamp), and then Ucell is
discharged according to the state of the cell. When the magnetization directions of
the two films are antiparallel, MTJ is characterized by high-resistance RAP,
IAP¼URD/RAP. When the magnetization directions of the two films are parallel,
MTJ is in low-resistance RP, IP¼URD/RP. The reference current Iref ¼ (IAP þ IP)/2,
since IAP < Iref, Ucell > Uref, the final read data is “0,” otherwise it is “1.”
STT-MRAM combines the advantages of high speed of SRAM, high density of
DRAM, and nonvolatile nature of flash. And it has low operating voltage and low
power consumption. Moreover, only two to three masks are needed for fabricating in
798 F. Bai et al.

Fig. 41.21 STT-MRAM

sensing principle

CMOS logic process, so it is very suitable for embedded applications, such as

embedding in FPGAs, CPUs, MCUs, and SoCs. Along with the maturity of pMTJ
(perpendicular MTJ) technology, it will also play a role in the field of data storage.
Therefore, STT-MRAM technology has broad application prospects. From the
perspective of circuit design, the technical challenge encountered by STT-MRAM
is that it is difficult to identify because of the low-resistance window (small tunneling
magnetoresistance) and the wide resistance distribution. In addition, there is read
disturb problem caused by read current. So it is important to focus on reading
techniques that improve resolution and reduce read disturb.
At the IEDM 2016, Samsung reported an embedded 8-Mbit pMTJ STT-MRAM
based on a 28 nm CMOS logic manufacturing process. The R&D team of Hynix and
Toshiba reported the first 4-Gbit stand-alone pMTJ STT-MRAM with a cell area of
9F2, which is very close to the DRAM cell size.
41 Memory Design 799

ReRAM

Resistive random access memory (ReRAM or RRAM) stores data based on the
resistance values of the resistive material. When it is in high resistance state (HRS),
it represents “1,” and when in low resistance state (LRS), it represents “1.” As shown
in Fig. 41.22, the resistive cell uses capacitor-like metal-insulator-metal (MIM) struc-
ture, consisting of a layer of dielectric sandwiched by two layers of metal electrodes.
The mechanism is that bias voltage between the electrodes lead to state change in
dielectric material, conductive filaments are generated (i.e., SET, HRS becomes LRS,
write “1”) or broken (i.e., RESET, LRS becomes HRS, write “0”). Data can be read out
by measuring the resistance value. The metal electrode can be a conventional metal
material, such as Au, Pt, Cu, Al, etc., and the dielectric layer material is a binary
transition metal oxide (TMO), such as the potential candidate hafnium oxide (HfOx)
and titanium oxide (TaOx)). Due to the difference of electrode material and dielectric
material, ReRAM-resistive cell is divided into unipolar and bipolar. Bipolar cell
resistance is related to both voltage amplitude and direction, while unipolar cell
resistance depends only on the voltage amplitude in one direction.
Currently, the structures of the ReRAM memory cell being studied include
one-transistor one-resistor (1T1R, as shown in Fig. 41.22), one-diode one-resistor
(1D1R), and one-selector one-resistor (1S1R) capacitors. The selection transistor in
1T1R can achieve isolation between cells, reducing leakage and alleviating cross
talk problem, but the cell area is too large, so it is ideal for embedded applications
where performance and reliability are prioritized. 1D1R and 1S1R can reach 4F2
(F is the minimum feature size) and are easy to implement cross-point array structure
(cross-point) and three-dimensional (3D) stacking, reducing storage costs signifi-
cantly, so it is very suitable for achieving high-density stand-alone memory. Like
STT-MRAM, ReRAM adopts current-mode sense amplifier (CSA) to identify the
cell resistance value by applying a small read voltage on BL.

Fig. 41.22 ReRAM 1T1R cell structure

800 F. Bai et al.

Compared with flash, ReRAM has the advantages of higher speed, lower operating
voltage, longer work life, better miniaturization ability, and easier compatibility of
CMOS technology. Therefore, it has broad application prospects and is considered to
be the most potential competitor of next-generation nonvolatile memory (NVM)
technology. First of all, ReRAM is ideal for embedded applications, its simple device
structure makes the fabrication process relatively simple, requiring only one to two
additional masks, and the material and integration process is fully compatible with
standard CMOS processes. Secondly, with the maturity of 3D integration technology
and the application of multilevel storage technology, it is still expected to become an
important technology for large-capacity storage, which is widely used in many
industrial fields, such as data computing and storage system. Furthermore, it has
good anti-irradiation property for medical and aerospace applications. Of course,
ReRAM has its own shortcomings. Because its physical mechanism is based on defect
with poor controllability, it has poor device uniformity. This poses severe challenges in
terms of device structure, integrated process technology, and circuit design technology.
Based on its advantages, industry and academia have done a lot of research work
on it. Many companies have made important reports at IEDM, ISSCC, and VLSI
conferences, but currently only Panasonic and Fujitsu have related products for
embedded applications.

PCRAM

Phase change random access memory (PCRAM or PCM) stores data based on the
resistance change before and after a phase change of the material. The chalcogenide
(Ge2Sb2Te5 Ge2Sb2Te5, GST) is a relatively a mature phase change material. It
undergoes a rapid reversible phase transition between crystalline and amorphous
states after thermal excitation. The crystalline state is a low-resistance state,
representing “1,” and the amorphous state is a high-resistance state, representing
“0.” As shown in Fig. 41.23, the phase change memory cell consists of an upper
electrode, a phase change material, a resistance heater, and a lower electrode. The

Fig. 41.23 PCRAM cell structure

41 Memory Design 801

process of phase change material from crystalline state to amorphous state is called
RESET (write “0”). After applying write current, the temperature of phase change
layer rises rapidly due to the heating effect of the electric resistance heater. When the
melting point of the phase change film is reached, part of the material melts, loses the
state of the crystal, and locks it after rapid cooling. The amorphous state is very
stable at room temperature. The process of phase change material from amorphous to
crystalline is called SET (write “1”). When the material is heated to between the
melting temperature and the crystallization temperature, nucleation and crystallite
growth occurs rapidly within a few nanoseconds and the material changes to a
crystalline state. The read operation is implemented using CSA, which identifies
the resistance of the memory cell by applying a small voltage.
Three challenges exist in PCRAM. Compared with SET process, the RESET
process happens at a higher temperature and requires more current and heat, which is
a major obstacle to the reduction of PCRAM size. Further, as the thermal conduc-
tivity of the resistance heater is low, in order to convert electrical energy to thermal
energy to the greatest extent, it is necessary to increase the thermal conductivity; in
addition, the difference between maximum resistance and minimum resistance can
reach several orders of magnitude, which is very suitable for multilevel storage.
However, the R-T curve of the phase change material must satisfy the step-like
shape, and the resistance value of each step remains relatively stable over a wide
temperature range to ensure the stability of the stored data. Therefore, the biggest
challenge for multilevel storage is resistance drift. The resistance is highly correlated
with temperature and the drift reduces read margin and causes read errors. Solving
the above challenges requires a lot of work on memory cell materials and structures,
as well as circuit design techniques.
Phase change memory can be operated in bytes, with fast read and write speed,
good endurance, and nonvolatility. In recent years, many companies have been
working on it, including Samsung, Micron, IBM, and others. In July 2015, Intel
and Micron announced the joint development of 3D X-Point memory technology,
claiming that it is a revolutionary storage technology since NAND came out in 1989,
the speed is 1000 times faster and the endurance is 1000 times longer than NAND
flash, and the storage density is 10 times higher than traditional storage technology.
Currently this technology allows a single chip with two layers to store 128 Gb data.
In the future, the capacity can be further upgraded by improving lithography and
increasing the number of storage layers.

Further Reading
1. T.M. Coughlin, Digital Storage in Consumer Electronics: The Essential Guide, 2nd edn.
(Springer, Stanford, CA, USA, 2017)
2. B. Keeth, B. Johnson, F. Li, R.J. Baker, DRAM Circuit Design: Fundamental and High-Speed
Topics, 2nd edn. (Wiley-IEEE Press, Piscataway, NJ, USA, 2007)
3. S. Oza-Rahurkar, Low Voltage, Low Power SRAM Design: Design Example (LAP LAMBERT
Academic Publishing, Saarbrücken, Germany, 2016)
4. R.P. Tripathi, R.K. Verma, Design of Low Leakage SRAM (LAP LAMBERT Academic Publish-
ing, Saarbrücken, Germany, 2018)
SoC Design
42
Xiaolang Yan, Kai Huang, and Jianyi Meng

Contents
System-on-Chip (SoC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Intellectual Property Core (IP Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
Embedded Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
Peripheral IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
Hardware/Software Codesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
Security Enhancement Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
IC Design for Artificial Intelligence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Abstract
System-on-a-chip (SoC) is an integrated circuit (IC) which implements CPU,
memory, accelerating unit, and some peripheral interfaces into a unique design.
With the continuous improvement of integration, more and more external chips or
IPs are integrated into a single chip. The performance and functions of a SoC
design have become more and more powerful. This chapter introduces the basic
concept of SoC and IP cores. The embedded CPUs, system bus, peripheral IP
cores, interrupt controllers, and software drivers are also introduced. In addition,
the methodology of hardware and software codesign is introduced for realizing a
function with both software and hardware. Finally, the security enhancement
technology in the SoC is introduced to enhance the ability of information security.

X. Yan · K. Huang (*)

Institute of VLSI, Zhejiang University, Hangzhou, China
e-mail: Huangk@vlsi.zju.edu.cn
J. Meng
Department of Microelectronics, Fudan University, Shanghai, China

© Publishing House of Electronics Industry 2024 803

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_42
804 X. Yan et al.

Keywords
System-on-a-chip · IP core · Embedded processor · System bus · Interrupt
controller · Software/Hardware codesign · Security enhancement

System-on-Chip (SoC)

The SoC (system-on-chip) integrates various functional modules, including proces-

sor, memory, and peripheral interface, of an electronic system on one chip [1, 2].
SoC is essentially a complex IC, it boosts design efficiency with increasing chip
scale and complexity, that is more highly integrated than application-specific inte-
grated circuit (ASIC). A typical SoC is shown in Fig. 42.1 and comprises processor,
memory, and various peripheral functional modules (IP cores), which are
interconnected by system bus.
SoC design tasks include such technologies as integration of IP cores, hardware/
software codesign, system functional verification, design for testability, and
low-power design. IP literally means intellectual property, and IP cores in SoC
refer in particular to circuit modules dedicated for specific functions. IP cores can
be entirely reused by different designs, or be sold as a whole to a third party. The
reusability of IP cores means the practice of directly integrating proven IP cores into
SoC, which significantly shortens the design and development cycle.
The hardware-software co-design technology means the technology of defining
reasonable hardware and software architecture in accordance with system applica-
tion requirements, and main indicators to be considered include cost, performance,
power consumption, and memory architecture. Connecting circuits among IP cores
and among functional modules in SoC are referred to as glue logic.

Fig. 42.1 Typical SoC

42 SoC Design 805

System functional verification means the process of employing such methods as

simulation to check whether actual operation of the system meets defined require-
ments and help designers to better improve products. The DFT (design for testabil-
ity) technology is used to identify errors in the chip-making process and tell
defective chips from normal chips and generally includes the scan chain technology,
memory self-test technology, and boundary scan technology.
The low-power design technology is designed to reduce the power consumption
of SoC in various aspects and generally include clock gating technology, multiple
voltage domain technology, power gating technology, and voltage and frequency
scaling technology.
There are many types of SoC, e.g., single-core and multicore SoCs according to
the quantity of processors in SoC. Single-core SoCs are used in application aimed
only for controlling. Multicore SoCs are used in application scenarios such as large-
scale computing and stream media processing. If classified according to reliability
levels, SoC can be a high-reliability SoC and a consumer-grade SoC. High-reliability
SoCs are generally used in such fields as aerospace, military, industry, and automo-
bile,while consumer-grade SoCs are used for consumer electronics. In terms of
hardware logic programmability, SoC can be further divided into hardware program-
mable SoC (PSoC) and traditional hardware nonprogrammable SoC. Due to adop-
tion of the hardware programmable logic technology, hardware programmable SoCs
possess hardware programmability, flexible design methods, and reconfigurable,
extensible, and upgradeable functions, and has the in-system programmability of
hardware and software.

Intellectual Property Core (IP Core)

The intellectual property core (IP core) means a circuit module that is applied in SoC
and whose specific functions can be reused, and it has such features as standardiza-
tion and tradable. IP cores are generally well-developed circuit modules that have
been proven in industrialization and can be directly integrated by SoC designers into
chips to shorten the design and development cycle significantly. Because numerous
design techniques especially intellectual properties are adopted, IP cores play the
role as an intellectual property carrier. In modern SoC design methods, designers are
able to carry out SoC designs including digital/analog IC and modules like field
programmable gate array (FPGA) on the basis of IP cores. One SoC architecture
based on IP core is illustrated in Fig. 42.2.
In terms of the form of delivery, IP cores can be divided into three types, i.e., soft
core, hard core, and firm core. (1) Soft core is a process irrelevant design code
described by the register transfer level (RTL) hardware description language (HDL).
Soft core is based on the description of IP core functions and subjected to behavior-
level design optimization and functional verification, and can be flexibly applied in
various processes. (2) Hard core is the physical realization layout of soft core after
logic synthesis, and placing and routing, and takes such forms as mask layout of
physical structure of circuits and a full set of process files required for application.
806 X. Yan et al.

Fig. 42.2 One SoC architecture based on IP cores

Fig. 42.3 Characteristics and

requirements on packaging
and reusability of IP cores

The advantage of hard core is that circuit placing and routing is bound together with
specific process, thus ensuring such requirements as performance and power con-
sumption and shortening SoC design time; its disadvantages are poor flexibility and
difficult process transition. (3) The form of firm IP core ranges between that of soft
core and hard core, and firm core is generally delivered in the form of gate-level
netlist. The final placing and routing of firm cores is generally done by the user, so
the shape, size, and port location of such cores can be changed. Therefore, firm IP
cores have higher flexibility than hard cores.
The reusability of IP cores is an effective methodology to boost SoC design
efficiency. In order to enable the reusability of IP cores in different systems, the key
is to conduct the packaging of IP cores. The characteristics and requirements of IP
core packaging and reusability are shown in Fig. 42.3. IP core packaging requires the
description of IP core’s complete information in different aspects, including config-
uration files, definition of signal port, bus type, and register address allocation. In
order to ensure the reusability of IP cores, any information generated by IP core shall
42 SoC Design 807

meet the reusability standard. The compatibility of such information with EDA tools,
hardware and software library, and hardware design platform shall be checked, and
the quality and reusability level of IP core shall be evaluated.
IP core packaging generally obeys the following three principles. (1) Normaliza-
tion principle: unify design specifications of IP core, e.g., regulate interface signal
according to specific naming rules, unify reset modes, and regulate coding styles.
Normative design assists subsequent use of IP and reduces introduction errors during
system integration. (2) Simplification principle: gradually break down complex
functional modules into a number of specific modules with unitary function. Gen-
erally speaking, simple designs can be more easily understood and integrated by
third parties, which can reduce the introduction problems during designers’ design
and verification. (3) Localization principle: define functions within a number of local
modules whose functions are mutually independent and orthogonal, and define
explicit interfaces among modules. Localization design combines key indicators
including function, cost, power consumption, and timing with independent modules,
and forms complex IP cores by splicing those modules. In summary, the interna-
tional IP core standardization bodies including VSIA (Virtual Socket Interface
Alliance), OCP-IP (Open Core Protocol International Partnership), and SPIRIT
(Structure for Packaging Integrating and Reuse IP in Tool Flow) are working hard
on the standardization of IP cores to increase the packaging and reuse efficiency of
IP cores. The IP core standardization organizations are alliances set up by the SoC
design industry to address the inconsistency of IP core packaging interfaces encoun-
tered in the SoC design process.
Depending on different types of signals to be processed, IP cores can be divided
into digital and analog IP cores. Among others, digital IP cores can be further
divided into processor IP cores and peripheral IP cores: processor IP cores include
Cortex series from ARM, MIPS32 series from MIPS, and CK series from C-SKY,
while peripheral IP cores include DDR, PCIe, DMA, SPI, IIC, and UART. Analog IP
cores include ADC, DAC, LDO, and PLL. Companies like Synopsys and Cadence
can also supply analog IP cores.

Embedded Processor

Embedded processor is the IP core “embedded” in SoC responsible for running

software program, and is the control and computing core of SoC. Embedded
processor is generally a low-power, low-cost processor. SoC’s requirement for
embedded processor is a comprehensive balance of performance, power consump-
tion, and cost. Working power consumption of embedded processor represents the
bulk of SoC’s dynamic power consumption. In battery powered systems, the amount
of power consumption of embedded processor directly determines the battery time of
the whole embedded system. In addition, SoC’s cost control is strict and reducing
hardware cost of embedded processor is SoC’s specific requirement. Embedded
processor generally adopts the reduced instruction set computer (RISC) architecture,
which has numerous single-cycle instructions and simple pipeline architecture. The
808 X. Yan et al.

embedded processor design principle is as follows: simplify the design as much as

possible while retaining the functions meeting application requirements, and mean-
while carry out design enhancements in such aspects as processing capability,
adaptability, and reliability depending on different application scenarios.
At present, mainstream embedded processor architectures include ARM, MIPS,
Tensilica (of Cadence), and ARC (of Synopsys); and CK series by C-SKY in
Hangzhou, M* core and IBM PowerPC by C*core in Suzhou. Nowadays, main-
stream embedded processor generally adopts 16-bit/32-bit instruction set, 32-bit/
64-bit data path, and load/store memory architecture, whose basic instruction set
adopts simple, direct instruction encoding method with simple functions and can
conduct customization and extension for specific applications. Embedded DSP
processor is a type of processor specially used for signal processing and is generally
developed through customization of DSP processor or addition of DSP coprocessor
to general-purpose processor. Its architecture and instruction algorithm adopt special
design. Embedded DSP processors currently in wide use include CEVA DSP
processor and Verisilicon ZSP processor.
There are generally two development trends of embedded processor: firstly, high
performance, e.g., mobile phone–embedded processor and the typical products are
ARM Cortex-A processor series; secondly, low power and low cost, e.g., embedded
processor used in IoT (Internet-of-Things) field, and ARM Cortex-M series are
currently used widely. Embedded processors are generally operated through IP
core licensing, ARM provides embedded processor IP core series and is now the
world’s largest supplier of IP cores by revenue. In recent years, a number of open-
source free processor IP cores have been emerging. A typical representative is RISC-
V led by University of California Berkeley, which can provide basic instruction set
architecture (ISA) and reference prototype design.

System Bus

The system bus is a public hardware channel for communication and interconnection
among various devices (e.g., embedded processor, memory and peripheral IP cores)
in SoC, and it provides an interconnection mechanism for devices to access shared
hardware and undertakes the task of data transmission in the digital system.
Depending on their different functions, devices connected by system bus are
divided into master devices and slave devices. (1) Master devices mean devices that
can initiate transaction tasks actively. For instance, a processor may control periph-
erals and read/write data through bus; some peripherals may also access other
peripherals and read/write data through bus. (2) Slave devices are devices that
respond to transaction tasks initiated by master devices. For instance, memory
may respond to master device’s read operation and return read data. In addition,
some devices may actively initiate an access to the bus as master devices, and may
also respond to bus transactions as slave devices.
42 SoC Design 809

SoCs are generally designed with many master devices and slave devices.
Different slave devices correspond to different nonoverlapping address areas on
the bus, and the bus initiates target address of transaction task through master
devices. Different bus protocols are designed with different master device access
modes. For instance, according to Advanced Microcontroller Bus Architecture
(AMBA) 2.0 protocol, the devices on the same advanced high-performance bus
(AHB) or advanced system bus (ASB) share a fixed address and data transaction
channel. This means that when a master device occupies the AHB bus, all other
master devices are in a waiting state. However, advanced extensible interface
(AXI) bus in the AMBA 3.0 protocol uses different ID numbers to distinguish
master devices, and a particular master device may initiate a request while the
access by other master devices is not completed. A SoC architecture based on
AMBA 2.0 bus as shown in Fig. 42.4. AHB bus connects high-speed devices like
embedded processor and memory, while advanced peripheral bus (APB) connects
low-speed devices like serial ports and timer. Bus arbitration mechanism includes
polling mechanism and priority mechanism. While transmitting data, the bus may
adopt different transmission types to adapt to transmission requirements at
different lengths and rates. As a master device in the system, the high-
performance ARM processor may access high-bandwidth external memory inter-
face and high-bandwidth on-chip RAM through AHB bus, and may access
low-speed devices on APB bus like UART, keyboard, timer, and PIO through
AHB to APB bridges.
Depending on different working frequencies, buses are designed as high-speed
buses and low-speed buses: high-speed buses support high clock frequency and
have high data bandwidth and performance with rather high power consumption,
and they are generally used for connecting high-speed devices like CPU and
DMA; low-speed buses have low working frequency, poor performance, and low
power consumption, and they are suitable for connecting low-speed peripherals
like keyboard and serial port. High-speed buses and low-speed buses may
communicate with one another through bridge. Nowadays, influential buses

Fig. 42.4 One SoC architecture based on AMBA 2.0 bus

810 X. Yan et al.

among SoCs in the industry include AMBA bus, CoreConnect bus, Wishbone
bus, and OCP bus, etc.

Peripheral IP Core

Peripheral IP core refers to the generic terms of peripheral function IP core other than
the embedded CPU in a system-on-a-chip (SoC), including the serial bus interface,
memory controller, etc. Peripherals are generally connected with processors through
buses and usually the slave devices of the bus. After receiving an instruction from the
processor, the peripheral offers a specific function. As an important part of SoC, the
peripheral assists the processor in completing the control, computing, and other
tasks, which increases the work efficiency of the processor.
The peripheral generally works under the control of processor, and the processor
manages the peripheral through reading/writing the peripheral’s registers. The
peripheral registers generally include two categories: The first category is the control
register, and the processor writes the configuration of such registers to achieve the
control of peripherals; the second category is the state register, and the processor
knows the current working state of the peripheral through reading this type of
register.
According to function classification, there are four types of common peripherals.
(1) General data transfer protocol interface peripherals, such as I2C, SPI, UART,
MAC, USB, etc., and these peripherals carry out data receiving/sending according to
a data transfer protocol. (2) General control peripherals, such as a general-purpose
I/O interface (GPIO), a pulse width modulation interface (PWM), etc., which may
perform special control over the pins. (3) Accelerator-type peripherals, similar to the
coprocessor, accelerating the specific type of computing, such as image codec, high-
speed encryption, and convolution operation. (4) System function peripherals,
helping the processor to complete the system operation function of SoC, and
ensuring the correct execution of the application, such as a timer and an interrupt
controller.
According to the speed classification, common peripherals are divided into the
high-speed peripheral and the low-speed peripheral. (1) The high-speed peripheral
performs complex tasks or computing with high working frequency, such as image
processing accelerators, high-speed encryption and decryption engines, and high-
speed communication interfaces. (2) The low-speed peripheral is generally respon-
sible for low-speed communication of SoC with the outside, and maintaining the
SoC system function with low working frequency, such as I2C and INTC.
With the increase in peripheral types and improvement of performance, to
match the speed, timing, and format between the peripheral and the processor,
the peripheral has gradually developed into a circuit with the independent control
units and interfaces. With the increasing diversity of peripheral function and the
more demand of performance requirements, how to design a peripheral which is
highly reliable, simple to control, smart, and easy to extend becomes the future
development trend.
42 SoC Design 811

Interrupt Controller

Interrupt refers to a hardware request signal to the processer generated by the

peripheral IP core in SoC, the peripheral requests the processor to suspend the
currently executing task and to perform a specific task required by the peripheral.
In interrupt mode, the processor can directly run other tasks after sending a task
command to the peripheral, and handle the interrupt when an interrupt request
arrives, avoiding unnecessary waiting, and increasing the parallelism between
tasks. The generation and processing flow of an interrupt are shown in Fig. 42.5.
Interrupt response and processing flow: After receiving an interrupt signal, the
processor immediately stops the program currently being executed, save the current
state of the processor and program counter, and then enter the interrupt service
routine, and then resume original program after handling the interrupt. One interrupt
service routine corresponds to one interrupt source, and each interrupt source has its
specific interrupt service routine. In the interrupt service routine, a processor gener-
ally needs to carry out the work in three parts: the first is save context, i.e., in order to
return correctly after interrupt handling, the processor status and the program counter
prior to execution of special tasks that an interrupt source requests are saved; the
second is to parse the current interrupt and perform a corresponding action; and the
third is to restore context and then return to the program prior to interrupt.
The interrupt controller is an IP core in SoC used for the interrupt source
collection, masking, and priority management. The component generating an inter-
rupt signal is referred to as the interrupt source, and the interrupt generated by the
interrupt source is divided into the level interrupt and the pulse interrupt: the level
interrupt generates one continuous valid level when the interrupt occurs and the valid
level is maintained before the interrupt is cleared; one valid pulse is generated when
the pulse interrupt occurs, the pulse is not maintained, and the interrupt controller
needs to capture and record the pulse interrupt. In the case that the system application
does not need concern over a certain interrupt, the interrupt generated by the

Fig. 42.5 Generation and handling flow of an interrupt

812 X. Yan et al.

interrupt source can be masked before being passed to the processor. The interrupt
can be masked by setting the interrupt bit to be invalid in the interrupt controller.
Both the system module and the peripheral may generate an interrupt, and if multiple
interrupt sources generate an interrupt simultaneously, the processor core cannot
respond to all interrupt requests at the same time. Therefore, in the case when
multiple interrupts occur at the same time, interrupt shall be handled in some
order, which means allocating the priority for different interrupts. An interrupt
with a high priority is handled first, and that with a low priority is handled later.

Driver

Driver is a special kind of infrastructure software that enables application software to

communicate with hardware. Its function is to provide calling interface for upper
software to control the work of hardware device. Firmware is a kind of driver that is
fixed in the hardware by hardware vendors.
The software and hardware architecture of SoC can be divided from bottom to top
into hardware device, hardware driver, and upper software. And the hardware driver
can be divided into hardware-dependent layer (HDL) and hardware abstraction layer
(HAL), as shown in Fig. 42.6a. As an important part of the system architecture, the
hardware driver mainly offers following functions: initialization and reset the equip-
ment; read the request data transmitted by the upper software to the hardware device
and return the response data of the hardware device; and detect errors and handle
interrupts.
Given a close connection with hardware devices, hardware drivers are usually
provided by SOC vendors, which program the hardware driver based on the char-
acteristics of the hardware. The interfaces and functions of hardware drivers needed
to be realized are determined by hardware characteristics. From the perspective of
the SOC software framework, at a lower level, the hardware driver controls the
operation of hardware device, and, at a higher level, it provides the standard calling
interface to facilitate the upper software to use. For the upper software, hardware
drivers are like independent black boxes, whose function is to enable specific

Fig. 42.6 Block diagram of the software and hardware (including firmware) architecture of SoC
42 SoC Design 813

hardware to provide services for the upper software in a standardized application

interface manner, hiding the details of the operation of the device in the process of
working. As long as the driver layer calls the same interface, software designers can
make the application run on different hardware, and hardware designers can con-
stantly upgrade the hardware without affecting the old software’s running on the new
device. When the upper software needs to use a certain hardware function, it will first
send corresponding instructions to the peripheral driver, which, after receiving the
instructions, will translate them into electronic signal commands that the peripheral
controller can understand.
In an operating system, the hardware-dependent layer (HDL) is usually provided
by hardware vendors in the form of firmware, while the hardware abstraction layer
(HAL) is integrated into the operating system, and is provided by operating system
vendors in the form of standard device driver, as shown in Fig. 42.6b. Currently, the
Windows and Linux operating systems which have leading market shares both
integrate the HAL in their system kernel. However, the upper interfaces of device
drivers of different operating systems are not the same, and the firmware interfaces of
different device vendors are also different. As a result, software developers cannot
choose device vendors at will. In the future, standard device driver interface and
firmware interface will be further standardized to enable software developers to
seamlessly switch between devices from different device vendors.

Hardware/Software Codesign

Hardware/Software codesign and co-optimization (HSCO) refers to the process of

hardware and software conduct defining and developing together during the cycle of
SoC development. When defining SoC, specific functions can be realized either by
processors running software or by using specific hardware. Software implementation
offers flexibility and scalability, but is less energy efficient; hardware implementa-
tion allows high-energy efficiency, but once the design is finished, changes cannot be
made. Through the HSCO, we can quantitatively study the advantages and disad-
vantages of the software-based and hardware-based implementation approaches for
each component in the system, so as to find out the optimal solution to SoC design.
Thus, hardware/software codesign and co-optimization (HSCO) is a basic design
methodology of SoC.
Hardware/Software codesign can be divided into three stages, namely hardware
and software partitioning, hardware and software cosimulation and verification, and
hardware and software synthesis, as shown in Fig. 42.7.
The hardware and software partitioning is to divide functions at the system level,
with some of the functional modules of the system through hardware implementation
and some through software implementation. When dividing the hardware and
software functions, design developers should take into account of a variety of
factors, such as the development time and costs of the system and the available
resources on the market. In the SoC development and design process, the hardware
814 X. Yan et al.

Fig. 42.7 Hardware/Software codesign (HSCO) process

and software partitioning is a complex and difficult process, and is the most
important part in the development and design of SoC.
Hardware and software cosimulation and verification is to verify and evaluate the
correctness and performance of hardware and software functional design. In tradi-
tional design, hardware and software are usually developed and designed indepen-
dently. Then, at the later stage of the system design, the hardware and software are
integrated together for verification. In the case of codesign, hardware and software
are designed interactively, and the system’s software and hardware verification can
be carried out at every stage of the design. The purpose of simulation and verification
is to use the simulation and verification system to discover problems in design as
early as possible in the early stage of design, so as to avoid alteration in the later
stage of system design, since that may cause waste of time and more costs.
Hardware and software synthesis is a process to transform high-level hardware
and software description into low-level software and hardware implementation. Its
42 SoC Design 815

main task is to study and utilize all kinds of hardware and software resources
provided by the system under the constraints of system design, and realize the
final hardware and software system on the basis of meeting the requirements of
system design performance.
Study on the methodology of hardware software codesign began in early 1990s,
and then it grew rapidly. At present, the hardware/software codesign methodology is
widely used in SoC design. A complete set of SoC hardware and software codesign
and verification can be provided based on ARM’s RVDS (Real View Development
Suite), Cypress’ PSoC Creator IDE, and Synopsys’ Virtual Platform.

Security Enhancement Design

Security enhancement design refers to the use of specific design methods and
technologies to enhance the security protection capabilities of integrated circuits.
Security protection involves the whole hardware and software system. Different
from security technology at software level, IC’s security enhancement design refers
to the defensive design for side-channel attack (also known as SCA), which are
applied to cryptographic chips and on-chip security systems. SCA refers to a series
of attack methods aiming at the acquisition of sensitive information from
the realization of hardware and software of cryptographic algorithm, and from the
physical supporters of the realization. According to the different sources of side-
channel information, SCA can be classified into time attacks, power consumption
attacks, electromagnetic attacks, sound attacks, fault injection attacks, etc. These
attack methods are great threat to the security function of the chip. Only when the
security of themselves are ensured, can these chips truly provide security services for
the information society, realize identity authentication, maintain data security, and
construct a trusted and reliable network.
Security enhancement design is based on three basic principles to counter side-
channel attacks [3]. (1) Randomization: By some measures, the time, power con-
sumption, electromagnetic, sound, and other information of cryptographic chip are
randomized, which makes it hard for attackers to carry out data statistics and
correlation analysis. (2) Blindness: Due to mathematical and algorithmic design,
the attacker will lack critical additional information, cannot predict the sensitive
content of the cryptographic calculation process, and cannot carry out the
corresponding side-channel analysis. (3) Masking: The cryptographic chip masks
the intermediate results of cryptographic operations by generating random numbers
as the mask, while the final results of operations can be correctly recovered. Masking
results in strong randomness of intermediate results and the difficulty of statistics and
analysis of side-channel information increases dramatically.
At present, security enhancement design technologies at algorithm level, archi-
tecture level, and circuit level have been studied and developed. For symmetric and
asymmetric cryptography, corresponding anti-attack algorithms are developed in the
algorithmic structure, which can eliminate and hide the side-channel information that
may be leaked. The anti-attack algorithm will introduce some redundant operations,
816 X. Yan et al.

which will result in additional burden on the performance and power consumption of
cryptographic chips. Security enhancements can be designed for microarchitectures
of CPUs and cryptographic accelerators, such as repairing vulnerabilities of the
microarchitecture, adding security instructions and special hardware units, which
can effectively suppress many side-channel attacks. On the other hand, a new type of
circuit logic which is highly secured can be proposed to fundamentally solve the side
information leakage caused by unbalanced power consumption of CMOS comple-
mentary logic. However, much antiattack circuit logic has the problems of large area
and high-power consumption. How to balance capability of anti-attack and cost of
implementation is also an important research area. As shown in Fig. 42.8, the
implementation of chip security enhancement requires systematic and cross-level
design techniques, so as to establish security barriers at all design levels and prevent
attackers from using vulnerabilities and side-channel information at any level to
threaten the security of the core part of the chip.

Fig. 42.8 Multilayer security enhancement design technology

42 SoC Design 817

The emergence of security enhancement design is closely related to the rapid

development of SCA technology. The differential power attack method proposed by
Professor Paul Kocher in the 1990s [4] is a milestone in the history of side-channel
attacks. Since then, academia and industry have fully realized that cryptographic
chips must have measures and technologies to defend against side-channel attacks,
thus giving birth to the technical direction of security enhancement design. Infineon,
NXP, and other companies have accumulated strong technical strength in security
enhancement design, which has made their chip products have anti-attack charac-
teristics. In recent years, China has made great progress in the security enhancement
design of cryptographic chips. Relevant IC design companies in China have devel-
oped smart card chips with certain defensive ability against attacks, and have formed
corresponding technical capabilities in security protection. With the vigorous devel-
opment of Internet and IoT technology, the problem of network space security has
become increasingly prominent, and the importance of chip security enhancement
design has become increasingly critical. In the future, not only IC design entities, but
also various network technology companies and Internet operators will contribute to
the important issue of improving chip security. The technology of security enhance-
ment design will continue to develop. At the same time, the industry will develop
and improve the whole process automatic detection equipment and integrate devel-
opment environment for chip protection. The security enhancement design through
the whole process will integrate the key technologies of each level and single point
into an organic entirety to maximize efficiency, and pay attention to the collaborative
development of hardware carrier and software environment to enhance the level of
automation and intelligence and ensure a good user experience.

IC Design for Artificial Intelligence

At present, artificial intelligence (AI) has become one of the most popular hot spots.
AI in research and application fields make computers have capabilities similar to
human intelligence that makes meaningful judgments on the input of the environ-
ment through research and development of computers. The factors that determine the
quality of AI are usually the computing power and the amount of data. The way to
achieve AI is adopting machine learning (ML), which allows the machine to
gradually approach the effect we hope to achieve through training and learning.
With the rapid growth of processors’ computing power and data volume, the way of
machine learning is also undergoing revolutionary changes, and the concept of deep
learning (DL) has been introduced. Deep learning enhances its nonlinearity through
its multilevel morphology, which can lead to stronger fitting ability. In addition, it is
similar to the process of layer-by-layer automatic extraction of features from bionics,
which guarantees the quality and richness of the extracted features, which improve
its performance when compared with traditional ML algorithms.
With the development of the algorithm model, the performance of the model is
gradually improved, and the depth and complexity of the model itself is greatly
increased. Taking the ImageNet Large-Scale Visual Recognition Challenge
818 X. Yan et al.

(LSVRC) as an example, released by Alex Krizhevsky of the University of Toronto

and his mentor Geoffrey Hinton, AlexNet won the championship with 83.0% Top5
classification accuracy in 2012, and its performance has increased by more than 10%
compared to the previous traditional model. AlexNet itself is a convolutional neural
network with a five-layer convolutional layer and a three-layer fully connected layer,
containing 61 million weight parameters and 7.4 billion multiply-accumulate oper-
ations. By the year of 2017, the most complex network model layer has more than
1000 layers, the weight parameters and the number of multiplication and addition
operations are several orders of magnitude higher than AlexNet, and the recognition
accuracy that can be achieved has surpassed that of human. AlphaGo, which recently
defeated many human Go masters, its complex decision-making model requires
more than 1300 CPUs and 280 GPUs to provide computing power in its first version
of the distributed implementation that defeated Li Shishi. It can be seen that, to meet
the strict power consumption and real-time requirements of the increasingly complex
artificial intelligence algorithms, a powerful processor is needed as a support;
therefore, the refined design of the processor chip is the necessary condition for
application requirements of improving and satisfying the computing performance of
the chip.
Generally speaking, for AI, whether it is model training or forward inference, the
computing speed of the processor chip is an indicator that needs to be considered
first; and in some low-power scenarios such as application in embedded mobile
devices, the hardware power consumption also needs to be strictly controlled.
Traditional CPUs are stretched out when facing data and computationally intensive
artificial intelligence algorithms due to their serial execution. Therefore, increasing
the parallelism in processor computing is a major direction of performance improve-
ment. NVIDIA proposes the concept of general-purpose GPU (GPGPU) computing,
which applies GPUs with a large number of parallel computing stream processors to
the development of AI algorithms, and provides mature and stable software envi-
ronment support such as CUDA (Compute Unified Device Architecture) and
cuDNN (Compute Unified Deep Neural Networks). Due to the powerful computing
power of the GPU, the GPU has been widely used in model training scenarios
focusing on model accuracy and data center, and server environment. But we also
noticed that common GPU boards consume up to 200–300 W, which limits their use
in low-power scenarios. Therefore, considering the application scenario and the type
of algorithm, the internal architecture of the chip is customized to improve the
overall energy efficiency ratio of the chip, which becomes another mainstream
direction for the development of artificial intelligence chips.
Generally speaking, for a certain type of AI algorithm, it often has a partitionable
characteristic, and the divided subalgorithm blocks have certain similarities. Taking
the convolutional neural network which is commonly used in image applications as
an example, the most densely convolved convolution layer can be abstracted into a
sliding window type multiplication and addition operation, and the size and stride of
the sliding window and the number of calculation channels can be abstracted as
configurable parameters. In hardware architecture design, the computation path and
the storage structure are usually customized and configurable for the algorithm in
42 SoC Design 819

consideration of the way of it is divided and abstracted. Most researchers will

quickly and iteratively develop accelerated hardware structures using FPGA chip
implementations. A number of research institutions have already released FPGA-
based accelerated architecture design at top academic conferences, and industry
companies have begun to deploy common algorithm models in applications through
FPGA acceleration, and achieve good performance and low-power consumption.
Next, we can also design the computing and storage cores as an application-specific
integrated circuit (ASIC) to achieve higher-energy efficiency. The outstanding ASIC
chip design known today has been able to control power consumption to the
milliwatt (mW) level with hundreds of GOPS (billion operations per second)
computing power. ASIC has many advantages in high-energy efficiency and low
production cost under the premise of wide application market. However, its one-time
engineering cost and large development cost often have certain risks in the process of
rapid algorithm evolution. Therefore, different platforms should be selected for
different R&D and market needs.
In recent years, algorithm optimization for hardware implementation has also
been evolving, including data quantification, model sparsification, and other tech-
nologies that have progressed, and these technologies have helped reduce the
on-chip computing resources and storage bandwidth limitations of artificial intelli-
gence chips while achieving higher throughput at a lower hardware cost. The
variability of data bit width and the irregularity caused by model sparsity pose a
challenge to the realization of hardware implementation. In the future, the AI chip
design will be more inclined to hardware and software codesign and co-optimization
(HSCO) to achieve more optimized and general solutions.

References
1. W. Fischer, N. Homma (eds.), Cryptographic Hardware and Embedded Systems – CHES 2017,
19th International Conference Taipei, Taiwan, September 25–28, 2017 Proceedings. Springer
2. P.C. Kocher, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other
Systems, in CRYPTO, (1996), pp. 104–113
3. H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, L. Todd, Surviving the SOC Revolution:
A Guide to Platform-Based Design (Kluwer Academic Publishers, Boston, 1999)
4. M. Arora, Embedded System Design: Introduction to SoC System Architecture (Learning Bytes
Publishing, Islamabad, Pakistan, 2016)
Programmable Logic Circuit Design
43
Shaojun Wei and Shouyi Yin

Contents
Programmable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Field-Programmable Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Electrically Programmable Logic Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Programmable System-on-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Reconfigurable Computing Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

Abstract
Programmable logic circuit (PLC) has the advantages of high flexibility, short
development cycle, and strong scalability. It is widely used in communication,
industrial control, military, and other fields. This chapter focuses on the PLC
design technology. Firstly, it introduces the main categories and functional
characteristics of PAL, GAL, complex PLD (CPLD), and FPGA. After that, the
hardware description language, system structure, storage mode, and other core
technologies of the representative programmable logic devices (PLD), such as
field programmable gate array (FPGA), electrical programmable logic device
(EPLD), and programmable system chip, are analyzed. Finally, the main advan-
tages and technical features of the state-of-the-art reconfigurable computing chips
in this field are introduced.

Keywords
Programmable logic · PLD · FPGA · EPLD · Programmable system on chip ·
Reconfigurable computing chip

S. Wei (*) · S. Yin

Institute of Microelectronics, Tsinghua University, Beijing, China
e-mail: yinsy@tsinghua.edu.cn

© Publishing House of Electronics Industry 2024 821

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_43
822 S. Wei and S. Yin

Programmable Logic

Programmable logic is a circuit logic that provides multiple functions which can be
implemented by programmable logic devices (PLD). Programmable logic has many
advantages over fixed logic. First of all, the flexibility of the programmable logic is
relatively high, and the required functions can be changed at any time through
programming. Secondly, the development cycle of the programmable logic circuit
is shorter than the fixed logic circuit (such as ASIC), and the development cost is
relatively low; finally, the programmable logic circuit is very scalable, allowing for
later functional updates and upgrades. Fixed logic devices are suitable for massive
large-scale applications, and for some circuits that require very high performance,
fixed logic circuits are more suitable than programmable logic circuits.
The first commercial programmable logic device (PLD) is programmable array
logic (PAL) from Monolithic Memories, Inc. in 1978. In recent years, the market
share of PLD has grown rapidly, and their functions have become more diverse, and
high-performance programmable devices have begun to be popular.
The current PLDs can be mainly divided into three categories. (1) Generic Array
Logic (GAL): Developed on the basis of PAL and invented by Lattice Semiconduc-
tor. GAL has the same characteristics as PAL, but GAL can repeatedly be burned or
clear the circuit configuration and architecture configuration, while PAL can only be
burned once. (2) CPLD (Complex PLD): Compared to PAL and GAL which are
suitable for small logic functions, CPLD can realize a larger circuit. There are
usually several PALs inside a CPLD, and the interconnections between PALs can
also be programmed according to requirements. (3) Field Programmable Gate Array
(FPGA): Based on the technology of gate array, it has been developing with
continuous innovation.
In addition to the logical part, the PLD also contains a storage part. The data
storage carriers are mainly Si anti-fuses, SRAM, EPROM, or EEPROM and flash
memory. The current development of PLD is mainly implemented by computer
programming. The source code is written in hardware description language (HDL).
The hardware description language is best known for VHDL and Verilog HDL.
The development direction of PLD programmable devices is toward high density,
high speed, and low power consumption. As the design of PLDs has grown in size,
electronic design automation (EDA) has become the primary design tool.

Field-Programmable Gate Array

Field-programmable gate array (FPGA) is based on PAL, GAL, and CPLD. It is a

semi-custom circuit that offers lower development cost, expandable functionality,
and more logic cells than full-custom circuits.
At present, the hardware description language (Verilog or VHDL) is used to
describe the circuit logic, which is the mainstream technology for FPGA design
verification, and then the relevant software tools are used to perform logic synthesis,
layout and routing, etc., and then burn the produced files to the FPGA chip.
43 Programmable Logic Circuit Design 823

Although FPGAs are slower and have lower performance than application-specific
integrated circuits (ASICs), they have the advantage of being less difficult to develop
and their internal functions can be modified over and over again. At present, FPGA is
almost a must-have component in electronic systems. This is because the conve-
nience and flexibility of FPGAs help electronic products quickly seize the market.
While field-optimizable CPLDs and FPGAs both contain a large number of pro-
grammable logic cells, their system architectures are greatly different. Compared
with CPLD, FPGA has more connection units; it is more flexible but also more
complicated. CPLD has fewer connection units and the delay time is easier to
estimate. Another obvious difference is that FPGAs have built-in high-level modules
and memories such as adders and multipliers, so many new FPGAs can be
reconfigured within the system.
Currently, the following are mainly the ways to store programs in the FPGA.
(1) Programmable read-only memory (PROM): It can be programmed only once,
and the programmed content cannot be erased. (2) Erasable programmable read-only
memory (EPROM): An erasable and programmable technology that can erase the
content in memory with UV light. (3) Anti-fuse: Usually CMOS circuit and can only
be burned once. (4) EEPROM: Programmable read-only memory technology that
can erase content with electrical signals. (5) Static Random Access Memory
(SRAM): Based on static memory technology, programmable within the system.
(6) Flash: A special type of EEPROM.
Currently, the most well-known FPGA vendors are Xilinx, Altera (now Intel),
Actel (now Microsemi), Lattice Semiconductor, and Achronix Semiconductor. The
inventor of FPGA, Xilinx, is the largest FPGA supplier in the world.

Electrically Programmable Logic Device

Electrically programmable logic device (EPLD) is an erasable programmable logic

device that uses electrical signals.
The design process of EPLD usually has the following main steps:

1. Use schematic diagram or hardware description language to describe the logic.

2. Before the designer writes the designed logic onto the device, it is necessary to
perform verification of the design result, which is generally through computer
software simulation to check whether it meets the design requirements, and this is
called “pre-simulation.”
3. After computer software compiling the logic description into a simplified Bool-
ean algebra expression, the compiler software adapts the specific expression
according to the target device and generate the standard load file (JED file) of
the device. This process is usually referred to as “synthesis.”
4. The logic is downloaded to the device for functional verification.

The logic functions of EPLD devices can usually be designed using schematic or
hardware description languages. The schematic description is very straightforward,
824 S. Wei and S. Yin

and the circuit function is directly used to describe the circuit function. The disad-
vantage is that it is not concise. Commonly used hardware description languages are
Verilog and VHDL. The hardware description language can accurately implement
the logic functions of the circuit. For simulation and synthesis, the most commonly
used tools are ModelSim and Quartus. A programmer is a device that programs a
programmable device. The JED file needs to be downloaded to the device by the
programmer to let the chip work according to the design logic. The process of
programming through downloading means that the computer downloads the JED
file into the programmer and then writes the JED file to the device according to the
characteristics of that device.
EPLDs are a type of PLD that are not yet configured or programmed for a specific
purpose. Typically, an EPLD has an array of initially unconnected programmable
logic devices; to be configured or programmed by the user electrically, they are used
to build reconfigurable devices that can be used in a variety of applications
depending on their programming. EPLDs have an undefined function when they
are manufactured, which is unlike logic gates that already have a defined set of
functions.
There are limited reports on EPLDs in recent years on this technology in the
literature; a research group at Portland State University has used EPLDs from
Cypress Semiconductor for self-testable and self-repairable study as well as for a
routing partition fitting problem [1, 2].

Programmable System-on-Chip

Programmable system-on-chip (PSoC) is an embedded system design solution

developed on the basis of programmable logic devices (PLDs) to meet the increasing
demands of system integration [3, 4]. System designers can switch from previous
board-level system designs to chip-level system designs and implement various
functional units required for design and integrate them into FPGAs in the form of
IP (Intelligent Property), thus achieving high efficiency, flexible, and highly inte-
grated embedded systems.
PSoC features the entire system on a single chip. The design process is to describe
the system function using the top-down method and begins with the top of the
system behavior level, i.e., collaborative design from application function, software
algorithm, chip architecture, embedded operating system, and circuit module to
devices.
The core design technologies of PSoC mainly include the following three aspects.

1. Software and hardware co-design and co-verification technology: to comprehen-

sively trade off the system design metrics, perform software and hardware
function partitioning of complete system functions, and accomplish design
space exploration.
2. IP core generation and multiplexing technology: At present, IP core multiplexing
has become the core technology in integrated circuit design. Through the
43 Programmable Logic Circuit Design 825

inheritance, sharing, and reuse of the IP core, the EDA tool can realize the system
function design, synthesis, and verification, which greatly improves the design
efficiency, accelerates the development process, and effectively reduces the
development risk.
3. System level and inter-module interface design and verification technology:
PSoC has various modules such as software and hardware function modules, IP
core modules, and circuit modules. Inter-module interface communication
becomes a key issue in system design and verification.

At present, Xilinx, Altera, etc. have released a variety of PSoC products and
solutions, implementing co-processing architecture combining processor cores (such
as ARM, NIOS, etc.) and FPGA. PSoC solutions have been widely used in many
areas such as network communication, data center, and machine learning.
In general, PSoC technology is to integrate large and complete electronic systems
into a single programmable system chip as much as possible, to make the electronic
system optimally designed in function, performance, power consumption, reliability,
size, cost, time-to-market, product maintenance, and hardware upgrades. A PSoC
can integrate analog and digital blocks into a single system; PSoC can integrate
MCU, ASIC, and FPGA for a single application [1, 2].

Reconfigurable Computing Chip

The design of reconfigurable computing chip is based on a reconfigurable computing

architecture. Reconfigurable computing is a parallel computing mode of spatial-
temporal programming. In contrast, the traditional general-purpose processor is the
computational mode of temporal programming, and the FPGA is the computational
mode of spatial programming. The reconfigurable computing chip is a disruptive
technology in the field of integrated circuits and has wide applicability.
The so-called reconfigurable computing refers to the use of programmable com-
puting resources in the system under the control of configuration information to
construct the most suitable computing architecture according to the needs of the
application, to achieve or close to the high performance of the ASIC. The essence of
reconfigurable computing is to reconfigure the functions and interconnections of
programmable computing resources multiple times, making the system suffice for
high performance, low power consumption, easy maintenance, and low cost.
The reconfigurable computing chip hardware architecture consists of a
reconfigurable datapath (RCD) and a reconfigurable controller (RCC), as shown in
Fig. 43.1. The reconfigurable datapath is responsible for parallel processing of the
data stream, and the reconfigurable controller is responsible for configuration infor-
mation management and task mapping scheduling. In a reconfigurable computing
system, the datapath can be dynamically reconfigured by calling or modifying
configuration information, which preserves the computational performance of cus-
tom circuit (in a hardware way) and the computational flexibility of the general
processor (in a software way).
826 S. Wei and S. Yin

Fig. 43.1 Diagram of

reconfigurable computing
chip architecture

The configuration strategy of the reconfigurable computing chip can be charac-

terized into static reconstruction and dynamic reconstruction.
The static reconstruction can only reconstruct the function of the datapath of the
reconfigurable computing chip before the computing starts but cannot reconstruct
the function of the datapath during the computing process due to the large time cost.
The most typical reconfigurable computing chip with static reconstruction charac-
teristics is FPGA. A common working mode of an FPGA is to load configuration
information from off-chip memory for system reconfiguration when the system is
powered on. The size of the FPGA configuration information is generally large, and
the reconstruction process typically lasts from tens to hundreds of milliseconds or
even up to several seconds. After the functional reconfiguration is completed, the
FPGA can perform the corresponding computation. The functionality of the FPGA
can no longer be reconstructed during the computing process. If computation is
needed, be sure to first interrupt the computing task currently being performed by the
FPGA. Because it is a single-bit programming device (fine-grained reconfigurable
computing chip), the flexibility of the FPGA is very high, and almost any form of
digital logic can be realized without considering the capacity. This is one of the
important reasons why FPGAs can be very successful in business. However, the
fine-grained reconfigurable size makes FPGA need a lot of configuration informa-
tion, and the time cost and power cost of reconfiguration become very large.
The reconfiguration time of a typical dynamic reconfigurable chip is generally in
the range of a few nanoseconds to tens of nanoseconds. Since the time cost of
function reconstruction is relatively small, the feature that the datapath of the
reconfigurable computing chip can also perform functional reconstruction in the
calculation process is called dynamic reconstruction. The most typical
reconfigurable computing chip with dynamic reconstruction features is Coarse-
Grained Reconfigurable Architecture (CGRA). The usual way CGRA works is that
43 Programmable Logic Circuit Design 827

after CGRA completes a given computing task, it quickly loads the new configura-
tion bit stream for functional reconfiguration. The reconfiguration process usually
lasts only a few to a few hundred clock cycles. After the functional reconfiguration
completes, CGRA continues to perform the computational tasks for the new
configurations.
A major feature of reconfigurable computing chips that differs from other circuit
implementation is the need to configure the datapath. Once configured, it can
perform the specified functions with high performance like an ASIC circuit. As
shown in Fig. 43.2, the reconfigurable datapath is loaded externally by the config-
uration loader, which forms part of the configuration of the reconfigurable datapath.
It is important to shorten the configuration time of the reconfigurable datapath, so
that switching between different configurations can be completed quickly, and the
real-time processing capability of the circuit can be improved.
There are two common ways to shorten the configuration time. One is to increase
the granularity of the datapath to reduce the total amount of configuration informa-
tion; the second is to reduce the amount of configuration information input from the
outside of the datapath through a hierarchical configuration structure. A hierarchical
configuration structure can greatly compress configuration information. Since dif-
ferent levels of configuration information are stored in different memories, and each
layer of configuration information contains a list of the next layer of configuration
information to be used, the configuration information is fetched layer by layer,

Fig. 43.2 Configuration information fetching technology

828 S. Wei and S. Yin

instead of fetching large amount of input from outside. In addition, since the higher-
level configuration information only contains a list of the lower-level configuration
information, the lower-level configuration information is repeatedly used by differ-
ent lists, thereby reducing the total amount of configuration information. When the
reconfigurable datapath is configured, the hierarchical configuration structure is
fetched layer by layer, and finally each datapath unit will get its own configuration
information. By parsing the configuration information, the datapath controlling
module controls the operation of each computing unit, the input/output of data,
and the loading time of the configuration information, thereby performing schedul-
ing of the entire reconfigurable datapath.
In recent years, reconfigurable computing technology has become a new hot spot
in integrated circuit research. The reconfigurable computing chip has the character-
istics that hardware changes with software changes, and software and hardware can
both support programming, which breaks through the traditional hardware-based
software programming calculation mode and realizes the energy-efficient dynamic
reconfigurable computing technology of “circuit changes with algorithms, architec-
ture changes with applications.”

References
1. D.V. Hall, M.A. Perkowski, C.H. Lee, D.S. Jun, Evolvable Hardware, NASA/DoD Conference on
Self-Repairable EPLDs: Design, Self-Repair, and Evaluation Methodology, vol. 1, pp.
183 (2000)
2. M. Chrzanowska-Jeske, S. Goller, Partitioning approach to find an exact solution to the fitting
problem in an application-specific EPLD device, in Proceedings of EURO-DAC 93 and EURO-
VHDL 93- EDAC, vol. 1, pp. 39–44 (1993)
3. D. Tomanek, What is PSoC?, in 2010 International Conference on Applied Electronics, Sept
8–9 (2010)
4. K. Xue, G.C. Wan, M.S. Tong, Construction and validation for a PSoC wireless transmission
system, in 2016 Progress in Electromagnetic Research Symposium (PIERS), 8–11 (Aug. 2016)
Electronic Design Automation Tools
44
Xiaoming Liu, Yi Liu, Taotao Lu, Fan Yang, and Junqi Yang

Contents
IC Design Automation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
Flow Management Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
System Level Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
Schematic Capture Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
Analog Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
Digital Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
Analog/Digital Mixed-Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Logic Synthesis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Formal Verification Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Design for Testability Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Auto Generation of Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Automatic Generation and Optimization of Testing Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Physical Design Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Parasitic Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
Accurate Computation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
Fast Modeling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Layout Verification Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Design Rule Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Layout vs Schematic (LVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
Electrical Rule Check (ERC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
Layout vs Layout (LVL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
Timing and Power Analysis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Static Timing Analysis (STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Dynamic Timing Analysis (DTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Power Analysis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Design for Manufacturing (DFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

X. Liu · Y. Liu · T. Lu · F. Yang (*)

Huada Empyrean Software Co., Ltd., Beijing, China
e-mail: yangjq@empyrean.com.cn
J. Yang
School of Microelectronics, Fudan University, Shanghai, China

© Publishing House of Electronics Industry 2024 829

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_44
830 X. Liu et al.

Design for Yield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

Design for Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

Abstract
EDA is the acronym of Electronic Design Automation. IC designer uses EDA
tools to complete schematic design, layout design, circuit simulation, design
verification, chip manufacturing, and packaging testing. The automation and
intelligence of EDA tools improve the efficiency and accuracy of IC designs.
The main EDA tools used in IC design can be divided into three categories:
input design and data management, synthesis design, and verification and opti-
mization. The input design and data management tools help users quickly to input
design objects, design requirements, and manage the design data, for instance,
hardware description language (HDL) and compiling, input and editing, the
design and process management of integrated circuit, and layout. The synthesis
design tools help users to convert behavioral RTL design into structural gate-level
netlist design, which is accomplished through placement and routing, etc. The
verification and optimization tools help users to verify the validity of IC design
and the rationality of improved design structure, for instance, IC simulation and
verification, physical design rules and LVS check, layout parasitic parameter
extraction, sequential and power consumption improvement, manufacturability,
yield, reliability, etc.

Keywords
EDA · Schematic capture · Layout capture · Simulator · Logic synthesizer ·
Formal verification · Design for testability · Physical design · Parasitic
extraction · Layout verification · Timing and power analysis

IC Design Automation

Electronic design automation (EDA) tools, as an important part of IC design

automation in IC design industry, can assist design engineers to execute every design
stage in IC design flow.
EDA tools widely used in IC design can be divided into three categories: design
creation and data management tool; design synthesis and design implementation
tools; verification and optimization tool [1]. (1) The design creation and data
management tools help users quickly create and input design objects, design
requirements, and manage design data, for instance, hardware description language
(HDL) and design compilation, input and editing, design and process management
of IC, and layout. (2) The synthesis design tools help users accomplish the design of
each level, for instance, the system design and synthesis, logic synthesis, placement
44 Electronic Design Automation Tools 831

and routing, etc. (3) The verification and optimization tools help users verify the
validity of their design and the rationality of improved design structure, for instance,
IC simulation and verification, physical design rules and LVS check, layout parasitic
parameter extraction, sequential and power consumption improvement, manufactur-
ability, yield, reliability, etc.
The design flows of digital circuit and simulation circuit associated with EDA
tools are shown below in Figs. 44.1 and 44.2.
The automatization and intelligence of EDA tools spare users from complicated
operations and significantly improves the efficiency and accuracy of design. Based
on this perspective, the logic synthesis is the most prominent application of
EDA tool.
Different companies must obey the same data criterion of EDA tools, e.g.,
OpenAccess (for the database standard), GDS II and OASIS (for layout data
standard), etc. Since all EDA tools have standard data interface, users can easily
access to any EDA tools from different companies throughout the design process at
different levels and there is no need of data format conversion for different EDA
tools.
In recent years, EDA technique has rapidly developed. More and more new EDA
techniques and tools are emerging in annual global conference – Design Automation
Conference (DAC). Nowadays, most EDA R&D enterprises are located in the USA,
such as Synopsys, Cadence, Mentor (acquired by Siemens in 2017), etc. Empyrean
Software is a representative of China EDA R&D enterprises.

Fig. 44.1 Design flows of digital circuit and related EDA tools
832 X. Liu et al.

Fig. 44.2 Design flow of analog circuit and related EDA tools

Flow Management Tool

Flow management tool is a standardized management tool which helps IC designer

accomplish massive complicated IC design with high quality in a minimum period
of time.
The “flow” in flow management includes the process from requirement definition
to generating layouts at each design stage, the process of checking the quality of
intellectual property core (IP core) and standard cell library, and the process of
clients’ customization.
Flow management tool basically manages design data and configuration data.
Design data includes the data from the whole process of IC design, e.g., circuit
schematics, layouts, RTLs (register transfer level), netlists, circuit simulation result,
timing and power analysis results, parasitic parameter extraction result, etc. Config-
uration data includes the corresponding design data of IP core, standard cell library,
physical verification rules, technology physical property information and SPICE
model.
Functionalities of flow management tool offer functions such as:

1. Information Sharing: forms dependency between each phase; collects changes

from each phase; delivers messages of phase changing to the team members
2. Authority Management: assigns different authorities to different designers; pro-
tects the safety of design data
3. Version Management: manages different historical versions for the same data;
switches and compares data of different versions
44 Electronic Design Automation Tools 833

Fig. 44.3 Design time statistics for different phases

4. Data Synchronization: synchronizes data from different designers; compares and

combines conflicting versions
5. Issue Tracking: records issues of each phase; helps designer track the process of
each phase
6. Open Interface: provides open development environment and third-party tool
interface; facilitates data input and migration; facilitates extension of customized
functions
7. Visualization of Flow: collects information at each stage of creating; observation,
configuration, execution, tuning, and report; connects each phase together via
graphical interface and statistical analysis; helps users with a convenient and
straight-forward method manipulate IC design project

The design time statistics of different periods, which are used in logic synthesis,
design and planning, placement and routing, and chip assembling, is shown in
Fig. 44.3.
As the chains of IC design and the types of data become more and more abundant,
the data volume grows larger, and the demand of collaborative design becomes more
urgent. It will be necessary to use flow management tool to manage design processes
and design data.

System Level Simulator

System level simulator’s functions are modeling and simulating the electronic
system at high level so that the iteration from system design to physical implemen-
tation and the risk of issues raised during mid- and late-phase of physical imple-
mentation are reduced.
834 X. Liu et al.

System level simulator supports system modeling flexibly by using built-in or

outer estimation algorithm, implementation algorithm, and simulation algorithm to
evaluate and to verify the functions and performance of the system.
System level simulator uses system modeling language to describe the system.
Modeling language has the following features:

1. Builds up system models of every functional module; allows modeling with

different levels to describe different modules; allows information exchange
between modules
2. Provides choices of different implementation for modules, for instance, using
hardware or embedded core to implement, choosing different structures to
implement, etc.
3. Provides various module libraries; supports implementing of specific module by
using existing design modules or IP cores

C/C++, SystemC [2], and SystemVerilog (IEEE 18002017) are commonly used
modeling languages. To satisfy the evolving requirement of simulation and system
description, new system modeling languages are developing. Some languages
describe the system abstractly, which satisfies general system design, such as
UML (Unified Modeling Language™) and SysML (Systems Modeling Language);
the others support more on the customization of embedded system design, such as
SMDL (Semantic Model Definition Language) and SSDL from the system design
tool Teraptor ®.
Many system-level simulators describe system based on modules with GUI
(graphical user interface), such as LabVIEW (Laboratory Virtual Instrument Engi-
neering Workbench, from National Instruments), MATLAB (Matrix Laboratory, by
MathWorks), SystemVue (from Agilent), VisualSim Architect (from Mirabilis
Design), and Simulink (by MathWorks).
In short, system-level simulators are broadly used in system and chip design by
many design companies. It plays an increasingly important role in design, verifica-
tion, and debugging in embedded systems and SoC.

Schematic Capture Tool

A schematic capture tool provides interactive schematic editing functions, which can
accomplish hierarchical schematic design and provide necessary data support for IC
simulation, placement and routing, and full custom layout design.
Schematic capture tool supports component symbol input and schematic input
according to the hierarchical design of the schematic, corresponding to symbol and
schematic view. The function of component symbol input is to create its
corresponding component graphical symbols based on the characteristics of the
schematic, which is used to reference it at high level IC design. The function of
schematic input is to represent the connection between electronic components, the
parameters of electronic components, and the characteristics of the circuit.
44 Electronic Design Automation Tools 835

Schematic capture tool also provides the function of generating component symbols
of components automatically. Figure 44.4 shows the schematic of an inverter and its
corresponding component symbol.
Schematic capture tool can describe the circuit at system, module, unit, and
transistor level. It offers creation and editing of the parameters of components,
circuit nodes, and annotation and supports electrical rules checking, such as short
circuit and open circuit.
The data stored by schematic capture tool is divided into physical information and
logical information. Physical information generally refers to graphical data, such as
the shape of I/O, the location information of I/O, etc. Logical information refers to
the connection information of the schematic which is the topology information of the
schematic.
There are two types of data exchange provided by schematic capture tool:
Electronic Design Interchange Format (EDIF) and netlist. EDIF generally contains
physical and logical information of the schematics. The data of the different sche-
matic capture tools can be exchanged in the form of EDIF. Netlist, which is different
from EDIF, does not contain physical information and only contains logical infor-
mation. Depending on the application, different forms of netlist, such as CDL
(circuit description language), SPICE, Spectre, and Verilog, are commonly used.
SPICE and Spectre are also both used as names of circuit simulators and names of
netlists.
Due to the development of IC design methodology and increasing difficulty of
design, schematic capture tools present two major trends: usability and scalability.
For usability, schematic capture tool provides more convenient and flexible func-
tions, such as using different colors to distinguish the connections of wires, real-time
electrical rule checking, intelligentized connection, etc. For scalability, schematic
capture tool not only satisfies the requirements of creating and editing schematics but

Fig. 44.4 An inverter: (a) schematic view, (b) symbol view

836 X. Liu et al.

also provides more interfaces for cooperating with other tools, such as interface of
schematic simulation tool, interface of debugging simulation results, interface of
schematic driven layout, interface of constraint driven layout, etc.

Circuit Simulator

Circuit simulator can be divided into three categories: transistor-level analog circuit
simulator, gate-level and RTL-level digital circuit simulator, and analog/digital
mixed-signal simulator.

Analog Circuit Simulator

The basic flow of analog circuit simulator is shown in Fig. 44.5:

The problem of analog circuit is expressed with a partial differential equation as:

dQt
f ð V t Þ þ Eð V t Þ ¼ I t 
dt
where t is the time, Vt is the node voltage, It is the node-independent current source,
Qt is the node charge, f(Vt) is the nonlinear node current, and E(Vt) is the controlled
node current. By using Newton-Raphson iteration method, the equations can be
solved to get the following iteration result:

dQt
V t,iþ1 ¼ Y t 1 I t   f ðV t,i Þ  EðV t,i Þ þ V t,i
dt

where Yt is the Jacobian matrix of f(Vt) þ E(Vt) and i ¼ 1,2,3,. . . is the iteration step:

Y t ¼ @ ðf ðV t Þ þ EðV t ÞÞ=@V t

Generally, Yt is a sparse matrix whose complexity of calculation can be reduced

by LU decomposition algorithm. Before decomposing, re-ordering the rows and
columns of Yt reduce the effort of decomposition as well as improve the stability of

Fig. 44.5 Analog circuit simulator process

44 Electronic Design Automation Tools 837

iterative computation. Yt of circuits with special structures is a dense matrix which

can be solved better by using algorithms such as PCG and GMRES. Charge Qt
partially differentiated of time t can be calculated by single-step algorithms such as
forward and backward Euler methods or multi-step algorithms such as TRAP and
GEAR. The accuracy and stability of the algorithms are influenced by the type of the
circuit.
The effort taken to solve the equations increases extraordinarily as the number of
nodes increases, so lots of acceleration techniques are introduced into commercial
analog circuit simulator.

1. Parallel computation: distributes the calculation on current and Jacobian matrices

to multiple CPU.
2. Bypass technology: when node voltage changes in slight manner, linear interpo-
lation is used to skip recalculation of nonlinear current and Jacobian matrices.
3. Node folding technology: uses linear interpolation method to eliminate inner
nodes of nonlinear components in order to reduce the number of equations.

For larger circuits, simulators introduce fast SPICE technologies which reduce
the accuracy but increase the speed and capacity of simulation greatly. These
technologies include the following.

1. Table model: uses table looking up and interpolation method to calculate the
current and charge of nonlinear components.
2. Event-driven: divides the circuit into multiple partitions and solves them only
when the port signal is changed.
3. Isomorphism: sharing Jacobian matrices of partitions with the same structure and
similar node voltages; solves the equation set once; and uses linear interpolation
to correct the tiny differences between partitions.

Moreover, parasitic effects can influence the performance and functions of IC, so
post-simulation of analog circuit accounting for the parasitic effects is introduced. In
post-simulation, parasitic components cause the size of matrices increase extremely
and coupling effects cause the matrices denser, so the acceleration technologies are
introduced to increase simulation speed and capacitance with little influence in
accuracy. Some common technologies are shown below.

1. RC Reduction: simplifies parasitic RC networks into equivalent circuits with

relatively small scale via physical or mathematical equivalent methods [3].
2. Circuit Partition method: divides the circuit into several partitions with little
coupling effect, calculates to get the result and substitutes result of all partitions
back to the top port matrix to get the solution. Some common methods are
Hypergraph-Partition, BBD, and SuperLU [4–6].
3. Multi-Rate method: partitions circuit according to work frequency; sets relatively
small time step for partitions with high-frequency signals to ensure calculation
838 X. Liu et al.

accuracy; sets relatively large time step for partitions with low-frequency signals
to increase calculation speed.

Digital Circuit Simulator

Figure 44.6 illustrates the digital circuit simulation process. Digital circuits are
usually described with VHDL, Verilog HDL, and SystemVerilog languages. Those
types of languages offer the quantization and test of the sequential relationship of
logic signal. Digital circuit simulator uses event-driven method to simulate signal
logics, which means the I/O signal of logic unit works at finite logic state and its
output is recalculated only when the state of input signal changes. The event-driven
method is shown in Fig. 44.7.
In digital circuit post-simulation, SDF (Standard Delay Format) file with accurate
delay timing extracted from post layout of circuit design can be attached to get more
accurate result [7]. Digital circuit simulation is faster but less accurate than analog
circuit simulation.

Fig. 44.6 Digital circuit simulation process

Fig. 44.7 Digital circuit simulation with event-driven method

44 Electronic Design Automation Tools 839

Analog/Digital Mixed-Circuit Simulator

There are analog and digital signal circuit simulators, to simulate at transistor-level,
gate-level, or RTL-level. The core of analog/digital mixed-signal simulator is iden-
tifying connection node between analog signal and digital signal and conversion
algorithms which transfers the continuous analog signal and discrete digital signal in
the node back and forth. Analog/digital mixed-signal simulation is illustrated in
Fig. 44.8.

Logic Synthesis Tool

Logic synthesis tool performs step-by-step to automatically transform a digital

design from an RTL description to a gate-level netlist through Boolean minimization
and optimization. Figure 44.9 shows the working flow of logic synthesis.
Logic synthesis can take the following three inputs: RTL design in Verilog or
VHDL language description; target timing, area or power constraints; technology
libraries that contain logic gates, such as AND, OR, XOR, NAND, and registers.
Logic synthesis compiles, synthesizes, and optimizes RTL circuit description
according to the target constraints as described below:

Fig. 44.8 Analog/digital mixed-signal simulation process

Fig. 44.9 Working flow of

logic synthesis
840 X. Liu et al.

1. Compiles RTL input design in Verilog or VHDL hardware description language

into technology-independent initial circuit.
2. Performs arithmetic optimization for arithmetic logic operations (such as addi-
tion; subtraction, multiplication, division, and complex mixed calculation) from
the initial circuit. For instance, there can be different architecture implementation
methods for a multiplier to achieve different timing, power, and area trade-off.
The appropriate selection of the implementation method based upon the target
constraints greatly affects the final synthesis quality of results.
3. Performs technology-independent sequential and combinational optimization.
Sequential optimization mainly includes finite state machine (FSM) and register
optimization. Combinational optimization mainly involves Boolean optimization.
4. Maps optimized technology-independent sequential and combinational logic into
gate-level netlist. Then the synthesis compiler performs technology-dependent
optimization to meet target timing, power, and area constraints, based upon those
available from technology libraries.

After finishing the above process, logic synthesis will then generate an optimized
gate-level circuit netlist. It must be ensured that the logic functions are equivalent to
the initial input RTL design.
As IC design scales continue to grow and manufacturing technologies continue to
shrink, synthesis compiler should consider the effects of back-end placement and
routing for more accurate timing and area estimations, in order to achieve better
correlations between front-end synthesis and back-end place and route. At the same
time, to increase the design efficiency, it should also adopt hierarchical and parallel
optimization techniques to reduce the turnaround time due to growing design
complexity.

Formal Verification Tool

Formal verification tools determine whether the functional behavior of a hardware

design is correct or not by using mathematical and logic algorithms.
There are usually two kinds of methods: equivalence checking and property
checking. In IC design process, many steps can edit and change the function of a
design, for example, inserting testing logic structures, clock tree synthesis, ECO, etc.
Verification by using simulation is very time-consuming and also it is hard to
guarantee verification coverage. Through static and mathematical logic algorithms,
equivalence checking is used to compare the logic consistence between original
design and the optimized design. In theory, the design checking can be fully covered.
Given two netlists (initial netlist and revised netlist), suppose that their input
signals, output signals, and the number of registers are the same, then an equivalence
checking tool usually pairs input signals, output signals, and registers in the initial
and revised netlists to generate multiple pairs of combinational logic cones. Then, it
uses algorithms such as BDD (binary decision diagram) [8] and SAT solver (con-
junctive normal form solver; SAT stands for the Boolean satisfiability problem) to
44 Electronic Design Automation Tools 841

Fig. 44.10 Equivalence

checking

compare the two combinational logic cones in every pair. If, for all the pairs, the two
combinational logic cones’ Boolean functions are equivalent, the static and sequen-
tial logic functions of two netlists are the same [9]. The concept of equivalence
checking is shown below in Fig. 44.10.
When there are different numbers of registers in the initial netlist and revised
netlist, the algorithm above usually will find that the Boolean functions of two
combinational logic cones in some pairs are not equivalent. In such situation, we
cannot conclude that the functions of two netlists are the same or not, and thus we
have to use some sequential equivalence checking algorithms to further analyze
whether the logic functions of two netlists are consistent or not [10].
Property check is the method of analyzing whether a given design satisfies
certain properties or assertions. First, use logic structure to describe system models,
such as sequential logic structures and finite state machines; use formal logic
expressions to describe desirable properties. Then, use formal verification algorithms
to check whether the design satisfies those properties or not. Property checking
algorithms can be further classified as theorem proving or model checking.
Theorem proving techniques represent the design and property under validation
by using certain formal logic expressions, and then those expressions are trans-
formed by using axioms, reasoning rules, and proved theorems to show that the
design satisfies those properties. This process usually requires manual involvement
and good understanding of how the system is designed and its functionalities.
Model checking uses sequential logic structure or finite state machines to describe
the design under validation and uses temporal logic to describe the properties that the
design should have. Then, it searches design state spaces using techniques such as
BDD, SAT solver, and ATPG (Automatic Test Pattern Generation) and checks
whether the design satisfies those properties in all possible states or not [11]. If
any property is not satisfied by the design, model checking can give counter-
examples for better fault location. Model checking algorithms usually do not require
manual involvement. However, if the design’s reachable state space is too large, it
will encounter the so-called state explosion problem that may prevent it from
obtaining final result in a limited time.
842 X. Liu et al.

As the complexity of IC designs continues growing, equivalence checking and

property checking technologies also need continued improvement to handle designs
with growing scale.

Design for Testability Tool

Design for testability (DFT) tools in IC industry can automatically generate test logic
circuits and test vectors by manual insertion or tool synthesis. Design for testability
tools can improve the coverage of test significantly and reduce the difficulty and cost
of testing chips in automatic test equipment (ATE).

Auto Generation of Test Circuit

Scan-based design is the most common design for testability (DFT) tool. It converts
the registers of testing circuit into scan registers and then connects the scan registers
to one or more scan chains to transmit testing signals. The generation of testing
circuit in DFT involves a series of complex operations which usually requires the
help of automatic tools. A typical DFT synthesis flow is shown in Fig. 44.11.
There are four main steps in the process:

1. Converts regular sequential registers into scan registers

2. Checks whether the test circuit meets the DFT rules or not
3. Automatically/manually repairs the part of circuit that violates DFT rules
4. According to DFT constraints and target setting, connects scan chains and
composes the required logic to be added

Automatic generation results of testing circuit include gate-level netlist with DFT,
DFT operation descripted by STIL (Standard Test Interface Language), and DFT
analysis report.

Fig. 44.11 Automatic process of scan-based design for testability

44 Electronic Design Automation Tools 843

Automatic Generation and Optimization of Testing Vector

Based on DFT netlists and STIL results, Automatic Testing Vector Generator can
produce signal of testing vector needed for chip testing automatically. After opti-
mized by compression coding, broadcasting compression, and logic transform
compression, testing vectors can reduce the amount of test data, the time taken by
testing, and the number of test channels on the premise of guaranteeing the test
coverage.
D algorithm, also known as multi-dimension path sensibilization method, is the
first complete automatic test pattern generation (ATPG) algorithm [12] whose basic
ideas are using circuit simplify table and D vector propagation in order to pass the
faults to output along all the sensitized paths and then obtaining the final testing
vectors via compatibility check. To ensure the validity of choosing sensibilization
methods in massive combinational circuits, PODEM and FAN algorithm improved
D algorithm [13, 14]. Then SOCRATES [15] improves the efficiency of logic
implication, path sensibilization, and multiple back trace. The industrial ATPG
tools mostly use methods based on SOCRATES and make further improvements.
In addition to those scan-based design DFT methods, there are some more DFT
solutions in recent industry. LBIST (logic built-in self-test) adds special hardware or
software components into the circuit and tests the circuit itself without external test
equipment. LBIST and MBIST (memory built-in self-test) can be used in memory
self-tests.

Physical Design Tool

The function of physical design tools is to accomplish IC layout design by automatic

placement and routing technique or manual editing.
Automatic placement and routing can be divided into four steps: floor planning,
placement, clock tree synthesis (CTS), and routing [1].
Floor planning ensures chip area, optimizes module shape, and allocates the
placement area for standard cells, I/O pad, and macro under certain geometrical
constraints. Some commonly used floor planning algorithms are the following:
placement dimension-changing algorithm; module placement based on the growth
of clusters; simulated annealing algorithm; and mapping problems into analytic
solutions of equations.
Placement is divided into two categories: global placement and detailed place-
ment. It places standard cells on the legal position in rows of core area and satisfies
the design rules, which optimizes the performance requirements of wire length,
timing, congestion, and power consumption. The problem of placement is
NP-complete problem which cannot be optimized by algorithms with polynomial
time complexity. In real applications, we usually search for a feasible solution as an
approximation of the optimal solution. Algorithms commonly used in solving
placement problems can be divided into three categories which are graph algorithm
(depth-first search and critical path), deterministic algorithm (linear programming,
844 X. Liu et al.

non-linear programming, and dynamic programming), and stochastic algorithm

(simulated annealing algorithm [16]).
The placement flow can be solved as below using simulated annealing algorithm.

Given initial temperature T¼T0 (T0  0), Iteration time at

every temperature N, initial solution state X0
while (T > 0) {
for (loop¼1; loop<¼N; ++loop) {
Get a new solution Xnew in neighborhood functions
(e.g. Module transform or unit location)
Calculate and evaluate the change in function ⊿E ¼
E(Xnew) – E(X0) (e.g. Total length of wires in Netlist)
if (⊿E < 0) {
Set Xnew as current new solution
} else if (exp(-⊿E/T) > random(0, 1)) {
Set Xnew as current new solution
}
}
Lower temperature T
}
Output the optimized result derived from above

Clock tree synthesis inserts buffer in clock circuit and transfers clock signal to
every synchronous cell (flip-flops) so its optimization goal is that the path delay and
clock skew are reduced as much as possible. Some common clock tree synthesis
algorithms are H-tree algorithm and fishbone algorithm, as shown in Fig. 44.12. In
order to reduce clock skew and influence caused by process variations, high-
performance clock system design also uses mesh structure but that takes more
routing resources and area.

Fig. 44.12 H-tree type clock tree and fishbone type clock tree
44 Electronic Design Automation Tools 845

Routing is divided into global routing and detailed routing [17]: global routing
reasonably allocates nets to proper routing area and avoids congestion at local zone;
detailed routing accomplishes the connection between pins and vias on the routing
tracks in order to avoid short and open error. According to the area of routing and the
distribution of nodes in the area, detailed routing can be divided into channel routing,
switchbox routing and region routing. Results of double channel routing and net
vertical constraint graph are shown in Fig. 44.13.
With the development of IC technology at 28 nm node and more advanced
technologies, physical routing needs to support multiple patterning technology
(MPT) so that manufacturability is guaranteed.
Additionally in IC physical design environment, one must rely on layout editing
tools to input the layout information. Layout editing tools provide a 2-D geometric
graphics creating and editing environment based on polygons and offer interactive
editing and operation functions according to layout’s features and design rules. It
will output physical layouts in GDS II or OASIS format. The basic functions of
layout editing tools include the following: (a) supports hierarchical editing;
(b) binding with the technique, distinguishes different layers of technique according
to specific color, wire type, and filing; (c) supports creating, zoom-in/zoom-out, and
stretch of basic shapes such as rectangle, polygon, path, etc.; and (d) uses parame-
terized cell to reduce duplicate input.
As IC design methodology develops, requirements for layout editing tool become
more advanced, which mainly reflects as follows:

(a) Introduces two types of new technologies by interacting with circuit: SDL
and CDL
(b) Derives auto placement and routing for analog circuit by combining analog and
digital circuits
(c) Provides quick display and multithreading query for higher requirements of
massive expanded design scale
(d) New technology of layout editing is demanded with the development of current
techniques, such as grid-aligning technology for FinFET

Fig. 44.13 Double channel routing result and net vertical constraint graph
846 X. Liu et al.

Parasitic Extraction

Parasitic extraction functions as extracting parasitic parameters of layout intercon-

nect wires and devices according to the process technology data in order to obtain
circuit netlists with parasitic parameters for performance analysis and post-
simulation of circuit.
Parasitic parameters include parasitic resistance, parasitic capacitance, and para-
sitic inductance. Parasitic parameters have impact on time delay, power, and signal
integration significantly. As process develops, parasitic parameters have become the
key factors of circuit function and performance. In IC design, parasitic extraction is
one of the indispensable steps in IC design.
Two typical parasitic parameter extraction methods are available: accurate com-
putation method and fast modeling method. Accurate computation has high accuracy
but low speed, so it is usually used in small-scale applications with high require-
ments in accuracy, such as process analysis, building standard cell library, RF circuit
analysis, etc. Fast modeling method has lower accuracy but is thousands times faster
than accurate computation method, so it is always widely used in chip-level parasitic
extraction.

Accurate Computation Method

Accurate computation method, also called field solver method, calculates the para-
sitic parameters through solving electromagnetic field equations to get accurate field
distribution. Accurate computations are similar for parasitic capacitance, resistance,
and inductance. The example below shows accurate computation of parasitic capac-
itance. Accurate computation method of parasitic capacitance is based on numerical
method which solves the following Laplace equations with bias voltages [18, 19].

@2u @2u @2u

ek ∇2 u ¼ ek þ þ ¼0 within Ωk ðk ¼ 1, ⋯, MÞ
@x2 @y2 @z2
u¼u above Γu
@u
q¼ ¼q¼0 above Γq
@n
@u @u
ea  a ¼ eb  a , ua ¼ ub above ΓI
@na @na
where Ω ¼ UΩk is to be resolved domain and Ωk stands for the space possessed
by the kth dielectric, M is the total dielectric number, u is the bias voltage, q ¼ @u/@n
is the electric flux, and εk is the dielectric constant of kth conductor. Here n denotes
the unit vector and a and b are two neighboring media.
According to different numerical methods, accurate computation method applies
mesh partition to 3-D field and discretizes Laplace equations into integral equations
on the mesh. It solves linear equations to obtain the electric field intensity on the
surface of conductors. Then it solves for induced charge through the equation below
44 Electronic Design Automation Tools 847

@u
Qi ¼ e dΓ
Γi @n

which calculates Qi the charge Q of the ith conductor; following the equation,
Cij ¼ Qi/Vij, each capacitance value can be calculated. Numerical methods include
boundary element method (BEM) and finite element method (FEM). BEM
discretizes 2-D boundary of 3-D area, uses weighted residual method, and applies
Green formula to convert Laplace equations to discrete integral equations on 2-D
boundaries. Meanwhile, it uses boundary conditions to convert the discrete integral
equations into linear algebra equations and solve for solution. FEM discretize 3-D
area directly. It uses variation principle to convert Laplace equation into extreme
problem to minimize the value of error function in every element and then converts
integral equations into linear equation sets to solve for solution.

Fast Modeling Method

Fast modeling method analyzes geometric graphs of layouts by building parasitic

parameter model and then uses pattern matching method to derive parasitic param-
eters. Commonly used models are 2-D and quasi 3-D models. Since quasi 3-D
model considers the property of 3-D structure, its calculation result is more
accurate than 2-D model’s, so it is widely used in large-scale layout parasitic
extraction.
Using parasitic capacitance calculation as an example, quasi 3-D model divides
capacitors in 3-D structure into overlap capacitor, lateral capacitor, and fringe
capacitor to consider their effects to the total capacitance separately as shown in
Fig. 44.14. Each capacitance value is calculated by a table look-up model or
analytical formula method.
Fast modeling method requires accurate computation method to calculate the
typical patterns and to build the model library, produces model parameter of calcu-
lated layout geometries according to pattern match method, and searches through
model library to get results.
As process develops, more and more process factors influence parasitic parame-
ter. 3-D structure grows more and more complex, which sets higher requirements for

Fig. 44.14 Quasi 3-D model diagram

848 X. Liu et al.

parasitic parameter extraction. Meanwhile, the circuit scale continuously grows

larger, which sets higher requirements for parasitic parameter extractor in speed
and accuracy. Parasitic parameter model is so complex that it must consider multiple
factor combinations to get better computation accuracy. Especially in FinFET
technology, due to the huge difference between device structure and traditional
process, parasitic extraction encounters new challenges.

Layout Verification Tool

Layout verification tool is used to check whether the layout satisfies design rules,
electrical rules, and consistency between layout and schematic or not [1], which
plays an important role in reducing risk of design faults.
Layout verification tool supports both flat and hierarchical mode. Flat mode is the
foundation of layout verification tool; hierarchical mode takes full advantage of
layout hierarchy to efficiently avoid repetition errors and to improve the speed of
processing layouts. For large-scale layouts, parallel technology is applied to improve
the efficiency of layout verification.
Layout verification tool mainly includes design rule check (DRC), layout vs
schematic (LVS), electrical rule check (ERC), and layout vs layout (LVL).

Design Rule Check

Layout design must obey the design rule of manufacturing technology which
includes width, spacing, enclosure, density, and antenna check. Any violation in
layout design will cause manufacturing failures, for example, open circuit error
which might be due to small wire width.
The key technology used by DRC includes hierarchical processing and scan-line
algorithm. Hierarchical processing technology adjusts layout-line algorithm to cause
manufacturing failures, e.g., open circuit. Scan-line algorithm includes scan-line
algorithm based on trapezoid and edge. Edge is a line segment and expressed by
the coordinates of its two ends. Scan-line algorithm based on edge basically converts
one 2-D geometric problem into two 1-D problem, which includes the following
steps:

(a) Get the location of current scan line.

(b) Add new edges into the current scan-line and construct the current scan-line and
edge set with the initial edges.
(c) Sort the edge set in the current scan-line.
(d) Traverse the edge set in the current scan-line and carry out logical process
according to different commands.
(e) Delete the leaving edges in the current scan-line and go back to step a.
44 Electronic Design Automation Tools 849

Fig. 44.15 Use scan-line

algorithm to calculate “AND”
of two layers

In Fig. 44.15, L1 and L2 are input layers; x1, x2, x3, and x4 are coordinates which
guide scan-line terminate to calculate; Result is the result layer.

Layout vs Schematic (LVS)

The main functions of LVS tools are checking the consistency between netlists
extracted from layouts and those from schematics. Major technologies involved
are netlist extraction technology and netlist comparison technology. The main job
of netlist extraction is to extract the net, device, and devise properties in circuit. The
essence of netlist comparison is the graph isomorphism problem in graph theory.
The fundamental theory of LVS comparison is, given initial matching pairs,
matching more devices and nets by tracking and given no initial pairing, obtaining
initial matching pairs by signature partition [20]. By repeating the above steps, the
process stops when all devices and nets in layouts and schematics are matched or no
new matching pair comes up. For unmatched devices and net, it checks the environ-
ment to repair and to rematch; if repair failure appears, it reports the failure as an error.
Among LVS comparison, signature partition method assigns corresponding sig-
nature values to devices according to the type of devices and divides devices into
different sets according to the signature values. According to the connection between
nets and devices, it also assigns signature values to nets and divides them into
different sets.
In Fig. 44.16, two circuits are extracted from layout and exported from schematic
separately where LVS reports an open circuit error.

Electrical Rule Check (ERC)

The electrical rule check (ERC) is aimed to verify violations such as open, short,
path check, etc. ERC is based on layouts; it can quickly check and directly locate
common problems in design without schematics. ERC functions are included in
LVS tool.
850 X. Liu et al.

Fig. 44.16 Netlist comparison

Layout vs Layout (LVL)

Layout vs layout (LVL) tool is applied mainly in two fields. First, when revising
layouts, designers need LVL tool to help check the difference before and after
revision. On the other hand, since layout data is usually flattened when making
mask, LVL tool is used to compare the difference of layouts before and after
flattening. LVL check involves key technologies such as hierarchical processing,
scan-line algorithm, data compression, parallel computation, etc. In addition, since
there are few rules involved, LVL can apply special acceleration techniques
according to different types of layouts.
After the technology progressed at 40 nm node and beyond with narrower metal
lines and spacing and thinner inter metal dielectric layers, the influences among
metal lines and coupling with interconnection environment is more significant and
44 Electronic Design Automation Tools 851

the optical proximity correction (OPC) takes into effect. The 2D check technology
used by classical layout verification tool cannot satisfy the requirements anymore, so
there is a need of using 3D and optical analysis to analyze various effects and to
develop new checking technologies, such as pattern match, double/multi-pattern,
smart fill, etc.

Timing and Power Analysis Tool

Timing analysis tool is used to check whether the design of synchronous circuit
satisfies given time constraints (setup constraint, hold constraint, etc.). It is divided
into static timing analysis (STA) and dynamic timing analysis (DTA). Power anal-
ysis tool is a separate analysis engine used to analyze both static power (such as
leakage power) and dynamic power (such as clock nets switching) dissipations.

Static Timing Analysis (STA)

STA is an adequate method to do time verification for massive gate-level circuits; it

does not require testing vectors to calculate timing path delay. To begin with, STA
uses statistical wire load model or SDF resistor and capacitor value. According to
time model in cell library and topology structure of circuit, it checks whether the
setup time and hold time for every flip-flop satisfy the design requirements or not. Its
advantages are high coverage rate and high speed; its disadvantage is the disability of
analyzing asynchronous logic circuits and analog circuits.
Static timing analysis uses PVT (process, voltage, and temperature) corners, such
as BC, TC, and WC (best, typical, worst cases; see Fig. 44.17) to reflect different
working conditions of circuit under environments with different PVT conditions.
Cell library, under each corner, is characterized for the cell timing model (time-delay
value and time constraint value). Theoretically, time closure ensures that chips in
every working scenario has no time violation. Practically, one or more special corner
will be selected for validation.

Fig. 44.17 Timing check at BC-WC mode

852 X. Liu et al.

(a) Single model: Uses the same corner condition to analyze the setup time and hold
time for each timing path in the whole circuit.
(b) Best-case/worst-case model: Uses the best conditions to analyze hold time of
time paths; uses the worst conditions to analyze setup time of time paths.
(c) OCV (on-chip variation, see Fig. 44.18) model: Uses amplification and reduc-
tion multipliers to slow down data path transfer and speed up clock path transfer
when analyzing setup time and vice versa when analyzing hold time. With 28 nm
node and beyond, advanced OCV (AOCV) appears to extend OCV [21]. It
eliminates the pessimistic factors of OCV and checks the list to get time delay
value for every cell according to different depths of logic and different physical
distances of time paths. In order to tackle the systematic and random changes in
chips and between chips, statistical static timing analysis (SSTA) method is
introduced [22]. It uses probability distribution functions to calculate the arrival
time of each signal at each node in order to eliminate unnecessary timing over
correction. The difficulty of SSTA is that the probability distribution function is
difficult to calculate and the memory required for calculating massive statistic
data is huge associated with long run time.

Dynamic Timing Analysis (DTA)

In SoC design at 16 nm technology node and IoT ultra-low voltage designs, STA
timing calculation based on corner is not accurate so that dynamic time analysis
based on transistor-level simulation is required. It uses parallelism and special
acceleration technology to accomplish fast and accurate simulation of critical time
paths and obtains exact time information of time paths to help timing convergence.

Power Analysis Tool

Power analysis tool gives statistical report based on temperature, switching activity,
load, current, voltage, and power of the circuit. It analyzes the circuit power integrity
issues due to IR-drop and electromigration (EM). Its main functions include the
following:

Fig. 44.18 Timing check at OCV mode

44 Electronic Design Automation Tools 853

(a) Signal Integrity Analysis: Checks APL/LIB/LEF library cell data; checks cor-
rectness and completeness of DEF/SPEF/IPF/STA/VCD design data
(b) Design Defect Analysis: Checks whether the resistance, capacitance, and peak
current of power/ground network matching the expected value or not (which
might be due to the unreasonable distribution of pad, the non-optimized power/
ground routing and excessively high frequency)
(c) Hotspot Analysis: Checks whether static resistance and current, dynamic IR
drop, and power electromigration satisfy the sign-off standard; if there is viola-
tion, locates the issue in the area and traces back to the find the root causes

Design for Manufacturing (DFM)

In semiconductor industry, design for manufacturability or design for manufacturing

(DFM) refers to a set of methods applied for the early stage of designs, where the
difficulties, specifications, and constraints of manufacturing processes are taken into
account. Therefore, the final products hold good manufacturability and yield, and
they can be manufactured with lower cost, less time, and higher quality.
In IC, for the severe challenges of IC manufacturing process, DFM technology
mainly includes the design optimization of the front-end-of-line (FEOL) and back-
end-of-line (BEOL) of ICs to solve or to partly alleviate the difficulties of process
manufacturing, in order to improve the functional yield and parametric yield.
As process nodes of IC technology have progressed at nanoscale, IC manufactur-
ing is facing increasingly serious challenges. For example, sub-wavelength lithog-
raphy processes using light sources with 193 nm wavelength cause serious
distortions of patterns on silicon wafers, and chemical mechanical polishing
(CMP) process leads to serious deviation of interconnects in its thickness (vertical
direction). Therefore, the impacts of IC process variations become more and more
serious.
In sub-wavelength lithography, even applying resolution enhancement tech-
niques (RET), distortion phenomena such as “round-off,” “short,” and “partial
disappearance” are still easy to occur at the ends and corners of interconnects, as
shown in Fig. 44.19. The patterns, producing severe distorted patterns on wafers, are
termed lithography hotspots, which are prohibited in layouts. Designers need to
thoroughly check all hotspots with lithography hotspot detection tools before the
tape out.
Figure 44.20 describes the effect of dummy filling on chip surface topography
after chemical mechanical polishing (CMP). After inserting metal dummies, the
height variation of chip surface is obviously smaller than that if no inserting
dummies. Unfortunately, the introduced dummies will usually increase parasitic
capacitances and deteriorate circuit performances. Therefore, the main challenges
of dummy filling tools are how many dummies to insert, where to insert dummies,
and what are the shapes of dummies. The above technologies of lithography hotspot
detection and dummy insertion are commonly used in DFM.
854 X. Liu et al.

Fig. 44.19 Lithography hotspots

Fig. 44.20 The surface topography of chip before and after dummy insertion and CMP

Generally speaking, DFM technologies are an extension and optimization of

traditional EDA design flows, which usually includes the following technologies.

1. DFM-aware standard cell design not only considers the manufacturability of the
standard cell itself but also considers the interaction of lithography near the
boundary of adjacent cells. In standard cell synthesis with DFM, besides meeting
the traditional design rules, it also needs to be compatible with a large number of
new added DFM design rules. Even in order to improve yield, the standard cell
line-gap needs to be optimized. In order to be compatible with non-traditional
lithography processes, such as multiple pattern lithography (MPL) and self-
aligned double pattern lithography (SADP), and to satisfy constraints of increas-
ing tension of routing channel resources, the pin accesses need to be carefully
optimized.
2. In DFM-aware placement optimization, the effects of double/triple/multiple pat-
terning lithography (DPL/TPL/MPL) and chemical mechanical polishing (CMP)
should be taken into account during placement of processes under 20 nanometers.
3. DFM-aware routing optimization considers the compatibility with non-traditional
lithography technologies such as multiple patterning exposure and electron beam
lithography, etc., besides the optimization objectives of routability and total wire
length in traditional routing algorithms.
44 Electronic Design Automation Tools 855

4. DFM-aware mask optimization technologies include layout decomposition of

multiple exposure lithography, DSA (directed self-assembly), electron beam
lithography and their hybrids, hotspot detection technology in mask, etc.
5. Metal dummy insertion is used to improve the smoothness of chip surface
topography after chemical mechanical polishing.
6. Redundant via improves the reliability of via.

When process nodes of IC enter nanoscale, some DFM technologies are now in
the reference flows of foundries. They become the necessary steps for designers to
follow. In the foreseeable future, DFM technologies will continue to expand with the
development of emerging manufacturing and design technologies. With the help of
electronic design automation (EDA) tools with DFM-aware function, IC designers
need to fully consider the difficulties in manufacturing in the early stage of design, in
order to improve the yield of IC chips after tape out.

Design for Yield

As IC technology node continues to shrink, the adoption of complex processes has

made process variations increasingly serious. Process variation refers to the random
fluctuations in geometry and electrical parameters during IC fabrication. For exam-
ple, sub-wavelength lithography using 193 nm wavelength light source leads to
wafer pattern deviations, chemical mechanical polishing results in severe deviations
in copper interconnect height, and random fluctuations in doping cause variations in
device parameters. The process variations make the performances of ICs exhibit
significant random fluctuations. The breaks and shorts caused by process defects
such as dust may also lead to functional failure of the circuit.
Design for yield (DFY) aims to reduce the impact of process defects and process
variations on circuit performance via early design effects. In contrast, design for
manufacturability (DFM) tends to solve the manufacturing difficulties such as
chemical mechanical polishing (CMP) flatness and sub-wavelength lithography
that may exist in chip manufacturing through design effects.
Technology used in DFY firstly establishes a stochastic model of the process
variations and device models consisting of random parameters. Based on these
models, the yield estimation and optimization can be realized through circuit simu-
lation. By building the random delay models of the standard cells, the yield estima-
tion and optimization of digital circuits can also be realized.
Analog circuits are more sensitive to process variations, and the effects of
mismatch have been taken into consideration for a long time. In DFY, it is necessary
to further consider the influences of process variations on the designs. Analog circuit
designers generally improve the yield of circuits by adding margins or employing the
centralized design methodology. In recent years, there exists research on the auto-
matic yield optimization of analog circuits. Cadence’s Virtuoso design environment
provides tools such as multi-process corner optimization and yield optimization.
856 X. Liu et al.

The DFY methods of digital circuits can be divided into two categories: corner-
based method and statistical method. In nanoscale IC designs, more PVT corners are
introduced to improve the yields of the ICs. Synopsys’ IC Compiler and Cadence’s
Innovus provide the abilities of corner-based optimizations. The statistical optimi-
zation methods are still under development. IBM developed the statistical timing
analysis tool and optimized the yields based on the statistical timing analysis.
However, statistical methods have not been widely used in the industry. Synopsys
and Cadence have also recently released statistical timing analysis tools, and statis-
tical methods may become the trends for the future IC designs.
Yield enhancement includes a variety of techniques. Traditionally, it refers to the
redundant via insertion and interconnect widening techniques to reduce the failures
caused by dust defects. The yield enhancement today also refers to optical proximity
correction (OPC), dummy fill insertion for CMP technology, hotspot detection and
correction techniques, and various yield optimization techniques.
Recently, post-silicon tuning and self-healing techniques have been introduced to
improve the yield after fabrication. These methods introduce some tunable cells in
the circuits to adjust the bias, the drive capability, and the loads of the circuits. After
the circuit is fabricated, according to the actual variations of the circuits, the tunable
cells are manually or automatically tuned to improve the performances or yields.
Such a design approach can reduce the unnecessary area and power overheads
introduced to deal with process variations.
DFY is crucial for the design of nanoscale IC. The process variations should be
considered in the design stage to improve the yield. As the technology node
continues to shrink, design for yield would be more and more difficult and important.

Design for Reliability

Negative bias temperature instability (NBTI), hot carrier injection (HCI), electro-
migration (EM), electrostatic discharge (ESD), and radiation effects have great
impacts on the reliability of ICs. Design for reliability (DFR) aims to reduce the
impact of these factors on the function and performance of ICs through design
effects, which thus improves the reliability of integrated circuits.
NBTI effect refers to the drift of the threshold voltage of PMOS. At higher
temperature and negative bias, the Si-H bond at the PMOS interface breaks to create
interface traps, and the gate oxide traps capture holes, which causes the PMOS
threshold voltage (Vt) to drift, resulting in the degradation of the timing and the
failures of the circuits.
HCI effect is due to the fact that when the source-drain biased voltage of the
channel is high, part of the carriers with sufficiently high energy enters the oxide
layer, which leads to the variations of the threshold voltages and thus the timing
degradations of the circuits. As the feature size of the circuit continues to shrink, the
HCI effect becomes more and more significant.
In recent years, the reliability problems caused by NBTI and HCI effects have
attained more and more attentions. Firstly, it is necessary to establish models of the
44 Electronic Design Automation Tools 857

NBTI and HCI effects on threshold voltages. With these models, it is possible to
simulate the circuits considering these two effects in the circuit design stage. Extra
margins can be introduced to ensure that the circuit can still work under the
influences of the two effects. For NBTI, by avoiding the transistor in the critical
path operating under a negative bias for a long time, it is possible to mitigate the
effects of NBTI.
EM effect is another important factor affecting the reliability of the circuit.
When the circuit works, current flows through the metal interconnect. Metal atoms
will also be transported along with the electron flow. If the current is too large,
there are depletion of metal atoms in interconnect and eventually lead to large
cracks and even broken with high resistance or open-circuit failures. In reliability
design, the currents of critical interconnects are analyzed, and for interconnects
with large currents, the interconnect width is increased to alleviate the effect of the
EM effect.
FinFET (fin field-effect transistor) devices are widely adopted in technology
nodes below 22 nm. Compared to conventional planar transistors, the heat generated
by FinFET devices cannot be dissipated through the substrate, causing severe self-
heating effects. Self-heating can cause reliability problems in FinFET ICs. For
example, if the temperature is too high, the electromigration effect will be more
serious; likewise, the circuit performance will be degraded. The heating effect of
FinFETs is usually mitigated by improving the process and reducing the power
consumptions.
ESD effect is the main factor that damages the IC via excessive electrical stress.
The ESD protection circuit in I/Os provides a current path for electrostatic discharge,
which avoids electrostatic current flowing into the chip. ESD effect can be described
with [23] machine model (MM), human-body model (HBM), and charged-device
model (CDM). The damage can be caused by one more mechanisms described by
these ESD models.
Ionizing radiation can also cause the instability of the ICs [24]. Ionizing
radiation particles will introduce interface trap in MOS, which leads to changes in
parameters such as threshold voltage and mobility, thus affecting the performances
of the circuits. The failure caused by such long-term radiation is known as the total
ionizing dose (TID) effects. The transient current produced by radiation can also
cause short-term state inversion of sensitive devices such as SRAM cells, resulting in
soft errors. The failure caused by such radiation is known as single-event effect
(SEE). Radiation hardened circuits are widely used in military and aerospace fields.
For TID effects, processes, devices, circuits, and layouts can be hardened to improve
the stability of the circuits. For the soft errors caused by the transient currents
produced by the radiation, triple modular redundancy (TMR) design, error correction
code, or re-execution after detecting an error could be employed to improve the
stability and reliability.
For the reliability problems caused by NBTI, HCI, and EM effects, it is more
important to establish accurate physical, circuit-level, and cell-level models for
simulation. With accurate simulation, the circuits can be optimized. The ESD
protection technique is mature. Radiation hardened circuit design is a specialized
858 X. Liu et al.

field in reliability design, mainly used in military and aerospace applications. It

reduces the influences of radiation and improves circuit reliability through circuit
and process improvements and redundancy design techniques.

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tional Conference on Computer-Aided Design, 1999, Digest of Technical Papers, (IEEE, 1999),
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maximum subdomain degree minimization, in IEEE/ACM International Conference on
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(Springer, Tsinghua University Press, 2014)
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21. S. Wang, D. Wang, Application of AOCV in multi-voltage design of 28 nm process. China

Integr. Circuit 23(8), 43–49 (2014)
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Comput.-Aid. Design Integr. Circuits Syst. 27(4), 589–607 (2008)
23. D.Y. Hu, C.-Z. Chen, Reliability aspects of advanced IC technologies with ESD and anti-
radiation capabilities. ECS Trans. 60(1), 1185–1190 (2014)
24. C.-Z. Chen, Y. Sun, D.Y. Hu, H. Wu, Quality Factors of Ionizing Radiation in CMOS Transistor
Gate (CSTIC, Shanghai, March 18–19, 2019), https://ieeexplore.ieee.org/document/8755620
 Section VI
IC Manufacturing and Management
Min-Hwa Chi, Nanxiang Chen, Hanming Wu, Haijun Zhao,
and Weihai Bu

Introduction

The manufacturing of Integrated Circuits (IC) plays an important role in entire IC

industry for continuously driving new progresses of Moore’s law, more-than-Moore,
and post Moore era. IC manufacturing not only supports circuit design and product
development but also supports semiconductor equipment, materials, testing, and
packaging industry. This section systematically reviewed all aspects of VLSI
manufacturing technology, including technology evolution, Si-device structures
and physics, state- of-the-art unit process and module process, and advanced inte-
gration technology, including super junction, strained Si engineering, epi source/
drain, immersion lithography, self-aligned dual patterning technique, CMOS with
poly-gate and high-k metal gate (HKMG) technology, FinFET, Gate-all-around
(GAA), nano-wires and nano-sheet, 3D device, DRAM, 3D NAND, Floating-gate
flash memory, PCRAM, RRAM, MRAM, and Design-Technology Co-Optimization
(DTCO). This section also summarized non-Si-based devices and ICs (e.g., com-
pound Semiconductor, MEMS, Photonics) as well as heterogeneous integration
technology on Si wafers. Furthermore, this section also discussed the state-of-the-
art management and business models in IC industry.
The Evolution of IC Manufacturing
Technology 45
Weihai Bu and Wenbo Wang

Contents
Moore’s Law and Technology Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
Process of Post Moore’s Law Era . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
Technology Roadmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
FEOL, MOL, and BEOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870

Abstract
The evolution of IC (integrated circuit) manufacturing technology is mainly
based on the scaling of semiconductor devices and processes. The technology
scaling trend was predicted by the famous Moore’s Law during the past half of
century. The IC development no longer closely follows the forecast by Moore’s
Law in recent years, so the post-Moore’s Law era begins. The semiconductor
industry organizations jointly proposed general technology roadmaps, e.g., ITRS
(International Technology Roadmap for Semiconductors) and IRDS (Interna-
tional Roadmap for Devices and Systems). IC manufacturing processes are
generally divided into Front-End-of-Line (FEOL) and Back-End-of-Line
(BEOL), with Middle-of-Line (MOL) added after high-k metal gate process
and eSiGe process were introduced.

Keywords
Moore’s law · Post Moore’s law · Scaling · Roadmap · FEOL · MOL · BEOL

W. Bu (*)
Semiconductor Technology Innovation Center (Beijing) Corporation, Beijing, China
e-mail: weihai_bu@sticbj.com
W. Wang
SiEn (Qingdao) Integrated Circuit Co., Ltd., Qingdao, China

© Publishing House of Electronics Industry 2024 863

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_45
864 W. Bu and W. Wang

Moore’s Law and Technology Scaling

CMOS technology is continuously scaled down as one of the most important

features in the development of IC (integrated circuit) technology. ICs (also called
chips) integrate many components and devices together on the wafer using semi-
conductor planar technology to form specific functions, such as miniaturized
(scaled) transistors, resistors, capacitors, inductors, interconnect lines, and other
components. ICs are closely related to the process technology and its scaling
capability. Technology scaling means that the scaled devices can be fabricated as
the advancement of process technology, so that more devices can be integrated on
the same chip area. The key parameters such as the line width and spacing in the
active areas, gates, contact holes, metal interconnects, etc. in the IC are called feature
sizes or critical dimensions (CD). The technology with a set of feature sizes of
devices is called a technology node or generation, such as 0.35 μm technology node
in the 1990s, 90 nm technology node in the early 2000s, and 10/7 nm technology
node in manufacturing at 2019. At different technology nodes, the feature sizes that
determine the integration density of ICs are different. In short, the scaling of the
feature size leads to greatly enhanced integration density, chip performance, and
costs. Therefore, the advancement of IC technology is aimed at scaling device size
with improved price/performance; the IC manufacturing technology is increasingly
difficult and complicated. Figure 45.1 shows the rapid increase in the number of
transistors integrated on a single microprocessor from 1971 to 2017. In 1989, Intel’s
CPU 80486 integrated about one million transistors. In 2015, Oracle’s SPARC M7

Fig. 45.1 Increase in the number of transistors integrated on a single microprocessor from 1971
to 2017
45 The Evolution of IC Manufacturing Technology 865

integrated 10 billion transistors [1] in a chip. Technology scaling (or the advance-
ment of IC) over the past 50 years has followed Moore’s Law [2].
Moore’s Law was first proposed in 1965 by Gordon Moore, one of the founders
of Fairchild Semiconductor Corp. and Intel Corp. The general statement of Moore’s
Law is that, under the assumption of maintaining the lowest unit cost, the number of
transistors integrated in an IC doubled every 2 years and also the performance and
integration density. Therefore, each technology node of IC is approximately scaled
0.7 linearly and 0.5 in area from the previous node. Moore’s Law forecasts the
pace of information technology development and guides the long-term roadmap and
R&D targets for IC industry [4]. Although this trend has been going on for more than
half a century, Moore’s Law is considered as a predictive observation on the
development of IC technology and industry and essentially an economic law. The
realization of Moore’s Law enables consumers to continue buying higher perfor-
mance products at lower prices. From the development of several technology nodes
after 22 nm, the pace of IC development appears gradually slowing down than the
Moore’s Law. Currently, Intel takes 2.5 years or longer to introduce a new generation
of technology. The long-term effectiveness of Moore’s Law is largely related to the
progresses of IC manufacturing technology with innovations in new devices, pro-
cesses, and materials.

Process of Post Moore’s Law Era

The post-Moore’s Law era or the post-Moore era refers to the new era that IC
industry and technology are facing after Moore’s law “failing” or “slowing down.”
In this era, the IC development no longer closely follows the forecast by Moore’s
Law. Since Moore’s Law was proposed more than half a century ago, it has been
predicted to be failing more than once. However, in actual development, scientists
and engineers can keep Moore’s law valid by using innovative new technologies,
devices, materials, etc. in IC technology until the technology feature size more and
more approaches the physical limit. From recent technology advancement, Intel, as
the world leader in IC, took 2.5 years to develop from 22 nm to 14 nm nodes, and it
takes 3 years to develop from 14 nm to 10 nm nodes (Fig. 45.2) [3]. After 10 nm
node in manufacturing in 2019, Intel’s 7 nm technology node may be in mass
production in 2022. TSMC has adopted a more relaxed design rule (than Intel’s) in
the definition of new technology node; thus, it appears that TSMC can still maintain
the trend of technology development with one node advancement every 2 years. As
of 2019, the maturity of EUV lithography scanner is meeting the requirements of
advanced manufacturing. If the 193 nm immersion lithography technology continues
to be used in advanced technology nodes, one design layer must be divided into three
or even four patterning layers. As a result, the difficulty of patterning in the scaled IC
technology is greatly increased. Therefore, it is often mentioned that Moore’s Law is
about to end or has ended, so that the IC industry is entering the post-Moore era.
Moreover, the traditional naming of technology node (e.g., 0.13 μm) was directly
related to the feature sizes of devices (e.g., the minimum physical gate length);
866 W. Bu and W. Wang

Fig. 45.2 Intel’s IC technology scaling roadmap

however, in the post-Moore era, the definition of the technology node is no longer
directly related to any single feature size, but related to the integration density (e.g.,
doubled with respect to the previous node).
The industry has proposed two options in the development of post Moore’s Law,
i.e., “More Moore” and “More than Moore.” “More Moore” means that technology
scaling continues as Moore’s law with new device structures, processes, and mate-
rials introduced. FinFET is expected to be used up to 7 nm node, and 5 nm node, and
beyond may introduce the new gate-all-around (GAA) nanowires (NW), nanosheet,
or other new 3D devices [3, 4]. The EUV lithography is expected for mass produc-
tion at 7 nm or 5 nm nodes. “More than Moore” includes developing various
advanced technologies for specific applications in post-Moore era (e.g., RF, Mem-
ories, Imagers, etc.). The overall integration density and performance of the chip can
be further improved while maintaining the cost reduction with 3D monolithic
integration and 3D packaging technologies, such as SiP. The Si-based optical
interconnects and other non-Si-based new technologies may also be applied for
mass production.

Technology Roadmap

The technology roadmap refers to the forecast of trend in technology development

for a period of time formulated collectively by IC industry-related associations or
enterprises. It generally includes the long-term and short-term roadmaps. IC
45 The Evolution of IC Manufacturing Technology 867

manufacturing technology progresses rapidly as a highly complex process, and the

industrial segmentation is relatively fine in the industry chain. IC manufacturers need
to face many different IC customers, and also implement various equipment, soft-
ware and raw materials from different vendors in IC industry. In order to ensure that
companies in the IC industry maintain a more consistent pace of development
compatible with Moore’s Law, the semiconductor industry organizations jointly
proposed general technology roadmaps that follow Moore’s Law. Among them,
International Technology Roadmap for Semiconductors (ITRS) is the most repre-
sentative. ITRS mainly elaborates the challenges and possible solutions faced by
various technologies in the field of IC from various technical perspectives. It predicts
the time of future technology nodes as well as the specific device and process
parameters, electrical targets, etc., and various emerging technologies are also
summarized. For a long time in the past, ITRS was an important basis and standard
for academic research and industrial development. However, in recent years, due to
the increasing challenges in the development of IC technologies, leading IC manu-
facturers are unable to develop products with the pace of ITRS. However, ITRS still
plays a role as reference guidelines.
The latest edition of ITRS was released in 2015 with forward looking to the
technology trends of 2030. ITRS claims that the mode of PC-driven for the perfor-
mance improvement of microprocessors will gradually be replaced by the new mode
of IC development as driven by the smart terminals for artificial intelligence (AI) and
Internet-of-Things (IoT). Therefore, ITRS 2015 is called ITRS2.0 because it has
been greatly revised compared to ITRS 2013. ITRS 2015 mainly focused on seven
sections, i.e., system integration, heterogeneous integration, heterogeneous compo-
nents, outside system connectivity, more Moore, beyond CMOS, and factory inte-
gration. Table 45.1 shows the ITRS2.0 Roadmap (partial).
In addition to ITRS, there are other technology roadmaps proposed by other IC-
industry-related organizations, such as Nano Electronics Roadmap for Europe and
System Device Roadmap Committee of Japan. In 2016, IEEE also developed the
International Roadmap for Devices and Systems (IRDS). Moreover, leading IC
manufacturers have also launched their own technology roadmaps, though forecast-
ing over shorter time period but to be updated yearly based on technology and
market trends.

FEOL, MOL, and BEOL

IC manufacturing process is generally divided into Front-End-of-Line (FEOL) and

Back-End-of-Line (BEOL). FEOL generally refers to the manufacturing process of
devices and mainly includes isolation formation, gate structure, source and drain,
contact holes, and so on. BEOL generally refers to the formation of interconnect
metal lines used to transmit electrical signals among devices in a chip, such as
dielectric deposition, metal lines, and pads formation. Generally, contact holes
 868

Table 45.1 ITRS2.0 Roadmap (partial) [4, 5]

Year of mass production 2015 2017 2019 2021 2024 2027 2030
Logic tech. node 16 nm/14 nm 11 nm/10 nm 8 nm/7 nm 6 nm/5 nm 4 nm/3 nm 3 nm/2.5 nm 2 nm/1.5 nm
逻辑器件结构选项 FinFET FinFET FinFET FinFET LGAA VGAA VGAA
FD-SOI FD-SOI LGAA LGAA M3D M3D M3D
VGAA
Basic DR of Half pitch of mx in 28.0 18.0 12.0 10.0 6.0 6.0 6.0
logic device MPU/SoC
Half pitch of M0/M1 in 28.0 18.0 12.0 10.0 6.0 6.0 6.0
MPU/SoC
Half pitch of CPP 35.0 24.0 21.0 16.0 12.0 12.0 12.0
(contacted poly pitch)
Physical gate-length of 24 18 14 10 10 10 10
HP logic tech.
Physical gate-length of 26 20 16 12 12 12 12
LP logic tech.
W. Bu and W. Wang
45 The Evolution of IC Manufacturing Technology 869

formation is regarded as the divider between FEOL and BEOL. Contact holes are
formed by patterning (contact holes) and dielectric etching in vertical direction and
followed by tungsten (W) filled as W-plug to connect the first metal layer and the
transistors. Via is the connection path between two adjacent metal layers, and located
in the dielectric layer between the two metal layers, filled with metal, e.g., aluminum
(Al), tungsten (W), or copper (Cu).
To improve transistor performance, the high dielectric constant (high-k, or HK)
gate dielectric and metal gate process (MG) are introduced since 45 nm / 28 nm
nodes. Replacement metal gate (RMG) and Local Interconnect (LI) process are
added after transistor source/drain formation. These processes are between FEOL
and BEOL, and not used in the earlier conventional process, so it is often referred to
as Middle-of-Line process (MOL).
Generalized IC manufacturing should also include steps such as testing and
packaging. Relative to testing and packaging, component and interconnect
manufacturing are the first part of IC manufacturing, and collectively referred as
Front-End (FE) process, while testing and packaging are referred as Back-End
(BE) process. Figure 45.3 illustrates the IC manufacturing process for clearly
indicating the FEOL and BEOL as well as the front end and back end of the entire
IC manufacturing processes.

Fig. 45.3 Schematic diagram of the manufacturing process of the IC

870 W. Bu and W. Wang

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Trans. Electron Devices 69(3), 922 (2022)
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M.G. Bardon, M.H. Na, A. Spessot, S. Biesemans, Future logic scaling towards atomic channels
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5. ITRS2.0 Publication. http://www.itrs2.net/itrs-reports.html
Silicon-Based Integrated Circuits
46
Weihai Bu, Wenbo Wang, and Poren Tang

Contents
Bipolar Junction Transistor (BJT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
Fin Field Effect Transistor (FinFET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Fully Depleted SOI (FD-SOI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
Super Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
Laterally Diffused MOSFET(LDMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
Integrated Passive Devices (IPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
Integrated Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Integrated Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Integrated Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

Abstract
Bulk silicon (Si) substrates and silicon-on-insulator (SOI) substrates are the basic
substrate materials for silicon-based ICs. Refer to Sect. 9 of this book for detailed
information of polycrystalline Si, single crystal Si, Si wafer with epitaxy, SOI
substrate, and testing of Si wafers. Si-based devices are the fundamental compo-
nents of ICs. Si-based devices mainly include bipolar junction transistor (BJT),
MOSFET, FinFET, fully depleted SOI (FD-SOI), super junction (SJ), lateral
diffusion MOS (LDMOS), integrated passive device (IPD), etc.

W. Bu (*)
Semiconductor Technology Innovation Center (Beijing) Corporation, Beijing, China
e-mail: weihai_bu@sticbj.com
W. Wang
SiEn (Qingdao) Integrated Circuit Co., Ltd., Qingdao, China
P. Tang
Semiconductor Manufacturing International Corp, Shanghai, China

© Publishing House of Electronics Industry 2024 871

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_46
872 W. Bu et al.

Keywords
BJT · MOSFET · CMOS · FinFET · Tri-gate · FD-SOI · GAA · Power device ·
Super junction · LDMOS · Passive device

Bulk Si substrates and Si-on-insulator (SOI) substrates are the basic substrate
materials for Si-based ICs. Refer to Sect. 9 of this book for detailed information of
preparation of polycrystalline Si (poly-Si), single crystal Si, Si wafer with epitaxy,
SOI substrate, and testing of Si wafers. Si-based devices are the fundamentals of
IC. Si-based devices mainly include bipolar junction transistor (BJT), MOSFET,
FinFET, fully depleted SOI (FD-SOI), super junction (SJ), lateral diffusion MOS
(LDMOS), integrated passive device (IPD), etc.

Bipolar Junction Transistor (BJT)

Bipolar junction transistor (BJT) is one of the most important devices in the history
of IC development. Different from MOS transistors, when bipolar transistors are in
operation, both electrons and holes are involved in conduction and referred to as
bipolar transistor. As shown in Fig. 46.1, a BJT can be viewed as two back-to-back
pn junctions integrated together. Based on different combinations of pn diodes, BJT
can be divided into n-p-n and p-n-p types. Taking one n-p-n transistor as an example,
the p-doped region is the base (B), and the two n-doped regions on the side of base
are the emitter (E) and the collector (C), respectively. When the n-p-n BJT turns on,
the emitter junction (i.e., base-emitter) is positively biased, and the collector junction
(i.e., base-collector) is reverse biased. The emitter injects electrons into the base
region under positive bias. Some of these electrons will be recombined with holes in
base as base current, and most of these electrons will be continuously moved toward
and collected at the collector under high reverse electric field as collector current.
Because the base region is normally thin and low in doping, the captured base
current is much smaller than the collector current; this is the amplification principle

Fig. 46.1 Schematic of BJT structure

46 Silicon-Based Integrated Circuits 873

of the base current in bipolar transistor. Figure 46.1 illustrates the structures of npn
and pnp bipolar transistors (BJT).
BJT is a bulk device, where the electrons and holes are transported in the bulk of
semiconductor; thus BJT has the characteristics of high trans-conductance, speed,
and power consumption. In fact, before the 1970s, most of ICs were designed mainly
on bipolar transistors. With integration density increasing, the power consumption
and heat dissipation of ICs becomes more and more prominent, and BJT were
gradually replaced by MOS transistors mainly due to the much smaller leakage
current of MOS transistors. Though currently most ICs are based on CMOS tran-
sistors, BJT is still widely used in analog, RF and high-speed, high power circuits as
related to its larger current gain, and higher trans-conductance (than MOS
transistors).

MOSFET

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most impor-

tant elements of ICs. Metal, oxide, and semiconductor serve as gate electrode, gate
dielectrics, channels, and source/drain in the MOSFET respectively, i.e. the basic
MOSFET consists of gate, source, drain and body. The concentration of electrons
and holes in the channel region can be controlled to form accumulation, depletion,
and inversion by applying the gate voltage. The transistor realizes the switching
on/off functions based on these operations. Depending on the types of channel
doping, MOSFETs have two types: n-type MOSFET (or nMOSFET, nMOS,
n-MOS, or n-FET) and p-type MOSFET (or pMOSFET, pMOS, p-MOS, or
p-FET). These MOSFETs are referred to as complementary MOSFET
(C-MOSFET or CMOS). The channel of the planar MOSFET is a plane, and the
source and drain (source/drain) is self-aligned with respect to the gate with relatively
simple fabrication process. After replacing BJTs, planar MOSFETs dominated in the
development of ICs.
A conventional planar MOSFET has only one gate, and the single-gate device has
limited channel controllability. It faces a dilemma in the scaling of IC technology: on
the one hand, the short channel effect related to the small channel length is to be
suppressed by higher doping in the channel and thinner gate dielectric; on the other
hand, the very high channel doping and thin gate dielectric will result in random
doping fluctuation effect, gate leakage, channel mobility degradation, and higher
noise. The problem of device leakage and performance degradation becomes more
and more serious, especially when IC technology progressed to 20 nm technology
node and beyond. To enhance the gate-to-channel control, fully depleted SOI
MOSFETs and three-dimensional (3D) multi-gate MOSFETs (or FinFET) become
replacements for single-gate planar MOSFETs in advanced 14 nm, 10 nm, and 7 nm
technology nodes.
874 W. Bu et al.

Fin Field Effect Transistor (FinFET)

FinFET is a type of 3D multi-gate devices with features of folded thin-fin

like channel with surrounded double or triple-gate as shown in Fig. 46.2. Thinner
channel and multi-gate electrode can improve the gate control capability of
the channel and ensure that the device operates in a fully depleted mode. Compared
with planar CMOS devices, FinFET has obvious capability in suppressing the short
channel effects, improving device performance, and reducing leakage current due to
its 3D fully depleted structure. With the better control of short channel effects, the
channel doping of FinFET can be significantly reduced for improving the mobility
degradation and random doping fluctuations. The double-gate or tri-gate FinFET can
significantly improve the subthreshold slope of the device to be close to
60 mV/decade [1]. On the same Si wafer area, FinFET can result in larger effective
channel width for stronger driving capability.
FinFET was named in 1999 by the team of Chenming Hu of the University of
California, Berkeley [2]. The original concept was named as DELTA (depleted lean-
channel transistor) device [3], or tri-gate transistor [4] by Intel Corporation. In the
technical literatures, these Fin-based multi-gate devices (whether double-gate or
triple-gate) are all referred to as FinFETs.
Prior to 2006, the fabrication of FinFETs did not include the source-drain
selective epitaxy and strained Si technology, thus the drive current was generally
lower (than modern FinFET). Also the discrete nature of fins leads to less flexibility
to adjust the channel width for IC designers. Intel’s paper published in 2006 firstly
used source-drain epitaxy at source-drain area for strained Si; thereby the mobility is
enhanced and contact resistance is reduced. FinFETs can achieve sufficient drive
capability with the drive currents of both nMOS and pMOS to more than 1 mA/μm
[5]. In addition, IC designers could adjust channel width of FinFETs by using
different numbers of fins.

Fig. 46.2 Schematic diagram of two devices

46 Silicon-Based Integrated Circuits 875

FinFETs also face many challenges in mass production, e.g., large aspect ratio of
fins to be patterned and etched precisely, smooth surface and defect free, fin doping
by implants, and damage-free processes post-fin formation,. The non-planar wafer
surface due to the fin structure results in challenges in etching and gap filling,
sidewall spacer formation, etc. The increase of fin height can result in larger effective
channel width, but the parasitic capacitance also increases. The effective channel
width as achieved by the number of fins is discrete in nature and less flexible in IC
design.
FinFET technology was matured in mass production for the first time by Intel at
22 nm node; it is the mainstream technology for IC manufacturing at 16 nm/14 nm
nodes and beyond. In 2015, Intel, Samsung, TSMC, and GlobalFoundries were all
capable in manufacturing at 16 nm and 14 nm nodes of FinFET technology. As of
May 2019, Samsung and TSMC are in volume manufacturing 10 nm and 7 nm
FinFET technology. With high mobility channel materials, such as III-V compound
materials for nMOS and Ge/SiGe for pMOS, the performance of FinFET can be
further improved at 5 nm node. Currently, the most recent progress in gate-all-around
[6] and 3D devices [7] are maturing at 3 nm nodes.

Fully Depleted SOI (FD-SOI)

Silicon-on-insulator (SOI) wafer is composed of a top Si layer, a buried oxide layer,

and a Si substrate. With the development of IC technology, bulk Si substrate CMOS
faces many challenges (e.g., latch-up effect, short channel effect, increased leakage
current, threshold voltage shift, increased parasitic capacitance, etc.). ICs on SOI
substrate (referring to SOI-IC) can suppress the above problems. SOI-ICs have more
efficient dielectric isolation between devices; it can completely eliminate the para-
sitic latch-up effects. The parasitic capacitance and RC delay are reduced, leading to
better operation speed. The short channel effect is suppressed with reduced power
consumption. Finally, the fabrication of SOI-IC uses less photomask quantity and
has simpler process flow (e.g., no need of STI isolation). The SOI devices can be
divided into partially depleted SOI (PD-SOI) and fully depleted SOI (FD-SOI)
devices according to whether there is a neutral (i.e., not depleted) region in the
channel region when the device is in operation, as shown in Fig. 46.3. The top Si
layer of the FD-SOI device is thinner, and the Si layer is completely depleted when
transistor is in operation. FD-SOI devices eliminate the Kink effect and the parasitic
BJT caused by the neutral region. In the meantime, the ultra-thin top Si layer
improves gate-to-channel controllability and subthreshold swing, so FD-SOI devices
have good short-channel characteristics.
Some analysts believe that from 28 nm and 20 nm nodes, cost per single transistor
will not fall any more or even increases, based on bulk Si CMOS and FinFET
processes. The main supporters of FD-SOI technology (e.g., IBM, STM,
GlobalFoundries, etc.) believe that FD-SOI will be more competitive at advanced
nodes. FD-SOI technology has certain advantages in low-leakage and low power
applications. Based on its excellent gate control capability, FD-SOI technology can
876 W. Bu et al.

Fig. 46.3 Schematic diagram of device structure on different substrates

Fig. 46.4 Schematic of SOI

FinFET technology

continuously extend the process of planar CMOS. In addition, some companies and
research institutes are also studying the FinFET on SOI technology as shown in
Fig. 46.4.
Compared with bulk Si FinFET, FD-SOI is still a planar structure and the process
is easier and lower in manufacturing cost. SOI process is relatively simple, but the
SOI substrate material is a little bit more expensive (than bulk) and somewhat
limiting the wide applications. The ecological environment of FD-SOI is also a
limiting factor as lack of simulation software, design IPs, and design tools than those
for bulk Si technology. Therefore, FD-SOI is mainly used for low power and low
leakage applications.
46 Silicon-Based Integrated Circuits 877

Super Junction

Super junction (or super-junction, SJ) is a technology for manufacturing power field
effect transistors. Its name first appeared in 1993 [8]. The breakdown voltage of the
traditional high-voltage (n-type) power MOSFET is mainly determined by the
voltage tolerance of the depletion region of pn junction (i.e., the n-type epitaxial
layer and p-type body). The voltage blocking on the depletion region is mainly on
the side of n-epitaxial layer as the p-type body region has higher doping. In order to
increase the breakdown voltage, one can use lower doping of epitaxial n-layer and
larger thickness. However, both the lower doping and thicker film will increase the
on-resistance of the power MOS transistor; this leads to increase the power con-
sumption during. Due to the above trade-off, the on-resistance of the conventional
high-voltage power MOS transistors is limited by the breakdown voltage referred to
as “Si limit” in the industry. In order to break through this limit, academician Chen
Xingbi of the Chinese Academy of Sciences and other scientists proposed three
methods to improve the structure of the drift layer from 1988 to 1995. These
methods are the basis of super junction. Taksuhiko et al. summarized the idea of
super junction and proposed the concept of “super-junction theory” in 1997 [9].
Figure 46.5 illustrates a comparison between a conventional power MOSFET and a
typical super junction MOSFET [10].
As shown in Fig. 46.5b, the super junction MOSFET is different from conven-
tional power MOSFETs. It has a p-type region deep into the epitaxial n-layer in the
vertical direction. The doping concentration of the p-type region is lower than that of
the original p-type body. Such device structure can compensate for the charge at
n-epi layer and greatly expand the depletion region of the pn junction to the side of
the p-type region. The depletion region works as voltage drop layer and relaxes the
requirement of breakdown voltage for n-epitaxy. Under the same breakdown

Fig. 46.5 Schematics of two different structures of power MOSFETs

878 W. Bu et al.

voltage, the doping concentration of the n-epi layer of the super junction MOSFET
can be increased, and the on-resistance can be greatly reduced. Compared with tradi-
tional power MOSFET, super junction MOSFET has many advantages (e.g., lower
conduction loss, higher drive current capability, lower gate charge, lower turn-on
voltage, faster switching speed, more excellent unclamped inductive switching (UIS)
capability, and 100% avalanche breakdown test). However, the super junction structure
has some problems and defects (e.g., the structure is more complicated and difficult in
fabrication process with higher cost; the np composite structure also leads to a worse
reverse recovery of the device).
For the fabrication process, the main feature of the super junction power MOSFET
process is that multiple parallel n-type and p-type composite implant regions need to be
formed in the vertical direction, wherein the n-type region and the p-type region have
high aspect ratio and high vertical tilt angle (typically 85
–89.5
). These requirements
result in more complexity in the process of super junction power MOSFETs. At present,
the mainstream super junction power MOSFET process can be divided into two
methods; one is multiple ion implantation and epitaxy and the other is deep trench
etching and filling technology. In the method of ion implantation, the depth and the high
aspect ratio of the super junction n-type region and the p-type region are often not
ensured by ion implantation alone; and usually a combination of multiple ion implan-
tations and multiple epitaxial processes are required. The process of implementing a
super junction power MOSFET through a deep trench process is to epitaxially grow
n-layer on an n þ substrate firstly, then etching to form a deep and steep Si trench, and
then epitaxially filling the p-type Si to form a super junction structure.
Infineon is the first company in the world to achieve mass production of super
junction MOSFETs. Shanghai Huahong Grace Semiconductor Manufacturing Cor-
poration can provide super junction MOSFET foundry service on 200 mm wafers,
and there are products with different voltage levels of 500–900 V based on deep
trench process. The super junction technology can also be used for IGBTs (insulated
gate bipolar transistors).

Laterally Diffused MOSFET(LDMOS)

The structure of a conventional LDMOS device is illustrated in Fig. 46.6. The

process scheme is briefly described here. The two impurities as doped in the same
window region (p-Ext and n þ source) have different diffusion coefficients, doping
levels and polarities. After high temperature process, the impurities with larger
diffusion coefficient made a longer lateral diffusion (d1 in Fig. 46.6) and form a
channel (d1) with gradient concentration. The polarity of the window region is
determined by impurities with higher doping concentration, transistor source
formed. Generally, LDMOS devices endure a relatively high drain voltage. Reduced
surface field (RESURF) technology can improve the breakdown voltage at drain
(BVD). By designing drift region (as n-Well in Fig. 46.6) with low doping
46 Silicon-Based Integrated Circuits 879

Fig. 46.6 Structure of a traditional LDMOS device

concentration between the channel and drain, width of drain pn junction depletion
layer and breakdown voltage can be increased. Factors such as doping concentration
of drift region and pn junction depth affect the drain breakdown voltage. Synchro-
nized optimization of device on-resistance (Ron) and breakdown voltage can be
achieved by optimizing the doping profile of the drift region or introducing impu-
rities with the opposite polarity in the drift region. For LDMOS devices, proper
design of field-plate (FP) (e.g., oxide thickness, field length, and location) can reduce
the electric field at the edge of the field plate; this leads to gentle variation of electric
field for higher breakdown voltage. The poly-Si gate is shown in Fig. 46.6 with one
portion (d2) controlling the turn on and off of the channel and the other portion
extending above the field oxide (see d3) as a field plate. The spikes of electric field at
the edge of the field plate on surface can be eliminated and thus premature break-
down of the device can be avoided [11].
Shallow trench isolation (STI) or deep trench isolation (DTI) is introduced in
advanced IC technology. The drift region and channel can be formed by ion
implantation technology instead of relying on the differences in lateral diffusion of
the n and p doping. That results in complementary LDMOS possible [12]. Compared
with bipolar transistors (BJT), LDMOS transistors have higher gain, better fre-
quency stability and thermal stability, simpler bias circuit, constant input impedance,
lower thermal resistance and noise, and better durability. LDMOS is suitable for
communication applications with wide frequency range, high linearity, and long
service life. LDMOS [13] is widely used due to its excellent process compatibility
with CMOS. The schematic diagram of a fully isolated LDMOS device structure and
CMOS compatible flow is shown in Fig. 46.7.

Integrated Passive Devices (IPD)

Integrated passive devices (IPD) are the passive components (e.g., resistors, induc-
tors, capacitors, transmission lines, power dividers/combiners, and metal intercon-
nects) integrated on a single chip. Its preparation processes are compatible with IC
880 W. Bu et al.

Fig. 46.7 Schematic diagram of the process flow with fully isolated LDMOS device compatible
with CMOS process

fabrication processes (e.g., thin film, photolithography, and etching). IPD can reduce
product size and improve product performance.

Integrated Resistors

There are many types of integrated resistors, which can be generally divided into two
types: non-metal and metal resistors. Traditionally, the former are commonly used in
Si-based IC processes, while the latter in compound semiconductor processes.
However, with the development of Si-based IC, especially the introduction of
high-k metal gate process, metal resistors can also be a candidate. The non-metal
resistors refer to the resistors made of semiconductor material or poly-Si with the
resistivity depending on doping level. Based on this, non-metal resistor can be made
by using diffusion, ion implantation, and annealing process, where the doping level
of the semiconductor material and poly-Si can be tuned. Simultaneously, the desired
shape and size of resistor can also be obtained through the layout design. Metal
resistor refers to deposit a thin metal film on the dielectric by using evaporation or
sputter coating technique and then remove the excess metal by photolithography
etching or lift-off process to form proper resistance value. Commonly used metal
resistor materials are nickel-chromium (Ni-Cr) alloy, tantalum nitride (TaN), and
titanium nitride (TiN).

Integrated Capacitors

They are usually divided into metal-oxide-semiconductor (MOS) capacitors, metal-

insulator-metal (MIM) capacitors, PN junction capacitors, interdigital structure
capacitors, etc., which can be fabricated by semiconductor processes.
46 Silicon-Based Integrated Circuits 881

Integrated Inductors

There are three types of integrated inductors: the single turn coil, the multi-turn coil,
and the transmission line. Among them, the multi-turn coil is divided into the spiral
and the angle type. Capacitors and inductors are fabricated by metal deposition,
electroplating thickening, and wet or dry etching processes. These process steps are
simple but require precise control. High-quality capacitors and inductors play a
direct role in filtering, decoupling, and reducing phase noise in matching circuits.

Interconnections

Connection of components on the chip can be realized by using interconnection

lines. In order to improve the integration of the chip and reduce parasitic effects, the
interconnection lines should be as narrow and short as possible under the premise of
meeting the current density requirement. Small current interconnect line fabrication
should select the minimum line width as provided in the process. A design with long
interconnect line should take the delay into consideration. When the operating
frequency is in the microwave and millimeter wave (mm-wave) range, the intercon-
nect lines cannot be treated as pure resistors; the effects of parasitic parameters and
skin effect need to be considered.

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Compound Semiconductor Device and IC
47
Min-Hwa Chi, Ying-Kun Liu, and Long Qin

Contents
Compound Semiconductor Power Devices and Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
SiC Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
GaN Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
High Mobility Channel ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
III–V CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Tunneling FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
2D Material for Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Si Photonics ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
Waveguides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
Photodetectors, Modulators, and Lasers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
Radio Frequency Integrated Circuits (RFICs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Microwave Monolithic Integrated Circuits (MMIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Si-MMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
GaAs-MMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
SiGe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
GaN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
InP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Graphene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894

Abstract
The first generation of semiconductor material is represented by Si and Ge in
Group IV, and the second and third generations of semiconductor materials are
mainly compound semiconductors (CS), e.g., GaAs and InP (the second gener-
ation) as well as GaN and SiC (the third generation of CS materials). Those
compound semiconductor (CS)-based discrete devices and ICs have superior
M.-H. Chi (*)
GTA Semiconductor Co., Ltd., Shanghai, China
e-mail: minghua_ji@gtasemi.com.cn
Y.-K. Liu · L. Qin
Hebei Semiconductor Research Institute, Shijiazhuang, China

© Publishing House of Electronics Industry 2024 883

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_47
884 M.-H. Chi et al.

capability than Si-based discrete devices and ICs; e.g., GaN is suitable for higher
operation frequency, SiC for higher operation temperature and voltage, InAs and
GaAs capable for light emission, and MoS2 or WSe2 with higher mobility. These
CS materials have superior material characteristics than Si, e.g., larger bandgap,
direct bandgap for light generation, etc. However, Group III-V or II-VI CS
materials are considered as cross-contaminants to Si devices in modern CMOS
fab. Also, only small diameter substrate available (e.g., 150 mm in diameter or
smaller), thus it is slow and difficult in developing and manufacturing full
CS-based devices and ICs. Instead, enabling technology for forming high quality
CS material on SOI or bulk Si substrate (with large wafer size or on selective
areas) is highly desirable, so that not only the capability of Si-based IC can be
expanded, but also accelerating CS-based devices and ICs in manufacturing
toward many new applications.

Keywords
Compound semiconductor · Power device · SiC · GaN · High-mobility channel ·
Si photonics · RFIC · MMIC

The first generation of semiconductor material is represented by Si and Ge in Group

IV, and the second and third generations of semiconductor materials are mainly
compound semiconductors (CS), e.g., GaAs and InP for the second generation as
well as GaN and SiC for the third-generation CS materials. Those compound semi-
conductor (CS)-based discrete devices and ICs have superior capability than Si-based
discrete devices and ICs; e.g., GaN is suitable for higher operation frequency, SiC for
higher operation temperature and voltage, InAs and GaAs capable for light emission,
and MoS2 or WSe2 with higher mobility. These CS materials have superior material
characteristics than Si, e.g., larger bandgap, direct bandgap for light generation, etc.
However, Group III-Vor II-VI CS materials are considered as cross-contaminants to Si
devices in modern CMOS fab. Also, only small diameter single crystal substrates are
available (e.g., 150 mm in diameter or smaller); thus it is slow and difficult in
developing and manufacturing full CS-based devices and ICs. Instead, enabling
technology for forming high quality CS material thin-film on SOI or bulk Si substrate
(with large wafer size or on selective areas) [1, 2] is highly desirable, so that not only
the capability of Si based IC can be expanded, but also accelerating CS-based devices
and ICs in manufacturing toward many new applications.

Compound Semiconductor Power Devices and Integration

SiC Integrated Circuits

SiC has a wide bandgap and widely used in high voltage and high power devices,
e.g., discrete power MOSFET and insulated gate bipolar transistor (IGBT). These
power devices integrated with digital and analog IC (e.g., gate driver, regulator,
47 Compound Semiconductor Device and IC 885

and configurator) together to form silicon carbide (SiC) ICs for multiple applica-
tions, e.g., high-speed railroad, hybrid automobile, battery charger, avionics, and
deep-mining machinery and other applications in extreme environments. The devel-
opment of SiC ICs is limited by the lack of stability and accuracy of fabrication
process. In the twenty-first century, semiconductor manufacturing industry has been
developing more stable and advanced new technology, which makes the design of
SiC mixed signal integrated circuit and more complex digital integrated circuit begin
to be realized, e.g., 15 V 1.2 μm CMOS based flow [3] (HiTSIC flow from
Raytheon). Common SiC substrate is mainly 400 in diameter (100 ¼ 25.4 mm),
some are 600 (i.e., 150 mm). Recent new method [4] shows that vapor-liquid-solid
(VLS) method with metal as catalyst can eliminate or reduce dislocation defects
significantly; thus, it is possible to grow single crystals (3C-SiC) in selective area on
Si substrate.

GaN Integrated Circuits

GaN discrete devices have shown superior performance in power switching and
microwave/millimeter wave applications. By integrating the power switch and its
driver circuit on the same chip, parasitic inductance can be significantly reduced
(for better reliability and performance of power ICs) and the cost of assembly and
packaging is also reduced as greater advantages. The main difficulty in realizing
GaN ICs is in the formation of p-MOSFET; one flow is shown in reference [5]:
(a) epi GaN is grown selectively on the same chip for nMOS and pMOS transistors
formation. (b) AlN/Si3N4 dielectric layers are grown by MOCVD as gate dielec-
tric of nMOS and pMOS transistors as in Fig. 47.1. GaN single crystal films grown
on different substrates (e.g., SiC or Al2O3) can be used to fabricate GaN-based
CMOS ICs, but these substrates (SiC or sapphire) are also small in size (400 or
150 mm) and expensive, so it is highly desirable to develop large area (or specific
area) growth on Si substrates, e.g., Technology of Hetero-epitaxy GaN Single
Crystal Films [6].

High Mobility Channel ICs

III–V CMOS

Compared with Si materials, germanium silicon (SiGe), germanium (Ge), and III-V
compound semiconductor materials have higher mobility [7]. They can be used as
channel materials for CMOS for continuous scaling of Si-based CMOS. These
materials still face the following challenges: (a) Ge and III-V compounds have
higher dielectric constant and smaller bandgap than Si. If they are used as the
channel materials in planar CMOS, they will have larger Short Channel Effect
(SCE) and leakage current; but those CMOS with FinFET structure can have better
gate control over channel and reduce leakage current. At present, Ge, SiGe, and
InGaSb all have higher hole mobility and are more suitable as p-type channel
886 M.-H. Chi et al.

Fig. 47.1 Illustration of GaN nMOS and pMOS formation on the same sapphire [5]

materials. InGaAs is the first choice for n-channel materials, but there are still many
difficulties in optimizing contact resistance, reducing off-state current, improving
reliability, and Si integration. (b) In order to avoid the complication of CMOS
integration, a single channel material system [8] is much easier for the formation
47 Compound Semiconductor Device and IC 887

of n-type and p-type MOSFETs with good performance. AlGaSb/InGaSb structure is

a good choice due to higher electron and hole mobility as related to their energy band
structure. (c) The integration process of non-Si materials: large lattice mismatch
(such as Ge lattice mismatch about 4%, In 0.53 Ga 0.47 As lattice mismatch about
8%) will produce a large number of lattice defects in the semiconductor layer.

Tunneling FET

Compared with traditional MOSFET, the tunneling FET (TFET) [9, 10] has sharper
switching characteristics and more suitable for ultra-low power (ULP) circuits. The
operation of TFET is based on the band-to-band tunneling (BTBT) mechanism of
electrons (as also referred to as gate-induced-drain-leakage (GIDL) current). The
simplest device structure is a gate-controlled p-i-n diode (or gated pin diode). TFET
devices can be turned off or on by the gate voltage. The off-state current of TFET is
usually several orders of magnitude lower than that of traditional MOSFET. The
sub-Vt slope (SS) of TFET is smaller (or sharper) than that of traditional MOSFET
(60 mV/decade). In the process design of traditional MOSFET circuits, it is neces-
sary to reduce the gate-induced drain current (GIDL) to reduce the off-state current,
but in the TFET circuit, the source should enhance the GIDL inter-band tunnel
penetration current to enhance the device’s operating current. Therefore, TFET
devices can be optimized by selecting semiconductor materials with smaller
bandgap, such as InGaAs or GaAsSb, to generate higher BTBT current. Hetero-
structured TFETs (such as smaller bandgap materials for source and larger bandgap
materials for drain) can further optimize device characteristics by band engineering
(such as band arrangement of fracture gap and cross gap structures). Complementary
TFET technology is needed in logic circuits; where the design of n-TFET is clear, but
the design of p-TFET is difficult due to the influence of Fermi degeneracy, which
limits the p-TFET to reach a lower sub-Vt slope (<60 mV/decade). In short, narrow
bandgap materials can be used to implement low sub-Vt slope devices (such as
TFET) for ultra-low power circuits. In addition, III-V materials and 2D semicon-
ductor materials (such as WSe2 and MoS2) may also be used in TFET.

2D Material for Channel

Recent progresses in graphene since 2004 has triggered great attention to use
two-dimensional (2D) materials. However, graphene has zero bandgap and is not
suitable to be used as channel materials in MOSFET. Recently, single or multiple
layers of molybdenum disulfide (MoS2) or tungsten selenide (WSe2) [11] have been
demonstrated to have large enough bandgap, reasonable mobility, ultra-thin channel
(for device scaling capability), lower dielectric constant, and flexibility (for flexible
electrons); thus, these 2D materials are promising as channel materials in MOSFET.
Several features of these 2D materials are summarized as follows. (a) Although the
888 M.-H. Chi et al.

mobility of these 2D materials is only moderate (vs Si channel), the ultra-thin atomic
layer channel (up to atomic layer thickness < 1 nm beyond the limit of traditional Si
channel) can achieve smaller minimum gate length for maintaining good electro-
static control over the channel. (b) The lower dielectric constant (than Si) leads to
suppressed short channel effect, reduced gate capacitance (unit area), and reduced
on-current as well as trans-conductance. (c) 2D materials have a larger electron
effective mass that enables to reduce the direct tunneling current between the source
and drain. (d) The flexibility of these 2D materials is suitable for many new
applications in flexible electronics. Compared with most 2D materials, the mobility
of traditional flexible electronic device materials (e.g., organic or amorphous semi-
conductors, metal oxides, etc.) is even much lower.
In summary, the CMOS with 2D materials as channel is expected to exceed the
traditional Si-based channel toward scaled device and good performance. The
application of new 2D materials in flexible electronic devices is promising though
still many challenges existing.

Si Photonics ICs

Optical interconnection can effectively realize broadband, high speed, and low
power data communication, so the integration of Si optoelectronic devices [12]
and CMOS circuits together has great market demand. Optical elements that can
be integrated on Si wafers include optical waveguides, photodetectors, light-
emitting diodes (LEDs), Mach-Zehnder modulators (MZM), and lasers. Optical
receiver/transmitter IC includes light source, modulator (including control loop),
photodetector, and receiver/generator circuits. The fabrication of Si optoelec-
tronic devices must be based on CMOS technology with quality and accuracy for
mass production. The different requirements of various optical elements are
summarized below.

Waveguides

Optical signals are transmitted in low-loss waveguides. The splitting and routing of
optical signals must pass through waveguide band-pass filters, and the transmis-
sion of optical signals to optical fibers must be achieved through the coupling
between light and chips. Especially, submicron Si waveguides have a very sensi-
tive effect on the polarization of optical signals. Therefore, Si waveguides must
have accurate CD, layer thickness, and optical quality, e.g., the light signal is not
absorbed too much to avoid scattering on rough surface. Due to process variations,
the working wavelength must be adjusted or the circuit must be actively compen-
sated. So it is necessary to integrate the Si photonic devices and CMOS circuits on
a single chip (or hybrid 3D integration) for achieving high performance Si photo-
electronic ICs.
47 Compound Semiconductor Device and IC 889

Photodetectors, Modulators, and Lasers

Light signals can be converted into electrical signals through photodiodes. Carrier
density in Si waveguides can be modified by using embedded diodes (selective
epitaxy growth of Ge on Si substrates) or capacitors, which can generate phase or
amplitude modulation to couple electrical signals into optical carriers. Laser light
sources can be integrated on a single chip IC using III-V technology and then
bonding or off-chip coupling on CMOS IC chips. At present, wide bandgap GaN
has been widely used to fabricate blue LEDs.
The integration of Si photonic devices into standard CMOS/SOI is shown in
Fig. 47.2 [13]. Only two process modules need to be added: groove etching module
to form optical devices (such as waveguides, couplers, etc.) and selective Ge epitaxy
growth to integrate photodetectors on Si wafers. On this Si photon/CMOS technol-
ogy platform, various Si photoelectron structure modules can be formed; e.g.,
waveguide, optical I/O, phase/amplitude modulator, and photodetector. Optical I/O
(such as grating couplers) should have very small coupling loss in standard single-
mode fibers.
Optoelectronic devices can also be integrated on existing heterogeneous
integrated CMOS/SOI process platforms [14]. For example, Ge/SiGe, III-V
compounds can be integrated on CMOS/SOI wafers, as illustrated in Fig. 47.3.
SiGe with strained structure can enhance the dispersion effect of plasma and
reduce the effective mass of holes, so it can improve the efficiency of optical
modulator. Ge-based photonic devices (nanowire waveguides) have been dem-
onstrated in mid-infrared applications. In addition, photo-electronic devices such
as InGaAsP nanowires (including optical switches and photodetectors) can be
directly formed on high quality photonic insulating layer, as III-V on-isolator
(III-V-OI), by wafer bonding technology. At present, the process feasibility of
epitaxy growth of III-V compounds on Si wafers has been demonstrated.

Fig. 47.2 Si-photonics devices integrated with CMOS/SOI on a single chip [13]
890 M.-H. Chi et al.

Fig. 47.3 Si-photonics technology platform

Radio Frequency Integrated Circuits (RFICs)

Early radio frequency integrated circuits (RFICs) were mainly based on Si-based
discrete bipolar transistors connected with passive components such as diodes, induc-
tors, and capacitors and then integrated on the PCB to form RF hybrid ICs. Since the
1990s, with the advancement of IC technology, RFICs have realized the integration of
various transistor chips with passive components (or chips), e.g., diodes, inductors,
and capacitors, on a ceramic substrate by miniaturized packaging for significantly
reducing the size of the RF circuits and replacing the old hybrid circuits using discrete
devices [15]. Therefore, the RFICs have made great progresses with rapid develop-
ment for wireless communication technology. After entering twenty-first century, with
the further development of CMOS, RF GaAs, and RF GaN chip technology, RFICs
have gradually evolved toward the monolithic ICs (RF-MICs).
RF-SOI refers to the technology for forming RF devices on SOI substrate, where
SOI substrate refers to a thin Si layer on SiO2 over bulk Si substrate (see 6.2.4). It is
one of the mainstream choices for deep sub-micron low-voltage and low power
CMOS IC on SOI substrate [16]. The advantages of RF-SOI are: (1) High operating
frequency. The device’s ft./fmax can be increased to 3–5 times than the millimeter
wave technology. (2) It can realize IC stack structure while improving power and
energy efficiency ratio. (3) SOI substrates can reduce parasitic effects and enable RF
chips achieving higher quality factor, less power loss, and better noise figure.
Meanwhile, product’s insulation level and linearity have also been improved. (4)
RF-SOI can integrate power amplifier (PA) and control function circuits together on
a chip. (5) RF-SOI also can have back-gate bias capability for fine tuning RF circuits.
At present, RF-SOI is gradually replacing the compound technology in the field of
wireless communication, e.g., smartphones, Wi-Fi, etc.

Microwave Monolithic Integrated Circuits (MMIC)

Microwave monolithic integrated circuit (MMIC) is a type of circuits on the chip

based on IC manufacturing technology. MMIC integrated microwave transistors,
diodes, passive devices (including resistors, capacitors, inductors, power transmission
47 Compound Semiconductor Device and IC 891

lines, power divider/synthesizers, etc.), and interconnect metal on the same semicon-
ductor chip and realized ultra-miniaturization of microwave power amplifier (PA),
microwave low noise amplifier (LNA), mixer, multichannel power synthesis, and
microwave signal transmitting/receiving as well as multifunction circuits.
At present, active transistors commonly used in MMIC can be divided into
Si-based transistors and compound heterojunction transistors according to the
manufacturing materials. Among them, Si-based transistors mainly are referred to
Si bipolar junction transistor (BJT), Si complementary metal-oxide-semiconductor
(CMOS) field effect transistor, and Si laterally double diffused metal-oxide-semi-
conductor (LDMOS) field-effect transistor. Compound heterojunction transistors
mainly include germanium-silicon (SiGe) heterojunction bipolar transistor (HBT),
InP HBT, GaAs metal semiconductor field effect transistor (GaAs MESFET),
heterojunction field effect transistor (GaAs HFET), high electron mobility transistor
(GaAs HEMT), pseudomorphic high electron mobility transistor (GaAs PHEMT),
InP HEMT or pHEMT, GaN HEMT, and GaN PHEMT. In addition, graphene
MOSFET and other devices, which are at the initial stage of research and develop-
ment (R&D), have also been explored for the development of MMIC.

Si-MMIC

From the early 1980s to the mid-1980s, Avantek in the USA improved the cut-off
frequency of Si-BJT up to 10 GHz by equi-planar, self-aligned, submicron lines, and
shallow trench isolation techniques. Avantek took the lead in the development of
Si-MMIC with microwave broadband, serialization, and high performance by use of
directly cascading two BJT amplifiers and integrating the feedback resistor and bias
resistor on the same chip. The input and output impedance is 50 Ω, and there is a
need to add matching circuit. It adopted single power supply, which was easy to
operate. In the 1990s, Si-MMIC was widely used in microwave low-power and
low-noise applications with band below 4 GHz (Po < 1 W @ 1 GHz).

GaAs-MMIC

As the electron mobility of GaAs is 7 times higher than that of Si, its drift velocity is
much higher than that of Si, so the performance of GaAs devices is much superior to
that of Si devices in microwave and millimeter wave frequency band. GaAs material
has an important influence on the development of microwave semiconductor tech-
nology. GaAs MESFET is one of the most important semiconductor devices in
microwave field because of its low noise, high power, and wide bandwidth. In
1974, Plessey in the UK developed GaAs-MMIC amplifier. In 1986, TI released a
commercial GaAs power amplifier (MESFET MMIC-TGA8014), which adopted
two-stage MESFET cascade amplification and is mainly used in phased array radar
and other systems [17]. Since the 1990s, with the maturing of GaAs material and
device process technology, GaAs MMIC with multistage cascade amplification
892 M.-H. Chi et al.

achieved a substantial development with its working frequency reaching 3 mm band

range. The products including power amplifier (PA), low-noise amplifier (LNA),
mixer, transmitter/receiver (Tx/Rx), multi-functional chip circuits, etc. are maturing
and reliable. The output power of the GaAs power amplifier MMIC in the X band
(9–10 GHz) has reached 12 W, the gain has reached more than 25.5 dB, and the
power-added efficiency (PAE) is greater than 45% [18]. GaAs MMIC manufacturing
techniques include growth of multilayer GaAs epitaxial layers by molecular beam
epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) techniques,
isolation technology, deep sub-micron T-gate manufacturing technology, source and
drain Ohmic contact technique, gold metallization (metal electrodes and intercon-
nect), via hole on the back connect to ground, air bridge technology, etc. GaAs
MMIC also integrated resistors, capacitors, inductors, interconnects, and power
dividers/power generators on the same chip to match the impedance of I/O port to
50 Ω.

SiGe

In order to achieve higher working frequency and lower power consumption,

Si-based SiGe RF CMOS and BiCMOS process technologies have been widely
developed in the early twenty-first century. At present, the working frequency of
such devices can reach 60 GHz, but its output power is less than 100 mW, which
limits its applications.

GaN

GaN has higher critical breakdown electric field and higher carrier saturation drift
velocity. In 2015, products of C-band to W-band high power and high efficiency
broadband power amplifiers had been produced using GaN material by combining
MMIC and circuit topology techniques. Broadband robust low noise amplifier,
Ka-band high power GaN SPDT (single-pole double-throw) switch, X-band high
power GaN high/low pass phase shifter, W-band GaN VCO (voltage-controlled
oscillator), X-band front-end of transceiver, and X-band GaN multichip module
had been manufactured also. The monolithic hetero-IC on Si substrate, which
integrates GaN amplifier and its gate bias control circuits based Si-CMOS, had
been developed [19]. The manufacturing process of GaN MMIC is compatible and
similar to that of GaAs.

InP

The electron mobility and carrier saturation velocity of InP are extra high, which can
improve the working frequency of MMIC up to THz range. Due to InP material
technology, device technology and circuit topology technology are gradually
47 Compound Semiconductor Device and IC 893

maturing. In 2015, DARPA employed InP HEMT technology with 25 nm gate

length, 10-stage HEMT (2 gate fingers and total gate width of 8 um) amplifier, and
a common source design, realizing a milestone of terahertz monolithic circuit
(TMIC) for the first time [20]. The amplification at 1 THz (1000 GHz) with 9 dB
measured gain at 1 THz has been demonstrated as illustrated in Figs. 47.4 and 47.5.

Graphene

In 2013, H. Madan et al. in the USA fabricated RF low-noise amplifier on semi-

insulating SiC substrate by use of the high mobility and high velocity characteristics
of graphene. It achieved a minimum intrinsic noise figure of 0.26 db@1 GHz. In the
same year, E. Guerero in Italy also fabricated a graphene ring oscillator (RO) with
the maximum oscillation frequency of 1.2 GHz, which contributed to the develop-
ment of graphene ICs. In 2014, IBM’s S. J. Han et al. made a receiver IC based on
graphene, which can realize signal amplification, filtering, and down-conversion
functions. It is compatible with the Si-based CMOS process and can be used for the
receiver in wireless communication and maintain the 4.3 GHz carrier signal [21].

Fig. 47.4 Microscope image

of TMIC [4]

Fig. 47.5 SEM image of TMIC [20]

894 M.-H. Chi et al.

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interconnect systems, in ASP-DAC 2013, Yokohama, 22–25 January 2013, (IEEE, Yokohama,
2013)
14. M. Takenaka, Y. Kim, J. Han, et al., CMOS photonics technologies based on heterogeneous
integration of SiGe/Ge and III-V on Si, in IEDM 2015, Washington, DC, 7–9 December 2015,
(IEEE, Washington, DC, 2015)
15. RFIC. http://baike.baidu.com/item/RFIC. 08 June 2017
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17. Z. Liu, S. Li, Semicond. Technol. 6(3), 8–23 (1992)
18. W. Feng, S. Ni, Semicond. Technol. 5, 341–346 (2016)
19. Zhengping Zhao, Semicond. Technol. 1, 1–7 (2015)
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21. Z. Wang, S. Wang, Micronanoelectron. Technol. 52(10), 613–619 (2015)
Micro Electro-Mechanical Systems (MEMS)
48
Yunqian He, Aisheng Yu, Xuanjie Liu, and Yuelin Wang

Contents
Wet Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Dry Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
Sacrificial Layer Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Bonding Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
Electrostatic Bonding Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
Thermal Bonding Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Cavity-Silicon on Insulator (Cavity-SOI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
MEMS and CMOS Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Pre-CMOS/MEMS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Intra-CMOS/MEMS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
Post-CMOS/MEMS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910

Abstract
Typical process technologies for MEMS device manufacturing include wet etch-
ing, dry etching, sacrificial layer technology, bonding, and SOI with cavity. Wet
and dry etching processes are also common in standard CMOS processes, but
they are uniquely different in MEMS technology. The wet etching in MEMS
process is mainly different in the etching depth, anisotropic wet etching skillfully
Y. He
Huawei Technologies Co., Ltd, Shanghai, China
A. Yu
SAIC (Shanghai Automotive Industry Corporation) Motor R&D Innovation Headquarters,
Shanghai, China
X. Liu
Semiconductor Manufacturing Electronics (ShaoXing) Corporation, Shaoxing, China
Y. Wang (*)
Shanghai Institute of Microsystem Information of Technology, Chinese Academy of Sciences,
Shanghai, China
e-mail: ylwang@mail.sim.ac.cn

© Publishing House of Electronics Industry 2024 895

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_48
896 Y. He et al.

for achieving accurate control of patterns, or forming suspended structures. For

CMOS, the wet etching is often used to remove thin films, such as hard mask
materials (e.g., Si-oxide, Si-nitride, etc.). CMOS process pays less attention to
anisotropic wet etching technique but more attention on the selectivity of etchants
to different materials. Compared with CMOS process, the largest difference in the
dry etching for MEMS technology is the etching depth (1–100 um scale) and the
etching depth-width ratio. For CMOS process, dry etching is often used for
patterning with smaller etching thickness (nm scale) and etching depth-width
ratio, but the requirement of morphology, accuracy, uniformity, and selectivity are
very high.

Keywords
MEMS · Wet etching · Dry etching · Sacrificial layer · Bonding · Cavity-SOI ·
Integration

Typical technologies for MEMS device manufacturing include wet etching, dry
etching, sacrificial layer deposition and removal, bonding technology, and SOI
with cavity. Wet and dry etching techniques are also common in standard CMOS
process, but they are uniquely different in MEMS technology mainly different in the
etching depth, anisotropic wet etching for achieving accurate control of patterns, or
forming suspended structures. For CMOS, the wet etching is often used to remove
thin films, such as hard mask materials (e.g., Si-oxide, Si-nitride, etc.). CMOS
process pays less attention to anisotropic wet etching technique but more attention
on the selectivity of etchants to different materials. Compared with CMOS process,
the largest differences in the dry etching for MEMS technology is the etching depth
(1–100 um range) and the etching depth-width ratio. For CMOS process, dry etching
is often used to etch for mask patterning with smaller etching thickness (nm range)
and etching depth-width ratio, but the requirements of morphology, accuracy, uni-
formity, and selectivity are very high.

Wet Etching

Although IC processing is dominated by dry etching, the majority of etch processing

for MEMS fabrication is wet chemical etching. Today, due to different etch rate in
crystalline directions, the wet etching can be generally categorized as isotropic wet
etching and anisotropic wet etching, as illustrated in Fig. 48.1.

1. Isotropic wet etching: The most widely used isotropic etchant is a mixture of
hydrofluoric acid (HF), nitric acid (HNO3), and acetic acid (CH3COOH), also
called HNA etchant. The etch rate of Si and selectivity to mask material is
dependent on the composition of each component in the etchant and processing
48 Micro Electro-Mechanical Systems (MEMS) 897

Fig. 48.1 Isotropic wet

etching and anisotropic wet
etching

Table 48.1 The wet etching characteristics of KOH and TMAH

Parameters Value (KOH) Value (TMAH)
Etch rate of <100> orientation 5 μm/h 40  C 20 μm/h 80  C
10 μm/h 50  C
Selectivity of <111>/<110> 100:1 50:1
Etch rate of Si3N4 (nm/min) <1 <0.1
Etch rate of SiO2 (nm/min) ≈10 <0.1
Surface Very good Good
Toxicity No Yes
Metal ion Yes No

temperature. The isotropic wet etching is used less in MEMS practically due to its
lateral etching of the material.
2. An-isotropic wet etching: It has been widely used in various MEMS products,
such as pressure sensors, accelerometers, acoustic sensors, etc. In practice, KOH
and tetramethylammonium hydroxide (TMAH) are widely used as anisotropic Si
etchants in MEMS manufacturing with their characteristics shown in Table 48.1.
Anisotropic etching has different etching rates in different crystal directions [1].
Various structures have been fabricated on Si substrates, i.e., grooves (cavities of
pressure sensors, etc.), pyramid structures (probes of atomic force microscope,
etc.), and suspension structures (beams of accelerometer cantilever, etc.). In
anisotropic wet etching, as the etching time increases, the crystal planes at fast
etch rate will disappear and leave only the crystal plane at slowest etch rate; at this
time, the shape of the etched cavity hardly changes but only slowly increases in
size, and the resulted cavity is called self-limiting structure. Figure 48.2 illustrates
a way to predict the self-limiting wet etching results using arbitrary mask patterns:
(a) Find the four maximum points of the mask pattern in four directions. (b) Make
four straight lines parallel to the <110> crystal direction at four points. (c) The
area enclosed by four straight lines is the topography of the self-limiting structure.
(d) The etching depth is determined by the thickness of the wafer, the self-stop
surface, and the window size. As noticed, some areas covered by masks can also
898 Y. He et al.

Fig. 48.2 Wet etching windows of the self-limiting structure. The gray areas represent masks, and
dashed outlines represent the self-limiting structure topography

Fig. 48.3 Fabrication process of the cantilever accelerometer

Fig. 48.4 Wet etching of cantilever beam

be etched. In MEMS manufacturing, this way is widely used to form cantilever

beam structure.
3. Cantilever formation: Fig. 48.3 shows the fabrication process of the cantilever
accelerometer using anisotropic wet etching. (a) Firstly, depositing films (Si3N4,
SiO2, or SiO2/Si3N4) on the Si substrate. (b) Then, deposit and pattern piezoelec-
tric material. (c) Next, deposit and pattern metal film for electrodes. (d) Then
patterning wet etching windows. (e) Anisotropic wet etching of Si substrate for
releasing movable cantilever beams. The wet etching of the cantilever beam is
illustrated in Fig. 48.4.
4. Convex corner compensation: In some micromachining, etching of convex corner
is to be avoided. For example, when a rectangular is required, the convex corner
48 Micro Electro-Mechanical Systems (MEMS) 899

Fig. 48.5 Convex corner compensation for ideal structures. (a) 20 min. (b) 45 min. (c) 90 min

etching will cause severe distortion of the four corners of the rectangle. Some
methods of convex corner compensation have been proposed, and the literature
[2] is a good summary. The common convex corner compensation is mainly to
increase the pattern at the corner of the mask for the protection of the convex
corner. The size and shape of the compensation pattern are adjusted by the etching
depth and the type of etchants for achieving ideal structures. Figure 48.5 shows
the convex angle compensation of a strip pattern at corner with different wet
etching times [3]. By controlling the etching time, a perfect corner can be
obtained when the compensation strip is just removed.

Dry Etching

In the MEMS manufacturing, commonly used dry etching includes reactive ion
etching (RIE), deep reactive ion etching (DRIE), and XeF2 isotropic etching. Among
them, the RIE is also commonly used in IC manufacturing. DRIE, also known as
inductively coupled plasma etching (ICP), is a highly anisotropic dry etching
process. DRIE uses a Bosch process that alternates between etching and passivation
to solve the problem of not being able to fabricate high-aspect-ratio (HAR) structures
or steep sidewalls in RIE [4]. The DRIE uses two RF sources, where the coil RF
source (coil-RF) is used for plasma generation and the plate RF source (plate-RF) for
bias generation. The separate RF sources can adjust the RF power and plasma
concentration in the RIE etching, respectively. DRIE technology has greatly
advanced the development of MEMS. Currently, the main DRIE equipment sup-
pliers are STS in the UK and Alcatel in France. The cryogenic process and the Bosch
process are the two main ways to achieve DRIE. The Bosch process is a patent of the
German company Robert Bosch GmbH [4]. Figure 48.6 shows the DRIE process.
Problems with the DRIE process include RIE lag, charging, and scalloping
effects. The RIE lag effect is related to the size of the window as illustrated in
Fig. 48.7a, b; it can be divided into positive effect (i.e., faster etch rate at larger
window) and inverse effect (faster etch rate for smaller window). The charging effect
900 Y. He et al.

Fig. 48.6 DRIE process

Fig. 48.7 The effects of DRIE

causes lateral etching at the bottom of the deep cavity as shown in Fig. 48.7c. The
scalloping effect is shown in Fig. 48.7d, and it can be reduced by adjusting the
etching time and the passivation time in equal proportions.
The fabrication process of the resonator by the DRIE process is shown in
Fig. 48.8. The main steps include the following: (a) oxidation form a wet etched
48 Micro Electro-Mechanical Systems (MEMS) 901

Fig. 48.8 The fabrication process of the resonator by DRIE

mask layer; (b) wet etching to form a resonant cavity; (c) bonding to form the
resonant material on the resonant cavity; (d) thinning the resonator block and
forming electrodes; and (e) releasing the movable resonant block by DRIE. DRIE
is also used in manufacturing high-density DRAM memories; the required channel
depth is usually 10-20 μm. In addition, another new application area of DRIE is the
through-silicon via (TSV) technology; this is a new scheme to implementing three-
dimensional (3D) stacking and interconnection of IC chips [5].
XeF2 etching is an isotropic etching technique. At room temperature, when the
pressure is less than 100mTorr, XeF2 changes from a solid to a gaseous state and
reacts with Si at room temperature, and the etching rate can reach 20-50 μm per
cycle. At the same time, XeF2 has a good selection ratio of mask materials, such as
Si-oxide, Si-nitride, Al, and photoresist. However, the XeF2 etching depth is not easy
to control, and the etching by-products contain HF gas and require strict exhaust gas
treatment.

Sacrificial Layer Technology

Sacrificial layer technology has been rapidly developed since its development in the
1980s at the University of California, Berkeley [6]. Sacrificial layer technology for
MEMS technology is a unique technology different from standard IC technology.
The technique utilizes a thin film material that can be etched or removed as an
intermediate layer between the structural layer and the substrate. After the structural
layer is patterned, the intermediate layer material (referred to as sacrificial layer) is
removed by wet etching or dry etching to form a movable or suspended microstruc-
ture. Such movable or suspended microstructures are indispensable components as
actuators or sensors in MEMS devices (e.g., micro pressure sensors, gyroscopes,
accelerometers, and micro-motors) [7–9]. Therefore, the sacrificial layer technology
will play a critical role in the innovation and manufacture of new MEMS devices in
the future. Sacrificial layer materials include poly-Si, resist, metal film, and
902 Y. He et al.

Fig. 48.9 Microstructures by the sacrificial layer technology

polyimide. The sacrificial layer process mainly includes five steps: (1) deposition of
the sacrificial layer material on the substrate; (2) etching of the sacrificial layer
material, making support points for the structural layer; (3) deposition of the
structural layer material on the sacrificial layer; (4) patterning of the structural
layer material; and (5) dry etching or wet etching of the sacrificial layer material,
releasing the patterned structural layer to form movable microstructures or cavities.
Figure 48.9 shows some microstructures by the sacrificial layer technology, and
Fig. 48.10 shows the fabrication process of the polysilicon micro-bridge.
Sacrificial layer technology often uses wet etching to release the patterned
structural layer due to the fast etch rate with good selectivity and simple process
and equipment. However, after the wet etching, it is necessary to evaporate the
solution and dry the wafer; therefore the microstructure is easily deformed and
adhered during this process. When the liquid is evaporated, the liquid removal
between the microstructure and the substrate is slower, and a large surface tension
occurs at the interface between the liquid and the air; the vertical component may
pull the microstructure closer to (or even touching) the substrate and result in
deformation of the microstructure or even adhering to the substrate as shown in
Fig. 48.11. For structural failures caused by surface tension, effective solutions have
been developed, such as supercritical drying technology and new dry etching
techniques.

Bonding Technology

Bonding technology is one of the conventional techniques in MEMS technology. It

refers to a process technology that closely combines Si wafers with Si wafers, glass,
and metal materials through physical mechanisms or chemical reaction. In MEMS
manufacturing, in order to realize complex processes for suspension microstructures
and device packaging, bonding technology has developed rapidly including electro-
static bonding, thermal bonding, and Au-Si bonding technologies. They are fully
compatible with Si technology for planar and bulk technologies. Among them,
48 Micro Electro-Mechanical Systems (MEMS) 903

Fig. 48.10 The fabrication process of the polysilicon micro-bridge

electrostatic bonding and thermal bonding technology are commonly used in MEMS
manufacturing.

Electrostatic Bonding Technology

Electrostatic bonding technology was first proposed by Wallis and Pomerantz in

1969 [10]. This technique takes full advantages of the effect of impurities in the
bonding material shifting toward the electrode under the electrostatic field, forming a
strong electric field at the bonding interface to achieve a tight bonding between the
materials. Due to the strong electric field, this technology, also known as field-
assisted bonding or anodic bonding, is widely used in the bonding of glass to
semiconductors, metals, and alloys. Figure 48.12 shows the principle and process
of the electrostatic bonding between Si and glass [11]. Firstly, the Si wafer is placed
904 Y. He et al.

Fig. 48.11 Deformation and

adhesion of the microstructure

Fig. 48.12 The principle and process of the electrostatic bonding between silicon and glass

on an anode heating plate, and the glass is aligned with the Si wafer and connected to
the cathode. The heating plate is then heated to 300–500  C, the intrinsic carriers in
the Si wafer move violently, the resistivity of the Si wafer drops to the metal
resistivity, and the surface potential is equal to the anode. Then the switch is closed
to apply a voltage of 500–1000 V. The impurity ions in the glass are rapidly deflected
toward the cathode under a strong electric field, and the immobile negative charge
left at the interface forms a depletion layer, forming an electrostatic field with the
anode, generating electrostatic attraction. The peripheral circuit has a current output.
Finally, as the ions are constantly shifting and the depletion layer is continuously
widened, the electric field at the interface is continuously enhanced. When the
peripheral current output is zero, the bonding is completed. Electrostatic bonding
technology is widely used in sensor fabrication and packaging, SOI material prep-
aration, and bonding of glass to metals or alloys due to its low bonding temperature,
simple bonding control, and excellent bonding quality.
48 Micro Electro-Mechanical Systems (MEMS) 905

Fig. 48.13 The principle and process of the thermal bonding between silicon and silicon

Thermal Bonding Technology

It was first proposed by Lasky [12]. In high temperature environments, the technique
relies on the bridging of chemical groups on the surface of the material to form
strong covalent bonds between the atoms at the interface of the bonding material to
achieve tight bonding. Thermal bonding technology can be bonded only by high
temperature, so it is also called direct bonding technology, and has been widely used
in bonding between Si and Si and Si and Si-oxide. Figure 48.13 shows the principle
and process of the thermal bonding between Si and Si [13, 14]. The -OH group is
first modified on the surface of the wafer by pretreatment. The two stacked Si wafers
are then placed in a high temperature chamber. Finally, the bonding is achieved by
heating to above 1000  C as a key stage. When the temperature is heated from room
temperature to 400  C, the interface changes from H bonding to Si-O bonding. When
the temperature is from 400  C to 800  C, water molecules diffuse into the oxide
layer, and the original group destroys the bridged oxygen to form non-bridged
oxygen. When the temperature is heated to above 800  C, the water molecules at
the bonding interface rapidly diffuse, and the gas pressure is lowered to form a
vacuum. Under the combined action of atmospheric pressure, high-temperature Si
deformation and interfacial oxide flow, micro-gap and voids at the bonding interface
are eliminated. When the temperature reaches 1000  C, a series of reactions occur at
the bonding interface and forming Si-Si covalent bonding tightly. The thermal
bonding technology is widely used in power electronic device, SOI material, sensor
and microstructure, Si and other material bonding, Ti-Ti and Ti-SiO2 bonding, etc.
due to its simpler process control and excellent bonding quality.

Cavity-Silicon on Insulator (Cavity-SOI)

Conventional Si-on-insulators (SOI) substrate introduce an insulating layer into

bulk Si substrate by means of separation-by-implanted-oxygen (SIMOX) at high-
temperature and smart-cutting to achieve electrical isolation between the top
906 Y. He et al.

surface Si layer and the substrate Si. If Si trenches are etched and formed on the Si
wafer during the fabrication of the SOI wafer, and then bonded and polished to
thin surface Si layer, a SOI wafer with cavities can be fabricated and is referred to
as cavity-SOI (cavity-SOI). The difference between the conventional SOI and the
cavity-SOI substrate is shown in Fig. 48.14. For the MEMS industry, the advan-
tages of using the cavity-SOI substrate are (a) eliminating the common stress
problems in poly-Si, (b) achieving high precision resonant frequency in MEMS
resonators by the high precision film thickness, (c) excellent smoothness of the
surface and side walls, (d) thinner structures, (e) higher thermal conducting for
MEMS components, and (f) shorter manufacturing time and lower cost.
Compared to traditional SOI substrates, cavity-SOI substrates are more
suitable for processing vertical or horizontal moving microstructures [15, 16]
(e.g., capacitive inertial sensors, pressure sensors, microphones, RF devices,
microfluidic devices, etc.) because of the cavity can be easily released by dry
etching. The fabrication process of MEMS resonator on cavity-SOI substrate is
shown in Fig. 48.15a. The process flow includes the following [17]: (a) thinning
the top Si layer thickness (by CMP, wet etching, or dry etching); (b) electrode
patterning and formation; and (c) patterning structure, then releasing the movable
structure through DRIE. Figure 48.15b shows the SEM image of the MEMS
resonator.

Fig. 48.14 Difference of the SOI and cavity-SOI substrate

Fig. 48.15 MEMS resonator on the cavity-SOI substrate

48 Micro Electro-Mechanical Systems (MEMS) 907

MEMS and CMOS Integration

The manufacturing technology of MEMS [18] is mainly based on the standard

CMOS technology with only a few steps dedicated to the MEMS structure. The
integration of MEMS device with CMOS circuits on the same chip can add enhanced
functions from mature logic IPs for signal processing and referred to as micro-
systems or MEMS IC. The CMOS area may include MCU (micro-controller-unit),
digital signal processor (DSP), I/O interface IPs, memory, etc.; and the MEMS
device may include pressure sensors, chemical and biochemical sensors, micro-
phone, accelerators, gyroscope, magnetic sensors, acoustics, RF switches, etc. [19]
Since 2000, bio-micro-electromechanical system (Bio-MEMS) has attracted much
attention. Bio-MEMS is a biochip integrated with CMOS for bioinformatics identi-
fication and analysis, medical diagnosis, tissue cell engineering, medical injection,
surgery assistance, etc. The integration of MEMS and CMOS can be achieved by
adding MEMS steps before (pre-CMOS/MEMS), during (intra-CMOS/MEMS), or
after (post-CMOS/MEMS) CMOS process [19, 20].

Pre-CMOS/MEMS Technology

Pre-CMOS/MEMS means that part or all of the MEMS steps are completed before
the CMOS. The Si wafer with MEMS structure already formed can be considered as
initial material for CMOS process. Figure 48.16 illustrates the pre-CMOS/MEMS
process with MEMS module as developed by Sandia National Laboratories [21].
Firstly, cavity for MEMS is formed by anisotropic etching on Si substrates, and then
multilayers of poly-Si are deposited in cavity and processed to form micro-
structures. After the formation of the MEMS, SiO2 and other fillers are deposited
in the cavity and perform CMP planarizing the surface. Then the wafer is sent to the
standard CMOS line as initial material. Then, after CMOS device is formed, MEMS
and CMOS are electrically connected by metal interconnection. Finally, open
MEMS area (by masking steps) and perform dry etching or wet chemical etching
to release the microstructures to complete the pre-CMOS/MEMS integration. This
scheme can minimize potential damages of CMOS circuits and sensitive MEMS
structure.

Intra-CMOS/MEMS Technology

In standard CMOS flow, the formation of MEMS structure can also be inserted
before metal interconnect. This scheme is mostly used to form high temperature
poly-Si with annealing as micro-structures with compatibility [19] to CMOS
process. Figure 48.17 illustrates that a thicker layer of field oxide is formed
on CMOS substrate as sacrificial layer, then doped or un-doped polysilicon
 908

Fig. 48.16 Illustration of pre-CMOS/MEMS technology [21]

Y. He et al.
48 Micro Electro-Mechanical Systems (MEMS) 909

Fig. 48.17 Illustration of intra-CMOS/MEMS technology

layer is deposited and annealed as micro-structural layer; then, after the micro-
structure pattern is formed, the sacrificial layer (field oxide) is removed by dry or
wet etching to release the micro-structures. Then return to the CMOS process,
deposit Si-oxide on the surface, and continue to form contact, via, and metal
interconnects.

Post-CMOS/MEMS Technology

Post-CMOS/MEMS integration is to complete standard CMOS process first, and

then add MEMS process in a dedicated MEMS fab. The post-CMOS/MEMS
integration scheme has the lowest cost than the above two schemes and currently
the most widely used. The process temperature of MEMS steps shall not exceed
450  C and the final micro-structure releasing through dry or wet etching [19]. Post-
CMOS/MEMS technology can be further divided into three cases based on differ-
ence of process. (a) Whole structure of MEMS formed on the CMOS substrate: As
illustrated in Figs. 48.18 and 48.19, the gyroscope with low temperature poly-SiGe
as the structure layer is integrated on the standard 0.35 μm CMOS platform [22].
(b) Need to add layers after CMOS: The post-processing temperature must be below
450  C. For example, the integrated accelerometer of MEMS needs to add Si
structure on the metal layer by low temperature fusion bonding, then form the
structure layer of MEMS by deep reactive ion etching (DRIE), and connect the
MEMS and CMOS by W-plug. (c) CMOS and MEMS are processed separately and
perform wafer-level bonding together, e.g., eutectic bonding (e.g., CMOS and
MEMS integrated accelerometer gyroscope). This method has advantages of good
process compatibility, more freedom for structural material of the MEMS, and
minimized chip area.
910 Y. He et al.

Fig. 48.18 Gyroscope structure with low-temperature poly-SiGe integrated at 0.35 um CMOS
platform [5]

Fig. 48.19 Illustration of post-CMOS/MEMS of gyroscope (with low-temp poly-SiGe) integrated

at CMOS platform

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Unit Processes
49
Hanming Wu, Hong Xiao, Weihai Bu, Shan Yu, and Poren Tang

Contents
Photolithography (Lithography) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
Phase-Shift Mask (PSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
Immersion Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
Extreme UV (EUV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
Computational Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
Physical Simulation of Photolithography Imaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
Optical Proximity Correction (OPC) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
The Source-Mask Optimization (SMO) Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Oxidation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Diffusion Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
Plasma Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
Thermal Annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
Physical Vapor Deposition and Sputtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
Chemical Vapor Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Atom Layer Deposition (ALD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
Chemical Mechanical Polishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
Epitaxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Solid Phase Epitaxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
Gas Phase Epitaxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

H. Wu (*)
School of Micro-nanoelectronics, Zhejiang University, Hanzhou, China
e-mail: hanmingwu@zju.edu.cn
H. Xiao
KLA-Tencor, Milpitas, CA, USA
W. Bu
Semiconductor Technology Innovation Center (Beijing) Corporation, Beijing, China
S. Yu
China Semiconductor Industry Association, Beijing, China
P. Tang
Semiconductor Manufacturing International Corp, Shanghai, China

© Publishing House of Electronics Industry 2024 913

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_49
914 H. Wu et al.

Dry Etching and Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

Wet Etching and Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936

Abstract
A complete Si-based CMOS integrated circuit process flow usually includes
hundreds to thousands of basic steps. These basic process steps are referred to
as “unit process” steps as they can be executed at a single tool (e.g., furnace,
chamber, equipment, lithography scanner, etc.). In manufacturing, several basic
unit process steps can be grouped as a “module process” loop for a well-defined
function (e.g., STI module, gate stack, lithography align/exposure/develop/
implant/PR-removal, contact formation, metal/via formation by dual-damascene,
etc.). Similarly, these modules can be further grouped into frontend-of-line
(FEOL), middle-of-line (MOL), and back-end-of-line (BEOL), to form a com-
plete CMOS integration process flow.

Keywords
Lithography · Oxidation · Diffusion · Implantation · Annealing · Film
deposition · CMP · Epitaxy · Etch

A complete Si-based CMOS IC process flow usually includes hundreds to thousands

of basic steps. These basic process steps are referred to as “unit process” as they can
be executed at a single tool (e.g., furnace, chamber, equipment, scanner, etc.). In
manufacturing, several basic unit process steps can be grouped as a “module
process” loop for a well-defined function (e.g., STI module, gate stack, lithography
align/exposure/develop, implant/PR-removal, contact formation, metal/via forma-
tion by dual-damascene, etc.). Similarly, these modules can be further grouped into
process sections of frontend-of-line (FEOL), middle-of-line (MOL), and backend-
of-line (BEOL) to form a complete CMOS integration flow.

Photolithography (Lithography)

The conventional lithography is relative to the advanced lithography which is still

applied in manufacturing. Typically, lithography of 193 nm ArF is considered as
advanced lithography (see Table 49.1) as it can support technology from 0.13 μm to
7 nm nodes with immersion and self-align multi-patterning techniques. The EUV
lithography is matured in 2019 and implemented in IC manufacturing at 7 nm node
and beyond.
In order to transfer the designed layout pattern on mask to Si wafer, the first step is
photoresist (PR) exposure and followed by etching process in order to transfer the
pattern onto PR first and then to Si wafer. Because the PR is not sensitive to yellow
light wavelength, most lithography areas in fab are in the yellow light; thus it is often
49 Unit Processes 915

Table 49.1 Lithography and technology nodes

Light band and source Light wavelength Technology nodes
UV (mercury) g-line 436 nm
0.5 μm
i-line 365 nm 0.35 ~ 0.25 μm
D UV KrF 248 nm 0.25 ~ 0.13 μm
ArF 193 nm 0.13 μm ~ 7 nm
Immersion 193 nm
F2 157 nm Not commercialized
E UV (plasma) Extreme-UV (soft X) 13.5 nm 7 nm, 5 nm and below

referred to as yellow light area. Lithography technology was firstly used in the
printing industry, and it was the main technology in the early manufacturing of
printed circuit board (PCB). Since the 1950s, lithography has become a mainstream
technology in IC manufacturing for layout pattern transfer to Si wafer. The key
parameters for lithography include resolution, sensitivity, alignment, and defects.
The most critical material in lithography is photoresist (PR) material; and PR can be
designed and optimized for various UV light wavelengths, e.g., the g/i lines, 248 nm
KrF, and 193 nm ArF photoresists. For example, the i-line PR commonly has
diazonaphthoquinone (DNQ) linear phenolic resin material, which is not suitable
for 193 nm lithography. PR can be categorized into positive and negative. The
negative PR results in the exposed area hardened and remaining on the wafer
surface; the unexposed PR dissolvable by the developer. The positive PR is just
the opposite to the negative PR, i.e., the exposed area dissolvable by the developer
and the unexposed area PR hardened and remaining on the wafer surface. Most
advanced technology nodes utilize positive PR due to better resolution in nano-
lithography process. At 16/14 nm nodes and beyond, positive PR with negative
developer solution is used for contact and metal/via processes, where the unexposed
PR is removed by negative developer and the pattern contrast is enhanced for small
trench patterns.
Typical lithography process includes eight steps: wafer clean, PR coating, soft-
bake, alignment-and-exposure, post-exposure-bake (PEB), development, hard-bake,
and pattern inspection [1, 2]. (1) Wafer clean: It is mainly wet cleaning and drying.
Any contamination from previous processes would weaken the adhesion between
the wafer and PR. Therefore, a thorough cleaning is needed for good adhesion. (2)
PR coating: It is realized by rotating Si wafer technique. Different PR requires
different coating parameters, including rotation speed, thickness, and temperature.
(3) Soft-bake: It is sometimes called pre-exposure bake or pre-bake mainly for more
uniform thickness, better PR adhesion and integrity in the following etch or implant
steps. (4) Alignment and exposure: This is the most critical step in lithography. The
mask (reticle) needs to be precisely aligned with respect to prior alignment mark on
wafer, and then the wafer is exposed on a small area (i.e., field) step-by-step to a
designed light source. The exposed area can activate the light-sensitive component
in PR and transfer layout pattern from mask to PR. This equipment is called stepper,
which is often the most expensive tool in Fab with its capability often representing
916 H. Wu et al.

the technology capability of the Fab. (5) Post-exposure-bake (PEB): This is a short
bake after the exposure. The purpose of the PEB for ArF and i-lines is different. For
ArF, the PEB is necessary for removing the effective component and achieving
dissolvable PR by developer. For i-line, the PEB is mainly for improving adhesion
and reducing the adverse effects of standing-wave on PR edge profile. (6) Develop-
ment: This step is to dissolve the PR portion by developer, e.g. exposed PR (for
positive PR). It can remove the unwanted PR and transfer the layout pattern on mask
to PR on wafer. The key process parameters include developer temperature and time,
solution amount and concentration, and clean (rinse). By adjusting the relevant
parameters in developing process, the difference of dissolution rate between exposed
and unexposed PR can be maximized for required developing effect. (7) Hard-bake:
By an appropriate heating, the process is to vaporize the residues (water and
developer solution, etc.) left from previous step for improving the adhesion and
etch resistance. The optimized heating temperature and time depends on PR char-
acteristics and optimized for avoiding PR pattern distortion and enhancing PR
strength. (8) After-development-inspection (ADI): Defects created during prior
steps are to be detected in-line in this step. By using pattern recognition technique
for scan inspection, the scanned image is compared with defect-less pattern or layout
database, the abnormal differences are considered as defects. If the defects number is
higher than upper limits, the wafer should be re-worked or discarded. Most process
steps in IC manufacturing are not reversible (re-workable), only the lithography is
one of few steps allowing rework.
As the CD scaling down continuously, the short light wavelength for lithography
is preferred. There are two light sources that are widely used in lithography tools,
i.e., mercury lamp and excimer lasers. The light source must be stable, reliable,
adjustable and short wavelength, high strength, as well as long life. In the advanced
technology nodes, only single light wavelength can achieve the resolution target in
manufacturing [3]. Currently, the ArF lithography is the mainstream for critical
layers in advanced CMOS technology nodes.

Phase-Shift Mask (PSM)

To improve resolution of the photolithography (or briefly lithography, or litho),

several resolution enhancement techniques (RET) have been developed so that the
applications of optical lithography can be extended to the most advanced IC
manufacturing. Phase-shift mask (PSM) can effectively reduce system constant k
and improve lithography resolution [1]. It is not very difficult to transfer a tiny,
isolated pattern from a mask to PR on a wafer; it is very challenging to transfer
density patterns with tiny pitch on the mask to the PR on the wafer. This is related to
the diffraction and interference of the diffracted light leading to increased light
intensity and poorer contrast of neighboring patterns to be resolved as shown in
Fig. 49.1a. To solve the problem, PSM is introduced. The PSM has a phase-shifter at
every other opening (clear, transparent area) on the mask, where destructive
49 Unit Processes 917

Fig. 49.1 Working principle for lithography using conventional mask and phase-shift mask

interference by the opposite phase shift can improve the contrast of the image as
shown in Fig. 49.1b.
PSM can enhance the contrast of the printed patterns in lithography process and
improve resolution by 40% to 100% from the traditional binary mask. Several types
of PSM have been developed; all of them rely on the destructive interference to
enhance the image contrast of the pattern and the gap between the two neighboring
patterns. There are alternated PSM (Alt-PSM) and attenuated PSM (Att-PSM),
combo PSM, edge-enhancement PSM, and etched quartz PSM. Alt-PSM and etched
quartz PSM can improve resolution better than other types and enable the
sub-wavelength lithography possible [4]. However, these two PSMs are more
expensive to fabricate due to complex process in mask-making. Instead, the half-
tone mask PSM and opaque-MoSi-on-glass (OMOG) mask are popular in IC
manufacturing. OMOG has lower mask error enhancement factor (MEEF) and can
improve lithography resolution and process yield.

Immersion Lithography

Immersion lithography is an improvement of the 193 nm lithography, thus it is also

commonly referred to as 193 nm or DUV immersion (or wet) lithography. The key
lithography parameter is resolution, which can be expressed as R ¼ k1λ/(n*NA).
From the expression, the resolution value (R) is proportional to system constant (k1)
and wavelength (λ) and reversely proportional to numerical aperture (NA) and
refractive index (n) of the material between the objective lens and wafer. Increase
n can improve resolution, thus by replace air between the objective lens and wafer
918 H. Wu et al.

with high-refractive index materials (e.g., oil and de-ionized (DI) water), we can
improve lithography resolution.
In the early 2000s, logic IC device reaches 65 nm technology node, which is
equivalent to the pattern density with half-pitch of 65 nm. A 157 nm from F2-laser
was actively expected to replace 193 nm from ArF excimer laser to become the next-
generation lithography wavelength. However, due to many technical difficulties in
CaF2-based optical lens, photomask, pellicle, anti-corrosion coating, and contami-
nation control issues, 157 nm could not reach its maturity for IC manufacturing
compared with the lower cost 193 nm immersion lithography. In 2002, study of
193 nm immersion lithography found that if high-purity DI wafer (n ¼ 1.44 at
193 nm) is used to replace air (n ¼ 1) between the objective lens and wafer, the
resolution can be improved to satisfy the requirement of 45 nm node lithography.
Semiconductor manufacturers started to introduce immersion lithography into high-
volume manufacturing (HVM) in 45 nm and 32 nm technology nodes. Currently,
193 nm immersion lithography is widely employed in IC manufacturing processes.
The first-generation immersion lithography system as NA is about 0.75–0.93. The
second-generation immersion system has NA about 1.35. The immersion lithogra-
phy systems use high-purity DI wafer with temperature precisely controlled to the
same level as objective lens and wafer.
While stepping with high-speed between reticle shots, high-precision control is
needed to prevent a single water droplet leaving behind in the previously exposed
area and tiny air bubble generating in the water sheet (~0.5 mm) between the
objective lens and the wafer surface. The 193 nm immersion lithography system
can pattern 28 nm logic IC devices in a single patterning process. Combining with
multiple patterning techniques, the 193 nm immersion lithography can be pushed to
14 nm, 10 nm, and 7 nm technology nodes [1, 5]. Currently ASML dominates the
193 nm immersion lithography market with Nikon as a distant minor player.

Extreme UV (EUV)

Extreme ultraviolet (EUV) lithography is a lithography technique in which the

illuminant wavelength is in the extreme ultraviolet range. In the air environment,
the most critical parameter of lithography is R ¼ k1λ/nNA and n ¼ 1 in vacuum. It
can be seen that there are three ways to improve the resolution, i.e., reducing the
process factor k1, decreasing the wavelength λ, and/or increasing the numerical
aperture NA. According to the formula of depth of focus (DOF), DOF ¼
k2λ/(NA)2, increasing the numerical aperture will reduce the DOF and affect the
imaging effect, even if it can improve the resolution. Therefore, the most effective
method of improving lithography is to shorten the illuminant wavelength. Before
0.13 μm technology node, deep ultraviolet (DUV) lithography with a wavelength
of 248 nm can meet the requirements; at 90 nm node, lithography with a wavelength
of 193 nm is necessary at some critical layers. It can be said that the main methods of
improving lithography is to reduce the illuminant wavelength before immersion
lithography is used at the 45 nm node. Extreme ultraviolet (EUV) rays are
49 Unit Processes 919

electromagnetic radiation with wavelength between 1 and 50 nm. They are also
named as vacuum ultraviolet rays or soft X-rays as their wavelength is in between
ultraviolet rays and X-rays. The methods for generating EUV light sources are
mainly laser-produced plasma (LPP) and discharge-produced plasma (DPP) [6].
The main challenges for EUV lithography to be implemented in IC manufacturing
are that the optical output power is too low to achieve enough throughput, and the
PR, reticle, and reticle pellicle of EUV lithography have extremely high difficulties
[1]. All optical modulations need to be achieved by a mirror system, but usually
materials have high energy absorption rate at EUV, so it is difficult to make
conventional optical lens for EUV modulation. In order for the reticle to effectively
reflect EUV with 13.5 nm wavelength, it is necessary to stack up to 50 layers of
Mo/Si film on a quartz mask substrate as a mirror as illustrated in Fig. 49.2.
Furthermore, optical detection of defects on the reticle is extremely difficult. In
general, optical detection can catch all pattern transfer defects caused by surface and
phase defects, but these defects are buried under the multilayer film due to the
multilayer mask structure of EUV. At present, optical EUV mask detection technol-
ogy is still in infancy stage, so photomask detection and electron beam mask
detection only stay in the development and experimental stages of EUV lithography.
At present, only the Netherlands ASML can produce commercial EUV lithogra-
phy systems with breakthroughs in critical technologies. Most of the leading com-
panies have purchased or ordered EUV lithography systems for R&D at 7 nm and
5 nm nodes. EUV lithography in these companies has achieved positive results, and
the throughput rate is close to the level of 3 times of 193 nm immersion lithography.
It has been announced that EUV is to be used for IC manufacturing at 7 nm node in
2019. Almost all pattern layers of 7 nm node can be completed by EUV single
exposure, which can reduce the photomasks by more than 20 layers. Less mask layer
number can reduce process complexity and production cost, improve yield, and
shorten product development cycle time. Although EUV lithography has the above
advantages, its unit price is very high. As of 2020, it is still the most expensive
process equipment in the IC history. EUV lithography is successfully used for
manufacturing at 7 nm node by TSMC and Samsung in 2019.

Fig. 49.2 Schematic of the EUV mask

920 H. Wu et al.

Computational Lithography

Computational lithography is a way to enhance the fidelity of pattern transfer in

lithography by using computer-assisted technology. It is an evolution of resolution
enhancement technology (RET) and involves three main technology solutions:
lithography imaging physics simulation, optical proximity correction (OPC), and
source-mask optimization (SMO) as compared in Table 49.2. Computational lithog-
raphy predicts the patterns formed on Si wafer by lithography simulations; so that the
mask patterns (on reticle) and lithography process conditions are both adjusted and
optimized with iterations. The goal is to transfer the desired design patterns onto the
Si wafer more truthfully by optimizing mask patterns (on reticle), lithography
equipment, and process conditions. Computational lithography plays an important
role in design for manufacturability (DFM) or design and technology
co-optimization (DTCO). The computations of mask layout separation and combi-
nation in double patterning or multiple patterning are also considered as a general-
ized computational lithography technology.

Physical Simulation of Photolithography Imaging

It refers to the technology that uses Abbe imaging model to simulate the final
photolithography effect by calculating mask diffraction, pupil, modulation, and
interference imaging in turn. Lithography imaging physics simulation refers to the
technique of simulating the final lithography effect using the Abbe theory of
imaging, including calculating mask diffraction, pupil modulation, and interference
imaging effect sequentially. Among them, various technical parameters of the mask
aligner (e.g., defocusing, wave aberration, polarization, etc.) and optical parameters
of the PR (e.g., film structure, refractive index, and absorption coefficient of each

Table 49.2 Three computational lithography technology solutions comparison

Computational
lithography Optical
technology Lithography imaging physics proximity Source-mask
solution simulation correction optimization
Core model Diffraction and interference Fast imaging Hybrid model
imaging model model
Input Parameters of mask aligner and Mask graph Pupil filling
lithography processes parameters and initial
mask graph
Output Final lithography effect Corrected Optimized pupil
mask graph filling parameters
and corrected mask
graph
Usages Initial parameter configuration and Compensate Increase the
optimize the parameters of mask the pattern lithography process
aligner and lithography processes distortion window
49 Unit Processes 921

layer) are expressed in a unified equation on the pupil plan to calculate the pupil
modulation effect. Various process parameters (e.g., photo-chemical reaction param-
eters, development parameters, etc.) are loaded into the calculation of spatial light
intensity distribution on the PR to simulation the final process effect. In the mask
aligner developing, lithography imaging physics simulation can be used to optimize
equipment parameters and guide performance debugging. In the lithography process
developing, lithography imaging physics simulation is often used to determine the
equipment and process for mass production, initial parameter configuration, and
trend analysis of lithography effects during optimization.

Optical Proximity Correction (OPC) Technology

It is a lithography enhancement technique for correcting pattern defects and distor-

tion after lithography. It is also a resolution enhancement technology (RET) widely
used in IC manufacturing [7]. When the minimum line width of the semiconductor
device is close to the wavelength of the light source, due to the influence of the
optical proximity effects (OPE), the pattern transferred to the Si wafer has deforma-
tion and defects (e.g., shortened size, line tip, rounded corners, etc.). The OPC
technique uses simulations to modify the patterns (on reticle), such that the trans-
ferred patterns (on Si wafer) approaches the target pattern (in data base) as illustrated
in Fig. 49.3 [8]. The principle of OPC technology is to compare the final patterns
(on Si wafer) with the designed patterns (in database) and then to compensate the
patterns (on reticle) for minimizing pattern defects and deformations by a compen-
sation rule library or model. In the more advanced technology, the influence of
etching should also be considered and included in the OPC technique. After

Fig. 49.3 The OPC processing flow [8]

922 H. Wu et al.

repeating iterations, the final physical patterns formed on the wafer are as close as
possible to the target designed patterns for ensuring the normal operation of devices
and the circuits. Therefore, the OPC compensation procedures can be “rule-based”
OPC technology as typically used at 0.18 μm and earlier nodes or “model-based”
OPC as typically used at 0.13 μm node and beyond.

The Source-Mask Optimization (SMO) Technique

It uses a similar ray tracing algorithm to perform back-calculation from the target
image to obtain the desired optimal pattern on reticle and light source configuration
scheme. The technology uses a precise imaging model to calculate the lithographic
imaging effects with different pupil filling parameters and mask layout corrections
for maximizing lithography process window. The lithography imaging physics
simulation technology and the OPC technology are combined with SMO to calculate
the influence of the pupil filling parameters and the mask layout correction amount
on the final lithography effect. The overall optimized pupil filling parameters and the
mask layout corrections are further optimized by multiple iterations toward best
compensated pattern distortion, sharpest contrast of imaging, and maximized pro-
cess window.
The development of computational lithography has enabled the extension of deep
UV immersion lithography to exceed the industry’s prior predictions. It can meet the
lithography requirements of the 14–10 nm technology nodes at least and win more
time for the EUV lithography technology to be maturing. Computational lithography
improves the resolution and image fidelity of the lithography process, but it also
imposes more restrictions on the circuit design toward more complex design rules. In
addition, computational lithography needs huge computation resources in the devel-
opment of IC technology, and requires a large amount of EDA software and CPU
hardware resources. In order to develop advanced technology beyond 7 nm nodes,
manufacturers may need to establish a computational lithography platform similar to
a supercomputing center.

Oxidation Process

In IC chip manufacture, there are two ways to form Si dioxide (SiO2), i.e., thermal
oxidation and thin film deposition. Oxidation process refers to the thermal process
under oxygen or steam ambient to form Si dioxide SiO2 on Si wafer. The thermal
oxide has excellent isolation property and stable; thus it is widely used in IC
manufacturing (e.g., gate oxide in CMOS, STI isolation, surface passivation, implant
hard mask, diffusion barrier layer, buffer layer between Si and other materials, etc.).
Si oxidation can occur in air at room temperature to form SiO2 film, the oxidation
rate is about 1.5 nm/h, that with maximum thickness of about 4 nm. As the native
oxide is poor in quality and not controllable in growth, it is necessary to remove
49 Unit Processes 923

native oxide before high quality oxide is grown with high purity oxygen at high
temperature [1, 2, 9].
There are two different oxidation processes, i.e., dry oxidation and wet oxidation,
according to designed reaction gases. (1) Dry oxidation reaction is Si þ O2 ! SiO2,
O2 molecular in reaction gas penetrate the surface SiO2 and reach the boundary of
SiO2 and Si to form new SiO2 film. Dry oxidation can form dense and uniform SiO2
film with high quality to serve as gate oxide in CMOS transistors, tunnel oxide in
memory cells, diffusion mask, thin buffer oxidation, or liner before thick Si dioxide
deposition. (2) Wet oxidation reaction equation is represented as H2O(Vapor) þ
Si ! SiO2 þ 2H2. In wet oxidation processes, water vapors can be either carried by
O2 or generated by the reaction between hydrogen (H2) and oxygen (O2). The
oxidation ratio can be controlled by adjusting the ratio of H2 or vapor and oxygen.
Safety attention must be paid so that the ratio of hydrogen and O2 should be less
than 1.88:1. Because both O2 and vapor can exist in wet oxidation, hydroxide
(OH) can be formed at high temperature. The diffusion rate of OH in SiO2 is higher
than O2 and the oxidation rate of wet oxidation is about one order of magnitude
higher than the dry one. Beside the traditional dry and wet oxidations, chlorine (Cl),
such as HCl and DCE(C2H2Cl2) or other ramifications, is often added to increase the
oxidation rate and film quality. Meanwhile, Cl is accumulated near the boundary of
Si-SiO2 interface. The Cl silicide can promote the SiO2 formation under O2 envi-
ronment and also passivate sodium (Na) ions SiO2 from contamination to devices
[10, 11]. Therefore, most dry oxidation processes need to add Cl in process recipes.
Because the temperature is high and process time is long in traditional oxidation
processes, it is necessary to strictly limit the thermal budget to avoid device
degradation by impurity redistribution at advanced technology node. In high-k and
metal gate (HKMG) flow, rapid thermal oxidation (RTO) or chemical oxidation is
adopted to form ultra-thin interfacial layer. In rapid thermal oxidation, the temper-
ature ramps up and down is 100–1000 times faster than traditional oxidation in
furnace, and the thermal budget is greatly reduced. In chemical oxidation, combi-
nation of ozone (O3) oxidation and chemical materials can fabricate high-quality
SiO2 film at room temperature due to its significantly low thermal budget.

Diffusion Processes

Diffusion is the process of material diffusion from high to low concentration areas
until achieving uniform concentration. It follows Fick’s law. Diffusion can occur in
two or more materials as driven by concentration difference between different
regions. One of the most important properties of semiconductor is its conductivity
can be modulated by dopant concentration. By intentionally adding different impu-
rity atoms (referring to as dopants) into pure Si or III-V compound semiconductor
material, n-type or p-type semiconducting can be formed. The doping process can be
realized by diffusion and/or ion implantation. Diffusion has lower cost; however, it
cannot independently control dopant concentration and junction depth. Ion
924 H. Wu et al.

implantation is more expensive, but it can independently control dopant concentra-

tion and junction depth with accuracy as required by most IC devices [1].
In the 1970s, feature sizes of IC devices were in 10um range, and traditional
thermal diffusion was widely used in the doping processes. By diffusing dopant
materials into semiconductor material, it can alter its conductivity and other physical
properties. For example, by doping boron (B) into Si, it becomes p-type Si with holes
as charge carriers; and by doping phosphorus (P) or arsenic (As), it becomes n-type
Si with electrons as charge carriers. When the n-type Si is in close contact with
p-type Si, it forms a p-n junction. While the scaling of the IC device into nm range,
isotropic diffusion process could result in dopant diffusion too far and leading to
leakage or even short. Therefore, except few niche applications, such as deep well,
uniform junction of high-voltage (HV) devices, almost all doping processes are
performed by ion implantation (with low thermal budget). FinFET has been widely
used after 14 nm node, with the fin width < 10 nm, ion implantation may damage the
fin structure; thus, the solid source diffusion may be used for the doping of fins or
simply no doping for fully depleted fins during operation.

Ion Implantation

Ion implantation is one of the key processes in IC manufacturing. It refers to the

process of accelerating the ion beam to certain energy (typically in the range of keV
to MeV) and then implanting it into the surface layer of solid materials to change the
physical properties of the surface layer. In IC technology, the solid material is usually
Si, and the implanted ions are usually boron (B), phosphorus (P), arsenic (As),
indium (In), germanium (Ge), etc. as illustrated in Fig. 49.4. Implanted ions may
change the conductivity of surface layer or form PN junction in CMOS. Ion
implantation is widely used in IC manufacturing.

Fig. 49.4 Illustration of

n-type source/drain formed by
As+ or P+ implantation at
nMOS area
49 Unit Processes 925

Compared with the conventional doping through thermal diffusion process, the
ion implantation process has the following advantages. (1) By adjusting the energy
and dose of implantation to change the profile of implanted ions (i.e., ion concen-
tration vs depth), the impurity ions with higher specific concentration can be deeper
into the substrate as not achievable by diffusion process. (2) Although the incident
ions implanting into the substrate material will have a small transverse scattering due
to collision, they can be doped at the desired position according to the mask pattern.
The mask material for blocking ions can be those commonly used in semiconductor
process (e.g., PR), which is very helpful to improve the integration. (3) Ion implan-
tation uses scanning method to inject ions into Si wafer sequentially at relatively low
temperature for breaking through the limitation of solid solubility in diffusion
process; it can result in higher local concentration, shallower junction depth, and
more uniform distribution.
The ion implantation process is widely used in the doping of deep buried layer,
retrograde well, threshold voltage (Vt) adjustment, source/drain shallow extension,
source/drain main junction, poly-Si gate doping, PN junction formation, and resistor
and capacitor in IC manufacturing. In preparing Si-on-insulator (SOI) substrate,
buried oxygen layer is formed by high dose of oxygen (O) ion implantation, and the
“smart cut” technique is realized by high dose of hydrogen (H) ion implantation. Ion
implantation is accomplished by an ion implanter. The most important process
parameters are dose and energy: dose determines the final concentration, and energy
determines the range (i.e., depth) of the ion.
According to the different requirements of device design, the implant conditions
can be divided into high-dose/high-energy, medium-dose/medium-energy, medium-
dose/ low-energy, or large-dose/low-energy. In order to achieve good process results,
different implanters should be used according to different requirements (e.g., high
current implanter for large does implant, high voltage implanter for high energy ion
implant, etc.). After ion implantation, annealing (RTA, furnace, or laser anneal) at
high temperature is usually performed for repairing lattice damage caused by ion
implantation and activating impurity ions.
In conventional IC technology, though the post implant annealing temperature
has a great influence on doping, the temperature of ion implantation process itself is
not very critical. At the 14 nm FinFET technology node, some ion implantation steps
need to be performed at low (e.g., 70  C) or high temperatures for changing or
tuning the effects of lattice damage.

Plasma Doping

It is well-known that any surface near the plasma always get ion bombardment due to
the electron charge induced self-bias as well as externally applied bias. Ion bom-
bardment energy can be few electron volts (eV) to over 10 thousand eV and thus can
be used to replace some ion implantation processes. The largest advantage of plasma
doping is its higher throughput with ultra-low energy doping [1]. This is because
plasma doping is a whole surface process with no need of wafer movement, while
926 H. Wu et al.

Fig. 49.5 Illustration of structures for PIII and PLAD systems

traditional ion implantation is either a spot process or a band process and needs wafer
movement to achieve uniform doping of full wafer.
Plasma doping (PLAD) or plasma immersion ion implantation (PIII) systems
have been developed for replacing the traditional ion implantation system in high
volume manufacturing HVM processes, mainly these doping processes that do not
require high-purity of ion species and ion energy but need high throughput, such as
ultra-shallow junction and deep trench doping as illustrated in Fig. 49.5.
Usually radio frequency (RF) power is used to generate plasma and dopant ions in
dopant source gas and bias power to accelerate ions to bombard the wafer surface.
The most commonly used PLAD dopant source gas is B2H6 for B doping. For IC
devices that need junctions with super-high dopant concentration, it would take a
long time with traditional high-current ion implanter. PLAD has much higher
throughput than the high-current implanter because it dopes the whole wafer simul-
taneously, while ion implanter only dopes a “spot” or a “band” one at a time. The
disadvantage of PLAD is that it cannot select exact ion species, nor can it precisely
control the dopant concentration; therefore, it is mainly used for higher dosage and
non-critical ion implantation layers. The main applications of PLAD are in DRAM
manufacturing process (e.g., poly-Si gate counter doping and array contact doping).
In PLAD system, dopant ions bombard wafer surface and implant into substrate.
Dopant ion flex is mainly controlled by the external RF or microwave power while
ion energy is mainly determined by bias RF power. The magnetic field can help to
maintain at low pressure, and magnetic field location can be controlled by current in
magnetic coil. Plasma uniformity can be controlled by the magnetic field. PLAD
technology is a low-energy process, ion energy usually lower than 1 keV. It can be
used to from ultra-shallow junction of sub-100 nm device. Compared with tradi-
tional ion implantation technology, PLAD has disadvantages of unable to select
specific ion species and wide ion energy distribution (i.e., possibly energy contam-
ination). Thus PLAD system cannot precisely control the dopant concentration and
junction depth.
49 Unit Processes 927

Thermal Annealing

The annealing process is also called thermal annealing. The process is to place the Si
wafer in a high temperature environment for a certain period of time to change
the microstructure of the surface or interior of Si wafer to achieve a specific purpose.
The most critical parameters of the annealing process are temperature and time. The
higher temperature with longer time results in more thermal budget. In the actual IC
manufacturing process, the thermal budget needs tight control. If there are multiple
annealing steps, the thermal budget is additive, i.e., DTeff ¼ DT1 þ DT2 þ . . . þ
DTn. The thermal budget allowed in the entire process is less and less in the
advanced technology nodes; this means that the thermal process steps need to be
at lower temperature and shorter time [12].
Typically, the annealing process is combined with other process steps (e.g., ion
implantation, thin film deposition, metal silicide formation, etc.). The most common
combination is thermal annealing after ion implantation. Ion implantation can impact
the substrate atoms away from the normal lattice position (i.e., damages in the
substrate lattice). Thermal annealing recovers these lattice damages and also activate
the implanted impurity atoms. The temperature required for lattice damage recovery
is about 500  C and about 950  C [2] for impurity activation. In theory, the longer
annealing time and higher temperature results in higher impurity activation rate.
However, too high thermal budget will lead to excessive diffusion of impurities, and
it will result in degradation of the device and circuit performance. Therefore, the
conventional long-time furnace annealing has been gradually replaced by rapid
thermal annealing (RTA).
In the manufacturing process, some films require thermal annealing process after
deposition to change their physical or chemical properties. For example, densifying
the loose films to change its dry etching rate or wet etching rate; post deposition
annealing (PDA) after high-k gate dielectric growth improves the high-k dielectrics
toward lower gate leakage current and higher dielectric constant. Another type of
annealing process is used more often during the formation of a metal silicide. A
metal film (e.g., Co, Ni, Ti) is sputtered onto the surface of the Si wafer and alloyed
with Si by RTA at a lower temperature. Some metals have different alloy phases
formed under different temperature conditions, and it is generally desirable to form
an alloy phase with low contact resistivity and low body resistivity in the process.
As mentioned earlier, the annealing process is divided into high temperature
furnace annealing and RTA depending on the thermal budget requirements. High
temperature furnace annealing is a traditional annealing method with higher tem-
perature with longer annealing time and higher thermal budget. Some special
processes, such as Separation by IMplantation of OXygen (SIMOX) to form SOI
substrates, deep n-Well drive-in, generally require a high thermal budget to achieve a
perfect lattice or uniform impurity distribution, so the furnace annealing is a better
choice. RTA treats the wafer with extremely fast rise/fall and short dwell time at the
peak temperature, and it is often referred to as rapid thermal processing (RTP). RTA
achieves compromise optimization among lattice defect recovery, impurity activa-
tion, and minimum impurity diffusion in the ultra-shallow junction process, and it is
928 H. Wu et al.

essential in the manufacturing process of advanced technology nodes. Both of the

rise/fall temperature process and the short-time staying at the peak temperature
compose the thermal budget of RTA. Conventional RTA temperature is about
1000  C and the time is about several seconds.
In recent years, the thermal budget becomes more and more strict, and flash lamp
annealing (FLA), spike annealing, and laser spike annealing (LSA) have been
developed. The annealing time has reached the order of milliseconds (ms), and
even there is a trend toward to microseconds (μs) and sub-microseconds in the
development. The most unique advantages of laser annealing are the limited volume
and very short time. The energy of the laser source can rapidly heat the wafer surface
near the melting point [1], and then the wafer surface is cooled down quickly in
about 0.1 ns due to the high thermal conductivity of Si material. The laser annealing
system can activate dopant ions with minimal impurity diffusion after ion implan-
tation and has been used in 45 nm node and beyond. Laser annealing systems can
also be used together with spike annealing systems to achieve optimal results.

Physical Vapor Deposition and Sputtering

Physical vapor deposition (PVD) technology refers to the formation of thin films on
the surface of wafers by physical methods, such as vacuum evaporation, sputtering,
ion plating, and molecular beam epitaxy. In the very large-scale IC (VLSI) industry,
the most widely used PVD technology is sputtering technology mainly for the
formation of the electrode and interconnect of ICs. Sputtering film deposition is a
process in which rare gases (e.g., Ar) are ionized into ions (e.g., Ar+) under an
applied electric field at high vacuum and bombarded the material target source at
high voltage environment. The atoms or molecules of the target are impacted and
flying (with collision-free at high vacuum) toward the wafer surface for thin film
deposition as illustrated in Fig. 49.6. The chemical properties of Ar are stable, and its
ions will not react with targets and films.
As IC technology entering 0.13 μm Cu interconnect, TiN or TaN thin films are
needed as barrier metal layers. The demand of industrial drives the development of
chemical reactive sputtering technology. In the sputtering cavity, not only Ar, there is
also N2 as reactive gas for reacting with Ti or Ta atoms bombarded from target
material to form TiN or TaN films on wafer surface [2]. There are three commonly
used sputtering methods, i.e., direct current sputtering, radio frequency
(RF) sputtering, and magnetron sputtering. As advanced CMOS technology con-
tinues, the layers of interconnect also increases with more extensive application of
PVD technology. PVD materials include Al-Si, Al-Cu, Al-Si-Cu, Ti, Ta, Co, TiN,
TaN, Ni, WSi2, etc.
PVD and sputtering process are usually completed in a highly sealed reaction
chamber with a vacuum of 1  107 – 9  109 Torr, which can ensure the purity of
the gas in the reaction process. At the same time, a high voltage is needed to ionize
the rare gas to produce a high enough voltage to bombard the target. The main
49 Unit Processes 929

Fig. 49.6 Diagram of PVD process

parameters for evaluating PVD and sputtering process include particle count, the
resistivity, uniformity, reflection index, thickness, and stress of the films.

Chemical Vapor Deposition

Chemical vapor deposition (CVD) refers to the process technology of depositing

thin film on the wafer surface by chemical reaction of reactants in various gas states
with different partial pressures at a certain temperature and pressure. In the IC
manufacturing, the needed thin film materials are generally Si-oxides, Si-nitrides,
Si-carbides, poly-Si, a-Si, and other materials. Selective epitaxy technology, e.g.,
SiGe epitaxy at source/drain or selective epitaxy growth (SEG) of Si, is commonly
used at 45 nm nodes (and beyond) and is also a CVD technology. This technique can
continue to form single crystal materials of the same kind or similar lattice along the
original lattice on single crystal Si substrates (or other material). CVD is widely used
in the growth of insulating dielectric films (e.g., SiO2, Si3N4, SiON, etc.) and metal
films (e.g., W, etc.) [1]; some basic chemical reactions at a certain temperature are as
follows:

SiH4 þ O2 ! SiO2 þ 2H2

SiH4 þ 2PH3 þ O2 ! SiO2 þ 2P þ 5H2
SiH4 þ B2 H6 þ O2 ! SiO2 þ 2B þ 5H2
3SiH4 þ 4NH3 ! Si3 N4 þ 12H2
930 H. Wu et al.

Fig. 49.7 Diagram of CVD

process

Other gases used for CVD chemical reaction include N2O, Si(C2H5O)4, SiCl2H2,
and WF6. In general, there are various CVD technologies based on different pres-
sure, temperature, and precursors. If based on operating pressure, there are atmo-
spheric pressure CVD (APCVD), sub-atmospheric pressure CVD (SAPCVD), and
low pressure CVD (LPCVD); if based on temperature, there are high temperature/
low temperature CVD (HTO/LTO CVD) and rapid thermal CVD (RTCVD). There
are also silane-based CVD, TEOS-based CVD, and metal organic-based CVD
(MOCVD) in line with various reactant sources; there are also thermal CVD,
plasma-enhanced CVD (PECVD), and high-density plasma CVD (HDCVD) based
on energy type for chemical reaction. The latest development is the flowable CVD
(FCVD) which has excellent gap filling capability. Various CVD deposition methods
may result in thin film with different characteristics, e.g., chemical composition,
dielectric constant, tension, stress, and breakdown voltage. They are used according
to different process requirements (e.g., temperature, step coverage, gap-filling, etc.).
A CVD process is illustrated in Fig. 49.7.

Atom Layer Deposition (ALD)

Atomic layer deposition (ALD) refers to the layer-by-layer deposition of atoms on

the substrate through the growth of monoatomic films. Typical ALD implemented
by alternately pulsing gas precursors into the reactor. For example, first, the
reaction precursor #1 is introduced to the substrate surface and then chemically
adsorbed to form a monoatomic layer on the surface. Then, the precursor #1
remaining on the surface and the reaction chamber is pumped out by gas pump.
Then, the reaction precursor #2 is introduced to the substrate surface and reacts
with the precursor #1 adsorbed on the surface to form a chemical reaction on the
surface. The reaction will terminate automatically after the completion of reaction
with the precursor #1 as a self-limiting mechanism of ALD. Then, the residual
49 Unit Processes 931

reactants and by-products are removed by pumping and ready for repeating the
next step of growth, and the layer-by-layer deposition of thin film material can be
achieved. Both ALD and CVD are gas phase chemical reactions on the surface, but
the gas phase reaction of CVD does not have self-limiting mechanism. Thus, the
key in the ALD technology is to select precursors with self-limiting mechanism.
Thus, ALD thin film deposition can achieve excellent step coverage, uniformity,
and consistency with well-controlled thickness, composition, and structure of the
films. ALD thin films are widely used in the field of IC manufacturing, especially
for the spacer formation as well as thin films in through holes and trenches with
larger aspect ratio.
The main applications of ALD technology in IC manufacturing include the
formation of spacers at gate sidewall, high-k gate and metal gate (HKMG), barrier
layer in Cu interconnect process, micro-electromechanical system (MEMS), opto-
electronic materials and devices, organic light-emitting diode (OLED), DRAM
and MRAM dielectrics, embedded capacitors, electromagnetic recording heads,
and other thin films. In the advanced node of IC technology, the device is
continuously scaled to smaller CD, thinner film thickness, and larger aspect ratio
(i.e., the depth to width ratio of trenches, contacts, and vias), and ALD technology
is widely used. For example, the FinFET devices at 14 nm node (and beyond) need
to use the self-align double exposure (SADP) technology to form fins, where the
spacer of mandrel needs to be formed by ALD technology. The ALD technology is
also widely used in the deposition of thin dielectric and metal films in HKMG
formation.

Chemical Mechanical Polishing

Chemical mechanical polishing (CMP) is one of the important processes in the

manufacture of integrated circuits, also known as chemical mechanical
planarization. In the early 1980s, during the manufacture of DRAM, IBM
established a CMP process for silicon oxide (SiO2) in order to achieve global
planarization of the inter-metal dielectric layer (IMD) on the wafer surface and
later extended to tungsten (W) CMP. As transistor integration continues to increase,
copper (Cu) interconnects have become the only choice for IC back-end-of-line
(BEOL) processes since the 0.13 μm process node, which has made the Cu CMP
significant. With the forward extension of Moore’s law, in the high-end process from
28 nm node, the fabrication process of the MOSFET gate also introduces a CMP
process to achieve a more uniform gate height.
The implements and consumables used in CMP include polishing platform,
slurry, pads, post-CMP cleaning equipment, end point detection and process control
instrument, waste treatment, and testing equipment. The equipment used in CMP
process is generally called a polishing platform. The mainstream polishing platform
usually has a large circular polishing table. The polishing table is attached with a pad
made of different materials according to the process, and the wafer is loaded. The
932 H. Wu et al.

carrier head applies pressure on the back of the wafer so that the surface of the wafer
is pressed down on the pad. The slurry flows through the liquid delivery line of the
polishing machine from the tiny nozzle onto the specific position of the pad, and then
the slurry is naturally dispersed between the wafer and the polishing pad as the pad
moves.
The physical part of the CMP principle is the friction, and the chemical part is the
oxidation reaction. During the process, the wafer and the pad generally rotate in the
same direction but with different speed, and the head which carries the wafer also
generates radial oscillation, and there is a relative movement between the wafer and
the pad due to the different speed. The material on the surface of the wafer is
oxidized by chemical in the slurry and then converted into a substance easy to
separate, while the abrasive particles in the slurry peel off the material from the
surface of the wafer by mechanical friction. The mechanical and chemical reactions
are performed simultaneously; and when the two are balanced, a stable polishing rate
and a good defect result can be resulted. Since the CMP process can achieve a
uniform micro-pattern surface by the different removal rate between the high and
low position of the micro-pattern (the removal rate at higher topology is higher than
that at lower topology), the CMP process can achieve both global and local
planarization, while the latter makes the CMP process an irreplaceable position in
advanced IC manufacturing processes. The CMP process combines the chemical and
physical effect. The single chemical or physical effect cannot meet all the require-
ments of surface accuracy, roughness, uniformity, material removal rate, and surface
loss. The CMP process combines the advantages of both effects while ensuring
material removal efficiency and can achieve accurate thickness of surface material
layer, better flatness and uniformity, and nano-scale or even atomic-level surface
roughness with less surface loss.
Based on simple physical and chemical principles, the CMP process delivers
accurate and stable micro-process results. This makes it one of the most widely used
and expanding processes in IC manufacturing. For example, in advanced technology
development, the formation of the transistor gate is directly affected by CMP
process, and the CMP process is becoming more and more important to influence
the final device performance. The unique character of CMP process is that it can be
tailored to the needs of the polishing process by properly designing the slurry and
pad. Depending on the materials, CMP processes are mainly divided into Poly-CMP,
SiO2-CMP, SiC-CMP, W-CMP, and Cu-CMP.

Epitaxy

Epitaxy is the process to grow a crystal layer on a single crystal substrate with the
same orientation as the original substrate. Epitaxy technology is widely used in
semiconductor manufacturing (e.g., epitaxial Si wafer, embedded source/drain,
epitaxial growth on LED substrate, etc.). According to the different phase states of
growth source, epitaxy can be divided into solid phase epitaxy (SPE), liquid phase
epitaxy (LPE), and gas phase epitaxy (GPE). SPE and GPE are commonly used in IC
manufacturing.
49 Unit Processes 933

Solid Phase Epitaxy

SPE normally means growth of a single crystal layer on the substrate by a solid
source, such as re-crystallization post ion implantation by thermal annealing. During
ion implantation processing, the Si atoms of Si wafer are bombarded by high energy
implanted ions, which break away from the original lattice position and thus form a
surface amorphous Si layer. After high temperature thermal annealing, the random
distributed Si atoms will return to the normal lattice position and keep the same
orientation with the substrate.

Gas Phase Epitaxy

The growth methods of gas (vapor) epitaxy include chemical vapor epitaxy (CVE),
molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE). Chemical vapor
epitaxy (CVE) is the most commonly used method in IC manufacturing. Chemical
vapor epitaxy (CVE) is one of special chemical vapor deposition (CVD) processes.
In both CVE and CVD, reactive gases are mixed and chemically reacted on the wafer
surface for forming the deposited films. The difference is that the CVE film is a
single crystal layer, so the impurity content in the equipment and the cleanliness of
the wafer surface are much more important. Early chemical vapor epitaxy (CVE) of
Si needs to be performed at high temperature (more than 1000  C). With the
improvement of process equipment, especially the adoption of load-lock chamber
technology, the cleanliness of reaction chamber and the impurities on surface of Si
wafer has been greatly improved. The epitaxy of Si can be performed at a lower
temperature (600–700  C). In IC manufacturing, CVE is mainly used for epitaxy Si
wafer process and embedded source/drain epitaxy process of MOS transistor. Epi-
taxial Si wafer technology is to epitaxy a layer of single crystal Si on the surface of Si
wafer.
Compared with the original Si substrate, the epitaxial Si layer has higher purity
and fewer lattice defects, thus improving the yield of ICs. In addition, the growth
thickness and doping concentration of epitaxial Si layer on Si wafer can be designed
with flexibility to device tuning, e.g., reducing substrate resistance and enhancing
substrate isolation. Embedded source/drain epitaxy technology is widely used in
advanced logic technology nodes by epitaxy growth of doped SiGe or Si. The main
advantages of the embedded source/drain epitaxy technology include the following:
it can grow pseudo-crystalline layer containing stress, improving channel carrier
mobility; it can in situ doping source-drain for reducing parasitic resistance and
defects.

Dry Etching and Cleaning

Dry etching in IC manufacturing mainly refers to plasma etching, i.e., the use of
plasma ions to etch specific materials. The equipment system used in large-scale
production is usually low temperature non-equilibrium plasma. There are two main
934 H. Wu et al.

discharge modes in plasma etching, namely, capacitive coupled plasma (CCP) and
inductive coupled plasma (ICP). In capacitive coupled discharge mode, plasma
discharges are generated and maintained in two parallel plate capacitors through
an external RF power supply. Usually, the gas pressure is from few to 10’s of mtorr,
and the ionization rate is less than 105. In inductively coupled discharge (ICD)
mode, plasma is usually produced and maintained at low pressure (10’s of mTorr) by
the inductively coupled input energy. Usually the ionization rate is greater than 105
and thus also referred to as high density plasma.
High-density plasma source can also be obtained by electron cyclotron resonance
(ECR) and helicon wave discharge. High-density plasma can optimize the etch rate
and selectivity of etching process and reduce plasma damage [1] by independently
controlling the ion flux and ion bombardment energy through RF or microwave
power supply as well as the RF bias power supply on the substrate.
The process of dry etching is to inject etching gas into vacuum chamber and
generate plasma by RF glow discharge after pressure stabilized. Free radicals are
generated by decomposition after high-speed electron impact and diffused to the
surface of the wafer for absorption [1]. Under ion bombardment, the adsorbed free
radicals react with atoms or molecules on the surface to form gaseous by-products
and discharged from the reaction chamber. Dry etching process can be divided into
four categories.

1. Physical sputtering etching: It mainly depends on the energy-carrying ions

bombarding the surface of the etched material. The number of atoms sputtered
depends on the energy and angle of the incident particles. With constant energy
and angle, the sputtering rates of different materials are usually only 2–3 times
different, i.e., not much selectivity. The reaction process is mainly anisotropic.
2. Chemical etching: The plasma provides gaseous etching atoms and molecules
reacting with surface material to produce volatile gases, e.g., Si (solid) þ
4F ! SiF4 (gaseous), photoresist + O(gaseous) ! CO2 (gaseous) þ H2O
(gaseous). Such pure chemical reaction has good selectivity. If not considering
the lattice structure, it shows isotropic characteristics.
3. Ion energy-driven etching: ions are not only the particles for the etching, but also
the energy-carrying particles. The etching efficiency of the energetic particles is
more than one order of magnitude higher than the physical or chemical etching
alone. The optimization of physical and chemical parameters is a key for con-
trolling the etching process.
4. Ion-barrier composite etching: it mainly refers to the formation of polymer-like
barrier protection layer by reaction of particles in the etching process. In the
process of plasma etching, the adding of C to Cl and Cl2 etching can result in a
layer of chloro-carbon on sidewall for anisotropic vertical etching.

Dry cleaning mainly refers to plasma cleaning. The removal and ashing of PR can
be achieved by bombarding surface with ions in the plasma and the interaction
between the activated atoms and molecules and the cleaned surface. Unlike dry
etching, the orientation selectivity is usually not included in the consideration, so the
49 Unit Processes 935

process design is relatively simpler. In large-scale production process, F-based gas

and O2 or H2 are mainly used as the main body of reactive plasma. Furthermore, by
adding a small amount of Ar plasma, the enhanced ion bombardment can improve
the cleaning efficiency. In plasma dry cleaning process, remote plasma is usually
used for reduced damage by ion bombardment; the reaction of chemical free radicals
is enhanced for improving the cleaning efficiency. The long-distance plasma can
generate stable and high-density plasma by microwave outside the reaction chamber
and generate a large number of free radicals into the reaction chamber for cleaning
reaction. F-based gases (e.g., NF3) are mostly used for dry cleaning in industry. More
than 99% of NF3 is decomposed in microwave plasma. There is almost no ion
bombardment effect in the dry cleaning process, so it is beneficial to protect the Si
wafer from damage as well as the reaction chamber.

Wet Etching and Cleaning

Wet etching is one of the earliest technologies in IC manufacturing. Although most

wet etching processes are isotropic and are replaced by anisotropic dry etching, it
still plays an important role in cleaning those non-critical layers with larger
CD. Especially in the etching of oxide and removal of residues on surface, it is
more effective and economical than dry etching. The main materials to be etched by
wet etching include Si-oxide, Si-nitride, mono-Si, or poly-Si. Hydrofluoric acid
(HF) is usually used as the main chemical for wet etching of Si-oxide.
In order to improve selectivity, dilute HF acid buffered by ammonium fluoride
(NH4F) was commonly used in the process. In order to keep the pH stable, a small
amount of strong acid or other elements can be added. Doped Si-oxide is easier to
corrode than pure Si-oxide. Wet removal is mainly used to remove PR and hard mask
(Si-nitride). Hot phosphoric acid (H3PO4) is the main chemical solution for wet
chemical stripping Si-nitride. It has a good selectivity to Si-oxide. Before such
chemical stripping process, the Si-oxide attached to the surface needs to be pre-
treated with HF acid in order to remove the Si-nitride evenly [1, 2].
Wet cleaning is similar to wet etching in that the pollutants on the wafer surface,
including particles, organics, metals, and oxides, are removed by chemical reaction.
The main wet cleaning is based on wet chemical methods; though many are replaced
by dry cleaning methods, there is no way to completely replace wet cleaning. The
common chemicals used in wet cleaning are H2SO4, HCl, HF, H3PO4, H2O2,
NH4OH, NH4F, etc. In practical applications, it is necessary to mix one or more
chemicals with deionized (DI) water in a certain proportion to form a cleaning
solution, e.g., SC1, SC2, DHF, BHF, etc. [13, 14]
Wet cleaning is often used in the pre-deposition process of oxidation or oxide
deposition, as it must be performed on the absolutely clean surface of Si wafer.
Common Si wafer cleaning processes are shown in Table 49.3. In 1970, the RCA wet
cleaning method was proposed by W. Kern and D. Puotinen of Radio Corporation of
America (RCA). In this method, the No. 1 cleaning solution (RCA1 or SC1) is
alkaline solution, which can remove surface particles and organic matter; the
936 H. Wu et al.

Table 49.3 Common Si wafer cleaning processes [14]

No. Clean steps Purpose
1 Hot H2SO4/H2O2 Removal organic and metal
2 DI water Cleaning
3 Diluted HF (DHF) Removal native oxide
4 DI water Cleaning
5 NH4 OH/H2O2/H2O Particles removal
6 DI clean (room temp, 80–90  C, room temp) Cleaning
7 HCl/H2O2/H2O Removal metal
8 DI water Cleaning
9 Diluted HF(DHF) Removal native oxide
10 DI water Cleaning
11 Drying Drying

No. 2 cleaning solution (RCA2 or SC2) is acidic solution, which can remove surface
metal pollutants and particles. In recent years, cleaning technology has been widely
used in high-end chip manufacturing process supported by new technologies such as
vapor clean and ultrasonic assisted cleaning.

References
1. H. Xiao, Introduction to Semiconductor Manufacturing Technology (Prentice Hall, Columbus,
2001)
2. M. Quirk, J. Serda, Semiconductor Manufacturing Technology (Chinese Version) (Publishing
House of Electronics Industry, Beijing, 2006)
3. Y. Wang, J. Kang, The challenge and development of silicon based IC lithography. J. Semicond.
23(3), 225–237 (2002)
4. B. Chen, Micro-lithography and micro/nano-fabrication technologies[J]. Micronanoelectron.
Technol. 1, 69–73 (2011)
5. J. He, Z. Gao, B. Li, et al., Research progress of materials for 193nm immersion lithography
[J]. Semicond. Technol. 33(9), 743–747 (2008)
6. H. Zhao, H. Zhao, EUV light sources for lithography[J]. Semicond. Technol. 32(1),
12–16 (2007)
7. X. Ma, G.R. Arce, Computational Lithography[M] (Wiley, 2010)
8. P.D. Bisschop, Optical proximity correction: A cross road of data flows. Jpn. J. Appl. Phys.
55(6S1) (2016)
9. S. Sze, Semiconductor Device Physics and Technology (John Wiley, 2002)
10. http://wenku.baidu.com/view/92bb379b6529647d272852c7.html
11. https://wenku.baidu.com/view/26f1239b51e79b896802268c.html
12. C.Y. Chang, S.M. Sze, ULSI Technology[M] (McGraw-Hill College, 1996)
13. T. Hattori, Trends in Wafer Cleaning Technology[M]//Ultraclean Surface Processing of Silicon
Wafers (Springer Berlin Heidelberg, Berlin, 1998), pp. 437–450
14. T. Ohmi, Total room temperature wet cleaning for Si substrate surface[J]. J. Electrochem. Soc.
143(9), 2957–2964 (1996)
Module Processes
50
Hanming Wu, Shan Yu, Hong Xiao, and Poren Tang

Contents
Twin-Well or Dual Well . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Channel Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Polysilicon Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
High-κ Metal Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Silicidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Contact Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
Al/Cu Interconnect and Dual Damascene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Double Patterning Technology (DPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Strained Silicon (Compressive/Tensile Stresses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
Embedded Source and Drain Selective Epitaxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950

Abstract
A complete Si-based CMOS integrated circuit process flow usually includes
hundreds to thousands basic steps, that is, “unit process” steps as described in
Chap. 5. In manufacturing, several basic unit process steps can be grouped as a
“module process” loop for a well-defined function (e.g., STI module, Gate stack,
lithography align/exposure/develop/implant/PR-removal, Contact formation,
Metal/Via formation by Dual-Damascene, etc.).

H. Wu (*)
School of Micro-nanoelectronics, Zhejiang University, Hanzhou, China
e-mail: hanmingwu@zju.edu.cn
S. Yu
China Semiconductor Industry Association, Beijing, China
H. Xiao
KLA-Tencor, Milpitas, CA, USA
P. Tang
Semiconductor Manufacturing International Corp, Shanghai, China

© Publishing House of Electronics Industry 2024 937

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_50
938 H. Wu et al.

Keywords
Well · Isolation · Channel · HKMG · Silicidation · Contact · Interconnect ·
Double patterning · Stained silicon · Selective epitaxy

Twin-Well or Dual Well

One of the basic process modules in complementary MOS transistor integrated

circuit (CMOS IC) technology is the formation of twin-wells (i.e., n-wells and
p-wells), where the n-type metal-oxide semiconductor transistor (nMOS) and
p-type metal-oxide semiconductor transist (pMOS) transistors are formed inside,
respectively, as illustrated in Fig. 50.1. When the wells are formed by ion implan-
tation, the typical technology is based on retrograde doping to adjust the electrical
characteristics of transistors. A first implant with high-energy and high-dose is used
with dopant depth about 1 um and the implant area is the same as the well; this is
mainly for suppressing the punch-through between Source/Drain. Then, a second
implant is performed with shallower depth using lower energy and dose for achiev-
ing the proper threshold voltage (Vt). Well doping by implantation not only adjusts
the Vt of transistor but also solves some common issues of CMOS ICs (e.g., latch-up
effect and other reliability issues) [1].
Currently, the twin-well process is a standard process module in CMOS IC
technology which is based on earlier nMOS and/or pMOS processes. In the early
twin-well CMOS process, there was no high-energy and high-dose implantation, but
medium-energy and medium-dose ions were implanted into the region of n-well and
p-well, and followed by annealing to form independent n-wells and p-wells. With the
advancement of ion implanter, high-energy and high-dose implant is no longer an
issue, so that the twin wells with retrograde doping profile are a standard process for
good device characteristics.
The widely used twin-well process starts to form n-wells first, including the
growth of sacrifice oxide layer, lithography to define n-well area, then n-well
implantation and annealing. The formation of p-wells is similar to that of n-wells.
The process conditions of twin-well lead to optimized electrical characteristics of
nMOS and pMOS transistors (e.g., breakdown voltage among wells, effective

Fig. 50.1 Diagram of twin-well structure

50 Module Processes 939

electrical isolation, latch-up prevention, appropriate Vt, etc.). Additionally, the Si

substrate doping also influences the implant parameters for twin-well formation.

Isolation

ICs are composed of many transistors, and the states of each transistor (on or off) are
different with fast switching during operation. If there is no effective isolation,
transistors will interfere with each other and the ICs will not work properly. The
isolation technology is to block the interferences of current and voltage between
active regions of transistors to ensure normal operation of devices and circuits. There
are various isolation technologies, for example, pn junction isolation, dielectric
isolation, and the combined isolation by pn junction and dielectric. The dielectric
isolation technology includes local oxidation of Si (LOCOS) isolation and shallow
trench isolation (STI).

1. pn junction isolation: It is the earliest isolation technology, which works easily as

excellent isolation when reverse biased. However, the pn junction isolation
results in wide depletion regions at reverse bias, leading to large size and
capacitance, and slow in speed. It is not suitable for the purpose of isolation
for ICs.
2. LOCOS isolation: With the development of CMOS planar technology, LOCOS
has been the mainstream technology for achieving effective isolation of active
regions. The basic LOCOS process steps are: (a) to pattern Si-nitride (Si3N4) as
mask layer for Si oxidation, (b) to perform thermal oxidation in the field between
active regions, and (c) to remove Si3N4 by hot phosphoric acid. The LOCOS
isolation structure between the active areas is completed.
3. STI isolation: It has replaced LOCOS as the mainstream isolation technology
since 0.25 μm CMOS technology node due to the lateral thermal oxidation
(i.e., the “bird’s beak” of LOCOS) is still large in size as shown in Fig. 50.2.
The basic process steps of STI formation include: (a) to pattern and form
300–400 nm deep vertical Si trenches by anisotropic dry etching in isolation
areas, (b) to perform pre-oxidation surface treatment (forming a thin liner); (c) to
fill the trenches with SiO2 by CVD, and (d) finally to remove excess SiO2 from
the surface by CMP for planarization. As the width of STI region varies

Fig. 50.2 Illustration of STI isolation structure in CMOS process

940 H. Wu et al.

significantly, there are challenges for CMP planarization; this leads to add smaller
“dummy” STI trenches in large isolation region for optimizing the uniformity of
CMP planarization. Additionally, the bottom corner, sidewall slope angle, and
depth of Si trench will influence the device characteristics (e.g., leakage current,
breakdown voltage, etc.). As the clock speed of IC increases to RF or even
microwave band, the requirements for suppressing the noise and interference
become increasingly more stringent. In some applications, STI may not meet the
requirements, there are needs for additional deep trench isolation (DTI) or air-gap
isolation methods.

Channel Process

The most direct way to adjust the threshold voltage (Vt) of Metal Oxide Semicon-
ductor Field Effect Transistors (MOSFETs) is to implant ions into the channel areas
of nMOS and pMOS selectively, so that the Vt’s can reach the target values,
respectively. In addition, the Vt of MOSFET will also be affected by the high energy
ion implantation in the channel region for punch-through suppression between
Source/Drain as well as the lightly doped drain (LDD) implant with large angle tilt
ion implantation to reduce the short channel effect. The process parameters for twin-
well formation also affect Vt to a certain extent.
Channel technology is one of the core technologies for achieving stable char-
acteristics of MOSFET, such as Vt, short channel effect (SCE), noise, and punch-
through. With the scaling of device, there are many factors affecting Vt (e.g.,
uniformity of gate dielectric thickness, variations of gate length and width, fluctu-
ations in channel doping, the depletion effect and doping fluctuation in poly-Si
gate, the width of side-wall spacer, and the LDD extension of Source/Drain). For
instance, in order to improve the short channel effect, spacer and LDD process
were introduced in the 1980s. In order to prevent the device punch through
between Source/Drain, the large tilt angle ion implantation (with multiple rota-
tions) from the side of the gate is used in addition to ion implantation at channel
area. Next, the SiON and high-k gate dielectrics are introduced to solve the
deterioration of gate leakage by the thinning of gate oxide. Therefore, the channel
technology is no longer confined to ion implantation into the channel area. The
SiGe selective epitaxial deposition at Source/Drain can induce compressive stress
along the channel with higher hole mobility in p-MOS and is a key channel
engineering at 40 nm CMOS node and beyond.
As SOC is increasingly important for artificial intelligence (AI) and Internet-of-
things (IoT) era, MOSFETs in ICs are separately optimized for operation at different
voltages and Vt. The device leakage current and noise issues are more complicated to
be improved and random factors increase sharply with scaled voltage and Vt; all
these may result in severe challenges in channel engineering.
50 Module Processes 941

Polysilicon Gate

The formation of polysilicon (polycrystalline, or poly-Si) gate is one of the most

critical steps in IC technology, because it includes the thermal growth of the thinnest
gate oxide (dry and/or wet oxygen), advanced lithography, and dry etching for
patterning poly-Si gate, and precise control of spacer processes. Poly-Si gate struc-
ture is usually the smallest physical critical dimension (CD) in the technology node
and is the key to the formation of transistors. The common process flow of poly-Si
gate is the following: (1) firstly, grow gate oxide SiO2 film with thickness 1 ~ 10 nm
(Note: There are MOSFETs working at different voltages; thus, multiple thickness of
gate oxide is to be formed by using multiple oxidation steps.), and (2) the chemical
vapor deposition (CVD) and doping (in situ, diffusion or ion implant) of poly-Si, and
(3) finally pattern poly-Si gate by lithography and dry etch.
The lithography tool used for patterning the poly-Si gate is the most advanced and
expensive equipment in the technology node. It uses UV light source for exposure
with wavelength ranges from g-line (436 nm), i-line (365 nm), to Deep Ultra Violet
(DUV) (248 and 193 nm), and 193 nm immersion type. Optical proximity correction
(OPC) technique and phase-shift-mask (PSM) technology are used in mask-making.
In the lithography process, anti-reflective coating (ARC), hard photoresist
(PR) technology, and multiple exposure technology are used. Poly-Si gate is etched
by the most sophisticated etching equipment and technology, usually using NF3,
SF6, HBr, Cl2, and other gases, for high selectivity with respect to SiO2. Poly-Si gate
inspection technology is also the most sophisticated for accurately detecting the line
width and profile of poly-Si gate after lithography and etching. In order to solve the
poly-Si gate depletion effect and the high interface density issue, the high-k metal-
gate (HKMG) process is the mainstream in the advanced IC process at 45 nm node
and beyond; this appears to be lowering the importance of poly-Si gate technology.
However, the poly-Si gate process is still dominating at older nodes and is regarded
as one of the key corner stones in IC technology.

High-k Metal Gate

As the scaling of the transistor continues, the gate oxide thickness is required to
reduce in order to maintain enough gate capacitance. However, when the physical
thickness of gate oxide is reduced to lower than 1.5 nm, the direct tunneling leakage
current increases exponentially and the device cannot work properly. The introduc-
tion of gate dielectric of HfO2 with high relative dielectric constant (as denoted by
Greece Alphabet κ or εr, and usually by k for convenience) in the range of 24–40 can
result in larger physical thickness than SiO2 (k ¼ 3.9) to suppress the direct tunneling
current through the gate and it still can scale the equivalent oxide thickness (EOT)
continually for advanced CMOS nodes. The alloys or compound layers of TaN, TiN,
TiAl, and W are used to form metal gate stack for replacing the doped poly-Si gate
electrode. The metal layers can adjust the work function (for Vt adjustment),
942 H. Wu et al.

lowering the resistivity, eliminating the poly-Si depletion effect, and providing good
contact between high-k dielectric and metal gate stack.
Now, high-k metal-gate (HKMG) technology is widely used at 28 nm node and
beyond with greatly improved performance and reduced leakage current at the same
power consumption. For a long time in the past, gate SiO2 is grown at high
temperature by dry or wet thermal oxidation of Si, then nitrogen (N) is added to
form SiON gate dielectric during the oxidation for higher dielectric constant than
SiO2. The decrease of poly-Si gate electrode thickness results in not only higher
poly-Si resistance, but also increased device delay and gate depletion effect. Under
this background, the HKMG process is used and adopted from 28 nm node as the
mainstream process with much enhanced performance but also more complexity in
process.
As the device structure of HKMG is very different from that of poly-Si/SiO2 gate,
the process flow architecture of the device has fundamental changes, so that a large
number of IP cores need to be redesigned. During the initial development phase of
HKMG process, there are 2 process integration schemes, that is, gate-first and gate-
last, respectively. The gate-first process is relatively simple but the Vt of pMOS is
difficult to control; and the gate-last process is more complicated, but it can modify
the work function of gate material for effectively tuning the Vt and even implement
the stress Si engineering for improving the hole mobility in channel area of pMOS.
Gate-last process gradually becomes the dominating mainstream scheme for both
high performance and low power consumption (e.g., cell phone application proces-
sor and baseband chip, etc.).

Silicidation

In order to reduce the contact resistance and series resistance of Source/Drain in

MOSFET, silicide process is introduced in CMOS technology. The industry has
successfully integrated WSi2, TiSi2, CoSi2, and NiSi as process modules. In earlier
W-silicide process, the W-silicide was deposited on the surface of polycrystalline
silicon by CVD technology with reaction gases WF6 (as W source) and Si2H6 (as Si
source). After W-silicide process, there are mainly three kinds of silicide process in
CMOS manufacturing [2].

1. Ti-silicide process: It is widely used in the fabrication of IC at 0.25um node and

earlier. The silicide process is simple and stable at high temperature in CMOS
flow. The main process steps include deposition of Ti metal by Physical Vapor
Deposition (PVD) sputtering and followed by 2-stage annealing. The first
annealing is performed by furnace or RTA in 600–700  C to form a high
resistance C49 mesophase; then the second annealing is performed at slightly
higher temperature in 800–900  C leading to transition into a low resistance C54
phase (from C49 phase). When the linewidth of Ti-silicide on Si is narrower, the
Ti-silicide resistance increases due to insufficient transformation. To achieve
sufficient phase transformation, the second annealing needs to be at higher
50 Module Processes 943

temperature and longer time substantially; however, the heat budget shall not be
too high in order to avoid leakage and degradation of MOSFET.
2. Co-silicide process: The annealing temperature for Co-silicide formation is sig-
nificantly lower than Ti-silicide (e.g., 700  C for the second annealing). Thus, the
lower thermal budget of Co-silicide is preferred (for replacing Ti-silicide) at
0.25 μm (and beyond) until 65/45 nm nodes, where the linewidth effect appears
again. Furthermore, shallower junction depth required for advanced CMOS (e.g.,
65/45 nm nodes and beyond) also sets a limit of thermal budget due to the Si
consumption during Co-silicide process (i.e., Co-silicide process consuming
more Si than Ti-silicide). Thus, the industry was looking for an alternative
again (e.g., Ni-silicide) with lower thermal budget for advanced CMOS node of
45 nm and beyond.
3. Ni-silicide process: For advanced CMOS process at 65/45 nm nodes and beyond,
the industry has the developed Ni-silicide (NiSi) process with lower thermal
budget and less Si consumption as a superior replacement of Co-silicide. The
annealing for Ni-silicide formation can be one or two steps at lower temperature
(usually <600  C) and shorter time than Co-silicide process by using Spike
Annealing (SA) or Laser Anneal (LA) annealing with fast temperature ramp-up
and down, short time at peak temperature, etc. This effectively reduces the
diffusion of dopants and/or atoms for suppressing adverse effects on ultra-
shallow junctions and channel doping profile in MOSFET. In addition to the
above 3 silicide processes, a low temperature thin Ti-silicide process is developed
at 14 nm node and beyond. This process can significantly reduce the contact
resistance at Source/Drain and leakage. This is actually a thin Ti-Si compound as
different from the traditional TiSi2. Its resistivity is not lower than that of NiSi, but
its contact resistance can be effectively reduced by changing the Schottky barrier
in contact with Si.

Contact Process

The contact process of ICs is the process used to connect the active devices and
passive elements manufactured in the front-end-of-line (FEOL) to the first intercon-
nect metal of the back-end-of-line (BEOL). The contact process integrates several
process steps including: (1) Deposit CVD Si3N4 (as etch-stop layer) and SiO2
(as interlayer dielectric (ILD)) by CVD and then planarize by CMP. (2) Define
contact pattern through lithography process, then open contact holes by etching SiO2
or Si3N4, and finally perform thermal reflow for forming a smooth profile of contact.
(3) Perform PVD of barrier layer (e.g., Ti/TiN, Ta/TaN) and then fill contact by CVD
of W and finally CMP to form W-plug. (4) Perform anneal at ~400  C for forming
good Ohm contact between metal and Si substrate.
Contact process is one of the most difficult and key processes in IC manufacturing
technology. The size of contact hole is one of the smallest critical dimensions
(CD) to determine the chip area. Considering that the contact holes are landing on
either the Source/Drain Si active areas or on the poly-Si gate, the depth of the contact
944 H. Wu et al.

holes is different. As the shallower contacts are etched faster than the deeper
contacts, there is a need to add a layer of “etch-stop” (usually Si3N4 for high
selectivity vs SiO2), so that contact etching can be stopped at the Si-nitride and
continue with a slight over etch to remove the Si-nitride, interface Si-oxide, and a
small Si loss (<100 nm) without damaging the underlying material. Usually, the
gases of dry etching contact holes are mixtures of CF4, C2F3, C3F8, NF3, and He. The
profile of the contacts also needs attention. The shallower and deeper contacts have
similar size with smooth surface and slightly larger upper openings (like a bell) for
better uniformity of barrier layer deposition to form contact plug.
In order to achieve good openings and smooth shape of contact holes, phosphorus
(P) and boron (B) are added into SiO2 layer to form the B-P-Si glass (BPSG) or P-Si
glass (PSG) formed by thermal annealing reflow. After W deposition, the final CMP
or dry etching tungsten (W) metal is performed to remove the W remaining on the
surface of SiO2 to form W-plug inside contact holes.

Al/Cu Interconnect and Dual Damascene

Aluminum (Al) and Copper (Cu) interconnect technology serves for connecting
transistors and passive devices formed at FEOL into ICs and carry signals to operate.
The surrounding dielectric layers serve as mechanical supporting structure and
electrical isolation between adjacent metal lines and inter metal layers. The metal
contacts (also known as diffusion contacts) refer to the connection between the
Source/Drain and the first metal layer (M1); the Via refers to the connection between
adjacent metal layers. Contacts are usually filled with W, and Via’s are filled with
metal (e.g., Cu or Al or Co) with liners (e.g., Ta/TaN). Multiple layers of metal
interconnection are formed by repeating the formation of metal lines and Via’s with
only the thickness, critical dimension (CD), and pitch variation (usually progres-
sively larger rules). The main metal materials include Al, Al-Si (Si doped Al), and
Al-Cu alloys. The Al interconnect technology is dominating at older nodes (e.g.,
0.18 μm node and earlier); and the Cu interconnect technology is the main stream
since 0.13 μm node and beyond.
The Cu interconnect technology replaced Al interconnect mainly due to Cu’s
higher conductivity (than Al) leading to thinner metal layer (less topology), less IR
drop (less energy loss), less RC delay (for higher speed), and more resistant to
electro-migration (superior reliability). The ILD is also progressed to low-k material
for lower coupling capacitance between metal lines. Cu interconnect technology was
successfully implemented for production by Intel at 0.13 μm node.
As the dry etching of Cu is difficult due to the non-volatile by-product materials,
Cu interconnect is formed by dual damascenes method. As illustrated in Fig. 50.3,
the flow started by patterning Via and trench in the dielectric material first, then
deposit barrier layers (e.g., Ta/TaN to block Cu diffusion into ILD) and Cu seeding
layer by PVD, and followed by Cu filling into Via and trench through electrical
plating method (e.g., Electrochemical Deposition (ECD)). Finally, extra Cu is
removed by CMP technology.
50 Module Processes 945

Fig. 50.3 Illustration of dual damascenes process flow (Via fist)

946 H. Wu et al.

Double Patterning Technology (DPT)

Double patterning (DP) is also referred to as double exposure. The idea is to divide
the data of the same mask layer into two masks and patterning separately. With the
development of IC manufacturing, the lithography technology is facing enormous
challenges and the layout design is increasingly more stringent, for example, lines on
the layout arranged in one direction for better resolution. Nevertheless, the 193 nm
single exposure immersion scanner can achieve resolution limit of line/space pitch
along the same direction about 80 nm. If the line/space pitch is less than 80 nm, then
the double or multiple patterning techniques must be adopted unless more advanced
lithography tools (e.g., Extreme Ultra Violet (EUV) or e-beam) are used. Currently,
there are two most common dual patterning techniques in industry, that is, self-
aligned double patterning (SADP) and litho-etch-litho-etch (LELE). The SADP
technique based on 193 nm immersion lithography scanner starts to form mandrel
with larger pitches, then form side-wall spacers as new lines with 1/2 of the earlier
pitch. This technique is more suitable for layout layers with regular line type pattern,
such as Fin Field-Effect Transistor (FinFET) process or metal lines. By similar
techniques, SADP technique can be further developed into self-aligned quadruple
patterning (SAQP) or self-aligned multiple patterning (SAMP) technology. SADP
technique greatly reduces the requirements of lithography capability and no overlay
issues, but it posts layout limitation to lines only. For complex distribution of small
size and high-density layout patterns, the LELE technique is more suitable. As

Fig. 50.4 Illustration of LELE process flow

50 Module Processes 947

illustrated in Fig. 50.4, the LELE dual patterning technique includes the dividing of
layout pattern into two patterns separately (based on certain algorithms) with each
pattern within the limit of lithography capability. Then the LELE process is simply to
perform the first mask exposure and etching to transfer the pattern to a hard mask
layer on wafer, then expose the second mask (with the PR pattern on wafer) and
perform the second etching (using the combined PR pattern as well as the hard mask
pattern) as etching barrier, in this way, the combined two patterns are transferred to
wafer. The LELE dual patterning technique is slightly different in implementation
according to different applications, but no matter what method is adopted, the key is
to ensure that the final patterns are as close as possible to designed layout [3]. The
technical difficulties of LELE mode are in the separation and combining of the two
partial patterns, align/overlay of two exposures, and pattern quality degradation due
to multiple pattern transfers. In addition to the above two dual patterning techniques,
there are also ways to expose the same mask twice and then etch it once, but this
method is seldom used in industry due to high requirements on PR.
Strictly speaking, 32/28 nm nodes are the last generation of single exposure
lithography technology. Although the line end-cut technique is used in gate pattern-
ing as a quasi-dual patterning technique, the critical layers at 20/14 nm nodes start to
adopt dual patterning techniques, including SADP and LELE. At 7 nm node, SAQP
and LE technology may be used many times. These methods actually break through
the limitation and extend the capability of DUV (193 nm) lithography by dividing
one layer of pattern into multiple partial patterns.
However, process complexity increases and negatively impacts on yield. As the
mask and lithography tools are both the most expensive materials and equipment in
IC manufacturing, the dual or multiple patterning techniques significantly increase
manufacturing costs. With the maturing of EUV lithography technology recently, the
EUV lithography is used for manufacturing at 7 nm node in 2019 and is also
expected at future nodes.

Strained Silicon (Compressive/Tensile Stresses)

Strained silicon technology refers to the engineering of stress in Si as induced by

lattice mismatch or difference in thermal expansion of materials in CMOS process.
Strained Si can be either compressive (Si atoms spacing reduced) or tensile (Si atoms
spacing expanded). The compressive strain is induced by compressive stress, and the
tensile strain is induced by tensile stress. In advanced IC technology, the strained Si
technology is used to enhance the electron/hole mobility by tensile/compressive
stresses, respectively, and in turn to enhance the driving currents of Complementary
Metal Oxide Semiconductor Field Effect Transistor (CMOSFET). Due to the Si
lattice structure, the band structure of (tensile/compressively) strained Si leads to
reduced effective mass and scattering probability, and therefore leads to enhanced
mobility of electron/hole, respectively. This is the mechanism that the strained Si can
improve device driving current.
948 H. Wu et al.

Both global and local Si strain engineering are useful for enhancement of
MOSFET performance [3]. The global strain engineering refers to the relatively
uniform stress in the whole thin layer material by the thermal coefficient or lattice
mismatch with respect to the Si wafer substrate for inducing stress in the channel.
Local strain engineering refers to the stress locally at the device surface for inducing
stress in the channel of MOSFET. The effect of local strain is closely related to
device structure and stress proximity (i.e., the distance between local stress region
and device channel). Epitaxial growth of Si thin layers on SiGe substrates is a
common global strain technology. Larger SiGe lattice constants (vs Si lattice) results
in Si thin layers expanded (i.e., tensile strain) than the un-strained values, thus
forming tensile stress in the Si layer. The magnitude of stress is mainly determined
by the thickness of the Si thin layer and the content of Ge in the SiGe substrates.
Unlike the global strain, the local strain is mainly achieved by introducing local
stress in the MOSFET, such as selective epitaxy of Ge and Si in the Source/Drain
region of the device. The stress generated is not only related to the concentration of
Ge, but also closely related to the structure of the device (especially the proximity of
the epitaxy layer to the channel). Finally, the strain engineering is also affected by the
spacer, shallow trench isolation (STI), silicide, or ILD and metal layers at BEOL, so
that the mobility enhancement of electrons and holes are often degraded after the full
CMOS process.
According to the direction of strain, strain can also be biaxial, (i.e., relatively
consistent stress in X and Y directions) or uniaxial (i.e., stress mainly along a single
direction). It has been demonstrated [4] that electron mobility can be enhanced by
tensile stress along the channel and hole mobility is enhanced by compressive stress
along the channel. After 90 nm nodes, Si strain engineering is implemented as
mainstream in MOSFET devices, for example, epitaxy growth SiGe at Source/
Drain for pMOS and deposition of tensile stress layer for nMOS. Selective growth
of SiGe (with in situ doped Boron) at the Source/Drain of pMOS can induce
compressive stress along the channel of pMOS by the larger lattice constant of
SiGe than Si. A dielectric layer (e.g., Si-nitride) with tensile stress can be selectively
deposited over n-MOS area, also as the contact etch-stop layer (CESL), and can
induce tensile stress along channel by thermal annealing after deposition; this is also
referred to as stress memory technology (SMT).
Similarly, the strain layer with compressive stress can also induce compressive
stress for pMOS, however, this effect for hole mobility enhancement is much less
than SiGe epi growth method for pMOS; thus, the most commonly used stressed
layer technology is the tensile stress layer for nMOS devices. Certainly, Dual-Stress-
Liner (DSL) can be introduced to deposit compressive and tensile stress on pMOS
and nMOS, respectively, but its integration is more complicated and is seldom used
in practical process. Similarly, for nMOS devices, the tensile strain along the channel
can also be induced by epi growth of SiC or Si:P (in situ Phosphorus doped) in the
Source/Drain, but its effect is small compared with the stress layer technique or SMT
and also seldom used in practice.
50 Module Processes 949

Embedded Source and Drain Selective Epitaxy

Embedded Source/Drain selective epitaxy refers to the selective epitaxy of an in situ

doped single crystal layer (e.g., in situ doped Si or SiGe) in the Source/Drain region
of MOS transistors. This is also an example of strain engineering. Because the
performance of MOSFETs can be significantly improved by using embedded
Source/Drain technology, including the increase of drive current and switching
speed, it is widely used in 65 nm technology nodes and beyond. Currently, the
embedded Source/Drain process for pMOS transistors generally refers to the epitaxy
growth of p-doped single crystal SiGe; while for nMOS transistors, it generally
refers to the epitaxy growth of n-doped single crystal Si.
Generally, selective epitaxy is performed at lower temperature, compared with
epitaxy Si wafer process. One way to reduce the epitaxy growth temperature is to
reduce the pressure in the process. At present, the vacuum epitaxy growth is operated
under 40–100 Torr, and the process temperature is about 1000  C. When the process
pressure is further reduced to 0.01–0.02 Torr, the operation temperature can be
reduced to 750–800  C. The stress generated is not only related to the process
parameters and Ge concentration, but also to the different relative positions between
Ge and Si and the channel. Source/Drain selective epitaxy generally uses Si-nitride
or Si-oxide as hard mask layer. Etching gas is used to inhibit the epitaxy growth on
the masking layer, and growth only in the exposed Source/Drain region.
The Source/Drain selective epitaxy process generally consists of four steps:
pre-cleaning before epitaxy, in situ cleaning (e.g., SiCoNi), in situ hydrogen baking,
and selective epitaxy growth. Pre-epitaxy cleaning is usually performed in acid
tanks, using hydrofluoric acid (HF) and RCA cleans to remove surface oxide layer
and impurities. SiCoNi cleaning is also used to remove the natural oxide layer, and in
situ hydrogen baking further reduces the content of oxygen and carbon atoms on the
surface of Si wafers. Selective epitaxy growth is simply chemical vapor epitaxy by
using chemical reaction gas, for example, Si sources (such as SiH4, SiH2Cl2), Ge
source (GeH4), etching gases (HCl, Cl2), carrier gases (H2, N2), chemical reactions
on the wafer surface.
For the embedded SiGe process of pMOS devices, the growth of SiGe (larger
lattice constant than Si) in Source/Drain can induce uniaxial compressive stress
along the channel with enhanced hole mobility. In the embedded SiGe epitaxy
process, the content of Ge and doping concentration should be optimized for
achieving higher device performance as well as minimum defects, for example,
non-uniform growth, lattice defects (dislocation, stacking faults), etc. In early planar
MOSFET device, embedded SiGe epitaxy preferred to use a “sigma” shaped struc-
ture, while with the emergence of 3D device of FinFET, SiGe epitaxy preferred to
use a “U” shaped Source/Drain.
For nMOS devices, Source/Drain selective epitaxy includes doped Si epitaxy and
doped silicon carbide (SiC) epitaxy in Source/Drain. The epitaxy growth of doped Si
can elevate the surface of the Source/Drain, thus reducing parasitic resistance and
defects by the subsequent silicide process. In order to further improve the perfor-
mance of nMOS, the Source/Drain epitaxy SiC technology has been proposed. As
950 H. Wu et al.

the lattice constant of SiC is smaller than Si, uniaxial tensile strain can be induced in
the channel of nMOS for enhancing electron mobility. However, the Source/Drain
epitaxy of SiC process suffers excessive defects and stress relaxation, so the tech-
nology needs further studies.

References
1. G. Xudong, Foundation of Silicon Integrated Circuits Process (Beijing University Publishing
House, Beijing, 2013)
2. Z. Fang, J. Tang, Z. Xu, Development and evolution of metal Silicides in integrated circuits.
Appl. IC 9, 51–52 (2008)
3. H. Xiao, Introduction to Semiconductor Manufacturing Technology (Prentice Hall, Columbus,
2001)
4. J. Wang, Strained silicon-a technology to extend Moore’s law. Microelectronics 38(1),
50–56 (2008)
Integration
51
Min-Hwa Chi

Contents
Frontend-of-Line (FEOL) Integration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Shallow Trench Isolation (STI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Dual-Well and Deep n-Well Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Gate-Oxide and Poly-Gate Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Off-Set Spacer and n/p LDD Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Main Spacer and n+/p+ Source/Drain Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
SiGe Epi for p-MOS S/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Stress Memorization (SMT) for n-MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Middle-of-Line (MOL) Integration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Self-Aligned Silicide Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
High-k Dielectric and Replacement Gate (RMG) Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
Contact and W-Plug Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Back-End-of-Line (BEOL) Integration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Metal-1 Formation (Single Damascene) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Dual Damascene and Multi-interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
CMOS Integration Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
CMOS Integration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Planar CMOS Integration Flow with HKMG [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
FinFET Integration [5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Non-volatile Memory (NVM) Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Floating-Gate Flash Memory Integration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Phase Change RAM (PCRAM) Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Resistive RAM (RRAM) Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Magnetic RAM (MRAM) Integration [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
3D NAND Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Dynamic RAM (DRAM) Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Design-Technology Co-optimization (DTCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977

M.-H. Chi (*)

GTA Semiconductor Co., Ltd., Shanghai, China
e-mail: minghua_ji@gtasemi.com.cn

© Publishing House of Electronics Industry 2024 951

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_51
952 M.-H. Chi

Abstract
A complete silicon-based CMOS integrated circuit process flow usually includes
hundreds to thousands “unit process.” Further, several basic unit process steps
can be combined as a “module process” for a well-defined function as described
in Chaps. 5 and 6. Similarly, these modules can be further grouped into frontend-
of-line (FEOL), middle-of-line (MOL), and backend-of-line (BEOL), to form a
complete CMOS integration process flow as a platform. Furthermore, additional
functional modules, e.g., NVM, DRAM, 3DNAND, CIS, etc., can be inserted
into the platform for various applications of non-volatile memory, DRAM, RF,
BiCMOS, system-on-chip, etc.

Keywords
FEOL · MOL · BEOL · CMOS integration · NVM · 3D NAND · DRAM · DTCO

Frontend-of-Line (FEOL) Integration Flow

Shallow Trench Isolation (STI)

The STI formation is illustrated in Fig. 51.1. The process starts with a thermal
oxidation of the Si substrate (referred to as “initial-ox”) and then a thin layer of
Si-nitride (~100 nm) as deposited by LPCVD method. Then, the photo-lithography
masking steps are performed by spin coating photo-resist (PR) and UV exposure
(using a mask referred to as “AA”) with active-area protected from UV
(i.e., isolation areas exposed to UV); then after PR developed, the exposed nitride
and initial oxide are sequentially removed by plasma dry etching methods. Then,
after PR removal with the exposed nitride surface serving as hard-mask, Si plasma
etching is performed to form deep enough trenches in the Si substrate (e.g., depth of
300 nm–500 nm for electrical isolation at 2.5 V–3.3 V operations). Certainly, the
masking materials (i.e., PR as a “soft mask” and nitride as “hard-mask”) shall be
thick enough to survive the sequential plasma etching of nitride, oxide, and Si. After
Si trench formed, an oxidation is performed to form a “liner” of the trench and
followed by CVD oxide fill-in the trenches (with thickness slightly more than the
depth of trenches) and rapid-thermal-annealing (RTA) to harden the CVD oxide.
Then, a chemical-mechanical-polishing (CMP) is performed to planarize the surface
and followed by the removal of remaining nitride and oxide. Then, a fresh thin
thermal oxide (referred to as sacrificial oxide or Sac-ox) is grown on surface for
reducing defects. Then, CVD oxide is performed to fill-in the trench. The high-
density plasma (HDP) CVD oxide has greater capability of gap-filling into trenches
than prior LPCVD oxide; thus it is popularly used in modern CMOS (e.g., 0.13 μm
node or newer). The new flowable CVD (FCVD) has greater gap-filling capability
than HDPCVD, as widely used at 14 nm node and beyond.
51 Integration 953

Fig. 51.1 Illustration of sallow-trench-isolation (STI) formation

Dual-Well and Deep n-Well Formation

The formation of n-well and p-well (i.e., dual-well) is illustrated in Fig. 51.2 with
masking steps and implants through the thin SAC-ox. The sequence of n-well or
p-well formation has little impact to the final performance of n-type or p-type
transistors. The p-MOS transistors are formed within n-wells; and n-MOS transistors
are formed with in p-wells. The n-well and p-well implants typically have multiple
passes (with various energy/dose and species) for not only forming the wells and also
for Vt adjustment and punch through prevention of p-MOS and n-MOS transistors,
respectively. The RTA after n-well implant is used to activate dopants and drive
dopants deeper. Similarly, a deep n-well (DNW) can be formed on Si-substrate by
using a mask exposing deep n-well areas for implanting n-type dopants and followed
by drive-in (not illustrated in Fig. 51.2). DNW can be used to isolate p-wells inside
and outside the deep-well.

Gate-Oxide and Poly-Gate Formation

The dual gate-oxide and hard-mask gate-stack scheme is illustrated in Fig. 51.3.
After the removal of SAC-ox by wet clean, the first gate oxide is thermally grown
954 M.-H. Chi

Fig. 51.2 Illustration of dual-well formation

(for high quality and low level of traps inside). Then a mask for opening the core area
is performed (by using the mask “Core”), and followed by wet HF dip; then the
second gate-ox (Gate-ox-2) is thermally grown for transistors in the core area. Note
that, the IO area (i.e., non-“Core” area) has experienced twice of oxidation, thus the
gate oxide is thicker as desired for IO transistors. After gate-ox is readily grown on
both the core and IO transistor areas, layers of poly-Si and hard-mask (thin SiON and
PECVD oxide) are deposited. After the deposition of gate-stack, the hard-mask layer
is patterned (by using the mask “poly” and plasma etching oxide and SiON with high
selectivity to poly-Si surface), and then PR removed, and poly-Si is etched in
sequence using the SiON and oxide as hard-mask. After a removal of SiON, a
re-oxidation (~3 nm) of poly gate-stack edge is performed by furnace or rapid-
thermal-oxidation (RTO) methods for annealing any damage or defects in oxide
(as resulted from plasma etching of gate-stack). As the gate pattern determines the
channel length of transistors with the smallest critical dimension (CD), thus the hard-
mask scheme is needed for patterning the gate-stack toward better resolution and
uniformity than the simple photo-resist (PR) patterning scheme.
51 Integration 955

Fig. 51.3 Illustration of gate-ox and gate-stack formation

Off-Set Spacer and n/p LDD Formation

The formation of off-set spacer and n/p LDD is illustrated in Fig. 51.4. A thin layer
(typically ~2 nm) of SiN or Si-oxynitride is deposited and then etched back to form a
thin spacer on the edge. The remaining oxide on surface is ~2 nm after the off-set
spacer etch-back, and it is important to always keep some remaining oxide on Si
surface for protection at every step in later process. The off-set spacer is used to
space out the lateral diffusion distance by n/p LDD implants (for reducing short-
channel effects); it is an optional step for 90 nm or older CMOS nodes, but it is
needed at 45 nm node and beyond. Then, the lightly doped-drain (LDD) implants for
n-channel and p-channel MOS selectively. After completion of implants, a spike
anneal is performed for removing defects and activation of LDD implanted dopants.
The sequence of n/p LDD implantation (dose/energy) and the spike anneal or RTA
(with time and temperature profile) may impact transistor property significantly.

Main Spacer and n+/p+ Source/Drain Formation

The next is the formation of the main spacers and n+/p+source/drain (S/D) formation
as illustrated in Fig. 51.5. Firstly, composite layers of Teos-oxide (CVD oxide using
956 M.-H. Chi

Fig. 51.4 Illustration of offset spacer and n/p LDD formation

Teos precursor) and Si-nitride are deposited, and plasma etch-back of Si-nitride and
Teos-oxide is performed to form composite main spacers. Then, perform n+ and p+
source/drain implant to n-MOS and p-MOS areas, respectively (using masking
51 Integration 957

Fig. 51.5 Illustration of main spacers and n+/p+ source/drain formation

steps), and followed by RTA or spike anneal to activate dopants and remove defects.
The shape and materials of spacers can minimize the degradation of hot carrier in
transistors. The energy/dose determines the depth of the S/D junction and will also
impact the transistors’ performance, e.g., junction leakage, resistance, and break-
down voltage.
958 M.-H. Chi

SiGe Epi for p-MOS S/D

Since 32 nm CMOS node, new process modules of high-k and metal gate (HKMG)
[1] and strained Si S/D are implemented to reduce the gate leakage and enhance the
hole mobility in p-MOS channel as illustrated in Fig. 51.6. The process flow is
described here briefly. Firstly, after the formation of off-set spacer and n/p LDD,
perform selective patterning (using masking steps) to open p-MOS area; then,
perform dry etching to form cavity (with depth of ~30–100 nm) and followed by
anisotropic wet etching to form “diamond shape cavity” at p þ S/D area. Then,
perform SiGe epi growth with in-situ B doping (or implant B and followed by RTA).
The diamond tip of the SiGe p þ S/D can induce compressive stress along the
channel direction and enhance hole mobility in p-MOS channel significantly.

Stress Memorization (SMT) for n-MOS

At 32 nm or earlier nodes, n-MOS electron mobility can be enhanced by stress

memorization technique (SMT) from combined effects of poly gate deformation
(poly-gate SMT) and S/D recrystallization (S/D SMT). However, at 28 nm node and
beyond, the advanced HKMG technology adversely eliminated the gate induced
SMT for n-MOS, instead only the S/D SMT effect is utilized to enhance n-MOS
performance. The n-S/D SMT formation is illustrated in Fig. 51.7. Firstly, n-S/D
surface is selectively implanted by Ge or Si for forming amorphous surface; then, a
thin layer of tensile liner (e.g., Si-nitride) is deposited and followed by RTA. The
surface of n-S/D area is recrystallized, and tensile stress is induced along the channel
with electron mobility enhanced significantly. Finally, the liner can be removed and
the rest of process steps continue.

Fig. 51.6 Evolution of p+ source/drain [2]

51 Integration 959

Fig. 51.7 Illustration of SMT formation at n-S/D [3]

Fig. 51.8 Illustration of self-aligned silicide formation on S/D and poly gate surface

Middle-of-Line (MOL) Integration Flow

Self-Aligned Silicide Formation

The conventional CMOS (e.g., 32 nm or earlier) technology is based on process flow

with poly-gate formation earlier than S/D (as referred to as “gate-first” flow); then
silicide is formed on poly-gate and S/D surface in self-aligned manner. The self-
aligned silicide flow is illustrated in Fig. 51.8. After poly-gate and S/D formation, a
wet clean or dry etching to remove oxide on AA area and poly gate surface, a thin
layer (10 nm–20 nm) of metal (Co or Ni) is sputtered, and followed by the first RTA
(400–550  C), the metal in contact with Si is reacted to form metal silicide. Then, the
remaining un-reacted metal on oxide is removed by wet SC1 solution and followed
960 M.-H. Chi

by a second RTA (~700  C). Thus, metal-silicide is formed on AA and poly gate
areas in a self-aligned manner, and it is referred to as self-aligned silicide or
“salicide” process. Then, thin layer SiON and PSG deposition is performed and
followed by CMP planarization. A layer of CVD oxide (Teos-oxide) is deposited to
seal the PSG and referred to as interlayer dielectric (ILD).

High-k Dielectric and Replacement Gate (RMG) Formation

The new high-k dielectric (Hf-oxide based) and replacement metal gate (RMG)
technology was successfully developed by Intel (~2007) and implemented at 45 nm
CMOS node. The high-k gate dielectric is based on Hf-oxide (e.g., HfO2, HfSiOx,
HfSiON, etc.) and can significantly reduce leakage current through the gate dielec-
tric. The metal gate (e.g., multiple layers of TiN, TaN, TiAl, Al, W, etc.) can reduce
gate resistance significantly (than poly-gate) and enhance signal speed. As the
Hf-oxide dielectric is recrystallized by S/D anneal and leads to larger leakage
current, thus, high-k dielectric is better formed after S/D formation by removing
the initial poly gate (serving as “sacrificial gate”) and replaced by metal layers as
illustrated in Fig. 51.9. This CMOS flow is often referred to as “gate-last” or “high-k
metal-gate” (HKMG) flow; and it is dominating process features at 32/28 nm nodes
and beyond.

Fig. 51.9 Illustration of high-k and replacement metal gate (HKMG) flow
51 Integration 961

Contact and W-Plug Formation

The masking step to open contacts is then performed (with mask “CT”) and followed
by plasma etching of PSG and SiN on contacts. Then, Ti and TiN is sputtered, and W
(~3 kA) is deposited by CVD method and RTA annealed. After polishing the
W-surface (by CMP) until Teos-oxide surface exposed, the W-plug is formed inside
the contact as illustrated in Fig. 51.10. The Ti layer is important to minimize the
contact resistance and TiN on sidewall coverage is needed to maintain the integrity
of the W filling process into contact (i.e., no void) and prevent W diffusion into Si or
SiO2.

Back-End-of-Line (BEOL) Integration Flow

Metal-1 Formation (Single Damascene)

Then inter-metal dielectric (IMD) layers (e.g., SiCN ~30 nm, C-containing low-k
PECVD oxide ~200 nm, and Teos-oxide 25 nm) are deposited and followed by
patterning (with mask “Metal-1”) and oxide etching. The IMD1 layers are mainly for
good sealing or capping for more porous low-k dielectrics. Then, Ta/TaN (barrier
layers) and Cu seeding layers are deposited and followed by Cu fill (by ECP method)
and CMP planarization. Metal-1 interconnection is formed, and this is single dam-
ascene technique as illustrated in Fig. 51.11.

Fig. 51.10 Illustration of contact and W-plug formation

962 M.-H. Chi

Fig. 51.11 Illustration of metal-1 formation by single damascene technique

Dual Damascene and Multi-interconnection

The formation of via-1 (V1) and metal-2 (M2) interconnection is performed by dual
damascene method. The dual damascene can be performed by either via-first or
trench-first flows. The via-first flow is illustrated here as in Fig. 51.12 with IMD2
layers (e.g., SiCN ~50 nm and C-containing low-k PECVD oxide (Black-Diamond)
~600 nm) deposited and V1 patterned (using mask “V1”) and etched. The multi-
layer IMD1 layers are mainly for good sealing or capping for porous low-k dielec-
trics. Then, BARC (bottom anti-reflection coating) is filled in via (for planarization)
and a layer of LTO (low temperature oxide) is deposited. Then, M2 is patterned
(using mask “M2”) and oxide is etched. After BARC removal and cleaning, Ta/TaN
(barrier layers) and Cu seeding layers are deposited and followed by Cu fill (by ECP
method) and CMP planarization, and then M2 interconnection is formed. This is dual
damascene method. Similarly, the trench-first flow performs M2 trench first and then
forms patterning V1 and etching oxide, then deposit Ta/TaN barrier layers and Cu
seeding, and followed by Cu fill and CMP planarization. By repeating the above
steps, multiple-interconnection levels can be achieved.
51 Integration 963

Fig. 51.12 Illustration of V1 and M2 formation by dual damascene technique

CMOS Integration Technology

CMOS Integration Flow

A typical cross-section of modern planar CMOS logic device structure (e.g.,

45 nm/28 nm nodes) is illustrated in Fig. 51.13. The substrate is typically p-type
silicon bulk or silicon-on-insulator (SOI) wafers with 200 mm (800 ) or 300 mm (1200 )
in diameter. There are multiple layers of Cu interconnection. The top two layers of
metal are thicker and often used for fabrication of passive components (inductors or
capacitors). The top Al layer is used for bonding pads for packaging process. The
insect shows more features of CMOS transistors with poly-silicon and silicided gate-
stack, gate dielectric (SiO2 or high-k dielectric), LDD (S/D extension), epi strained
S/D, etc. The main features of modern CMOS transistors at 28 nm node include
features of Co- or Ni-salicided poly gate-stack, nitrided SiO2 or high-k gate dielec-
tric, offset spacer, lightly doped drain (LDD) or shallow source/drain (S/D) exten-
sion junction, multi-layers (ONO) of main spacer, and Co- or Ni-silicided S/D deep
junction. The transistor for internal core logic circuits is typically operated at
0.9–1.1 V with channel length (~30–40 nm), thinner gate dielectric (~1.5–2 nm),
and shallower SD extension junction (15–20 nm). The transistors for IO circuit
(i.e., interfacing to circuits outside the chip) are typically operated at 1.5 V, 1.8 V or
964 M.-H. Chi

Fig. 51.13 Illustration of modern planar CMOS device structure (45 nm/28 nm nodes as an
example)

2.5 V with longer channel length (~100–200 nm), thicker gate dielectric (~3-6 nm),
and deeper SD extension junction (~25–30 nm) correspondingly. The smaller
operation voltage of core logic is for minimizing operating power. At 45/28 nm
CMOS nodes, there are features of strain engineering by applying stress along
transistor channel direction for mobility enhancement (e.g., tensile stress for elec-
trons in n-MOS and compressive for holes in p-MOS). At 28 nm CMOS node, epi
SiGe strained S/D (for p-MOS) and stress memorization effect (for n-MOS) are
standard features. At 20 nm CMOS node and beyond, new process modules of high-
k metal-gate (HKMG), dual strain S/D (for n-MOS) with SMT, as well as epi SiC or
Si:P (in situ P doped Si). At 16 nm/14 nm/10/7 nm nodes and beyond, the CMOS
transistors are all based on the non-planar FinFET structure.
A modern planar CMOS logic process flow is illustrated in Fig. 51.14 with
process parameters relevant to 28 nm node. Firstly, STI is formed (Step-1), then
followed by n-well (for pMOS) and p-well (for n-MOS) formation (Step-2) with
selective implanting dopants into wells respectively. Then, the gate oxide and gate-
stack layers are formed (Step-3). After the poly gate-stack is patterned and
re-oxidized, off-set spacer and LDD implant performed (Step-4) for n- and p-MOS
transistors. Then strained p þ S/D is formed with SiGe epi (Step-5); and n þ S/D is
formed with SMT (Step-6). Then silicide, ILD, contact, and W-plug are formed
(Step-7) and continue with BEOL flow to form M1 (Step-8) and Via-1/M2 (Step-9).
51 Integration 965

Fig. 51.14 Illustration of gate-first CMOS process flow with S/D stress engineering

By repeating the dual damascene steps, multiple interconnections in the “back-end-

of-line” (BEOL) are completed. Steps 1–6 are often referred to as the frontend-of-
line (FEOL) process, Step-7 as middle-end-of-line (MOL) process, and Steps 8–9 as
back-end-of-line (BEOL) process.

Planar CMOS Integration Flow with HKMG [4]

The high-k dielectric (Hf-oxide based) and replacement metal-gate (RMG) technol-
ogy (referred to as HKMG) was successfully developed by Intel (~2007) and
implemented at 45/32 nm CMOS node. To avoid recrystallization, the high-k
dielectric is better formed after S/D anneal in the RMG flow, thus referred to as
gate-last HKMG flow. The HfO2 based high-k gate dielectric can significantly
reduce leakage current through the gate dielectric; and the metal gate with multiple
layers of TiN, TaN, TiAl, Al, W, etc. can reduce gate resistance significantly and
966 M.-H. Chi

Fig. 51.15 Illustration of planar CMOS process flow with replacement metal gate (RMG)

enhance transistor speed. The RMG flow is illustrated in Fig. 51.15. After forming
ILD, those process steps in right box are inserted to form RMG, i.e. CMP to expose
the surface of the sacrificial poly-gate surface, etch hard mask (Si-nitride and
Si-oxide), use dry or wet etching to remove poly-gate; then form high-k dielectric
(with interface oxide and HfO2), then perform annealing, deposition of TiN
(as capping layer), anneal, deposition of a-Si followed by spike anneal, then wet
remove a-Si, deposition of TaN (etch stop) and p-WF (work function) layer (TiN),
the pattern and open n-MOS area, and etch p-WF. After PR removal, deposition of
51 Integration 967

n-WF (TiAl) and metal layers (Al or W by CVD or Ti, Al, W by PVD). Other steps
are the same as in Fig. 51.14.

FinFET Integration [5]

Since 22 nm node and beyond, the CMOS transistor is all based on the nonplanar
FinFET structure. Intel was the first successfully implementing FinFET technology
at 22 nm node. The FinFET process flow is similar to the CMOS planar flow
(Fig. 51.15) except that Step-1 is replaced by Step-10 (for STI and Fin formation)
as illustrated in Fig. 51.16. The STI and Fin formation (Step-10 ) flow is described
here: Firstly, deposit mandrel and hard mask (HM) layers, then pattern mandrel
(by masking and etch), and form first spacer (by thin film deposition and etch-back);
then remove mandrel (if selectively mandrel removal, then add HM etch and PR
removal); then etch Si (120–150 nm) using the first spacer as hard-mask; then
gap-fill by SiO2 and followed by CMP and annealing to form STI isolation between
fins; thus fins are formed all in the same direction. Then perform masking steps (for
opening the single-diffusion-break (SDB) slits and for fin cutting perpendicularly to
fin direction), then etch Si and SiO2 (50–80 nm), gap-fill (SDB gap) by SiO2, and
perform CMP (SDB is formed for isolation between fins along the fin direction).
Finally, perform SiO2 etch (30–50 nm) to reveal the fin height. Other steps are
similar to Fig. 51.15.

Non-volatile Memory (NVM) Integration

The floating-gate flash memory is typically stand-alone and formed in FEOL before
forming logic transistors. The thermal cycles related to the floating-gate process
steps may alter the characteristics of logic transistors (and also logic IPs); i.e., flash
memory process is not CMOS friendly or compatible with CMOS logic if integrating
together on the same chip. Recent development of emerging NVM technologies [6],
e.g., phase-change RAM (PRAM, PCM, or PCRAM), resistive RAM (RRAM or
ReRAM), and magnetic RAM (MRAM), are interesting for embedded applications
as they are processed at BEOL with minimum alteration of CMOS logic. Further-
more, these NVM memory technologies at BEOL can be stacked into 3D toward
large density, high performance, and low power. This section describes the process
flows of floating gate ETox cell at FEOL as well as those emerging NVM cell
at BEOL.

Floating-Gate Flash Memory Integration Flow

Flash memory has been the mainstream NVM since 1990 due to an increasing need
of nonvolatile storage of data. Flash memory is based on conventional poly floating-
gate structure (i.e., a poly layer in the gate dielectric of MOSFET) with electrons
968 M.-H. Chi

Fig. 51.16 Illustration of FinFET process flow with HKMG

51 Integration 969

Fig. 51.17 Illustration of ETox floating-gate flash memory process flow

stored on the floating-gate leading to the modulation of threshold voltage of the

transistor (representing data “1” or “0”). The write and erase operations are simply
the addition or removal of electrons on the floating-gate. Currently the flash memory
is organized as NOR and NAND architecture with integration in ~10Gb density and
with known limitations in high operating voltage (~10 V), slow erase (~1 ms), and
limited endurance to (~105). The read operation of NAND flash memory is even
slower than NOR. Currently, the 3D stacked NAND (3D NAND) is mature as the
mainstream NVM for large capacity storage. The process flow of a typical double-
poly floating-gate cell (well-known as ETox cell) is illustrated in Fig. 51.17, where
the cell fabrication is performed before the CMOS transistor formation. The floating-
gate cell (ETox) is difficult to be scaled at 45 nm node and beyond, as it is mainly
related to the cell interference from adjacent cells due to the thicker poly-Si floating
gate. Recent advances include the development of SONOS (Si-oxide-nitride-oxide-
Si) cell, charge-trapping TANOS (TaN-Al2O3-nitride-oxide-Si) cell, and band-gap
engineered SONOS, where the thin layer nitride serving as charge trapping (for
970 M.-H. Chi

replacing the “floating-gate” in ETox cell) can reduce the interference of coupling
from adjacent cell. Also, the multi-level or multi-bit cell is mature and can signifi-
cantly increase the NVM memory capacity.

Phase Change RAM (PCRAM) Integration

It is scalable favorably toward low voltage operation, faster programming, low

power, low cost, and high endurance (~108). The most popular material for
PCRAM is GST (pseudo-binary combination of GeTe and Sb2Te3) chalcogenide
alloy with some doping (a few % of N, C, or O) in a “mushroom” shape cell. Cell
structures are improved continuously for smaller RESET current by reducing the
bottom heater size and the critical volume of material for switching between the
amorphous (high-R) and crystalline (low-R) phases. The PCRAM integration flow is
illustrated in Fig. 51.18: After W-plug formed (any BEOL layer), deposit by GST
and TiN and patterned (one mask) on top of the W-plug, and continue with ILD and
via formation to form PCRAM cell. The mechanisms of crystallization and structural
relaxation will set the ultimate limit of scaling and reliability with ultra-thin phase-
change materials to ~3–10 nm range.

Resistive RAM (RRAM) Integration

The characteristics of bi-stable resistive switching is found in perovskite oxide (e.g.,

SrTiO3, SrZrO3 (SZO), PCMO, PZTO, etc.), transition metal oxides (e.g., Ni-O,
Cu-O, W-O, TiON, Zr-O, Fe-O, etc.), solid state electrolyte, and even polymers.
These materials can all be used in RRAM cell with high and low R representing logic
states “1” or “0.” The switching mechanisms (other than structural phase-change) are

Fig. 51.18 Illustration of PCRAM process flow

51 Integration 971

Fig. 51.19 Illustration of resistive RAM (RRAM) integration flow at BEOL

mainly based on the growth and dis-rupture of conductive filaments related to metal
ions, O ions/vacancies, reduction-oxidation, electron trapping/de-trapping (Mott
transition), high field dielectric breakdown, and thermal effect. The RRAM cell
usually consists of a select transistor and one MIM (metal-insulator-metal) resistor of
resistive switching materials. RRAM appears promising due to scalability, low
voltage operation, and compatibility with BEOL (particularly Cu-O and W-O
based cell). Currently, RRAM’s endurance is in the range of ~103–105. The
RRAM process flow at BEOL is illustrated in Fig. 51.19.

Magnetic RAM (MRAM) Integration [7]

The magnetic tunnel junction (MJT), typically two ferromagnetic layers sandwiched
with a thin insulator barrier (MgO or Al2O3), shows bi-stable tunneling magneto-
resistance (TMR) as memory element in MRAM (storage logic states “1” and “0”).
The TMR is resulted from the magnetic states of the “free” ferromagnetic layers with
respect to the “pinned” layer in spin parallel or anti-parallel. The MTJ with CoFeB/
MgO/CoFeB structure can achieve high TMR ratio of ~500% (i.e., ~5 larger than
conventional Al-O based MJT). Typical MRAM cell has 1 T-1MJT (i.e., one MJT
vertically integrated above one select MOS transistor) and can be switched mainly
by 2 mechanisms in array, i.e., field switching (by magnetic field generated from
adjacent x/y write lines) and spin-transfer-torque (STT) switching (by direct current
through the MTJ). The STT MRAM, which employs the direct injection of spin-
polarized current through MJT for switching the spin polarity in the free layer, has
demonstrated recently low write current (<106 A/cm2 in 10 ns pulse), good retention
(>10 years), small cell size (6F2, F the smallest feature CD), fast read (~30 ns), and
high endurance (~1014). STT MRAM is actively pursued in industry for embedded
972 M.-H. Chi

Fig. 51.20 Illustration of magnetic-RAM (MRAM) integration flow

applications and promising for replacing DRAM, SRAM, and Flash in future. The
process flow for MRAM formation is illustrated in Fig. 51.20.

3D NAND Integration

At 20 nm CMOS node and beyond, conventional planar NAND with floating-gate

approached scaling limit due to the capacitive coupling from adjacent floating-gate
cell. To realize higher storage capacity, NAND integration is toward 3D stacking. In
3D NAND, charge can be stored in floating gate or charge trapping layer (CTL). 3D
NAND flash memory with CTL and vertical channel (referred to as 3D NAND or
V-NAND) is based on junction-less (JL) thin-film transistor (TFT) and has good
reliability. The main stream 3D NAND [8, 9] is developed by Samsung, e.g., the
first-generation 3D NAND has density of 32–65 Gb with 24 layers stacking (2013),
the second generation 128Gb with 32 layers stacking (2014), the third generation
256Gb with 48 layers stacking (2015), 3D NAND with 64 layers already in
production (2017), and 3D NAND with 96 layers in production and 128 layers
stacking in sampling (2019). Figure 51.21 illustrates the array and cell structures of
3D NAND [1]. The bottom select transistors (CSL/GSL) are inversion type MOS
transistors, all other storage cells are junction-less type TFT transistor (JL-TFT). At
transistor turn-off, the TFT is in full depletion with the on-off current ratio large than
106. The charge trapping layer (CTL) is based on thin Si-nitride with high charge
trapping density for low capacitive coupling effect and interface from adjacent cells;
however, the electron and holes at CTL may diffuse laterally and degrade the charge
stored in cell. The write/erase operation is based on FN tunneling of electrons and
holes and optimized by the structure of ONO and barrier layer (usually Si-oxide or
Mo-oxide for low electron injection from reverse field direction). 3D NAND has
51 Integration 973

Fig. 51.21 Illustration of 3D NAND array and cell structure [8]

Fig. 51.22 Illustration of 3D NAND integration flow [8]

demonstrated superior capability of fast write/erase, storage window >6 V, write/

erase endurance >104, data retention of 10 years at 85  C, etc.
Figure 51.22 illustrates the 3D NAND integration flow [8]. After CMOS S/D
formation, multiple layers of SiO2 and Si2N3 layers are deposited (a), then, perform
lithography mask and etching to form deep channel hole (b) with aspect ratio > 30:1,
and then filling deep channel holes with high quality poly-Si and form the array of
gate pad (c). Then, perform lithography masking and word-line (WL) cut etch (d),
implant to form CSL lines, then wet removal of Si-nitride, deposit gate dielectric and
974 M.-H. Chi

ONO layers (as charge trapping) with uniform thickness and film composition and
low defect density at channel-dielectric interface. Then, deposit W film as gate
electrode, and etch W to form separated WL (e). Then, continue with BEOL flow (f).

Dynamic RAM (DRAM) Integration

DRAM is a key memory for computing intensive systems and still the main work
horse of memory in today’s systems. There are two main DRAM technologies based
on the deep trench cell or the stack capacitor cell. At 70 nm and beyond, stack
capacitor become the mainstream of DRAM cell. The DRAM cell structure is
continuously optimized toward high-speed, high density, and low power for high
performance system. Figure 51.23 illustrates the process flow for DRAM with both
trench-capacitor and stack-capacitor added to CMOS baseline. The stack-cell is
formed after the CMOS transistor and is mainly used for stand-alone high density
DRAM. The deep trench cell can be formed before the formation of CMOS

Fig. 51.23 Illustration of DRAM integration flow

51 Integration 975

Fig. 51.24 Integration of eDRAM with FinFET at 14 nm node [10]

transistor and is more suitable for embedded DRAM integration with logic together.
New embedded DRAM can be integrated with FinFET at 14 nm node (with SOI and
high-k metal gate) [10] as in Fig. 51.24, where cell capacitor of deep trench
(capacitance ~10 fF) is formed at FEOL with electrode TiN (by ALD). The doped
poly filled in trench capacitor connected to the FinFET (as pass transistor).

Design-Technology Co-optimization (DTCO)

As CMOS scaling to 20 nm node and beyond, IC design and process engineers need
to work closely together for design and optimization concurrently. Therefore, a new
methodology for the design-process technology co-optimization (DTCO) is intro-
duced. The concept of DTCO can be viewed as a derivation or enhancement from
design-for-manufacturability (DFM). Design and process engineers work together
closely from the early stage of development for efficiently optimizing technology
and improving manufacturability.
In IC industry, wafer fab’s, design houses, IP providers, and EDA tool vendors,
packaging companies are all important links in the IC industry chain. In earlier
technology nodes, wafer fab’s, design, and IP houses, EDA tool vendors all work
relatively independently and in a “one-way” manner as illustrated in Fig. 51.25.
Generally, 2 or 3 years before the target mass production of new technology, the
device target spec is characterized and defined, and then the process development
starts accordingly. After the baseline process is demonstrated to be stable, a process-
design-kit (PDK) is prepared for circuit/IP designers for product design and yield
enhancement.
As seen from Fig. 51.25, the flow of information is essentially “one-way” in the
technology development, i.e., from process (wafer fab’s) to IP and EDA tools, and
then to circuit design. Once the definition of technology and the process flow are
defined earlier, it is difficult to revise later in the paths. With the scaled CMOS
devices, it is necessary to characterize the device and circuit design and revise as
needed at early stages of development. In the advanced technology nodes, the wafer
976 M.-H. Chi

Fig. 51.25 Illustration of

conventional methodology for
technology development and
design service [11]

Fig. 51.26 Illustration of DTCO methodology for advanced technology development and design
service

foundry, IP houses, and EDA vendors are all involved in the entire stages of
technology development for process optimization, product debug, and yield
improvement as the design-technology co-optimization (DTCO) methodology [12]
as illustrated in Fig. 51.26.
The DTCO technology includes the following three aspects, i.e., lithography,
CMP, and their manufacturability interactions; the establishment of best trade-off
between IP library and SRAM cell; and the establishment of device characteristics
and layout dependent model [11, 12]. (1) Firstly, in advanced CMOS nodes, the
introduction of 193 nm deep ultraviolet (DUV) lithography, 193 nm immersion
lithography, self-align multiple patterning (SAMP) lithography, as well as the use
of optical proximity correction (OPC), off-axis illumination (OAI), and source-mask
51 Integration 977

optimization (SMO) lead to very complex lithography technology. If only the device
layout is scaled blindly (i.e., linear shrinking in x and y direction), then there are
many defects related to lithography limitations (e.g., line-end spacing, missing small
patterns, etc.) and other processes; as a result, the yield is poor. Thus, by using
DTCO technology in the early stage of process development, the device layout can
be evaluated and revised timely as needed with the capability of lithography and
other processes to achieve optimized process and layout design. (2) Secondly, by
analyzing process defects and circuit performance of various IP cores and SRAM
cells, a group of IP libraries and SRAM cell are selected for best trade-offs toward
high yield and high performance. (3) Thirdly, the continuous CMOS scaling leads to
increased variations of CMOS characteristics as related to layout environments.
Thus, it is important to characterize the layout-dependent proximity effects (LPE)
on devices and circuits at early stage of process development for best performance
and yield.

References
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Washington, DC, 2007)
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gate era for RF SoC (System-on-Chip) applications, in IEDM 2010, San Francisco, December
6–8, 2010, (IEEE, San Francisco, 2010)
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5. S. Natarajan, M. Agostinelli, S. Akbar, et al., A 14 nm logic technology featuring 2nd –
generation FinFET, air-gapped interconnects, self-aligned double patterning and a
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Types of Integrated Circuit Corporations
52
Nanxiang Chen, Shilin Fang, Rufei Chai, and Guoqiang Li

Contents
Integrated Device Manufacturer (IDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Fabless Design Houses [1, 2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Module Manufacturers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Memory Manufacturers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Wafer Foundry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
IP Design and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Outsourced Semiconductor Assembly and Test (OSAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
Photomask Manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
Semiconductor Equipment Manufacturers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
Semiconductor Material Manufacturers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
Wafer Substrates Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
Photoresist Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
Semiconductor Assembly/Packaging Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
Electronic Design Automation (EDA) Companies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
Distributors and Sales Representatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

Abstract
Driven by Moore’s law, the integrated circuit (IC) industry is progressed at high
speed with innovations and development and already fundamentally impacts
human being toward high quality life. At the same time, the industry is also
N. Chen
Yangtze Memory Technologies Co., Ltd., Wuhan, China
S. Fang · R. Chai (*)
China Resources Microelectronics Ltd., Wuxi, China
e-mail: chairf@crmicro.com
G. Li
Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd., Shanghai, China
Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, China
ICWise Market Information Consulting (Shanghai) Co., Ltd., Shanghai, China

© Publishing House of Electronics Industry 2024 979

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_52
980 N. Chen et al.

evolving quickly from highly vertical integration mode toward lateral collabora-
tion. As a result, new types of companies and sub-industries were evolved from
traditional integrated device manufacturers (IDMs), to fabless design houses,
module manufacturers, wafer foundries, IP design and services, packing houses,
outsourced semiconductor assembly and test (OSAT) companies, photomask
manufacturers, semiconductor equipment manufacturers, semiconductor material
manufacturers, electronic design automation (EDA) vendors, and IC component
distributors. As the industry approaching more mature, the evolution of IC
industry continues. There are also signs of merging business modes together,
for example, system houses starting circuit design (e.g., Apple, Huawei); EDA
company, fabless design house, and foundry companies also developing of IPs
(e.g., Synopsis, Cadence, GlobalFoundries); and some wafer manufacturers also
in advanced packaging business (e.g., TSMC). It appears the IC industry chain is
continuously evolving with the development of economy and technology.

Keywords
IDM · Fabless · Foundry · IP · Design service · OSAT · Photomask · Equipment ·
Materials · EDA

Driven by Moore’s law, the integrated circuit (IC) industry is at high speed in
innovations and development for new generations of products and already funda-
mentally impacts human being toward high quality life. At the same time, the
industry is also evolving rapidly from highly vertical integration mode toward lateral
collaborations. As a result, new types of companies and sub-industries were evolved
from traditional integrated device manufacturers (IDM), to fabless design houses,
module manufacturers, wafer foundries, IP design houses and services, packaging
houses, outsourced semiconductor assembly and test (OSAT) companies, photomask
manufacturers, semiconductor equipment manufacturers, semiconductor material
manufacturers, electronic design automation (EDA) vendors, and IC component
distributors. As the industry approaching more mature, the evolution of IC industry
continues. There are also signs of merging business modes together, for example,
system houses starting circuit design (e.g., Apple, Huawei) of products; EDA
company, fabless design house, and foundry companies also developing of IPs
(e.g., Synopsis, Cadence, GlobalFoundries); and some wafer manufacturers also in
advanced packaging business (e.g., tsmc). It appears the IC industry chain is
continuously evolving with the development of economy and technology.

Integrated Device Manufacturer (IDM)

IDM refers to a company incorporating full capability from circuit design, wafer
manufacturing, to testing and packing, as well as product sales under its own
brand, it is also named as IC device manufacturer (IDM); some typical IDM
52 Types of Integrated Circuit Corporations 981

companies are Intel, Samsung, SK Hynix, Micron, and Texas Instruments (TI). In
earlier stage of IC industry, almost all companies are IDMs due to the following
advantages: (1) Internal advantages: IDMs have advantages in organization and
management efficiency for achieving shorter time from new product concept to
production and faster time-to-market. (2) Higher overall profit: The product
design and sales are at both ends of the “smile” curve with the highest profit
margin in the value chain. (3) Overall superior technology: IDMs have own IPs
and long-term accumulation of experiences in product and design and know-how
in process technology.
As the CMOS technology advancing, not only the cost to build a new wafer fab
and equipment increases dramatically, the cost for developing new generation of
technology also increases dramatically; e.g., USD$2B–6B for logic 14/10/7 nm
technology nodes. Furthermore, the cost for developing circuits, IPs, and products
at new CMOS node also increases dramatically as related to the cost of masks,
simulations, iterations, as well as lower product success rate and shorter life at new
CMOS nodes, etc. Thus, IDMs prefer less investment to build new fab’s and use
foundries for overflow capacity needs. Currently, most IDMs become “fab-lite”
(e.g., NXP, Infineon, FUJI, Renesas, etc.).

Fabless Design Houses [1, 2]

Fabless design houses refer to IC companies focusing on product design and have no
fab facilities, also referred to as fabless IC design companies, e.g., Qualcomm,
Broadcom, MediaTek, UNISOC, and HiSilicon. These fabless design houses own
and sell their products. However those circuit intellectual property (IP) design
houses (e.g., ARM) are also referred to as chipless companies, and design service
companies do not sell IC products. Fabless companies, already in business for
30 years since 1984, directly face customers and serve IC industry. They fully rely
on foundry for manufacturing wafers and assembly houses for packaging, both the
foundry and assembly houses actually reduced entry barriers for fabless houses into
IC market. The fabless houses, wafer foundry, and assembly/packaging houses
together have capability as if a full IDM (i.e., “virtual IDM”). There are many
fabless design houses, some small (<10 designers) or large (e.g., Qualcomm,
AMD, MediaTek). Currently, the number of fabless companies is far exceeding the
number of wafer fab’s in China, e.g., ~750 fabless in 2015, ~1400 fabless in 2018,
and ~1700 fabless in 2019.
The fabless houses need to have strong interaction with foundries in order to use
foundry’s most advanced technology (often in R&D) for their new products.
Similarly, wafer foundries often need to understand new product targets from
leading fabless houses in order to define technology specifications for developing
new CMOS technology. Thus, they are often referred to as “virtual fab” and
“virtual design house” each other and together “virtual IDM” for today’s IC
industry.
982 N. Chen et al.

Module Manufacturers

Electronic systems are often divided into several functional modules (packages or
PC-boards); each module may include controllers, sensors, RFICs, power devices,
and passive components. A module manufacturer focuses on the design, develop-
ment, and production of such modules. It is increasingly in-efficient for a system
house to perform the design, development, and verification of functional modules
(e.g., gate drive, power amplifier, controller circuits, etc.) or sub-modules (sensing
and communication, etc.). Thus, there are dedicated module manufacturers provid-
ing professional services to system houses for manufacturing modules or
sub-modules (as if the “foundry” manufacturing wafers for IC design houses).
Many IDMs and/or fabless houses may also step in the area of module design/
manufacturing to increase their competitiveness on the market. By focusing on
module development and manufacturing, module makers have expertise in effective
and professional design (for high quality and reliability with less component counts,
etc.), adopting new materials, and new advanced packaging. It is important that
system houses and module manufacturers work closely together to develop high
performance systems with effective cost.
Based on functions in systems, modules can be categorized as power module, RF
module, and communication module. Infineon, ABB, Mitsubishi, and Fuji electron-
ics are well-known power module providers. Typical RF module providers are TDK
and AVAGO. Typical communication module providers are Rohm and Longsys. In
addition, Huawei and Unisoc are also competitive in RF and communication module
areas.
Based on the package format, modules can also be categorized as multi-
component (MCO) and multi-chip (MCP) types, where MCO modules include one
or more ICs and one or more discrete semiconductor devices together, and MCP
modules have several chips on the same or different substrates encapsulated within a
single package. The World Semiconductor Council (WSC) [1] is working actively to
custom codes approved for MCO and MCP modules as product class in IC industry.

Memory Manufacturers

Memory products include SRAM, DRAM, and flash memory (NAND flash and
NOR flash). An IDM (e.g., Intel, Samsung, Texas Instruments) or a pure-play
foundry (e.g., TSMC) may manufacture multiple IC products, such as processors,
memories, and digital and analog circuit designs. However, when an IC manufac-
turer mainly focuses on memory products, one can call it a memory manufacturer.
For example, Micron Technology and SK Hynix have been ranked in the top world
memory manufacturing players in recent years. While memory market grows rap-
idly, e.g., the DRAM sales has contributed 15% to the semiconductor market; about
30–40% of DRAM products have been consumed in China and another 30–40%
consumed in the USA. Overall in memory market in 2021, DRAM shared 61%,
NAND flash 39%, and NOR, EEPROM, and others took about 3%.
52 Types of Integrated Circuit Corporations 983

The increased demand on various memory products has invoked several domestic
memory manufacturers to invest more R&D effort in these areas. Two domestic
memory manufacturers are introduced below. (1) Yangtze Memory Technologies
Co., Ltd., focused on NAND flash and, (2) GigaDevice and ChangXin Memory
Technologies Inc., focused on DRAM and others.

1. Yangtze Memory Technologies Co., Ltd. (YMTC) was established in Wuhan,

China, in 2016. It is an IDM focusing on the design, manufacture, and sale of 3D
NAND flash memory. After years of development, YMTC has become an
advanced memory solution provider recognized by the industry and global
customers.
The company aims to provide various products and complete system solu-
tions, ranging from 3D NAND flash memory chips to embedded applications,
cSSDs, and eSSDs. YMTC objects to create high-performing, industry-leading
products widely used in mobile devices, consumer electronics, PCs, servers, and
data centers.
YMTC has formed a team of more than 11,000 employees in total worldwide,
including over 6000 R&D and engineering professionals. Currently, YMTC
possesses three R&D centers in Wuhan, Shanghai, and Beijing.
Operating two advanced 12-inch Fabs, YMTC is leveraging cutting-edge
technology to mass produce advanced 3D NAND flash memory chips, boasting
a higher bit density, faster I/O speed, lower power consumption, and better quality
and reliability.
At Flash Memory Summit (FMS) 2018, YMTC debuted its groundbreaking
Xtacking ® architecture and was awarded the “Best of Show” for Most Innovative
Flash Memory Startup Company. Furthermore, YMTC was honored with a Most
Innovative Memory Technology Award on the FMS 2022.
2. GigaDevice Semiconductor Inc. was initiated from in 2005 by Yi-ming Zhu and
Qing-ming Shu. Yi-ming Zhu jointly with Hefei Municipal Government founded
ChangXin Memory Technologies Inc. (CXMT) in 2016; together GigaDevice
(GD) and CXMT have formed an IDM of domestic dynamic random access
memory (DRAM), integrating R&D, manufacturing, and sales in mainland
China.
GigaDevice is started with the memory design in the initial stage. Based on the
patterned technology dySRAMTM, the company developed low-power, low-cost
SRAM IP and IC products. In 2008, the company launched the first SPI NOR
flash by the indigenous pattern technology gFlashTM in China market; GD has
successfully became a leading company of NOR flash globally. In 2013, the
company launched the first 32-bit general MCU based on Arm ® Cortex ®-M3
core in China. At the same time, the first 8-pin SPI NAND flash was launched in
the global market. As an IC design house, GD integrates flash memory, micro-
controller (MCU), and sensor designs as platform solution.

In Mar. 2017, CXMT first phase ground breaking was at Hefei Airport Economic
Demonstration Zone, planned monthly output 100 K of 300 nm wafers. The
984 N. Chen et al.

cooperation of CXMT and Polaris introduces the DRAM technology and pattern
from Qimonda, a German DRAM fab (was top 2 worldwide). CXMT has been
further establishing an effective R&D mechanism toward the latest equipment. The
core technology developed independently by CXMT testifies that we’re the succes-
sor and promoter of Qimonda. In Sept. 2019, the first phase rolled out for pilot small
volume production. In 2020, the high speed and low power memory chip and
module moved to mass production. The application covers server, PC, smart
phone, consume, etc. and receives positive feedback from the industry. Being a
significant breakthrough from Zero to One, CXMT has successfully developed
product at sub-20 nm technology node and in mass production. Having established
12-inch fabs in Hefei and Beijing, CXMT is successful in both producing high-
volume products of two generations of technology nodes and achieved a break-
through in the development of DRAM products from scratch in mainland China.

Wafer Foundry

Wafer foundries provide IC fabrication services for fabless design houses but do not
perform IC design or product sales. It is evolved from IDM for better efficiency and
lower cost by sharing wafer fab facilities. Wafer foundries are intensive in capital,
technology, and talents for equipment, development of technology, and daily oper-
ations. In order to have good business return, wafer foundries must have large
enough scale and high-capacity utilization. The cost of developing new technologies
is at fixed level and allocated with sufficient orders. The capacity needs to be
invested at large scale and maintained closely to full production. Since the late
1980s, the progresses of wafer foundry business have enhanced the efficiency and
cost of product development and also enabled large number of IC fabless design
houses; the pace of the IC industry is also accelerated.
Wafer foundries have the following features: (1) Wafer foundries focus on wafer
production on customer’s demands, achieve good efficiency and high yield, have
continuous improvement in technology, and develop new technology based on new
product targets (from customers). Fabless design houses pay for the wafer services in
fab and no need to invest the cost for wafer fab’s. (2) Wafer foundries serve many
fabless design houses (as customers and partners); this helps to stabilize the capacity
utilization and minimize the impact of fluctuations of single product or market
segment. Also, fabless design houses can focus on IC design and product develop-
ment and just interface with wafer foundries and assemble houses. (3) The collab-
oration model of wafer foundries and fabless design houses has accelerated and
enhanced the advancement of both process and design technologies and operation
efficiency (i.e., lower cost in development and manufacturing). Currently, TSMC,
GlobalFoundries, UMC, and SMIC are the top 4 pure-play wafer foundries. Pure-
play wafer foundries do not compete against design houses, but as close partners in
product development and manufacturing.
Besides the above pure-play wafer foundry, there are also two related business
models. (1) Captive wafer foundry with IDM as basis: In this case, the foundry uses
52 Types of Integrated Circuit Corporations 985

IDM’s technology platform and its surplus capacity for wafer foundry. In this
business model, the offered processes may be more advanced, but customers are
more limited to use IDM’s platform with similar product features. The foundry and
its IDM customers may have competition on market. For IDM, this could reduce the
influences of sales volume and industry periodicity on its capacity utilization.
Currently, Samsung and Intel are the largest captive foundry with limited customers,
e.g., Samsung performs foundry on advanced technology for Apple and Qualcomm,
but both Apple and Qualcomm also use other foundries (e.g., TSMC). (2) “Virtual
IDM”: This is a business model developed from wafer foundry with close collabo-
ration between fabless design and wafer foundries. Wafer foundry provides part of
their capacity exclusively to those bounded fabless design houses (as preferred first-
class device manufacturers with priority in capacity, technology platform, and
technical support) but often needs to share profits in return. In the 1990s, most
200 mm foundries can advance their technology by upgraded equipment capability.
But in the 300 mm era, only a few foundries can afford to continuously upgrade
technologies due to huge investment for advanced equipment and new technology
development. According to the statistics of market research institutions, in the era of
200 mm at 0.13 um node, there are ~20 companies worldwide capable of the 0.13 um
technology node and among them ~10 wafer foundries.
In the era of 300 mm fab, there are ~10 companies worldwide with 28 nm node,
and among them ~5 are pure wafer foundries. It is expected that only a few
companies (e.g., TSMC, Samsung, Intel) in the world will have 7 nm node technol-
ogy. This is certainly related to the huge capital expense and R&D cost for technol-
ogy development. While there are fewer mainstream logic wafer foundries, there are
increasingly more foundries for specialty technologies. This trend is also consistent
with the ICs for artificial intelligence (AI) and Internet of Things (IoT) era [3, 4],
where specialty functions (e.g., RF, memory, sensors, power devices, etc.) are
increasingly to be integrated with logic circuits.

IP Design and Service

IP design houses and service companies refer to those that use the process data from
wafer foundries to design IC macro and provide corresponding services. IP is also
referred to as IP cores. Such companies generally do not design their own chip
products. The IP which is literally understood as “intellectual property”, means
circuits with specific functions with well-defined interfaces and reusable in IC
design. These IPs are the basic components to realize application-specific integrated
circuits (ASIC) and system-on-chip (SoC) [5, 6]. IP cores can be divided into soft,
fixed, and hard cores. There are three business models for those IP houses or “chip-
less” IC design houses. (1) IP business model based on wafer foundries: The wafer
foundries can purchase IP licenses from IP suppliers and validate them on foundry’s
process platforms. Then the wafer foundries pay license fees to IP suppliers. SoC
design houses choose wafer foundries and determine the process platform and
verified IPs to be used. After paying “IP user fee” or IP NRE (non-recurring
986 N. Chen et al.

Fig. 52.1 The business

model of fabless design house

engineering) fee to IP supplier, then SoC design houses can be granted IP usage right
and design document; then SoC product design can be started. After complete SoC
design and start in manufacturing, the wafer foundry pays royalty to IP vendor
regularly based on the actual shipment of SoCs. This business model is illustrated in
Fig. 52.1. (2) IP business model based on IP vendors: The users directly obtain IP
specifications and related data packages from IP vendors for evaluation, then select
proper IP soft cores for design and verification, and pay IP vendors a one-time “IP
copyright license fee.” Users also pay “IP copyright tax fees” to IP providers based
on the die or wafer price. (3) IP business model based on design services: The users
propose target product specifications, and then the design service houses evaluate the
product specifications (e.g., IP technology, area, cost, NRE, and full chip design
service, etc.) and propose a product development plan for customers. The cost of IP
cores used is included in the budget. According to the expected future output of
customers’ products, a turnkey business model can be developed. The service fees of
designing chip and subsequent packaging and testing will be charged, and the IP
copyright tax will be charged according to the agreement. The functions provided by
high value-added IP are often complicated in design, difficult in verification, and
long cycle for development and verification, so they play a critical role in SoC
design.
On the one hand, IP vendors and wafer foundries have formed a close collaborate
relationship, and both sides cooperate to develop IPs and serve the common design
customers; on the other hand, IP vendors can greatly shorten the SoC design and
verification cycle and save the R&D cost even if providing partially verified IP
module. Therefore, IP vendors, wafer foundries, and SoC design houses are in
mutually beneficial and win-win relations. With the increasing degree of system
integration and complexity of SoC designs, IPs are more diversified and increasingly
at critical role for the successful SoC design and wafer manufacturing. Currently, the
mainstream IP providers are briefly described below: (1) ARM, offering high price/
performance, high code density, low power consumption, and low chip area ARM
52 Types of Integrated Circuit Corporations 987

structure-based RISC microprocessor. Its IPs are widely used in various portable
consumer products. (2) Synopsys and Cadence: Through the benefits of their EDA
tools, they offer various digital and analog IPs and also offer customers total turnkey
solution. (3) Silicon images, Rambus, Sonic IC, Ceva: offering various high-speed
interfaces, digital media players, digital signal processor (DSP), SATA, and
Bluetooth IP. (4) eMemory and SST: Offering IP for non-volatile memory (NVM)
such as OTP, MTP, and eFlash, focusing on various popular applications such as
digital power and encrypted chips. In China, there are IP companies, e.g., Verisilicon
and ACTI, offering power IP, high speed interface IP, and special application specific
IP. They also offer design service technical support and full chip design solutions.

Outsourced Semiconductor Assembly and Test (OSAT)

Outsourced semiconductor assembly and testing (OSAT) belongs to the back-end

process of product manufacturing. Assembly (or packaging) and testing work refers
to the processing of wafers after wafer fab, complete sort, dicing, final test, and
packaging and then attach on advanced package module or PCB separately. In 1968,
the establishment of Amkor Technology represents the separation of the assembly
and testing industry from IDM model. Open assembly and testing houses
(or foundries) charge customers processing fees by providing wafer packaging and
testing services. Another kind of companies purchase wafers, assemble and test
them, and sell final products under their own brand. Testing can be divided into
probe test and final test. (1) The purpose of the probe test is to screen those
unqualified chips before packaging and reduce waste in packaging process. The
function of the chips is tested by contacting the probe with the pads on the chip, and
the unqualified chip is marked and screened after cutting. (2) The final test is after
assembly which is used to ensure that all the malfunction chips will be screened out
and not delivered to customers.
The early packaging and testing is low in technology content and labor-intensive.
With the development of IC industry and the progresses of advanced technology,
packaging technology has also progressed from DIP, SOP, and QFP to QFN, BGA,
Flip-Chip, and WLCSP. With the development of packaging materials (lead-frame
and plastic packaging), packaging and testing technologies are closely related with
front-end advanced IC technologies as illustrated in Fig. 52.2. With the development
of 3D and wafer-level packaging (WLP) [7–9] technologies in the post-Moore era,
bumping and other middle-end processes have emerged one after another. Tradi-
tional wafer foundries are extending into packaging, while packaging houses are
extending into wafer manufacturing. This is a trend of integration of business
models. At the moment, the mainstream OSAT vendors are ASE, Anker, TFME,
SPIL, JCET, TSHT, and China resources Anst. Through offering chip-on-wafer-on-
Si (CoWoS) [10–12] and integrated fan-out (InFO), TSMC enters assembly and
testing areas. SMIC and JCET set up a joint venture to build and develop 300 mm
bumping technology and the associated assembly process. ASE also enters the front-
end process and builds its own process technologies.
988 N. Chen et al.

Fig. 52.2 The evolution of semiconductor assembly

Photomask Manufacturer

In the process of wafer manufacturing, it is necessary to form a specific pattern on the

wafer by photolithography tools (e.g., DUV scanner), and based on this pattern, dry
etching, wet etching or cleaning, ion implantation, deposition, and other processes
are performed. One critical tool in photolithography technology is the photomask
with required layout patterns. Photomask making refers to the conversion of circuit
layout to the physical patterns on the photomask with key steps, including the
transfer of patterns, algorithm of separating sub-layers of layout, and data security
protection. It is one of the most critical loops in the IC industry. Mask shops have two
main operation modes: in-house and commercial mask-making. Usually, large IDMs
or wafer foundries will invest to have their own mask shop (i.e., in-house mask shop)
to serve internal needs of wafer manufacturing. Commercial mask shop refers to a
professional mask-making company for external customers with wide range of
products in ICs, liquid crystal displays (LCD), touch screens, optical components,
etc. The mask-making procedures are typically as follows: Design house places an
order ! Data processing ! Exposure ! Development ! Etching ! Strip-
ping ! Defect detecting and repairing ! Adhesive film cleaning ! Final product
shipment.
In the 1970s and 1980s, domestic mask shops were small in scale, and their
mask-making is mainly for their internal fabrication lines. At the end of the
52 Types of Integrated Circuit Corporations 989

1980s, independent commercial mask shops appeared in China and mainly

capable for the technology nodes of 3–5 μm. Currently, mask-making technology
has progressed rapidly with the highest technology level at 7 nm node and
beyond. In China SMIC has a mask shop with mask-making capability for
28 nm node.

Semiconductor Equipment Manufacturers

Semiconductor equipment suppliers refer to companies that can supply various

equipment or instruments for wafer fabrication, packaging, testing, and provide
corresponding technical support and services. Early semiconductor IDM compa-
nies have capability to make their own equipment. Later, with the advancing of
the IC industry, these departments for equipment manufacturing have evolved
into professional independent suppliers of semiconductor equipment. With the
continuous advancement of IC manufacturing technology, semiconductor equip-
ment suppliers have invested considerable resources in R&D of tools and process
details (e.g., recipes for new process); and currently, top equipment suppliers
have achieved leading or monopoly position almost in all process areas. The
refurbishment of secondhand equipment also becomes a new business model,
which includes single tool or multiple sets, or even a full secondhand line of
equipment transfer. Semiconductor equipment is an important role in the whole
industrial value-chain. It is a major fixed asset for wafer foundries and packaging
houses, where equipment investment can be as high as ~70% of the total assets.
Equipment capability set the limit of technology capability of the IC industrial.
For example, 7 nm technology has demonstrated as early as 2004, but the 7 nm
node finally went into production in 2019 with modern equipment and process
technology greatly enhancing for manufacturability. In the 300 mm line, the
equipment is increasingly complicated, not only in hardware, but also in process,
materials, and production automation system.
Semiconductor manufacturing process equipment mainly includes lithography
tools, etcher, ion implanter, oxidation diffusion furnace, rapid thermal annealing
(RTA), physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic
layer deposition (ALD), chemical mechanical polishing (CMP), wet clean system,
in-line measurement, and testing systems. The development and manufacturing of
semiconductor equipment is based on combined know-how from optics, physics,
chemistry, machinery, electronics, precision instrumentation, automation, and other
technologies. It has the characteristics of high technology content, difficult in
manufacturing, and high equipment value.
Most of the main semiconductor equipment manufacturers are located in devel-
oped countries such as the USA, Japan, and the Netherlands. International main
providers include ASML, Lam research, Tokyo electron, and KLA-Tencor. Chinese
providers include NAURA, AMEC, Piotech, SMEE, CETC No.48 and No.45
institutes, CEIC, HWATSING, ACM, and HANS LASER.
990 N. Chen et al.

Semiconductor Material Manufacturers

Semiconductor material vendors refer to the manufacturers of wafer substrates as

well as the materials of electronic grade gases, chemicals, sputtering targets, photo-
resist (PR), slurry, and other materials needed in IC manufacturing, packaging and
testing. Semiconductor materials require high purity and materials for critical pro-
cess steps are usually required to reach 6 N (99.9999%) or better. Wafer substrates
have strict control range of Si purity and doping parameters and also require high
surface cleanliness and low defect density. In a semiconductor fab, there are more
than 10’s of 100’s of different materials in use with various forms (as gas, liquid,
solid). They may be highly toxic, corrosive, flammable, and explosive (e.g., hydro-
gen, methane, silane, HF acid, H2SO4 acid, nitric acid, organic solvents, etc.).
Therefore, the transportation, storage, use, and waste disposal of materials must
follow strictly those control procedures from international standards and national
regulations.

Wafer Substrates Vendors

Early semiconductor manufacturers had some ability to produce Si substrates and

other materials. With the development of the industry, the substrate material vendors
are gradually independent to perform professional operations and prefer to supply
the leading wafer manufacturer first. At the same time, the material manufacturers
are also developing rapidly under the drive of the IC industry. Substrate material
manufacturers are mainly located in Japan, Germany, and China/Taiwan, e.g., Shin-
Etsu, Sumitomo Mitsubishi, Global Wafer (China/Taiwan), Siltronic, Soitec
(France), and so on. By the end of 2016, Chinese vendors can provide Si substrates
from 100–200 mm in size. Currently, the advanced technology of GaAs materials is
still in the hands of large companies in Japan, Germany, and the USA. Up to the end
of 2016, GaAs materials supplier in China mainly produce low resistance GaAs
wafers for LED.

Photoresist Vendors

With the development of IC technology toward scaled devices, the PR for ultra-fine
lines in nm range is very important. Currently, the main suppliers of advanced PR are
mainly those companies with long-term development and production of organic
photosensitive materials. Up to the end of 2016, China has not yet the ability to
produce PR for the technology below 65 nm node. China vendors already have some
market scale in grinding fluid, metal target, Cu plating bath, and other IC process
materials.
52 Types of Integrated Circuit Corporations 991

Semiconductor Assembly/Packaging Materials

It includes bonding wire, ceramic material, lead frame, mold component, TAB, COF,
and so on. At the moment, main semiconductor assembly material vendors are in
Japan and the USA.

Electronic Design Automation (EDA) Companies

EDA technology refers to the computer software system based on the computer-
aided design (CAD) technology, using computer as the hardware platform, and
completes the product design according to the hardware description language
(HDL) (including Verilog HDL and VHDL). The RTL source code can complete
many design functions, e.g. logic compilation, simplification, module segmentation,
synthesis and timing optimization, automatic layout/routing, pre/post simulation,
chips, logic mapping, DFM effect, and GDS data generation, etc. A modern IC chip
may have billions of transistors and EDA tools are essential for such design. TCAD
(technology computer-aided design) mainly simulates and optimizes the process and
device structure and also belongs to EDA technology. Major international EDA
vendors also involve in IP design and services by taking advantages of their own
design tools.
Currently, there are about 100 EDA vendors worldwide, mainly in the USA,
Europe, and Israel. The top three EDA vendors are Synopsys, Cadence Design
Systems, and Mentor Graphics with over 50% of world market share. These three
vendors compete in similar fields but with different strength. For example, Synopsys
has advantages at digital front-end and back-end, prime time sign-off, as well as
various analog and digital IP total solutions. Cadence has advantages on analog
designs, digital back-end, design services, double data rate IPs, etc. Mentor has
advantages in caliber sign-off, design for testability (DFT), and optical proximity
correction (OPC). Similar to semiconductor design industry, there are also a lot of
mergers occurred in EDA industry. The top three EDA houses have acquired many
smaller EDA or IP houses to increase their market shares and optimize their design
capability, e.g., Synopsys acquired Magma, Mentor bought BDA, and Cadence
bought Tensilica. In 2017 Siemens bought Mentor and acquired know-how and
opportunity to extend its business in chip design; Mentor also can have sales support
as well as investment to extend portfolio. The main EDA providers in China is
Empyrean; based on the unique requirements of Chinese customers, Empyrean
focuses product development on customized total design services as a technology
breakthrough.
EDA tool manufacturers, continuously gathering top talents and scientists for
R&D and improving EDA tools, can lead the IC industry toward advanced design
methodology with fabless design houses, wafer foundries, testing, and packaging
992 N. Chen et al.

houses. The EDA business also evolves from permanent license into term base
license (TBL), which means customers need to continually extend its contract and
re-order. By using advanced design process flows and softwares provided by EDA
vendors, customers can effectively design their products and shorten the time-to-
market; at the same time, EDA vendors can also upgrade and optimize their EDA
products based on customer feedback and drive EDA industry moving forward. In
return the advancements of EDA industry also drive the progresses of IC industry.

Distributors and Sales Representatives

Distributors, also known as distribution networks or distribution channels, refer to

the sales channels for transferring products from manufacturers or designers to
consumers or end-users. The selling of products from the design houses and man-
ufacturers to the end-users is completed by the distributors, sales agents, or channel
providers except for the direct sales from the original factories.
The main functions of distributors and sales representatives are the following:
(1) Selling vendor’s products to various customers with different volume and
locations. (2) Distributor could fulfill customer’s demands in logistic and payment
terms as a role similar to bank and logistic company. (3) Providing necessary
technical support especially for small or middle size companies in remote areas;
some distributors even provide customized system solution by utilizing its technical
know-how. (4) Reduce the number of distributors per customer, and provide cus-
tomers one-stop shopping services for reducing customer’s cost. (5) Reduce ven-
dor’s cost and investment in product promotion and sales and technical support.
The distribution industry for semiconductor has the following features: (1) Dis-
tributors may build inventories according to customer forecast for ICs with large
volume and seasonal fluctuations. (2) Due to strong competition and critical time-to-
market, distributors can provide detailed product description and technical support,
help customers design PCB, or reference designs with products from various
vendors. (3) Distributor typically holds various technical seminars together with
vendors for identifying potential customers and push products into a wider range of
markets. (4) The product selling is increasingly through the Internet.

References
1. B. O’hUallachain, Restructuring the American semiconductor industry: Vertical integration of
design houses and wafer fabricators. Ann. Assoc. Am. Geogr. 87(2), 217–237 (1997)
2. Fabless manufacturing., https://en.wikipedia.org/wiki/Fabless_manufacturing
3. T. Haga, A. Okada, S. Matsuo, On Si platform opens a new world in AI-IoT service era. NTT
Tech. Rev. 15(1), 1–5 (2017)
4. C.A. Tschider, Regulating the IoT: Discrimination, privacy, and cybersecurity in the artificial
intelligence age. SSRN Electron. J. (2018)., https://www.academia.edu/79908708/Regulating_
the_IoT_Discrimination_Privacy_and_Cybersecurity_in_the_Artificial_Intelligence_Age
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5. System on a chip., https://en.wikipedia.org/wiki/System_on_a_chip

6. A. Patil, A.A. Shirolkar, A review on System-on-Chip (SoC) designs for real-time industrial
application. Int. J. Trend Sci. Res. Dev. 2(1), 1534–1537 (2017)
7. Wafer-level packaging, https://en.wikipedia.org/wiki/Wafer-level_packaging
8. Wafer Level Chip Scale Package (WLCSP), Application Note, NXP (Freescale Semiconductor,
Inc.), Document Number: AN3846, Rev. 4.0, 8/2015
9. P. Garrou, Wafer level chip scale packaging (WL-CSP): An overview. IEEE Trans. Adv.
Packag. 23(2), 198–205 (2000)
10. D. Patel, Advanced packaging part 2 – review of options/use from Intel, TSMC, Samsung,
AMD, ASE. Sony, Micron, SKHynix, YMTC, Tesla, and Nvidia (2022). https://www.
semianalysis.com/p/advanced-packaging-part-2-review
11. S.Y. Hou, C.W. Chen, C. Hu, et al., Wafer-level integration of an advanced logic-memory
system through the second-generation CoWoS Technology. IEEE Trans. Electron Devices 99,
1–7 (2017)
12. S.K. Goel, S. Adham, M.J. Wang, et al., Test and debug strategy for TSMC CoWoS stacking
process-based heterogeneous 3D-IC: A silicon study, in Handbook of 3D Integration: Design,
Test, and Thermal Management, ed. by P.D. Franzon, E.J. Marinissen, M.S. Bakir, vol.
4, (Wiley-VCH Verlag GmbH & Co., 2019), pp. 325–346
Management and Modes of IC
Manufacturing Enterprises 53
Xiangdong Chen, Jianxin Yan, and Liang Ma

Contents
Organizational Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
Production Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
Collaboration Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
Administration Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
Strategy Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
Strategy Management of the IDM Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
Strategy Management of the Foundry Enterprises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
Planning Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
Technology Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Module Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Product Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Quality Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
Chip Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
Chip Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
Clean Room Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
Marketing and Sales Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
Cleanroom Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Dustproof Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Temperature/Humidity Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Anti-Static Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Materiel Management and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Material Control Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
Inventory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
Equipment Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
The Equipment Inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
The Equipment Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
Equipment Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
Preventative Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Equipment Maintenance Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007

X. Chen · J. Yan (*) · L. Ma

Hangzhou Silan Microelectronics Co., Ltd., Hangzhou, China
e-mail: yanjianxin@silanic.com.cn

© Publishing House of Electronics Industry 2024 995

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_53
996 X. Chen et al.

Waste Material Treatment Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007

Environmental Protection Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
Safety Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
Information Security Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012

Abstract
The management of IC manufacturing enterprises mainly manages the entire
process of production, material control, process management, and quality control
in the manufacturing IC chips through effective organizational forms. The
requirements of enterprise management have certain peculiarities. This section
mainly introduces the unique characteristics of IC manufacturing enterprises,
management methods from the aspects of the company’s organizational structure,
strategy, planning, technology, quality, marketing and sales, cleanroom, mate-
rials, equipment maintenance, waste material treatment, environmental protec-
tion, production safety, and information security.

Keywords
Enterprises management · Organizational structure · Strategy and planning ·
Technology and equipment · Marketing and sales · Environmental protection ·
Safety

Organizational Structure

The organizational structure of a wafer fab in volume manufacturing can be divided

into 3 groups, that is, production, collaboration, and administration groups according
to the functions. All groups follow the basic principles of profession and organiza-
tional cooperation.

Production Groups

It is directly related to the IC manufacturing, mainly including wafer production, process

engineering, equipment engineering, etc. The organizational structure is usually based
on convenience and effectiveness of management, mainly including the following
3 types. (a) The departments are established by engineering functions, for example,
the lithograph, etching, thin-film, wet etching/clean, etc., and are responsible for all
engineering functions (e.g., process and maintenance, etc.). (b) The departments are
established by operation functions, for example, production, process, and maintenance,
etc., and are responsible mainly for operation functions. (c) The departments are
established based on various combinations of the above. For example, the manufactur-
ing department is responsible for both operation function of production management as
well as engineering functions (i.e., process and equipment engineering projects).
53 Management and Modes of IC Manufacturing Enterprises 997

Collaboration Groups

Collaboration group includes technical support, quality assurance, material,

power and facility, etc. (a) The technical support department is mainly responsible
for the customer support on chip design services, mask-making, failure analysis
(FA), etc., offering proper process technologies and process flow to the
manufacturing department according to customers’ demand, conducting the tech-
nology management and maintenance for the online products with standard
technology, and developing new process and product technologies. The technical
support department may include functions of technology R&D, product (yield),
technical services, process integration, etc., where the new technology R&D and
process integration departments may be independent or under the manufacturing
group in some companies. (b) The quality assurance department is mainly respon-
sible for establishing the quality assurance system, quality control of production,
and management process. The IC production has the characteristics of multiple
process steps, long process time and production cycles, etc. During the production
process, it is almost impossible for any step to rework except the lithograph
process; hence the production quality must be guaranteed for each step. The
quality assurance department mainly includes functions of quality control (QC),
quality system (QS), quality engineering (QE), customer quality assurance
(CQA), reliability assurance and failure analysis (RA/FA), etc. In some compa-
nies, the CQA department may be lumped into the technical support or the
marketing/sales department; and the RA/FA department is merged into technology
department. (c) The material department is responsible for purchase and storage
management of key materials, for example, production materials, equipment,
spare parts, physical assets, engineering materials, office supplies, and living
facilities, etc. It includes purchase department, foreign trade department, ware-
house, etc. (d) The power and facility department is responsible for producing and
providing ultrapure water, nitrogen, oxygen, hydrogen, power conditions (e.g.,
electricity, compressed air, constant temperature, and humidity), specialty process
gases, as well as waste water and gas treatment, etc.

Administration Groups

The administration group mainly includes functions of general administration,

human resources (HR), financing and accounting (F&A), and environment/health/
safety (EHS), etc. with structures not very different from typical companies. Among
which, the EHS is particularly important as dangerous chemicals (e.g. inflammable,
explosive, toxic, and corrosive chemicals, special gases, etc.), high-temperature and
high-pressure equipment are used in the IC production; further, production staffs
regularly work in a relatively enclosed environment for a long period of time. Thus,
under these circumstances, the IC fab must pay extra attention to the management of
environment, occupation health, safety, etc.
998 X. Chen et al.

Strategy Management

The IC chip manufacturers (or chip-makers) have 2 types of business models, that is,
IDMs and wafer foundries, which are subject to different management strategies.
The strategy for development is the most essential as it leads the companies to
develop new technologies and products continuously, explore new market segments,
and enhance competitiveness with business growth.

Strategy Management of the IDM Enterprises

The IDMs are mainly divided into 2 types: one is to meet the needs of different
market segments with specialty technologies; and the other is to have its own end
products, that is, mainly manufacturing ICs for self-use. For the first type of
IDMs, the strategic development management mainly includes the following
4 aspects. (a) Continuously expand the product applications based on existing
specialty technologies. (b) Continuously develop more specialty technologies to
meet specific purposes for customers. (c) Produce the system-on-chips (SOC)
[1, 2] by integrating more ICs based on specialty technologies together with
customers. (d) Develop new products along the technology roadmap of “More-
Than-Moore” [3] to avoid the competition toward further scaling of “More-
Moore.” For the second type of IDMs, the strategic development management
mainly involves the following 5 aspects: (a) Through IC design, continuously
upgrade the existing products by improving performance and functions.
(b) Exceed customer expectations for developing new IC chips. (c) Integrate
different types of chips among end products into system-on-chips (SOC),
increase the market competitiveness of the products by further scaling the end
products and reducing the manufacturing costs. (d) Expand the end products for
different market segments and develop new types of products. (e) Develop new
IC chips along the 2 different development directions, that is, More-Moore’s law
and More-Than-Moore.

Strategy Management of the Foundry Enterprises

The wafer foundries typically offer manufacturing services with the main strategy of
focusing on the needs of chip design companies. It involves the following 5 aspects:
(a) Make full use of production capacity for reducing manufacturing costs.
(b) Continuously expand the standard processes to meet the design needs of various
customers. (c) Keep track of the most advanced manufacturing technologies in the
world to standardize IC manufacturing processes and use them in production.
(d) Continuously expand production scale for meeting customer needs. (e) Follow
Moore’s law for technology development and lead customers to design and develop
new products using more advanced technologies.
53 Management and Modes of IC Manufacturing Enterprises 999

In terms of technology development strategy for both IDM and foundry, the
strategy of More-than-Moore’s is accelerated when the product development is
behind the Moore’s law.

Planning Management

The overall planning management model is usually performed by the IC manufactur-

ing companies. The overall objectives are distributed to all levels in management,
from managers to front-line workers, so that all can strive their respective planning
objectives and tasks to ensure the realization of the overall objectives. The company
shall establish the first primary level objectives or key performance indicators (KPIs)
for sales income and profits; then divide the primary KPIs into the second level KPIs
for wafer output, sales volume, cost, and quality, and assign to the production line
and each functional department; the second level KPI can be further divided into the
third level KPIs for online wafer yield, single-wafer material cost, production cycle
time, overall equipment efficiency, on-time delivery rate, etc. For each specific KPI,
the responsible department or staff must be assigned. Each department shall set its
own targets according to the corresponding target distributed to them. For example,
the manufacturing department distributes the company’s second level KPIs for wafer
output, cost, and quality into the production cycle time, single-wafer material cost,
and online wafer yield; then it further divides these KPIs to the lithograph, etching,
thin film, and other engineering teams for the task, and further assigns them to the
responsible individual. According to the above method, the company can establish a
KPI network with vertical and horizontal hierarchical structures to realize global and
local organic unity.
Plans are divided into long-term, medium-term, and short-term plans. The exe-
cution and adjustment of each plan is a complementary process with optimization to
overall goals. (1) Long-term planning: After the preliminary long-term plan, it is
necessary to evaluate comprehensively whether it meets the company’s future
strategic development and profit expectations based on current production line
capacity. If not satisfying, it is necessary to adjust the plan and re-evaluate it. After
repeated adjustment and re-evaluation, then, it is possible to finalize a long-term plan
for both the future development and profit expectations as well as the actual situation
of the company. (2) Mid-term planning: The mid-term plan is first forecasted by the
sales department based on customer orders, and then it is evaluated using the
productivity model to formulate the schemes for new equipment configuration,
key capacity improvement, etc. If the above-mentioned measures cannot meet the
plan, the sales department is notified in time to make corresponding adjustments and
re-evaluation. Then, a proper midterm-plan is available. (3) Short-term planning:
The short-term plan includes an input and output plan within short term (e.g., next
month). The capacity management department shall evaluate the input plan and
coordinate with execution and manufacturing teams on the capacity resources in
1000 X. Chen et al.

order to guarantee smooth execution of the input plan. The output plan is realized by
both the execution and manufacturing teams based on the delivery quantity, cycle,
and inline product status through tight controlling.
Finally, the plan assessment refers to the assessment of the execution of both
mid-term and short-term plans. The main KPIs of the mid-term plan are the timelines
of accomplishing the capacity extension program, while the main KPIs of the short-
term plan are the wafer production cycle time, on-time delivery rate, etc.

Technology Management

Technology management for IC manufacturing is mainly divided into process

module (or unit process) management and product management as interrelated
through the process flow.

Module Management

It is also called the unit process management. In fab, there are many process
modules, for example, diffusion, lithograph, etching, implantation, and thin film.
Each step in the process flow has only one process condition for achieving the
specific process results. The module management shall include both hardware and
software management. The hardware management for production equipment
includes the startup, shutdown, recipe compilation, repair and maintenance, and
spare parts. The software management includes preparation of SOP, training, main-
tenance of mature process, development of new process, formulation of the material
specification, fabrication of tooling and fixtures, statistical process control (SPC),
and the assessment of capacity and efficiency, etc.

Product Management

It covers from product development to mass production and can be divided into
4 stages: development, manufacturing design, process design, and freeze and mass-
production. (1) Development: Firstly, a product owner will confirm customer’s
requirements and establish a project team, development plan, initialization report,
processing flow chart, a list of materials, equipment, and facilities required for
development. Secondly, the owner will ensure the product complying with the
requirements for EHS and Hazardous Substance Process Management (HSPM) and
identify particularities of the product during processing in fab. Lastly, the owner will
also make plans for purchasing new equipment and new materials, new process
development, and evaluation of reliability and process capability. (2) Manufacturing
design: The owner will document design rules, prepare device cross-section, confirm
layout design, follow up mask-making, and ensure the delivery of engineering lots.
The new processes, equipment, and materials need to be confirmed by auditing the unit
53 Management and Modes of IC Manufacturing Enterprises 1001

process development reports, new equipment acceptance reports, and test reports, etc.
Not only that, but the control plan, process flow, Incoming Quality Control (IQC)/In
process quality control (IPQC)/Outgoing Quality Control (OQC) and Chip Probing
(CP)/wafer acceptance test (WAT) specs will also be well documented. (3) Process
design: After the engineering lots are smoothly into production, the owner will prepare
the product datasheet and engineering lot summary reports, obtain the customer’s trial/
approval report, update the process flow, IQC/IPQC/OQC and CP/WAT specifications
and control plan, complete the Failure Mode and Effect Analysis (FMEA) form,
analyze the product’s cost and capacity, make a mass production plan, etc. (4) Freeze
and mass-production: When all of the above documents are frozen and standardized,
the product is ready for mass production.

Quality Management

Quality management mainly includes quality control in chip development, chip

production, cleanroom control, and standardization, etc.

Chip Development

Quality control is required for each stage in the chip development process. (1) Project
planning phase: When proposing the development target spec and feasibility eval-
uation, the IC chipmakers shall communicate fully with the customers, set the
development objective, make quality control plan, and secure quality demands for
materials, equipment, tooling, and other related resources. (2) Product design phase:
During the design of experiments (DOE) and layout drawing, the engineering
specifications, technical standards, and packaging standards, etc., shall be well-
prepared. (3) Process development phase: The quality evaluation for sample making,
trial batch, engineering lot, and other production-line products shall be performed,
then submitted to customers for trial samples. (4) Finalization phase: After the final
batch is qualified through trial production and approved by the customers, the
process technologies and product standards are finalized as described in the docu-
ments and submitted to customers for review and the product quality and quality
management process is accepted. (5) Mass production phase: After being approved
by the quality review, the documents for mass production are delivered to the
production department. The products are subject to quality control.

Chip Production

Due to the long process of IC manufacturing, it is necessary to perform quality

management for production in order to ensure qualified products are produced. The
quality management for chip production includes automatic production, standard-
ized operation, monitoring and measurement of production process, non-conformity
control, environment management, equipment/tooling management, management of
1002 X. Chen et al.

monitoring and measuring equipment, process change management, etc. The chip
manufacturing process is controlled by means of offline and online SPC. An offline
SPC is used to monitor the technology, process, and testing equipment; while the
online SPC is used to monitor process parameters. The production process control
lead to the optimal yield with good quality. For each SPC-controlled item, the
process quality shall be evaluated regularly, and each responsible person shall
analyze these items and trigger actions for continuous improvement.

Clean Room Control

To ensure the environment in the clean room meeting stringent requirements, real-
time monitoring shall be performed for the temperature, humidity, cleanliness, air
pressure, antistatic property, and other relevant parameters of the cleanroom. The
temperature/humidity and other parameters of the warehouse are also controlled to
guarantee the storage conditions for materials and chemicals meet the relevant
requirements [4, 5].

Standard

The standardization refers to the preparation, execution, and management process,

and economic performance. As the process technologies differ greatly for different
products, it is necessary to prepare corresponding technical standards, such as the
materials standards (for Si wafer, chemical, conventional gas, special gas, or other
materials), process standards (for lithograph, etching, and diffusion), technology
standards (for design rules, process procedures, product test, and reliability test); as
well as environment standards (for cleanroom particles, temperature/humidity, anti-
static property, air supply/discharge, etc.).

Marketing and Sales Management

The IC manufacturing is a service-oriented business. With the development of the

information technology (IT), both the IDMs and wafer foundries understand the
importance of “customer satisfaction”; thus, the key policy of marketing and sales
(M&S) management is to continuously enhance and focus on customer demands.
The customer demand management of the foundries includes the technical
consultation services at early stage, customer property/technical document manage-
ment, communication during the foundry process, and failure/reliability analysis for
foundry products through close coordination with customers. The foundry product
design rules, process conditions, technical standards, and test standards shall be
subject to full communication and demonstration; the foundry product documents
and properties provided by the customer (e.g., masks) shall be properly managed and
protected; during the foundry process, the enterprise shall communicate with cus-
tomers about the product progress, abnormal processes, etc.; after the product is
53 Management and Modes of IC Manufacturing Enterprises 1003

manufactured, the foundry shall assist the customer in the product failure and
reliability analysis (FA and RA), and jointly negotiate the improvement measures,
etc. For the special demand and expectation from the customers, the foundry shall
organize the related departments to review.
The customer demand of the IDM chipmakers or IC design houses is to obtain a
satisfactory chip product and services. When making the marketing strategies, full
considerations shall be made to the demands of interest groups, for example, design
houses, distributors, and end users. (1) Design houses’ demand: The IDMs must
pursue constant development and profit. At the market incubation period, it is
necessary to improve the market recognition of new products; at the market growth
period, the enterprises will develop various types of the product series, do better and
more than the competitors, and complete the sales channel and distributor excitation
methods; at the market maturity stage, the IDMs will continuously launch new
products and introduce promotional policies aimed at different customer groups; at
the market declining stage, the investment shall be recovered as quickly as possible
and new product application shall be expanded. (2) Distributor’s demand: IC
products have wide applications, and the establishing of distributor’s channel is
one of the important strategies for marketing. IDMs can help distributors manage
chip applications for end users to meet the needs of distributors. (3) End users’
demand: IC products are applied in specific end applications; therefore, it is needed
to collaborate with customers for developing new applications and market, and to
continuously satisfy the end user’s demand.

Cleanroom Management

The cleanroom management includes particle management, temperature/humidity

management, and anti-static management.

Dustproof Management

Particles in the cleanroom environment may lead to failure of ICs, degrade product
quality and yield. Therefore, the cleanroom for IC production has strict particle
control requirements. (1) Cleanroom personnel management: Systematic manage-
ment is performed for the staff uniform and behaviors; for local high-level
cleanrooms, the number of personnel entering the cleanroom shall be restricted.
(2) Clean uniform management: Purchase, production, usage, and cleaning of the
cleanroom uniform must be strictly controlled. (3) Clean room logistics manage-
ment: Both the material entry system for accessing the cleanroom and the standard
material clearing and cleaning management system shall be established.
(4) Cleanroom equipment and tooling management: the specific management system
for the entry and exit of equipment, tools, and machines shall be established.
(5) Particle control: It is necessary to prevent the ambient gas from entering the
cleanroom, in order to guarantee the gas pressure in the cleanroom is positive to
1004 X. Chen et al.

outside, gas pressure in the high-level cleanroom areas is positive to the low-level
cleanroom areas, and the air exchange rate, fresh air amount, and exhaust air rate
meet the requirements.

Temperature/Humidity Management

In the IC chip manufacturing process, the temperature/humidity of the chip

production environment must be maintained within proper limits. When the
temperature variation is large, especially in lithography step, error may occur
due to thermal expansion of equipment, tools, mask, Si wafer, etc., and impact the
product yield. The cleanroom also has strict requirements on humidity. If
the humidity is too low, static electricity may occur, and the IC chips may be
damaged in case of improper handling; if the humidity is too high, water film may
build up on the surface of the Si, resulting in poor adhesion of PR and poor fine
line patterns. The temperature/humidity criterion for the cleanroom shall be set
based on different production processes. The temperature/humidity control ratio
in the lithograph area is relatively high. The cleanroom is usually designed with
fresh air handling unit, fan filter unit, and dry coil unit in order to meet the
temperature/humidity requirements for the cleanroom. The temperature/humidity
control management in cleanroom is performed by online monitoring, real-time
monitoring, etc.

Anti-Static Management

IC chips are easily damaged by electrostatic charge; especially at the back end of
chip manufacturing, chip testing, and packaging stages. The operation area of the
cleanroom for IC manufacturing shall be anti-static. The anti-static floor is used with
Cu sheets completely connected together with the ground; and the building structure
is set at the wall and beam-column positions. The production equipment, instrument,
workbench, and materials shelf must be grounded with ground chains dragged on the
ground. Resistance measurements between 2 points of the anti-static floor and
between any point of the anti-static floor and the floor shall meet the specified
requirements.

Materiel Management and Control

The material management in the IC manufacturing industry has the characteristics of

a large quantity of import materials, high material value, high purity, high hazard,
large variety, small batch, short shelf time, special requirements for transport and
storage, even requiring the purchase license, transportation license, etc. IC
manufacturing industry also has a higher requirement on stability and uniformity
53 Management and Modes of IC Manufacturing Enterprises 1005

of material quality and supply capacity than other industries. Material management
includes material control management and warehouse management.

Material Control Management

Material control management mainly includes the following 8 aspects. (1) Strictly
control the material types; establish comprehensive material purchase standards; and
control the increase or change of material specifications by strict review. (2) Deter-
mine the material procurement cycle, and supply the materials required for produc-
tion from time to time according to the demand of procurement cycle and production
to satisfy the demand of materials. (3) Control material procurement price, with
annual price-reduction goal. (4) Control the quality of the vendors’ material to be
good and stable. (5) Strengthen the management work of material receivers/distrib-
utors, improve the staff’s efficiency, and guarantee the material first-in first-out to
prevent any occurrence of idle stock and waste materials. (6) Establish the proper
safe inventory and reduce the asset overstock according to the material usage
amount, frequency, and procurement cycle during the production. (7) Establish
performance appraisal system for material management team for improving staff’s
enthusiasm and initiative. (8) Properly invest the warehouse equipment and reason-
ably utilize the warehouse resources and storage space.

Inventory Management

Vendor managed inventory (VMI), safe inventory, and procurement plan are adopted
for inventory management and control, including the following aspects. (1) Procure-
ment plan control: Determine various material demand plan based on the production
plan and ensure company’s uninterrupted production by using the safe inventory
technology. (2) Material plan: Prepare the material plan per the delivery schedule
based on the production plan. (3) Procurement: Control suppliers to deliver at the
right place with agreed quantity and time at a reasonable price, and ensure that there
are 2 or more suppliers of key materials. (4) Statistical analysis: Collect, categorize,
and analyze materials data, forecast price trend, find substitutes, and evaluate the
supplier’s supply capability. (5) Quality control: Perform material inspection and
qualify materials. (6) Material receiving/distribution: Perform the actual receiving
and processing of materials, verify goods, and notify the quality department or the
use department for quality inspection of incoming materials; then send materials to
the storage or location of use. (7) Warehouse management: Chemicals need special
warehouses and double-lock management; many materials have temperature/humid-
ity control and ventilation requirements; highly toxic products need to be monitored
by networking with local authority of public security. (8) Warehouse control:
Periodically check the material entry/exit status, control of inventory in stock in
real-time, perform inventory regularly, notify abnormal situation in time.
1006 X. Chen et al.

Equipment Management

IC manufacturing equipment is the most important part of fab, thus the equipment
management procedures need to be well performed in inspection, maintenance,
repair, and preventive maintenance, etc., to ensure the best condition for manufactur-
ing and technology stability [6, 7].

The Equipment Inspection

It mainly refers to the check and inspection of equipment power conditions and
parameters as per the specs. In case the specified requirements are not met, the
equipment shall shut down immediately, and notify equipment engineers or man-
agers for disposition or repair.

The Equipment Maintenance

It can be classified into 3 types: (a) Scheduled maintenance, including maintenance of

transmission parts of equipment (such as lead screw, bearing, and belt of the transmis-
sion system), implanter beam maintenance, etc. (b) Conditional maintenance, that is,
the maintenance cycle is determined by the number of wafers processed. This is related
to the reactants and by-products produced and deposited in the internal structure of the
equipment (i.e., the process chamber), and if accumulated thick enough, further
impacting the chamber characteristics (e.g., particles, uniformity, film thickness,
critical-dimensions, etc.) and equipment parameters (such as power, leak rate, vacuum,
flow, etc.). The maintenance of Etching chamber, Chemical Vapor Deposition (CVD)
chamber, Low pressure CVD (LPCVD) chamber, and epitaxial chamber are classified
as conditional maintenance. (c) The combination of the above. As the failure of certain
key parts is relevant to both service time and reactants of equipment, scheduled and
conditional maintenance is to be triggered whenever a condition is met.

Equipment Repair

It mainly refers to troubleshoot by the service engineers based on equipment

principle, structure, and other knowledge and skills, there are 3 types including
condition-based overhaul, posterior maintenance, and active maintenance. (a) The
condition-based overhaul means the process control alarm system (e.g., SPC
control). Equipment parameters are input into the system daily and alarm limits
are set from the trending of key parameters of equipment status. In case of
deterioration, it is necessary to repair the equipment in time. (b) Posterior mainte-
nance refers to unscheduled repair after the occurrence of an equipment fault. The
repair efficiency can be improved with daily full preparation of labor, spare parts,
tools, etc. (c) Active repair refers to the repair work for the equipment with
53 Management and Modes of IC Manufacturing Enterprises 1007

high frequency of fault occurrence or too high service cost of some components.
The components need to be improved at the design stage for minimizing fault
frequency and maintenance costs.

Preventative Maintenance

It refers to the repair or replace components by utilizing early detection techniques

and statistical analysis in order to keep equipment in best working condition.
Preventative maintenance has lower maintenance cost, less impact of equipment
failure on normal production, and increase equipment utilization. The preventative
maintenance items of key equipment can be carefully identified by analyzing
maintenance data in fab database.

Equipment Maintenance Management

The main indexes include: the inspection completion rate, maintenance completion
rate, up-time, mean-time-to-repair (MTTR), mean-time-before-failure (MTBF),
wafers-per-hour (WPH), overall equipment-efficiency (OEE), etc., where the equip-
ment efficiency is used to reflect the overall equipment maintenance and operation
capability. The future equipment maintenance management is certainly to reduce the
equipment repair frequency and time and improve capability for equipment mainte-
nance, etc., by more automated detection, modularized parts or components, and
fully utilizing advanced techniques, for example, big-data analysis.

Waste Material Treatment Management

Waste gas, wastewater, and hazardous waste are the main waste materials generated
from IC manufacturing. (1) Waste gas mainly includes acidic waste gas, alkaline
waste gas, organic solvent gas, as well as a small amount of process tail gas and
ordinary waste gas (heat). After the waste gases, that is, acid-base, organic, process
tail gas, and ordinary exhaust waste gas, are treated, respectively, the gas is
discharged into the high atmosphere. Ordinary waste gas (heat) is emitted from the
roof of the fab; the acid-base waste gas and organic waste gas shall be emitted from
the exhaust funnel into a height of at least 15 m (for different pollutants, the
requirement on emission height may be different). (2) The wastewater shall be
recycled by category and treated separately. There are various kinds of wastewater,
including acid-base, ammonia-containing of low to medium concentration,
F-containing, and organic, which shall be collected separately. Different kinds of
wastewater enter into their respective treatment systems separately, that is, acid-base,
ammonia-containing, fluoride-containing, and organic wastewater systems, respec-
tively. CMP grinding wastewater, waste gas scrubbing tower drainage water, RO
concentrated wastewater from pure water station, cooling tower circulating water
1008 X. Chen et al.

drainage, and other ordinary wastewater shall be treated in the ordinary wastewater
system. After meeting the national standard emission requirements, the treated
wastewater is then discharged into the general wastewater treatment plant for
centralized treatment again. (3) Hazardous waste includes both liquid and solid
waste. The liquid waste is recovered and treated by category. Waste acid, high-
concentration ammonia-containing waste liquid, PR waste liquid, and organic sol-
vent waste liquid are collected through the waste liquid recovery system set on the
equipment, placed by category, and recycled by the environmental service company.
The solid waste mainly includes mercury waste, wastewater treatment slurry, waste
packaging material, waste reagent container, electronic mixed waste, etc. The mer-
cury waste, mainly including the waste mercury-containing lamp bulbs, shall be sent
to the environmental service company for centralized disposition. The wastewater
treatment slurry, mainly including the slurry generated from treatment of
F-containing wastewater (main compositions are CaF2, SiO2) is dehydrated into
mud cake and transported outward. The mud cake belongs to ordinary solid waste
with low toxicity and can be sent to the eligible environmental service company for
disposition. The waste packaging materials mainly include waste packaging cases,
bags, cartons, plastic gloves, etc., and can be sold to waste recyclers. The waste
reagent containers (e.g., including glass, plastic products) are sent to the eligible
environmental service company for disposition or recycled by the original plant. The
electronic mixed wastes (including waste hardware, waste metal, etc.) belong to
ordinary solid waste and can be sold to waste recyclers. The principles of solid waste
disposal are comprehensive utilization, full recovery, maximum rational use of
resources, reduction of solid waste generation, safe and reasonable treatment, and
disposal.

Environmental Protection Management

The environment protection management includes the prevention from the sources,
process management control, inspection evaluation, hazard rectification and acci-
dent/incident investigation and treatment, and emergency responses. (1) Prevention
from the sources refers to analysis and evaluation for any wastewater, waste gas,
noise, soil pollution possibly generated in the past, at present, and in the future under
normal, abnormal, and emergency situations through identification and evaluation of
environmental factors. The environmental factors are subject to level-to-level man-
agement using proper evaluation method based on certain rules and regulations to
establish and implement control measures for reducing the environmental risks by
order of elimination, substitution, engineering control, sign/identification, etc.
(2) Process management control means that the environmental protection is
implemented and executed according to the enterprise environmental protection
management measures, operation of pollutants treatment facilities, environmental
safety and emergency disposition, online pollution monitoring, pollutant detection
analysis, and other management documents. (3) Inspection evaluation refers to the
evaluation and appraisal for the source and process of the environmental protection
53 Management and Modes of IC Manufacturing Enterprises 1009

management of the environmental responsible department by establishing the up-

to-standard environmental evaluation system, with the evaluation results linking
directly to the department performance. The environmental protection manage-
ment department shall perform regular or irregular inspection according to the
checklist of standard environmental items, with the inspection results regarded as
one of the bases for the process appraisal. (4) In terms of the hazard rectification
and accident/incident investigation, the environmental hazard troubleshooting
system with checklists is established from the aspects of environmental protection
and treatment of waste water, gas, solid, noise, etc. A special personnel is assigned
for daily environmental inspection, and any hazard found shall be eliminated or
rectified in time by the relevant department according to the hazard level. The
effect of rectification is subject to evaluation as per the up-to-standard environ-
mental evaluation system. The enterprise field management personnel shall
arrange a specialist to track the rectification and verification of the environmental
hazards found during patrol inspection, followed by performance appraisal.
(5) Emergency responses refer to the practical 3-level emergency plan as
established in accordance with the relevant laws, regulations, and requirements
in the National environmental protection emergency response law. Emergency
drills are conducted regularly or irregularly and jointly with relevant governmen-
tal agencies, surrounding companies, or even residents if it is necessary in order to
improve the response capability of personnel.

Safety Management

The IC manufacturing line is in a closed cleanroom with complicated processes and

using various types of hazardous chemicals and specialty gases, hence their safety
management system is different from ordinary manufacturing industries. The safety
management includes safe production management, occupational health manage-
ment, fire safety management, and accidents emergency management, etc.

1. The safe production management mainly consists of the safe production

responsibility and organizational system, source prevention and control sys-
tem, supervision inspection and objective up-to-standard evaluation system,
accident survey treatment system, equipment facilities safe management sys-
tem, hazard assessment and rectification system, and emergency response
system. In view of various hazardous chemicals and the corresponding equip-
ment and facilities in production, the effective risk identification and preven-
tion control measures are built and perfected, and safety management
responsibilities are implemented with regular supervision, inspection, and
appraisal; the safety approval procedures for new equipment, new materials,
and new processes are strictly implemented to control the risks from the
sources and reduce the accident risks.
1010 X. Chen et al.

2. The occupational health management refers to the prevention, control, and

elimination of occupational hazards for protecting employee’s health from harm-
ful factors. The related occupational harmful factors are more complicated than
ordinary industries, involving various types of hazardous chemicals. All kinds of
new process, material, and equipment are continuously put into production.
Hence, it is necessary to identify and control the occupational harmful factors
with more flexibility and effectiveness. The IC manufacturer shall identify,
prevent, and detect harmful factors regularly in the entire production, workers,
production environment, and workplace, so as to ensure that the occupational
exposure limit on the production site is qualified.
3. The fire safety management means that the effective fire prevention and
extinguishing system is established through research on occurrence and develop-
ment of fire incident according to laws and regulations and technical standard of
firefighting. As flammable and explosive chemicals, pyrophoric material, strong
oxidant, corrosive chemical, and other hazardous chemicals are involved in the IC
manufacturing, there exist high-temperature, high-pressure, and other dangerous
factors in the equipment. The complicated air supply/exhaust ducts are laid in the
clean room, which lead to high complexity and risk in the work of fire control, so
the operation of automatic fire alarm system, sprinkler system, gas fire-
extinguishing system, and gas detection alarm system must be ensured. The fire
extinguishers suitable for the pyrophoric substances are provided on site, with
various firefighting detection and personnel training at fixed schedule. The
technical preventive measures are taken in the electric fire prevention areas,
explosion-proof leakage-proof and cleanroom areas with respect to air supply/
ventilation pipe fire prevention, bulk combustible gas fire prevention, and harm-
ful chemicals fire prevention, coupled with the regular fire inspection personnel to
prevent and extinguish fire.
4. Emergency management mainly refers to rapid responses and effective disposi-
tion after the production accidents occurred, and to control and minimize any loss
caused by accidents. As a large amount of dangerous chemicals and specialty
gases are used in the production, the IC manufacturer must control and eliminate
any safety accidents at the early stages of the occurrence to prevent the accidents
from expanding further, which may result in serious consequences. First of all, the
manufacturer should make full preparation for any accident at the construction
stage, set and install various fire safety and emergency measures during the
plant’s construction, deploy the emergency apparatus and materials suitable for
the site; second of all, the accident emergency rescue plan suitable for the on-site
production process and equipment shall be prepared and perfected (e.g., fire,
dangerous chemical leakage, and sudden power failure emergency plans). The
detailed site emergency disposition plan must be made; at last, a relatively
professional emergency response team (ERT) must be organized; various emer-
gency skill training must be carried out, and various accident emergency drills
must be conducted at a fixed schedule with a summary of the drill and accident
disposition experiences and continuously bring to perfection the emergency
rescue plans.
53 Management and Modes of IC Manufacturing Enterprises 1011

Information Security Management

The informational security risks faced by IC manufacturers mainly include virus,

network attacks, information leakage, etc. Computer virus infection will cause
network congestion, system breakdown, and data and file corruption (or even
missing or leakage), resulting in immeasurable loss of company’s important files
or data. It is deemed as the prime security threat among all kinds of information
security issues. The interconnection of the company information systems is in favor
of transmission of the company data, such as e-mail system, office automatic system,
manufacturing execution system (MES), and SPC system. However, it also sets high
requirements on the network security protection, defense of network attack risk,
protection of company information system, and information data security. In terms
of information leakage, with the interconnection of the office automation and
company information system, the product design file, process parameters, and
production management data are faced with all safety risks during the transmission
of Intranet and Internet, for example, the data validity and availability are affected in
case the data are intercepted by illegal users, disclosed by internal employees, or
illegally modified.
To remove all information security risks, the IC manufacturers must establish a
complete information security protection system, including the following:
(1) Performing the information security risk evaluation: The chipmakers shall
perform the comprehensive information security risk evaluation according to the
actual enterprise condition, with reference to ISMS ISO27001 or national manage-
ment measures for classified protection of information security, rely on the aid of the
external security consultant companies when necessary to make a list of the safety
risks and shortcomings, establish the security strategies, and revise the information
safety-related systems. (2) Perfecting and improving the information security man-
agement level: The information system security is dependent on the network security
strategy and management strategy used when the system is selected, which is
inseparable from the well-established management systems. On the basis of perfect
information security tools and technical means, a series of rules and regulations, such
as office network access, IT terminal security and confidential document manage-
ment, are established to guide information security work. (3) Building the informa-
tion security protection system using advanced technologies: In view of various
information security hazards, information security planning and corresponding
solutions are established and implemented. For the office information system, the
corresponding protection system shall be established, such as terminal management,
IPS intrusion defense, and disaster recovery management systems. In terms of the
data security protection in the chip-making process, the company shall establish the
corresponding security system jointly with the solution, for example, the parameters
of lithography scanners can be protected by using the built-in RFID sensor in clean-
room suit for identity recognition coupled with the equipment control terminal for
preventing unauthorized personnel from peeking the process parameters. For the
design technical file, the file encryption system is used to prevent the information
leakage from the source.
1012 X. Chen et al.

The management of information security of the IC manufacturer [8–10] is a long-

term, complicated, and systematic project, with information technology (IT), equip-
ment system, mechanism and management, and many other aspects. The solutions
for information security must be planned and implemented in a systematic manner in
order to ensure confidentiality, completeness, and effectiveness of the company
information.

References
1. S. Tripathi, C. Moha, System on chip design and its future challenges. J. Crit. Rev. 7(1),
723–727 (2020)
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2010)
3. More-than-Moore White Paper, 2022 Update Version, International Roadmap for Devices and
Systems
4. Cleanroom Cleaning, Gowning, and Maintenance- Procedure, Contamination Control, and ISO
Protocol, Production Automation Corporation. https://blog.gotopac.com/2018/01/26/
cleanroom-cleaning-procedure-contamination-control-iso-14644-1-protocol/
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procedure, in Handbook for Critical Cleaning, ed. by B. Kanegsberg, E. Kanegsberg, 2nd edn.,
(CRC Press, 2011), pp. 103–118
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 Section VII
Packaging and Testing of IC Products
Keyun Bi, Xiekang Yu, Hongwei Sun, and Daquan Yu

Introduction

The packaging and testing (PT) industry is indispensable in IC industry chain.

Recently, under the promotion of “Outline for promoting of national IC industry”
and “National investment fund of national IC industry,” the development of PT
industry in China has progressed rapidly. Conventionally, the functions of packaging
include the supporting for mechanical protection, electrical signal transmission,
power distribution, and thermal management for ICs. With the development of IC
technology, the package of IC plays new roles in integration of multiple functions
and testing of complex system-in-packages (SiP). With the development of
advanced packaging technologies, the wafer-level-packaging (WLP), system-in-
packaging (SiP), three-dimensional (3D) packaging, etc. are rapidly emerging
toward further miniaturization of electronic system and enhancement of reliability.
By continuously supporting from National Major Science and Technology Projects,
the capability and technology of packaging and testing have progressed significantly
toward high-end products for overall IC industry. By reading this Section, readers
are systematically expected to become familiar with the status of packaging and
testing industry, key processes for both traditional and state-of-the-art packaging
technologies, and in-depth understanding of the packaging and testing, reliability,
standardization, etc. Sincerely, we would like to express our great appreciation to all
the authors, reviewers, related organizations, translators, and individual friends, who
have made this Section with great quality.
Development of Packaging and Testing
Industry 54
Jian Cai, Guoliang Yu, Hongwei Sun, Jian Wu, and Lin Tan

Contents
Developing of Global PT Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
The Status and Characteristics of PT Industry in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
The Collaborative Innovation of PT Industry Chain in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Main Business Model of Global PT Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
The PT Business of Major Global IDMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
IBM Microelectronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
Intel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Samsung Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Semiconductor PT Research Institutes in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Universities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Research Institutes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024

Abstract
IC packaging increasingly plays a more important role in the More-than-Moore
era. Wire bonding, flip chip, and through-silicon-via (TSV) are mainstream
interconnection technologies since the 1960s. System-in-Packaging (SiP) was
proposed in the early 2000s and is becoming popular in industry. The Packaging
and Testing (PT) industry in China has developed very quickly in the last
15 years. There are different collaborative innovations, such as new cooperation

J. Cai (*) · L. Tan

School of Integrated Circuits, Tsinghua University, Beijing, China
e-mail: jamescai@tsinghua.edu.cn
G. Yu
TongFu Microelectronics Co., Ltd., Nantong, China
H. Sun
National Center for Advanced Packaging Co., Ltd., Wuxi, China
J. Wu
National Technology Innovation Strategic Alliance for IC Assembly and Testing, Wuxi, China

© Publishing House of Electronics Industry 2024 1015

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_54
1016 J. Cai et al.

models of Industry-University-Research, strategic alliance for IC assembly and

testing, establishment of technology research center, etc. With these innovations,
the PT industry has expanded rapidly and gradually integrated with leading edge
technologies. According to CSIA, the revenue of Packaging and Testing is about
one-third of the whole semiconductor industry in China. There are two major
business models in PT industry all over the world. One is the PT factories being
subordinate to the integrated device manufacturers (IDMs), and the other is
independent PT houses also known as Outsourced Semiconductor Assembly
and Testing (OSAT). In China, some universities and research institutes are
working on packaging technologies for contributing to industry promotion.

Keywords
Packaging and testing · More-than-Moore · IDM · OSAT · Business model ·
Collaborative innovation

Developing of Global PT Industry

As an indispensable link in the Integrated circuits (IC) industry, IC packaging

(or assembly) and packaging and testing (PT) industry has been progressed with
the advancement of IC technologies. Traditionally, packages serve for supporting
ICs (e.g., mechanical protection, interconnection and extraction of electrical signals,
power distribution, and thermal management, etc.); packaging also offers new
functions with the development of silicon technology in system integration. From
the perspective of package types, the early package technologies mainly include
metal Transistor Outline (TO) package and Ceramic Dual-In-line Package (CDIP),
both belonging to Pin-Through-Hole (PTH) package type. For advanced IC tech-
nologies, higher packaging density is needed, leading to the development of more
package types. Since the early 1990s, dual-in-line through-hole package has grad-
ually transferred to surface mount package type. Typical package types include
Small-Outline-Package (SOP), Quad-Flat-Package (QFP), Ball-Grid-Array (BGA)
package, and so on. With the development of advanced technologies, wafer level
package (WLP), 3-dimensional-package (3DP), and system-in-package (SiP) have
emerged recently. Distinction between the package types and technologies is increas-
ingly blurred. According to the interconnection method between chips and packages,
they are usually referred to as wire bonding (WB), tape automated bonding (TAB),
flip-chip (FC), and through-Si-via (TSV) technology [1, 2], etc.
Traditional package technologies mainly utilize the lead-frame as carrier and wire
bonding for interconnection (e.g., DIP, SOP, and QFP); then the combination of wire
bonding interconnection and package substrate appeared (e.g., BGA, Land Grid
Array (LGA), etc.); and later the flip-chip technology on package substrate (e.g.,
FC-BGA) was implemented.
International Semiconductor Technology Roadmap (ITRS) has clearly proposed
two directions for future IC technology development: More Moore (as the
54 Development of Packaging and Testing Industry 1017

continuation of Moore’s law) and More-than-Moore (as the extension of Moore’s

law). Along the technical roadmap of More-than-Moore, there is increasing attention
on the integration of multiple functional ICs in SiP, including information processing
chips (e.g., Central Processing Unit (CPU), Micro Control Unit (MCU), memory,
etc.) and information interaction chips (e.g., radio frequency ICs, sensors, etc.).
Therefore, system-in-package (SiP) [3–5] has become one of the mainstream tech-
nology paths for system integration.
According to recent statistics, the total revenue of global packaging and testing
(PT) industry is about USD$50 billion in 2016. IC Insights estimated that revenue of
PT industry (also referred to as Outsourced Assembly and Testing, OSAT) accounted
for 55% of the total, which essentially reflected the scale of the global PT industry
and its proportion in the IC industry chain. Currently, in the global PT industry,
companies in Taiwan China have the leading positions, and companies in Mainland
China have made remarkable progresses.

The Status and Characteristics of PT Industry in China

China IC packaging and testing (PT) industry plays a key link in national IC industry.
Among China’s 3 major aspects of IC industry, that is, IC design, IC manufacturing,
and PT, the PT industry is about 33.6% in 2018, slightly higher than the international
average. In recent years, China’s PT industry has grown rapidly. The sales revenue
increases from more than RMB¥100 billion in 2013 to more than RMB¥190 billion in
2018, with an average annual growth of about 19%. The distribution of PT companies
in China is mainly located in Yangtze River Delta, Pearl River Delta, and Beijing and
Tianjin in Bohai Gulf areas. Due to the geographical advantages of Xi’an and Chengdu
cites, the PT industry in the mid-west regions is also developing rapidly. According to
statistics, by the end of 2018, there were 99 large PT companies in China.
From the perspective of market applications, the growth of China’s IC market is
mainly driven by the computer, network communication, consumer electronics,
automotive electronics, industrial control, and other markets. Driven by the Internet-
of-Things (IoT), Cloud Computing, Big Data, and other related industries, China’s
construction of data centers continues to boom with strong demand for servers,
storage, and other products. The production and sales of consumer electronics and
traditional home appliance remains stable. Driven by the trend of consumption
upgrading and home appliance intelligentization, the IC market has grown slightly.
The growth of smart mobile devices (as represented by smart bracelets and watches)
is the main driving force to the market.
The medium and high-end package products (e.g., BGA, Chip Scale Package
(CSP), WLP (WLCSP), FC, Flip-chip ball-grid-array (FCBGA), Flip Chip Chip
Scale Package (FCCSP), and SiP, etc.) have achieved mass production in China’s PT
industry. According to incomplete statistics in 2018, among the advanced IC prod-
ucts in China, there is about 34% using the medium and advanced packages; 40% in
advanced packages. In recent years, though the growth rate of smart mobile devices
(e.g., smart phones/tablets, etc.) that widely used medium and advanced packages
1018 J. Cai et al.

has slowed down, the demand for various advanced packages increases due to the
large volume of products and continuously increasing need of optimized device
capabilities.
It is widely believed that the Internet-of-Things (IoT) is the main driving force for
future semiconductor growth. In order to meet the IoT market, the IC industry needs
to have many key technologies, not only the IC Design and wafer manufacturing, but
also the PT with enhanced R&D in the advanced 3D and System-in-Package (SiP)
technology. Since various IC products are used in mobile phones, 3D packaging is
needed for size reduction. In the future, those PT companies with integrated system
package and module capabilities will win the market.
Through independent innovation and international cooperation, as well as con-
tinuous implementation of major projects, the Chinese PT companies have contin-
uously enhanced their capabilities in flip-chip, bumping, wafer level packaging
(WLP), and other advanced technologies. Certainly, from the perspective of the
overall situation, among the top 10 in global PT industry, there are only 4 Chinese
domestic and Sino-foreign joint ventures. In terms of advanced packaging technol-
ogy and process, the gap between Chinese local and international large companies is
still quite obvious. Therefore, China PT industry needs to make joint efforts to meet
the future market demand for a reasonable planning, constantly increase investment
on R&D, and enhance innovations. In the future, the Chinese PT industry continu-
ously collaborates with international companies and also performs mergers and
acquisitions (M&A) of overseas companies to leap in advanced packaging technol-
ogy for domestic and international market.

The Collaborative Innovation of PT Industry Chain in China

China IC packaging and testing (PT) industry chain is in leap-frog development

through collaborative innovation with policy’s guidance and government support.
PT industry has expanded rapidly and gradually integrated with leading-edge tech-
nologies. Key equipment and material manufactures are partially localized in China.
Collaborative innovations of China PT industry have the following aspects.
Firstly, the PT industry-wide collaboration is promoted through Industry-
University-Research model. During the 11th and 12th 5-year plan period, collabo-
rative R&D projects, as supported by the National Science and Technology Major
Project, were performed by IC designers, foundries, PT companies, equipment and
material suppliers, and universities and research institutes. Innovations have been
achieved and accumulated with less cycle time by tightly integrating the industry
chain through products. Innovative projects are collaboratively performed by
resources sharing and fully utilizing advanced packaging technologies as well as
co-optimization from design and products. This enables PT companies to have
unique and strong core competitiveness in advanced packaging technologies for
superior production and applications. The model promoted the collaboration
between the IC and PT industry for a sustainable development model.
54 Development of Packaging and Testing Industry 1019

Secondly, the industrial resource integration and upgrade of high-end value chain
is accelerated. National Technology Innovation Strategic Alliance for IC Assembly
and Testing (NAAT) was established in Beijing in 2009 for the purpose of promoting
the development of the PT industry chain. The alliance was originated by JCET
(Jiangsu Changjiang Electronics Technology), TFME (Tongfu Microelectronics),
and 27 other key organizations from PT industry with focus on manufacturing,
R&D, and education. The alliance organized a series of key collaborative OSAT
(outsourced assembly and testing) projects for VLSI technology and manufacturing
including key PT equipment and material projects for communication and multi-
media chips. These efforts have changed the long-term monopoly by international
enterprises and enabled Chinese manufacturers to participate in international com-
petition. The development of supporting industry such as PT equipment and material
is greatly enhanced. Currently, the alliance regularly invites experts and scholars to
analyze International Technology Roadmap of Semiconductor (ITRS) for exploring
future trend of PT industry, searching for breakthrough, and drafting roadmap of
equipment and material. China has made significant progress in R&D and industri-
alization of advanced packaging technology, equipment, and materials, and acceler-
ated the development toward high-end value chain.
Thirdly, National Center for Advanced Packaging (NCAP) Co. was established in
Sept. 2012 for promoting R&D of fundamental technology of OSAT. It is a joint
venture by Institute of Microelectronics (IME) of the Chinese Academy of Science
(CAS) and four other leading companies (JCET, TFME, Huatian, SCC). Since the
establishment of NCAP, the platform of the alliance has been focused on intellectual
property (IP) and R&D by considering the overall needs of PT industry. NCAP
developed many advanced high-density 3D packaging technologies, provided tech-
nology service to customers all over the world, played a globally leading role in
advanced technologies for IC packaging and system integration, and continuously
enhanced the advancement of the IC industry in China. Through the innovative
model of PT consortium, NCAP collaborates with renowned semiconductor com-
panies, end users, packaging and testing companies, as well as material and equip-
ment suppliers to form joint R&D teams. By 2018, a number of consortia have been
founded and made fruitful achievements. Among them, Material and Equipment
Consortium, including 12 members, evaluated and qualified their package solutions
for domestic and global markets. In addition, the Large Panel Fan-out
(FO) Consortium led by NCAP has contributed to the first domestic Fan-out-
panel-level-packaging (FOPLP) [6, 7] technology available and improved China’s
competitiveness in the global market. This innovative model has made a beneficial
exploration and attempt for joint R&D of key technologies for PT industry.

Main Business Model of Global PT Industry

According to the operation model, global PT companies are mainly divided into two
categories, namely, the PT factories subordinate to the vertical integrated device
manufacturers (IDMs), and the independent PT (or Outsourced Semiconductor
1020 J. Cai et al.

Assembly and Testing, OSAT) houses. IDM owns its own IC products, and its PT
houses usually only serve its own IC products. OSAT has no IC products of its own,
and can provide services for other companies (including fabless design houses and
wafer foundries). According to the statistics in recent years, the global market of
IDM and OSAT is essentially equivalent to each other. However, in general, revenue
and market share between IDMs and OSATs are rarely compared and ranked. IDMs
have a complete supply chain from IC design, manufacturing, and PT, while OSAT
needs to form a complete supply chain with fabless and foundries to achieve their
own operations. IDMs may also be suppliers to other design companies or foundries.
Sometimes IDMs choose to work with OSAT to complete a large number of mature
PT works.
In addition, the traditional wafer foundries generally form partnership with
OSATs or PT houses. There are new development of technologies emerged in
advanced packaging, e.g. wafer-level packaging, 3D integration with TSV inter-
connection, and innovative fan-out packaging. Some foundries began to enter the
PT field selectively, for example, Taiwan Semiconductor Manufacturing Com-
pany (TSMC) developed CoWoS (Chip-on-Wafer-on-Substrate) and Integrated
Fan-Out (InFO) technology to respond to the packaging needs. The operation
model and infrastructure between foundry and OSAT are different in that the gross
margin of foundry is higher than that of OSAT as an important factor for customer
selection. At the same time, if the design house chooses OSAT to complete its PT
services, it can usually choose two or more suppliers with different solutions. In
addition, OSAT has certain advantages for the manufacturing of SIP and system
integration products based on own capability of multiple packaging technologies
for IC chips.

The PT Business of Major Global IDMs

According to IC Insights, the revenue of IDMs PT business accounts for 48% of the
overall PT business in 2018 as illustrating the vital role of IDMs in PT business.
Some representative enterprises like IBM, Intel, and Samsung are included, which
have a long history and large scale.

IBM Microelectronics

It had PT business before it was acquired by Global Foundries in 2015. At

present, its PT business has been combined with the IT Infrastructure Service
Department. In the 1960s, IBM led the C4 (controlled-collapse chip connection)
technology development and the applications to flip-chip packaging. IBM, as a
pioneer in the PT industry, offers comprehensive PT services, especially with
large size and high complexity packages. Its turnkey solution includes material
 54

Table 54.1 Global top 10 OSATs in 2010–2016

Rank 2010 2011 2012 2013 2014 2015 2016
1 ASE ASE ASE ASE ASE ASE ASE
2 AMKOR AMKOR AMKOR AMKOR AMKOR AMKOR AMKOR
3 SPIL SPIL SPIL SPIL SPIL SPIL JCET
4 Statschippac Statschippac Statschippac Statschippac Statschippac Statschippac SPIL
5 PTI PTI PTI PTI PTI JCET PTI
Development of Packaging and Testing Industry

6 UTAC UTAC J-device JCET JCET PTI TSHT

7 Shinko Shinko UTAC J-device J-device J-device TFME
8 J-device J-device JCET UTAC UTAC UTAC KYEC
1021
1022 J. Cai et al.

analysis, design assessment, quick prototyping and mass production, supporting

IDM, OEM, etc. IBM has extensive experiences in advanced technologies. In
flip-chip packaging technology, IBM has optimized design and manufacturing
processes for single chip, multi-chip, large-sized complex structures, and high-
reliability applications. Package miniaturization with reliability improvement has
been realized through innovations in structural integrity, electrical performance,
thermal management, inter-connection and under-fill materials, substrate mate-
rials, and overall package design. IBM excels at packaging large die or multi-
components on large laminate platforms. Ceramic packaging includes lead or
lead-free solder materials for chip-on-substrate (COS) and package-on-substrate
(POS) inter-connection. In addition, CSP (Chip Scale Package) leads the industry
with larger footprints, which utilizes fully tested known-good-die (KGD) and a
proprietary bare die rework process in order to improve product yield. Leading
edge packaging is exemplified through innovations in Si photonics optical cou-
pling with an emphasis on automating the assembly of fibers and compliant
polymers to deliver a tightly aligned structure, and Si-based millimeter
(mm) Wave integration, etc.

Intel

Its PT business is affiliated in the custom foundry department with PT houses

located in Malaysia, China, and Vietnam. The PT center in Chengdu founded in
2003 is its largest package production base in the world and also one of the largest
chip package test centers of Intel, where half of the notebook computer chips are
produced. Intel not only provides various types and sizes of package products,
including standard Flip-chip ball-grid-array (FCBGA) [8–10] package, but also
provides solutions to different requirements (e.g., high-performance multi-chip
packaging and high-density CSP packaging). Intel is the global leader on multi-
chip-package (MCP) technology. It adopts high performance hybrid multi-chip
interconnection technology to reduce the cost of traditional 2.5D and 3D
approaches. The solutions overcome challenges such as performance, bandwidth,
and heat dissipation. The embedded multi-die interconnect bridge (EMIB)
[11, 12] developed by Intel is an innovative advanced packaging technology
which enables the interconnection of chips by Si bridge structure. The EMIB
technology results in lower cost and higher yield by eliminating the Si-interposer
and greatly reducing the manufacturing complexity of the high bandwidth and
multi-chip integration. At the end of 2015, Altera (acquired by Intel) launched
Stratix 10 DRAM SiP based on 14 nm node; this device efficiently integrates
high-performance FPGA and DRAM chips (SK Hynix’s 3D stacked broadband
memory, HBM2) in a single package by using EMIB. Its special structural design
meets the most stringent memory bandwidth requirement of high-performance
systems. Compared to the current discrete DRAM solution, Stratix 10 DRAM SiP
has a 10 times improvement in memory bandwidth.
54 Development of Packaging and Testing Industry 1023

Samsung Electronics

It is the largest subsidiary of Samsung group providing packaging service including

QFP, T-type Quad Flat Package (TQFP)/L-type Quad Flat Package (LQFP), Enhanced
Chip Carrier Package (ECP), Plastic Ball Grid Array (PBGA), Fine-Pitch Ball Grid
Array (FBGA), LGA, Fan-in Wafer Level Package (FI-WLP), Tape Carrier Package
(TCP), Chip on FPC film (COF), Chip on glass (COG), and so on. Its PT products
nearly cover the whole semiconductor devices, from application processer (AP) to
CMOS imaging sensor (CIS). As the only corporation which can provide the one-stop
service including wafer fab, testing, packaging, and memory integration (e.g., DRAM,
Flash, and low-power storage), Samsung, with a perfect ecological system, has absolute
predominance globally. Many world top packaging products have been made by
Samsung electronics for its leading R&D activities, for example, the largest fine-
pitch flip-chip packaging, the earliest mass production of high density DRAM with
TSV technology, the first AP product in SiP with TSV, the leading package-on-package
(PoP) in smart phone applications, and the highest capacity solid-state-drive (SSD)
with flash memory stacking technology, etc. Samsung proposed Widcon technology
(3D Stacking of AP and DRAM with TSV) in 2013. Samsung led mass production of
DDR4 DRAM based on TSV technology in 2014. In 2015, Samsung launched the first
embedded package-on-package (ePoP) memory with 3GB LPDDR3 mobile DRAM,
32GB embedded multi-media-card (eMMC) [13, 14] and controller integrated in one
package for the first time. Compared with embedded multi-chip-package (eMCP)
which can combine two packages, ePoP has a significant improvement.

Semiconductor PT Research Institutes in China

Semiconductor packaging and testing (PT) technology research institutions in China

can be roughly divided into universities and research institutes.

Universities

IC packaging is highly interdisciplinary. Depending on their own strengths, some

universities in China have performed long-term study in fundamental research and
application on IC packaging. In recent years, universities actively in this field
include Peking University, Tsinghua University, Fudan University, Shanghai Jiao
Tong University, Harbin Institute of Technology, Huazhong University of Science
and Technology, Southeast University, Shanghai University, Beijing University of
Technology, Central South University, South China University of Technology,
University of Electronic Science and Technology of China, Tianjin University, etc.
The packaging research programs in these universities include fundamental research
on advanced packaging materials, technology, and structure (e.g., 3D heterogeneous
integration based on TSV), design methods (e.g., EMC design of SIP), reliability,
and fundamental research related to packaging, etc. In addition, Harbin Institute of
Technology, Beijing Institute of Technology, Huazhong University of Science and
1024 J. Cai et al.

Technology, Xidian University, Guilin University of Electronic Technology, Xiamen

University of Technology, Jiangsu University of Science and Technology, and
Nanchang Hangkong University have set up independent electronic packaging
technology or microelectronics manufacturing majors to promote the education
and training of professionals.

Research Institutes

According to the statistics of Packaging Society, China Semiconductor Industry

Association (CSIA), there are 36 research institutes involved in packaging technol-
ogy research in 2016. The main research work of these institutions includes ceramic
packaging, opto-electric packaging, hybrid circuit packaging, metal and ceramic
substrate development, packaging material development, packaging equipment
development, reliability testing, etc., which are applied in various areas including
high reliability applications. Research institutes under China Electronic Technology
Corporation (CETC) carried on comprehensive research in packaging development,
including custom packaging design, packaging equipment, packaging materials, etc.
The Institute of Microelectronics of the Chinese Academy of Sciences (IMCAS),
Shanghai Institute of Microsystem and Information Technology (SIMIT) have also
made in-depth research on advanced packaging technology, including MEMS pack-
aging technology. In addition, research institutes of aeronautical and space systems
have also performed R&D on targeted packaging technology. Based on the current
development of packaging technology, some research institutes have established the
business departments or research centers of micro-system research to carry out R&D
on system integration.

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Integrated Circuit Package Types
55
Guoliang Yu, Haizhong Shi, and Honghui Wang

Contents
Definition and Function of Conventional Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Grading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Progresses of Major Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Conventional Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Single-Inline Package (SIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Dual-Inline Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
Small-Outline Package (SOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
Small-Outline Transistor (SOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
Transistor Outline (TO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
Advanced Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
Through-Hole and Surface-Mount Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Through-Hole Packages (THP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Surface-Mount Package (SMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
Quad Flat Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Quad Flat Package (QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Quad Flat No-Lead (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044
Characteristics of QFP and QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Organic Substrate Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
Wafer Level Packaging (WLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
System-in-Package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
Microsystem Packaging (MSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Multi-chip Modules (MCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Embedded Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Three-Dimensional Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
Chip-on-Board (COB) Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056

G. Yu (*) · H. Shi · H. Wang

TongFu Microelectronics Co., Ltd., Nantong, China
e-mail: yu.gl@tfme.com

© Publishing House of Electronics Industry 2024 1027

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_55
1028 G. Yu et al.

Substrate Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057

Ceramic Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Organic Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Glass Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Classification of Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Plastic Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Metal Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Ceramic Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Glass Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Package Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Wire Bonding (WB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Tape Automated Bonding (TAB) [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Flip-chip Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Lead Frame Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
Hermetic Package and Non-hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Non-hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Package Type Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067

Abstract
This chapter describes the main types of packages and the evolution of package
technologies of integrated circuits. Firstly, the definition and function of conven-
tional packages are described, and the concept of advanced package is explained.
After that, main packaging technologies such as quad flat packaging (QFP),
system-in-package (SiP), wafer-level packaging (WLP) and three-dimensional
(3D) packaging, microsystem packaging, multi-chip module, and embedded
packaging are presented. Then, the classification and properties of packages
that depend on materials, interconnects, and hermeticity are introduced. Finally,
the selection of packaging types in the application is illustrated and discussed.

Keywords
Conventional package · Advanced package · QFP · WLP · SiP · 3D package ·
Substrate package · Lead frame package · Hermetic package · Non-hermetic
package

Definition and Function of Conventional Packaging

We describe the definition, effect, function, and classification of the conventional

packaging technologies in below.

Definition

In a narrow sense, the packaging refers to the assembling of packages for IC chips;
the generalized definition of the packaging (or assembly) refers to the entire process
including: assembling the known good dies (KGD), components, etc. onto the
55 Integrated Circuit Package Types 1029

carrier, forming the electrical connection by using appropriate interconnect technol-

ogy, and adding package to form an effective module. When the package of IC chips
(die) is mounted, the chips can be encapsulated by a specific process using materials
(e.g., plastic, metal, ceramic, glass, etc.) so that the IC can stably and reliably work
under the working environment and conditions.

Effect

Packaging technology is an important part of IC technology. Package is mainly used

to place, attach, seal, protect the chip, and ensure electrical and thermal performance
of the ICs. The specific functions include isolating the chip from external environ-
ment; avoiding the chip being affected by harmful gases, moisture, etc.; ensuring the
surface of the chip is clean and dry; providing suitable external leads for the ICs;
providing package for the ICs to resist the harsh external environment; and providing
better mechanical strength for the ICs in long-term normal operations. For power
circuits and high-frequency circuits, a good package plays an important role in heat
dissipation and shielding.

Function

The function of the packages usually includes five aspects, namely, power distribu-
tion, signal distribution, heat dissipation channel, mechanical support, and environ-
mental protection. (a) Power distribution: Firstly, we should consider the power-on,
so that the IC chip can communicate with external circuits. Secondly, the package
must distribute the power to different parts inside the package for optimized internal
consumption of power. (b) Signal distribution: In order to minimize the delay of the
electrical signal, the path between the signal line and the path through the package
input/output (I/O) should be minimized. To avoid crosstalk of high frequency
signals, the layout for signal lines and ground needs to be optimized. (c) Heat
dissipation channel: The structure and materials of the package play a key role in
the heat dissipation of the device. For ICs with high power, additional cooling
measures, e.g., heat sink (sheet), air cooling, and water cooling, are considered.
(d) Mechanical support: Packages provide reliable mechanical support for IC chips
to accommodate different operating environments and conditions. (e) Environmental
protection: Before packaging, IC chips are already subject to environmental influ-
ences. When packaged ICs are used, they may encounter very harsh environments.
Therefore, the environmental protection capability of the package is obviously
important.

Classification

The packages can be generally divided into plastic, metal, ceramic, and glass
packages based on the packaging materials.
1030 G. Yu et al.

Grading

IC packaging is generally classified into chip-scale packaging (0-level), component-

level packaging (1-level), board-level packaging (2-level), and equipment level
packaging (3-level). (a) The “0-level” packaging is a chip-scale packaging (CSP).
Generally, the interconnect methods for chip-level packaging is wire bonding (WB),
tape automated bonding (TAB), or flip-chip bonding (FCB). (b) The “1-level”
packaging is component-level packaging that encapsulates one or more IC chips
with appropriate materials, e.g., plastics, metals, ceramics, etc., or combination.
(c) The “2-level” packaging is board level packaging for the process of mounting
ICs, resistors, capacitors, connectors, and other components on PCB. (d) The “3-
level” packaging is equipment level packaging for assembling all the above PCBs
(boards or cards) into the final system.

Progresses of Major Package Types

1947: AT&T Bell Labs invented the first transistor, opening the era of electronic
packaging.
1950s: The package was mainly 3-pin transistor outline (TO) – metal and glass
package and later developed into various ceramic and plastic packages.
1960s: The dual-in-line package (DIP) was developed with ceramic-metal lead
package of 4 to 64 pins. In 1970s, DIP became the dominant package type for
small- and medium-scale ICs. With the advent of plastic DIP, it is widely used in a
large number of civilian products.
1970s: IC technology developed rapidly. Transistors with a number of 211–216 could
be integrated into a Si chip, and the large-scale IC (LSI) appeared. At this time,
the integration of components increased significantly, and the chip size was
continuously expanded.
1980s: With the advent of surface mount technology (SMT), various surface mount
component/device (SMC/SMD) packaging technologies were mature. The pack-
aging technologies (e.g., leadless ceramic chip carrier (LCCC), plastic leaded
chip carrier (PLCC), quad flat package (QFP), etc.) were standardized in mass
production in the early 1980s. As the performance of epoxy materials continu-
ously improved, the packaging density of ICs was further increased with scaled
pitch of pins and reduced cost. The packaging of ICs was more mature for mass
production. Plastic quad flat package (PQFP) became the leading package type of
IC in the 1980s with up to 240 I/O pins. At the same time, for SMT applications,
the small- or medium-scale ICs (SSI, MSI) and the LSI chips with a small number
of I/O pins adopted the small outline package (SOP) as a derived package
from DIP.
1980s and 1990s: As IC feature sizes decreased and integration level increased, the
chip size continued to increase, and ICs advanced to the very large-scale integra-
tion (VLSI) stage with millions of transistors and hundreds or even thousands of
I/0 pins. The original QFP and other types of electronic packages were unable to
55 Integrated Circuit Package Types 1031

meet the requirements for VLSl. The IC package pins have evolved from a
peripheral arrangement to a matrix distribution type, such as pin grid array
(PGA) package and ball grid array (BGA) packages.
1990: The United States developed the micro ball grid array (μBGA) packaging
technology, and Japan developed the chip-scale packages (CSP) technology. The
two packaging technologies are essentially the same and the ratio of package area
to chip area is less than 1.2. These technologies solved the fundamental contra-
diction of small chips and large packages. CSP can be divided into lead frame
type package, rigid interposer type package, flexible interposer type package, and
wafer-level-package (WLP). At the same time, the application of flip-chip
(FC) technology triggered again the evolution of IC packaging technology.

In the twenty-first century, as approaching the limit of Si process, IC technology

enters the “post-Moore’s law” era. The focus is shifted from the continuous scaling
of IC manufacturing technology in the past to a system-level design and innovative
packaging technology. Advanced packaging technologies have been developed in an
unprecedented way in the early twenty-first century. Multi-chip module (MCM)
package, system-in-package (SiP), 3D package, and chip size (or scale) package
(CSP) were developed rapidly and widely used. At the same time, system-on-chip
(SoC) package, micro-electro-mechanical-system (MEMS) package, through-Si-via
(TSV) technology, bumping, surface activated bonding (SAB), and other technolo-
gies have achieved new breakthroughs toward mass production.
The development of packaging technology and its structure closely keeps up with
the progress of IC manufacturing technology, and each generation of ICs has new
packaging technology and structure correspondingly. Since the twenty-first century,
advanced packaging technologies have been rapidly developed. As electronic
devices advancing toward shorter, smaller, lighter, thinner, more functional, and
integrated, the electronic packaging in the IC industry is increasingly more
prominent.

Conventional Packaging

Conventional packaging usually refers to the entire process from the individual dies
cut from the wafers and packaged into various forms, mainly SIP, DIP, SOP, SOT,
TO, QFP, QFN (quad flat no-lead), DFN (dual flat no-lead), BGA, and other
packaging forms. Sometimes BGA and QFN are also listed in the scope of advanced
packaging.

Single-Inline Package (SIP)

The leads of SIP are leaded from one side of the package and arranged in a straight
line as shown in Fig. 55.1. The main SIP package outlines are SIP8, SIP9, SIPT10,
etc. SIPT means that the tab is on the top of the plastic body as a heat sink as shown
1032 G. Yu et al.

Fig. 55.1 SIP8

Fig. 55.2 SIPT10

in Fig. 55.2. In general, the number of SIP leads is 2–23, and the pitch of the lead is
usually 2.54 mm (100 mil) or 1.27 mm (50 mil).

Dual-Inline Package (DIP)

The leads of DIP are leaded from both sides of the package and arranged in two
straight lines as shown in Fig. 55.3. After the invention of IC in 1958, DIP was the
most representative IC package before the advent of surface mount devices (SMD).
At present, although the usage of DIP is greatly reduced, it is still actively used. The
number of DIP leads is in the range of 4–88 with a standard lead pitch of 2.54 mm
(100 mil). The DIP packaging is still evolving, e.g., the shrink DIP (SDIP) with a
smaller lead pitch of 1.778 mm (70 mil); the super-shrink DIP (SSDIP) with further
scaled lead pitch of 1.27 mm (50 mil); the heat-sink DIP (HDIP) with wide leads in
the middle of the DIP for heat dissipation as in Fig. 55.4; and also the DIP with a tab
(DIPT) on the side for heat dissipation as in Fig. 55.5. According to the different
package materials, DIP products can be divided into ceramic DIP package (CDIP)
55 Integrated Circuit Package Types 1033

Fig. 55.3 DIP8

Fig. 55.4 HDIP12

Fig. 55.5 DIPT14

and plastic DIP package (PDIP). In general, DIP products are also distinguished by
the row spacing, i.e., e1 between the two rows of leads, in DIP300mil, DIP400mil,
DIP600mil, DIP750mil, and DIP900mil series as in Fig. 55.6. In general, the
maximum lead number in the DIP300mil series is 20. If more than 20 leads in the
1034 G. Yu et al.

Fig. 55.6 Row spacing

diagram

Fig. 55.7 SOP8

DIP300mil standard package, it is called as skinny DIP (SKDIP) for distinguishing

from other series, which usually includes SKDIP22, SKDIP24, SKDIP28, and
SKDIP32.

Small-Outline Package (SOP)

SOP belongs to surface mount device as shown in Fig. 55.7. The size and weight of
SOP are much smaller than those of DIP. SOP series packages usually have two
types of leads. One kind of SOP with “L” shaped lead (commonly known as seagull
wings) is usually referred to as SOP; another kind of SOP with “J” shaped lead is
commonly referred to as SOJ. When the base island of the metal lead frame on the
surface of the SOP package is exposed, its heat dissipation is improved; this kind of
SOP is referred to as heat-sink SOP (HSOP) as in Fig. 55.8. According to the
different package materials, SOP products can be divided into ceramic SOP
(CSOP) and plastic SOP (PSOP). The lead pitch of SOP has various specifications,
55 Integrated Circuit Package Types 1035

Fig. 55.8 HTSSOP20

Fig. 55.9 SOT223

e.g., 1.27, 0.8, 0.65, 0.50, and 0.40 mm. When the lead pitch is not greater than
0.65 mm, it is called shrink SOP (SSOP). According to JEDEC standard (Design
guide 4.15), when the package overall height is less than 1.20 mm, it is called thin
SOP (TSOP). According to JEDEC standard (MO-153), when the total height of
package is less than 1.20 mm and the lead pitch is less than 0.65 mm, it is referred to
as thin shrink SOP (TSSOP). One package named Mini SOP (MSOP) is based on
TSSOP with smaller package size, e.g., the package size of MSOP8 is about 30%
smaller than TSSOP8.

Small-Outline Transistor (SOT)

SOT is one of the early surface mount devices, mainly including the package types of
SOT23, SOT89, SOT143, SC70, and SOT223, as in Fig. 55.9. Among them,
according to the thickness and size of the package, SOT23 can be divided into two
types: TSOT23 (thin SOT23 as in Fig. 55.10) and SSOT23 (small SOT23). The
materials for SOT packages are all plastic.
1036 G. Yu et al.

Fig. 55.10 TSOT23-5

Fig. 55.11 TO92

Transistor Outline (TO)

Metal TO package once was the earliest and most widely used package. With the
development of packaging technology, metal TO packages have been replaced by
plastic TO packages. The TO packages of through-hole mounting type mainly
include TO92, TO126, TO251, TO220, TO220FP, TO247, and TO262 as shown
in Figs. 55.11, 55.12, 55.13, 55.14, 55.15, 55.16, and 55.17. The TO packages of
surface mount type mainly include TO252 and TO263 as in Figs. 55.18 and 55.19.
The lead number of TO package is usually 2–7.
Conventional packaging is still actively used. (1) SIP (single-inline package) is
mainly used in television, radios, and other household electronic products (e.g.,
audio power amplifier circuit, FM stereo phase-locked loop decoder circuit, etc.)
and some measuring instruments (e.g., LED level indicator, resistance chain, etc.).
(2) DIP (dual-inline package) is mainly used in fixed telephone, recorder, radio,
television, and other household electronic products (e.g., audio integrated power
amplifier circuit and single-chip microcomputer control circuit) and also com-
monly used in photo MOS of packaging industrial control field. (3) SOP (small-
55 Integrated Circuit Package Types 1037

Fig. 55.12 TO126

Fig. 55.13 TO251

Fig. 55.14 TO220-3

1038 G. Yu et al.

Fig. 55.15 TO220FP

Fig. 55.16 TO247

Fig. 55.17 T0262

55 Integrated Circuit Package Types 1039

Fig. 55.18 TO252

Fig. 55.19 TO263

outline package) is mainly used for laptop computers, router memory circuit,
television, and other consumer electronics power management and display driver
circuit. (4) QFP (quad flat package) is not only used in microprocessors of
consumer electronics (e.g., air conditioner and washing machine), LSI circuits of
digital logic (e.g., gate arrays), and also analog circuits (e.g., VTR (video tape
recorder) signal processing, audio signal processing, and information processing
circuits of set-top boxes and satellite receivers). (5) SOT (small-outline transistor)
package is commonly used to medium and low power tubes of electronics (e.g.,
mobile phones, notebook computers). (6) TO (transistor outline) package is com-
monly used to medium and high power devices electronics (e.g., lighting equip-
ment, switching power supply, microwave ovens, electric cars). In summary, as
driven by the market demand, the innovation and evolution of conventional
packaging is continuing and a variety of new packaging structures have emerged.
Although with the increasing requirements of high speed, miniaturization, system-
atization, and low cost of electronic products and devices, the limitations of
1040 G. Yu et al.

conventional packaging are more prominent, and the quantity of demand is con-
stantly declining. However, due to its simple packaging structure and low
manufacturing cost, there is still a certain market space at present.

Advanced Packaging

Advanced packaging refers to current leading edge packaging types and technolo-
gies. Currently, technology as flip-chip (FC), wafer level package (WLP), and 2.5D
and 3D packages are regarded as advanced packaging technologies. (1) Flip-chip
package makes the metal bumps on the first die and then the die was flipped to form
interconnect with the substrate using solder. Usually under-fill epoxy is applied to
redistribute thermal expansion to improve reliability. The advantages of flip-chip
package are smaller package size, shorter interconnects, and high I/O counts.
(2) WLP is performed on the wafer with dies assembled and tested simultaneously.
After the wafer is sawed to single die (or chips) at last, it can be attached on substrate
or PCB directly. WLP’s major process involves redistribution layer (RDL) formation
technology including sputtering, photolithography, electroplating, etc. WLP enjoys
advantages of lighter, thinner, and smaller product, shorter signal wire, better
efficiency, and lower cost. According to different structures, WLP can be divided
into fan-in and fan-out. For fan-in product, the package size is the same as the die,
while for fan-out product, the package size is larger than the die. (3) On the basis of
2D packaging technology, the 2.5D package added a Si interposer between the dies
and the assembly carrier. The interposer is used to connect the metal traces on upper
and bottom surfaces with the use of through-silicon-via (TSV). This is usually
processed through flip-chip package technology. With the interposer, the wiring on
the surface metal layers can be processed in the same way as on dies for improving
product’s capacity and performance. (4) 3D packaging stacks the dies directly and
can be processed through wire bond, flip chip or both, or through TSV technology.
3D structure reduces product size further and improves product capacity and per-
formance. At present, the major limits of TSV are bad thermal dissipation and
high cost.
Advanced package, widely applied in computers, telecommunications, medical
care, aviation, and so on, boosts the growth of package technology and the whole
electronics industry. At present, flip-chip, 2.5D, and 3D package are applied mainly
to memory, CPU (central processing unit), GPU (graphic processing unit), and so on;
WLP is mainly applied to power amplifier, wireless connector, RF transmitter, etc.
In recent years, fan-out is one of the popular advanced packaging technologies,
and it can be classified as fan-out wafer level packaging (FO-WLP) and fan-out
panel level packaging (FO-PLP). Based on fan-out technology, fan-out package on
package (FO-POP) and other technologies can be further developed. Fan-out struc-
ture enables huge increase of I/O’s while wafer level or panel level fan-out process
can improve efficiency and reduce cost. Therefore fan-out packaging technology is
the trend and promising in the future.
55 Integrated Circuit Package Types 1041

Through-Hole and Surface-Mount Packages

According to the different ways of connecting with PCB, IC package can be divided
into two kinds: through-hole packages and surface-mount packages. These two
kinds of package devices can be used alone or mixed in PCB.

Through-Hole Packages (THP)

The THP uses the through-hole technology (THT) to install IC chips on PCB. The
device in HTP is called through-hole device (THD). The THP is the earliest package
outline when the IC was invented in 1958, and it is characterized by straight plug
leads. After being inserted into the through-holes on the PCB, wave soldering is used
for welding. The device and solder joint are located on both sides of the PCB as
shown in Fig. 55.20. According to different package outline and structure, it can be
divided into transistor outline (TO), single-inline-package (SIP), dual-inline-pack-
age (DIP), and pin-grid-array (PGA).

Surface-Mount Package (SMP)

SMP refers to the surface mount technology (SMT) for installing ICs on PCB. The
ICs in SMP is called surface-mount devices (SMD). SMP is another type of IC
package outline invented for IC high-density, miniaturization, and thinness. It
generally has “L” type leads, “J” type leads, ball, or pad (convex block). The device
is attached to the soldering pad on the PCB surface and followed by reflow welding.
The device and solder joint are located on the same side of PCB. According to the
different package outline and structure, surface mount devices can be divided into
small outline package (SOP), transistor outline (TO), small outline transistor (SOT),
quad flat package (QFP), quad flat no-lead (QFN), dual flat no-lead (DFN), and ball
grid array (BGA).

Fig. 55.20 Soldering

of THD
1042 G. Yu et al.

No matter the through-hole packages (THP) or the surface mount packages

(SMP), the materials used in the package body are mainly divided into ceramic
(C), glass (G), metal (M), and plastic (P). For example, “PDIP” represents a plastic
DIP. Plastic is the most commonly used packaging materials, and if not identified
materials, it usually refers to the plastic packaging. Plastic QFP products of “J” type
lead is also known as PLCC (plastic leaded chip carrier). Ceramic QFN is also called
LCCC (leadless ceramic chip carrier). Table 55.1 lists the characteristics of THP and
SMP.
SMP has more advantages over THP. But due to the high installation density of
the SMP on the PCB, the requirements for heat dissipation are higher too. Also due
to different coefficient of thermal expansion (CTE) of device and PCB, it is easy to
cause cracking at solder joints. The most serious is the moisture absorption problem
by the plastic body. Because the SMP is heated when welding the plastic body as a
whole, it is easy to cause the water vapor absorbed by the plastic body and resulting
in internal stratification phenomenon or even the plastic body burst in serious cases.
It is seen that, compared with THP, SMP differs not only in appearance, but also in
the design of IC chips, packaging structure and materials, testing technology, and
corresponding equipment. As related to the breakthrough of these key technologies
and materials, the SMD and technology are widely adopted. Certainly, the THP has

Table 55.1 The characteristics of through-hole package and surface mount package
No. Item HTP
1 Lead number Except PGA, the lead number is
generally no more than 100; the
pin number of PGA is no more
than 500
2 Installation Compared with SMP, with the
density same number of leads, the
package area and weight is
larger. The ratio of chip area to
package area is small, usually
less than 1:10
3 Electrical Large parasitic inductance,
property resistance and capacitance, slow
signal transmission
4 Automatic Large size and weight, complex
production shape, need a variety of through
hole machines
5 Product cost High material cost and low
production efficiency
6 Reliability Solder joint defect rate is high;
not resistant to mechanical shock
and high frequency vibration
7 Environment The usage of packaging materials
protection is large
SMP
Up to 1000 þ (e.g., BGA)
Compared with THP, with the
same number of leads, the
package area of SMP is
25% ~ 40% of THPR. Its weight
is 5% ~ 15% of THP. The ratio of
chip area to package area can
exceed 1:1.14, very close to 1:1
Small parasitic inductance,
resistance and capacitance, fast
signal transmission
Small size, light weight, easy to
mounting
Low material cost and high
production efficiency
Solder joint defect rate is lower
than 50%, with good mechanical
shock resistance and high
frequency vibration resistance
The usage of packaging materials
is less
55 Integrated Circuit Package Types 1043

the characteristics of convenient welding, good reliability, easy maintenance, low

sensitivity to material moisture, good heat dissipation performance, large power, etc.
It is usually used in the case of not so demanding on the size or high-power devices.
Therefore, THP is still active in the market.
From the perspective of packaging material properties, ceramic, glass, and metal
packaging belong to hermetic packages (HP). It can effectively prevent the intrusion
and corrosion of liquid type pollution in the environment and mostly used in military
equipment, aerospace, ship, and other advanced fields and electronic products with
high reliability requirements. Plastic package belongs to the non-hermetic package.
Compared with ceramic, glass, and metal packaging, plastic packaging has simpler
process and lower cost; and it is mostly used in consumer electronics.
THD are usually used in electronic products without strict requirements on
package size, e.g., television, electric car, microwave oven, and desktop computer.
In particular, some medium and high power transistors usually adopt TO packages
with through holes. When there are strict requirements on the package size, such as
mobile phones, digital cameras, laptops, and other portable electronic products,
surface mount packages (SMP) are usually used.

Quad Flat Packages

There are two main types of four-sided lead flat packages, i.e., packages with leads
(QFP) and packages without leads (QFN).

Quad Flat Package (QFP)

QFP is the package whose “L” shaped leads are extended out from four sides of the
package body as shown in Fig. 55.21. QFP is usually classified according to
the package thickness as in Table 55.2. In addition, QFP with a pitch of less than

Fig. 55.21 QFP

1044 G. Yu et al.

Table 55.2 The classification of QFP

Package Lead Lead
Type Description thickness/mm Package size number pitch/mm
MQFP Metric 2.00, 2.50, 2.70, 10 mm  10 mm ~ 40 mm  64 ~ 376 0.40, 0.50,
QFP 2.80, 3.40, 3.80, 40 mm 0.65, 0.80,
4.10 1.00
LQFP Low profile 1.40 4 mm  4 mm ~ 28 mm  20 ~ 256
QFP 28 mm
TQFP Thin 1.40 4 mm  4 mm ~ 28 mm  20 ~ 256
profile QFP 28 mm

Fig. 55.22 HQFP

0.65 mm is referred to as FQFP (fine-pitch QFP). QFP with the lead frame base
island on the package surface exposed for heat dissipation or with heat-sink is
referred to as HQFP (heat-sink QFP) as shown in Fig. 55.22. According to the
different materials used in the packages, QFP packages can be divided into ceramic
and plastic QFP. Usually the initial words of the package are added as C (for
ceramic) or P (for plastic) for distinguishing, e.g., “PQFP” as the QFP of plastic
material. Plastic is the most commonly used packaging materials, and if no
identification of materials, it usually refers to the plastic packages.

Quad Flat No-Lead (QFN)

QFN packages have the pads at the bottom of the package body for soldering to the
PCB as in Fig. 55.23. There are two classification methods for QFN packages as the
following: (a) Based on product height, see Table 55.3, and (b) based on separation,
mainly divided into cutting and punching. Cutting means use of resin or metal blade
to cut package body for separation; punching means use of mold punching to cut
package body for separation. Punch QFN is often called PQFN (punch QFN).
55 Integrated Circuit Package Types 1045

Fig. 55.23 QFN

Table 55.3 QFN package outline (according to the product height)

The
maximum
product Pads
type Description height/mm Package size number Pads pitch/mm
QFN Normal 2.54 10 mm  10 mm ~ 25 mm  68, 74 0.50, 0.55, 0.60,
QFN 30 mm 0.65, 0.70, 0.75,
0.80, 0.85, 0.90,
0.95, 1.00, 1.05,
1.10, 1.15, 1.20,
1.25
LQFN Low QFN 1.70 10 mm  10 mm ~ 25 mm  68, 74 0.50, 0.55, 0.60,
30 mm 0.65, 0.70, 0.75,
0.80, 0.85, 0.90,
0.95, 1.00, 1.05,
1.10, 1.15, 1.20,
1.25
TQFN Thin QFN 1.20 1 mm  1 mm ~ 19 mm  4–156 0.40, 0.50, 0.65,
19 mm 0.80, 1.00, 1.27,
1.50
VQFN Very thin 1.00 1 mm  1 mm ~ 19 mm  4–156 0.40, 0.50, 0.65,
QFN 19 mm 0.80, 1.00
WQFN Very very 0.80 1 mm  1 mm ~ 19 mm  4–156 0.40, 0.50, 0.65,
thin QFN 19 mm 0.80, 1.00
UQFN Ultra thin 0.65 1 mm  1 mm ~ 19 mm  4–156 0.40, 0.50, 0.65
QFN 19 mm
XQFN Extremely 0.50 1 mm  1 mm ~ 2.5 mm  4–24 0.35, 0.40, 0.50
thin QFN 3.4 mm

Characteristics of QFP and QFN

(a) QFP package characteristics: large number of leads, large contact area, high
welding strength, and reliability. The lead width of QFP is 0.13–0.50 mm, and the
lead thickness of QFP is 0.09–0.20 mm. The leads of QFP are very fine with small
1046 G. Yu et al.

parasitic parameters. So QFP packages are suitable for high-frequency applications.

Currently, the largest QFP package size is 40 mm  40 mm, the largest number of
leads is 376, and the minimum lead pitch is 0.40 mm. If the package size is further
increased, the package warping deformation will be increased too. If the lead pitch is
reduced, it is easy to cause short circuit between the leads due to burr or bridging
during reflow. If the number of leads is further increased, the co-planarity of leads
cannot be guaranteed, and it is easy to cause virtual soldering and open the circuit
during reflow. Therefore, BGA and other packaging technologies should be adopted
if more leads needed. (b) QFN package characteristics: QFN packages have no leads,
so the installation area is smaller and the height is lower. QFN packages have short
path connection between the internal leads and external terminal and leading to
smaller inductance and internal resistance for better electrical performance. QFN
packages have an exposed chip mount, as leading to excellent heat dissipation
performance. When the packaged device is installed on the PCB for reflow welding,
thermal stress will be generated between the PCB and the package body. QFN
packages are installed closer to the PCB, so the stress is not easy to be released at
the solder pads. Therefore, if the number of I/O does not exceed 156, QFN package
can be used; otherwise, BGA and other package outline should be considered. In
addition, the solder joint of QFN packages and PCB are at the bottom of the device,
so it is difficult to rework.

Applications

At present, QFP/QFN packages are widely used in many fields. (a) Ceramic QFP
packages are mostly used in military communication, aerospace, marine, and
other advanced fields and electronic products with high reliability requirements.
(b) Plastic QFP packages are mainly used in air conditioning, washing machines,
and other household electronic microprocessor, satellite television receiver,
set-top box, television, mobile phone LCD driver circuit, audio circuit, and
mobile storage equipment. (c) QFN packages are mainly used in smart phones,
PDA, and other portable mobile electronic devices, such as aerial switch, power
amplifier circuit, etc. (d) QFN packages are also used in some detection instru-
ments and sensors, such as accelerometer, magnetic sensor, gyroscope, pressure
sensor, etc.

Organic Substrate Packaging

Organic substrate packaging refers to the packaging of single chip, multi-chip, and
multi-component through wire bonding, flip chip, or system in a package technol-
ogy to fan-out the signals and power to the solder pads or solder balls on the back
of the organic substrate. Organic substrate materials are divided into rigid sub-
strates and flexible substrates. At present, rigid substrate are widely used in the
55 Integrated Circuit Package Types 1047

market. The main package outlines are ball grid array (BGA) and land grid array
(LGA) as shown in Figs. 55.24 and 55.25.
Organic substrate packaging has the following advantages. It has large I/O
numbers and high I/O density. Compared with LQFP with the same size, the I/O
numbers of BGA can achieve 5–6 times than that of LQFP. This kind of packag-
ing has a high yield of die mounting. The defect rate can be controlled below
5x106. The heat dissipation effect is good. It is easy to fabricate micro circuit
(the most advanced PCB technology can reach 20–30 μm). Flexible design plan
can be adopted to realize the free definition of output terminals according to the
demand. The good co-planarity of I/O’s reduces the electrical loss caused by poor
co-planarity in the assembly process. It is applicable for SiP with high density
and high performance. Also organic substrate package has high reliability. The
high cost of substrate is the shortcoming of organic substrate packaging. It is easy
to get warpage in the package process. Rework is difficult, and after rework, the
BGA mounting on the chip is needed again before it can be used. The package
thickness is thicker, and it has been replaced by fan-out technology in some
fields.

Fig. 55.24 Ball grid array (BGA)

Fig. 55.25 Land grid array (LGA)

1048 G. Yu et al.

BGA/LGA packaging technology has been a mature high-density package tech-

nology since the 1990s and currently plays an important role in small, light, and high
performance package. Its package products are widely used in consumer electronic
products (e.g., smart wearing equipment, encryption module, medical equipment,
etc.). Organic substrates will play an increasingly important role in BGA/LGA field,
with the continuous thinning and smarter consumer electronics and mobile products.
At the same time, substrate package will develop toward multi-function and high
integration. The development trend of substrate package will be in the following
aspects. (a) In the aspect of high density, the research and exploration of ultra-high
density substrate will be carried out to meet the growing demand of integrated
packaging technology, e.g., micro-porous technology with small diameter
(<35 μm), ultra-precision narrow-pitch metal wire technology (<10 μm), low-cost
flat micro-via and direct-stacked multi-layer interconnection technology, etc. (b) In
the aspect of high performance, while maintaining signal integrity and power
consistency, the thickness of the substrate is reduced and ultra-thin or coreless
substrates are developed. (c) In the aspect of component integration, the embedded
passive and active devices are also optimized to achieve the best system
performance.

Wafer Level Packaging (WLP)

Wafer level packaging (WLP) is defined as all the assembly and test processes are
performed at wafer level and all input/output (I/O) pads are distributed within the
chip surface as referred to as fan-in wafer level packaging (FI-WLP) technology.
Its core characteristic is to use redistribution layer (RDL) technology to
reconfigure the pads in the perimeter of the chip, and then bumps (or solder
balls) are fabricated on wafer. The ratio of the chip area and the final package area
are 1:1 of the standard. The single package after packaging can be directly
applied to the assembly process.
The features of wafer level packaging (WLP) are described as below. (1) WLP
has small size, small inductance between chip and PCB, short data transmission
path, high stability, and good heat dissipation capability; it is used in various
electronic products to meet the requirements of light thin and small packages.
(2) WLP has more process optimization than traditional packaging process and has
great consistency with the chip size, containing RDL, wafer bumping, wafer level
testing, wafer dicing, and packing with carrier tapes. It is able to support one-stop
turnkey service of advanced packaging solutions with significantly reduced cycle
time and cost. (3) WLP requirements should be considered when the chip is under
design, which benefit the chip layout design and can improve device performance.
As shown in Fig. 55.26, the RDL technology is a general solution for WLP for chip
pads linking to external pins, and the bumping technology is an optimal choice to
finally connect the chip directly to the PCB.
55 Integrated Circuit Package Types 1049

Fig. 55.26 Wafer level packaging

WLP, as a hotspot in current packaging, is an integration technology to include IC

design, wafer fabrication, assembly and test, and substrate manufacturing together.
WLP has the smallest chip size package (CSP) and the advantage of better electrical
performance. WLP is mainly used in consumer portable products with low pin
counts (including analog/mixed signal, wireless, automotive electronics, etc.) and
also can meet memory chips packaging characteristics with lightweight and ultra-
thin/large-sized requirements. There are three main development trends: (1) Firstly,
the number of layers of WLP structure are reduced for lower package cost and
shorter process time with good product performance and reliability. (2) Secondly,
with the development of new technology and the application of new materials, the
performance and reliability of WLP products can be improved to meet severer
product application requirements. (3) On the basis of these technologies, WLP can
meet the development trend of fan-out wafer level packaging (FO-WLP), wafer
system-level packaging, 3D wafer level packaging (3D-WLP), high-density redis-
tribution layers, and other advanced packaging technology.

System-in-Package (SiP)

System-in-package or system-integrated-package (SiP) is a single standard package

with multi functions that combines multiple active ICs with different functions and
optional passive devices as well as other devices (e.g., MEMS or optics, etc.) to form
a system or sub-system [1]. The mainstream package form of SiP is BGA (ball grid
array). The package carrier is mostly a substrate or a printed circuit board (PCB), and
passive components can be embedded into the package carrier according to require-
ments. Compared with traditional board level system integration, SiP has smaller
size, lower cost, and improved system performance and great integration level.
Compared with system-on-chip (SOC), SiP has many advantages, such as a short
development cycle, low cost, high flexibility, and so on.
According to the way of assembly of chips, SiP can be divided into 2D, 2.5D, and
3D structures. (1) For 2D SiP, multiple chips are assembled onto the surface of the
same package carrier. The assembly process includes WB (wire bonding), FC (flip
chip), or a mixture of two processes as shown in Fig. 55.27. Since the traces on the
1050 G. Yu et al.

Fig. 55.27 2D structure of SiP

Fig. 55.28 2.5D structure of SiP

Fig. 55.29 3D structure of SiP (WB and FC)

package carrier are 3 orders of magnitude wider than on chips, the structure is limited
in the number of interconnect chips. (2) The 2.5D SiP is based on the 2D SiP
technology, and a Si interposer is added between the chip and the package carrier.
The interposer is connected to the metal on the upper and bottom surfaces by using
TSV (through-Si-via). The 2.5D structure usually uses flip-chip assembly process as
shown in Fig. 55.28. Due to the use of the interposer, the traces of the surface metal
layer can be the same process as the surface of the chip, which greatly improves the
product in terms of capacity and performance compared to the 2D structure. (3) For
3D SiP, the chips are stacked. The assembly process can adopt mixed assembly
processes that contain wire bonding and flip chip, and the TSV technology for
interconnection as shown in Figs. 55.29 and 55.30. The 3D structure further reduces
the size of products and increases the capacity of products. Using TSV technology
can reduce the interconnection distance and improves the performance of products.
However, based on the current TSV technology, poor heat dissipation and high cost
are the main reasons that restrict its development.
55 Integrated Circuit Package Types 1051

Fig. 55.30 3D structure of SiP (TSV and FC)

SiP is suitable for low-cost, small form factor, and short-life electronic products
such as power amplifiers, Bluetooth modules, high-performance processors, mem-
ory cards, smart wearable devices, etc. as widely used in consumer electronics,
especially in the Internet of Things (IoT). 3D SiP can greatly improve the perfor-
mance and capacity of products as the development trend of SiP technology for the
future. Based on the core techniques of TSV formation, wafer thinning and rewiring
process, chip/wafer bonding, TSV stacking, and package stacking are the key
technologies for SiP. Ultra-low wire loop bonding technology, narrow pitch wire
bonding technology, new die attach technology, new wire bonding materials, fine
pitch Cu pillar flip bumping, and micro bumping technology will become the key
packaging processes in SiP.

Microsystem Packaging (MSP)

Microsystem packaging (MSP) technology serves application products by integrat-

ing and combining several functional chips with necessary parts and package
platform according to the principle of system optimization. Microsystem starts
from system engineering perspective to manufacture, assemble, and integrate min-
iaturized functional devices on frames, substrates, and so on through encapsulation,
interconnection and other micro-processing technology, radio technology (RF),
optics (or optoelectronics) technology, and micro-electromechanical system
(MEMS) technology at the core.
According to different definitions, microsystem package (MSP) technology is
divided into many different packaging technologies (e.g., microelectronic package,
RF package, optoelectronic package, MEMS package, and multifunctional SiP).
(1) Microelectronic package technology serves miniaturized electronic devices and
circuits with micron/nanometer process on semiconductor material. (2) Radio
frequency (RF) package technology serves small, multi-function, portable, and
cost-effective radio devices. It is an important technology in the application of
microsystem package technology. (3) Optoelectronic package technology refers to
the package for systematic integration for optoelectronic devices, electronic devices,
and functional application materials. (4) MEMS package technology merges micro-
electronic package technology and mechanical engineering technology.
1052 G. Yu et al.

MSP divides into three package levels including die level, device level, and
system level. (1) Die level packages: package for protection of fine components in
micro devices (e.g., pressure sensor, cantilever beam, microelectrode, microchannel,
etc.). The main goal is to protect the die and other core components to prevent plastic
deformation or fracture; to protect the circuit for system signal conversion; to
provide necessary electrical and mechanical isolation for components; and to ensure
system’s functional realization under normal and overload situation. (2) Device level
packages: usually composed of MEMS device, power, signal and system’s interface,
etc. It targets at reducing size and cost at the prerequisite of devices’ performance.
(3) System level packages: package dies and core components and major signal
processing circuits. System level package needs to shield electromagnet for the
circuits and provide proper mechanical and thermal isolation. Interface problems
in system-level package mainly arise from the assembly of components of different
sizes.
Microsystem is practically applied in automotive electronics, computers, com-
mercial equipment, communication products, consumer electronics, industrial and
medical electronics, military, and avionics systems [2]. 3D integration technology of
MSP technology is developing to 3D space. On the one hand, it can increase the
transistor density and improve the performance of microelectronic products; on the
other hand, it can develop 3D heterogeneity, realize functional diversification, and
promote the development of microsystem package products. This will reduce size
and weight and improve the performance and intelligence level of microsystem
package products in the future.

Multi-chip Modules (MCM)

Multi-chip module (MCM) packaging assembles various different micro devices

(i.e., IC chips, SMT devices, etc.) on multilayer substrates through micro-soldering
and packaging processes to produce microelectronic products (i.e., modules, parts,
subsystems, and systems) with high density, high performance, and good reliability.
MCM packaging technology is a new generation of microelectronic packaging
technology based on PCB technology and SMT.
According to different structures and processes of multilayer substrate, MCM can
be divided into three categories as below. (1) MCM-L uses multilayer PCB with
mature manufacturing technology and low production cost. However, limited by
assembling mode of chips and substrate structure, it is difficult to achieve high-
density wiring and the electrical performance is ordinary. It is mainly used for
products whose working frequency is less than 30 MHz. (2) MCM-C is based on
co-fired ceramic hybrid circuit technology with multi-layers and high density wir-
ings, high assembly efficiency, and better performance. It is mainly used for reliable
products whose working frequency is between 30 MHz and 50 MHz. (3) MCM-D
applies film deposition process on Si, ceramic, or metal substrate to form high
density wirings. MCM-D packaging is mainly used for products with high working
frequency.
55 Integrated Circuit Package Types 1053

According to packaging dimension, MCM can be divided into 2D-MCM and

3D-MCM. In comparison with 2D-MCM, 3D-MCM expands not only in x-y
dimensions but also in z direction (vertical direction).
MCM packaging has the characteristics as below. (1) Multi chips are assembled
densely on one substrate, which saves packaging material and simplifies process,
and reduces packaging size and weight. (2) MCM is a high-density product in that
dies account for at least 20% of the substrate’s area and the interconnect wirings are
shortened with reduced response time. (3) MCM is composed of analog and digital
circuits, power devices, optoelectronic devices, microwave devices, and as many
kinds of devices mounting with optimized packages. It alleviates disturbing noises
among wirings, facilitate impedance control, and improve circuit performance.
(4) MCM can relieve or prevent problems of single-IC package (e.g., thermal
resistance, lead wire, and wielding) and enhances product reliability. (5) MCM
applies several new technologies, e.g., advanced IC microfabrication technology,
thick-film, ceramic and PCB multilayer substrate technology, and advanced high-
density interconnect and packaging technologies of chips. (6) Due to its high density,
heat on unit MCM substrate increases and requires better cooling function. More-
over, new supporting equipment and software of MCM shall be developed and
improved.
3D-MCM packaging technology is a quickly developed high-end technology to
meet urgent need from high-end markets. It saves power consumption, decreases
weight and size, and reduces noise and costs. With these advantages, 3D-MCM
technology is one of the most important directions of future micro packaging
technologies. MCM packaging is expected to be widely applied in large-scale
computer systems, switching and transmission systems in the communications
industry, and electronic system products such as radar, automotive industry, medical
instruments, etc.

Embedded Packaging

Embedded packaging, or embedded-integrated packaging, is a packaging technol-

ogy that integrates passive components (e.g., capacitors, resistors, inductors) and
even active devices (e.g., chips) into the substrate to achieve system integration and
functional modularization as shown in Fig. 55.31. Compared with traditional pack-
aging, embedded packaging has the characteristics of increasing packaging density,
reducing packaging size, and realizing multi-function of electronic equipment. In
addition, embedded packaging also can improve design freedom and shorten devel-
opment cycles.
Embedded packaging substrate mainly includes ceramic, organic, silicon, and
glass substrates. (1) Ceramic substrate: It has the advantages of high mechanical
strength, good heat resistance, high heat conductivity, good stability, low thermal
expansion coefficient, high insulation resistance, and so on. However, the dielectric
constant of the ceramic is relatively large that the transmission speed of the signal
can be reduced. Ceramic needs to be sintered at high temperature, thus there is a
1054 G. Yu et al.

Fig. 55.31 Embedded package

problem of sintering shrinkage. The thickness of the ceramic substrate is large, the
size precision is poor, and the strength of the product is difficult to control. As a
result, its market share is becoming smaller and smaller. (2) Organic substrate:
compared with ceramic substrate, organic substrate does not need to be sintered at
high temperature and no sintering shrinkage problem; also it has low dielectric
constant and the cost for mass production. Its main disadvantage is thermal stress,
as its thermal expansion coefficient is quite different from an electronic device; it is
easy to form aging and structural defects and leads to the degradation of product life.
(3) Silicon substrate: silicon substrate has good heat dissipation ability and the
silicon-through-via (TSV) vertical interconnection technology is widely used in
3D interconnection technology. The main problem is that the thermal expansion
coefficient of silicon substrate does not match with that of conductive metal-through-
via material, and the residual stress in TSV may lead to cracking. (4) Glass substrate:
Glass substrate has good stability, it can be produced with no holes coating for
insulation, transparency, large size, and small thickness. It has the advantages of
moisture-proof and gas-tight. Through-glass-via (TGV) is the key technology of
glass substrate. Replacing TSV by TGV is an important research direction.
Embedding components in the substrate can greatly shorten the wiring distance,
but the interface between different materials is easy to crack due to the non-matching
of material properties (e.g., the coefficient of thermal expansion, etc.). Thus, there
are needs of further R&D in material, design, and packaging technology, substrate
structure, special strain relaxation, the repair and the 3D arrangement of the ele-
ments, etc. Ceramic substrate embedded packaging is generally used in high reli-
ability products (e.g., military products, RF products, etc.). The embedded
packaging of organic substrate is widely used in microprocessors, memory, and
other devices, and the embedded packaging of Si substrate is mainly used in high
power devices because of its high parallelism and good thermal conductivity. The
embedded package of glass substrate is mainly used in the field of display (e.g., flat
panel display, FPD). The development and progress of embedded packaging tech-
nology also need continuous R&D on process, design, and materials. In addition, the
substrate and component manufacturers and OSATs are all playing important roles in
55 Integrated Circuit Package Types 1055

realizing the embedded integrated packaging. The substrate technology with embed-
ded components will also accelerate IC industry in turn, thereby enhancing each
other toward rapid development.

Three-Dimensional Packaging

Three-dimensional (3D) packaging technology is a kind of micro-electronic assem-

bly technology as based on two-dimensional (2D) packaging technology as well as
vertical direction packaging technology. 3D packaging is divided into embedded,
active substrate, and stacked types. (1) Embedded 3D packaging is a new packaging
method, which can realize system integration and functional modularization by
embedding the components in multi-layer wiring or in the core of substrate.
(2) The 3D packaging of active substrate adopts Si wafer integration technology.
In the fabrication of the substrate, the general IC manufacturing method is used to
integrate the primary components and form the active substrate and then multi-layer
wiring is implemented. The surface assembly components and devices are attached
on the top of ICs, so as to realize the 3D packaging. (3) Stacked 3D packaging is to
interconnect two or more bare chips or encapsulated chips in a vertical direction and
then encapsulate them to form a 3D structure [3]. 3D packaging (wire bonding and
flip chip) is illustrated in Fig. 55.32.
3D packaging technology has the characteristics of increasing package density,
reducing package size, improving signal transmission speed, reducing power con-
sumption and noise, realizing multi-function of products, and so on. 3D intercon-
nection methods mainly include wire bonding, flip chip, through-silicon-via (TSV),
thin film wire, and so on. Among them, TSV technology can realize the vertical
interconnection between chips; without wire bonding, it can effectively shorten the
length of interconnect, reduce the delay and loss of signal transmission, and improve
the signal transmission speed [4].
In 3D packaging, the heat dissipation is the most important problem due to the
increased package density and volume reduction. Generally, the heat dissipation can
be solved by using low thermal resistance substrate and high heat transfer packaging
material, cooling 3D devices, and using heat conduction through hole between

Fig. 55.32 3D packaging (wire bonding and flip chip)

1056 G. Yu et al.

laminated elements. In addition, the chip embedded in the substrate with different
thermal expansion coefficient may produce complex stress, so special strain mitigation
measures are needed. Therefore, continuous R&D shall be performed on the design,
packaging process, components, structural changes of the substrate and packaging
equipment, survey and inspection return repair, and 3D layout of components.
3D packaging technology has been used in consumer electronics since 2014, such
as memory chip packaging (including bulk memory chip stacking) and high-
performance chips. By 2015, 3D packaging technology has been applied to some
high-end CPU, GPU, and network chips. Now, both 3D fan-out (Apple processor)
and 3D integration (including image sensors, fingerprint sensors) devices with TSV
have been produced in mass production. In the future, the advanced 3D packaging
technology will be widely used in various fields, including high technology products
and many consumer electronics.

Chip-on-Board (COB) Packaging

Chip-on-board (COB) packaging refers to technology for connecting bare chips with
conductive or non-conductive adhesives to interconnect substrates and achieving
electrical connection by wire bonding or using the flip chip (FC) technology to
connect chips to substrates for electrical and mechanical connection. Chips are
vulnerable to contamination or man-made damage if they are directly exposed to
air; it will affect or destroy the function of the chips, so it is necessary to protect chips
by epoxy molding compound, as shown in Fig. 55.33.
The characteristics of COB package are described below. (1) The main advan-
tages of COB package: Surface-mounted technology (SMT) is usually suitable for
single-chip packages, but COB packaging is more suitable for multi-chips and array
packages on the same substrate. The COB packaging has simpler interface structure
(than SMT technology) and leads to less thermal resistance at interface and excellent
heat dissipation performance, which improves product life and efficiency of devices.
COB is the package that chips are mounted on substrate directly. It has simpler
process and external circuit with reduced cost of packaging and suitable for auto-
mated production. (2) The main disadvantages of COB package: there are mainly
two kinds of substrates for high power COB package currently, aluminum (Al) and
ceramic substrate. Al substrate is cheaper, but its heat dissipation is poor; on the

Fig. 55.33 The structure of COB package

55 Integrated Circuit Package Types 1057

contrary, the ceramic substrate has better heat dissipation, but more expensive. The
properties of packaging materials have a great influence on COB package; chips not
only affect the performance of system, but also to the heat dissipation of the system;
there are also many problems in the mismatch (e.g., between chips and packaging
adhesive, chips and substrate, etc.) and heat dispersion. In the actual production, the
whole heat dissipation system is much more complex and leads to high cost.
Along with the development of LED applications, users have higher requirements
on product reliability and stability. COB package technology can directly encapsu-
late multiple chips on PCB, and it reduces process and cost; it also solves the
problem of heat dispersion of LED. In addition, COB package is widely used in
high-end, high-pixel image sensors with chips mounted on the solder pad of PCB,
bonded by wire and mounted with infrared lens, etc. In recent years, the competition
of COB market is increasingly fierce, and technology needs to be constantly
upgraded for lower cost. In the future, flip COB for LED applications with small
light source and higher efficiency is the trend of market [5, 6].

Substrate Packaging

The substrate is a carrier for IC chips providing electrical connection, protection,

support, heat dissipation, and so on. Using a substrate for packaging can achieve the
purpose of increasing the number of pins, reducing the volume, improving the
electrical performance, and multi-chip modularization. Substrate package refers to
a package form in which a package substrate is used as a chip carrier. The substrate
can be mainly divided into ceramic substrate, organic substrate, and glass substrate.

Ceramic Substrate

It mainly comprises high-temperature co-fired ceramics (HTCC) substrate and

low-temperature co-fired ceramics (LTCC) substrate. According to the base material,
the alumina ceramic substrate is divided into Al2O3 ceramic substrate, AlN ceramic
substrate, BeO ceramic substrate, SiC ceramic substrate, and so on. The ceramic
substrate has excellent mechanical strength, high thermal conductivity, good heat
resistance, good chemical stability, thermal expansion coefficient closer to the chip,
low warpage, etc. Owing to relatively large dielectric constant of the ceramic, signal
transmission speed is reduced. It is difficult to meet the requirements of thinning and
light weight with high integration, due to thick ceramic substrate, low package
density, large weight, and the cost of the ceramic substrate is relatively high.

Organic Substrate

The organic substrate can be classified into rigid substrate and flexible substrate
according to the substrate material as the most widely used type. Compared with the
1058 G. Yu et al.

ceramic substrate, high-temperature sintering is not required, the dielectric constant

is low, the processing is easy, the thickness can be made thinner, and the cost is low,
which is suitable for mass production. The main disadvantage of the organic
substrate is that the coefficient of thermal expansion (CTE) is quite different
from that of the chip, which is easy to cause warpage, and the thermal conductivity
is relatively low. The effect of these two aspects is mainly reduced by improving
the substrate material. The package form using the organic substrate as a carrier
mainly includes ball grid array (BGA) and land grid array (LGA) and mostly
interconnected by wire-bonding (WB) and flip-chip (FC) process. The organic
substrate shortens the distance from the chip to the terminal, reduces the signal
transmission path, leads to inductance and resistance, and improves the perfor-
mance of the circuit. The organic substrate thickness is getting thinner. The line
width and spacing, the lead-out pad or the solder ball size, and pitch are also
reduced, and the number of input/output ports can be greatly increased at the same
package size. (For instance, high-density interconnector (HDI) greatly improves
the capacity and performance of the product.) The organic substrate can integrate
multiple chips that have different functions on one substrate. Passive components
can also be buried in the substrate as needed. It not only reduces the size of the
system, but also the distance of signal transmission and power dissipation for
further improving the product performance.

Glass Substrate

The glass substrate, mainly used for flat panel display (FPD), is one of the basic
materials. The main principle is to form a conductive pattern by vapor-depositing a
conductive film on the glass that has fine surface flatness and using photolithography
for patterning. To achieve high electrical resistivity, low thermal expansion, good
chemical properties, and ultra-high flatness, the circuit is connected by conductive
rubber strip or conductive tape.
The ceramic substrates are generally used in high-reliability products (such as ICs
for aerospace), high-power density RF circuits, power management circuits, etc. The
organic substrates are widely used in microprocessors, memories, field-
programmable gate arrays (FPGA), digital signal processing (DSP), power amplifier
(PA), and other devices. Due to its good performance, the organic substrates are
often used to special fields, e.g., aviation, automotive, medical, etc. The glass sub-
strates are mainly used in the area of FPDs.
Substrate package will become lighter, thinner, higher density, and larger
capacity (system-level 3D package) with its technical advantages. Fan-out pack-
age uses organic substrate, glass substrate, or Si substrate as package carrier,
including FO-WLP (fan-out wafer-level package) and FO-PLP (fan-out panel-
level package). The fan-out structure can greatly increase the number of input/
output ports and using the process of wafer level or large board-level package can
55 Integrated Circuit Package Types 1059

Fig. 55.34 The development trends of substrate packaging

increase efficiency and reduce production costs. The fan-out package will be a
trend in substrate package, including FO-MCP (fan-out multiple chip package),
FO-POP (fan-out package on package), FO-SiP (fan-out system-in-package), and
3D FO-POP (the fan-out 3D package). The development trends are shown in
Fig. 55.34.

Classification of Packaging

According to the different materials, the packaging can be divided into plastic
packaging, metal packaging, ceramic packaging, and glass packaging.

Plastic Packaging

It is a kind of packaging methods that takes plastic as the shell of IC. It protects the
semi-finished products after the wire bonding process by epoxy resin and other
molding materials. Advantages of plastic packaging: Simpler processes and suitable
for automated production with efficiency; easy to achieve thin, miniaturization, and
lightweight due to the reduced weight and volume; and it can save a lot of metal and
other materials due to the low cost of the shell. Disadvantages of plastic packaging:
Poor mechanical properties; poor thermal conductivity; no electromagnetic
shielding; and insufficient airtightness. Plastic packaging is the most commonly
used form of packaging as seen everywhere in consumer electronics, automotive
electronics, and aerospace electronics.

Metal Packaging

It is a kind of packaging methods that takes metal as the shell of ICs. It is one of
the packaging methods that can meet the high reliability requirement. Main
characteristics of metal packaging: It can well protect the chip from environment
due to the excellent thermal conductivity and mechanical properties; it can be
used among wide temperature range usually 65  C to +125  C; it has good
1060 G. Yu et al.

airtightness and small leakage rate; it is packaged by metal shell with ceramic
substrate and various types of insulator packaging. When metal packaging is used
in high or low temperature, high humidity, strong impact, and other harsh
environments, it can play a good physical protection of the chips. It is widely
used in the military and highly reliable civilian electronic packages as the
guaranteed package reliability due to its good electromagnetic shielding and
small thermal resistance.

Ceramic Packaging

It is a kind of packaging methods that takes ceramic as the shell of IC. It is one of the
packaging methods that can meet the high reliability requirement. Advantages of
ceramic package: Good airtightness sealing protection for IC and excellent reliabil-
ity; good high frequency insulation performance of ceramics for high frequency,
ultra-high frequency, and microwave applications; and stable electrically, heat, and
mechanically. Disadvantages of ceramic package: Brittle and easy to be damaged by
mechanical stress; expensive in raw materials, complex process, low batch produc-
tion efficiency, and high cost; weaker in the ability of thinness, miniaturization, and
process automation than plastic packaging; and no advantage in high I/O density IC
packages. Ceramic packaging is mainly used for products with high reliability and
open seal structure requirements (e.g., surface acoustic wave (SAW) devices, GaAs
devices with air-bridge, MEMS devices, etc.).

Glass Packaging

It is a kind of packaging methods that takes glass as the shell of IC. It is an

important packaging method in high reliable airtight packaging technology.
Glass materials can also be used for the sealing of ceramic-ceramic, ceramic-
metal and other materials. Advantages of glass packaging: Good electrical insu-
lation, high temperature resistance, acid and alkali resistance; good airtightness;
simpler technology and low cost compared with other kinds of airtight packag-
ing; and adjustable thermal properties by the composition of the glass. Disad-
vantages of glass packaging: High process temperature to about 430  C and long
holding time and not suitable for temperature sensitive circuits; not easy to
achieve vacuum packaging; need electroplating treatment of the external pin
after sealing and special control the erosion of the glass in the electroplating
process; and weak mechanical strength and easier glass broken under mechanical
impact. Glass packaging is widely used in diodes, memory, LED, MEMS sensors,
solar cells, exhaust temperature thermocouple electrode components for aviation
engines, and other products. With the development of electronic components
toward miniaturization, high performance, and high reliability, the sealing tem-
perature of glass packaging is required to be lower and sealing strength is
required to be higher.
55 Integrated Circuit Package Types 1061

Package Interconnects

Package interconnects refer to that I/O of the chips were connected with the package
substrate by wire bonds, metal bumps, etc., and as a result, the output of the chip
function is realized. Package interconnects include wire bonding, tape automated
bonding (TAB), and flip-chip (FC) bonding technology.

Wire Bonding (WB)

Wire bonding technology includes ultrasonic thermal compression bonding and

ultrasonic wedge bonding. (a) For ultrasonic thermal compression bonding technol-
ogy, metal wires are used, and with the heating of the substrate, lead frame, under the
force and ultrasonic from bonding head of wire bond machine, ceramics capillary is
used to make bonding between metal wire and chip pads, between wire and
substrate, or terminals of lead frame. (b) For ultrasonic wedge bonding technology,
in order to realize function I/O, under the force and ultrasonic applied by wire bond
machine bonding head, metal wedge capillary is used for the bonding between the
metal wire and chip pads, between metal wire and substrate, or lead frame. Metal
wires included pure Au wire, Pd-Cu wire, Ag alloy, bare Cu wire, Al wire, Al ribbon,
etc. The selection of metal wire depends on the current carrying capacity, cost, Al
thickness on chip pads, corrosion resistance, etc. Figure 55.35 is the local diagram of
ultrasonic thermal compression bonding production.

Tape Automated Bonding (TAB) [7]

It is one packaging technology, in which, ultrasonic thermal compression machine

is used to realize the soldering between bumps on chip surface and the bumps on
tape (Fig. 55.36); then the chip is encapsulated by packing as in Fig. 55.37. The

Fig. 55.35 Local diagram of wire bonding with ultrasonic thermal compression
1062 G. Yu et al.

Fig. 55.36 Tape automated bonding

Fig. 55.37 Tape automated bonding packing

key process of TAB includes bump manufacture, tape manufacture, inner lead
bonding to outer lead, and encapsulation. The requirement for tape material is high
temperature performance, good thermal matching, low shrinkage, and high
mechanical strength. The typical bump material on chip surface is Au or
Au-alloy. The advantages of TAB are light, thin, short, and small in package,
and high density of interconnects, better electrical performance, and higher bond-
ing strength than wire bonding.

Flip-chip Bonding

Flip-chip bonding technology, bumps are fabricated on chip electrode pads, and then
bumps are bonded with the pads on substrate or lead frame surface to realize the
function I/O of the package. Bump types on chip surface include Cu pillar, solder
ball, and Au bump. Bonding types include IR reflow and thermal compression bond
55 Integrated Circuit Package Types 1063

Fig. 55.38 The local drawings of a flip chip

(TCB). The method of Cu pillars and solder bumps is to flip the chip, then dipping
wash-clean flux or non-clean flux on the surface of Cu pillars and solder bumps, and
connect the chip to substrate or lead frame by IR reflow. The bonding method for Au
bumps is to coat non-conductive paste (NCP) on substrate surface or stick
non-conductive film (NCF) on the surface of bump wafer, then flip the chip, and
connect the chip to substrate by thermal compression. Flip-chip materials include
molding under-fill with epoxy molding compound, capillary under-fill, NCP, and
NCF. Figure 55.38 shows the cross-sectional view of flip chip interconnects between
die and organic substrate using Cu pillar.
Currently, wire bonding is still the major packaging interconnect technology for
low cost. But it is not suitable for products with high density and high frequency
requirements. Flip chip is suitable for high density, high frequency, and high current
products, such as power management, smart terminal processors, etc. TAB is
majorly used for large-scale multi-lead IC packaging.

Lead Frame Package

The following aspects of lead-frame package are discussed: (1) Definition, lead
frame (LF) type package usually refers to package with the carrier of lead frame,
which is made of copper-based alloy, iron nickel alloy, and so on, mainly
different from ceramic shell and organic laminated substrate packaging. The
outline series of the lead frame class package is quite wide (e.g., TO, DIP, ZIP,
SIP, SOP, QFP, PLCC, QFN, DFN, SOD, and SOT). (2) Classification: According
to the different production mode of lead frame, it can be divided into die stamping
lead frame and chemical half-etching lead frame. In the 1970s, American corpo-
ration Olin developed low-cost Cu-based alloy C19400 and C19500 materials for
lead frame production, promoting the stamping lead frame development, for
which forming more than 10 stamping lead-frame series such as DIP, SOP,
1064 G. Yu et al.

QFP, and TO. Since the twenty-first century, the lead frame produced by the semi-
etching process has QFN, DFN, and other series, which are mainly produced by
the semi-etching method of chemical agents. (3) Characteristics: Lead-frame
class encapsulation has internal lead integrated with exposed pin or terminals,
which has excellent electrical output capacity. Stamping lead-frame has the
advantages of high production efficiency and low cost, but it also has the
disadvantages of large package size, low package density, low package effi-
ciency, and high package comprehensive cost. The lead frames used for QFN,
DFN, and other half-etched lead frame packaging also have the disadvantages of
low production efficiency and high cost, but they have the advantages of small
package size, high unit density, high packaging efficiency, and low comprehen-
sive packaging cost. Half-etched lead frame is suitable for QFN, DFN, and QFP
with high pin number which is difficult to be realized by stamping method or lead
frame which has not been finalized in the initial stage of product development.
When the total number of encapsulated I/O ends exceeds 300, it is difficult to
produce a suitable lead frame no matter by die stamping or etching. Generally, it
needs to replace the lead frame with laminated substrate with high cost. (4) Appli-
cations: The lead frame type package is mainly used in the production of the total
number of I/O terminals less than 300 devices, having high proportion in con-
sumer, industrial, automotive fields, and so on. (5) Development trend: Lead
frame class encapsulates gradually developed from the hole instrumentation to
surface mounting, from double row to quadrilateral and arrays, from 1.27 mm and
1.0 mm, 0.8 mm, and 0.65 mm to narrower pin pitch of miniaturization, thin,
integration of high-density packaging development, DIP, SOP, QFP lead frame
encapsulation gradually replaced by no pin DFN and QFN, and some TO prod-
ucts have been replaced by short pin or no pin power DFN.

Hermetic Package and Non-hermetic Package

One of the purposes of packaging is to insulate the chip from external gases;
therefore, packaging can be divided into two types: hermetic package and
non-hermetic package.

Hermetic Packages

It is a kind of packages that can prevent water vapor and other pollutants from
intruding for high reliability packages. Hermetic packaging materials include metal,
ceramic, and glass. Hermetic packages usually need to be heated to a higher
temperature before packaging to remove moisture. Hermetic packages prevent
pollution and greatly improve the reliability of circuits, especially active devices.
(a) Metal packages are the most commonly used type of hermetic package. Glass
55 Integrated Circuit Package Types 1065

insulators and ceramic insulators are commonly used to make signals and the input
and output ports of power supply. The metal material is mainly made of 4 J29 (Fe54-
Ni29-Col7 alloy, corresponding to ASTM F-15 alloy). It has excellent bonding
properties with glass and is often used as cavity and pin materials. Metal package
not only has excellent water molecule permeation resistance but also provides good
heat conduction and electronic shielding performance. (b) In the manufacturing
process of ceramic shell or ceramic substrate, W or W-Mo and other metal pastes
are printed on the raw ceramic diaphragm, and interconnect wires, through holes,
and metallized sealing areas are formed during high temperature co-firing. Then, Ni
layer is activated and plated, and Ni-Au layer is plated after brazing metal parts; the
cover plate made of Fe-Ni alloy and Fe-Ni-Co alloy is plated in the same way with
4 J42, 4 J29 and others have similar expansion coefficients with ceramics. The Au80/
Sn20 alloy solder commonly used in the nitrogen protective furnace is melted to
form a seal. (c) Another cheap but less reliable method of sealing is to use
low-melting point glass to seal a ceramic cover plate and the necessary metal leads
directly onto the ceramic base. This method simplifies the structure and process
steps, greatly reducing the cost. Glass can be used for both metal and ceramic
package. Glass materials have good chemical stability, oxidation resistance, electri-
cal insulation and compactness, and their thermal properties can be changed by
adjusting the composition.

Non-hermetic Package

Non-hermetic packaging uses plastic as IC shell, mainly thermosetting plastic,

including organic Si, polyester, phenolic, and epoxy, among which epoxy resin is
the most widely used. Relatively speaking, non-hermetic package is a kind of
packaging in which water vapor and other pollutants easily penetrate into circuit
components. It is developing rapidly, with the progress of plastic packaging technol-
ogy and chip passivation technology, the failure ability of electronic devices caused
by moisture intrusion has been greatly reduced, so plastic package is becoming more
and more important. Compared with hermetic package, non-hermetic package has the
advantages of simpler manufacturing process, high production efficiency, small
weight, suitable for miniaturization of circuit, good insulation performance, and
lower cost. The disadvantages of non-hermetic packaging are some poor mechanical
properties, weak heat dissipation and heat resistance, easy expansion, and so on.
Hermetic packages are widely used in multi-chip module (MCM), micro-electro-
mechanical system (MEMS), monolithic microwave integrated circuit (MMIC), and
military fields because of its high reliability. Non-hermetic packages are widely used,
such as consumer electronics, high-end processors, vehicle products, etc. in semi-
conductor industry. Now, people are pursuing the high performance of electronic
products, but at the same time, they are demanding higher and higher hermetic
performance, which requires high reliability, low cost, and other challenges by
developing new technologies, processes, and materials.
1066 G. Yu et al.

Package Type Selection

The selection of package types is an important step for IC design, assembly, and final
test procedure. It may cause IC product function cannot be realized, higher cost, even
the failure of IC design if unsuitable package type is selected. For package type
selection, full consideration [8] should be taken for assembly method, package body
size, total package pin counts, product reliability requirement, heat dissipation
performance, cost etc.

1. Assembly method. The first step for package selection is to fix assembly method
which directly determines how to design PCB and how to connect IC product
with PCB when completed IC packaging. PTH (pin through hole) and SMD
(surface-mount device) are the two main types. PTH is to connect PCB through
package outline leads by plug in type (e.g., SIP and DIP); SMD means ICs are
bonded on PCB quickly by surface mount technology (e.g., QFP, QFN, BGA,
SOP, etc.).
2. Package body size. Chip size (length, width, thickness) will be constricted due to
the capability limitation of assembly process. It needs to make sure chip can be
mounted in the package, then to select package body thickness according to
product thickness. Now packages are getting thinner since consumer electronics
is becoming lighter, thinner, shorter, and smaller; and a smaller, thinner package
can save PCB smaller area and lower cost.
3. Package pin counts. The total pin counts should be equal to or more than the total
leading-out pin number about IC chips required (including input, output, control,
power, ground, etc.)
4. Product reliability requirement. Although plastic package belongs to
non-hermetic packaging, its anti-moisture and mechanical performance and the
thermal stability are not very good, it has cost advantage. Metal and ceramic
packages belong to hermetic packaging, which have better performance on
moisture resistance, heat dissipation, and mechanical properties. Their assemble
accuracy is not good and the cost is higher. Therefore, military and aerospace ICs
with high reliability requirements should choose ceramic or metal-ceramic pack-
aging; as for industrial and consumer electronic products, plastic packaging is
suitable due to general reliability requirement and low cost.
5. Requirements for heat dissipation and electrical performance. ICs will generate
heat when in operation, so it needs to perform thermal and electrical simulations
to confirm whether it can meet customer design targets. Thinner package body
size is better for heat dissipation. Normally, for high power product, designer
should not only consider the selection of low resistivity, high thermal conductiv-
ity material for die bonding, using of high thermal conductivity encapsulation
material, using alloy for soldering process, but also choose enhanced packages
with embedded/exposed heat sink on package (e.g., HSPBGA, HSBGA,
EDHSQFP, DHSQFP, QFN, E-pad LQFP, etc.) to increase the product’s heat
dissipation and cooling capability.
55 Integrated Circuit Package Types 1067

6. Cost. For electronic products, high packaging cost will make the electronic
product uncompetitive and lose the market and customers. In general, product
with large package size is expensive than that with small package size for the
same package type. For different package types, the cost for package using
substrate is higher than using lead frame; product with multi-layer substrate is
expensive than with single layer substrate; product cost with high reliability
requirement is higher than that requiring low reliability.

References
1. International Technology Roadmap for Semiconductors 2005 Edition Assembly and Packaging
(2005), 31–32
2. Tummala TT, Fundamentals of Microsystems Packaging (2001)
3. D. Deng, F. Wu, L. Zhou, et al., 3D package and its latest research. Micronanoelectron. Technol.
47(7), 443–450 (2010)
4. Y. Yan, Y. Ji, X. Ming, 3D-TSV package technology. Electron. Packag. 14(7), 1–5 (2014)
5. S. Qi, S. Ding, P. Zheng, et al., Research of the effect on the LED optical performance from COB
packaging [J]. Electron. Packag. 12(3), 6–9 (2012) 18
6. C. Huang, Y. Wang, B. Peng, Research and analysis of high-power LED COB package technol-
ogy [J]. China Light Light. 5, 1–5 (2014)
7. Greig WJ, Integrated Circuit Packaging, Assembly and Interconnections (2007)
8. C.A. Harper, Electronic Packaging and Interconnection Handbook, 4th edn. (The McGraw-Hill
Companies, 2005)
Key Technologies and Processes
for Traditional Packaging 56
Daquan Yu, Zhi-Quan Liu, Ming Li, Linghua Zhu, and Xiaowei Guo

Contents
Wafer Thinning Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Mechanical Grinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
Dry Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
Wet Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
Wafer Dicing Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Die-Attach Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Wire Bonding (WB) Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Molding Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Plating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
SOP Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
QFN Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Wire Bond BGA Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Back Grind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Die Saw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
Die-Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
Plasma Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084

D. Yu (*)
School of Electronic Science and Engineering, Xiamen University, Xiamen, China
e-mail: yudaquan@xmu.edu.cn
Z.-Q. Liu
Shenzhen Institute of Advanced Electronic Materials, Shenzhen Institutes of Advanced
Technology, Chinese Academy of Sciences, Shenzhen, China
M. Li
School of Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, China
L. Zhu
Wuxi Zhongwei High-tech Electronics Co., Ltd., Wuxi, China
X. Guo
Huatian Technology (Xi’an) Co., Ltd., Xi’an, China

© Publishing House of Electronics Industry 2024 1069

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_56
1070 D. Yu et al.

Wire Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085

Molding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Post Curing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Reballing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Cut & Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Technology and Processing of Metal Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Wire Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Sealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Leak Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Ceramic Packaging Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Sealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
Leak Detection [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
Plant Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091

Abstract
Today, traditional packaging technologies still play important roles for most of
the ICs, MEMS, and sensors due to the advantages of low cost, good reliability,
and huge production capacity. Continuous innovations of these technologies are
driven by new applications such as 5G, automotive, IoT applications, etc. In this
chapter, the main processes of traditional packaging such as wafer thinning, wafer
dicing, die-attach, wire bonding, molding, plating are introduced. Then the
structures, processes, developing trend, and applications for several typical tra-
ditional packaging technologies, i.e., SOP (small outline package), QFN (Quad
flat no-lead package), WB-BGA (wire bond ball grid array), Metal Packaging,
and Ceramic Packaging are explained and discussed.

Keywords
Wafer thinning · Wafer dicing · Die-attach · Wire bonding · Molding · SOP ·
QFN · WB-BGA · Metal packaging · Ceramic packaging

Wafer Thinning Process

Wafer thinning, also referred to as back-side grinding, is the process to thin the wafer
to required thickness by grinding or etching. The wafer thinning is not only impor-
tant for thin package, but also conductive for heat dissipation. With the continuing
demand for small form factor and ultra-thin package, wafer thinning becomes an
essential process for both traditional packaging and wafer level packaging (WLP).
Currently, there are a number of methods for wafer thinning such as mechanical
grinding, dry etching, wet etching, etc. The selection of wafer thinning process is
based on the specific requirements.
56 Key Technologies and Processes for Traditional Packaging 1071

Mechanical Grinding

Mechanical grinding is the most widely used wafer thinning technology. There are
two thinning modes. One is creep-feed mode as widely used for the wafers with
diameter less than 150 mm, where the wafer is motionless, and the grinder is rotating
to thin the wafer. Another is in-feed mode as widely used for wafers with diameter
larger than 200 mm; where wafer and the grinder are both rotating at the same time.
Currently, in-feed mode is the mainstream in packaging industry. Normally, there are
coarse and fine grinding stages. The coarse grinding removes main body of the wafer
by using diamond grinding wheel with large abrasive grains. The fine grinding
removes the final 40 ~ 100 μm thick silicon to the target thickness by using high-
speed diamond wheel with small abrasive grains. Typical automatic grinder has two
principal axes for coarse and fine grinding respectively and three chuck tables for
wafer placement which can be rotated. The main issue for mechanical grinding is
the wafer damage which is usually caused by lower mechanical strength of the
thin wafer, warpage, grinding damage, thermal stress, and Si particles during
grinding. In order to improve chip strength and reduce the wafer warpage, the
damage layer caused by fine grinding needs to be removed and the stress will
be released. The removal process can be performed by polishing, dry etch or wet etch.

Dry Etching

Under high frequency, SF6 gas will form plasma containing F ions, which can etch
the silicon wafer surface. Plasma etching speed can reach 10 μm/min, and the
removal thickness of the Si wafer is determined by etching time. For some wafer
level packaging application, the Si thickness to be removed can be 50 μm.

Wet Etching

There are two kinds of wet etching methods, i.e., isotropy and anisotropy. For isotropic
etching, HF and HNO3 mixture solution is used. The mechanism is that the HNO3
oxidized Si, and then HF can dissolve SiO2. The etching speed can reach 15 μm/min.
For some applications, TMAH solution is used. The etching speed is usually 1 μm/min,
which is quite slow. For anisotropy etching, KOH solution is used. OH ions react with
Si and the final etching profile is directly related to Si crystal orientation.
With the trend of package miniaturization, the thickness of the wafer after
thinning becomes thinner and thinner. In order to reduce the risk of wafer broken
during wafer transfer between equipment, thus an integrated system was introduced
for grinding, polishing, tape release, dicing tape attachment all in one single system.
The product after wafer thinning can be proceeded by dicing directly, which benefits
the improvement of the packaging capability.
1072 D. Yu et al.

Wafer Dicing Process

Wafer dicing process is also known as wafer cutting process, which refers to use
different methods to separate dies or chips from the wafer. It is an essential process in
semiconductor packaging. At present, wafer dicing can be divided into three differ-
ent methods, i.e., mechanical, laser, and plasma dicing. (1) Mechanical dicing: Ultra-
thin diamond blade with high-speed rotating is used to cut through the wafer into the
dicing tape 20 ~ 30 μm. The wafer is divided into chips along the scribe line between
the chips. At present, the blade used for mechanical cutting is mainly the hub blade,
on which the diamond is formed by electroplating. During the process of mechanical
dicing, cooling water is necessary to cool the blade and remove the heat generated
during cutting, and take away the pollutants and Si particles. (2) Laser dicing: It can
be divided into straight and stealth dicing (SD). Straight dicing refers to laser cutting
through the whole wafer to separate individual chips. The theory of stealth dicing
(SD) is to use the traditional diode-pumped solid-state (DPSS) laser (nm-level
infrared) to penetrate through the material surface and focus on the internal positions.
When the internal laser power density exceeds the critical value, the ribbon SD layer
(polycrystalline layer/high-dislocation density layer and microcrack/hole) can be
formed at any depth, and then the chips can be separated by wafer expansion. SD
technology overcomes the disadvantages of traditional laser dicing, such as thermal
damage caused by material melting. SD is quite suitable for ultra-thin Si wafers to
achieve high-speed and high-quality cutting. (3) Plasma dicing: In the process,
firstly, photoresist is used to cover the surface of the wafer. Then remove the
photoresist on the dicing street between the chips by exposure and developing
process. The exposed Si will be etched by plasma, which was produced by ionized
special gases formed under high-frequency direct or alternating current, in the
low-pressure vacuum chamber. At present, plasma dicing is preferably used for
the dies with ultra-small size. On one hand, it can reduce the dicing cost and improve
the dicing quality. On the other hand, it can reduce the width of dicing scribe lines
and increase the numbers of gross chips on the wafer.
With the development of wafer manufacturing process below 90 nm, low-k
material was used as the insulator between the conduct interconnects. Due to the
poor heat resistance, chemical, mechanical ductility, and poor stability of low-k
material, wafer dicing becomes more challenging. Conventionally, the industry uses
the straight laser dicing to remove the low-k dielectric layer in the scribe line then cut
the wafer into individual dies by mechanical dicing.

Die-Attach Process

Die-attach is also called chip mount process. Generally, chip mount means that chips
or other carriers are fixed together by a machine using bonding materials on a
platform, or a cavity which is constructed to realize a certain function, or a device
56 Key Technologies and Processes for Traditional Packaging 1073

which is composed of selected materials. The earlier traditional definition of chip

mount refers to the process step before packaging, where the diced wafer dies are
attached to the lead frame or substrates of different packaging forms using the attach
glue, film or other materials through the special mounting equipment [1]. Purpose of
die-attach is to achieve an effective physical connection between the chip and the
carrier, to meet the electrical performance requirements achieving a conductive or
insulating connection between the chip and the frame, to conduct the heat generated
on the chip to the outside of the device as a conductive medium meeting a certain
dissipation effect [2]. There are some requirements of die-attach process. Permanent
attachment is required. The electronic products should not fail when operating on
field; this is especially important for products used in harsh environments. The
materials selected should be free of contaminants and no gas is released during the
heating process of remaining production flow. Die-attach process itself should have
high efficiency and low cost [3].
The die-attach process is roughly classified into the following four categories.
(1) Silver die-attach: Known as epoxy attachment, it refers to the incorporation of
silver (Ag) powder into the liquid resin binder for bonding chip and frame to form a
permanent physical connection and to achieve heat conduction, which is an eco-
nomical and practical assembly method. (2) Eutectic die-attach: The metal melts at
the high temperature and its atoms are active under the molten state. The principle
used is that at least the melting point of one composite is lower than the melting point
of others to complete the soldering attachment process. The materials used for the
eutectic mounting are generally Au-Sn, Au-Si, Au-Ru, etc. (3) Solder die-attach:
Lead-tin (Pb-Sn) wire is used as the bonding medium between the chip and the
frame. The lead-tin wire is melted into liquid under high temperature and then to
form a certain structure by a design spanker with a pressure. Before solder die-attach,
the frame will pass through the track with a N2-H2 mixed gases for the oxidation-
reduction reaction. (4) Thermosonic flip-chip die-attach: The principle is to apply
ultrasonic energy to the bumps on the chip with a certain pressure and temperature in
a certain period of time, to achieve the connection of the chip to frame by the bond
between bumps and frame, substrate or pads. The key materials, tooling, and their
functions for die-attach equipment are listed in Table 56.1.
The main die-attaching steps are as follows. (1) Die pickup: The ejector pin jacks
up the chip from bottom of the blue film and the chip contacts the vacuum nozzle.
Then the chip is pulled up by the nozzle due to the negative pressure, which provides
a reverse force for the adhesion from the blue film as shown in Fig. 56.1. (2) Epoxy
writing: The liquid epoxy (conductive or insulating) is applied to the pad of lead
frame as shown in Fig. 56.2. (3) Bonding: Mount the chip on lead frame coated with
epoxy as in Fig. 56.3. The die-attaching process needs to be continuously improved
according to the changes in materials and package characteristics. With the minia-
turization of electronic devices, the development of ultra-small ultra-thin chips will
bring unprecedented challenges to die-attaching process. It will also enrich more and
more complex and higher-intensity interconnect processes [4].
1074 D. Yu et al.

Table 56.1 The key materials, tooling, and functions for die-attach equipment
Materials/tooling Functions
Pickup tool Rubber material, formed by molding process, to directly contact the chip,
to pick the chip by negative pressure followed reliable movement, and finally
to realize attachment.
Needle To jack up the chip, allowing it to be released from the film on the wafer
quickly, and to support suction nozzle for chip pickup.
Dispensing tool According to a certain shape, the silver paste is accurately written in a
predetermined position on the stage.
Lead frame Used as a circuit connection frame to fix and carry the chip, and to provide
physical support.
Silver paste Ensure the physical bond of the chip and frame, and achieve functions such
as conduction, insulation, and heat dissipation, etc.
Bonding carrier Alloy box for storing of lead frames.

Fig. 56.1 Die pickup

Fig. 56.2 Epoxy writing

Fig. 56.3 Bonding

56 Key Technologies and Processes for Traditional Packaging 1075

Wire Bonding (WB) Process

Wire bonding is a technique to interconnect chip (or other component) and substrate
(or lead frame) in microelectronic packaging. Wire bonding is widely accepted
because of its flexibility and ease of use [5]. In the wire bonding process, thin
metal wire (usually Au wire in diameter of 25 μm) is bonded to a metal pad on the
chip (usually Al) firstly and then the other side of the wire is bonded to substrate or
lead frame to form the interconnect. Using combination of temperature, force,
ultrasonic power, and time, wire bonding can realize the electrical interconnect
between chip and substrate or lead frame, heat dissipation of the chip, and signal
transmission between chips. Wire bonding is a kind of solid phase bond technology,
whose mechanism includes electrons migration and atomic diffusion between the
wire and the chip pad, and finally metal bonding at atomic level is resulted for a
stable and reliable interconnect.
Depending on the input energy, there are three kinds of wire bonding technolo-
gies, namely, thermocompression bonding, ultrasonic bonding, and thermosonic
bonding. According to the type of capillary, wire bonds can be classified into two
types, which are ball-wedge bonding and wedge-wedge bonding. Among the wire
bonding technologies, thermosonic ball bonding is the most commonly used as
related to the oxidation resistant of Au, Cu, and Ag wires with high tensile strength,
conductivity, and good reliability. However, Al wires are easy to be oxidized and
difficult to form Free-Air-Ball (FAB), they are generally used for wedge-wedge
bonding process. Common packaging forms using wire bonding are TSSOP, QFN,
DFN, BGA, and 3D packages.
The wire bonding process is illustrated in Fig. 56.4. FAB is formed during step-1.
The capillary travels down to the first bond location (bond pad) in step-2, and the first
bond (ball bond) is made in step-3 by bonding a spherical ball to the pad using
thermal and ultrasonic energy. Looping motions are programmed to obtain the
desired loop height and shape (step-4, -5, and -6). The second bond (stitch/wedge
bond) interconnects the opposite end of the wire loop to the metal of the substrate
(step-7). After the capillary rises to pay out the wire tail, the tail is broken off. The
bonding tool rises further to the ball formation height, and then forms FAB (step-
8 and step-9). Common mechanical tests to evaluate the quality and robustness of
joints include shear and pull tests which can be both nondestructive and destructive,
according to the standard of MIL-STD-883 (Method 2011.7 for destructive testing
and Method 2023.5 for nondestructive testing). High-temperature storage tests
(HTST), temperature shock and temperature cycling tests (TS&TCT), humidity-
related reliability tests (PCT and HAST), and electromigration tests (ET) are used to
evaluate wire bond reliability. JEDEC standard is generally used for test conditions
and methods.
Au wire is preferred in wire bonding due to its excellent ductility and resistance to
corrosion and oxidation; however, Au wire is expensive. Furthermore, the interme-
tallic compound (IMC) grows fast. Au wire is also ease to form Au5Al2, which has a
bad effect on reliability. In order to meet the requirements of high density and fine
pitch, materials with higher thermal conductivity and lower electrical resistivity
 1076

Fig. 56.4 Illustration of wire bonding process

D. Yu et al.
56 Key Technologies and Processes for Traditional Packaging 1077

(such as Cu and Ag) are used in wire bonding. Thermal conductivity of Au, Cu, and
Ag are 320 W/(m
K), 400 W/(m
K), and 430 W/(m
K) respectively. Meanwhile, the
electrical resistivity of Au, Cu, and Ag are 2.20 Ω
m, 1.72 Ω
m, and 1.63 Ω
m
respectively. However, pure Cu wire is prone to oxidation and pure Ag wire has the
problem of Ag migration. Therefore, Pd-coated Cu wire and Ag alloy wire are most
commonly used wires in package. The corresponding pad materials are Al and Au,
while Ni/Pd/Au pad is more suitable for Cu wire bonding. High-purity Au wires
(99.99%, 4 N) are used in the industry, and the common diameter range is 15–50 μm.
Au wire has excellent HAST (Highly Accelerated Temperature and Humidity Stress
Test) reliability, which is mostly used in military and aerospace electronic devices
with higher reliability requirements. Cu wires and Pd-coated Cu wires with purity of
4 N are most commonly used. The diameters of Cu and Pd-coated Cu wires are
18–50 μm and 18–30 μm respectively. Thickness range of Pd layer of Pd-coated Cu
wire is about 50–100 nm. Because the HAST reliability of Pd-coated Cu wire is
better than that of pure Cu wire [5], pure Cu wire is mostly used for lead frame
packaging, while Pd-coated Cu wire is used for substrate packaging.
The diameter range of Ag alloy wire is in the range of 16–75 μm. According to the
content of Ag, it can be divided into low Ag alloy wire (88%), medium Ag alloy wire
(95%), and high Ag alloy wire (98%). Ag alloy wire is commonly used in LED
package and substrate package. However, HAST reliability of substrate package of
Ag alloyed wire is lower than that of Pd-coated Cu wire. Furthermore, the reliability
of medium Ag alloy wire is better than that of high Ag alloy wire.

Molding Process

Molding is a packaging process that encapsulates chips or devices with molding

compound for protection. Through the molding, the chips, devices, and intercon-
nects originally exposed to outside are protected through external molding com-
pound for preventing devices from environment effect (especially humidity) and
product failures [6]. Molding technology is widely used in currently known package
types, such as TSSOP, DFN, QFN, SIP, BGA, the LGA, FSCSP, WLCSP, etc. With
the development of fan-out packaging, molding has a new function for reconstruc-
tion of the wafer, panel, and provides areas for metal wiring, and solder ball
formation. In the mainstream wafer and panel level fan-out packaging, molding is
the key process.
According to the different principles of molding, semiconductor molding can be
divided into transfer molding and compression molding, as illustrated in Figs. 56.5
and 56.6. Among them, transfer molding is widely used due to its advantages of
maturity, high reliability, and high output units-per-hour (UPH) of equipment. It is
mainly used in TSSOP, DFN, QFN, BGA, and other traditional packages. Compres-
sion molding is mainly used for the encapsulation of multilayer ultra-thin products
such as memory. Since the compounds do not flow in the molding cavity, it can
realize the nonwire sweep and ultra-thin molding, as well as the large area molding
1078 D. Yu et al.

Fig. 56.5 Schematic diagram of transfer molding

Fig. 56.6 Schematic diagram of compression molding

such as wafer level molding. It is mainly used in high-end packaging processes such
as LGA and WLCSP.
The molding material used in semiconductor sealing should have the following
characteristics. (1) Formability: It has to avoid damage to chips, gold wires, and
other products and devices, to reduce the overflow, to avoid the formation of voids
and incomplete filling, and has the property of rapid curing. (2) Reliability: It has
humidity resistance to prevent leakage current and aluminum circuit corrosion. It has
thermal deformation resistance to prevent wires from breaking, to avoid chip and
package fracture. It can endure high-temperature storage.
Molding is a thermochemical reaction process. Therefore, during the transfer of
molding compound, it will be preheated generally using high-frequency preheat
machine, where compound is put into the mold chase for 20–40 s (according to the
requirement of the mold machine) with the preheat temperature of 75–85  C (com-
pound surface temperature rather than the internal temperature). When transferring
the compound, in order to ensure the product quality, the mold temperature, transfer
pressure, transfer speed/time, clamp pressure, cure time, tablet quality, and other
parameters should be checked firstly. After the completion of molding, the product
quality shall be confirmed, e.g., the wire sweep, internal voids, delamination, and
56 Key Technologies and Processes for Traditional Packaging 1079

Table 56.2 Typical injection molding process parameters

Parameter Condition Remark
Mold temperature/ C 170 ~ 180 Depends on the mold chase and design
L/F PH temperature/ C 75 ~ 85 Depends on the mold chase
Transfer time/s 5 ~ 30 Depends on the mold chase and design
Transfer press(N/cm2) 686 If there are no flash and wire sweep, it is recommended
to use a large transfer pressure to ensure complete filling
Cure time/s 60 ~ 120 Depending on the mold size

defects in the appearance of the package, etc. Table 56.2 listed as a typical transfer
molding process parameter.
The complete molding process also includes plasma cleaning and post mold cure
(PMC). Plasma cleaning usually uses Ar and H2 mixed gas, whose purpose is to
remove the surface of the chip to be laminated dust and pollutants, and to make the
surface activation, to increase the molding interface adhesion, to prevent the occur-
rence of delamination. PMC can improve the hardness of the heat-curable compound
seals, stabilize the molecular structure of the solidified materials, reduce the stress of
the solidified materials generated when the compound seals are lowered to room
temperature after completion, and thus improve the mechanical properties of the
solidified parts.

Plating

Electroplating, also known as electrodeposition, is a method of preparing a func-

tional metal film. Electroplating is essentially an electrochemical reduction process
in which metal ions in an aqueous solution are reduced to atomic metals on a desired
substrate by means of electrons supplied from an external electric field, and by
controlling species, existence forms, concentrations of metal ions in the solution, and
trace additives, as well as temperature, current density, pH, agitation, etc., to control
the crystal morphology, crystal orientation, grain size, surface flatness, and metal
composition of the deposited metals, and finally obtain the required metal film with
special functions. Since electroplating is based on the preparation of metal film, it
mainly involves the preparation of various metal lines, pads, bumps, and contact
coatings in connectors in electronic packaging.
The advantages of electroplating are as follows: (1) Metal film or circuit
manufacturing with high density and high precision can be realized with various
lithography and mask technologies; (2) Electroplating equipment have less invest-
ment and simple process, and can realize large-scale and low-cost industrial
manufacturing compared with physical/chemical vapor deposition technology;
(3) Various special functions can be realized to meet product requirements, through
the selection of metal types and multilayer combination.
1080 D. Yu et al.

In electronic packaging, the plating process is essential. The processing

accuracy and functional requirements of electroplating vary for different pack-
ages. (1) In traditional lead frame type packages, such as DIP, QFP, QFN, SOP,
SON, etc., copper (Cu), silver (Ag), nickel (Ni), palladium (Pd), and gold
(Au) plating are mainly used for the treatment of Cu or iron (Fe)-nickel
(Ni) alloy lead frame surfaces. It is to ensure the solderability, bonding, and
protection of the surface of the frame. In order to reduce costs, partial plating is
often used for precious metal plating. (2) In the ball grid array type packaging,
such as BGA, FC-BGA, etc., the internal Cu lines in the organic packaging
substrates and redistribution lines (RDL) on the surface of flip-chip are mostly
combined by electroless copper plating and electroplating Cu. Most of the pads
on the surface need to be Ni-plated, then Ag, Au or Sn-plated, and the line width
is generally in the range of 5–50 μm. (3) In wafer level packaging (WLP), besides
Cu, Ni or Au plating for surface RDL, bumps are also made by electroplating for
products with high solder density, including masked Cu-plated pillars, Sn-plated
or Sn-plated alloy bumps. The line width of RDL is typically 1–25 μm and the
bump height can reach 200 μm.
With the development of electronic packaging technology and industry, electro-
plating will play an increasingly important role in high-density manufacturing, high-
precision manufacturing, and low-cost manufacturing.

SOP Process

The small outline package (SOP) device is a kind of wing-shaped surface mount
devices (SMD), whose pins lead out from both sides of the packaging body, and
its package structure is divided into embedded and exposed. The standard pin
pitch of the SOP is 1.27 mm, and the number of pins are in the range of 6–64.
SOP is one of the packaging forms with larger consumption in the market. SOP is
developed from DIP technology, and the derived package forms include SOJ,
TSOP, HSOP, ESOP, MSOP, VSOP, SSOP, TSSOP, EMSO, and ETSSOP. The
pin pitch of these packages is usually in the range of 0.40 ~ 1.27 mm. The most
obvious difference between SOP and DIP, SIP is that the pins of DIP and SIP are
in-line type, and the pins of SOP are wing-shaped surface mount type. The main
advantages are as follows. Compared with DIP and SIP which have the same pin
count, the SOP is much thinner and the pin pitch of SOP is reduced at least 50%
and there are more package categories derived from SOP. The connection
between chip and pin of SOP is short, and the parasitic capacitance of SOP is
smaller than DIP. Finally, the package has better heat dissipation. Figure 56.7
shows the product diagram of SOP, SSOP, and TSSOP, and Fig. 56.8 shows the
product diagram of ESOP and ETSSOP. SOP packaging technology is a surface
mount device (SMD) type packaging manufacturing process. SOP packaging
process is as follows. First, thinning and dicing, then attaching the IC chip to
56 Key Technologies and Processes for Traditional Packaging 1081

Fig. 56.7 The product diagram of SOP, SSOP, and TSSOP

Fig. 56.8 The product diagram of ESOP and ETSS0P

Fig. 56.9 The standard flow of SOP packaging process

the carrier of the SOP lead frame. After baking, bonding (wire-bonding) to
connect the chip to the chip, chip to the inner pin. Molding is used to encapsulate
chips, bond wires, and inner pins. Finally, the entire SOP production process is
completed by post mold curing, marking, plating, trim, and form and testing.
SOP packaging process standard flow is shown in Fig. 56.9. (1) Thinning: The
discs with back gold (back silver) are not thinned. Nonback gold (back silver)
wafers are roughened and finely ground to reduce the original wafer. (2) Dicing:
According to the packaging requirements, selecting a common blue film, a DAF
(Die-Attach Film) film, a CDAF (Conductive Die-Attach Film) film or a UV
(Ultra-violet Rays Film) film. At present, the dicing mainly adopts mechanical
cutting using diamond blade or laser cutting process. (3) Die-attach: Three kinds of
processes are as follows: adhesive, rubber film, and UV film die bond. (4) Bonding:
Wire bonding, the wire has gold wire, copper wire, silver alloy wire, aluminum
wire, and other materials, using ultrasonic thermal bonding process. (5) Molding:
SOP adopts injection molding process. (6) Post mold cure: Use an oven to bake the
molded product at high temperature. (7) Marking: Use the laser marking machine
on the front of the product to generate the product logo (formerly known as
“printing”). (8) Plating: Use pure tin electrodeposition process. After tinning, the
product needs to be baked. (9) Trim & form: On the integrated machine of
trimming and forming, first flushing waste, next trimming the middle ribs, then
forming, automatically into the tube. (10) Testing: Use tube or braided integration
testing technology.
1082 D. Yu et al.

QFN Process

The Quad Flat No-lead Package (QFN) package which is a surface-mount package is
a nonleaded, square-shaped package with conductive pads (leads) that are electri-
cally connected to the outside on all four sides of the package. The pitch is generally
0.65, 0.5, 0.4, and 0.35 mm. Since there is no lead on the outside of the package, the
mounting area and height are smaller than QFP. There is a large exposed heat sink on
the bottom center of QFN packages. The QFN package has no gull-wing leads, the
conductive path between the internal leads and the pads is short, and the self-
inductance coefficient and the internal line resistance are low, which can provide
superior electrical performance. The exposed heat sink has a heat dissipation path
that allows the QFN package to have excellent heat dissipation. Figures 56.10 and
56.11 show the basic structure of WB-QFN (Wire Bonding-QFN) and FC-QFN
(Flip-Chip QFN). Combined with MCP and SiP packaging technology, these struc-
tures provide a good I/O design solution for the flexible diversity of QFN, and
further increase the package density.
The QFN packaging process flow is close to that of the traditional package. The
main differences are as follows. (1) QFN lead frame generally taking the filming
process before molding. The wire bonding parameter mode is different from the
traditional one. If improperly controlled, it will cause the second bonding break. In
addition, multiple injections must be used to avoid void and wire sweep. (2) The
separation of QFN products is by package sawing process. During it, appropriate
process (such as low-temperature water) is used to avoid tin melting, resin soft knife
is used to reduce the sawing stress, and the appropriate cutting speed is used to avoid
delamination, etc. (3) QFN warpage is controlled by selecting proper molding
compound with different shrinkage rates. Chips of different thickness and size are
also need to be matched with compound shrinkage. (4) QFN lead frames are all
etched. The frame design includes stress, antidelamination, burr prevention, and
other consideration. The quality of the frame design determines the level of product
quality.

Fig. 56.10 Cross section

view of WB-QFN

Fig. 56.11 Cross section

view of FC-QFN
56 Key Technologies and Processes for Traditional Packaging 1083

The traditional QFN process is as follows:

FC-QFN product process is as follows:

With the rapid development of modern electronic information technology, there is

an increasing demand for miniaturization, portability, versatility, high reliability, and
low cost of electronic products. Because QFN packaging can well adapt to the needs,
its market share will be increasingly large.

Wire Bond BGA Process

For Ball Grid Array (BGA) packaging having, the solder balls at the bottom of the
substrate act as I/O in circuit, which increase the number of IC interconnects directly.
The large I/O spacing reduces the SMT failure rate. BGA packaging technique has
been widely used in PC chipsets, microprocessors, memories, DSPs, and other
devices since the mass production in the early 1990s. Wire bonding BGA assembly
process can be divided into frontend and backend processes. The specific processes
are shown in Fig. 56.12.

Back Grind

Wafer is thinned by high-speed spinning grind on its backside through grinding

wheel. Cooling and cleaning by water operations are needed to prevent high
temperature and chipping accumulation during thinning process. If the chip needs
to be grinded to a relatively thinner thickness, polishing treatment according to the
product type is necessary to eliminate internal stress and to prevent the generation of
chipping for less risk of chip surface cracking. After back grind, the surface film of
1084 D. Yu et al.

Fig. 56.12 BGA assembling process

the wafer would be removed by tape. Then thickness measurement and quality
inspection would also be carried out.

Die Saw

The wafer should be fixed on the metal ring through the blue film for dicing into
individual chips after back grind. Two main types of die saw methods exist, namely,
blade dicing and laser dicing. Blade dicing means cutting completely by a circular
blade on the wafer cutting path, dividing the entire wafer into individual chips, and
arranging individual chips on the blue film in an orderly manner. While laser blade is
performed by laser beam lighting on the wafer cutting path to evaporate the material
on it and, is to separate the wafer into individual chips. IC wafer process is
developing toward the process node below 10 nm. And the application of the
wafer low-k material increases. Laser dicing can meet the requirements of less
external force, small cutting width, and high cutting quality, etc.

Die-Attach

The chip would be fixed on the PCB through Ag-paste, die-attach-films (DAF), and
other patch materials based on the design drawing. Its main function is to fix the chip
and to transfer the heat on the chip.

Plasma Cleaning

Plasma cleaning before wire bonding uses ionized argon ions, electrons, and active
groups to form volatile gases on the PCB and chips. Aforementioned gases would be
pumped away by the vacuum system. Thereby the effect of surface cleaning would
56 Key Technologies and Processes for Traditional Packaging 1085

be achieved, which makes the bonding force of the wire better. Plasma cleaning
before molding is the same as it before wire bonding. It uses ionized argon ions and
oxygen ions to wash away the surface contaminants and carbides to activate the PCB
surface. Bonding force between PCB and molding compound would increase for
better product reliability.

Wire Bonding

Wire bonding is the most critical part of the assembling process. Bonding wire
(Au wire, Cu wire, Ag alloy wire) would be connected with the Al pad on the chip
and the metal pad on the PCB by wire bonding to realize electrical conduction.
Figure 56.13 shows the SEM image after BGA process.

Molding

Firstly, the molding compound is melted into a low-viscosity liquid at a high

temperature and injected into a cavity; and then the epoxy resin inside the molding
compound is solidified by auxiliary agent, e.g., hardener or coupling agent to
complete the molding process.

Post Curing

The molded material is cured under high-temperature condition. Generally, the mold-
ing compound is not completely reacted at the end of molding process, so it needs to
stabilize the molecular structure of the epoxy resin and improve the plastic body
hardness by high-temperature baking. Internal stresses would also be eliminated.

Fig. 56.13 SEM image after

BGA process
1086 D. Yu et al.

Marking

Ink printing or laser engraving on the front side of the chip would be proceed to mark
the product name, production cycle, and other information on the surface of the
product to facilitate product identification and traceability as is shown in Fig. 56.14.

Reballing

It is a special process for BGA assembling, where the flux is printed on the solder
ball pads on the back of the PCB (NiAu or Cu-plated OSP antioxidation treatment)
and the solder balls are placed. The solder balls are melted in reflow oven and
eutectic solder balls are formed on solder pads. After cooling, the balls are fixed on
the pads. Solder balls through reflow become the I/O outer pins of the BGA package,
connecting the chip to the external circuit. Figure 56.15 shows the diagram of ball
mounting process.

Cut & Sort

The process before cutting and sorting is carried out in units of strips. This station
divides the entire BGA substrate product into individual BGA chips by cutting or
stamping to form the final product.
The main flow of the bonded BGA assembling process is listed above. QA
inspection and shipment inspection processes exist after each main process. Each

Fig. 56.14 Package (a) before and (b) after marking

Fig. 56.15 Diagram of ball mounting process

56 Key Technologies and Processes for Traditional Packaging 1087

of these processes has an impact on the electrical characteristics and reliability of the
bonded BGA assembly. Hence, specific flow and process may be required for a
particular BGA product design.

Technology and Processing of Metal Packaging

The metal packaging process refers to an electronic packaging technology that uses
metal cases as a package casing or a base, in which chip or substrate is mounted and
bonds them together, and the outer lead passes through the metal cases by means of
the metal-glass (or ceramic) assembly process, and leads to the function of the
internal components and the input of external power supply signals. The metal
cases is often made of steel, Cu, Al, Kovar alloy, etc., and the surface is electroplated
with a certain thickness of Ni or Ni-Au layer. The good sealing property of the
encapsulation can protect the chip from the influence of external environmental
factors. Metal packaging is mainly used in various ICs, microwave devices, and
other products, which can be used flexibly and conveniently with good
compatibility.
The typical forms of metal packaging are shown in Fig. 56.16.
The typical process flow of metal packaging is as follows:

Assembly

These components, PCB (printed circuit board)/ceramic substrates, chips, patch

components, etc., are assembled and solidified in the metal casing cavity by epoxy
bonding or alloy solder welding, so as to fix components, protect chips, and
convenient for subsequent bonding leads.

Fig. 56.16 Typical metal packaging forms

1088 D. Yu et al.

Wire Bonding

According to packaging design, different specifications of Au wire or (Si doped) Al

wire are used to bond and connect the chips, components with external pins in the
interior of the cavity, which can play an important role in electrical connection. The
conventional bonding processes include Au wire ball bonding process and (Si) Al
wire ultrasonic wedge bonding processes, and so on.

Sealing

The shell or base of metal casing is welded seamlessly to the cap or cap by parallel
seam welding, alloy solder sealing, energy storage welding, and other processes, in
order to isolate the internal (components) from the external environment and avoid
the influence of external water vapor or other gases. Sealing is usually carried out in
inert gas or vacuum environment to ensure that the atmosphere inside the chamber is
in a stable and controlled state.

Marking

The product type, batch number, serial number, and other information are marked on
the main surface of the metal casing to facilitate the identification and late tracing of
the device type, batch, etc. Common processes include ink printing, laser marking,
and so forth.

Leak Detection

According to different test conditions, the sealed shell is detected roughly and finely,
and the unqualified products are eliminated. The procedures require that the first
detailed leak detection, and then rough leak detection. The types of detailed leak
detection tests include tracer gas helium (He) fine leak detection, radioactive isotope
fine leak detection, and optical fine leak detection. At the same time, the types of
crude leak detection tests include fluorocarbon crude leak detection, dye impregna-
tion crude leak detection, weight gain crude leak detection, optical crude leak
detection, and so on.

Ceramic Packaging Process

Ceramic packaging process refers to a kind of semiconductor assembly technology

which uses CPS (Ceramic Packaging Shell) or ceramic substrate as the carrier to
do the die-attachment on the die pad area of substrate or cavity, hereafter
56 Key Technologies and Processes for Traditional Packaging 1089

to interconnect the die and shell or substrate by wire bonding or flip-chip (FC) and
then to use metal or ceramic plate, cap to seal the die in the cavity. Ceramic
packaging is a high reliability packaging technology developed for electronics
products adapt to long life requirement or harsh environment such as high temper-
ature, high humidity, high energy radiation, etc.
Ceramic packaging materials include alumina (Al2O3), aluminum nitride (AlN),
silicon carbide (SiC), etc. High-power density IC packages usually use ceramic
shells or substrates with high thermal conductivity. According to different sintering
temperature, they are divided into high-temperature cofired ceramic (HTCC) and
Low-Temperature cofired ceramic (LTCC) shells or substrate. Some LTCC sub-
strates have high coefficient of thermal expansion close to organic substrates, such
as FR4 and some have low coefficient of thermal expansion close to silicon chips.
Ceramic packaging mainly include Ceramic Dual In-line-pin package (CDIP),
Ceramic lead-free chip carrier package (CLCC), Ceramic Dual Flat No-lead package
(CDFN), Ceramic Quad Flat No-lead package (CQFN), Ceramic Quad Flat Package
(CQFP), Ceramic with “J” shaped leads in a Quad Flat package (CQFJ), Ceramic
Small Outline Package (CSOP), ceramic with “J” shaped small outline lead (CSOJ),
Ceramic pin grid array (CPGA) packaging, Staggered pin grid array (SPGA) pack-
age, Micropin grid array package (MPGA), Ceramic Land Grid Array package
(CLGA), Ceramic Ball Grid Array package(CBGA), Ceramic Column Grid Array
package (CCGA), Low-temperature glass fusion seal series ceramic package,
Ceramic package with light window structure, etc. Different ceramic packaging
types have different processes and they also vary according to different quality
requirements.
A typical process flow chart of ceramic packaging is illustrated in Fig. 56.17.
Many processes in ceramic packaging are the same with the ones of plastic

Fig. 56.17 Typical process flow chart of ceramic packaging

1090 D. Yu et al.

packaging, e.g., wafer back grinding and metallization, chip mount, wire bonding,
flip-chip bonding, reflow, under-fill, ball mounting or column plant, marking, trim/
form (if needed), etc. Leak detection and column plant are peculiar to the ceramic
packaging process.

Sealing

The sealing processes include parallel seam welding, glass, solder, and laser sealing,
etc. The sealing processes in ceramic and metal packaging are almost the same, but
stored energy welding of metal package is not suitable for ceramic package sealing
and glass sealing of ceramic package is also not suitable for metal package.

Leak Detection [7]

Refers to the process which applies a certain pressurized tracer gas (such as nitrogen,
and krypton-85), or tracer material (such as fluorocarbon compounds, dyes, etc.), on
the IC with cavity through the leakage hole with the specified pressure and time. And
after the specified time, the quantitative analysis of the released tracer gas can be
used to judge the sealing leakage rate and whether it is within the specification. As
for the integrated circuit with thin cover, an optical interferometer can be used to
observe the deformation of the cover caused by a certain air pressure applied on it to
determine whether the leakage rate is within specification.

Plant Column

The plant column process is almost same as PBGA or CBGA’s ball mount process.
Figure 56.18 shows the typical CCGA Planting column process. Solder paste
printing process and reflow welding process shall be adopted for the column
planting. During the process of the column welding, Tooling shall be used to ensure
that the column is perpendicular to the shell or the substrate surface, and the
coplanarity of the outer end face of the column shall be within 0.1 mm.

Fig. 56.18 Typical CCGA planting column process diagram

56 Key Technologies and Processes for Traditional Packaging 1091

References
1. T. Wang, Y. Wang, et al., Die Attaching Process and Equipment (Publishing House of Electronics
Industry, Beijing, 2008)
2. K. Bi, Microelectronics Technology (National Defence Industry Press, Beijing, 2008)
3. T. Minbo, Electronic Packaging Engineering (Tsinghua University Press, Beijing, 2003)
4. R. Tummala, E.J. Rymaszwski, A.G. Klopfenstein, Microelectronics Packaging Handbook, 2nd
edn. (Publishing House of Electronics Industry, Beijing, 2001)
5. P.S. Chauhan, A. Choubey, Z.W. Zhong, et al., Copper Wire Bonding [M] (Springer, New York,
2014)
6. Z. Mao, J. Pan, Z. Yuan, 1C Packaging Foundation And engineering Design Examples (Elec-
tronic industry press, Beijing, 2014)
7. The General Reserve Department of PLA, Test methods and procedures for microelectronics
devices: GJB548J3 – 2005 [S] (Military Standard Publishing and Distribution Department of the
General Reserve Department, Beijing, 2007)
Process and Key Technology of Typical
Advanced Packaging 57
Steve Xinfu Liang, Chihchung Liang, Hongyan Guo, Weidong Liu,
and Xusheng Bao

Contents
Bumping Process and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
Flip-Chip Process and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
Flip-Chip BGA Process and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
Wafer Grinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
Flip-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
Underfill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
Flip-Chip Chip-Scale Package (FC-CSP) Process and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
Package-on-Package (PoP) Process and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
Wafer-Level Chip-Scale-Package (WL-CSP) Process and Technology . . . . . . . . . . . . . . . . . . . . . . . 1107
Fan-Out Wafer-Level Package (FO-WLP) Process Flow and Technology . . . . . . . . . . . . . . . . . . . . 1109
Through-Si-Via (TSV) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
3D Package Process Flow and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
Chip-Stacked 3D Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116
Hybrid 3D Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
Panel-Level Embedded Assembly Process Flow and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
System-in-Package (SiP) Process Flow and Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128

Abstract
ICs such as CPU, GPU, AP, and RFIC used today in high-performance comput-
ing, network communication, and smart mobile consumer products are continu-
ously shrinking in size by following the Moore’s Law in advanced nodes to
achieve enhanced performance, low power consumption, and high density in

S. X. Liang · C. Liang (*) · X. Bao

JCET Group Co., Ltd., Wuxi, China
e-mail: jerry.liang@jcetglobal.com
H. Guo
Zhejiang Hexin Semiconductor Co., Ltd., Jiashan, China
W. Liu
Tianshui Huatian Technology Co., Ltd., Tianshui, China

© Publishing House of Electronics Industry 2024 1093

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_57
1094 S. X. Liang et al.

compact sizes. The requirement of high performance and high density pushes the
rapid development of advanced packaging technologies away from traditional
wire-bonding (WB) interconnect to flip-chip 2D array packaging, wafer-level
packaging, 2.5D/3D system integration, SiP, etc. The current chapter describes
the typical advanced packaging process flows and key technologies currently
used in the IC package development and manufacturing. The individual topics
focus on the important advanced packaging fundamentals including bumping
technologies, wafer-level packaging, flip chip, fan-out packaging, TSV/3D, SiP
system-in-packaging, etc., covering typical process flows, key technologies, and
critical materials.

Keywords
Bumping · Flip-chip · FC-BGA (Flip Chip Ball Grid Array) · PoP (Package on
Package) · Wafer-level chip scale package (WLCSP) · Fan-out wafer-level
packaging (FOWLP) · InFO (Integrated Fan Out) · TSV (Through Silicon Via)

Bumping Process and Technology

Bumps are conductive protrusions built on top surface of IC chips as connection

directly or indirectly with bonding pads of IC chip and also as interconnect of chip-
to-substrate or chip-to-chip. The substrate includes Cu lead-frame, organic lamina-
tion substrate, and Si interposer. The metallic and nonorganic or compound material
can be used as structural material of bumps. In the 1960s, C4 (Controlled Collapse
Chip Connection) bump from IBM was the first time that industry used the bumps
for electrical interconnection in packaging [1]. From then on, a few kinds of bumps
were developed, including gold (Au) bumps, solder bumps, and pillar bumps.
Figure 57.1 illustrated these bumps. (1) Au bumps are composite of UBM (under
bump metallization) and plated Au and are used extensively for the LCD drive IC
interconnect with the glass or flexible substrate and for RFID IC interconnect with
the antenna. (2) Solder bumps have the UBM and solder (Sn, SnPb, and SnAg).
Solder bumps have solder thickness in the range of 10 μm to 100 μm and UBM
thickness < 10 μm. (3) Pillar bumps use thick plated Cu as UBM, and thin solder cap

Fig. 57.1 SEM picture of typical bumps

57 Process and Key Technology of Typical Advanced Packaging 1095

for welding as same function as solder bumps. Pillar bumps can totally replace the
solder bumps. As we know, Cu shows good performance in electrical and thermal
conductive, so it makes the pillar bumps a better alternative for electrical intercon-
nect and thermal dissipation. The fine pitch of pillar bumps is another feature better
than the solder bumps [2].
The advantages of bumping process are that all the processes are based on wafer
level and all bumps in all chips of each wafer are built at the same time. Before
applying the solder for bumps with the printing method, UBM should be formed on
chip first. Electro-less plating, PVD (Physic Vapor Deposition) metal layer, and
plating, these three processes are used for UBM in wafer-level bumping. Figure 57.2
shows the wafer-level bumping process flow with plating UBM and printing solder

Fig. 57.2 Process flow for solder bump with plating UBM and printing solder ball process
1096 S. X. Liang et al.

bumps. (1) Ti or TiW is deposited as barrier and adhesive layers. The following PVD
Cu layer is used as seed layer for plating. The function of barrier layer is to block the
diffusion between the seed layer and Al pad, and keep good adhesion with these two
metals. Before metal deposition, the oxide on the Al pads must be removed with the
Ar plasma in order to achieve good adhesion and lower contact resistance. (2) Per-
form the lithography process to form the pattern. The photoresist (PR) is coated on
wafer with spin-coat method. Then UV light illuminates on PR via the pattern on
glass mask and excites some reaction in PR to change its solubility in developer.
Then, let the PR on the wafer dip in the developer to form the pattern. (3) The wafer
with the PVD metal layer and PR pattern layer is dipped in the plating solution for
electrical deposit of certain thickness of metal as the UBM. Plating current, time,
plating chemistry concentration, and flow are key factors for depositing UBM
meeting requirement of dimension and reliability. After plating, the PR and PVD
metal out of the UBM area are removed with the corresponding chemistry. (4) The
ball placement and reflow is performed to weld the solder on the UBM. One metal
foil with holes whose locations are same as the UBM on wafer, called flux stencil, is
used to print the flux on the UBM surface. Then (another stencil similar with flux
stencil) print the solder ball on the UBM. The flux is pasted and sticked to the solder
balls. After that, the wafers with the flux and solder balls go through the reflow oven.
During reflow, the flux removes the oxide on the solder ball and UBM under certain
temperature, and solder balls melt and weld with the UBM after heating over the
melting temperature of solder. When the wafer goes out of reflow oven, a clean step
is needed to remove the by-product away from the wafer surface. The solder bumps
are formed.
Another method for forming solder bumps is plating. After plating UBM and
solder on UBM, and removing PR and PVD metal, then reflow process is performed
to form solder sphere bumps. This is a way to build pillar bumps too. Combined with
RDL (Redistribution Layer) process, variable bump structures are available as
shown in Fig. 57.3.

Fig. 57.3 SEM picture of bump with RDL

57 Process and Key Technology of Typical Advanced Packaging 1097

Flip-Chip Process and Technology

Flip-chip process refers to depositing bumps directly on the I/O pads of the chip, or
bumps after RDL, including solder balls, lead-free solder balls, copper (Cu) pillars
and gold (Au) pillars, flipping the chip heating, and combining the molten solder
with the substrate or frame to fan out the I/O of the chip into the desired packaging
process. Figure 57.4 shows the flip-chip packages.
Flip-chip technology was first developed by IBM in the 1960s and mass-
produced in the late 1990s, mainly used in high-end products (e.g., CPU, GPU,
etc.). With the advent of copper (Cu) pillar technology, the rapid development of
consumer smart electronic products (e.g., mobile phones, wearable products, etc.),
and increasing demand for product performance, more and more products have
shifted from traditional wire-bonded packages to flip-chip packages. Compared to
the traditional wire bonding process, the flip-chip packaging process has the follow-
ing advantages: (1) high I/O density; (2) due to the bump structure, the interconnect
length is greatly shortened with reduced interconnect resistance and inductance;
thus, the electrical performance of the package is greatly improved; and (3) the heat
generated in the chip can be directly transferred to the package substrate through the
solder bumps. Flip-chip technology includes many different processes. At present,
the industry’s flip-chip bump technology mainly includes Au pillars, solder bumps,
and Cu pillars as shown in Fig. 57.5. The corresponding soldering processes are
mainly ultrasonic bonding, reflow, and thermo bonding. Due to the development of
technology and products, the main underfill processes are capillary underfill,

Fig. 57.4 The flip-chip

package profile

Fig. 57.5 Schematic diagram of the bumps

1098 S. X. Liang et al.

compound underfill, nonconductive epoxy (NCP), and nonconductive film (NCF)

underfill.
As the CMOS technology continues toward high density, e.g., 16 nm, 10 nm, and
7 nm nodes, the density and performance requirements of the chip I/O are getting
higher, and the requirements of flip-chip are also higher for packaging process and
reliability in high-density microbump technology, small-pitch flip-chip bonding
technology, and underfill technology. Each process has its own differences for
various applications. For example, the choice of PCB or substrate types, whether it
is organic, ceramic, or flexible, determines the choice of assembly materials (includ-
ing bump types, flux, underfill, etc.) and to a certain extent also determines the
choice of equipment. Therefore, in the future, flip-chip packaging technology needs
to be optimized with product applications, chip design, package design, packaging
materials, equipment, and processes to find the optimal combinations and solutions.
Today, the flip-chip technology is widely used in consumer electronics. In the future,
applications in the Internet-of-Things (IoT), automotive electronics, and big data
will be widespread. Flip-chip is considered as a necessary process to promote
manufacturing of low-cost and high-density portable electronic devices.

Flip-Chip BGA Process and Technology

Flip-Chip BGA (FC-BGA) refers to bonding the chips on the substrate by flip-chip
(FC) technology and form flip-chip BGA packages. At present, FC-BGA is based on
the design of C4 and then performs packaging design and RDL of process technol-
ogy with the structure and shape of FC-BGA shown in Fig. 57.6.
FC-BGA is to form metal bumps on the I/O pads of the chip, and then bond the
metal bumps onto the organic substrate. By this way, the chips are flipped on the
organic substrate to form the FC-BGA packages. According to different product
applications, metal bumps include metal balls after wire bonding, Au bumps, solder
bumps, Cu pillars, and so on. According to different applications, the bump pitch of
the chip outputs will be different. FC technology concerns different varieties of metal
bumps. At present, FC-BGA packaging with solder bumps is more popular, and its
process flow is shown in Fig. 57.7 with three critical processes – wafer grinding, flip-
chip, and underfilling.

Fig. 57.6 Structure and shape of FC-BGA

57 Process and Key Technology of Typical Advanced Packaging 1099

Fig. 57.7 Key process flow of FC-BGA package with solder bumps

Fig. 57.8 Grinding wafer with bumps and underfilling technique

Wafer Grinding

Wafer grinding with bumps is to grind wafer to the required thickness in accordance
with the requirements of product application and package structure as shown in
Fig. 57.8. In the process of flip-chip, the bumps have been made on the incoming
wafers with wafer surface not smooth. Due to hollow between bumps, the wafer will
vibrate during grinding, which may easily lead to wafer crack or even breaking
especially for ultrathin wafers. To solve this problem, underfilling technology is
adopted into most grinding processes, which may maintain the wafer’s front surface
flat, so as to ensure the stability during grinding. At present, the wafer can be grinded
to less than 200 μm using underfilling technology.

Flip-Chip

This is a kind of high-accuracy surface mount technology (SMT). Chip is flipped 180

with the front surface of the chip and solder bumps facing downward. Then the solder
bumps are bonded onto the substrate by using high-accuracy coordinate alignment
technology (Fig. 57.9). In flip-chip process, the common bonding methods
are high-temperature pressing bonding and high-temperature reflow soldering.
1100 S. X. Liang et al.

Fig. 57.9 Flip-chip bonding

Fig. 57.10 Common bonding methods of flip-chip

High-temperature pressing bonding is to use a hot plate on the top of the chip to
directly transmit heat to the solder balls, so that the solder balls and solder paste melt
and bond with substrate to form a solid flip bonding after solidification as shown in
Fig. 57.10a. High-temperature reflow soldering is to place the chip on the substrate,
and then place the substrate in the high-temperature reflow oven. The solder balls
and paste can be melted at same time in the high-temperature reflow oven and
forming solid bonding as in Fig. 57.10b. In the process of flip-chip operation, the
substrate may be warped due to various internal stresses and results in quality
problems (e.g., bonding shift, poor bonding, bridge short, etc.).

Underfill

Underfilling is to fill the gap among the chip, solder bumps, and the substrate with
the underfilling materials to avoid shear stress failures caused by different coefficient
of thermal expansion (CTE) of the three materials. Underfilling involves fluid
mechanics, chemistry, thermodynamics, and stress mechanics with key factors of
viscosity, temperature, flow length, and time. The common underfilling methods are
capillary permeating and anisotropic bonding. At present, capillary permeating
technique is more commonly used as shown in Fig. 57.11. According to different
57 Process and Key Technology of Typical Advanced Packaging 1101

Fig. 57.11 Underfilling with capillary permeating technique

Fig. 57.12 FC-CSP assembly structure

die size and filling space, capillary permeating is divided into permeating with single
needle from single side or dual needles from dual sides.

Flip-Chip Chip-Scale Package (FC-CSP) Process and Technology

FC-CSP is a kind of chip-scale-package (CSP). According to the definition of

J-STD-012 standard [3], CSP is a form of assembly which packaging size is less
than 1.2 times of the bare chip. It implements the electrical connection between the
chips and substrates by using bumps on dies facing down, and the chip and substrate
bonding areas are directly connected. Compared to the wire-bonding (WB) and tape-
automated-bonding (TAB) methods, the FC-CSP takes advantages of much smaller
gap between chip and substrate, less signal loss, higher I/O density, being more
suitable for large-scale ICs (LSI), very large-scale ICs (VLSI), and application-
specific ICs (ASIC). FC-CSP assembly structure is shown in Fig. 57.12.
As a kind of advanced packaging technology, FC-CSP has the following features:
(1) small packaging size: FC-CSP assembly area is less than one-tenth of the QFP
with 0.5 mm pitch, only one-third to one-tenth of BGA package [4]; especially using
the Cu pillar bumps can further reduce the bump pitch, thus reducing the packaging
area; (2) more I/O numbers: In the same size chip packaging, compared with
traditional wire bonding packages, FC-CSP can accommodate more pin number;
(3) excellent electrical performance: Because the interconnecting wire between chips
and packages is shorter, smaller parasitic parameters, less interference, and shorter
signal transmission delay time, FC-CSP have a smaller resistance and faster signal
1102 S. X. Liang et al.

Fig. 57.13 FC-CSP assembly process flow

Fig. 57.14 FC-CSP chip

crack during cutting

transmission speed; and (4) realize a one-piece assembly: multichips of different

functions and surface mount devices (SMD) can be packaged in a single FC-CSP
assembly with process flow shown in Fig. 57.13.
The key technologies for FC-CSP are the following: (1) FC-CSP has high
requirements for the package thickness; therefore, the final thickness shall be strictly
controlled (at target value15 μm) during wafer back grinding. In addition, the
process parameters shall be adjusted to avoid product die break and crack during
cutting as illustrated in Fig. 57.14; (2) connecting the chip bumps and the circuits of
the substrate by reflow, it is necessary to prevent the circuits from open and short as
substrate pitch is too narrow during reflow process. The thermal shrinkage ratio
between chip and substrate is different, which may cause inconsistent warpage
57 Process and Key Technology of Typical Advanced Packaging 1103

during reflow. Fracture happens at the joint between bumps and substrates due to
certain stresses especially for relatively large area between chips and substrates;
(3) the reflow cooling rate must be strictly controlled to avoid the chip low-k material
and the joint between bumps and substrates breakage. Generally, the cooling rate
shall be controlled within 4
C/s below 150
C as shown in Fig. 57.15. (4) When the
gap between bumps and traces of substrate is too narrow, the alignment accuracy of
flip-chip attachment must be strictly controlled to avoid short circuit of bumps and
traces; and (5) after flip-chip attachment, the product must be molded and cured to
protect the internal chips. At the same time, it also has the effect of blocking outside
interferences. The solidification time and temperature in mold process must be
strictly controlled to avoid the delamination between epoxy molding compound
(EMC) and dies and to decrease package warpage.
Combined with technology and current development of IC manufacturing, main
structure types of FC-CSP are single die FC-CSP (Fig. 57.12), multichip side-by-
side FC CSP (Fig. 57.16), and stacked-die hybrid FC-CSP (Fig. 57.17). Laminated
packaging means multiple dies stacking up on a die cavity or substrate to realize the
connection between chips or packages. Laminated packages are mainly used in
mobile processors in order to reduce the power consumption, and reduce size,
improving the level of integration and performance of encapsulation. With rapid
development of FC-CSP and increasingly widespread use, the main applications are
as follows: (1) consumer electronics: mobile phones, camcorders, digital electronic

Fig. 57.15 FC-CSP reflow profile

Fig. 57.16 Structure of

multidie side-by-side FC-CSP

Fig. 57.17 Structure of

multidie stacked FC-CSP
1104 S. X. Liang et al.

products, DVD, wireless products, etc. (2) computers: voltage regulator, high-speed
storage, smart card, peripherals, etc.; (3) communication: digital pagers, mobile
phones, GPS, etc.; and (4) others: the FC-CSP have wide range of applications in
network communication, digital signal processing (DSP), mixed signal and RF
signal, application-specific IC, microcontroller, and other fields due to the high
number of pins, miniaturization, thinner, light-weight, and multifunction features
of FC-CSP.

Package-on-Package (PoP) Process and Technology

Package-on-package (PoP) is a new package which is the stacked packages of large-

capacity memory packages on a logic package with high integration at the bottom
[5]. This new high-density package is mainly used in a variety of consumer elec-
tronics such as smartphones, digital cameras, and portable wearable devices. The
model of PoP is illustrated in Fig. 57.18. The structure of PoP is illustrated in
Fig. 57.19.
PoP is mainly a system-integrated 3D package developed for mobile devices with
the following features: (1) Memory and logic devices can be freely combined, tested,
and replaced separately to ensure the yield; (2) the PoP stacks in the vertical direction
for saving the board area and improving the package density of the system; and

Fig. 57.18 The model

of PoP

Fig. 57.19 Structure of PoP

57 Process and Key Technology of Typical Advanced Packaging 1105

(3) vertical interconnection of stacked devices replaces traditional 2D packaging

interconnection, which can achieve faster data transmission between logic devices
and memory devices.
With the development of technology, there are several types of PoP structures.
(1) Tin (Sn) ball connecting PoP: Logic chips have more I/O pins, so it is often
packaged by flip chip (FC) technology and also used as the bottom component. The
bottom die uses capillary-underfill (CUF); its structure is shown in Fig. 57.20.
(2) MLP connecting PoP: In order to develop the thinner PoP structure, molding
laser package (MLP) technology emerged and is also called through-mold-via
(TMV) technology on the market. First, the solder ball will be mounted around the
side of chip before molding. Then solder bump will be exposed after laser drill
process which connects with upper devices. The structure is shown in Fig. 57.21;
and (3) fold-style PoP and BVA-type PoP: To meet the thinner size, stronger
function, more I/O pins, etc., fold substrate is applied and all kinds of packages
connect with it which forms fold-style PoP [6]. Moreover, bond via array (BVA)
technology [7] is also used. Structures are shown in Figs. 57.22 and 57.23.
All in all, there are solder balls, fold substrate, and BVA technology as the main
connection method between top and bottom packages. MLP-PoP process flow is
shown in Fig. 57.24. The key technologies in PoP are described as follows: (1) PoP
is a highly integrated 3D packaging technology with higher requirements for

Fig. 57.20 Structure of tin

ball connection PoP

Fig. 57.21 MLP type PoP

structure diagram

Fig. 57.22 Fold-style PoP

structure diagram
1106 S. X. Liang et al.

Fig. 57.23 BVA-type PoP

structure diagram

Fig. 57.24 MLP PoP process flow

packaging and wafer thickness (less than 100 μm). Therefore, higher requirements
are put forward for wafer back grinding (BG) process for better control to avoid
wafer crack and die chipping. Moreover, it is more easy to cause die peeling from
blue film when sawing the wafer of thickness less than 100 μm; (2) because of the
high integration of PoP packaging and the smaller distance between signal ports (less
than 0.3 mm), the higher requirements are put forward for solder ball mount process
with higher accuracy solder ball mount machine and control of the accuracy of the
ball alignment is tightened; (3) PoP packaging has a higher requirement for the
thickness of assembly products for within narrow tolerance. Therefore, in order to
avoid defects of incomplete molding, voids, and delamination between the layer of
epoxy molding compound (EMC) with dies and substrate, the best assembly mate-
rials are chosen by design of experiments (DOE) analysis as well as the parameters
of molding and postcuring processes; (4) as molding laser package of PoP
(MLP-PoP) is widely used at present, laser drilling process after molding is partic-
ularly important. Therefore, it is necessary to control the parameters of the energy,
pulse width, repetition frequency, and alignment of laser pulses, so as to control the
size, shape, and position of drilling holes to achieve better overlapping of the upper
57 Process and Key Technology of Typical Advanced Packaging 1107

Fig. 57.25 MLP PoP process

flow and laser-drilling cross-
sectional photo

and lower packages assembled as shown in Fig. 57.25; and (5) PoP, as the stacked of
two highly integrated packages, has a higher requirement for the warpage of the
upper and lower packages, e.g., having the same warpage direction as possible to
achieve the consistency of stacking. For the case of excessive warpage of the
packaging, the amount of solder ball needs to be better controlled during stacking.
When evaluating new products, warpage data of upper and lower packaging need to
be specially evaluated and analyzed.

Wafer-Level Chip-Scale-Package (WL-CSP) Process

and Technology

Wafer-level chip-scale-package (WL-CSP or WLCSP) refers to a technology of

packaging an IC with redistribution layer (RDL) formed, under bump metallization
(UBM), solder ball mounting, and functional probing test in wafer level and then
dicing the wafer into individual units. The resulted packages have same size as the
chips and the solder balls to form the mechanical and electrical interconnection with
the printed circuit board (PCB). WLCSP evolved from flip chip technology. IBM
developed the C4 (Controlled-Collapse-Chip-Connect) technology in the 1960s, and
in the 1990s some companies with bumping capability developed the WLCSP
technology. The main advantage of WL-CSP is the small form factor which makes
it a wide application in portable devices (e.g., PMIC (Power Management Integrated
Circuit), IPD (Integrated Passive Devices), EEPROM (Electrically Erasable Pro-
grammable Read-Only Memory), and RF front end). The solder ball pitch of
WL-CSP is typically at 0.4 mm and 0.5 mm as compatible with the traditional
PCB assembly process. It is easier to have solder ball thermal fatigue failures in a
bigger chip size WL-CSP because of the CTE mismatch between Si chip and the
PCB, so normally the package size of WLCSP is less than 6 mm  6 mm.
As shown in Figs. 57.26 and 57.27, there are BoP (Bump-on-Pad) and RDL
technologies in WL-CSP packages allowing placement of solder balls directly above
the I/O Al pads as well as elsewhere in the die. As shown in Fig. 57.28, there is a
kind of WL-CSP with commercial name as Super CSP by using thick Cu metal post
as UBM and the Cu posts encapsulated by resin material [8]. Polymer repassivation
1108 S. X. Liang et al.

Fig. 57.26 BOP-WLCSP

cross section

Fig. 57.27 RDL-WLCSP

cross section

Fig. 57.28 Structure of super CSP [8]

layer is widely used in both BoP-WLCSP and RDL-WLCSP as a stress buffer layer
or dielectric layer. The most popular polymer materials used in the industry are PI
(polyimide), PBO (polybenzoxazole), and BCB (benzocyclobutene). Regarding the
RDL layer, the most common metal materials are Al and Cu. The Al RDL is around
1–4 μm thick; and the Cu RDL with the additive plating process can be more than
10 μm thick to improve the current handling capability. UBM is the interlayer
between solder bump and the die final I/O pads to form good mechanical and
57 Process and Key Technology of Typical Advanced Packaging 1109

Fig. 57.29 Typical process flow for RDL-WLCSP bumping

electrical interconnection. UBM is a metal layer stack including diffusion barrier

layer and wettable metal surface. Sputter and sputter plus electro-plating process are
used to fabricate UBM layer and the typical material combination including Ti(SP)/
Cu(SP)/Cu(PL), TiW(SP)/Cu(SP)/Cu(PL), Ti(SP)/ Cu(SP)/Ni(PL), Ti(SP)/NiV(SP),
and Cr(SP)/NiV(SP). (Note: SP and PL mean sputtering and electro-plating, respec-
tively.) The electro-less plating Ni immersion Au (ENIG) can also be an option to
fabricate UBM. The typical process flow of RDL-WLCSP front-end bumping is
illustrated in Fig. 57.29. After bumping, the wafers then go to backend process
including wafer probing test, laser marking, dicing, and tape and reel process as
shown in Fig. 57.30.

Fan-Out Wafer-Level Package (FO-WLP) Process Flow

and Technology

Fan-out wafer-level package (FoWLP or FOWLP) is a type of WLP. Comparing

with traditional packaging, WLP does not need carrier like lead-frame or substrate.
Thus, it can achieve thinner and smaller packages. FO-WLP can support multidie,
2.5D/3D, and system-in-package (SiP). FO-WLP can completely remove any extra
bonding steps between dies and packages (i.e., no need of wire-bond or bumping), so
it can achieve the smallest scale in the z-direction. It can also achieve higher
reliability by removing critical potential point of failures, e.g., bump crack, bond
lift, and wire shift. Further, due to its shorter length of signal traveling, the electric
1110 S. X. Liang et al.

Fig. 57.30 WLCSP back-

end process flow chart

performance is better than other package as well. WLP can adopt a thinner line and
space width to achieve higher-density routing inside package. It can provide higher
bandwidth at a smaller scale to better serve the packaging need of advance ICs.
Embedded wafer-level ball grid array [9] (eWLB) is a FO-WLP technology with
highest accumulated volume production. Its production process flow is illustrated in
Fig. 57.31 (where the process steps in black boxes are key steps). Another FO-WLP
technology different from eWLB is integrated FO-WLP (InFO) [10]. The main
difference between InFO and eWLB is how die is placed on the temporary carrier.
InFO puts die facing up, plating a bump on pads. Put another PI layer for insulation
and protection, and polishing to expose the copper bump for metal layer connection.
This extra step and polishing can result in better coplanarity before metal layer
formation, thus lead a better yield. The process flow for InFO is shown in Fig. 57.32
(where the process steps in black box are key steps).
The key steps of FO-WLP production process are die placement, molding, and
metal layer. (1) Die placement has a very high requirement on both accuracy and
speed. Speed means productivity of die placement, which is highly associated with
cost, while placement accuracy is a key factor of metal layer yield as shown in
Fig. 57.33. When the size of temporary carrier or glass wafer continue to increase for
further production efficiency improvement and cost reduction, a good and uniform
accuracy from center to edge presents a very difficult challenge to the placement
equipment manufacturers. (2) Molding compound will be inserted and heated along
with packages during molding process. This will create die shifting (movement) and
warpage (due to the CTE difference between materials in the package and com-
pound). Die shift can cause metal layer mismatch (Fig. 57.33), while warpage can
57 Process and Key Technology of Typical Advanced Packaging 1111

Fig. 57.31 eWLB process flow

cause loss of focus during metal layer lithography as yield loss. Although increase
molding thickness can reduce warpage, but it defeats the purpose of using FO-WLP
for achieving thinner package. (3) Another key step is metal layer formation. Metal
layer formation mostly uses stepper, which is the most expensive equipment among
all other equipment in FO-WLP as a major cost factor. Yield of metal layer is the key
factor of the package yield. As mentioned above, the die placement accuracy and
warpage at molding is also a challenge to the yield of metal layer formation.

Through-Si-Via (TSV) Technology

Through-silicon-via (TSV) is one of the most advanced packaging technologies. The

key processes of TSV technology include TSV fabrication, RDL/micro bumps
manufacturing, wafer thinning, via reveal, wafer bonding, thin wafer handling
[11], etc. (1) TSV fabrication: There are two types of TSV structures as shown in
Fig. 57.34. Type I is a blind via, which does not require direct conductive connection
with the bottom side. Type II has direct conductive connection at the bottom. The
main processes of TSV fabrication include via etching, insulation layer deposition,
seed layer deposition, and conductive material filling. For TSV of type II, it is
necessary to selectively remove the insulating layer at the bottom of via after the
insulation layer deposition to open the pad or metal layer for electrical interconnects.
(2) RDL/microbumps: The redistribution layer provides the electrical routing of
TSVs and existing circuits or devices on the substrate, which can provide greater
degree of interconnect freedom. Microbumps are mainly used to realize the direct
electrical interconnects between TSV chip/interposer and other chips or packaging
1112 S. X. Liang et al.

Fig. 57.32 InFO process flow

substrates. For RDL with linewidth less than 1 μm, damascene process is needed,
and for linewidth larger than 1 μm, the process of electroplating through thick
photoresist can be used. (3) Wafer thinning: Wafer thinning can be divided into
two types according to the process schemes: wafer with TSVs and wafer without
TSVs. For wafer without TSVs, wafer thinning is relatively easier as long as the
57 Process and Key Technology of Typical Advanced Packaging 1113

Fig. 57.33 Relationship between die and metal layer

Fig. 57.34 Typical TSV fabrication process

smoothness of surface can be guaranteed. In the case of wafer with TSVs, it is

necessary to expose TSVs from the back of the wafer after thinning. Therefore, the
simultaneous grinding or polishing of Si wafer and TSVs filling material (such as
Cu) should be considered, and the contact or contamination of the filling material
with Si wafer should be prevented. (4) Wafer bonding and handling: After wafer
thinning is completed, there are usually some follow-up or temporary processes.
Therefore, it is necessary to ensure the safety of the wafers in these processing steps,
which is usually achieved by bonding with the carrier wafers. If the carrier wafer is
functional, it will be a permanent wafer bonding. Depending on the interlayer
material used, permanent bonding can be divided into SiO2 bonding, polymer
bonding, metal bonding, and the hybrid bonding technologies. When the carrier
wafer is nonfunctional, it is a temporary bonding, and the de-bonding is applied in
subsequent processes. (5) The basic process for thin wafer handling: The wafers
for thinning are first bonded to carrier wafers, then the wafers are thinned and
processed, and finally the carrier wafers are removed to complete the processing.
1114 S. X. Liang et al.

According to the process sequence of TSV and interconnects within active

devices in the integration scheme, TSV process can be divided into three
schemes, i.e., Via-first, Via-middle, and Via-last. Via-first means to build the
TSVs before active chip and its interconnect manufacturing; Via-middle refers to
making active devices first, then TSV, and interconnects manufacturing; Via-last
refers to the completion of active chip and interconnects first, and TSV
manufacturing at last. Via-middle and Via-last processes are currently widely
used for TSV integration.
At present, TSV has three main application fields, which are 3D IC packaging,
3D wafer-level chip size packaging (3D-WLCSP), and 2.5D interposer packag-
ing. (1) 3D IC packaging: At present, the main application of 3D IC is
for memories. The reason is that the pin density of memories is low, the layout
is regular, and the chip power density is low. 3D integration through TSV can
increase storage capacity, reduce power consumption, increase bandwidth,
reduce latency, and achieve miniaturization. (2) 3D WL-CSP: It is mainly
used in image, fingerprint, filter, accelerometer, and other sensor-packaging
fields. It is characterized by Via-last process, low TSV depth-width ratio
(1:1–3:1), and large via size. Considering the cost, most image sensor packages
adopt TSV structure with small aspect ratio. The packaging process is shown in
Fig. 57.35. (3) 2.5D interposer packaging: Interposer with fine pitch RDL
routing is aimed at high-performance applications such as FPGA and CPU. It is
characterized by multilayer fine pitch rerouting layers and fine pitch microbumps
on the front side. The depth-width ratio of the mainstream TSV reaches 10:1, and
its thickness is about 100 μm. Due to the technical difficulties and cost con-
straints, as well as the increase of packaging thickness, the 2.5D interposers are
currently in small volume production. Figure 57.36 shows the process flow of
TSV interposer.

Fig. 57.35 Packaging process of TSV image sensor with low aspect ratio
57 Process and Key Technology of Typical Advanced Packaging 1115

Fig. 57.36 Process flow of TSV interposer

Fig. 57.37 Conventional 2D packages (a) and 3D packages (b)

3D Package Process Flow and Technology

Advanced 3D microelectronic packaging technology is the industry trend to meet

portable electronics demand of ultrathin, ultralight, and high performance with low
power [12]. It is mainly used for high-speed computing, network, and GPU system
chips. The footprint difference between conventional 2D packages and 3D packages
is shown in Fig. 57.37. Chip-level 3D packaging can realize multifunction of
products by improving package density and signal transmission speed, reducing
package size, power consumption, and noise. As the package density increases and
the volume decreases, the calorific value of 3D package increases greatly. How to
solve the heat dissipation problem is the key to the packaging technology.
1116 S. X. Liang et al.

Three-dimensional packages are mainly divided into chip-stacked three-dimensional

packages and hybrid three-dimensional packages.

Chip-Stacked 3D Packages

The hybrid memory cube and TSV interconnect technology are used to stack the
chips vertically. As shown in Fig. 57.38, the memory chips are interconnected with
the logic chip through TSV interposer and microsalient points, the logic chip is
connected with the packaging substrate through TSV interposer and microsolder
joints, and the packaging substrate is connected with the PCB through reverse
soldering. As a key part of interconnection, TSV interconnect layer can improve
interconnection density and increase bandwidth. Its structure is illustrated in
Fig. 57.39. TSV production process includes hole formation, linear Cu filling,
rewiring, and convex point production.
The 3D stacks can be assembled using three different approaches as shown in
Figs. 57.40, 57.41, and 57.42. They are commonly referred to as wafer-to-wafer

Fig. 57.38 Chip-stacked 3D

packages structure

Fig. 57.39 Typical TSV

structure
57 Process and Key Technology of Typical Advanced Packaging 1117

Fig. 57.40 Illustration of the key steps in a W2W attach process

Fig. 57.41 Schematic flow

of D2W attach process

(W2W) attach, die-to-wafer (D2W) attach, or die-to-die (D2D) attach [12]. In W2W
process, entire wafers are aligned and then bonded, followed by the singulation of
individual die stacks. According to the welding face-to-face relationship, it can be
divided into two kinds of back-to-face welding and face-to-face welding. A signif-
icant advantage of a W2W process is that both bonding surfaces are very flat; thus,
there can be excellent wafer-to-wafer alignment, and hence very fine interconnect
pitches can be achieved. Key limitations of the W2W process include the following:
1118 S. X. Liang et al.

Fig. 57.42 Schematic flow

of D2D attach process

Fig. 57.43 The 2.5D packages structure

(1) All the die have to be of the same size; (2) the process precludes the ability to
bond known good die together; and (3) yield loss due to misalignment during this
process can be significantly expensive, especially in the case where multiple wafers
are stacked.
As shown in Fig. 57.43 2.5D package structure refers to multiple chips placed
side by side in the same packaging body, and the chips form a high-density
interconnection system through a high-density intermediary layer. Multichips,
micro bumps, and dielectric layer are the main components of 2.5D package. Typical
Si dielectric layer technologies include TSI (through-silicon-interposer), LCSI
(low-cost silicon interposer), POI (photo-defined organic interposer), LCGI
(low-cost glass interposer), and WLP (wafer-level package). Figure 57.44 shows
the 2.5D packaging process flow, where “HBM” denotes high bandwidth memory,
“KGD” the known qualified chip (known good die), and “BEOL” the back-end-of-
line.

Hybrid 3D Packages

Hybrid 3D package structure means a composite package structure containing a

variety of 3D package technologies. Figure 57.45 shows the 2.5D interconnec-
tion structure of TSV and Si interconnect layer. The interconnection between
memory chips and control chips, CPU, and 3D packages is conducted through
57 Process and Key Technology of Typical Advanced Packaging 1119

Fig. 57.44 The 2.5D packages process flow

Fig. 57.45 2.5D packages

with TSV and Si interposer

Fig. 57.46 EMIB

interconnect structure

TSV interconnect layer, forming a hybrid 2.5D-type 3D packaging structure.

Figure 57.46 shows the EMIB (embedded multidie interconnect bridge) inter-
connection structure, which is another 3D interconnection connection technology
different from TSV, and it can further reduce the cost of 3D packaging.
1120 S. X. Liang et al.

Panel-Level Embedded Assembly Process Flow and Technology

Panel-level (PL) embedded assembly is an integrated packaging technology com-

bined with chip packaging with SMT process based on substrate manufacturing
process. It can be single-die, multidie, module, or multidie stacking packaging.
Different from traditional packaging with dies or passive components placed on
top of substrate, PL embedded assembly embeds chips or passive components in the
inner layer of substrate, and hence it has shorter interconnecting path, more compact
body, superior thermal and electrical performance, and much higher integration
density. The concept of PL embedded assembly or packaging can be traced back
to the high-density PCB structure with chip embedded by GE in 1969 as shown in
Fig. 57.47. Although this concept was proposed, it failed to successfully realize due
to limitations of manufacturing process and material performance at that time.
With the improvement of substrate manufacturing process and enhanced material
performance, electronics products have been continuously advancing toward high
performance, multifunction, and miniaturization. This trend not only drives the chip
scaling, but also drives the chip-packaging technology toward new 3D stacking and
module packaging with breakthrough in packaging structures continuously. This
also drives material suppliers and research institutes for making efforts on new
embedded packaging structures and processes. In terms of various types of embed-
ded device, the PL embedded assembly technology can be classified as chip embed-
ded, passive component embedded, packages embedded and mixed embedded
packaging.

Fig. 57.47 High-density PCB with embedded chip

57 Process and Key Technology of Typical Advanced Packaging 1121

Currently, PL embedded assembly is a mainstream, e.g., bumpless build up layer

(BBUL) of Intel, chip-in-polymer (CiP) of Fraunhofer IZM, integrated module board
(IMB) of Imbera, embedded component technology (ECT) of AT&S, embedded
active device (EAD) of Oki, and so on. Although they have different names, the key
concerns of those technologies are described in the following aspects: (1) How to
effectively and reliably place dies or devices inside the substrate to make sure of
electrical interconnections between dies or devices and substrate, and especially
when to embed dies, as they are critical for yield and cost; (2) how to solve the
thermal stress mismatch among different CTE materials (i.e., chip, substrate, and Cu
trace) induced by thermal dissipation during the working state via structure design
and how to avoid structural and performance failures of chip cracks, Cu trace breaks,
lamination, etc. due to unbalanced thermal stresses and strains.
For the PL embedded assembly (Fig. 57.48), compared to the traditional wire
bonding (WB) packaging (Fig. 57.49) and flip-chip packaging (Fig. 57.50), the
largest difference is that dies or devices are embedded in the inner layer of substrate
other than placed on the top of substrate. So it has the following specific advantages
and performance. (1) The interconnection between chips and substrate may realize
either via Cu traces plating or via PL bonding process or flip-chip process in the
course of substrate manufacturing process. This packaging method finished in the
process of substrate manufacturing largely simplifies the process passing from
separate substrate process to packaging process. (2) This kind of direct interconnec-
tion between chips and substrate via Cu traces plating shortens the conductive path
and effectively reduces the parasitism. Hence, it brings us better RF performance of

Fig. 57.48 Panel-level

embedded assembly

Fig. 57.49 Wire bond

package

Fig. 57.50 Flip chip package

1122 S. X. Liang et al.

high-frequency signal, superior signal quality of audio signal, and faster speed of
data transmission. (3) Due to effectively embedding dies or components in inner
layer of substrate, the space of substrate surface is released, and therefore it provides
more space for 3D stacking and makes it easier to realize SiP packaging as illustrated
in Fig. 57.51. Also, as illustrated in Fig. 57.52, it is an embedded 3D stacking
package with space left for inductors on substrate. The stacking of PL passive
components is illustrated in Fig. 57.53. The product in panel form after overmolding
is illustrated in Fig. 57.54.
Based on the featured structural and performance advantages of PL embedded
package, currently, the main application focuses on analogic RF and power field
such as RF-IPD, DC/DC convertor, RFID, MOSFET, miniaturized IC driver, multi-
chip SiP module, etc.

Fig. 57.51 A cross section of

embedded packaging (mixed
embedding)

Fig. 57.52 A 3D stacking

package

Fig. 57.53 A panel-level 3D

component stacking

Fig. 57.54 The product in

panel form after overmolding
57 Process and Key Technology of Typical Advanced Packaging 1123

Fig. 57.55 PL embedded

assembly process flow (face
down+single-side Cu plating)

According to the combinations of whether the chip is face up or face down when
embedding, whether drilling first then plating Cu traces or plating Cu traces first then
grinding for the interconnect of device and substrate, and whether single-side plating
with carrier or double-side plating without carrier, etc., there are various kinds of
process flows for the PL embedded assembly technology. But the major steps of
various process flows are similar as illustrated in Figs. 57.55, 57.56, 57.57 and
57.58. Here we use the process flow with chip face down, single-side Cu plating first
with carrier and grinding after plating as an example; the main process flow is as
follows:

Lithography ! trace plating ! lithography ! Cu post plating

! die or component attach ! dielectric material lamination
! grinding to expose Cu post ! lithography ! second trace plating
! second dielectric material layer lamination ! grinding to expose outer lead
! carrier remove and surface finish
1124 S. X. Liang et al.

Fig. 57.56 PL embedded

assembly process flow (face
down+via drilling +double-
side Cu plating)

System-in-Package (SiP) Process Flow and Technology

System-in-package (SiP or SIP) contains mixed interconnections of single or mul-

tiple dies and a number of passives, discrete components to achieve an IC with
specific system functionality in a single package or module through system codesign
and comprehensive packaging technologies as illustrated in Fig. 57.59. Compared to
the System-on-chip (SOC) integration that usually focuses on digital and logic
circuits integrated on a single Si chip, SiP integration includes more analogy
applications (e.g., microwave, RF, power, etc.), which are almost impossible or
very hard to integrate on a single chip [13].
As an effective technology and methodology to design, develop, and manufacture
ICs and system functionality through packaging technology, there is no single or
fixed package outline or format for system-in-package (SiP); instead, most package
types can be used as the platform to achieve SiP package integration. To meet a wide
variety of functions and applications, many SiP products select the flexible LGA I/O
layout. However, SiP is rapidly adopted in applications with more complexity and
larger size; BGA with high pin count I/O layout and complete module has also
become popular [14]. SiP often requires EMI shielding to prevent the electro-
magnetic interference between the circuits and the environment by using conven-
tional metal lids, or compound molding with metal layer for EMI shielding in
57 Process and Key Technology of Typical Advanced Packaging 1125

Fig. 57.57 PL embedded

assembly process flow (face
up+single-side copper
plating)

advanced SiP. The types of SiP substrate or integration carriers include the follow-
ing: thin-film, thick film, and low-temperature cofired ceramic (LTCC) substrates;
high-density lead-frame; single-layer, multilayer, and embedded laminate substrates;
and fan-out wafer-level redistribution-layer (WL-RDL); etc. SiP packaging con-
structions and interconnections include the following: SMT þ WB/FC multidies;
SMT þ WB/FC stacking dies; high-density 3D/2.5D packaging; package-on-pack-
age (POP); fan-out wafer-level packaging (FO-WLP); etc.
A typical SiP assembly process flow is illustrated in Fig. 57.60. The SiP technol-
ogy integrates a number of different types of IC dies, discrete and passive compo-
nents, and new and nonstandard packaging processes, e.g., SMT and metal
sputtering for EMI shield. Many standard packaging processes and assembly equip-
ment can be used for the manufacturing of SiP-products; however, the SiP packaging
may need new requirements and specifications. (1) High-Density SMT Process:SiP
technology has been the major driving force for size reduction and miniaturization of
SMT components and prepackaged IC such as WLCSP and micro-CSP, SMT
inductors, and capacitors with ultrasmall body size (e.g., 0201, 01005, and
008004); all started their high-volume application first in the SiP packaging; and
1126 S. X. Liang et al.

Fig. 57.58 PL embedded

assembly process flow (face
up+via drilling + double-side
copper plating)

Fig. 57.59 System-in-package RF module

advanced WL-CSP is already using I/O pitch less than 200 μm, similar to that of flip-
chip bumps. High-speed and high-precision SMT equipment and processing must be
utilized to place and mount these ultrasmall components and fine pitch devices onto
the substrates, using solder paste and reflow process to form reliable connections.
Solder paste usually mixes solder alloy powders uniformly with flux paste; the
selections of solder alloy compositions, powder size and particle size distribution,
and flux types and properties are all important, depending on the specific component
and device types, package constructions, and assembly process. (2) Compound
Molding: SiP packaging requires very small spacing gap between ultrasmall
57 Process and Key Technology of Typical Advanced Packaging 1127

Fig. 57.60 A typical SiP assembly process flow with EMI metal shielding

Fig. 57.61 EMI metal shielding layer

components and fine pitch devices, making it very hard to completely fill these
spacing gaps with molding compound, causing potential reliability failures. Com-
mon solutions include the following: optimization of molding process parameters;
improvement of molding compound fluid and fill performance through specific
design modifications; optimization of molding compound particle size and distribu-
tion; and use of advanced compression molding process to achieve completely
uniform fill. (3) EMI Metal Shielding: As shown in Fig. 57.61, the EMI metal
shielding layer on top surface of molding compound is usually formed through
plasma sputtering deposition or electro-plating process. The plasma sputtering
deposition process gradually becomes the primary choice as a result of its process
flexibility, strong layer adhesion, and ease of production expansion; in addition, it
requires no environmental water treatment as directly associated with electro-plating
process. EMI metal shielding generally consists of multiple metal layers in order to
achieve sufficient adhesion between the metal layer and molding compound. Cu is
the primary EMI metal shielding layer as a result of its superior electrical conduc-
tivity, whereas stainless steel is used for the outer surface layer due to better
anticorrosion and antiwearing resistances. To establish complete EMI shielding,
1128 S. X. Liang et al.

the metal layers must uniformly and consistently cover the entire top surface and the
four sidewalls, and all connected to electrical ground. In certain highly complex SiP
products, the specific functionality requires compartment EMI shielding, further
increasing the EMI isolation between individual functional ICs and blocks inside
the SiP package.

References
1. E.M. Davis, W.E. Harding, R.S. Schwartz, et al., Solid logic technology: Versatile, high-
performance microelectronic. IBM J. Res. Dev. 8(2), 102–114 (1964)
2. A. Long, J. Xin, C.M. Lai, J. Chen, Y. Gao, et al., Pillar bump technology and integrated
embedded passive devices, in 7th International Conference on Electronic Packaging Technol-
ogy, (2006), pp. 1–5
3. J-STD-012, Implementation of Flip Chip and Chip Scale Technology (IPC, 1996)
4. Wang Z, Cheng L, Gao P, et al. CSP technology and its development foreground. Semicon-
ductor Technol., 2003, 28(12): 39–43
5. M. Dreiza, A. Yoshida, J. Micksch, et al., Guidelines for the design of PoP (package-on-
package). China Integrated Circuits 12, 61–65 (2005)., 60
6. Y.G. Kim, Folded stacked package development[C], in Electronic Components & Technology
Conference, (2002), pp. 1341–1346
7. Invensas Technologies. https://www.invensas.com/technologies/bva/
8. K. Hiraiwa, M. Minamizawa, FUJITSU. Sci. Tech. J. 36(1), 99–107 (2000)
9. T. Meyer, G. Ofner, S. Bradl, et al., Embedded wafer level ball grid array (eWLB), in
Electronics Packaging Technology Conference, (2008), pp. 994–998
10. C. Liu, S.-M. Chen, F.W. Kuo, et al., High-Performance Integrated Fan-out Wafer Level
Packaging (InFO-WLP): Technology and System Integration: 2012 IEDM (San Francisco),
pp. 1–4
11. P. Garrou, C. Bower, P. Ramm, Handbook of 3D integration: Technology and applications of 3D
integrated circuits. Dig. Dis. 28(1), 116–125 (1971)
12. S.F. Al-Sarawi, D. Abbott, F.D. Franzon, A review of 3-D packaging technology. IEEE Trans.
Compon. Packag. Manuf. Technol. 21(1), 2–14 (1998)
13. S.X. Liang, Development of high density microvia hybrid MCM-L packages, in 2000 HD
International Conference on High-Density Interconnect and Systems Packaging, Denver CO,
ETATS-UNIS (25/04/2000), vol. 4217, (2000), pp. 502–507
14. Apple S1, https://en.wikipedia.org/wiki/Apple_S1
Design Technologies for Advanced
Packaging 58
Jun Li, Yunyan Zhou, Min Miao, Wei Wang, Fei Su, and Fengman Liu

Contents
Typical Advanced Packaging Selection and Design Essentials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
SiP Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
2.5D Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
Wafer-Level Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Package-on-Package (PoP) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Chip-Package-PCB Codesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Electrical Codesign of Chip-Package-PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Heat Dissipation Codesign of Chip-Package-PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
Thermal-Mechanical Reliability Codesign of Chip-Package-PCB . . . . . . . . . . . . . . . . . . . . . . . . 1134
Electrical Considerations for Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
Signal Integrity (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
Power Integrity (PI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
Power Dissipation and Power Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
Thermal Design of Electronic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
Metrics of Thermal Design of Traditional Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
Demands of Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
Thermal Design of Internal Heat Conduction Resistance in Package . . . . . . . . . . . . . . . . . . . . . 1138
Thermal Design of External Heat Sink in Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
General Rules for Packaging Material Selection and Structure Design . . . . . . . . . . . . . . . . . . . . . . . 1140
Electro-Thermo-Mechanical Multiphysics Design [9, 10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141

J. Li (*) · Y. Zhou · F. Liu

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
e-mail: lijun@ime.ac.cn
M. Miao
Beijing Information Science and Technology University, Beijing, China
W. Wang
Peking University, Beijing, China
Institute of Microelectronics, Peking University, Beijing, China
F. Su
Beihang University, Beijing, China

© Publishing House of Electronics Industry 2024 1129

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_58
1130 J. Li et al.

DFM/DFR/DFT Codesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143

Design for Manufacture (DFM) [11, 12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
Design for Reliability (DFR) [13, 14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
Design for Test (DFT) [15, 16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
The Design and Simulation Flow for IC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
System Function Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
Selection of the Package Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
Structure Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Verification of the Key Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Product Manufacture and System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Current Status and Development Trend of Design and Simulation Tools . . . . . . . . . . . . . . . . . . . . 1147
Package Layout Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Package Electrical Simulation Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Package Thermal Management Simulation Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Package Mechanical and Process Simulation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Developing Trend of Packaging Multiphysical Field Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
Codevelopment of SiP and SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151

Abstract
With the trend of electronic products toward multifunctions, miniaturization, and
high performance, the advanced packaging and system-on-chip technologies are
the main methods to achieve higher added value products. In order to ensure
product performance, design technologies become increasingly more important.
This chapter summarizes and discusses the key points of design technologies for
advanced packaging. According to the performance requirements, different pack-
age types and material systems should be selected. Electrical, thermal, and
structural designs, even multiphysics analysis, and necessary collaborative
designs are needed.

Keywords
Electrical design · Thermal design · Structural design · Multiphysics coupling ·
Collaborative design

Typical Advanced Packaging Selection and Design Essentials

With the trend of electronic products toward multifunctions, miniaturization, low

power, and heterogeneous integration, the advanced packaging technologies (e.g.,
system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D packaging, etc.)
are increasingly used in electronic products. The demands of electronic products
vary with applications (e.g., high frequency/high speed, high reliability, high heat
dissipation, low cost, miniaturization integration, etc.). From design viewpoints, the
packaging materials and technologies should be selected based on actual requirements.
Low-loss materials are required for high-frequency and high-speed demand. Materials
58 Design Technologies for Advanced Packaging 1131

with high Young’s modulus and matched coefficient of thermal expansion (CTE)
match are needed for high-reliability applications. The thermal resistant short-
coming needs to be optimized for applications with large heat dissipation,
low-cost materials and processes for low-cost packaging technologies. SiP and
2.5D/3D packaging are suitable for miniaturization integration demand. In short,
the chip-package-PCB codesign, the electro-thermal-mechanical multiphysical
codesign, and DFX (e.g., DFM, DFR, DFT, etc.) are necessary to achieve high-
performance and high-reliability integration of packaging technologies with IC
designs. Finally, the selection and design essentials for several typical advanced
packaging are as follows.

SiP Technology

It can integrate a system or subsystem into a package. Generally speaking, multichip

module (MCM), 2.5D packaging, stacked packaging (PoP), and other 2D/3D pack-
aging technologies are in the domain of SiP technologies. It is applicable to some
small and modular electronic products (e.g., smart watch). Based on process capa-
bility and characteristics of bare dies and devices, both 2D with side-by-side
assembly and 3D stacking or embedded types for higher integration can be selected.
Considering the electrical performance, isolation and shielding technology can be
used to solve the noise interference problem. The optimization of heat dissipation
structure and material selection can be used to solve multichip “hot spots” problems,
especially for optical devices packaging with low-junction temperature. Considering
2D/3D heterogeneous chips integrated packaging, more attention needs to be paid
for the structural design and material selection for warpage, stress, and thermal
fatigue.

2.5D Packaging

2.5D packaging including multidies, a silicon interposer, and an organic substrate, is

suitable for fine-pitch high-density system to solve the limitation of organic sub-
strate. In 2.5D packaging structure, multidies locate on a Si interposer, and the
interposer locates on an organic substrate. Through-silicon-via (TSV) is used for
vertical signal interconnection. The 2.5D packaging is an important technology for
digital high-density system packaging, such as CPU, FPGA, and memory system
integration. The CTE of silicon interposer is the same or similar to that of a bare die,
and the thermal conductivity of silicon is very high. The material properties can
improve the reliability and heat dissipation abilities. Chip-package-PCB codesign,
design-for-test (DFT), and structural design are the major design methods for digital
system applications. 2.5D packaging is also applied for RF system integration. Some
passive devices, such as filters, antennas, and couplers can be integrated into one
package. High-frequency transmission, noise suppression, and heterogeneous chip/
device integration are the major design problems for RF system applications.
1132 J. Li et al.

Wafer-Level Packaging

Compared with the traditional package technology, wafer-level packaging (WLP)

can improve the production efficiency, and reduce the packaging cost of single chip.
According to the relationship between the layout of solder balls and chip size, it can
be divided into fan-in WLP (FI-WLP) and fan-out WLP (FO-WLP). WLP eliminates
substrate, wire bonds or C4 bumps, and reduces packaging cost and interconnection
parasitic. The thickness of WLP is thinner and can be used for high-frequency
applications. FI-WLP is applicable for low-density single-die packaging,
and FO-WLP is suitable for high frequency, even microwave chip-packaging, and
multidie packaging. For FI-WLP, the optimization of wafer-level warpage and local
stress during process is the key for design of experiments (DOE). For electrical
performance, chip-package-PCB codesign, and high-frequency transmission are the
major design methods for high-frequency and high-speed signal transmission in the
system.

Package-on-Package (PoP) Technology

It is a 3D packaging with packages stacked on together. Using PoP, the interconnect

length between top and bottom packages is reduced and at the same time, the vertical
interconnects provide enough bandwidth. The overall package size can be reduced
comparing with 2D packaging. The bottom package is usually a flip-chip ball grid
array (FCBGA) package. In order to further reduce the packaging thickness, fan-out
packaging can also be used in the bottom package. The typical application of PoP is
the integration of processor and memory systems in intelligent terminal, which is
used to shorten the transmission delay and improve the bandwidth between storage
systems. From the design point of view, the warpage control of top and bottom
packages, heat dissipation in 3D packages, signal integrity (SI), and power integrity
(PI) should be solved for PoP.

Chip-Package-PCB Codesign

The interactions among the chips, package, and printed-circuit-board (PCB) are
greatly influenced on the package performance. The chip-package-PCB overall
codesign can optimize the performance of the chips, packages, and the entire
systems, but also reduce design iterations, shorten design cycles, and lower design
costs of new products.

Electrical Codesign of Chip-Package-PCB

The first step of chip-package-PCB codesign is to analyze the product characteris-

tics, such as product function, environmental conditions, technical indicators, etc.
58 Design Technologies for Advanced Packaging 1133

According to this, chip design including the optimization of I/O pin layout is
performed. Combined with the chip’s function, performance, and cost, appropriate
interconnection is selected (e.g., wire bonding, flip-chip, etc.), which can reduce the
complexity of the substrate layout and improve the transmission characteristics.
Based on the chip’s netlist, pin distribution, and other die electric information, the
package design is implemented.
Considerations of the chip and product characteristics, the corresponding package
type (e.g., ball grid array package (BGA), Land Grid Array package (LGA), Quad
Flat No-lead Package (QFN), etc.) is selected to ensure properly input and output of
the signal and power of the chip. The package structure can realize the interconnec-
tion and mechanical protection of the chips. Synthesized with the layout difficulty
and function of the PCB, the designation of the entire system is completed. Then the
electromagnetic characteristics of the chip, package, and PCB are modeled and
simulated separately. After this, chip and PCB equivalent electrical model are
extracted, and imported into the simulated package electrical models.
The whole transmission path of the signal and power are established, and the
system-level simulation is completed. At last, based on the simulation results, the
impact of the chip, package, and PCB design to the entire system performance is
analyzed and the optimization design is carried out.
The electrical design and simulation process for chip-package-PCB codesign is
illustrated in Fig. 58.1. In the codesign process, combined with the respective
characteristics of the chip, package, and PCB, the power integrity design is
conducted to provide a clean and stable power delivery network for the chip,
which ensures a low-impedance and low-noise reference loop for the signal and
the suppression of electromagnetic interference.

Fig. 58.1 Electrical design and simulation process for chip-package-PCB codesign
1134 J. Li et al.

Based on the chip equivalent electrical model, e.g., SPICE or IBIS model,
package electrical model, e.g., RLCG, S-parameters or SPICE model, and PCB
model, e.g., RLCG or S-parameters, the electrical performance design and simula-
tion of the entire system are performed.
By the software modeling tool, hardware test instrument, and the electrical
characteristics of the interface circuit, the cooperated modeling and parameter
extracting of chip and package are completed. The design parameters and files
satisfying the system index are obtained by simulations. In the end, a complete
safely optimized design scheme is achieved.

Heat Dissipation Codesign of Chip-Package-PCB

The difference of thermal power consumption of the chip puts forward raises
different requirements for the package structures, materials, heat dissipation design,
etc. According to different characteristics of the product, the appropriate heat
dissipation mode (e.g., air cooling, water cooling, and natural convection), package
structure (e.g., internal heat sink, heat dissipation via, substrate structure, etc.), and
packaging materials (e.g., patch adhesive, molding compound, and substrate mate-
rials, etc.) are selected to effectively transfer heat generated by the chip to the PCB or
radiator.
The main purpose of heat dissipation collaborative design is to achieve reason-
able layout of chips, packages, and PCB, so as to control local hot spots and improve
overall heat dissipation, and meet the requirements of product performance and
reliability. Combining the simulation results with the testability experiments, the
temperature distribution analysis of the single or multichip integrated packages is
analyzed step by step, and the relationship between the chip, the thermal interface
material, and the whole heat dissipation structure is studied, and the design scheme is
adjusted and optimized to improve the overall heat dissipation performance of the
system.
Collaborative design optimizes the heat dissipation scheme and connection
mechanism of the system by using different materials, structures, and heat dissipa-
tion methods (e.g., Cu base and through-via, new thermal interface materials, and
auxiliary heat dissipation devices, etc.).

Thermal-Mechanical Reliability Codesign of Chip-Package-PCB

The main purpose of the codesign for the thermal mechanical reliability of chip-
package-PCB is to analyze the mechanical interactions, and to design and optimize
the structural and material of the chips, packages, and PCB.
Thermal-mechanical reliability analysis can simulate the stress gradient distribu-
tion of different packaging structures and materials so as to select structures and
materials that meet the chip parameters, and control the stress gradient distribution
within the range of stress-dependent properties such as linearity, gain, voltage offset,
58 Design Technologies for Advanced Packaging 1135

etc. It can also analyze the CTE mismatch of different materials among chips,
packages, and PCBs and the thermal stress and warpage due to process residual
stresses varying with temperature. The thermomechanical simulation method can be
used to analyze the problems layer-by-layer, and a practical and complete reliability
scheme can be proposed.

Electrical Considerations for Package Design

One of the major functions of packages is to provide the chips with power supply and
the routes for electrical signals, both to external chips and to internal chips in the
package. Their electrical performances are therefore essential to the proper func-
tioning of ICs integrated into a higher-level assembly. The following aspects are
considered for package design:

Signal Integrity (SI)

Signal integrity (SI) refers to the quality of electrical signal transmitted through
package-level interconnects, including both the voltage waveform accuracy and the
timing accuracy of signal rising/falling edges reaching the receiver input, which are
more specifically expressed by the indices on delay, reflection, cross talk, timing, and
oscillation characteristics. In engineering practice, the electrical signal transmission
may be degraded (e.g., a closed eye diagram at the receiver input) or even the circuits
may not keep its stability due to the distribution of nonideal physical factors (e.g.,
cross talk, radiation, impedance mismatch, and delays) among intricate package
electrical signal interconnects.
Thus, in order to ensure SI, it is necessary to grasp the mechanisms, characteris-
tics, and correction methods in design. At present, SI investigations are mainly
focused on the analog properties of digital circuits, and the fundamental principles
and analysis perspectives are actually the same as those of analog and RF/microwave
IC packages. Normally, SI issues are prominent in packages and circuit board
systems with operational clock frequencies higher than 50 MHz, while current
operational frequencies in digital circuits are well above this level and are continu-
ously increasing. Hence, the severity of the adverse impact from the nonideal factors
mentioned above rises sharply with the increase of frequency and SI issues become
more and more serious.
From an electromagnetic perspective, SI issues may fall into the following two
categories: (1) Parasitic couplings between adjacent signal interconnects and the
associated distortion of electromagnetic (EM) field distribution; (2) Parasitic EM
wave propagation modes, signal routes, and multiple reflections induced by
asymmetries and discontinuities along transmission lines.
Accordingly, the electrical design of packages based on the combination of
physical and circuit modeling and actual measurements can reveal the effects of
physical structure on the distribution and propagation of EM fields; and determine
1136 J. Li et al.

Fig. 58.2 The high-speed channel in a package interconnect system and the transmitting/receiving
waveforms and eye diagrams

parameters of the IC, auxiliary components, packaging substrate, and PCB. Then the
design rules for IC layout and other components, routing of high-speed signal
interconnects, filter and grounding, and corresponding signaling rules (e.g., data
coding and termination, and channel equalization measures) can be formulated, so
that the signal reaching the pin of the receiver chip can meet the timing, duration, and
magnitude requirements with good signal integrity.
Highly reliable physical transmission channel and mechanism can be established
by the adoption of appropriate signaling and influencing mechanism for SI. With the
help of signal recovery, it is seen in Fig. 58.2 that the received signal with a closed
eye diagram can be recovered to a level close to the output of the transmitter driver
output.

Power Integrity (PI)

It denotes the value accuracy and stability of the power supply voltage at the chip
power pins inside a package, which is expressed by the fluctuation range and the
noise of chip power supply voltage. In engineering practice, it is necessary to reveal
the impact of nonideal factors on the package power distribution network (PDN) and
master the anticipation and evaluation methodologies, so as to put forward corrective
measures in the design. The fluctuations of power supply will inevitably affect the
signal output and the receiving thereof, exacerbating SI issues, and as such, PI and SI
issues should be solved together.
The direct causes of PI issues include the resistance drops of power distribution
network (PDN) and the voltage fluctuations induced by current fluctuations in a
power loop (e.g., the synchronous switching noise, SSN). The former is a
58 Design Technologies for Advanced Packaging 1137

low-frequency signal that can be eliminated by identifying and reducing the parasitic
resistance in the design. For the latter, it results in fluctuations at higher frequency
and has impacts on chip, package, and PCB levels.
It is essential to analyze the PDN current loops and their waveform spectrums in
typical IC operation modes, and identify significant parasitic inductance, capacitance
or EM emissions in interconnects, and the spectral components of power supply
fluctuations. Potential solutions to suppress the voltage fluctuations can then be
proposed.

Power Dissipation and Power Capacity

The indices of power dissipation and capacity, as essential factors for long-term
thermal stability and power system design, are largely determined by operation
frequency and modes. At the package level, the major source of power dissipation
is the heat dissipation from the package interconnects, including ohmic heat and
dielectric loss in addition to the heat from IC chips.
The ohmic heating and dielectric loss cannot be neglected due to small cross
section of interconnect in package (a few square microns) and the extensive appli-
cations of new dielectrics. In addition, total power dissipation may also arise from
the interface-phonon interaction in the nanoscale interconnects of nanoscale ICs and
the through-IC vertical interconnects inside 3D package. For power electronic
devices, the power capacity is normally expressed by the maximum voltage and
current to ensure its long-term stability and reliable operation.
In order to accurately analyze the power consumption and power capacity,
thermal physical models of the package interconnect may be established using a
combination of theory, simulation, and measurement. Then the characteristics of
power consumption and output at various frequencies and operation modes are
calculated, so that the two parameters can be determined accordingly.

Thermal Design of Electronic Package

Metrics of Thermal Design of Traditional Packages

Key thermal resistance of typical packages of ICs as defined in the International

Semiconductor Equipment Materials Industry Association (SEMI STD G38-0996)
[1] and the International Electrotechnical Commission (JEDEC JESD51 standard)
[2, 3] is shown in Fig. 58.3, where TJ is the device temperature in the IC chip. As the
indicator of the thermal performance of the chip, the value of TJ is mainly deter-
mined by the power consumption and the heat dissipation capability.
Thermal optimization of an IC package can also be performed from two parts.
One is to reduce or homogenize the power generation of hot spots through a
low-power design, layout optimization design, etc. The other is to reduce the thermal
1138 J. Li et al.

Fig. 58.3 Thermal resistance of the package [4, 5]

resistance in the package, including optimizations of the internal heat conduction

resistance and the external heat sink dissipation capacity.

Demands of Thermal Design

In the 3D-stacked IC architecture, a large number of low thermal conductivity

materials are used as fillers. Meanwhile the size of the hotspot decreases with the
decrement of the manufacturing nodes, resulting in an exponential-shaped increment
of the heat conduction resistance, together with a dramatic increment of chip power
density, all making the thermal design of package more difficult.

Thermal Design of Internal Heat Conduction Resistance in Package

(a) Thermoelectric design: The hot spot distribution (thermal performance) of the IC
is determined by the power consumption (electrical design). With a thermal-
electrical codesign to plan the power distribution of the ICs and layout, the hot
spots can be evenly distributed within the chip. This is the first step in the thermal
design of package.
(b) Thermal design of TSV-based 3DICs: The redistributed Cu (RDL) hot wires and
through-silicon-via (TSV) hot via are usually composed of high-thermal con-
ductivity materials (e.g., Cu) in the 3D IC/packages as a high-thermal conduc-
tion path in thermal design. By the thermal-electrical codesign, the hot TSV and
hot wires can be carefully designed to achieve the maximum heat dissipation in a
limited area, thereby efficiently reducing the thermal resistance between hot
spots and heat sinks.
(c) Chip-level embedded microfluidic cooling techniques: The microfluidic cooling
technique [6–8] inside the chip is one of the frontier areas of the thermal
management of packages. By fabricating a microchannel inside the silicon
substrate and forming convection inside the channel, the distance from the hot
58 Design Technologies for Advanced Packaging 1139

spots to the heat sink can be dramatically shortened, thus reducing the thermal
resistance.

Presently, the microfluidic cooling technique is facing high challenge in design and
fabrication complexity, including design and fabrication of microchannel networks
in IC or interposers. The greatest challenge is the reliability of the embedded
microfluidic cooling which ensures a leak-free fluid flow under the working pres-
sure. Meanwhile, the mechanical reliability of 3DIC packages is facing tremendous
challenges due to the pressurized fluid flow in the embedded microchannels affected
by the small geometric size of the package.

Thermal Design of External Heat Sink in Package

(a) Thermal interface material (TIM): It is a material with a high thermal conduc-
tivity for physically connecting the chip with the heat sink. The TIM is one of the
important parts in the package. The interface thermal resistance is composed of
two parts: the contact thermal resistance at the interface between different objects
and the gas thermal resistance in the gaps at the contact interface. In general, a
low thermal conductivity of the interface material and a large roughness of the
contact surfaces will result in the interface thermal resistance. A general strategy
for TIM design is to add high-thermal conductivity fillers to the base of the
bonding material so as to improve the effective thermal conductivity. With the
development of new materials and composites, more and more TIMs with a high
thermal conductivity have been introduced into the packaging field (e.g., thermal
conductive adhesives, phase change materials (PCM), and thermal conductive
elastomers). As new high-thermal conductivity filler, carbon nanotubes and
graphene have also been used to improve the TIM properties thereby improving
the thermal performance of the package. Conductive Ag glue, Sn paste, and
eutectic soldering materials with good electrical conductivity are widely used in
applications.
(b) Heat sink technique: Heat sink is the unit that removes the heat from the package
to the environment. Techniques of heat sink usually include air cooling, immer-
sion cooling, liquid cooling, heat pipe cooling, thermoelectric cooling, phase
change cooling, microspray cooling, etc. Among which, air cooling and liquid
cooling are the mostly used. Air cooling technique usually uses metal materials
to form fin shape structure to increase the convection area, thereby improving the
heat dissipation capability. The liquid cooling technique, as the same as the
previously introduced microfluidic cooling but no microchannels, uses forced
convection of liquid to remove the heat. Similarly for the air cooling, to enhance
the heat dissipation capability, the channel structure needs careful design to
enhance the convection. Turbulence, if possible, holds better heat dissipation
capability but requires higher pump power to drive the fluid.
1140 J. Li et al.

General Rules for Packaging Material Selection and Structure

Design

The reliability of IC Packages relies on the proper selection of material and structure
design. The most commonly observed failure modes of IC packages include the die
cracks by thermal stresses or deformation, solder bridging or nonwetting during the
reflow process, etc., these are termed as thermomechanical reliability issues. Over
high thermal stress not only does harm to the mechanical integrity of IC packages,
but also affects the electrical property of die by piezoresistive effect. On the other
side, with the rapid scaling of IC, the current density in I/O increases drastically as
resulting in electromigration (EM) failures (Note EM is a phenomenon of mass
diffusion of conductive metal atoms from cathode to anode, which causes voids,
cracks, and open circuits at the cathode end, while those migrated atoms may pile up
at the anode end and cause hill-locks, short circuits, etc.).
Thermoplastic polymer materials are wildly used in ball grid array (BGA) and
plastic quad flat pack packing (PQFP) because of its light weight and low cost. But
these plastic materials may absorb moisture from environments, which can corrode
the metal part, furthermore, hot steam may formulate and cause popcorn cracks
during the reflow soldering due to the sudden increase of temperature. Meanwhile,
the moisture can also cause expansion of these materials and consequently cause
hydro-stress and some new failure modes, such as under bump opening in flip-chip-
packaging.
Optimal design of the packaging structure can improve the reliability, e.g., the
increase of the equivalent CTE in the 3D packaging based on TSV filled with Cu can
actually weaken the thermal mismatch between chip and substrate. Give the total
amount of TSV, an array distribution is more efficient than the ring distribution (with
TSVs only along the chip side) in reducing the thermal mismatch.
To improve the reliability of IC packaging, the following rules in the selection of
material and structure design shall be followed:

1. Coefficient of thermal expansion (CTE) mismatch among different packaging

materials shall be reduced to the greatest extent. By taking the flip-chip as an
example, ceramic substrate is more efficient in reducing the CTE mismatch
between substrate and chip in comparison with FR4 (Epoxy Glass Cloth) and is
thus helpful to increase the reliability of flip-chip. The use of under-fill with an
intermediate CTE between that of substrate and chip is another measure to
improve the reliability of flip-chip. In BGA packaging, the critical solder which
turns to fail firstly usually appears at the farthest point away from the center, so if
other conditions remain unchanged, reducing the size of the package is helpful to
improve the thermal fatigue of the solder.
2. Interconnections with proper material composition and geometric shape should
be employed. At the same current density, different material has different resis-
tance to electromigration. Adding proper elements to solder material can increase
its resistance to electromigration (EM). On the redistribution lines of PCB and
chips, sharp or right corners shall be avoided, as an obtuse angle of 135 is usually
58 Design Technologies for Advanced Packaging 1141

adopted to avoid/reduce the locally enhanced current density and thus less the
occurrence of EM. Microsolder joints formed by reflow-welding process turned
to have the current density concentrated at the corner connected with Cu pad,
especially at cathode side. Void and crack may form at cathode and extend along
the interface between IMC and solder. Study shows that thick Cu pad turns to
uniform the current density distribution and alleviate the EM failures. Another
rule tells us that the increase in the flexibility of microsolder is helpful to extend
its fatigue life.
3. Dry storage and baking technique should be employed to prevent moisture from
diffusing, especially for those packages in wet regions. To further avoid popcorn
crack, baking should be processed before reflow soldering, the temperature for
baking and the rate of temperature rising should not be too high. On certain
occasions with very high requirement on reliability, ceramic material which did
not absorb moisture completely should be used as packaging material, but this
will take a higher financial cost.
4. Symmetric structure and material arrangement should be guaranteed. From the
perspective of mechanical analysis, if the geometrical structure and material
arrangement are totally symmetrical, warpage displacement will disappear. A
seriously asymmetrical design turns to cause large warpage, which may lead to
nonwetting and solder bridging.
5. Virtual reliability design is suggested, which is mainly realized with finite
element method (FEM). Optimization in the package design can be realized to
minimize the thermal stress and thermal deformation for the best thermo-
mechanical reliability. In some big companies, FEM simulation has become an
important reference in package design. This can reduce the costs on failure
analysis and reliability experiment, and enhance the efficiency of product design
and accelerate the product listing to market.

Electro-Thermo-Mechanical Multiphysics Design [9, 10]

ICs in packages can be considered as typical composite structural systems consisting

of multiple materials, but also as typical multiphysics coupled systems. In the early
stage of packaging technology development, the multiphysics coupling is relatively
weak, and the designs and analysis for electrical performance and thermomechanical
reliability respectively are separated for simpler design. With the advancement of
nanoscale ICs and emerging of various advanced packages, all kinds of new
structural materials, novel nanoscale transistor structures, and novel interconnect
units like TSVs have been introduced into advanced ICs and packages.
In such a multiscale structure spanning from nanometer (nm) through millimeter
(mm) scales, the influence of material interfaces becomes increasingly prominent,
the multiphysics couplings, such as the electro-thermo-mechanical ones, are getting
more significant, and devices based on new physical effects may be integrated into
the IC package or even the IC itself. Therefore, multiphysics coupled designing must
be adopted for the design and analysis of nanoscale ICs and the associated
1142 J. Li et al.

Fig. 58.4 The coupled multiphysics in a package

single-chip or integrated package. Figure 58.4 displayed the intercoupled multi-

physics fields that may coexist in a package.
Corresponding multiphysics design should be made based on a thorough under-
standing and analysis of the coupling between mechanical, thermal, and electrical
fields and the relative intensities in-between; normally, it is to be eventually facili-
tated by codesign, coanalysis, cooptimization, and cosimulation, so that a design
loop is completed. A typical design loop may start with the electrical design; on the
basis of electromagnetic (EM) characteristic simulation for the physical layout, the
temperature and strain-stress fields distribution can be obtained by solving the EM
field and current distribution; and the thermal indices like junction temperature and
thermomechanical issues like delamination can be evaluated to decide whether it is
necessary to make a further optimization of the original layout.
At present, the package design and analysis software tools are developed for
noncoupled multiphysics. To realize a true multiphysics design, the following
approaches can be taken in the tool development and detailed design practice:

1. Implementation of the multiphysics coupling directly on the element meshing

level for physical modeling. Nowadays, the basic element models of various
kinds of physical modeling and simulation software are developed for just single-
physical field. The self-consistency and accuracy in solving may only be funda-
mentally guaranteed when the multiphysics coupling is realized on the element
level. However, even after the coupling are incorporated into the basic element, in
most cases, the meshing for each physical fields shall be optimized respectively,
which aggravates the difficulty of software solving, and may be implemented just
for a few field geometries.
58 Design Technologies for Advanced Packaging 1143

2. Combination of single-physical field design tools implemented with the data

exchange applets and execution control programs for automatic simulation.
Design tools for single-physical field may be combined with auto-run data
exchange applets and simulation execution programs, so that convergence of
designs and simulations can be eventually reached through the iteration of design
data flowing between the tools. This might be the most feasible solution for the
analysis of a composite multimaterial package system at present; however there
are drawbacks such as the low data conversion efficiency and declining of
solution efficiency induced by the data iteration. The methodology above is
beneficial for the integration of EDA software platforms which may manifest
itself as a highly efficient design tool implementation and is attracting more and
more attentions.

DFM/DFR/DFT Codesign

DFX includes design for manufacturing (DFM), design for reliability (DFR), and
design for test (DFT). DFX overlaps with each other and is inseparable. It is
necessary to consider the iterative optimization of design and process comprehen-
sively. The sketch of DFX codesign is shown in Fig. 58.5.

Design for Manufacture (DFM) [11, 12]

Based on the advanced packaging capability and the requirements of packaging

performance, the purpose of DFM is to integrate the design and manufacturing
ability comprehensively. The packaging capability plays an important role of pack-
aging design. The electrical, heat dissipation, and packaging structure design should
be determined by the process design criteria required for mass production, and the
process adjustment and optimization should be allowed under special requirements.
For example, in order to increase the heat dissipation ability, there is a large area of
bare pad at the center of the bottom of QFN package. According to the design rule of

Fig. 58.5 The sketch of DFX

codesign
1144 J. Li et al.

QFN package, the integration of single or multichip can be realized. In order to

provide RF and even millimeter wave application, the length of wire bonds and the
material of epoxy molding compound (EMC) should be optimized based on QFN
packaging process. Stacking dies is a typical 3D packaging, which can reduce the
package size and improve the integration density. In order to increase the number of
stacking chips, chip thinning and low-arc wire bonding process should be studied.
For the optimization of the package structure/materials due to the applications,
reliability should be considered at the same time. Therefore, the codesign for DFM
and DFR is needed.

Design for Reliability (DFR) [13, 14]

The purpose of DFR is to achieve iterative optimization of structure and material and
eliminate potential reliability hazards by DOE test design method. At the beginning
of the design, the reliability-related issues such as thermal stress/strain, thermal
fatigue, and electromigration of packaging can be studied and optimized by com-
bining simulation, theoretical analysis, and experimental verification. The thermal
stress is resulted from thermal mismatch between different materials, so the sym-
metrical structure and suitable materials shall be adopted. The thermal expansion
coefficient and glass transition temperature (Tg) are the key parameters of packaging
material. Under-fill shall be chosen to improve the reliability of packaging. For the
advanced packaging of low-k chip, the warpage and stress can lead to the delami-
nation on chip interface and other reliability problems, so the chip-package interac-
tion (CPI) issue is also an important part of DFR design. For the mass production
capability, the optimization process of DOE can be realized by finite element
simulation with different levels and factors. After experimental verification such as
warpage measurement, the final design scheme of packaging structure/material is
provided.

Design for Test (DFT) [15, 16]

Generally speaking, DFT refers to the process of designing systems and circuits with
a certain amount of hardware overhead and maximum testability. The purpose is to
detect production faults. For example, the common DFT methods of digital circuits
are scan test (SCAN), built-in self-test (BIST), boundary scan, and so on. These DFT
methods can be applied to conventional packaging forms, such as QFN, BGA, and
so on. For a complex packaging such as 2.5D, the DFT design should also be carried
out in the process of packaging preparation. In order to test the yield of TSV
interposer, besides direct contact measurement by probe, TSV test circuits can also
be designed mounted on a TSV interposer. For special requirement packaging,
including high-frequency/high-speed packaging, high-power packaging, etc., a sin-
gle performance test scheme is needed. For example, the electrical test vehicle based
on typical interconnection structures is used for electrical properties measurement;
58 Design Technologies for Advanced Packaging 1145

the thermal resistance test vehicle is used for junction temperature and thermal
resistance measurement; and the test vehicle based on Chrysanthemum chain is
used for packaging process development and reliability evaluation.

The Design and Simulation Flow for IC Packages

The design and simulation flow for IC package guide the package engineer in the
design and implementation of a complex package integration system. A typical
package design and simulation flow are shown in Fig. 58.6.

System Function Analysis

Defining the function and application scenarios of the product, and based on it,
technical indicators are formulated and the feasibility of the system implementation
is evaluated. To divide the functions of the packaging system, evaluate the imple-
mentation and interconnection of each functional area, initially integration scheme is
determined.

Fig. 58.6 A typical package design and simulation flow

1146 J. Li et al.

Device Selection

According to the function and index requirements of the packaged product, deter-
mine the device model in the package model (e.g., selecting the appropriate device
according to the operating frequency (rate), bandwidth, operating voltage, linearity,
power consumption, etc.) of the system; for different environments, the requirements
for the device are also different. Functional verification and link-level simulation are
completed in conjunction with the device model and connection relationships to
evaluate the feasibility of the solution and validate the design.

Selection of the Package Type

Different package types, such as BGA, QFN, LGA, POP, etc., are selected based on
the different functions of product, costs, and leading out methods of the pins of bare
chip. The pin distribution of a package mainly follows several principles: (a) easy to
encapsulate the substrate and PCB layout; (b) the reference loop of the signal is as
short as possible, and ensure the continuity of the impedance; (c) reduce the
impedance and noise of the power distribution system; use ground isolation between
different power levels; (d) the key signal lines are isolated by power or ground.

Structure Design

Structure design will directly affect the final cost, performance, and reliability of the
product. Design the package structure for the application environment and
indicators, select the appropriate substrate and packaging type, and complete the
evaluation of passive component modeling and interconnect model. For multichip-
packages, choose the appropriate stack or 3D structure. Structure design also needs
to consider some factors such as electromagnetic shielding, heat dissipation capa-
bility, reliability, and etc.
In order to optimize and evaluate the designed package structures, electrical
performance simulation, thermal management analysis, and thermal-mechanical
simulations are required with multiphysical coupling simulations. By using the finite
element method, the tasks include the following: (a) establish a 3D geometric model;
(b) set the simulation boundary conditions (e.g., constraints, ambient temperature,
etc.); (c) load the temperature curves, when analysis the temperature changes for the
reliability problems (e.g., warpage, delamination, chip cracking, solder joint failure,
etc.), which caused by the thermal expansion coefficient mismatch of different
materials in the package and the residual stress accumulated in the process;
(d) carry on the improvement of the next model and optimization design. Through
the simulation tests to determine the best package structures and materials selection,
if the experimental verification is required, the corresponding reliability test and
failure analysis can be carried out.
58 Design Technologies for Advanced Packaging 1147

Layout Design

The design rules of system-level of package electrical design include wiring and
bonding line design rules, the optimization principles of microstrip, substrate via,
and pin layout. To make the hot spots evenly distributed, each link meets the
transmission and isolation requirements, substrate stack design, and layout design
are completed according to design structure and actual requirements. Conduct
multiphysical coupling analysis, (e.g., electrical performance analysis, thermal-
mechanical simulation, and thermal management analysis), extract the electrical
model of the passive network, and combine the active chip model to perform link
function verification and performance optimization for better signal integrity (e.g., S
parameters, and TDR, etc.) and power integrity (e.g., IR drop, and input impedance,
etc.) of the simulation and validation index and reliability after layout. In the process
of layout design, the collaborative design and simulation between DFX (DFM, DFR,
and DFT) and chip-package-PCB are considered.

Verification of the Key Process

When the package structure is complex or the package structure/material and process
are optimized according to special requirements, key process verification is required.
For example, the wafer or board-level fan-out process requires strict control of the
warpage. In addition to simulation optimization, samples will be tested for experi-
mental verification on key processes such as plastic package and debonding. For the
CPI (chip-package-interaction) design of the low-k chip, the corresponding samples
are also prepared for reliability test verification for key processes.

Product Manufacture and System Testing

After the design, simulation and optimization of the package are completed, sub-
strate processing and microassembly are performed to complete the manufacture of
the package sample. Test board design and processing is based on test content,
interface, and plan. Set up the test environment, get the test results, and process
analysis. If the evaluation indicators are met, complete the package design, otherwise
optimize the design.

Current Status and Development Trend of Design

and Simulation Tools

The rapid development of IC and electronic systems promotes the continuous

innovation of packaging and integration technology toward light weight, high
integration, and diversification. The design and simulation tools of electrical, ther-
mal, mechanical, and structure in packages have been developed rapidly.
1148 J. Li et al.

Package Layout Design Tools

Package layout design tools can quickly analyze the feasibility of package design,
substrate, and PCB design, to reduce the design risk. Layout design tools have
design environment for system-level packaging design and chip-package design,
supporting pin grid array (PGA) package, solder ball array, microsolder ball array,
flip-chip, and lead bonding process, providing rule management tools throughout the
process of substrate design, providing design methods that support design rules, and
having complete design rule specifications environment; supporting chip creation/
editing; supporting blind and buried via design according to rules; supporting
ceramic packaging technology and TSV process design.

Package Electrical Simulation Tool

Package electrical simulation tool is one of the basic tools for studying electrical
performance of system-in-package (SiP), and it is an essential software for micro-
electronics packages and SiP. Signal integrity (including power integrity) simulation
software has a good interface with package layout design files. It can realize the
import and export of layout design software, finish time-domain and frequency-
domain simulation, model and optimize various package structures, and complete
the impedance analysis, cross talk and coupling of signal lines, parameter extraction,
S-parameter analysis, transfer coefficient analysis, and so on. Power integrity
includes DC and AC characteristics analysis, has become an important factor
affecting the performance of modern electronic systems. Power integrity simulation
can quickly position current density temperature, AC margin, and the stability of SiP
power supply to reduce risk.

Package Thermal Management Simulation Tool

Package thermal management is an important factor to measure product performance

and reliability. With development of the package miniaturization and high density,
thermal cross talk increases; at the same time, some stacked package structures result
in the increase of heat flux density and multichip integration also causes the “hot
spot” problem in the system. The thermal management simulation tool can simulate
and optimize the temperature distribution, thermal resistance analysis, current den-
sity of the packages.

Package Mechanical and Process Simulation Tools

The mismatch of thermal/humid expansion coefficients of various material systems

can easily result in thermal/humid stress, which leads to the reliability problems, e.g.,
package warpage, delamination, cracks, and creeps. The effects of stress impact,
58 Design Technologies for Advanced Packaging 1149

e.g., drop and vibration can also result in reliability problems (e.g., delamination,
crack, and creep of packaging). Package mechanical simulation tools can perform
multiphysical field coupling simulation analysis, which is usually used to determine
package structure and materials with simulation optimization methods. In addition to
mechanical simulation such as stress and warpage, typical packaging processes (e.g.,
molding and etching) can also be simulated by EDA; and can also be analyzed the
bubbles, molding flow, and morphology generated in the process for improving
packaging process, efficiency, and reducing production risks.

Developing Trend of Packaging Multiphysical Field Tools

Package design tools gradually include simulation functions and simulation tools
also cover design modules. Design and simulation tools show a trend of integration,
and multiphysical field simulation software has been developed rapidly. As shown in
Fig. 58.7 below, for example, layout design software gradually includes the func-
tions of electrical and thermal simulations. In addition to the interface of importing
design files, some simulation software vendors have developed design software.
Some multiphysical field simulation software includes several independent simula-
tion modules in different fields. Users can choose different design simulation
modules to perform package design and simulation according to the design require-
ments. Therefore, from practical view, the integration of packaging design and
simulation tools is an important trend; from the view of actual needs for engineering
projects, the multidisciplinary analysis tools enable problem solving from combined

Fig. 58.7 Design and simulation tools for packaging

1150 J. Li et al.

approaches and have ability for synthesizing and optimizing packaging issues from
overall considerations; thus, it will grow rapidly and widely used.

Codevelopment of SiP and SoC

With the rapid development of electronic technology, IC continues to develop in

three directions: (1) the feature size of IC chips continues to shrink; (2) a large
number of different requirements put forward demand on various types of IC chips;
(3) the third direction is the system integration technology for miniaturization.
Therefore, it appears that IC technology will continue in development of More
Moore’s law toward the integration of system-on-chip (SoC); on the other hand,
more types and functions will be integrated through system-in-package (SiP) as
more-than-Moore.
SoC and SIP are two effective system integration solutions. They have their
respective advantages and disadvantages, and also their own specific applications.
They provide a new way to continuously improve the performance, power con-
sumption, cost, and size of electronic systems. As the size of semiconductor devices
continues to shrink, SoC will face severe challenges (e.g., process fluctuation,
lithography cost increase, device performance deterioration, device power consump-
tion increase, etc.). Due to different process, it is very difficult for SoC chips to
integrate analog, radio frequency, digital, and even optoelectronics functions
together, and the integration of antenna, MEMS, and other micromechanical struc-
tures is even more difficult. Moreover, the cost of SoC chips is higher than the sum of
discrete devices with different functions. Therefore, SiP technology has been
attracted increasing attention by the industry. SiP technology is developed based
on SoC technology. It is flexible and easy to expand. It is an effective supplement to
SoC technology and will not replace SoC technology. Taking optoelectronics inte-
gration technology as an example, due to the limitation of the current development
level of optoelectronics technology and manufacturing technology, to achieve high-
performance monolithic integration, there are still many technical difficulties to
solve. The hybrid integration has tremendous advantages in design, processing,
and performance. The maturity and progress of photonic IC (PIC) and electronic
IC technology (EIC) have promoted the SiP as the key technology of optical
components and modules. With the increase of communication capacity and the
upgrade of network, the bandwidth and power consumption are extremely important,
which further promotes the progress of key technologies (e.g., bandwidth, power
consumption, manufacturing processes, and integration methods for PIC and EIC
chips) in order to meet the requirements of optical components, modules, and
systems. Figure 58.8 shows the integration of SoC and various SiP technologies.
The adoption of new principles and methods, the codesign of hardware and
software, the improvement of manufacturing process level, and process compatibil-
ity, result in rapid development of SoC. The implementation of high-performance
SiP packages also needs high demand for pin layout, physical size, material system,
and KGD (Known Good Die) of SoC chips. With the development of manufacturing
58 Design Technologies for Advanced Packaging 1151

Fig. 58.8 Integration of SoC

and SiP technology

equipment, new materials and packaging technology, the application of SiP tech-
nology will be extended to the heterogeneous integration based on highly compli-
cated SoC chips. In the process of SiP packaging, based on SoC chips, many new
packaging structure and technologies have been proposed with new challenges on
design, material, process, testing, and other aspects. It requires collaborative design,
cooptimization, and common development on signal integrity, thermal management,
reliability, testing, and interconnection manufacturing technology between SoC
and SIP.

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understanding/
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drive the design process from suitability to low cost. Int. J. Interact. Des. Manuf. (IJIDeM) (16),
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Press, 2001)
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siemens.com/valor-dfm-solutions/2022/05/11/proactive-design-for-test-dft-best-practices/
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Integrated Circuit Testing Technology
59
Zhiyong Zhang, Jianhua Qi, Kun Yu, and Qin Wang

Contents
Definition of IC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
Digital IC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156
Analog IC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158
Mixed-Signal IC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
Memory IC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
High Speed IC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
RF IC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
Programmable Device Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
SoC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
IoT/MEMS Chip Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Optimization of Testing Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Common Fault Model for Digital Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Common Fault Model for Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Design-for-Testability (DFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Management of Testing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
Test Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183

Abstract
Integrated circuit testing is continuously improved by the evolution of design,
manufacturing, packaging, and new applications. Testing not only contributes to
design verification, but also is an important means for defect screening. It is an
important constituent throughout the life cycle of ICs. This chapter focuses on the
test definition, fault model, digital signal, analog signal, mixed signal, and other

Z. Zhang · J. Qi (*) · K. Yu
Sino IC Technology Co., Ltd., Shanghai, China
e-mail: qjhhl@sinoictest.com.cn
Q. Wang
Shanghai Jiao Tong University, Shanghai, China

© Publishing House of Electronics Industry 2024 1153

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_59
1154 Z. Zhang et al.

different fields of testing. Meanwhile, the testing cost and data analysis involved
in mass production are also explained.

Keywords
Test definition · Test instructions · Fault model · Design for test · Test platform

Definition of IC Testing

In the post-Moore era, the complete testing solution of on-chip and off-chip testing is
becoming more complicated because of new design trends (e.g., safe and reliable
hardware-software co-design, redundant components, fault tolerant architectures and
protocols, and the integration of optical-mechanical-electrical devices). The
roadmap of advanced IC manufacturing process has led to the evolution of IC failure
test models. In addition, advanced packaging technologies (e.g., chip-scale-package
(CSP), wafer-level-package (WLP), through-Si-via (TSV), and 3D IC, etc.) bring
new test procedures and complex optical-mechanical-electrical integration failure
mechanisms leading to increasingly complicated IC testing. The emergence of new
applications such as the Internet, Internet-of-Things (IoT), Cloud computing, and big
data constantly promotes continuous development of IC test technology and
informationization [1].
As a critical step of verifying the functionality of IC products and analyzing the
performance parameters, testing is not only part of the design process but also part of
manufacturing. The primary function of the test is to detect whether there are
problems in the circuits, where the problems occur, and how to correct the problems.
If an IC fails at the test, the reasons may be the testing itself, product design, and/or
manufacturing process, etc. The testing technology is to develop suitable test plans
while considering both quality and economy, that is, to detect most errors at the
lowest cost.
Testing runs through the whole IC production lifecycle and can target design
verification, detection and screening, quality control, etc. Figure 59.1 shows the
main test sections in IC industry chain, where the parts with solid line frame are the
testing steps. The field of testing technology includes design for testing (DFT) and
design verification from the design stage, wafer acceptance test (WAT) and wafer test
from the manufacturing stage, final test, and failure analysis (FA). (1) Characteriza-
tion testing performs a comprehensive functional performance test on the function-
ality, DC and AC characteristics, to characterize the various limit parameters of the
IC and verify the correctness of the design. (2) Wafer sort performed on wafers after
the IC manufactured. It serves the purpose for screening the qualified circuits
(or chips) at the initial stage. With the requirements of wafer level packaging
(WLP), 3D heterogeneous integration, test mode evolution, and circuit trimming
customization, wafer level test has become more challenging. (3) Final test is a post-
package test to detect whether the circuits meet specifications. Sometimes the system
59 Integrated Circuit Testing Technology 1155

Fig. 59.1 The main test sections in IC industry chain

Fig. 59.2 Test basic

principle

level test is also included. The tests with higher cost are usually performed at this
stage to prevent unqualified products from entering into the final applications.
A basic block diagram of test principle is shown in Fig. 59.2, which applies a
certain stimulus to the circuit under test and observes the response of the circuit, then
compares it with the expected value. If the output is consistent with the expected
value, then the circuit functions properly. Otherwise, the circuit is faulty. Therefore,
the performance accuracy of the test platform, interface performance of hardware
and software, test stimulus generation, test response capture, data analysis and
processing, error compensation and calibration, and overall test plan formulation,
etc., are all closely related to the test implementation effect.
From the definition of the test plans, testing can be divided into the on-chip test or
design-for-testability (DFT), and off-chip test. The main purpose of the continuous
DFT design technology research in the industry is to improve fault observability,
reduce the performance requirements of external test instruments, and reduce test
time to achieve a balance between test quality and cost. However, the on-chip test
circuit is still imperfect especially for analog/radio frequency (RF) circuits; thus, the
1156 Z. Zhang et al.

off-chip test technology is important and not to be ignored. According to the type of
device under test (DUT), tests can be classified into digital IC and analog IC testing,
mixed-signal IC testing, high-speed signal IC testing, RF IC testing, programmable
device testing, memory IC testing, system on chip (SoC) test, IoT chip/MEMS chip
test, etc.

Digital IC Testing

Digital IC is the circuit where the signals must be discrete digital signals that are
interpreted as either 0 or 1 [2]. Digital IC test mainly includes DC test, AC test,
function test, and design for testability (DFT). The typical test procedure is in
Fig. 59.3. At the beginning of the test, it is necessary to verify that the IC under
test and the test system have good connectivity to eliminate the impact of poor
contacts. Then perform the function test to verify whether the IC has the expected
logic function or not. After that, the DC parameter test performs voltage or current
test on the measured pin. If the IC under test passes all these tests, then the
performance of the IC is proper. The last step is AC parameter test, which measures
the time-series relationship when the IC state is in switching to ensure that the state
transition occurs at the correct time [3]. DFT generates the test algorithm mainly
based on the fault model with test structure designed inside the circuit. During the

Fig. 59.3 A typical test

procedure of digital IC
59 Integrated Circuit Testing Technology 1157

test process, the changes of signal states of input pins and internal nodes caused by
the internal structure will both affect the signal states of the output pin. DFT mostly
adopts scan chains (SCAN) design and Built-In Self-Test design (BIST).

1. Contact test. The contact test mainly uses force-current-measure-voltage (FIMV)

to verify the contact between all test pins and the power/ground, as well as the test
system, test load board, test socket to ensure the contact on the entire test path is
good, and no short or open.
2. Functional tests usually perform by applying specific test patterns consisting of
level, timing, and waveform. When functional tests are in operation, the power
supply voltage, input and output voltages, output current load, and output sam-
pling are checked. The applied test patterns need to be at the rate specified by the
circuit test specification, and then the output pins of the circuit in each cycle need
to be checked. If any pin’s logic state, voltage, and timing do not match the
specification of the test pattern, then the circuit fails the functional test. Other-
wise, the IC passes the functional test. Functional tests usually include test pattern
generation, test pattern driving, and test result verification. The functional test
diagram is in Fig. 59.4.
3. DC parameters include input high/low current (IIH/IIL), input high/low voltage
(VIH/VIL), output high/low voltage (VOH/VOL), output short circuit current
(Ios), static current (Istatic), and dynamic current (Idynamic). Tests usually use
hardware resources of the test system such as precision measurement unit
(PMU) or device power supply (DPS), and are mainly performed using force-
voltage- measure-current (FVMI) or force-current-measure-voltage (FIMV).
Some parameters are also tested with force-voltage-measure-voltage (FVMV)
and force-current-measure-current (FIMI) modes. During testing, if the test
current is large, then Kelvin connection is useful for eliminating the voltage
drop on the line. For the voltage or current test of the output pin that is in certain
state of high or low, it is necessary to start with applying a test pattern so that the
measured pin of the circuit is in the expected high and low state, and then perform

Fig. 59.4 The functional test diagram

1158 Z. Zhang et al.

the measurement. With technology continuous in advancement, current main-

stream digital signal test system includes an PMU in each digital channel, for
parallel testing DC parameters of multiple pins.
4. AC parameters including frequency, rise/fall time, propagation delay, and setup/
hold time are measured by scanning through the method of changing the timing
edge of the test pattern in the functional test or directly using the time measure-
ment unit (TMU) of the test system. The accuracy of the test resources determines
the test accuracy.

The mainstream digital IC test system can test more than 7000 digital pins, with
the test rate reaching Gbps level and above, and the time edge accuracy reaching
100 ps and below. As the scale of digital IC testing is continuously in expansion, new
test technologies need to improve test efficiency with highly concurrent testing.

Analog IC Testing

Analog ICs include operational amplifiers (OA), filters, power management circuits
(PMC), analog switches, phase locked loops (PLL), RF front-ends, etc. Typical
parameters include leakage current, reference voltage, impedance, gain, sensitivity,
ripple reduction, frequency or phase response, harmonics, intermodulation distor-
tion, crosstalk, signal-to-noise ratio, noise figure, etc. Compared with digital IC,
there are fewer transistors in analog IC, and the parameters vary continuously over a
range of values. Because of the lack of a good fault model, there is no detachable
sub-circuit in the analog circuits. The test setup of pins, interface impedance, and
noises may cause errors in measurement. Such factors make analog signal testing
more difficult than digital testing.
Figure 59.5 is a basic principle diagram of the traditional test method. It is mainly
based on the functional test method, this method does not require a fault model and is
easy to handle. In terms of structural testing, because the analog circuits lack good
fault models and the mapping of structural simulation faults and functions is not
ideal, the structural test methods have not been widely applied in analog IC testing
even after years of research.
The traditional test methods have problems of using too many parameters, long
test time, difficulty in synchronizing stimulus and response, and complicated noise
processing. As technology advances and hardware/software costs decrease, a digital
signal processing (DSP)-based functional test method can be applied. Figure 59.6 is
a modern DSP-based analog test architecture diagram with core parts of arbitrary
waveform generators, waveform digitizers, and digital signal processors (DSP).
The DSP-based test method digitizes the analog signal as much as possible, and
greatly reduces the instrument crosstalk, noise, and drift. Meanwhile, multiple digital
sampling provides a better test solution by improving test accuracy and the repeat-
ability. However, if test parameters were not diverse, DSP-based test would have
59 Integrated Circuit Testing Technology 1159

Fig. 59.5 Function-based testing method for analog circuits

Fig. 59.6 Test method of analog IC based on DSP

higher cost than traditional test solutions. Since the analog IC DFT and BIST design
are lagging behind, the industry continues to study the fault-model-based test
method. IEEE 1149.4 is a boundary scan method for analog IC expansion, but
there is still no recognized solution for analog signal performance test. More research
effort is in need for relieving the requirement of high-performance complex analog
automatic test equipment (ATE) in the analog signal BIST field.
1160 Z. Zhang et al.

Mixed-Signal IC Testing

Mixed-signal ICs are circuits that include digital and analog circuit modules.
A circuit that converts digital signal into analog signal is called a digital-to-analog
converter (D/A or DAC), and a circuit that converts analog signal into digital signal
is called an analog-to-digital converter (A/D or ADC) [4]. Figure 59.7 shows how
the ADC/DAC works. With the continuous development of the IC industry, the
commercial ADC/DAC rate reaches tens of Gbps and the resolution (represented by
the number of bits) reaches 32bits. The function of the A/D converter is to convert
time-continuous, amplitude-continuous analog into digital signals with discrete time
and amplitudes, the function of D/A converter is just in opposite [5]. Sampling is the
process of converting a continuous (i.e., analog) signal into a discrete (i.e., digital)
signal. Conversely, reconstruction is the process of transforming discrete signals into
continuous signals [6]. Sampling and reconstruction have been widely used in
mixed-signal IC testing. In theory, to perform the sampling according to the sam-
pling theorem, the sampling frequency must be two times higher than the frequency
of the signal; but in the actual tests, over-sampling and under-sampling are some-
times applied. Testing based on digital signal processing (DSP) involves two types
of sampling: coherent sampling and non-coherent sampling. Coherent sampling is
required to satisfy Fs/Ft ¼ N/M, where Fs is the sampling frequency, Ft is the signal
frequency, N is the number of sampling points, and M is the number of sampling
periods. In addition, M and N should be both integers and relatively prime with each
other, which can avoid repeated sampling and improve efficiency [7]. Non-coherent
sampling for periodic signals is more likely to cause spectral leakage.
The mixed-signal IC testing includes DC and AC parameters (e.g., power con-
sumption, leakage, power supply rejection-ratio (PSRR), settling time, etc.). Static
and dynamic parameters tested are mainly for characterizing the transmission of
mixed-signal ICs. The ADC test diagram is in Fig. 59.8.

Fig. 59.7 ADC/DAC

principle diagram
59 Integrated Circuit Testing Technology 1161

Fig. 59.8 The ADC test diagram

During the test, the test system provides power supply, clock signal, analog
signal, and digital control signals to the IC under test. (1) The static test parameters
usually based on a full-code linear test include full-scale range (FSR), least signif-
icant bit (LSB), and differential non-linearity (DNL), integral non-linearity (INL),
offset error, gain error, and missing codes, etc. These parameters are determined by
inputting a full-scale triangular wave (with a low signal frequency) sampling the
actual output signal, and then making a comparison of the measured transmission
characteristics with the ideal characteristics. Static parameter test can also be deter-
mined by inputting a sine wave and using a histogram method. (2) In dynamic
parameters test, waveform generators are used to generate test waveforms of a
certain frequency. The generated waveforms applied to the circuit as input are
usually sine waves, and the accuracy of the input waveforms must be much higher
than the accuracy of the circuit. The output time-domain signal is sampled, and then
the sampled time-domain signal is transformed into a frequency-domain signal for
processing using fast-Fourier-transform (FFT). The dynamic parameters of the
mixed signal IC can be derived by analyzing the transformed signals. Dynamic
parameters include signal-to-noise ratio (SNR), total harmonic distortion (THD),
effective number of bits (ENOB), spurious free dynamic range (SFDR), signal to
noise and distortion (SINAD), intermodulation distortion (IMD), etc. In an ideal
converter, SINAD and SNR are the same. If SNR is the ideal state that the converter
can achieve, SINAD can reflect the actual performance parameters of the converter.
The closer SINAD to SNR is, the better the performance [8]. ENOB is calculated
based on signal-to-noise ratio, ENOB ¼ (SINAD-1.76)/6.02.
When testing mixed-signal IC, it also needs to consider the design of testability
and the connection between design and test, and to provide the software and
hardware environment required for the test. The mixed-signal IC test system needs
the capability of a digital IC test system. In addition, it should be able to generate
arbitrary high-accuracy waveform, capture and process both digital and analog
signal, and the digital module should be able to synchronize with the analog module.
1162 Z. Zhang et al.

Since the automatic test system cannot provide high-precision clocks and signal
sources that meet the testing requirements of the high-speed and high-precision
ADC/DAC, high-quality discrete instruments or loopback tests can be used. For
the test load board, it is necessary to ensure that the power supply and ground are
clean during the design process, pay special attention to the key signal routing (e.g.,
clock and high-speed high-precision signal, and the signal filtered sufficiently). The
new standard IEEE boundary scan method, as fully useable for mixed-signal testing,
can greatly reduce the difficulty and cost of the mixed-signal IC testing.

Memory IC Testing

Memory is a general-purpose device in the field of IC with large requirements from

the market. Memory devices can be classified into ROM, EPROM, E2PROM,
SRAM, DRAM, FLASH, etc. Semiconductor memories have extremely complex
high-density structures and high-precision timing simulation functions. Once the
memory design and the fault models are determined, proper strategies and test modes
can be designed. Memory failures are permanent or temporary as in Table 59.1,
listing some typical functional faults (e.g., stuck-at-faults, transition faults, coupling
faults, and neighborhood pattern sensitive faults). Table 59.2 illustrates commonly
used memory test patterns and fault models for meeting the needs of general memory
testing.
A separate semiconductor memory can be tested with a memory-specific test
system, which typically includes an algorithmic pattern generator (APG) with arith-
metic logic unit (ALU) for real time processing address operations and generating test
patterns according to an algorithm. Figure 59.9 identifies the 3 parts of the basic
architecture of semiconductor memory testing equipment: the address generator, data
generator, and controller core. The BIST solution is typically for embedded memories
because they are not easy to test directly. The memory BIST structure enables the
memory to generate stimulus, compare data, and compress data. A built-in redundancy
analysis (BIRA) or a built-in self-repair (BISR) is usually in the BIST structure with
capability of storing test results and performing on-chip redundancy repair. Due to the
increasing capacity of semiconductor memory and the long test time, the testing cost

Table 59.1 Memory functional faults list

No. Functional faults No. Functional faults
1 Cell stuck-at-fault 9 Address line stuck-at-fault
2 Driver stuck-at-fault 10 Address line open fault
3 Read/write stuck-at-fault 11 Short circuit between address lines
4 Chip select stuck-at-fault 12 Decoder open fault
5 Data line stuck-at-fault 13 Wrong address access
6 Data line open fault 14 Multiple simultaneous address access
7 Short circuit between data lines 15 Cell is forced to 0, but not set to 1 (or opposite)
8 Crosstalk between data lines 16 Pattern sensitization cell interaction
59 Integrated Circuit Testing Technology 1163

Table 59.2 Memory test patterns and fault models

Stuck-at- Transition Address Coupling
Test pattern faults faults faults faults
Checkerboard ● ●
algorithm
a
March algorithm ● ● ●
b
March C-algorithm ● ●
c
MATTS++ algorithm ● ● ●
Walk 0/1 ● ● ● ●
Ping pong ● ● ● ●
Butterfly algorithm ● ● ● ●
Diagonal algorithm ● ●
Shift invert ● ● ● ●
Address complement ●
Note:
a
March algorithm: One of the test algorithms often used in memory, ideal for “read-modify-write”
timing
b
March C-Algorithm: An improved March algorithm
c
MATTS++ algorithm: An improved March algorithm

Fig. 59.9 Basic architecture

of semiconductor memory
testing equipment

has been increasingly higher. In addition to the BIST internal full-speed test solution,
the current off-chip test solution is mainly based on parallel testing. According to
International Technology Roadmap for Semiconductor (ITRS) recent report, there are
more than 256 workstations that can be used for parallel testing DRAM and FLASH
memory and greatly reduce the testing cost. In future, memory testing requires new
fault models, advanced BIST schemes, and test patterns for quality and yield.

High Speed IC Testing

With the development of IC technology, high-speed signal design specifications are

constantly updated. As the data transmission rate in the system has increased to tens
or even hundreds of Gbps, high-speed or ultra-high-speed signals present challenges
and difficulties of test systems, hardware design, and signal integrity. The general
scheme adopted in China is to use a complete system for evaluating the performance
1164 Z. Zhang et al.

of high-speed interface circuits (e.g., by testing and analyzing the error rate); but the
test efficiency is low and there is no systematic and comprehensive evaluation for the
power/voltage level, timing characteristics, and reliability. An efficient and system-
atic test evaluation solution is to use automatic test equipment (ATE). With high-
quality resources, high-end automatic test equipment, and the development of
hardware design technology and test algorithms, the quality of high-speed signal
test transmission and intelligent and comprehensive test to high-speed signal chips
can be achieved. A typical high-speed signal transmission process from ATE to the
device under test (DUT) is shown in Fig. 59.10.
Usually, the parameters for testing high-speed signals include key performance
indicators (e.g., bit error rate (BER), eye diagram, voltage swing, common mode
voltage, output skew, and jitter). A complete scheme for testing and evaluating the
characteristics of high-speed serial data transmission interface can include the
following: (1) Voltage level parameters (e.g., range of common-mode and
differential-mode inputs, common-mode output, pre-emphasis and de-emphasis
levels, and interface leakage). (2) Time characteristic parameters (e.g., the frequency
range of high-speed signal, the rise and fall times of output signals, and transmission
and reception delays). (3) Characteristic parameters of transmission reliability (e.g.,
local clock jitter tolerance, jitter tolerance of high speed serial signal input, and jitter
amplitude of high speed serial signal output).
During high-speed signal test, in order to tackle the challenges of testing the low
voltage differential signals (LVDS), two differential channels of the automatic test
system are connected to the transmitting (or receiving) channel of the chip, and a
100 ohm resistor is designed as a terminal near the chip for testing LVDS as shown in
Fig. 59.11. The driving level of the mainstream high-speed signal IC test system has
a precision of 10 mV, and the minimum overdrive level of the comparator is 50 mV,
which can meet the requirements of LVDS high-speed small signal test. However,
the next generation ultra-high-speed signals will bring more challenges in testing,
and it is necessary to develop more flexible and reliable test solutions (e.g., new

Fig. 59.10 A typical high-speed signal transmission process

59 Integrated Circuit Testing Technology 1165

Fig. 59.11 A typical LVDS transmitter chip test scheme

waveform and system design simulation, spectrum and signal analysis, optical
communication, and high-speed testing) to obtain accurate and stable testing results.

RF IC Testing

High-frequency electromagnetic waves with long-distance transmission capability

are called RF signals. In the broad sense, RF includes the frequency band from
300 kHz to 300GHz [9]. The RF IC includes various functional circuits (e.g., low
noise amplifier (LNA), power amplifier (PA), Mixer, PLL, Switch, RF front-end,
modulator/demodulator, etc.). Powerful RF ICs can even integrate signal encoding
and decoding, data processing, control, and other functions, and are widely used in
3G/4G/5G, WLAN, GPS, and Bluetooth devices [10]. Figure 59.12 shows a typical
RF receiver circuit architecture.
Because the analysis method of the distributed parameter circuits is needed for
analyzing RF ICs, the microwave network method is usually used. The most
important parameter of the microwave network is the S parameters based on the
relationship between the incident wave and reflected wave. The S parameters can
evaluate the performance of reflected and transmitted signals [11]. Take the 2-port
network as an example; there are four S parameters (i.e., S11, S12, S21, and S22) as
shown in Fig. 59.13. From the perspective of signal propagation, the propagation of
an electrical signal is the propagation of the electromagnetic field in a wire.
According to the transmission line theory, if an obstacle is encountered (such as a
change in impedance), the signal will be reflected. Return loss is a parameter
indicating the signal reflection performance [12]. In actual tests, the signal is
transmitted with maximum power, minimum loss and reflection, where all the RF
signal paths must meet the requirements of impedance matching. When designing
actual hardware for testing, the RF signals on the board are usually connected by a
micro-strip line of 50ohm characteristic impedance. The RF port of the circuit board
1166 Z. Zhang et al.

Fig. 59.12 Typical RF receiver circuit architecture

Fig. 59.13 S-parameters

adopts a coaxial connector, and then the coaxial cable is used to connect to the RF
port of the test resource. Before testing, it is necessary to remove the loss by
calibration, where the loss is caused by the test equipment and connection lines.
In addition to DC and functional parameters, RF IC test parameters include S
parameters, power, gain, gain flatness, 1 dB compression point (P1dB), 3rd-order
intercept point (IP3), adjacent channel power ratio (ACPR), noise fig. (NF), phase
noise (PN), error vector magnitude (EVM), etc. These parameters mainly verify the
output power and linearity operating range of the RF ICs, the influence of noise, and
the amplitude and phase error of the modulated signals. RF IC testing is generally
performed in the frequency domain, where either its power is directly collected at a
specific frequency (the unit is decibel-milliwatt (dBm)), or the ratio of power at
certain frequencies is collected, (the unit is decibel (dB)). During testing, the power
module of the test system supplies power, the digital module provides a logic control
signal, and the RF source of the RF module provides test stimulus including
continuous wave (CW) signal, modulated signal, and multi-toned signal. The RF
receiver collects and analyzes the output of the IC under test. The RF receiver is
59 Integrated Circuit Testing Technology 1167

Fig. 59.14 The RF IC test

block diagram

required to have good dynamic range and noise floor. The combination of multiple
discrete instruments including signal sources, spectrum analyzers, or power ana-
lyzers can also be used for testing. The test diagram is shown in Fig. 59.14.
Future RF IC technology mainly requires wider working bandwidth, larger linear
range, higher frequency, more ports, lower noise, smaller size, and lower cost. As a
result, it is necessary to improve test system capabilities, increase test hardware
performance, and optimize test algorithms. As mixed-signal IC, more and more
experts are studying the testing of RF ICs for alternative approaches.

Programmable Device Testing

Programmable Logic Device (PLD) is a kind of new logic device that users can
program to realize certain logic functions. These devices are typically composed of
programmable AND, OR, and gate arrays; and they can be programmed to realize
certain logic functions. Programmable logic devices can be divided into simple and
complex PLDs according to their integration level. (1) Simple PLDs include pro-
grammable read only memory (PROM), programmable logic array (PLA), program-
mable array logic (PAL), and general array logic (GAL). (2) Complex PLD include
erasable PLD (EPLD), complex programmable logic device (CPLD), field program-
mable gate array (FPGA), etc.
With the development of programmable devices, CPU, DSP, ADC/DAC, mem-
ory, and other devices can be integrated into one programmable device to form a
system-on-programmable-chip (SoPC) as shown in Fig. 59.15. Testing a program-
mable device requires structural analysis of its resources, programming the device to
a circuit with a specific function through a test configuration (TC), and then testing
the functionality and parameters of the circuit through a pattern implementation
(TS) process. Programming of programmable device varies according to the tech-
nology of programmable logic cell (e.g., fuses, anti-fuse, erasable programmable
read-only memory (EPROM), electrically erasable programmable read-only mem-
ory (E2PROM), static random access memory (SRAM), and flash memory). Com-
monly used test programming methods include in-system programmable (ISP), joint
1168 Z. Zhang et al.

Fig. 59.15 A system-on-

programmable-chip (SoPC)

Fig. 59.16 Illustration of three-state ISP state machine

test action group (JTAG) protocol programming, serial peripheral interface (SPI)
programming, master mode, and slave mode programming.
In-system programming (ISP) technology is an advanced programming technique
proposed by Lattice in the 1980s and is widely used for programmable devices (e.g.,
PROM, CPLD, and FPGA). There are 2 types of ISP finite state machine transition
diagrams: the 3-state ISP state machine (as in Fig. 59.16) and the IEEE 1149.1
standard JTAG state machine (as in Fig. 59.17). There are several modes for FPGA
programming (e.g., master serial, slave serial, master parallel, slave parallel, and
JTAG modes). Different configuration modes can be selected by setting the status of
the 3 mode control pins. In order to improve the test efficiency, the test configuration
of the FPGA with the automatic test system usually selects the master parallel and
slave parallel modes.
There are several test methods for different types of programmable devices,
including in-system rapid configuration test, DFT test, built-in self-test (BIST),
scan test (SCAN), cascading functional test, black box–based test, dynamic
reconfigurable test, custom software test, adaptive test, and test methods based on
board-level application. With the development of testing technology, some new
testing methods are constantly coming out. To achieve higher test coverage, combi-
national methods are needed. The first step of programmable device test develop-
ment is to develop a configuration code. The configuration code can be developed in
the corresponding development environment (e.g., ISE from Xilinx, Quartus from
59 Integrated Circuit Testing Technology 1169

Fig. 59.17 Illustration of IEEE 1149.1 standard JTAG state machine

Altera, ispLEVER from Lattice, Libero SoC from Actel, Warp from Cypress, etc.).
These tools can generate download code in .bit, .rbt, .Bin, .svf, and other formats,
and then make an appropriate conversion according to the test requirements to
generate the configuration code. With the test system, the programmable device
can be configurable to form a circuit with certain functionality, and the test code can
be loaded to test the functionality and parameters of the circuit. The test process is
shown in Fig. 59.18.

SoC Testing

System-on-chip (SOC) integrates various cores or IPs (e.g. logic circuits, memories,
mix-signal circuits, etc.) into a single chip. It has the advantages of high integration,
high speed, small size, low cost, and low power consumption. System-in package
(SiP) differs from SoC in that dies can be tiled or stacked in SiP, while SoC
integrated multiple functional circuit modules on a single IC chip. Network-on-
1170 Z. Zhang et al.

Fig. 59.18 Illustration of programmable device test process

chip (NoC) is a system-level chip, where a large amount of computing resources and
the communication network used to connect these resources are integrated onto a
single IC chip. It leverages packet routing mechanisms to resolve problems such as
global clock synchronization. The system chip design is based on embedded cores.
Since SoC exploits the reuse of cores, the key challenge of SoC testing is how to
reuse the core tests. In addition, SoC integrates cores of different sources, different
types, and different design cores. Therefore, the test also needs to solve problems
59 Integrated Circuit Testing Technology 1171

Fig. 59.19 SoC test access mechanism

(e.g., how to efficiently transfer test data between input and output and how to
address the heterogeneity of embedded cores). Using the core test as a basis,
interconnections of cores and system-level test should be completed at the same
time. Figure 59.19 introduces the mechanism for testing the embedded core of an
SoC, where the core under test is accessed through the test shell.
In order to solve the core-based test problems, specifications and standards of
SoC test isolation, access, control, and observation should be established. IEEE has
developed a series of standards such as IEEE1149, IEEE1500, and IEEE1450 for
this purpose. (1) Since the publication of IEEE 1149.1 in 1990, boundary-scan
technology has been widely accepted. The scan chain integrates access terminals
for logic test into the circuit, providing accesses of controllability and observability
through scanning, which simplifies the access terminals of the circuit physical test.
On this basis, JTAG also introduced IEEE 1149.4 for mixed-signal circuits, and
IEEE 1149.7 reduced the number of test pins and other standards. (2) The IEEE 1450
standard is designed to provide a common graphical description language of test
patterns, which can be used without conversion on EDA simulation tools and ATE,
and establish a seamless connectivity between EDA and ATE. IEEE P1450.1 pro-
poses the standard test interface language, which will replace the value change dump
(VCD) and waveform generation language (WGL) waveform files generated from
traditional EDA simulation tools. (3) The IEEE 1500 is a scalable standard archi-
tecture for test case reuse and test integration of embedded cores and peripherals.
The IEEE 1500 features serial and parallel test access mechanisms (TAM) as well as
a rich instruction set to fulfill the test requirements of SoC core, interconnect, and
system. In addition, IEEE 1500 defines features that support kernel isolation and
protection, reducing test costs by (a) improving the automatic conversion efficiency
of design files, (b) facilitating design for testing (DFT) techniques, and (c) improving
1172 Z. Zhang et al.

Fig. 59.20 IEEE1500 core structure

the quality of SoC tests by refining access mechanisms. As shown in Fig. 59.20, for a
system with N cores, the overall architecture conforms to IEEE1500, including test
source (TAM source), test sink (TAM sink), test access mechanism (TAM), 1500
shell, shell I/O ports, etc.
The IEEE standards can effectively solve the problems of implementing tests for
SoC. Another issue with SoC testing is the cost. An effective way to reduce the cost of
testing a system chip is to reduce test time with concurrent testing, test scheduling, or test
compression. The concurrent test reduces the test time to the longest single path time by
simultaneously testing multiple function modules in the SoC. Test scheduling achieves
multi-core testing, reduces bus redundancy time, and avoids test conflicts by properly
distributing test sets and test access mechanisms for embedded cores. The increasing
level of integration and complexity of system chips, as well as the requirements of high
fault coverage, have led to an increase in test data. Test compression achieves the effects
of reducing memory channel data, low power test, and reducing test time by designing
compression method and test strategy that can optimize test stimulus response. Fig-
ure 59.21 shows the goals and methods of test optimization. The test methods of SiP
chip and network-on chip (NOC) are basically similar to the SoC test.

IoT/MEMS Chip Testing

The chips for Internet-of-Things (IoT) mainly include sensor chip, embedded pro-
cessing chips, RF chips, etc. The performance and functional evaluation of IoT chips
is crucial as an indispensable part of IoT. The IoT chips testing mainly analyzes
59 Integrated Circuit Testing Technology 1173

Fig. 59.21 Test optimization

methods and goals

transmission characteristics of the signal from device/module, circuit debugging,

power management, interconnection, and system level application as shown in
Fig. 59.22. IoT chips need to be tested and verified by a combination of methods,
including low power test, electromagnetic sensitivity test, stress test, high integration
and high precision system level test, reliability test, etc. With the development of
chip applications and test technology, new test methods are constantly being devel-
oped to improve test coverage.
The main challenges of IoT chip testing include low power, signal transmission
quality, and other aspects. Usually, the test is based on automatic test systems, where the
interfaces of test hardware are designed, and corresponding test software are developed
to complete low power test, electromagnetic sensitivity test, stress test, high integration
and high precision system level test, reliability test, and other indicator tests. Low power
tests evaluate several parameters including chip power, transient power, and peak power.
Electromagnetic sensitivity test includes functional electrostatic discharge test and
parameters including fast transient burst, electromagnetic sensitivity, and high frequency
electromagnetic compatibility. Stress test mainly includes performance tests under high-
voltage, high-frequency, high-temperature, strong electromagnetic interference, and
other strong stress conditions of multi-dimensional dynamics. In the test session, the
test process is used for tracking, test result analysis, backtracking, real-time display of
test results, and automatic generation of test reports. This improves test efficiency and
reduces product-to-market time.
As a micro-device or micro-system, the size of Micro-Electro-Mechanical Sys-
tems (MEMS) is only a few mm or even smaller. Considering the defects of the
manufacturing process and the cost, the performance and functional tests are
performed before packaging and application. The value of the test is to guide how
to improve the pass rate, and to measure and evaluate the performance and reliability
of MEMS chips. As a challenging part of the MEMS industry chain, the test solution
design and equipment environments for MEMS tests are different from traditional IC
tests. As shown in Fig. 59.23, MEMS chip testing is not only the input or output of
electrical signals, but also contains non-electrical test environments including pres-
sure, temperature, light, and electromagnetic. The content of the test includes
characteristic parameter tests of process, material, and structure, tests of dynamic
and static characteristics, weak signals, and small physical quantity tests, etc. The
parameters tested include performance parameters, for example, static/dynamic
characteristics analysis, sensitivity, linearity, quadrature error, and flow rate, as
well as electrical characteristics. Due to the complex MEMS test environment and
1174 Z. Zhang et al.

Fig. 59.22 IoT chip signal test

Fig. 59.23 MEMS test

numerous test items, it is necessary to integrate the MEMS test equipment into an
automated system and expand it into an open, universal test platform to improve test
reliability and stability. At present, the MEMS test system generates the stimulus
source by simulating the actual working environment of chips, and applies the
semiconductor automatic test system to test output signal of the chip. The test
parameters include test range and accuracy, resolution ratio, sensitivity, signal-to-
noise ratio, temperature drift and other parameters. The MEMS test can not only
provide customers with test data reports and analysis of product performance, but
also can track the product yield. Multi-station test, automatic test and failure analysis
and other functional software are used to improve product testing efficiency.

Optimization of Testing Cost

Depending on the product type and test requirements, the cost of testing accounts
for 10–30% of the total IC cost. The cost of testing includes operating costs,
equipment costs, hardware costs, and development costs. Operating costs include
59 Integrated Circuit Testing Technology 1175

relatively fixed costs (e.g., test plant costs, water and electricity consumption,
labor costs, etc.). Equipment costs refer to the cost of test machine, test software,
and equipment maintenance. Hardware costs include the cost of probe cards, load
boards, sockets, inks, and auxiliary materials. Development costs refer to the cost
of development and debugging of test programs, hardware, test pattern genera-
tion, and software tools. They are highly relevant to the product. In recent years,
the testability design has been added to the chip and the added cost can be
regarded as test cost.
As the level of integration and performance of IC products become higher and
higher, functions become more and more complex, test requirements continue to
increase, so the test cost will inevitably rise, resulting in a decline in product
competitiveness. How to provide cheap testing service with high quality and
continue to reduce cost of testing is a challenge. The following are a few common
ways to reduce the cost of testing. (1) Parallel testing: test cost and test time are
closely related; the longer the test time, the higher the test cost. As the test
equipment are becoming highly integrated, the test resources continue to
increase. As a result, more circuits are tested at the same time for improving
the test efficiency. The number of parallel tests increased from the past 2 and
4 stations to 256 stations to 512 stations, and the number of parallel memory test
stations is more than 2000. Parallel testing will not be in a stagnant state.
(2) Segmentation test: The high integration level of the system chip and the
built-in multi-modules greatly increase the difficulty of testing. It is difficult to
reduce the cost of testing system chips by large-scale parallel testing, because
such chips have large size and complexity. The test can be divided into multiple
modules with each test module at a relatively low cost. A typical example is the
testing of embedded high-capacity memory. The memory portion can be firstly
tested by the memory-specific test equipment with parallel testing for 128 sites or
higher. Then the general test equipment is used for testing other functions and
parameters; the total testing cost is significantly reduced. (3) Design-for-testabil-
ity (DFT): DFT mainly solves the problems of low fault coverage, long test
development cycle and long test time, which simplifies complex tests, reduces
the requirements on test equipment, and improves test efficiency. DFT mainly
includes scan design, built-in self-test (BIST), etc., and has been widely used in
IC product testing. (4) Concurrent test: The structure of IC is increasingly
complex. In particular, a large number of functional modules are integrated inside
the system chip. The traditional test schemes test each module in turn through a
serial method, so the test time is long. With independent test resources, capability
of back-end data processing, and support for multiple time control, the new test
equipment supports concurrent test of multiple modules. Concurrently testing
digital, analog, RF, high-speed, memory, and other module implementations at
the same time can significantly reduce testing time.
With the continuous development of technology, a general trend is that the
performance of electronic products continues to increase while the price con-
tinues to reduce. How to maintain competitive prices is a long-term theme of test
cost control.
1176 Z. Zhang et al.

Fault Models

Fault model is to build models that can simulate physical defects in the chip
manufacturing process as the basis of chip testing. The fault model [13] is used in
combination with EDA tools for fault simulation, automatic generation of test
pattern, pattern graphics verification, and to help diagnose faults. Once the circuit
design layout is complete, fault analysis can be performed to determine the location
and types of potential faults in the manufacturing process. Fault analysis considers
the logical properties of the circuits and the physical properties of layout, and makes
predictions based on historical data from past manufacturing process at the same
time. The result of the analysis is a fault list. Then the faults are sorted, usually
starting with the fault that is most likely to occur and the easiest to test, and ending
with the fault that is the least likely to occur and the hardest to test. To generate and
verify tests, a separate fault model is typically used to describe the circuit operating
state when there is a predicted fault. The fault simulator introduces a fault into the
design data, causing the circuit to behave as if there existed a target defect and then
developing a test to detect the fault behavior and verify its validity.

Common Fault Model for Digital Logic

(1) Stuck-at-fault: It is a type of fault where a certain signal in the IC is stuck at either
logic 0 or logic 1. The two cases are stuck-at-0 (SA0) and stuck-at-1 (SA1). It is the
most common fault model and used to characterize many different physical defects.
There are two types of stuck-at-faults: stuck-open and stuck-short faults. (2) Bridging
fault: A bridging fault considers two (or more) nodes unintentionally connected with
a low resistance. Bridging faults are generally classified into three categories:
non-feedback bridging faults between nodes, feedback-bridging faults between
nodes, and bridging faults between devices. (3) Transition delay fault: A transition
delay fault is a circuit fault where a signal cannot be stabilized to 0 from
1 (or stabilized to 1 from 0) within the specified time period. After a period, a trip
delay fault usually appears as a stuck at fault. (4) Path delay fault: A path delay fault
is different from transition delay fault, and refers to the transmission delay of the
signal on a specific path, especially the delay of the critical path.

Common Fault Model for Memories

(1) Cell stuck-at-fault: A cell stuck-at-fault means that the signal of the memory cell
is stuck at 0 or 1. (2) Transition fault (TF): A transition fault is a fault during state
transitions, which means that normal transitions do not occur when writing on a
memory cell. In order to detect this fault, each cell must be read and written in the
sequence of 0—>1 and 1—>0, and the value should be read immediately after
59 Integrated Circuit Testing Technology 1177

writing the opposite value. (3) Coupling fault (CF): The cell CF occurs mainly on
random-access memory (RAM), when writing to a cell and the transition happening,
the data of another cell is affected by this cell. Cell coupling may be an inversion
coupling fault (i.e., cell content inversion), a simple state coupling fault (i.e., cell
content changes only when there are specific data in other locations), and an
idempotent coupling fault (i.e., content of the cell changes only when the cell has
specific data). In order to test CF faults, after an odd number of transitions to a
connected unit, all cells should be read to avoid cell-coupling fault. (4) Neighbor
pattern sensitive faults: A neighborhood pattern sensitive fault is a special state-
coupling fault, that is, a data in a memory cell is affected by the data value in another
nearby memory cell. (5) Address decode fault: There may be one of the following
scenarios: one address can access to a cell, never access to a cell, or access to
multiple cells; or multiple addresses access to one cell. (6) Data retention fault:
A data retention fault is that the memory is not to hold data for a specified period.

Design-for-Testability (DFT)

Designers should consider the test requirements when designing ICs. By increasing
hardware overhead, the accessibility, observability, and controllability of internal
nodes can be improved, which makes it easier to test the circuit and reduce the cost of
testing. Such methodology is referred to as IC design for testability (DFT) [13]. DFT
requires trade-offs between chip area, I/O pins, chip performance, design cycle,
yield, and time cost. Scan is a commonly used method of design for testability in
digital circuits for built-in self-test (BIST) of memory and boundary scan test for
testing the board-level connection. (1) SCAN: Scan is the main technology of DFT.
The scan sequence is divided into 2 parts: shift and capture, to make sure that internal
nodes are controllable and observable. This is achieved by connecting the registers
into a long chain of shift registers. The basic element of the scan test structure is the
scan flip-flop. The most widely used types are the D-type flip-flops with a multi-
plexer and latches with a scan-end. (2) Memory built-in self-test (MBIST): The built-
in self-test approach of memory adds additional test circuits around the memory to
generate internal test patterns and compare the test results. The basic idea is that the
circuit itself generates test patterns and has an independent comparison structure to
determine whether the test results pass or not. Therefore, BIST requires additional
circuitry, including a pattern generator, a BIST controller, and a response analyzer as
shown in Fig. 59.24. (3) Boundary scan: It is a method of DFT, which allows the
testing of the inter-connections on the PCB and the ICs mounted on the PCB.
Boundary scan adds scan cells at the I/O ports of the circuit and connects them
into a serial scan path. This is different from internal scan, which uses a scan path as
connected by sequential cells with scan capability to replace common sequential
cells in the circuit. The principle is to add registers on I/Os of the core logic circuits
1178 Z. Zhang et al.

Fig. 59.24 Memory built-in self-test structure

Fig. 59.25 Logic built-in

self-test structure

and connect them so that data can be serially input to the cell under test and serially
read from the corresponding outputs. In order to address the problem of testing of the
inter-connections on the PCB and the ICs on the PCB, boundary scan was proposed
by the Joint Test Action Group (JTAG). Boundary scan was adopted by the IEEE in
1990 and became a standard, namely, IEEE1149.1. This standard specifies the test
I/O, structure, and operational instructions for boundary scan. (4) Microprocessor
DFT: For the DFT of Micro processing Unit (MPU)/Micro control Unit (MCU) and
DSP, the concept of isolation is added to the traditional tests in order to avoid the side
effects on the circuits. Isolation refers to separating the electrical I/O of the IP core
from the logic chip connecting these I/O. The IEEE P1500 standard defines the DFT
for embedded microprocessor cores, which mainly includes three parts: embedded
core test isolation, test access mechanism, and test control mechanism. (5) Logic
built-in self-test (BIST): In addition to scan-based DFT technology, logic BIST is the
59 Integrated Circuit Testing Technology 1179

development direction of DFT in designing highly integrated chips such as system-

on-chip (SoC). As shown in Fig. 59.25, the principle structure is mainly composed of
pseudo random pattern generation (PRPG), BIST controller, multiple input signature
register (MISR), and the scan path.
Modules or circuits using DFT technology include: (1) Microprocessors: Micro-
processors usually employ a custom test structure, typically a combination of parallel
pattern test and full-scan/partial-scan test. (2) Memories: The storage cell primarily
uses BIST, which provides a fast, easy-to-control test method. (3) Other digital
modules: The main choice is scan test technology. (4) Analog modules: The DFT of
analog circuits can be divided into 2 categories: accessible design methods and
reconfigurable design methods. The accessible design method is to insert test buses
or test nodes into the circuit under test to improve the controllability and observability
of the internal nodes. This is also the earliest test method for mixed-signal circuits. The
reconfigurable design method is still in the research stage. The main idea is to exploit
the re-configurability of the circuit under test to improve the testability.

Management of Testing Data

Only the ICs that have passed the test can be delivered to the customers or assembled
onto the final products. The standard for qualification is whether the ICs can pass all
the test items or not. The test data generated during the test is important for
evaluating and analyzing the functionality and performance of the circuits. The
test data mainly includes data log, yield summary, wafer map, and other files,
where the data log is usually in text (txt) format or standard test data format
(STDF). Modern test equipment supports outputting the data in text format. The
advantages of the text format are that it is readable by human using normal text
editors and does not require special software tools. However, the text format also has
several major disadvantages. Text files are often large in size. In addition, the data
generated by different test equipment have different formats, resulting in poor
compatibility, in-efficient statistical analysis, and difficult to integrate test data.
Furthermore, since the test data is stored sequentially in the file, it is very difficult
to extract and summarize for data analysis for design and applications. The industry
requires a common format for test data.
The standard test data format (STDF) was first proposed by Teradyne. It is
compact, easily compatible binary data format, which supports both Windows and
Unix platforms. Since data is stored in the file by index, querying data and generating
statistics become very convenient, and it is easy to interface with the previous and
subsequent processes. Currently, the mainstream test systems all support generating
test data files in STDF format. One disadvantage of STDF format is that it requires
special software tools for reading and editing. The versatility of STDF format test
data for design tools in the industry chain is shown in Fig. 59.26.
Wafer map is a graphical display of the test results of each wafer, where the test
results are represented with colors, numbers, or the combination of colors and
numbers. Its function is to display visually the distribution of qualified products on
1180 Z. Zhang et al.

Fig. 59.26 The versatility of

STDF format test data for
design tools in the industry
chain

Fig. 59.27 Illustration of a wafer map in Excel format

wafer with position information. The wafer map is called the inkless map for
packaging. Wafer maps are usually stored in image, excel, or text format. A wafer
map in excel format is shown in Fig. 59.27. The wafer map for packaging is usually
stored in text format, where the file contains product information (product name,
59 Integrated Circuit Testing Technology 1181

Fig. 59.28 Illustration of an

inkless map used for
packaging

batch number, chip number, notch direction, etc.) and graphics. Qualified/unquali-
fied products are represented by numbers or letters in the graphic. An inkless map
used for packaging is shown in Fig. 59.28. The test data is important for the IC
enterprises to analyze, predict, and trace back the products. The large amount of test
data (e.g., yield summary, wafer map, and other data) is regularly stored on test
equipment as well as uploaded to the cloud server for big-data analysis.

Test Platforms

The IC test platform is for medium testing (“medium” or “CP”) and final electrical
performance testing (“final test” or “FT”) in IC manufacturing processes as different
from the parametric test platform. While the parametric test reflects the suitability of
process control, the IC test platform is a system composed of a series of software and
hardware and integrates various testing functions (e.g., parametric test, data acqui-
sition, test result classification, data storage, and test data query). The IC devices can
be classified as qualified and unqualified by the test platform, and all the technical
parameters of each IC device can be extracted and saved.
1182 Z. Zhang et al.

Fig. 59.29 Test platform categories

The IC test platform can be categorized as test platforms for verification

analysis and for industrialization. As shown in Fig. 59.29, both of these two
categories of test platforms can be further divided into wafer-level and package-
level platforms. According to product size characteristics or test requirements, the
test platforms can be subdivided into 1200 wafer, 800 wafer, thin wafer, high
temperature, and low temperature test platforms, etc. The IC test platform empha-
sizes full-function testing, full-performance testing, full-coverage testing, fully
automated testing, and high-efficiency testing. The IC test platform usually
includes automatic test system (ATE), prober, handler, test program of instrumen-
tation and other hardware devices (Program), statistical analysis software (SPSS),
data traceability software (TDS), production line management system (ERP), etc.
The most important component is the ATE equipment. The world’s mainstream
ATE equipment is roughly divided into test systems for SoC, memory, analog IC,
mixed signal IC, and RF IC, etc.
It is easy to build a test platform that meets the testing requirements of ICs with a
reasonable combination of software and hardware; however, such a test platform
may not be efficient and economical for verification analysis as an industrial test
platform. Design engineers need to further develop or improve the test platform to
meet the requirements of new IC devices. As a result, it is an important direction for
test engineers to develop advanced test platform for achieving full-function, full-
performance, and full-coverage testing. The development for advanced testing
platform includes the following: (1) Seamless connection between platforms (e.g.,
from verification to industrial platforms and from wafer-level to package-level tests).
(2) Hardware interface matching as well as data and instruction format compatibility
between handlers, ATE, and probers. (3) Fully automated collaborative test control
between ATE and instruments. (4) Reliable data transfer and storage for simulta-
neous operation of multiple platforms. (5) Development of specialized testing
software and DUT board for different IC devices.
59 Integrated Circuit Testing Technology 1183

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A/D converter. Microelectronics 1, 126–129 (2012)
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Receiver (Tianjin University, Tianjin, 2009)
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82–83 (2010)
10. K. Yu, The study of RFIC testing technology. China Integr. Circ. 3, 41–46 (2015)
11. G. Bi, Electromagnetic Field and Microwave (Zhejiang University Press, Hangzhou, 2006)
12. H.H. Zhang, Application of return loss measurement method in the failure process of high-
frequency channel. Electric Power Inform. Commun. Technol. 10, 34–38 (2013)
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Electronics Industry, Beijing, 2011)
Integrated Circuits Packaging Reliability
60
Anjun Huang, Rongzheng Ding, Hanwu Xiao, Jian Lu, and
Hongwei Luo

Contents
Definition of IC Package Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
Reliability Design of Integrated Circuit Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Design Principles for Packaging Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Design Methods for Package Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Structural Design for Package Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Thermal Design for Package Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
Environment Resistance Design for Package Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
Manufacturability Design for Packaging Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
Reliability Testing for IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
Classification of Reliability Tests for ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
The Function of Reliability Tests for ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
Standards for Reliability Testing of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
National Standards of China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
International, Inducing, and Other Foreign Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Package Reliability Test Procedures for ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
Package Reliability Screening Test Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Package Reliability Quality Consistency Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Failure Analysis Methods for IC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Nondestructive FA Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Destructive FA Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197

A. Huang
Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Wuxi, China
R. Ding (*)
China Key System Co., Ltd (CKS), Wuxi, China
H. Xiao
Wuxi ZhongWei High-tech Electronics Co., Ltd., Wuxi, China
J. Lu
WiFi CMC Electronics Co., Ltd., Wuxi, China
H. Luo
China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou,
China

© Publishing House of Electronics Industry 2024 1185

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_60
1186 A. Huang et al.

Procedure of FA for IC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197

Typical Failure Modes and Classification of IC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Typical Failure Modes of Monolithic IC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
Typical Failure Modes of Hybrid IC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
Failure Classification of IC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
Failure Mechanisms of IC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
Failure Mechanism of Electrical Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
Temperature-Mechanical Stress Failure Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
Failure Mechanism of Climatic and Environmental Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
Failure Mechanism of Radiation Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
Simulation Analysis of Package Reliability of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
The Reliability Test Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
The Reliability Simulation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206

Abstract
Package reliability is a very important aspect for IC products and is studied for the
improvement and optimization of package design, processes, and materials, etc.,
as well as the development of measurement, test method, and applications. The
state-of-the-art reliability theory, mechanisms, and failure analysis (FA) methods
are urged to analyze, simulate, evaluate, and improve IC reliability, achieving
more accurate prediction of the product lifetime. This chapter mainly describes
the definition, design, testing procedures, and standards for the reliability of IC
packaging. In addition, the methods and procedures of FA are also introduced.

Keywords
Reliability design · Reliability testing · Failure analysis (FA) methods · Failure
modes · Failure mechanism · Simulation analysis

Definition of IC Package Reliability

The IC reliability can be defined as the probability of the ICs working for a specified
time under given conditions to achieve specified functions. The reliability of the ICs
can be evaluated by reliability parameters (e.g., reliable degree, failure-rate (FR),
mean-time-between-failures (MTBF), and mean-time-to-failure (MTTF), etc.). Reli-
ability contains three elements: durability, maintainability, and design reliability. The
IC reliability can be expressed as follows:

RðtÞ ¼ 1  FðtÞ ð1Þ

where R(t) is a reliability function as the probability of the IC working well at time
t, and F(t) is a cumulative failure distribution function as the probability of a
randomly selected IC failing at time t. Reliability is characterized by comprehen-
siveness, time, and statistics. To quantify the reliability, the mean-time-to-failure is
used to characterize the IC life as in below:
60 Integrated Circuits Packaging Reliability 1187

1
MTTF ¼ tf ðtÞdt ð2Þ
0

where f(t) is the probability density function at time t (t > 0).

The mathematical relationship between F(t) and f(t) is expressed as:

d
f ðtÞ ¼ FðtÞ ð3Þ
dt
Package reliability is a very important aspect of IC reliability. To ensure IC
reliability, the package reliability is studied for the improvement and optimization
of package design, processes, materials, as well as test methods and applications.
Due to the unknown effects of new package structures, processes, and materials on
reliability, the state-of-the-art reliability theory, mechanisms, and failure analysis
(FA) methods are urged to analyze, simulate, evaluate, and improve IC reliability for
achieving more accurate predictions of the product life. The multifunction packages
with various devices (e.g., ICs, sensor, passive components, MEMS, and biological
chips, etc.) need to perform package reliability tests as required to accomplish
reliability monitoring, statistics data, and clarify potential failure mechanisms for
developing new or improving IC products.
Package reliability is greatly affected by defects and failures in packages. The
failures occur when the IC performance is degraded by the effects of mechanical,
heat, chemistry or electricity, etc. with product parameters drifted outside the
acceptable ranges. Package defects can also accelerate failures in packages and
degradation of ICs and leading to unpredictable results. Package defects occur
randomly in any phase of manufacturing and assembly processes (e.g., chip passiv-
ation, die bonding, wire bonding, and pin formation). The study of package reliabil-
ity mainly focuses on identifying the locations, types, and potential sources of
defects and failures as the package body is vulnerable to various defects and failures.
Various tests and simulation analysis are useful to identify major failure factors (e.g.,
by using physical model, numerical method, trial and error method, etc.). The
acceleration test is useful to verify and confirm package failures. The failure rate
can be improved in manufacturing by optimizing process parameters and improving
package materials.
The evaluation of package reliability is mainly completed in the certification
process of IC packages, which consists of virtual, product, and mass production
certifications. (1) In the virtual certification process, product life is predicted by
physical failure models (e.g., based on failure mechanisms and failure time predic-
tion) and physical failure reliability prediction. (2) In the product and mass produc-
tion certification process, the physical test of manufacturing samples and
acceleration test for reliability evaluation are carried out. With the development of
FA technology, the reliability evaluation evolves from estimating field data failure
rate to employing physical failure prediction model for considering package char-
acteristics and loaded stress. Reliability can be evaluated by time-to-failure of failure
site generated by specific failure mechanisms under specific load conditions, and
1188 A. Huang et al.

reported by failure sites, stress import, and failure modes. International Association
of Electronic and Electrical Engineers IEEE 1413.1-2002 standards provide a flow
frame of reliability prediction for electronic systems or equipment, and cover
indispensable content in reliability prediction report.

Reliability Design of Integrated Circuit Package

Package reliability design is a technical activity that can be adopted to eliminate or

control the failure modes of packages for ICs. Package reliability design mainly
includes package structure, thermal, environmental resistance, and manufacturability
designs.

Design Principles for Packaging Reliability

Package reliability design should follow the following basic principles. (a) Explicit
reliability index and evaluation schemes should be identified for reliability design.
(b) Every aspect of the package design should be covered during package design,
including structural, thermal, and manufacturability designs, etc. (c) Potential failure
modes should be eliminated or controlled to the greatest extent. (d) Before new
structures, processes, and materials are used, the related reliability evaluation should
be performed strictly. (e) All factors including performance, reliability, cost, time,
etc. should be balanced carefully for improved design scheme.

Design Methods for Package Reliability

Generally, the methods for package reliability design are as follows. (a) Establish
and implement the principles of reliability design from the guidelines (e.g., the
generality, mature experiences, and failure lessons of package reliability) and
apply them to package designs. (b) Derating design method: Reducing the stress
causing by the thermal, electrical, mechanical, and other factors during working.
(c) Redundancy design method: Multiple leads are connected in parallel for the same
power supply in the package, or redundancy distribution of power supply is applied
reasonably. (d) Robust design method: Product’s performance can be designed to be
insensitive to the parameter fluctuations in assembling process by parameter and
tolerance design. (e) Simulation analysis method: The structure strength and thermal
performance of the package can be simulated by using finite element method.

Structural Design for Package Reliability

Structural design for package reliability should focus on the following five aspects.
(a) Die bonding strength on the substrates, especially the effects on bonding strength
60 Integrated Circuits Packaging Reliability 1189

related to temperature raise during operation. (b) Wire bonding reliability, including
the current carrying capacity, ability to resist mechanical shock, vibration, and other
external mechanical stress, bonding strength. (c) The hermetic sealing of packages.
(d) The structure and strength design of package lead to eliminate or reduce fatigue,
wear, fracture, and other failures. (e) The plating structure of package leads and
related soldering reliability evaluation.

Thermal Design for Package Reliability

Thermal design for package reliability refers to controlling IC junction temper-

ature within the allowed range with possible measures according to thermal
characteristics and heat transferring theory. Technical measures commonly used
in thermal design are described as follows. (a) Proper arrangement of devices
(including ICs) positions in package to balance the distribution of high-
temperature and low-temperature devices and avoid the concentration of hot
spots. (b) Shortening heat transfer path and reducing thermal resistance as far
as possible. (c) Thermal dispersion via should be added in ceramic package and
various substrates to reduce package thermal resistance. (d) Choosing materials
with low thermal resistance for improving the processing precision of thermal
contact surfaces, or adding materials with high thermal conductivity between the
contact surfaces. (e) Increasing the blackness of the surface to improve heat
dissipation through radiation. (f) Heat sink, heat pipe, fan, and other measures
shall be adopted to increase heat conduction.

Environment Resistance Design for Package Reliability

All of external environment conditions will be encountered in the process of

storage, transportation, and working. Based on the nature and features of the
environment, the impact of the environments should be analyzed and the envi-
ronment resistance design should be performed (e.g., moisture resistance design,
antisalt atmosphere (corrosion) design, mildew-proof design, and the design of
shock resistance and vibration resistance, etc.). (a) Moisture resistance design:
Materials with low hygroscopicity and stable performance in the hot humid
environment are used, and metals with close electrode potential are selected as
direct contact; hermetic package can be used for circuits with high requirement of
moisture-proof. (b) Antisalt atmosphere (corrosion) design: Selecting antisalt
atmosphere (corrosion) materials, or conducting anticorrosion coating treatment
on the surface. (c) Mildew-proof design: Choosing the materials with good
mildew-proof performance, which should be considered together with moisture
resistance design. (d) Shock and vibration resistance design: The intrinsic fre-
quency of the ICs should be out of the vibration frequency of the vibration source
and equipment. Commonly its intrinsic frequency should be more than two times
of the intrinsic frequency of the equipment. The intrinsic frequency of ICs can be
1190 A. Huang et al.

estimated by the calculation formula of components or by simulation. The

frequency range of electronic products affected by vibration generally falls in
20 Hz–2 kHz [1].

Manufacturability Design for Packaging Reliability

The key of design for manufacturability (DFM) is that the manufacturability is

considered in the package design for reducing cost and shortening the develop-
ment cycle. Manufacturability design mainly considers the following three
aspects. (a) The design of various package and substrates shall meet the require-
ments of materials, plating, minimum line width and line space, minimum ratio of
substrate thickness-to-via, minimum via size, etc. The manufacturing process
window should be maximized to improve the yield and reliability. (b) Device
selection: Such as temperature resistance properties of device, structure, and
materials of the package lead plating layer, the feasibility of the device with
existing process, etc. (c) Capability of assembly process: The structure and size
of pads, equipment capability for the design requirements, the solder reflow and
cleaning requirements to the design, device layout direction and spacing
requirements, etc.

Reliability Testing for IC

Reliability testing refers to the survey, analysis, and evaluation of the packaging
reliability by applying a certain amount of stress (e.g., electrical stress, thermal
stress, mechanical stress, etc.) to materials for by which to check whether its
performance is stable under various stresses, and whether the various parameters
exceed technical standard, as well as the completeness of the package structure,
to determine whether the package is qualified or reliable, the design is reasonable
and whether the manufacture is normal. The IC will encounter in a very complex
environment in storage, transit, and using, such as vibration, impact, and
mechanical effects, as well as moisture, salt atmosphere, radiation, and other
severe environment. In addition, they are required to work normally under
conditions of high or low temperature and dramatic temperature changes,
which may accelerate IC failures. The degree of these impacts will involve the
rationality of IC structure, the stability of packaging materials, the correctness of
the packaging process and the consistency of the quality. According to different
reliability requirements, different stress tests should be applied to projects.
Reliability testing can evaluate the reliability level of ICs to a certain extent, by
which to continuously optimize the package materials, improve the packaging
structure, optimize the packaging processes, and take the necessary measures to
ensure the reliability of packaging.
60 Integrated Circuits Packaging Reliability 1191

Classification of Reliability Tests for ICs

There are various methods to classify the reliability testing for ICs. Assorted by
environmental conditions, reliability testing is divided into simulation tests and field
tests under various stress conditions. Assorted by testing methods, it is divided into
electrothermal performance test, mechanical test, environmental test, etc. Assorted
by the level of testing stress, there are normal stress tests and accelerated stress tests.
Classified by whether samples would be destroyed in tests, there are destructive and
nondestructive tests. Classified by the purpose of reliability test, there are reliability
acceptance (including reliability appraisal), validation, statistics tests, etc. According
to the role played during testing, there are screening and acceptance tests. The most
common classification is according to whether samples would be destroyed in tests.
(a) Nondestructive tests: It does not need to do chemical or physical treatment which
is one of the development directions of failure analysis techniques. Nondestructive
tests mainly include external visual inspection, internal visual inspection, X-ray,
C-SAM, etc. (b) Destructive tests: It consists of electrical stress and environmental
tests. The former includes constant acceleration, mechanical shock, random vibra-
tion, bond-pull, die-pull, die shear tests, etc. The environmental tests are mainly
chemical tests that include high-pressure cooking, temperature cycling, moisture
soak, salt atmosphere, hermetic sealing, and flammability tests, etc.

The Function of Reliability Tests for ICs

(a) To expose the defects of structure and materials during early design and produc-
tion to screen defects. (b) To evaluate the failure modes in different working
conditions based on different test data as well as to study the failure mechanisms
for optimization of materials, package design, process, and reasonably improving
reliability. (c) Provide basis for the application of ICs and direct users to choose
factories and process route by approving the quality level to test the predetermined
reliability indicators. (d) Provide basis for the certification of IC packaging and the
acceptance inspection of products.

Standards for Reliability Testing of ICs

Standards for reliability testing of ICs are a series of normative documents that are
used to direct and stipulate the reliability assessment and validation tests, consisting
of a variety of standardized documents including generic specifications, basic
standards, handbooks and guidelines, etc. IEC standards, JEDEC standards, MIL
[3] standards, and European ESCC standards form the main standard systems
worldwide used for reliability testing of IC packages. In China, the standard system
1192 A. Huang et al.

is formed by civil standard and military standard systems. The former consists of GB
standards (referred to as China national standards), IEC standards, JEDEC standards,
and industrial standards, the latter consists of GJB standards (referred to as China
national military standard) and enterprise military standards, etc. Assorted by scopes
of region and profession, standards for reliability testing are divided into interna-
tional, national, industrial, and enterprise standards. Assorted by scopes of applica-
tions, they are divided into civil, military, and aerospace standards. International
standards include IEC, ISO, JEDEC, SEMI, IPC, and ISO standards. National and
regional standards include American ANSI and MIL, European ESCC and EN,
Japanese JIS and JEITA, German DIN, British BS, Chinese GB and GJB standards.
Industrial standards include Chinese GJB, QJ (referred to as China aerospace
standard), and SJ (referred to as China electronics standard).

National Standards of China

(a) The relevant national standards are GB/T 2423 series for “environmental testing
for electric and electronic products,” GB/T 2424 series for “basic environmental
testing procedures for electric and electronic products,” GB/T 4937 series for
“mechanical and climatic test methods for semiconductor devices,” and GB/T
8750-2014 for “bonding wires for semiconductor packages.” (b) The relevant
industrial standards include China national military standard as GJB 548B-2005
for “test methods and procedures for microelectronic devices,” GJB 1420B-2011 for
“general specification for packages of semiconductor ICs,” and GJB 76778B-2012
for “test methods for ball grid array (BGA),” aerospace standards as QJ 1906A-97
for “test methods and procedures for destructive physical analysis (DPA),” QJ
840-84 for “environmental technical requirement and test method for electronic
elements and devices,” electronic standard as SJ/T 10745-96 for “mechanical and
climatic test methods for semiconductor ICs,” SJ20129-92 methods for “measure-
ment of metallic coating thickness,” SJ/T 11200-2016 for “environmental testing –
Test Td: Solderability, resistance to dissolution of metallization and to soldering heat
of surface mounting devices.” (3) The enterprise standards normally established by
the associated companies are mainly the detailed specifications for package materials
(e.g., hermetic packages and seal lids, etc.).

International, Inducing, and Other Foreign Standards

(a) IEC Standards: The relevant standards published by International Electro-

technical Commission (IEC) include IEC60068 environment test series and
IEC60749 series: mechanical and climatic test methods for semiconductor devices,
etc. (b) JEDEC Standards: The relevant standards published by Joint Electron
Device Engineering Council (JEDEC) include JESD 22-Axxxx series, JESD
22-Bxxxx series, EIA/JESD 51 series: ICs thermal measurement method, JESD-
020C: moisture/reflow sensitivity classification for nonhermetic solid state surface
60 Integrated Circuits Packaging Reliability 1193

mount devices, etc. (c) MIL Standards: The main standard in MIL American military
standard system is MIL-STD-883 for test method standard of microcircuits. This
standard defines five series of test methods and criteria as environmental tests,
mechanical tests, electrical tests (digital), electrical tests (linear), and test procedures.
Many countries and regions often completely adopt MIL-STD-883 standard as their
national or regional military standard, other countries and regions partly adopt it into
their own standard sets which are supplemented with a few new established test
methods. (d) SEMI Standards: SEMI-Gxxxx series published by SEMI (Semicon-
ductor Equipment and Materials International) are the main standards for reliability
testing of ICs, which refer to the test methods for lead finishes: test method for Ag
plating quality, for molding compounds: test method for measurement of adhesive
strength between lead frames and molding compounds, for measurement of die shear
strength, and for measurement of pull strength of wire bonding, etc. (e) ESCC
Standards: European Space Components Coordination establishes a whole standard
system ESCC for aerospace devices, it is divided into five levels. The basic standards
are in level 2, including series 2xxx and series 2xxxx. The standards in level
2 stipulate the methods for reliability testing of ICs. Some of these test specifications,
like ESCC basic specification No. 20400 “Internal Visual Inspection” and ESCC basic
specification No. 20500 “External Visual Inspection and Dimension Check” are also
specified in level 2. (f) JIS Standards: JIS standards published by Japanese Industrial
Standards include JIS C00XX series: Environmental tests, JIS C5027: Storage (low
temperature) testing method for electronic components, JIS C5032: Sealing (immer-
sion cyclic) testing method for electronic components, JIS C5036: Endurance (elec-
trical) testing method for electronic components, JIS C5037: Endurance (mechanical)
testing method for electronic components, JIS C1000 series: Electromagnetic com-
patibility (EMC): testing and measurement techniques, and JIS C7022: Environmental
testing method and endurance testing method for semiconductor integrated circuits,
which are applicable to reliability test of IC. (g) IPC Standards: The relevant standards
published by ISO (the abbreviation of Institute of Printed Circuits) are mainly related
to those for solderability test, including IPC J-STD-002D: Solderability tests for
component leads, terminations, lugs, terminal and wires, etc. (h) ISO Standards: The
relevant standards published by ISO (International Organization for Standardization)
are ISO 14621-1: Space system – Electrical, electronic, and electromechanical (EEE)
parts – Part 1: Parts management, and ISO 14621-2: Space system – electrical,
electronic, and electromechanical (EEE) parts – Part 2: Control program
requirements, etc.

Package Reliability Test Procedures for ICs

Package reliability test procedures for IC usually should be divided into three
classes: screening, quality consistency, and acceptance procedures. Scientific and
reasonable procedure setting can effectively achieve the aim of IC evaluation or
reliability; but unreasonable procedures settings may lead to overstressing damage or
invalid evaluation adversely.
1194 A. Huang et al.

Package Reliability Screening Test Procedures

Common IC reliability screening test procedures are mainly divided into hermetic
and nonhermetic screening procedures. Generally, the inspection items and sequence
defined in the screening program cannot be changed freely, unless there is sufficient
data and evidences to illustrate a better screening with changes in test items, stress
levels, and the order of test items. The applicability of the screening test procedures
for hermetic and nonhermetic packages is different. A typical screening test proce-
dure for a hermetic packaged IC is illustrated in Fig. 60.1. When setting the
screening test program, the selection of stress conditions shall consider if it can
effectively eliminate early failures and does not cause overstress damage to normal
devices. Taking the homeostasis accelerated screening test of hermetic IC package as
an example, if the circumference of the sealing ring is less than 50 mm and the
package mass is less than 5 g, then it generally set at 30,000 g. In addition, it is
selected according to specific applications or determined after progressive tests from
low to high stress.

Package Reliability Quality Consistency Procedures

Factors such as package type, process, and material of ICs determine the inspection
items and stress conditions in the qualification (quality consistency) inspection
procedures. Since the evaluation test stress is dominated by destructive evaluation
items that can realize the quality level of affordable packaging, ICs that have been
verified as experimental items are generally no longer used in electronic products.
The qualification (quality consistency) test of package reliability usually includes
multiple groups of test items and electrical characteristic test items [2]. Among them,
the package reliability test items are usually divided into mechanical, climatic and
environmental, physical characteristics, chemical analysis, and other inspection
groups. Inspection group can be performed in parallel. It is also possible to select
and perform partial inspection groups first based on specific applications and
packaging process factors.
When setting up specific test items, the control level of key processes in the IC
packaging process should be considered for package reliability qualification (quality
consistency). However, the severity of the test items needs to be considered in
combination with the package and application requirements. In principle, the

Fig. 60.1 Typical screening test procedure for hermetic packaged ICs
60 Integrated Circuits Packaging Reliability 1195

rationality and applicability should be comprehensively considered in combination

with the quality level of IC packaging and the requirements of the application
environment, when selecting specific reliability test groups. For example, the
humidity factor has a more obvious influence on the reliability of the circuit package
for nonhermetic ICs. Therefore, more considerations should be given to the inspec-
tion items related to moisture factors (e.g., performing auto clave, HAST, tempera-
ture cycling, etc.). If the external leads of the ICs are BGA packages, corresponding
inspection items should be added (e.g., solder ball coplanarity, solder ball pulling,
solder ball shear, etc.).
It is generally necessary to refer to national military standards, industry standards,
and special regulations for use at the same time, when setting up qualification
(quality consistency) inspection procedures. Samples for the package reliability
qualification are randomly selected from the qualified batch after screening. All
kinds of test methods can be set up for independent groups, and the number of
samples to be tested should be selected for verification. The following principles are
followed in the implementation of inspection items: (a) Test first, then verify:
Perform climate environment or mechanical tests firstly, and then electrical perfor-
mance or sealing tests. (b) Implement effective evaluation: The test samples of each
independent group can be saved and reused, but it must be ensured that the test items
already performed will not interfere with the next test. Take a commercial monolithic
IC in nonhermetic package as an example, typical procedures for package reliability
qualification inspection are shown in Fig. 60.2.

Failure Analysis Methods for IC Packages

The failure analysis (FA) of IC packages is to identify the failure phenomena and
types from IC failures to identify failure mechanisms and make corrections in design
and process to prevent similar package failures. It usually contains nondestructive
and destructive analysis. Destructive physical analysis (DPA) is a destructive anal-
ysis as designed to prevent the use of ICs with obvious or potential defects by
randomly sampling and performing a series of destructive and nondestructive
physical tests and FA. Qualitative, quantitative, and structural analysis methods for
IC package failures are also divided into nondestructive and destructive FA methods.
Nondestructive FA will not change the existing state of IC package failures and will
not affect the performance of ICs. Instead, loss-effectiveness analysis will change the
existing state of IC package failures with permanent change in physical or chemical
state and not restorable.

Nondestructive FA Methods

Nondestructive FA is to observe and analyze the failure sites after a series of physical
processing of the package for finding failure root causes. These methods include the
following: (a) External visual: Pin fracture or lead loss. (b) Optical microscopy:
1196 A. Huang et al.

Fig. 60.2 Typical procedures for package reliability qualification inspection

Dendritic Ag on ceramic substrate. (c) Dye penetration test (microcrack of plastic

package). (d) Seal: Coarse fluorocarbon leak detection, tracer gas helium fine leak
detection, etc. (e) Radiography (Au wire fracture, metallization layer fracture,
conductor open circuit or short circuit, etc.). (f) Scanning acoustic microscope
(SAM) inspections: Interfacial laminar molding plastics cracks between the epoxy
molding compound (EMC) and the lead frame or substrate, etc. (g) Scanning
electron microscope (SEM) inspections: Opening circuit caused by metallization
electromigration, bond failure, etc. (h) Particle impact noise detection test (PIND):
The transient short circuit analysis of movable conductive particles in the cavity.
(i) Electrical tests: Quantitative measurement and analysis of open circuit, short
circuit, surface resistance, contact resistance, insulation resistance, and isolation
voltage of IC package, etc. (j) Infrared microscope (IRM) inspections: E.g., cracks
of die, conductor corrosion on the substrate, etc. (k) Thermal analysis: Analysis of
deformation failure of different package materials by thermomechanical analysis
technology, recognition of delamination failure caused by thermal decomposition of
the package materials by thermogravimetric analysis, etc. (l) Moiré interferometry
60 Integrated Circuits Packaging Reliability 1197

and synchronized microfocal X-ray Diffraction (detection of deformation and stress

in package). (m) XRF (X-Ray fluorescence) and XRD (X-Ray diffraction): For
analysis of surface contamination or residue, corrosion products, elemental surface
distribution after electrical corrosion, intermetallic compounds composition, etc.

Destructive FA Methods

Physical loss-effective (destructive) analysis methods include mechanical opening

analysis, laser decapping analysis, mechanical cutting analysis, sulfuric acid corro-
sion decapping analysis, focused ion beam (FIB) with microprecision cutting anal-
ysis (observation of internal open circuit, short circuit, crack, void, etc.), internal gas
analysis (the instability analysis of electrical properties due to the content of internal
water vapor), Auger electron spectroscopy (AES) analysis.

Procedure of FA for IC Packages

In order to prevent loss of failure evidence or incorrectly introducing new failures during
analysis, package failure analysis (FA) should be performed according to a standard
operation procedure (SOP). Typical flow chart of IC package FA is illustrated in
Fig. 60.3. (1) Collect data of failure sites: While collecting and preserving failure
samples, failure field data are collected, including failure environment, stress, occurrence
period, and electrical test data/results around the failure. Failure environment includes
temperature, humidity, irradiation, etc. Failure stresses include temperature, mechanical,
climate, electrical, and radiation stresses. Failure in reliability tests is necessary to know
the test items, stress levels, and time of the packages. Failure occurrence periods include
the experiences of failure packages, the stage of failure occurrence (development,
production, testing, storage, use, etc.), and the specific time. Around failures, the
electrical test conditions, electrical test data, and test results are also part of the collected
data. (2) Identification of package failure Modes: According to the collected failure field
data, function test data, and simple appearance inspection, the failure locations (e.g.,
chip surface/bottom or interface, lead-out end, sealing chamber, etc.) are analyzed and
determined. The experiences accumulated in FA and the data base in failure models
would identify the physical or chemical types of the surface phenomena on failure
samples. (3) Describe package failure characteristics: In FA, the failure modes of ICs are
described qualitatively or quantitatively by physical and chemical parameters. These
descriptions include but not limit to words, photos or pictures, test data, and their charts,
videos, sample preparation. (4) Determining the failure mechanism of packages:
According to the failure modes and failure parameters, the failure mechanisms of
packages are assumed and confirmed from the obverse and reverse. Failure phenomena
should be repeated; otherwise the assumptions must be reassumed and retested to
confirm the failure mechanisms. (5) Package failure corrections: According to the
determined failure mechanisms of package, corrections are taken to eliminate the root
1198 A. Huang et al.

Fig. 60.3 Typical process of IC packages FA

causes of failures. The effect of corrective methods needs to be tracked and verified. The
relevant documents of IC package should be changed accordingly.

Typical Failure Modes and Classification of IC Packages

IC package failure mode refers to the external visual representation [4] of the reliability
test process or the failures during storage and use as related to the IC package. Typical
failure modes for IC packages can be divided according to the types of ICs.
60 Integrated Circuits Packaging Reliability 1199

Typical Failure Modes of Monolithic IC Packages

The typical failure modes of monolithic IC packages mainly include the following
seven categories. (a) Plastic package appearance deformation, warpage, bubbling,
cracking, etc., molding compound delayering, lead wire short circuit or even wire
bonding disengagement, chip cracking, etc. (b) Short circuit caused by excess in
metal or ceramic package cavity; twisted deformation of bond wire or even wire
short circuit; bond wire is corroded to grow “white hair-like” substance; chip
pressure point Al layer or passivation layer crack under metal chemical corrosion
of the layer/wiring; chip shedding; short circuit caused by metal bubbling, cracking
or even peeling inside the plating layer or in the brazing zone; air leakage after
cracking of the glass or ceramic sealing zone, causing open circuit or short circuit of
lead wire corrosion at the bonding sites; metal material creep, crack propagation, and
fracture cause the resistance to become large or even open. (c) High-resistance,
brittle “purple spots” or“white spots” appear on the IC package bond wires. (d) The
under-fill between the flip-chip and the plastic laminate substrate or the ceramic
substrate is layered and cracked with broken bumps; the bump material in the flip-
chip is melted, migrated, and interconnected; the internal bump weld surface is
fatigue cracked, or the bump is empty inside and broken. (e) The failure of the chip in
the package due to electrostatic discharge or metal electromigration (EM). (f) The
contact resistance caused by chemical corrosion, fatigue deformation, fracture, and
shedding of the package is increased or even open; leakage, parameter drift or even
short circuit, functional failure caused by small insulation resistance; temperature or
mechanical stress of the solder ball or solder column lower defects, fatigue fracture
failures; weld failure caused by poor wettability or weldability of lead, solder ball or
solder column; short circuit failure caused by growth of Sn. (g) Radioactive radiation
from packaging materials causes drift in IC parameters and soft failure of α
particles [4].

Typical Failure Modes of Hybrid IC Packages

Hybrid IC package failures [4] can be divided into package internal component
failures and package shell failures. Among them, internal component failures include
component placement, interconnect, and substrate failures. The common failure
modes of hybrid IC package internal components include the following four cases
in addition to the typical failure modes of monolithic IC packages. (a) The insulation
resistance of active and passive components in the package decreases; mounting
components such as packaged internal chip components and chips fall off; chip
component/chip cracking; welding defects such as bonding void and weak bonding;
aging of bonding materials, etc. (b) Open circuit and short circuit failures of the
metal thick film itself, poor adhesion between the metal thick film and the substrate,
and falling off; Electrochemical migration between metal thick films [5] (e.g., Ag þ
migration); open circuit failures caused by virtual welding, cracking, etc.; in the joint
area of thick film and solder; degradation and failure of multilayer interconnection
1200 A. Huang et al.

caused by aging of polyimide insulation layer in thin film multilayer substrate.

(c) When the shell is sealed, the solder and flux enter the interior causing short
circuit and metal film corrosion failures. (d) The interconnect TSV Cu in the 2.5D-
and 3D-stacked structures is filled with void delamination and cracked failures;
delamination and rupture failure of laminated bare chips; the package of stacked
structure warps under temperature stress.

Failure Classification of IC Packages

The failures of IC packages, according to the continuity of failures [5], can be divided
into fatal and intermittent failures, slow degradation, etc. According to the time of
failures, there are early failures, random failures, wear failures, etc. Based on where
failures occur in parts, there are internal defect and external stress failures. According
to the source of failures, there are packaging raw material defects, packaging process,
failure in use, etc. According to the stress conditions of failures, there are electrical,
temperature-mechanical, climatic environmental, and radiation stress failures.

Failure Mechanisms of IC Packages

Failure mechanisms of IC packages refer to various stress factors and interaction

processes related to IC packages, such as electricity, temperature, machinery, climate
environment, and radiation, which lead to failures. According to different stress
conditions, failure mechanisms can be divided into electrical stress, temperature-
mechanical stress, climatic environment stress, and radiation stress.

Failure Mechanism of Electrical Stress

Electrical stress failures include functional failures such as electrostatic discharge in

packaging, positive feedback (latch-up) formed by the presence of n-p-n-p structure
in IC, or over-electrical stress damage such as moisture/pollution/damage (white
channel breakdown) of passivation layer medium, which leads to fuse of inner leads,
parameter drift or even short circuit caused by leakage between outer leads, burned
open circuit, etc. When Ag plating is applied to the surface of external pins of
devices packaged by some metal shells or silver wires are used as bonding wires,
Ag þ dendritic migration occurs due to Ag ionization under the action of water
vapor and electric field, thus causing short circuit failures.

Temperature-Mechanical Stress Failure Mechanism

Temperature-mechanical stress failure mainly includes the following nine cases.

(a) The solder squeezed into the cavity during the sealing process of the cavity
structure, the coating or sealing molten material falls off, and the process control
60 Integrated Circuits Packaging Reliability 1201

monitor (PCM) in paddle falls off to form the surplus in the cavity, which all may
lead to short circuit or accidental short circuit failures. (b) The Au-Al bonding point
generates brittle and high-resistance AuAl2 “purple spot” failure and Au2Al “white
spot” failure [6] under high-temperature conditions, as shown in Fig. 60.4.
(c) Because the thermal expansion coefficient and elastic coefficient of the chip,
bonding wire, lead frame or substrate, molding compound, and the like in the
package are inconsistent, when the temperature changes, the material expands and
contracts to generate internal stress, causing the bonding wire to pull out and break,
the chip to crack, or delamination failure with the substrate [7, 8]. (d) In the under-fill
process, SiO2 particles are filled unevenly, filling pressure and curing temperature do
not match, causing delamination of the filler and failures caused by cracking at the
bottom of the solder joint as shown in Fig. 60.5. Thermal expansion coefficient
mismatch and high-temperature process (such as reflow soldering) exceed the
melting point of the internal bump, leading to interconnect failure by bump melting
as shown in Fig. 60.6.
(e) The intermetallic compound (IMC) generated by solder (e.g., Au, Sn, Pb, Cu,
Ag, and the like) in the flip-chip bonding area is mismatched with the thermal
expansion coefficient between the substrate, the bonding pad and the chip under
the condition of temperature change, power-on heating or mechanical stress, and the
IMC cracking leads to the bonding pad to “gold brittle” cracking failure. The
mismatch between the solder and the welding temperature causes holes in the
welding spot due to the interdiffusion speed difference of various solder, thus
damaging the electrical connection and mechanical properties of the welding spot
[6], as shown in Fig. 60.7. (f) Under the change of periodicity temperature, TSV Cu
filling and Si hole wall, pad and solder ball, stacked die form, stacked package, etc.
in 2.5D- and 3D- stacked structure will cause cracking, delamination, and fermen-
tation starter failures due to stress caused by thermal expansion coefficient mis-
match. (g) Under the change of periodicity temperature or mechanical stress, the
bonding wire will undergo deformation, wire collision, and fatigue fracture, and

Fig. 60.4 Bond failure

caused by brittle Au-Al
compound
1202 A. Huang et al.

Fig. 60.5 Fracture failure of

solder ball at bottom

Fig. 60.6 Bond failure

caused by brittle Au-Al
compound

materials (e.g., metal, glass or ceramic, molding compound, etc.) will undergo creep,
fatigue crack propagation, fracture, and seal leakage failure. (h) Hydrogen in metal
or brazing materials accumulates and precipitates to stress concentration areas, and
combines with internal residual stress and external stress of the material, generating
huge pressure to cause “hydrogen embrittlement” fracture failures. (i) Sn plague
failure of powder Sn occurs when Sn-containing solder, brazing materials, and
Sn-containing plating layers are stored and work at too low temperature; leakage
and short circuit failure of adjacent pins are caused by Sn whisker growth in pure Sn
or Sn alloy coating package due to internal stress of Sn layer, crystal dislocation,
environmental factors, etc.
60 Integrated Circuits Packaging Reliability 1203

Fig. 60.7 Fracture failure of

solder ball

Failure Mechanism of Climatic and Environmental Stress

Stress failures in climate and environment mainly include the following three
situations. (a) After the molding compound, laminated organic substrate or under-
fill absorbs moisture, the moisture expands rapidly at high temperature, forcing it to
separate from other materials attached to it (e.g., chips, lead frames, etc.), causing
chip cracking, poor contact or fracture of internal solder joints, delamination or burst
failure [8]. (b) External ions, pollutants, and impurity ions in the encapsulation
material dissolve into water vapor to generate electrolyte, and long-term and slow
chemical corrosion or electrochemical corrosion occurs at the inner bonding wire or
exposed Al or Au-Al junction to generate “white hair” Al(OH)3 or corrosion spots as
shown in Fig. 60.8. (c) Sn, Au, Ni, and other protective coatings are too thin, pinhole
density is too high or defective, and impurity ions such as Na+, K+, Cl exist. Under
the action of water vapor and electric field, the metal shell, cover plate, and outer pin
generate electrochemical corrosion, causing leakage short circuit and pin drop as
shown in Fig. 60.9.

Failure Mechanism of Radiation Stress

Radiation stress failures refer to the soft failure of alpha-particles, in which the
electron-hole pairs generated along the path of radioactive elements contained in
packaging materials are aggregated in some areas of the chip under the action of
electric field after fission and emission of alpha-particles, causing the charge amount
in memory cells such as DRAM, SRAM, and the like to change, resulting in
erroneous flip of the circuit [7, 8].
1204 A. Huang et al.

Fig. 60.8 Chemical

corrosion of Al pressure
points

Fig. 60.9 External pin

corrosion caused by coating
defects

Simulation Analysis of Package Reliability of ICs

The two main research methods of IC package reliability are reliability tests and
reliability simulations.

The Reliability Test Methods

It is applying the specified stresses to IC packages or materials, such as electrical,

thermal, mechanical or combination stresses, and then check whether the perfor-
mance parameters of the tested sample exceed the technical specifications so as to
determine whether the IC package is failed or not.
60 Integrated Circuits Packaging Reliability 1205

The Reliability Simulation Methods

It is based on the basic theoretical methods of IC package reliability (e.g., thermal,

electrical, mechanical theory, and numerical calculation and computer technology).
IC package reliability can be evaluated through a large number of calculations for
simulating the IC packages under various stresses. The most frequently used
methods include finite element (FE) and finite difference (FD) methods. The soft-
ware ANSYS Workbench and Icepak are often used in IC package reliability
simulations. The reliability simulation methods are generally used in the stage of
product design and analysis. Compared with the reliability test methods, reliability
simulation methods are more economical and flexible, and can quickly and easily
change the model parameters and other related conditions, and so the simulation
analysis results are more obvious and comprehensive. The simulation methods are
cost saving and shorter cycle in the research of new products and also for studying
failure mechanisms in IC packages. The general procedures of IC package reliability
simulation methods used in analysis are as following: (a) Preprocessing: It is the first
step of IC package reliability simulation analysis. The simulation model of IC
package is established firstly (e.g., geometric models). Then, the model parameters
are defined, including material properties, structure parameters, cell partition, etc.
The IC package models for calculation are generated by the software.
(b) Calculation: It is the key part of IC package reliability simulation analysis,
including determining the type of reliability analysis, such as thermal, mechanical
or synthesis, setting the bound conditions for calculation and selecting the appropri-
ate solution method. (c) Postprocessing: It is to display the results of numerical
calculation in the form of graphics and data. The correctness of simulation model
and the rationality of the solution are verified in the step.
Life prediction is an important part of IC package reliability research. Fatigue
failures are the main causes of IC packaging failures. Defects are induced and grown
by thermal, mechanical, electromagnetic or chemical stress, and finally induce the
failures of IC packages. The life of IC packages is predictable by using the life
prediction models with input parameters derived from actual test or theoretical
analysis (e.g., plastic strain, creep strain, and strain energy density). For different
mechanical characterization parameters, the four life prediction models are catego-
rized as plastic strain, creep strain, energy, and fracture models. The life prediction
model of plastic strain is based on the time-independent plastic effects. The life
prediction model of creep strain is based on the time-dependent effects. The life
prediction model of energy is based on the hysteresis energy of stress and strain. The
life prediction model of fracture is based on the fracture mechanics, calculating the
accumulating damage effect caused by fracture process. The two main methods for
IC package life prediction are test and numerical simulation methods. For the
simulation method, the actual reliability test is simulated using finite element method
based on material constitutive model. The life is predicted using life prediction
model and the nonlinear simulation results. The general simulation procedures of
IC package reliability lift prediction are as following: (a) software simulation of life
test; (b) calculation of control mechanical parameters (cumulative creep strain,
1206 A. Huang et al.

cumulative strain energy density etc.); (c) life is predicted using life model and
control mechanical parameters.

References
1. Reliability Design of Semiconductor Integrated Circuit. http://max.bookl18.com/html/2015/
0525/17643569.shtm
2. W. Luo, J. Wei, H. Yang, Reliability Test Engineering for Electronic Components [M] (Publish-
ing of Electronics Industry, Beijing, 2005). English Draft: Qiaoyun Zou. Wuxi Zhongwei
Tengxin Electronics Co., Ltd.
3. MIL-STD-883J (2013), Department of Defense Test Method Standard Microcircuits [S]
4. X. Kong, Y. En, Electronic Component Failure Analysis Technology, M (Publishing House of
Electronics Industry, Beijing, 2015)
5. L. Yao, Reliability Physics, M. (Publishing House of Electronics Industry, Beijing, 2004)
6. Y. Lizhen, Reliability Physics [M] (Publishing House of Electronics Industry, Beijing, 2004)
7. C.A. Harper. Handbook of Electronic Packaging and Interconnection [M], 4th edn. Jia
Songliang, Cai Jian, et al. Trans. (Publishing House of Electronics Industry, Beijing, 2009)
8. E. Yunfei, L. Ping, L. Shaoping, Failure Analysis Technology for Electronic Components [M]
(Publishing House of Electronics Industry, Beijing, 2015)
Standardization of Integrated Circuits
Packaging 61
Le Luo, Jing Wang, and Kun Li

Contents
International Packaging Standardization Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208
International Electro-Technical Commission (IEC) [1, 2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208
Semiconductor Equipment and Materials International (SEMI) [3] . . . . . . . . . . . . . . . . . . . . . . . 1208
Association Connecting Electronics Industries (IPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
Joint Electronic Devices Engineering Council (JEDEC) [7, 8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
China Packaging Standardization Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
Standardization of Package Outlines and Package Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
National Standards for IC Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
China’s National Military Standard (GJB) and US Military Standards . . . . . . . . . . . . . . . . . . . . . . . 1212
Joint Electronic Device Engineering Council (JEDEC) Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
Association Connecting Electronics Industries (IPC) Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
Automotive Electronics Council (AFC)-Q100 Standards [11, 12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219

Abstract
Packaging standards define the requirements of structure, material, surface coat-
ing, external checking, and testing of product reliability, etc. This chapter
describes the standardization of IC packaging, including the introduction of
international packaging standardization organizations, such as International
Electro-technical Commission (IEC), Semiconductor Equipment and Materials
International (SEMI), Joint Electronic Device Engineering Council (JEDEC)
Standards, and Association Connecting Electronics Industries (IPC) Standards.
In addition, China packaging standardization organizations, the description of
standardization of package outlines and package naming, National Standard for

L. Luo (*)
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences,
Shanghai, China
e-mail: leluo@mail.sim.ac.cn
J. Wang · K. Li
China Electronics Standardization Institute, Beijing, China

© Publishing House of Electronics Industry 2024 1207

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_61
1208 L. Luo et al.

Integrated Circuit Packaging (GJB), US Military (MIL) standards, and Automo-

tive Electronics Council (AEC)-Q100 Standards are also discussed.

Keywords
Package standards · IEC · SEMI · JEDEC · IPC

International Packaging Standardization Organizations

International Electro-Technical Commission (IEC) [1, 2]

IEC semiconductor device standardization technical committee (TC47) with four sub-
committees prepares international standards of discrete semiconductor devices, Inte-
grated circuit (IC), Micro-Electro-Mechanical System (MEMS), and packaging. The
semiconductor device packaging standardization subcommittee (SC47D) prepares
international standards of semiconductor device packaging. Activities include package
mechanical outline drawings (including dimensions and tolerances), standardization of
device case measurement methods, assembly, testing, and burn-in sockets, etc., to
ensure the interchangeability of the package outlines of semiconductor devices. Cur-
rently, SC47D has two working groups: WG1 and WG2. WG1 (package outlines)
prepares international standards of the packaging outline for interchangeability and
installation. WG2 (terms, definitions, measuring methods, and related requirement for
semiconductor devices packaging) is responsible for coordinating and reviewing pack-
aging terms and design guidelines. In addition, WG2 prepares standards of outline
format, size, and tolerance measurement methods. The IEC 60191 series packaging
standards developed by the SC47D consists of six parts, of which the sixth part has been
expanded to 17 sub-parts. Comprehensive analysis of the TC47/SC47D standard has
the following characteristics: (a) IEC 60191-2 “Mechanical standardization of semi-
conductor devices. Part 2: Dimensions,” which has been updated with the twenty-fourth
version since its release in 1966, and new proposals (new dimensions) have been added
to it. This not only reflects that the IEC standardization work on the package dimensions
is very detailed and very specific, but also shows that the technology update in the field
of semiconductor packaging is very fast. (b) Since 2001, SC47D has issued Ball Grid
Array (BGA), land grid array (LGA), Fine-pitch Ball Grid Array (FBGA), Fine-pitch
Land Grid Array (FLGA), small outline package (SOP), Small Out-Line J-Leaded
Package (SOJ), and other outline drawings, dimension measurement methods, and
design guide standards for surface mount devices (SMD), reflecting the development
of IC packaging in the direction of the miniaturization and the surface array.

Semiconductor Equipment and Materials International (SEMI) [3]

The existing semiconductor equipment and materials international (SEMI) standards

[4] consist of 16 volumes by the application category, including 3D-IC, equipment
automation hardware, equipment automation software, factory, flat panel display,
61 Standardization of Integrated Circuits Packaging 1209

gas, LED, materials, MEMS, microlithography, packaging, photovoltaic process,

chemicals, safety instructions, silicon materials, process control, and traceability.
SEMI has developed dozens of packaging standards, focusing on lead plating, lead
frames, testing and testing methods for packaging materials, as well as a few package
design guidelines. With the continuous application of 3D packaging technology,
SEMI has released a series of 3D packaging materials, structural terms, measurement
standards, and guidelines to meet industry developments.

Association Connecting Electronics Industries (IPC)

IPC [5, 6] has released 105 standards until 2016, including technical standards,
technical specifications, and technical guidelines. IPC standards are recognized
internationally, and widely promoted and followed. IPC is a member of the interna-
tional electro-technical commission (IEC) electronic assembly standardization tech-
nical committee (TC91) and the president of the world electronics association
(WECC). The IPC package standard categories cover a wide range of topics
including dimension design, packaging technology, material inspection, and appli-
cation guidelines. IPC has also developed standards for advanced packaging (e.g.,
flip-chip, solder ball arrays, and chip scale packages).

Joint Electronic Devices Engineering Council (JEDEC) [7, 8]

It is a main body of electronic industry federation (EIA). JEDEC’s standardization

work in the field of semiconductor packaging is highly active. JEP95 standard has
different types of package outline drawings by registration, and many companies and
organizations register considerable new package outlines every year. JEP95 includes
more than five hundred package forms nowadays. In addition to the registered
package outline drawings, JEDEC also released design requirements for various
package formats, lead-out alignment rules, and related test methods (e.g., lead
integrity, solder-ability, wire bonding, etc.).

China Packaging Standardization Organizations

In 1986, China established the national semiconductor devices standardization techni-

cal committee (TC78), the discrete semiconductor devices technical subcommittee
(TC78/SC1), and the IC technical subcommittee (TC78/SC2). These are corresponding
to the International Electrotechnical Commission comittee (IEC TC47) and 2 sub-
comittes (SC47A, and SC47E) respectively. Due to the constraints, China did not set up
packaging standardization technical committee, as corresponding to IEC SC47D. TC78
is already active on the packaging standardization work, but mainly converted SC47D
packaging standards. In the early domestic packaging standardization work, some
standards were also converted from SEMI, including GB/T 14113-93 “terminology
1210 L. Luo et al.

of package for semiconductor integrated circuits” (refers to SEMI G1 ~ G5, G9, G19,
G22, G26, G27, and other standards), GB/T 14862-93 “Junction-to-case thermal
resistance test methods of packages for semiconductor integrated circuits” (refers to
SEMI G30) [9], GB/T 16526-1996 “Test method measuring the lead-to-lead and
loading capacitance of package leads” (refers to SEMI G24) [10]. At the same time,
GB/T16525-2015 “Specification of lead frames for plastic leaded carrier package” and
other lead frames series standards referred to the SEMI standard as well. Since there is
no packaging standardization committee corresponding to IEC SC47D for a long
period of time, Chinese packaging standardization falls behind semiconductor devices
standardization, and major packaging technology standards with independent intellec-
tual property (IP) are missing. On the other hand, relative research and investment on
packaging standards are seriously insufficient. As the centralized management unit of
electronic standards, the China Institute of Electronic Standardization has started the
preparatory work for the Technical Sub-Committee for Standardization of Semicon-
ductor Machinery (Packaging Standardization Committee) of the National Technical
Committee for Standardization of Semiconductor Devices. With the establishment of
packaging standardization committee, China’s packaging standardization will usher
into new opportunities and development.

Standardization of Package Outlines and Package Naming

The standardization of package outlines internationally is carried out earlier,

generally using standard supplement or dimension registration. (1) IEC 60191-2,
issued by IEC SC47D, “Mechanical standardization of semiconductor devices.
Part 2: Dimensions” continuously releases supplements to complement the new
form of packages. A large number of new packaging proposals are submitted to the
IEC every year, among which are submitted to the IEC by various national
standardization committees. As long as the number of countries that have reached
the required number agrees with the draft standard, standardization work can be
carried out. (2) JEP 95 is issued by JEDEC as “Registered and standard outlines for
solid state and related products,”, which is similar to IEC SC47D, proposed by its
member companies. As such IEC SC47D and JEDEC can ensure that the package
outlines are constantly updated, and the new package is standardized and
promoted.
In the 1980s and 1990s, China’s work on the standardization of semiconductor
package outlines is mainly GB/T 7092-93 “Outline dimensions of semiconductor
IC,” GB/T 15138-94 “Case outlines for film ICs and hybrid ICs,” and GB/T 7581-
87 “Dimensions of outlines for semiconductor discrete devices.” However these
three standards have not been updated since their releases. With the continuous
advancement of semiconductor technology, packaging technology is geared to the
needs of new devices in the direction of miniaturization, lightweight, and high-
density integration. The new packaging such as Ball Grid Array (BGA), Column
61 Standardization of Integrated Circuits Packaging 1211

Grid Array (CGA), Chip Size Package (CSP), Wafer Level Packaging (WLP), and
3D packaging continue to emerge, and the relevant national standardization is
urgently needed.
For the packaging naming standardization, the standardization organizations from
various countries have different outlines of packaging naming. IEC 60191-2
(“Mechanical standardization of semiconductor devices Part 2: Dimensions”) spec-
ified the standards of package dimensions and outlines for Japan, United States (US),
United Kingdom (UK), and other countries or regions. GB/T 7092-93 “Outline
dimensions of semiconductor IC,” etc., also provides the corresponding naming
method in China. In order to solve the problem of inconsistent naming of package
outlines in various countries, IEC 47D released IEC 60191-4 “Mechanical standard-
ization of semiconductor devices – Part 4: Coding system and classification into
forms of package outlines for semiconductor device packages”; it is named
according to the characteristics of package outlines. The conversion work of this
standard has been included in the 2015 national standard revision plan, and the
standard approval work has been completed and will be officially released.

National Standards for IC Packaging

The packaging standards in China are mainly defined by terms, dimensions, test
methods, and lead frame and packaging material associated standards. (1) GB/T
14113-1993 “Terminology of packages for semiconductor integrated circuit” mainly
specifies the basic terminology of semiconductor IC package in manufacturing,
application, and product inspection. (2) The outlines standard includes GB/T
7092-93 “Outline dimensions of semiconductor IC” and GB/T 15138-94 “Case
outlines for film IC and hybrid IC,” of which GB/T 7092-93 mainly specifies the
dimensions of semiconductor ICs, including flat package (FP), ceramic flat package
(CFP), dual in-line package (DIP), ceramic dual in-line package (CDIP), plastic dual
in-line package (PDIP), metal can package, small outline package (SOP), plastic
leaded chip carrier (PLCC), ceramic leadless chip carrier package (CCC), plastic
quad flat package (PQFP), quad flat package (QFP), and pin grid array (PGA).
(3) The test method standards include GB/T 14862-93 “Junction-to-case thermal
resistance test methods of packages for semiconductor IC” and GB/T 16526-1996
“Test method measuring the lead-to-lead and loading capacitance of package leads,”
which are all based on SEMI standards, specify the basic test methods of package
characteristics, such as thermal resistance and lead capacitance. (4) In terms of lead-
frames and packaging materials, the lead-frames standards have been established for
common package outlines such as DIP, Lead Carrier Package, SOP, and QFP, as well
as packaging material standards such as bonding wires, epoxy molding compounds,
glass powder, etc. China packaging standards related to IC packaging are shown in
Table 61.1.
1212 L. Luo et al.

Table 61.1 China packaging standards related to integrated circuits packaging

GB/T 14113-93 Terminology of package for semiconductor integrated circuits
GB/T 7092-93 Outline dimensions of semiconductor integrated circuit
GB/T 15138-94 Case outlines for film integrated circuits and hybrid integrated circuits
GB/T 7581-87 Dimensions of outlines for semiconductor discrete devices
GB/T 14862-93 Junction-to-case thermal resistance test methods of packages for
semiconductor integrated circuits
GB/T 16526-1996 Test method measuring the lead-to-lead and loading capacitance of package
leads
GB/T 14112-2015 Semiconductor integrated circuits – Specification for stamped lead-frames
of plastic DIP
GB/T 15877-2013 Specification of DIP lead-frames produced by etching
GB/T 16525-2015 Specification of lead-frames for plastic leaded carrier package
GB/T 15878-2015 Semiconductor integrated circuits – Specification of lead-frames for small
outline package
GB/T 15876-2015 Semiconductor integrated circuits – Specification of lead-frames for plastic
quad flat package
GB/T20254.1-2015 Copper and copper alloy strips for lead frame – Part 1: Flat strips
SJ/T 10424-93 Glass powder for passivation packaging for use in semiconductor devices
GB/T 8750-2014 Gold bonding wire for semiconductor package
SJ/T 11168-1998 Solder-wire for soldering cleanout-free
SJ 2659-86 Resin-cored soldering wire for electronic industry
SJ/T 10675-2002 Silicon dioxide micro-powder for electronic and electrical equipment industry
SJ/T 11197-2013 Epoxy molding compound

China’s National Military Standard (GJB) and US Military Standards

The packaging specifications are divided into general and detailed specifications
according to the military standard level, including semiconductor IC packages
(ceramic cases such as Ceramic Leaded Chip Carrier (CLCC), Small Outline
Package (CSOP), Ceramic Pin Grid Array (CPGA), CDIP, CFP, Ceramic Quad
Flat Package (CQFP), Ceramic Small Out-line J-leaded Package (CSOJ),
Ceramic Ball Grid Array (CBGA), Ceramic Land Grid Array (CLGA), etc.),
hybrid IC packages, semiconductor discrete device packages, and semiconductor
optoelectronic device packages. All have been used in domestic military produc-
tion lines. The detailed specification is mainly prepared by the military enter-
prises to guide the development, production, and inspection of the product to
meet the needs of the user. Overall, the hierarchy is complete and reasonable.
GJB 548B-2005 “Test methods and procedures for microelectronic device” is
mainly used in the aspect of packaging test method. For some specific packages,
the test methods are developed, such as GJB 7677-2012 “Test methods for ball
grid array (BGA).” China military packaging standards related to IC packaging
are shown in Table 61.2. Because of the versatility of the military and civil
packaging standards, there are not a lot of types and quantities of
military package standards at home and abroad. Military basic standards (such
61 Standardization of Integrated Circuits Packaging 1213

Table 61.2 China military packaging standards related to integrated circuits packaging
GJB 1420B-2011 General specification for packages of semiconductor integrated circuits
GJB 2440A-2006 General specification for packages of hybrid integrated circuits
GJB 7677-2012 Test methods for ball grid array (BGA)
GJB 923A-2004 General specification for packages of semiconductor discrete devices
GJB 5438-2005 General specification for packages of semiconductor photoelectron devices

as terms, definitions, dimensions, and test methods) can refer to the civil stan-
dards by supplement, so there is no need to develop separately. Military standards
need to be developed only at the different requirements for the application
environment and reliability.
Foreign military IC packaging standardization organizations mainly include the
US military standards (MIL) [3], the north Atlantic treaty organization standardiza-
tion agreement (STANAG), and the Japanese military standard NDSC, among which
MIL is representative. The standard for military devices packaging is mainly
MIL-STD-1835D (2004) “Electronic component case outlines,” issued by the US
military (MIL), which mainly specifies the type, structure, size, and symbol of the
military IC packages of 19 categories, mainly ceramic and metal package. For the
performance and reliability requirements of the package, the US military generally
includes it in the general specifications of the device (such as MIL-PRF- 38534
hybrid micro-circuit, general specification, MIL-PRF-38535 ICs manufacturing, and
general specification), so it does not have an individual specification for packaging.
Other foreign institutions (such as NASA, ESA, and JAXA) currently have no
relevant packaging standards.

Joint Electronic Device Engineering Council (JEDEC) Standards

There are varieties of electronic devices. The respective standards are generally set
by some developed countries or organizations. Regarding the standards in the field
of electronic packaging and testing, presently the most adopted standard organiza-
tion is JEDEC. It is an authoritative organization in microelectronic industry stan-
dards. Since its foundation in 1958, it has focused on setting standards in the field of
semiconductor. The platform of JEDEC gathers more than 100 manufactures of
advanced component and application quotient and therefore ensures the progres-
siveness and representativeness. JEDEC is also an open standard organization with
members coming from those possessing manufacture capability from all over the
world. (1) Features of JEDEC standards: JEDEC mainly engage in the terms,
definitions, and symbols related with semiconductor, appearance, assurance of
radiation, requirement for respective experiments, guideline for the purchase of
micro-circuit, test and experimental methods, failure analysis, quality control, and
a variety of products (including discreet component, memory, interface circuit, and
digital logic circuit, etc.). The core business of JEDEC is to promote the
1214 L. Luo et al.

establishment of the standard, which is based on open, easy to get, fast accomplish-
ment. JEDEC committee is leading the standard establishment in a broader technol-
ogy field, including the coordination with other organizations. The procedure of
establishing the standard includes integrating the manufacturers and suppliers,
associating with 15 committee, and 45 sub-committee. Since 2011, JEDEC
established JC-11, JC-14 committee, etc., and started the standardizing in 3D
packaging and also announced the standards in evaluating the reliability of 3D
packaging as well as the design rule of I/O arrangement, etc., supporting the
development in electronic packages. (2) JEDEC committee and sub-committee:
The board of management is in charge with the establishment of corresponding
committee for the standardization. The responsibility of every committee is to
propose the respective standard, make the policy and program, and then deliver to
the board of management for voting or approval. The service committee is dedicated
to the development of industry, including the appearance of the packages, definition
and terminology, the standard of the government, and the international standards,
etc. The product committee is dedicated to the respective technologies of the
assigned products (e.g., test method, specification of the devices, form format,
minimum configuration, lead and wiring, I/O requirement and applications, etc.).
Table 61.3 lists the assignment of responsibility of JEDEC committees.
JEDEC standard inquirers can log on to the JEDEC official website www.
jidec.org and click on the “STAND & DOCUMENT” link to see the classification of
JEDEC standard (see Table 61.4).
Inquirer can query the corresponding criteria by entering each entry from the
above list. Once you have registered, you can read or download the appropriate
standard documentation.

Association Connecting Electronics Industries (IPC) Standards

Association connecting electronics industry (formerly known as institute of printed

circuit, IPC) aims to enhance the competitive advantages of more than 3700 member
companies and help them achieve commercial success. IPC’s member companies
cover all aspects of the electronics industrial chain, including design, PCB, electronic
assembly, and testing. The services provided by IPC include industry standards,
training certification, market research and environmental protection, and meet the
global demand of 2 trillion US dollars of industry through various projects. IPC
provides business cooperation networks and information exchange platforms includ-
ing technology, management, and market for the global electronics industry. Since set
up in 1957 by six PCB companies, IPC has more than 3700 member companies. IPC
establishes its first office in China in 2002 and starts to provide close-range services to
Chinese electronics companies. To date, China has more than 500 member companies.
IPC greater China is headquartered in Qingdao, and with offices in Shanghai,
Shenzhen, Beijing, Suzhou, Chengdu, and Taipei. Through the volunteer organiza-
tions such as the board of directors, PCB management council, EMS management
council, PCB supplier management council, SMEMA council, solder evaluation
61 Standardization of Integrated Circuits Packaging 1215

Table 61.3 Assignment of responsibility of JEDEC committees

Committees Assignment of responsibility Subcommittees and their responsibilities
JC-10 Terms, definitions, symbols
JC-11 Mechanical standardization JC-11.1: Editing transactions and
procedures
JC-11.2: Design requirements
JC-11.4: Uncased devices
JC-11.5: Package interface (not active)
JC-11.7: IEC interface
JC-11.10: Microelectronic ceramic
packages
JC-11.11: Microelectronic plastic packages
JC-11.13: Semiconductor package and
related pressure gauges and tools (not
active)
JC-11.14: Microelectronic assemblies
JC-13 Government liaison JC-13.1: Discrete devices
JC-13.2: Microelectronic devices
JC-13.4: Rad-hard: Assurance-
characterization
JC-13.5: Hybrid, RF/microwave, and MCM
technology
JC-14 Quality and reliability of solid JC-14.1: Reliability test methods for
state products packaged devices
JC-14.2: Wafer-level reliability
JC-14.3: Silicon devices reliability
qualification and monitoring
JC-14.4: Quality processes and methods
JC-14.6: Failure analysis
JC-14.7: Gallium arsenide reliability and
quality standards
JC-15 Thermal characterization
techniques for semiconductor
packages
JC-16 Interface technology
JC-22 Diodes and thyristors JC-22.1: Thyristors
JC-22.2: Rectifier diode
JC-22.4: Signal and adjustment diode
JC-22.5: Transient voltage suppressor
JC-25 Transistor
JC-40 Digital logic JC-40.1: Digital logic families and
applications
JC-40.3: Registered memory support logic
JC-40.4: Fully buffered memory support
logic
JC-40.5: Logic validation and verification
JC-42 Solid state memories JC-42.2: SRAM memories
JC-42.3: DRAM memories
JC-42.3B: DRAM functions and features
JC-42.3C: DRAM parameters
JC-42.3D: DRAM pinouts
(continued)
1216 L. Luo et al.

Table 61.3 (continued)

Committees Assignment of responsibility Subcommittees and their responsibilities
JC-42.4: Non-volatile memory devices
JC-42.6: Low power memories
JC-45 DRAM modules JC-45.1: Registered DRAM modules
JC-45.2: Unbuffered DRAM modules
JC-45.3: Small DRAM modules
JC-45.4: Fully buffered DRAM modules
JC-45.5: Module interconnect
JC-63 Multiple chip packages
JC-64 Embedded memory storage and JC-64.1: Electrical specifications and
removable memory cards command protocols
JC-64.2: Form, fit, and climatic/
environmental methodologies
JC-64.3: Host controller
JC-64.8: Solid state drives
JC-65 Radio frequency identification
devices (RFID)
IEC SC47D Mechanical standardization of WG-1: Package form
semiconductor devices WG-2: Terms, definitions, methods, and
procedures

Table 61.4 Classification of JEDEC standard

Committees Document types
JC-10: Terms, definitions, and symbols (17) 1. JESD (JEDEC Standards) (352)
JC-11: Mechanical standardization (568) 2. JEP (JEDEC Publications) (86)
JC-13: Government liaison (36) 3. JM (JEDEC Manual) (7)
JC-14: Quality and reliability of solid state products (148) 4. J-STD- (Joint IPC/JEDEC
JC-15: Thermal characterization techniques for Standards) (8)
semiconductor packages (29) 5. JS (Joint Standard) (6)
JC-16: Interface technology (32) 6. JP (Joint Publication) (2)
JC-22: Diodes and thyristors (26) 7. JIG (Joint Industry Guide) (2)
JC-25: Transistors (36) 8. JES (JEDEC Specifications) (1)
JC-40: Digital logic (67) 9. JEB (JEDEC Engineering
JC-42: Solid state memories (141) Bulletins) (8)
JC-45: DRAM modules (97) 10. TENTSTD (Tentative
JC-63: Multiple chip packages (3) Standards) (2)
JC-64: Embedded memory storage and removable memory 11. EIA (EIA Standards) (10)
cards (24) 12. More...
JC-65: RFID (1)

council, OEM key components council, printed electronics council, designer council,
market and technical executive committee, and technical activities executive commit-
tee, IPC guides and supervises the association to help the association sense industry
needs, collect industry recommendations, and improve service quality.
61 Standardization of Integrated Circuits Packaging 1217

The business development status of IPC is as follows: (1) Standards develop-

ment: Through the organization of more than 10,000 industry experts worldwide,
more than 220 standards have been successfully developed. The IPC-A-610
standard is one of the most widely used standards in the world and is
recommended by the international electro-technical commission (IEC) as the
global preferred acceptance criteria for electronic components. 41 technical
groups in IPC China have completed the development of 31 standards. (2) Train-
ing and certification: IPC standard training is provided for employees of thou-
sands of electronic companies, and more than 250,000 people have obtained IPC
standard certification. (3) QML and QPL: IPC has introduced two validation
services, that is, IPC qualified manufacturers list (QML), IPC qualified products
list (QPL). QML certification is a highly operative system based on the IPC:
J-STD-001/IPC-A-610 standard for the fabrication process of electronic
manufacturing service enterprise. The QPL certification is a product quality
certification for suppliers’ products in accordance with standards such as lPC
J-STD-004/005/006. (4) Market research: Conduct market research such as IPC
global substrate quarterly statistics, quarterly statistics of solder products, quar-
terly statistics of process consumables, quarterly statistics of assembly equip-
ment, quarterly statistics of electronic manufacturing services, annual survey of
EMS industry, monthly statistics of PCB industry, etc. (5) Public policy initia-
tives: covering the environment, health and safety, international trade, intellec-
tual property protection, corporate social responsibility, etc. (6) Government
relations: IPC represents the electronics industry to provide advices, project
cooperation, and policy advocacy to the government in the process of setting
up a public policy. (7) Industrial projects: such as technical and management
conferences, seminars, lectures, manual welding competitions, and PCB design
competitions. (8) Exhibitions: such as APEX in Las Vegas, USA, IPC ESTC in
Las Vegas, USA, and international printed circuit and IPC APEX South China
fair (Shenzhen). Tree map of IPC standard is shown in Fig. 61.1. The schematic
diagram of IPC standardized quality management is shown in Fig. 61.2.
IPC’s classification of general electronic products is as follows. (1) Level-1
(general electronic products): This type of product mainly refers to products that
are mainly functional consumer electronics, such as radios, televisions, telephones,
computer peripherals, etc. (2) Level-2 (special service electronic products): This type
of product refers to products that require continuous operation and have a long
service life. It is best to keep working continuously (but the requirements are not
strict). Under normal circumstances, there will be no malfunction due to changes in
the use environment. It mainly includes communication equipment, measuring
instruments, etc. (3) Level-3 (high performance electronics): This type of product
refers to a key product that needs to be operated continuously or strictly in accor-
dance with the instructions. It is unacceptable to have an operational interruption in
the process of use, and the use environment is extremely harsh, such as aerospace
equipment, military equipment, life-saving equipment, etc.
1218 L. Luo et al.

Fig. 61.1 Tree map of IPC standard

The training and certification programs provided by IPC include: printed circuit
production requirements (IPC-A-600H), electronic assembly production require-
ments (IPC-A-610F), assembly process requirements (IPC-J-STD-001F), operations
and requirements of rework and repair (IPC-7711/21B), operation requirements of
cable harness assembly (IPC-A-620B), designer certification course (IPC-CID,
CID+), PCB qualification and performance specifications (IPC-6012C), etc.
61 Standardization of Integrated Circuits Packaging 1219

Fig. 61.2 Schematic diagram

of IPC standardized quality
management

Automotive Electronics Council (AFC)-Q100 Standards [11, 12]

The automotive electronics council (AEC) was originally established by the main
automotive manufactory companies for the purpose of establishing general standards
for parts qualification and quality systems for automotive electronics components.
High quality electronic components meeting these specifications are suitable for use
in the harsh automotive environment without additional component-level qualifica-
tion tests. That promotes the willingness of automotive component manufacturers to
exchange the product data. Therefore it in turn promotes the development of the
universal property of automotive components, providing the basis for rapid devel-
opment of the automotive component market. The standard of AEC-Q100 is used for
preventing various possible or potential faults of the automotive component prod-
ucts. The purpose is to guide the supplier of automotive components to use the chips
which conform to the specification during the development of the products.
AEC-Q100 guarantees the quality and reliability for each chip, the manufacturer’s
stated purpose of product use, also the data sheet and the instructions for the
functionality of the product as well as the consistency of the functionality and
properties of the component after continuous usage. The standard of AEC-Q100 is
divided into five grades: the most serious is grade zero with ambient temperature
range 40 ~ 150  C. The second grade is with ambient temperature range 40–
+105  C. The third grade is with ambient temperature range – 40–105  C, and the
fourth grade is with ambient temperature range 0–70  C.

References
1. International Electrotechnical Commission (IEC), https://www.oecd.org/gov/regulatory-policy/
IEC%20profile.pdf
2. M. Hanif, Introduction to IEC standards, https://www.iec.freestandardsdocuments.com
3. SEMI, https://en.wikipedia.org/wiki/SEMI
4. SEMI International Standards: Compilation of Terms, (updated 2018)
5. N. Davis, The History and Basics of IPC Standards: The Official Standards for PCBs. (October
20, 2017). https://www.allaboutcircuits.com/news/ipc-standards-the-official-standards-for-pcbs/
1220 L. Luo et al.

6. Z. Peterson, IPC Classes and Complying with IPC Standards for PCB Design. (June 4, 2021).
https://resources.altium.com/p/complying-with-ipc-standards-for-pcb-design
7. JEDEC, https://en.wikipedia.org/wiki/JEDEC
8. Standards & Documents Search | JEDEC, https://www.jedec.org/standards-documents
9. SEMI G30 – Test method for junction to case thermal resistance measurement of ceramic
packages. G Series: Packaging
10. SEMI G24 – Test method for lead to lead and loading capacitance of package leads. G Series:
Packaging
11. R. Oshiro, Fundamentals of AEC-Q100: What “Automotive Qualified” Really Means. https://
media.monolithicpower.com/mps_cms_document/w/e/Webinar_-_Fundamentals_of_AEC-
Q100-6Nov2018.pdf
12. AEC Documents, http://www.aecouncil.com/AECDocuments.html
 Section VIII
IC Equipment
Tianchun Ye, Zhiyao Yin, Jinrong Zhao, Yuan Pu, and Baoqin Chen

Introduction

Since the invention of integrated circuits (ICs) in the 1950s, the IC industry has been
developing rapidly while following the model of “one generation of equipment and
processes for each generation of products.” Therefore, IC manufacturing and testing
equipment serves as the guide and core of industrial technology upgrading and
development.
IC manufacturing often requires more than 1000 process steps, and each step
relies on the process of specific equipment to achieve it. Manufacturing and testing
equipment is the carrier of core technologies and processes of IC, and forms the
foundation of IC industrial development. It integrates human’s ultra-fine processing
technologies and represents the highest level of microfabrication in the world today.
Therefore, the IC industry is a comprehensive embodiment of a country’s high-end
manufacturing capabilities and commands huge strategic significance in global high-
tech competition among countries.
The continuous improvement of chip integration density not only makes the
internal structure and production processes of chips innovative but also sets forth
new requirements for the equipment and technologies that the production processes
rely on. At present, the accuracy of many processing technologies is close to
physical limits, raising the performance requirements for IC manufacturing equip-
ment and making the R&D of advanced equipment more challenging.
This section covers 13 topics, namely wafer manufacturing equipment, mask
manufacturing equipment, photo lithography equipment, diffusion and ion implan-
tation equipment, thin-film growth equipment, plasma etching equipment, wet
etching equipment, process testing equipment, assembly and packaging equipment,
main common module and parts, metrology and inspection equipment, and other
related equipment on the production line. This Section covers most kinds of equip-
ment related to IC manufacturing and briefly introduces the development of this
industry in China and other countries.
The Development of the IC Equipment
Industry 62
Guoming Zhang

Contents
The Development of International IC Equipment Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Development of the Global Semiconductor Equipment Market . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Overview of Major Global Semiconductor Equipment Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . 1226
Development Characteristics of the Worldwide IC Equipment Industry . . . . . . . . . . . . . . . . . . . . . . 1226
Overview and Characteristics of the Semiconductor Equipment Industry
in the United States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
Overview and Characteristics of the Semiconductor Equipment Industry in Europe . . . . . 1227
Overview and Characteristics of the Semiconductor Equipment Industry in Japan . . . . . . 1228
Overview and Characteristics of the Semiconductor Equipment Industry in the
Republic of Korea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
The Development Phases of IC Industry in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
“Self-Reliant” Entrepreneurship (1956–1979) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
Exploration and Development with “Introduction and Transformation” (1980–1999) . . . 1230
Rapid Pursuit with “Strategic Adjustment and Policy Support” (2000–present) . . . . . . . . . . 1231
The Development Status of the IC Equipment Industry in China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
Overview of the Chinese IC Equipment Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
Recent Development of Chinese IC Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
A Few Thoughts on the Chinese IC Equipment Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235

Abstract
IC manufacturing represents the highest level of ultra-micro machining technol-
ogy today and continues to set the standards of manufacturing equipment.
Equipment plays the most important role in the IC industry chain. After more
than 60 years of development since the invention of IC in 1958, the IC equipment
industry has undergone great changes. This chapter briefly introduces the

G. Zhang (*)
NAURA Technology Group Co., Ltd., Beijing, China
Hwatsing Technology Co. Ltd., Tianjing, China
e-mail: gmzhang@hwatsing.com

© Publishing House of Electronics Industry 2024 1223

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_62
1224 G. Zhang

development status and characteristics of IC equipment worldwide, including the

development history and the current development situation of equipment industry
in China.

Keywords
IC equipment · Development history · Industrial status · Characteristics · IC
industrial chain · Integrated circuit

The Development of International IC Equipment Industry

Development of the Global Semiconductor Equipment Market

The global semiconductor industry and corresponding equipment sales have been
growing steadily over the past decade, however, due to the emergence of new
applications in multiple markets, such as the electronization of traditional automo-
biles, electric vehicles, 5G and 6G communications, green energy, IoT, artificial
intelligent (AI), high-performance computing (HPC), medical electronics, etc., the
global semiconductor industry has shown a significant rapid growth since 2020,
which requires more investments to expand the production capacity to meet the
market demands. Therefore, as shown in Fig. 62.1, this is the highest investment on

Fig. 62.1 Global sales of semiconductor equipment. (Data source: SEMI)

62 The Development of the IC Equipment Industry 1225

record in the IC industry for three consecutive years (2020–2022), and the record fab
construction has driven total sales of semiconductor manufacturing equipment past
the $100 billion mark for two consecutive years (2021–2022). In which, total global
semiconductor manufacturing equipment sales by original equipment manufacturers
reached a new high of $107.64 billion in 2022, an increase of 4.91% over the
industry record of $102.64 billion in 2021.
In the past decade, the global semiconductor industry has maintained a steady
growth. After the completion of this stage of the global fab building wave, it is
expected that the total global semiconductor manufacturing equipment market in
2023 will temporarily shrink to 91.2 billion US dollars, due to the weakening chip
demand and the higher inventory of consumer and mobile devices. Thereafter, the
whole market will rebound by the subsequent capacity expansion stage from 2024.
The front-end and back-end equipment markets will continue to promote the growth
of the global semiconductor manufacturing equipment market. It is estimated that
equipment sales in 2028 will reach 149.8 billion, with a compound annual growth
rate (CAGR) of 10.4%.
In the next few years, the Asia-Pacific region will continue to be the most active
semiconductor equipment market. In Fig. 62.1, mainland China, China Taiwan, and
Republic of Korea remain the top three destinations for equipment spending through
2022. In addition, mainland China was the world’s largest semiconductor equipment
market for the third consecutive year in 2022, with revenues still reaching $28.3
billion despite a 5% year-on-year slowdown in investment in the region. The second
largest equipment spending destination was China Taiwan region, which grew 8%
annually to $26.8 billion, its sixth consecutive year of growth. Sales of equipment to
Republic of Korea fell 14% to $21.5 billion. Europe’s annual semiconductor equip-
ment investment soared from 3.25 billion in 2021 to 6.28 billion in 2022, with an
annual growth rate of 93%, while North America’s semiconductor equipment
investment rose from 7.61 billion in 2021 to 10.48 billion in 2022, with a growth
rate of 38%. Japan’s equipment investment also rose from 7.8 billion in 2021 to 8.35
billion in 2022, an increase of 7%. The rest of the world will invest a total of $5.95
billion in equipment in 2022, an increase of 34% compared to 2021. With the
exception of Republic of Korea, equipment spending in all the regions mentioned
have grown in 2022, although most regions will decline in 2023 before returning to
growth in 2024.
China Taiwan is expected to maintain its global lead in fab equipment spending
through 2024, with investments of $24.9 billion, up 4.2% year on year (YOY),
followed by Republic of Korea with investments of $21 billion. Export controls by
the United States are expected to limit the fab equipment spending in the China
region to $16 billion, matching the investments in the China region in 2023.
Therefore, it is expected that by 2024, mainland China will rank third in the global
spending on the imported fab equipment. Due to China’s efforts to promote the
development of domestic equipment, the investment in domestic equipment will
increase significantly, and the total investment in wafer fab equipment will still be
the first in the world.
1226 G. Zhang

Overview of Major Global Semiconductor Equipment Suppliers

The United States, Japan, and the Netherlands are major players in the IC equipment
manufacturing industry. Specifically, the United States holds a leading position in
such fields as plasma etching equipment, ion implanters, epitaxial growth systems,
chemical vapor deposition (CVD) systems, sputtering equipment, annealing equip-
ment, copper plating equipment, photoresist stripping equipment, mask manufactur-
ing equipment, process testing equipment, wafer cleaning equipment, and some
parameter measurement equipment. Japan maintains competitive advantages in
such fields as photo lithography systems, photoresist coating equipment, developing
equipment, packaging and testing equipment, oxidizing/LPCVD equipment, plasma
etching equipment, CVD equipment, testing equipment, and wafer transmission
systems. Meanwhile, the Netherlands is taking a leading position in the manufactur-
ing of advanced photo lithography systems.
The development of international semiconductor equipment enterprises started in the
1960s. After over half a century, the number of these enterprises has dropped from
several hundred during the industry’s heyday to several dozen at present due to mergers,
acquisitions, and integration. The top ten enterprises account for about 80% of total
market share, while market segments are becoming increasingly monopolized, creating
a “Matthew effect” [1] situation. Major global wafer manufacturers include Applied
Materials, ASML, Tokyo Electron Limited, Lam Research, KLA-Tencor, Screen Semi-
conductor Solutions, Hitachi High-Technologies, Nikon, Hitachi Kokusai, and ASM
International. These companies are mainly headquartered in the United States, Japan,
and the Netherlands.

Development Characteristics of the Worldwide IC Equipment

Industry

IC manufacturing technology represents the highest level of micro-manufacturing in

today’s world. It integrates modern ultra-fine processing technologies and is one of
the core technologies of the information industry. As one of the important founda-
tions of the IC industry, semiconductor equipment is a key portion in the entire
industrial chain. Because its development represents the R&D capabilities of high-
tech, it is also a key point of huge strategic importance in high-tech competition
among countries.

Overview and Characteristics of the Semiconductor Equipment

Industry in the United States

The semiconductor equipment industry of the United States has developed along with
the technical progress of the chip manufacturing industry. The United States is very
competitive in such fields as etching equipment, Plasma Enhanced Chemical Vapor
Deposition (PECVD) equipment, Physical Vapor Deposition (PVD) equipment, ion
62 The Development of the IC Equipment Industry 1227

implanters, testing equipment, and heat treatment equipment. The semiconductor

industry is originated in the United States. For most of the industry’s history, the United
States maintained a global leading position and set forth new requirements for semi-
conductor equipment to boost the development of equipment manufacturers [2, 3]. At
one point in the 1980s, Japan surpassed the United States in areas such as memory. In
order to compete with Japan in the memory industry and regain its share in the
semiconductor market, 13 major semiconductor companies, including IBM, Intel,
and HP, formed the Semiconductor Manufacturing Technology (SEMATECH) con-
sortium with the support of the US government in 1987. This consortium was founded
with the goal to integrate and share the financial resources of its member companies,
distribute the technical and financial risks of research and development, and promote
the status and visibility of US semiconductor manufacturing technology. It was also
intended to strengthen the development of new technologies through the cooperation
between the upstream and the downstream of the industrial chain, and accelerate the
development of the US semiconductor industry. In the 1990s, with support of the US
government, US semiconductor companies regained their leading position in the global
industry [4, 5]. The main competitiveness of US semiconductor equipment companies
is reflected in their technical innovation. They maintain their leading position in various
technologies through the close cooperation with major customers. To this end, com-
panies invest a large amount of financial resources in the R&D of new technologies,
and their R&D expenses usually cost 10–15% of their annual sales. For example, three
US companies, Applied Materials, Lam Research, and KLA-Tencor, maintain technical
leading positions and high market shares in the three fields of thin-film equipment,
etching equipment, and metrological equipment, respectively. Meanwhile, the
innovation-friendly tax policies of the US government, an advanced financing system,
and abundant talent resources also greatly boost the development of the semiconductor
equipment industry in the United States.
Besides companies’ investment in R&D, semiconductor equipment technologies
also require complicated collaborative research (including basic research, process
technology research, and optimization technology research). Each component inter-
acts with the others and is indispensable. Moreover, the R&D cycle is very long and
needs a continuous inflow of funds. In terms of basic research, top universities and
research institutes of the United States can provide strong support for related
companies’ technical innovation. Sufficient human resources and the multi-
disciplinary advantages of US scientific research institutes make it possible for
companies to cooperate with universities or research institutes to accelerate the
R&D of products, break through common technical bottlenecks in the industry
and core technologies, and share achievements.

Overview and Characteristics of the Semiconductor Equipment

Industry in Europe

IC equipment companies in various European countries are at different stages of

development. Well-known European IC equipment companies include ASML,
1228 G. Zhang

headquartered in the Netherlands, SUSS, headquartered in Germany, and IMEC,

headquartered in Belgium [6]. As a globally renowned independent public R&D
platform, IMEC serves as an indicator for R&D in the semiconductor industry. It
possesses advanced chip R&D technologies and processes, and has cooperated
extensively with giants in the global semiconductor industry, including Intel,
AMD, Samsung, TSMC, and Applied Materials, creating an exemplary platform
for “open innovation.”
ASML [7] is an internationally respected semiconductor equipment company.
As the largest semiconductor equipment company in Europe, ASML has mas-
tered global state-of-the-art patterning technology. In particular, ASML is still the
only supplier in the world providing commercial equipment for advanced immer-
sion lithography and extreme ultraviolet (EUV) lithography. ASML’s EUV
lithography is regarded in the semiconductor industry as the most important
technology for processes below 10 nm. Moreover, through its merger with
MHI, ASML has acquired measuring equipment for international advanced
processes. ASML owes its success to the Netherlands’ strategy of developing a
knowledge-based economy.

Overview and Characteristics of the Semiconductor Equipment

Industry in Japan

In the early stages, Japanese semiconductor equipment companies gradually

established their own industrial foundation through such means as technical
cooperation with US companies and realized key breakthroughs in several equip-
ment fields with their existing technological reserves and innovation efforts. In
the late 1980s, the center of the global semiconductor industry shifted to Japan.
Through strict production management and intensified quality control, Japanese
companies like NEC, Toshiba, Hitachi, and OKI established leading positions in
the global semiconductor industry with the production of DRAM chips. With the
expansion of the Japanese IC industry, the demand for equipment also grew,
which brought good opportunities for the development of Japan’s semiconductor
equipment industry. Thanks to Japanese semiconductor equipment companies’
comprehensive advantages in such aspects as price, quality, and service, many
Japanese and Korean semiconductor companies, which were expanding their
capacities at the time, preferred Japanese equipment manufacturers. Although
Japan’s economy has gone through a recession since 1990, Japanese IC equip-
ment companies still hold an extremely important position in the global semi-
conductor equipment industry. Main representatives include Tokyo Electron
Limited (TEL), Hitachi, DNS, Nikon, Canon, DISCO, and ULVAC. Currently,
the Japanese IC industrial chain is very advanced and complete, offering the
widest varieties of IC equipment and possessing strong local support for key
components and materials.
62 The Development of the IC Equipment Industry 1229

Overview and Characteristics of the Semiconductor Equipment

Industry in the Republic of Korea

The semiconductor equipment industry of the Republic of Korea has gradually

grown with the development of its flat panel display and IC industry, and is now
advancing rapidly. Specifically, industrial giants such as Samsung and SK Hynix
have played a significant leading role, and equipment companies have established
close partnerships with local users, which have promoted the development of Korean
equipment companies. Except for a few types of equipment such as steppers,
domestic production of the main types of process equipment and components has
been realized, but important equipment used in critical processes still needs to be
imported from other countries such as the United States and Japan.
Looking at the development of the international IC equipment industry, we can
see that its growth has the following characteristics.

1. A high proportion of R&D investment is needed to maintain the continuous

overall competitiveness of the equipment industry.
2. Innovation drives the growth and leads the technology. In accordance with
Moore’s law, links in the semiconductor manufacturing process continue to set
forth higher requirements for the upgrading and technological progress to the
equipment industry.
3. Mergers and acquisitions (Ms&As), and integration accelerate the development
of enterprises. Ms&As, and integration plays an increasingly prominent role in
the semiconductor equipment industry, and they are also important approaches
for major equipment manufacturers to achieve rapid growth and improve their
competitiveness.
4. Production services are outsourced and global high-quality resources are inte-
grated. Non-core business operations are outsourced to independent vendors with
more specialized skills in the related fields or links, and only core value creation
activities are retained. This business model has become a trend, a typical repre-
sentative of which is ASML in the Netherlands.

The Development Phases of IC Industry in China

The development of the IC equipment industry in China can be divided into the
following three stages.

“Self-Reliant” Entrepreneurship (1956–1979)

China began to develop semiconductor technology in 1958. In response to the

international environment at that time, China started its IC R&D in the 1960s.
1230 G. Zhang

During this period, the national government made plans for nearly ten universities,
dozens of research institutes, and state-owned enterprises (SOEs) to conduct the
research on semiconductor technology (processes, equipment, and materials) and
products, and to establish production systems. Through more than 40 years of
entrepreneurship and development, China basically implemented the goal of “inde-
pendence and self-reliance” in semiconductor and IC products, processes, equip-
ment, materials, and other areas. For example, all ICs and transistors used in the first
Chinese transistor computers (the 109B and 109C), IC computers (No. 156 and 151),
million floating-point operations per second computer, and ten million floating-point
operations per second computer (Machine No. 757) were produced domestically.
Moreover, these computers made significant contributions to national projects, such
as “Two Bombs and One Satellite” and ocean surveillance ships.
During this historical period, due to the strict international embargo, the technol-
ogy, equipment, and materials required for the manufacture of domestic integrated
circuits have always relied on independent R&D. With the support of national plans,
a group of universities, research institutes, as well as state-owned enterprises adopted
a nationwide and collaborative approach with the division of responsibilities. Rely-
ing on themselves and starting from scratch, they enabled the domestic semicon-
ductor manufacturing industry to achieve continuous improvement and forge ahead
through difficulties.

Exploration and Development with “Introduction

and Transformation” (1980–1999)

At the beginning of the reform and opening-up period, China witnessed an upsurge in
the introduction of semiconductor production lines. According to the statistics of the
former Ministry of Electronics Industry, the national government invested about RMB
1.3 billion in this area and 24 companies imported 33 upgraded integrated circuit
production lines from different countries to varying extents (mainly 3 ~ 4-inch
production lines).
Due to the lack of domestic industrial experience and factors related to the
contemporary management mechanisms and systems, enterprises that imported
production lines have encountered problems such as the lack of product fabrication
processes, incomplete equipment, and inadequate operating funds (especially R&D
funds), which caused problems in these imported production lines. As domestic
semiconductor manufacturing equipment was outdated, IC production lines could
only be upgraded by importing equipment, thus falling into a vicious cycle in which
“equipment is imported, it then becomes obsolescent, and new equipment is
imported again.” During this period, scientific research institutes and state-owned
enterprises originally engaged in the research and manufacturing of semiconductor
equipment were faced with widespread survival crisis and challenges such as
insufficient R&D funds, lack of interest in their products, and the impact of the
62 The Development of the IC Equipment Industry 1231

entrepreneurship trend. It was difficult for them to survive; therefore, many related
enterprises shifted their focus to other industries.
To break through the problems that emerged later in this “large-scale import”
period, the national government increased its investment in the R&D of IC processes
and equipment, successively organized and implemented major IC projects such as
“Project 908” and “Project 909,” and mobilized local governments to establish the
Northern Microelectronics R&D Base and Shanghai Microelectronics Base. In the
field of R&D of IC equipment, the state had formulated a national agenda for
tackling scientific and technological challenges in eight categories of equipment,
namely, photo lithography equipment, dry etching equipment, ion implanters, mag-
netron sputtering equipment, wafer processing systems, and IC product testing
equipment. In terms of the implementation, although enterprise platforms and
teams had been established and an industrial foundation had been laid to some
extent, the weakness of this foundation and limitations of R&D investment left
domestic equipment R&D in the prototype stages, and there was no ability to
provide domestic equipment to support the manufacturing industry.

Rapid Pursuit with “Strategic Adjustment and Policy Support”

(2000–present)

Since 2000, with the rapid development of information industries such as the
Internet, mobile communications, and intelligent terminals, China’s demand for
chips has increased significantly. As the cornerstones of information technology,
the IC and related equipment industries have attracted an increasing amount of
attention, and the development of the IC industry has become a national strategy.
While increasing the investment in the R&D of science and technology, the national
government has successively released relevant policies to encourage the develop-
ment of the IC industry (such as Documents of No.18-[2007] and No.4-[2011] of the
State Council), thus propelling the Chinese IC industry into a stage of rapid pursuit.
Since the “11th Five-Year Plan”, with the launch and implementation of the
national science and technology major project for “Ultra-Large-Scale IC
Manufacturing Equipment and Whole Sets of Fabrication Processes” (Program
02), China has begun to accelerate the layout of the innovation value chain around
its IC industrial chain. This effort has played a decisive role in the formation of
China’s IC industrial chain of manufacturing, equipment, materials, and packaging,
as well as the improvement of its competitiveness. Starting from scratch, China has
achieved breakthroughs in 300 mm high-end IC manufacturing equipment. Its main
front-end process equipment and advanced packaging equipment, such as etching
equipment, ion implanters, PVD equipment, and LPCVD equipment, have entered
domestic and overseas markets through assessments made by mass production lines.
Although domestic semiconductor equipment has made great progress, there is still a
wide gap between it and advanced international equipment.
1232 G. Zhang

The Development Status of the IC Equipment Industry in China

Overview of the Chinese IC Equipment Market

Since 2010, the scale of Chinese IC manufacturing has been expanding rapidly and
the demand for equipment has been growing continuously, however, the insufficient
supporting capability of domestic equipment has become an increasingly prominent
disadvantage. According to statistics from the China Electronic Production Equip-
ment Industry Association, the revenue from Chinese IC equipment in recent years
was RMB 3 billion yuan (about USD 450 million), accounting for about 1% of the
global market. Major Chinese suppliers of wafer manufacturing equipment are listed
in Table 62.1.
With the demands of cloud computing, big data storage for memory chips (mainly
3D NAND), and the boom of the IC manufacturing industry in China, the global IC
equipment market is expected to develop rapidly in the next few years. In 2018,
China became the fastest-growing region in the global semiconductor market with a
growth rate of 56%.
At present, China has achieved great progress in IC manufacturing equipment.
Domestic products have already replaced some specific products and have even
become customers’ baseline equipment. However, generally speaking, factors such
as the complexity and high cost of IC equipment technologies, the decisive role
played by key equipment in chip performance, and long-term customer habits have
led to the formation of a long-standing and relatively fixed pattern in the IC
equipment market. This brings obstacles and challenges for newcomers to the
market.
In such fields as advanced packaging, LED chips, and photovoltaic
(PV) manufacturing, the substitution rate of domestic equipment has increased
significantly. Specifically, domestic supporting capabilities already exist for the

Table 62.1 Major Chinese suppliers of wafer manufacturing equipment

Equipment
Plasma etching equipment
Chemical vapor deposition equipment
Ion implanters
Photo lithography equipment
Physical vapor deposition equipment
Oxidation diffusion furnaces/LPCVD/
annealing equipment
Atomic layer deposition equipment
Cleaning and wet etching equipment
Chemical mechanical polishers
Photoresist coating and developing
equipment
Testing equipment
Supplier
AMEC, NAURA
Shenyang Piotech, NAURA, AMEC
Beijing Zhongkexin, Shanghai Kingstone, CETC48
SMEE, Chengdu Institute of Optics and Mechanics,
Shanghai NANPRE
NAURA
NAURA, CETC48
NAURA, Shenyang Piotech
NAURA, Shanghai ACM, Shenyang KINGSEMI
Tianjin Hwatsing, Shanghai ACM, CETC45
Shenyang KINGSEMI
Shanghai Raintree, DJEL, Skyverse
62 The Development of the IC Equipment Industry 1233

whole production line of LED chips and PV manufacturing equipment. At present,

the domestic equipment occupies the mainstream in the market, which shows that
domestic equipment is closely related to customers’ control over fabrication pro-
cesses. In the future, with the rapid growth of the Chinese IC manufacturing industry
and further improvements in process integration, domestic equipment in technolog-
ical achievement is expected to realize the breakthrough in quality.
In the coming decade, China is set to become a main growth engine of the IC
manufacturing industry, with a new boom in plant construction on the horizon. As of
March 2019, there were more than 20 IC production lines under construction and
preparation in China, which creates a huge demand for IC equipment and brings
unprecedented opportunities for the development of domestic equipment.

Recent Development of Chinese IC Equipment

The period since the “12th Five-Year Plan” has seen the fastest rate of development
in Chinese IC equipment. In terms of technology, before the implementation of the
national science and technology major project Program 02 in 2008, China did not
produce any 300 mm equipment and only produced two types of 200 mm equip-
ment. Currently, the main types of key 300 mm equipment have been applied in
batches on the major IC production lines, and the overall mass-production processes
have reached the technology node of 28 nm. A variety of key equipment for
14–10 nm processes has entered customers’ production lines. Some equipment
for 7–5 nm processes has been approved for multiple applications in the experimen-
tal production lines of leading global customers. In terms of domestic equipment
manufacturers, some excellent enterprises have emerged. For example, dielectric
etching equipment and Through Silicon Vias (TSV) etching equipment developed
by AMEC have continuously replaced the equipment of American monopolies in the
production lines of world-class domestic and international customers, and are widely
used by leading customers around the world. In addition, NAURA is the Chinese
company providing the most types of IC manufacturing equipment. Its products
mainly include etching equipment, PVD equipment, oxidation furnaces, LPCVD
equipment, ultra-fine cleaning machines, atomic layer deposition equipment, epitaxy
equipment, and gas mass flow meters, all of which are now widely used in major
domestic and international production lines. Furthermore, a range of domestic
300 mm high-end equipment, such as Zhongkexin’s ion implanters, Shenyang
Piotech’s PECVD equipment, Shanghai ACM’s cleaning machines, Shenyang
KINGSEMI’s spin coaters, Shanghai Raintree’s optical size measuring equipment,
and Tianjin Hwatsing’s CMP equipment, has been used in batches by domestic and
international customers. In terms of major key equipment in the IC field, China has
basically established its own R&D capabilities and has achieved significant improve-
ments in its domestic supporting capabilities.
Moreover, to expand the technology application of domestic IC front-end process
equipment to the area of advanced packaging can not only enhance the local
supporting capabilities of China’s packaging field, but also accelerate the rapid
1234 G. Zhang

development of the packaging industry. During the “12th Five-Year Plan” period,
domestic complete sets of advanced packaging equipment, such as etching equip-
ment, PVD equipment, spin coaters, photo lithography equipment, PECVD equip-
ment, and cleaning equipment, have replaced imported ones in batches, and their
technical specifications have reached the international advanced level. In addition,
the superior after-sales service and the cost-effective equipment reduce the invest-
ment cost for China’s advanced packaging industry and also enhance the competi-
tiveness of domestic industries. Furthermore, owing to the improvement of
enterprises’ R&D capabilities and the continuous accumulation of core technologies,
domestic equipment has begun to replace imported equipment in large proportions in
pan-semiconductor fields such as LED, MEMS, and power devices, and has
achieved better results.
Besides the improvement of whole machines, local supporting capabilities of key
components have also been enhanced. During the “12th Five-Year Plan” period, a
number of domestic components, such as gas mass flow meters, vacuum dry pumps,
manipulator arms, and reaction chambers have achieved localized manufacturing,
and have been applied and sold in whole machine systems. However, in general, the
application of domestic components in high-end equipment for IC manufacturing
needs to be further intensified.

A Few Thoughts on the Chinese IC Equipment Industry

Although the domestic IC equipment industry has achieved a certain degree of

progress, a large gap remains between Chinese enterprises and advanced foreign
enterprises in terms of technical level and large-scale supply capability, which
requires continuous and effective R&D investment as well as technological
upgrading. In this period of intensive investment and rapid development in the
Chinese semiconductor manufacturing industry, there is an urgent need to enhance
the scale of development and the technological innovation capabilities of Chinese
semiconductor equipment manufacturers. These efforts should focus on the follow-
ing five aspects.

1. Accelerate the development of local suppliers of key components, reduce costs,

improve service quality, and increase the comprehensive competitiveness of the
domestic equipment industry.
2. Concentrate resources, invest in priorities, implement the large enterprise strategy
of alliance between giants, and participate in international competition. Interna-
tionally, IC equipment is becoming increasingly centralized, the technical diffi-
culty is growing, and the requirements for talent teams, R&D investment, and
corporate strength are very high. Without powerful comprehensive strength and
industrial scale, it is hard to compete with international leading companies.
3. Strengthen overall cooperation with leading local and international users,
improve the ability to develop advanced technologies, expand the application
scope of equipment, and realize the basic goal of developing from “pursuit” to
62 The Development of the IC Equipment Industry 1235

“advancing at an equal pace” or even “leading in some aspects.” Since the

massive financial investment is required in the early stage of semiconductor
equipment R&D and follow-up services, domestic companies need to depend
on strategic cooperation to accelerate technological progress, improve profitabil-
ity, and ensure sustained development.
4. Accelerate the development of professionals and technical teams, and establish an
advanced and effective talent development system. The IC equipment
manufacturing industry is a talent-intensive industry and needs a large supply
of high-quality R&D talents. Talent is one of the key factors in industrial
development. Meanwhile, enterprises also need to establish effective interna-
tional incentive mechanisms to attract domestic and international talents.
5. Accelerate domestic and international integration, mergers, and acquisitions,
deepen international cooperation, and realize mutual benefits and win-win results.

References
1. T. Bol, M. de Vaan, A. van de Rijt, The Matthew effect in science funding. PNAS 115(19),
4887–4890 (2018)
2. J. VerWey, What’s Causing U.S. Semiconductor Equipment Production and Exports to Grow?
(U.S. International Trade Commission, 2019)
3. Revitalizing the U.S. Semiconductor Ecosystem, Report to the President, (2022). https://www.
whitehouse.gov
4. W.J. Spencer, P. Grindley, Sematech after five years: High-technology consortia and
U.S. competitiveness. Calif. Manag. Rev. 35(4), 9–32 (1993)
5. D.H. Robert, Lessons from Sematech – MIT Technology Review, July 25, (2011)
6. IMEC Technology company, Wikipedia, https://www.imec-int.com
7. ASML, https://www.asml.com
Manufacturing Equipment for Silicon Wafer
63
Bin Liu

Contents
Overview of Manufacturing Equipment for Si Wafers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238
Single Crystal (Czochralski) Growth Furnace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
Float Zone Crystal Growth Furnace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Ingot Grinding Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
Slicing Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248
Silicon Wafer Annealing Furnaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
Edge Rounding Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
Lapping Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
Wafer Etching Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
Polishers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
Double-Side Grinders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
Single-Side Grinders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
Edge Polishers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
Double-Side Polishers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276
Single-Side Polishers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278
Final Cleaning Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284

Abstract
This chapter introduces 15 kinds of main silicon wafer manufacturing equipment,
including Single Crystal Growth Furnace, Float Zone Crystal Growth Furnace,
Ingot Grinding Machines, Slicing Machines, Silicon Wafer Annealing Furnaces,
Edge Rounding Machines, Lapping Machines, Wafer Etching Machines, Pol-
ishers, Double-Side Grinders, Single-Side Grinders, Edge Polishers, Double-Side
Polishers, Single-Side Polishers, and Final Cleaning Equipment. For each equip-
ment, we briefly describe process function, basic principle, main structure, basic
parameters, as well as main products in the market and their providers. The

B. Liu (*)
The 45th Research Institute of China Electronics Technology Group Corporation (CETC45),
Beijing, China

© Publishing House of Electronics Industry 2024 1237

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_63
1238 B. Liu

purpose is to give a general concept of the equipment to the readers who are
directly or indirectly involved in the wafer manufacturing industry. Since the
process flow for wafers equal to and less than 200 mm is different from that for
300 mm wafer, only the typical process flow is explained with annotations for
processes implemented specifically by 300 mm equipment.

Keywords
Czochralski · Orientation flat · Multiwire saw · Gettering · Surface damage ·
Wafer erosion · Chemical mechanical polishing · Total thickness variation · Haze
polishing · RCA

Overview of Manufacturing Equipment for Si Wafers

Single crystal silicon wafers (or Si wafers) are the main raw materials for integrated
circuits (IC), discrete semiconductor devices, and power devices. More than 90% of
ICs are manufactured on high-purity and high-quality Si wafers. The quality and
supply chain of Si wafers directly affect the quality and competitiveness of ICs.
Therefore, the Si wafer manufacturing industry is the most fundamental link in the
IC industry chain. While the global market has some degree of demand for 100 mm,
125 mm, 150 mm, and 200 mm Si wafers, the demand for 300 mm Si wafers
continues to expand, as the manufacturing of ICs on larger size wafers can reduce
the cost of production. However, with the increase in the diameter of Si wafers, the
requirements for key parameters, such as the site flatness of wafer surface, residual
impurities attached to the surface, internal defects, oxygen content, etc., are con-
stantly increased. At the same time also put forward higher requirements for Si wafer
manufacturing technology. The manufacturing equipment for Si wafers uses pure
polycrystalline Si material to produce a single crystal Si ingot with a certain diameter
and length, and then perform a series of machining and chemical processing pro-
cedures to make this single crystal Si ingot material into Si wafers or epitaxial Si
wafers. For the preparation of Si wafers with a diameter of 200 mm or less, the
typical technological process is as follows; single crystal growth ! cropping !
peripheral grinding (including flattening or V-groove reference surface treatment) !
slicing ! edge rounding (beveling) ! lapping ! etching ! gettering (annealing,
CVD, and application of backseal) ! polishing ! cleaning ! epitaxy ! packag-
ing, and other processes. For the preparation of Si wafers with a diameter of 300 mm,
the trend is to shorten the technological process, reduce the processing cost, and
improve the geometric accuracy, surface roughness (microroughness), and cleanli-
ness of silicon wafers. The technological process used by different manufacturers
varies, but generally involves the following steps; single crystal growth ! trunca-
tion ! outer diameter grinding (V-groove reference surface treatment) ! slicing !
chamfering ! surface grinding ! (etching) ! edge polishing ! double-side
polishing ! single-side polishing ! final cleaning ! (epitaxy/annealing) !
packaging and other processes. The technological process for Si wafers with a
63 Manufacturing Equipment for Silicon Wafer 1239

diameter of 300 mm is the same as that of Si wafers with a diameter of 200 mm or

less, including the edge rounding step, but the process flow after edge rounding is
different.
The manufacturing equipment for Si wafers described in this section is mainly
used for preparing Si wafers with diameters of 150 mm, 200 mm, and 300 mm in the
market. Although the market demand for Si wafers with diameters of 100 mm and
125 mm is gradually decreasing, the “Si wafers with a diameter of 200 mm or less” in
this section still include Si wafers of these two sizes. Single-side grinders, double-
side polishers, and single-side polishers are process equipment that is selected
according to users’ requirements and technological processes in silicon wafer
manufacturing. Within the industry, the single-side polishers and double-side pol-
ishers used in manufacturing Si wafers with a diameter of 200 mm or less are
collectively referred to as polishers. In the manufacturing of 300 mm Si wafers,
single-side grinders, double-side polishers, and single-side polishers are standard
process equipment, and their functions and performance are greatly expanded and
improved compared with the corresponding equipment used in the manufacture of
200 mm silicon wafers.
It should also be noted that, although certain types of equipment are used in the
manufacturing processes for all Si wafers, such as crystal growth, edge rounding,
etc.; however, considering the different manufacturing requirements for different Si
wafer specifications, a variety of models or series of equipment derived from the
same type of process equipment may have different process parameters, functional
parameters, and equipment cost. In addition, the manufacturing equipment for Si
wafers described in this section does not include equipment used to manufacture
epitaxial wafers or SOI substrates.

Single Crystal (Czochralski) Growth Furnace

A single crystal growth furnace is a type of process equipment which heats high-
purity polycrystalline silicon material into a melted (liquid) state in a closed envi-
ronment protected by a high vacuum or inert gas (formerly inert gas), so as to form a
monocrystalline silicon ingot with certain external dimensions. The operating prin-
ciple of the single crystal growth furnace is the physical process to recrystallize the
polycrystalline Si raw material into a monocrystalline Si ingot.
The single crystal growth furnace is also known as the Czochralski (CZ) single
crystal furnace, as shown in Fig. 63.1. The structure of the single crystal growth
furnace is mainly composed of a quartz crucible, graphite crucible, heater, heat
shield, cooling device, crucible support, spill tray, and electrode. The operating
principles are as follows: After adding a certain amount of polycrystalline silicon
raw material to the quartz crucible of the single crystal furnace, the quartz crucible is
heated to the polycrystalline Si melting temperature (1420  C), so that the Si material
is melted and the quartz crucible is filled with molten Si. Then the heating power is
slowly reduced to keep a stable furnace temperature. After the molten Si melt has
cooled, the seed rod of the CZ furnace is moved downward by a pulling mechanism.
1240 B. Liu

Fig. 63.1 Schematic of a

single crystal growth furnace

The Si seed is held by a chuck at the front section of this seed rod. The seed is a
small-size silicon single crystal with the same crystal orientation as the required
silicon single crystal, which is used as a seed for growing Si single crystals. Si single
crystals with different crystal orientations can be obtained by using seeds with the
corresponding crystal orientations. The silicon seed held by chuck is moved down
from the upper end of the CZ furnace and is immersed into the molten Si. Since the
molten Si maintains some degree of super-cooling near the solid–liquid interface
with the silicon seed at a given temperature, the molten Si then is recrystallized
around the seed in the same direction as the seed. The seed rod is continuously
rotated through the pulling mechanism of the single crystal furnace and is lifted at a
very slow speed while the molten Si continues to crystallize. As the seed rod
gradually is raised, the ingot grows continuously along with the seed crystal to
form a rod-shaped single crystal ingot. Heating power for the quartz crucible is
generated by a heater (high-frequency induction type or resistance heating type), and
the graphite crucible functions as a device for high-temperature loading, heat
transfer, and safety. The diameter of the single crystal that is formed can be
controlled by adjusting the heating power, the pulling speed, and the seed-holder
rotation speed. In the process of pulling the single crystal, a doping element such as
arsenic (As), boron (B), phosphorus (P), or antimony (Sb) can be added to the quartz
crucible to produce doped single crystals as needed. The single crystal growth
furnace has been widely used; its advantages are low manufacturing cost, low
resistivity of prepared single crystals (<100 Ωcm), the ability to produce single
crystals with large diameters (such as an ingot with a diameter of 450 mm), and the
ability to reuse the polycrystalline raw materials many times. The disadvantages of
the single crystal growth furnace are that the solid quartz crucible may be slightly
63 Manufacturing Equipment for Silicon Wafer 1241

dissolved into the molten silicon during the crystal growth step, in which impurities
such as Al, Fe, and Ca present in the quartz crucible itself can cause process
contamination. Figure 63.2 shows an image of a single crystal growth furnace and
Table 63.1 lists the main technical parameters of single crystal growth furnaces.
The thermal field control system of the single crystal growth furnace is one of the
most important modules for crystal formation in single crystal growth furnace. The
temperature gradient distribution of the thermal field directly affects the pulling
process of the single crystal furnace and the quality of the grown ingot, so the
structure and efficiency of the thermal field is one of the core technologies of this
type of furnace.
Single crystal growth furnaces can be divided into two types based on the
methods used to pull the seed. One type of single crystal furnace pulls the seed

Fig. 63.2 Image of a single

crystal growth furnace.
(Source: Zhejiang Jingsheng
Mechanical and Electrical
Co., Ltd.)

Table 63.1 Main Parameters Sample indicators

technical parameters of
Drawn crystal ingot diameter/mm 300
single crystal growth
furnaces Maximum loading weight/kg 260
Hot zone specifications/in 24–28
Furnace height (closed furnace)/m 7.83
Crystal stroke/mm 3700
Crystal rotation speed/(r/min) 0–30
Crucible stroke/mm 460
Crucible rotation speed/(r/min) 0–20
1242 B. Liu

rod upwards, while the other type uses the Bridgman-Stockbarger method. Gener-
ally, Si single crystals are prepared using the former type.
The furnace body of a single crystal furnace that uses the Bridgman-Stockbarger
method is usually composed of a high-temperature zone (upper part), a temperature
gradient zone (middle part), and a low-temperature zone (lower part). The operation
process begins by placing the polycrystalline Si raw material into a specially shaped
crucible containing a preinstalled seeds at the bottom. The crucible is heated in the
high-temperature zone of the furnace body to melt the material and keep it molten.
As the crucible is lowered by the lowering mechanism from the high-temperature
zone in the upper part of the furnace body through the middle temperature gradient
zone to the low-temperature zone in the lower part, then the melt begins to crystallize
into a single crystal. The single crystal furnace using the Bridgman-Stockbarger
method is mainly used for growing optical crystals made from materials such as
large-size alkali halogen compounds and fluorides [1].
At present, major semiconductor-level single crystal growth furnace manufac-
turers include XAUT Crystal Growing Technology Co., Ltd., Zhejiang Jingsheng
Mechanical and Electrical Co., Ltd., Beijing Jingyuntong Technology Co., Ltd.,
Beijing Sevenstar Electronics Co., Ltd., Linton Crystal Technologies, Ferrotec, and
PVA TePla.

Float Zone Crystal Growth Furnace

As shown in Fig. 63.3, the float zone crystal growth furnace is a type of process
equipment that utilizes the float zone (FZ) principle. In a protective high vacuum or
inert gas environment, a Si polycrystalline ingot passes through a small,

Fig. 63.3 Operation

principles and components
used in the FZ method
63 Manufacturing Equipment for Silicon Wafer 1243

high-temperature narrow closed zone in the furnace which generates a narrow

molten zone locally on the ingot. The polycrystalline ingot or the heating element
of the furnace body is moved so that the molten zone is simultaneously moved and
the ingot is gradually crystallized into a single crystal ingot (monocrystalline ingot).
Based on the segregation mechanism of dopants at the solid/molten silicon interface,
the unique features of monocrystalline ingots prepared by the FZ method are that the
purity of the monocrystalline ingot can be improved during the process to crystallize
the polycrystalline ingot into a single crystal, and the growth of the doped ingot is
relatively uniform.
According to the different surface tension, the type of zone furnace can be divided
into floating zone (FZ) melting and horizontal melting. FZ crystal growth used in
practical applications are generally of the FZ molten growth type. FZ crystal growth
furnaces can prepare high-purity low-oxygen Si single crystals without crucible,
which are mainly used for the preparation of high-resistance (>20 kΩcm) Si single
crystals and the purification of FZ silicon. These products are mainly used for the
manufacturing of discrete power devices. A schematic diagram of the structure of the
FZ crystal growth furnace is shown in Fig. 63.4 and an image of this type of furnace
is shown in Fig. 63.5. The structure includes a furnace chamber, an upper shaft, and a

Fig. 63.4 Schematic of the structure of a FZ crystal growth furnace

1244 B. Liu

Fig. 63.5 Image of a FZ crystal growth furnace. (Source: Zhejiang Jingsheng Mechanical and
Electrical Co., Ltd.)

lower shaft (mechanical transmission parts), a crystal ingot chuck, a seed chuck, a
coil (high-frequency generator), and gas holes (a vacuum port, a gas inlet, and an
upper gas outlet). The furnace chamber structure contains a water circulation system
for cooling. The crystal ingot chuck for holding the polycrystalline Si ingot is
attached to the bottom end of the upper shaft, while the seed chuck for holding the
seed is attached to the top end of the lower shaft. The heating coil uses a high-
frequency power source to form a narrow melting zone on the polycrystalline ingot.
Starting from the lower end of the polycrystalline ingot, the heating coil enables the
molten zone to crystallize into a single crystal through the rotation and lowering of
the upper and lower shafts. Table 63.2 lists the main technical parameters of the FZ
crystal growth furnace.
The advantages of the FZ crystal growth furnace are not limited to improving the
purity of single crystals. In addition, the growth of the doped ingot is more uniform,
and the single crystal ingot can be subjected to multiple purification processes.
63 Manufacturing Equipment for Silicon Wafer 1245

Table 63.2 Main Parameters Sample indicators

technical parameters of
Ingot diameter/mm 150, 200
FZ crystal growth furnaces
Argon flow control/(mL/min) 0–50
Furnace pressure/Pa 3.0  105
Upper shaft stroke/mm 2500
Lower shaft stroke/mm 2000
Upper and lower shaft movement 0–30, 1%
speed/(mm/min)
Upper and lower shafts fast movement 300
speed/(mm/min)
Vacuum pressure/Pa 1.0

Therefore, these prepared single crystals can be used to manufacture products such
as power electronic devices, photosensitive diodes, radiation detectors, and infrared
detectors. The disadvantages of float zone crystal growth furnaces are high
manufacturing cost and the small diameter of prepared single crystals. At present,
single crystals prepared by this method have a maximum diameter of 200 mm. In
addition, the total body height of the FZ crystal growth furnaces is higher, and the
movement of the internal upper and lower shafts is longer, so it can be used to grow
longer monocrystalline ingots.
At present, major manufacturers of float zone crystal growth furnaces include
Zhejiang Jingsheng Mechanical and Electrical Co., Ltd., XAUT Crystal Growing
Technology Co., Ltd., Beijing Jingyuntong Technology Co., Ltd., and PVA-Tepla.

Ingot Grinding Machines

The ingot grinding machine is a type of process equipment that uses a diamond
grinding wheel to grind the periphery of a silicon ingot into a single crystal ingot
with required diameter. It also grinds an orientation flat (OF) or a notch along the
ingot. The peripheral surface of an ingot as prepared by a single crystal furnace is
usually irregular and its diameter is larger than the required diameter of the silicon
wafer; through peripheral grinding, the desired ingot diameter can be obtained.
The ingot grinding machine performs to grind an OF or a notch in the ingot,
which means the machine is also used to perform a directional test and grind the
required diameter and then grind an OF or a notch in the ingot, as shown in
Fig. 63.6a; Fig. 63.6b shows an axonometric diagram. Generally, an ingot with a
diameter of 150 mm or less will have an OF; and diameter of 200 mm or more will
have a V-shaped notch. An ingot with a diameter of 200 mm can also have an OF as
required. The functions of the OF on ingots include enabling automatic positioning
operations by equipment in IC manufacturing processes, indicating properties of the
silicon wafer such as crystal orientation and conductivity type, and facilitating
production management. In addition, if the primary flat or notch is perpendicular
to the <110> direction; the orientation (of OF or notch) can be adjusted to prevent
1246 B. Liu

Fig. 63.6 OF or notch in ingots

Fig. 63.7 Operation principles and components of an ingot grinding machine

breakage during chip packaging, in which the dicing process can lead to natural
cleavage of the wafers.
The operation principles and components of an ingot grinding machine are shown
in Fig. 63.7 and an image of the machine is shown in Fig. 63.8. An ingot is held in
the center of the worktable of the ingot grinding machine. The rotation of the center
drives the silicon ingot to rotate. The diamond grinding wheel on the grinding head
63 Manufacturing Equipment for Silicon Wafer 1247

Fig. 63.8 Image of an ingot grinding machine. (Source: Midwest Yuanda Technology Co., Ltd.)

Table 63.3 Main Parameters Sample indicators

technical parameters of
Processing diameter/mm 200, 300
ingot grinding machines
Working stroke/mm 2800
Grinding wheel rotation speed/(r/min) 3200–8000
Spindle stock rotation speed/(r/min) 0–30
Grinding head stroke/mm 2400

(usually a cup wheel or a cylindrical wheel) rotates at a high speed and feeds
transversely opposite to the periphery of the silicon ingot, and either the ingot or
the grinding wheel moves in a reciprocating manner along the central axis of the
worktable to perform the grinding. Table 63.3 lists the main technical parameters of
ingot grinding machines.
Typically, the crystal orienting device used in ingot grinding machines is an X-ray
orienting device integrated into the grinding machine. The operation method is as
follows. The orienting device tests the outer cylindrical surface of the single crystal
ingot and rotates the ingot until the desired crystal OF is found, at which point the
rotation of the single crystal ingot is stopped. After the grinding wheel is fed to
perform the specified amount of grinding, either the ingot or the grinding wheel is
moved in a reciprocating manner along the central axis of the worktable, and the
desired OF is ground on the cylindrical surface of the silicon ingot along the crystal
axis direction. For silicon ingots with a diameter of 150 mm or less, the grinding
wheel used for the outer surface of the single crystal ingot can be used for grinding
the OF. For ingots with a diameter of 200 mm or more, another type of grinding
wheel on the equipment (generally a V-shaped grinding wheel) can be used for
grinding the notch, and the V-shaped notch is ground on the outer cylindrical surface
of the single crystal ingot along the crystal axis direction.
Ingot grinding machines can be divided into two types: Type one, the grinding
wheel moves horizontally, while the other type, the worktable moves horizontally.
1248 B. Liu

With the increase in the diameter and length of silicon single crystal ingots, as well as
the demand for the integration of crystal orienting devices and auxiliary grinding
wheels used for grinding notches, the most commonly used ingot grinding machines
at present are the type of worktables with horizontal movement function.
Major manufacturers of ingot grinding machines currently include Beijing Jingyi
Century Electronics Co., Ltd., Midwest Yuanda Technology Co., Ltd., Zhejiang
Jingsheng Mechanical and Electrical Co., Ltd., and TSK.

Slicing Machines

A silicon wafer slicing machine is a type of process equipment for slicing a single
crystal silicon ingot into thin silicon wafers having precise geometric dimensions
and a desired thickness. Before the 1990s, slicing machines used an inner-diameter
saw (IDS) blade to slice the Si ingot in a single-slice manner. The operation
principles and components are shown in Fig. 63.9, and an image of an IDS is
shown in Fig. 63.10. The IDS blade is a stainless steel ring with a thickness of
only about 0.12 mm to 0.15 mm. The inner edge of the ring is coated with a diamond
abrasive to form a fixed abrasive inner diameter cutting edge. The outer edge of the
ring is clamped by the upper and lower blade plates of the IDS with tension applied
to give the blade a certain degree of rigidity; and it rotates with the blade plates at a
high speed. The single crystal ingot material is glued to a chuck and mounted on an
IDS feeding device. After the feeding device moves by one distance length
(Z direction feeding) relative to the inner diameter blade based on a predetermined
thickness, the ingot is moved by the worktable from the inner end of the blade
toward the outer end of the blade (in the X direction, shown on the right side of
Fig. 63.10) relative to the inner diameter blade to perform the slicing. After the
slicing is completed, the worktable returns to the original position.

Fig. 63.9 Operation principles and components of the inner diameter saw
63 Manufacturing Equipment for Silicon Wafer 1249

IDS can be divided into vertical and horizontal types based on the different
bonding directions of the single crystal ingots’ crystal axes. The vertical type is
used to slice single crystal ingots with a vertical bonding direction, as shown in
Fig. 63.10, while the horizontal type is used for single crystal ingots with a
horizontal bonding direction. Table 63.4 lists the main technical parameters of
IDS. Major manufacturers of IDS include the 45th Research Institute of China
Electronics Technology Group Corporation and ACCRETECH.
The cutting edge of an IDS blade is coated with a layer of diamond abrasive with
a thickness of about 0.29 mm to 0.35 mm, which results in a large material loss at the
cutting site when the silicon wafers are sliced. At the same time, the increasing
diameters of wafers result in a relatively significant degree of variation in thickness,
as well as bow, warp, and a large surface damage layer on wafers sliced with IDS.

Fig. 63.10 Image of an internal diameter saw (Source: CETC45)

Table 63.4 Main Parameters Sample indicators

technical parameters
Blade dimensions/mm ODΦ690  IDΦ241(Φ235)
of IDS
Maximum diameter of ingot/mm 153
Workpiece length/mm 400
Slicing speed range/(mm/min.) 0.5–120
Feeding repeatability/mm 0.005
Slice thickness setting range/mm 0.001–40.000
Crystal orientation adjustment 7
(X direction)/( )
Crystal orientation adjustment 7
(Y direction)/( )
1250 B. Liu

These factors increase the difficulty and cost of subsequent processing of wafers.
The multiwire saw technology that emerged after the 1990s has become the main-
stream silicon wafer slicing method.
The earliest application of the multiwire saw is the free abrasive multiwire saw,
which uses the principle of free abrasive processing. The operation principles and
components are shown in Fig. 63.11. The slicing steel wire used in this kind of
machine (with a thickness of about 0.12 mm or so) is evenly wound around the main
spool rollers according to their gaps (with two to four main spool rollers) to form a
slicing wire frame, as shown in Fig. 63.12. The slicing edge of the frame is
horizontal, and the high-speed rotation of the main spool rollers moves the wire in
a high-speed winding manner. The ingot is horizontally glued to the feeding device
and is slowly fed in the vertical direction relative to the slicing edge of the frame. The
high-speed moving steel wire rubs against the ingot and abrasive slurry made of

Fig. 63.11 Operation principles and components of a multiwire saw

63 Manufacturing Equipment for Silicon Wafer 1251

Fig. 63.12 Slicing wire frame

Table 63.5 Main Parameters Sample indicators

technical parameters of
Ingot diameter/mm 300
multiwire saws
Ingot maximum length/mm 400
Slicing speed range/(mm/min.) 0.01–9
Slicing stroke/mm 360
Wire tension range/N 0–50
Crystal orientation adjustment 5
(X direction)/( )
Maximum wire speed/(m/s) 18

materials such as SiC is added in the friction zone, which coats the slicing steel wire
and creates a fine cutting effect. The process continues until a given number of
silicon wafers with predetermined thickness have been sliced. Table 63.5 lists the
main technical parameters of multiwire saws.
The use of abrasive slurry made from materials such as SiC for multiwire saws
creates a harsh working environment, so the wire slicing area needs to be enclosed, as
shown in Fig. 63.13. At the beginning of the twenty-first century, steel wire coated
with diamond abrasive appeared, and this diamond steel wire was adopted instead of
ordinary steel wire for slicing. The corresponding equipment is called a fixed abrasive
multiwire saw or diamond multiwire saw, marking a return to the era of fixed abrasive
technology. During the diamond multiwire sawing process, cooling liquid with
deionized water as the main component is used to cool the slicing area, which greatly
improves the working environment. Diamond multiwire saws have a good working
environment, low environmental pollution, and high processing efficiency, so they
represent the main direction for the development of silicon wafer slicing equipment.
1252 B. Liu

Fig. 63.13 Image of a multiwire saw. (Source: CETC45)

Multiwire saws can be divided into two types based on the feeding direction of
the ingot, namely the upper feed type and the lower feed type. In the lower feed type,
the ingot is sliced from top to bottom at the upper end of the wire frame, while in the
upper feed type, the ingot is sliced from bottom to top at the lower end of the wire
frame. There is little difference in the functions of these two types of multiwire saw;
they only differ in terms of the convenience of installing and maintaining the slurry
pouring device. At present, major semiconductor-level multiwire sawing machine
manufacturers include the 45th Research Institute of China Electronics Technology
Group Corporation, NTC, and SlicingTech (formerly Meyer Berger Company).

Silicon Wafer Annealing Furnaces

In the process of manufacturing polycrystalline Si and monocrystalline Czochralski Si,

these Si products contain many oxygen atoms. At certain temperature, these oxygen
atoms in the Si are converted into oxygen donors, which affect the resistivity of the Si
wafer. An annealing furnace is a type of process equipment that removes the oxygen
near the surface of the polished Si wafer through sustained heating and cooling. The
temperature in the furnace is raised to 1000–1200  C in a hydrogen or argon atmo-
sphere, causing the oxygen out-diffusion or to precipitate SiOx in layers while also
dissolving microdefects, decreasing the amount of impurities, reducing defects, and
forming a relatively clean area (denude zone) on the surface of the Si wafer. Because of
the relatively high temperature of the annealing furnace tube, it is also called a high-
temperature furnace. The annealing process is also known as gettering in the industry.
The operation principles and components of a horizontal annealing furnace are
shown in Fig. 63.14. The reaction chamber is a closed high-vacuum area composed
of a fused quartz tube, a quartz boat, and a temperature/pressure control system.
63 Manufacturing Equipment for Silicon Wafer 1253

Fig. 63.14 Operation principles and components of a horizontal annealing furnace

Hydrogen or argon can be introduced into the reaction chamber, and the desired
temperature and pressure can be reached in the reaction chamber by means of a
heater (which generally uses high-frequency induction heating or halogen lamp
heating). The Si wafer is kept at a higher temperature for a certain time in the
reaction chamber to achieve the purpose of annealing.
Si wafer annealing furnaces can be divided into two types: horizontal annealing
furnaces and vertical annealing furnaces. The main difference between a horizontal
annealing furnace and a vertical annealing furnace is in the orientation of the reaction
chamber layout. The reaction chamber of a horizontal annealing furnace has a
horizontal structure, and a batch of Si wafers can be loaded in the annealing furnace
reaction chamber for the simultaneous annealing treatment. The annealing time is
usually 20 to 30 minutes, but the reaction chamber requires a longer heating time to
reach the temperature required for the annealing process. Temperature control along
the length of the quartz tube in the reaction chamber is one of the key technologies
for the development of the horizontal annealing furnace.
Technological processes involving vertical annealing furnaces also allow a batch
of Si wafers to be simultaneously loaded in the annealing furnace reaction chamber
for annealing treatment. The reaction chamber has a vertical structure and the Si
wafers can be placed horizontally in the quartz boat. Because the entire quartz boat
can be rotated within the reaction chamber, the annealing temperature of the reaction
chamber is uniform, which results in uniform temperature distribution on the Si
wafers and thereby produces excellent annealing uniformity. However, the process
cost of vertical annealing furnaces is higher than that of horizontal annealing
furnaces. Table 63.6 lists the main technical parameters of vertical annealing fur-
naces and Fig. 63.15 shows an image of a vertical annealing furnace. At present,
major annealing furnace manufacturers include NAURA Technology Group Co.,
1254 B. Liu

Table 63.6 Main Parameters Sample indicators

technical parameters of
Silicon wafer diameter/mm 300
vertical annealing furnaces
Batch processing quantity (piece) 100
Number of FOUP stock (piece) 16
Heating tube inner diameter/mm 500
Heated flat zone length/mm 1040

Fig. 63.15 Image of a vertical annealing furnace. (Source: Koyo Thermal System Co., Ltd.) [2]

Ltd., the 48th Research Institute of China Electronics Technology Group Corpora-
tion, Koyo Thermal System Co., Ltd., ASM international, Tokyo Electron Ltd., and
Centrotherm International AG.

Edge Rounding Machines

An edge rounding machine is a type of process equipment that uses a form grinding
wheel to trim (grind) the edges of the thin sliced Si wafer into a specific R shape or T
shape to prevent the Si wafer edge from being damaged during subsequent pro-
cessing. The outlines of different Si wafer edge shapes are shown in Fig. 63.16 (refer
to the relevant SEMI standard for specific parameters). A Si wafer with a diameter of
200 mm or more generally has a notch and must be chamfered, which is a type of Si
wafer edge rounding process.
The operation principles and components of an edge rounding machine are shown
in Fig. 63.17. The Si wafer is clamped by vacuum suction on a spindle-mounted
chuck, and it is aligned with the spindle rotation center and rotated at a high speed.
63 Manufacturing Equipment for Silicon Wafer 1255

Fig. 63.16 Si wafer edge shape outlines

Fig. 63.17 Operation principles and components of an edge rounding machine

An edge form grinding wheel is mounted on the end of the grinding wheel spindle
and the silicon wafer is driven by a Z-direction motor to align it with the center of the
grinding wheel configuration groove, as shown in Fig. 63.18. The grinding wheel
spindle rotates at a high speed to drive the grinding wheel to rotate and laterally
contact the edge of the Si wafer. The X- and Y-direction motors perform interpolated
driving motion to make the grinding wheel feed horizontally relative to the edge of
the Si wafer and the outline of the OF for the required distance, at which point it
stops moving and returns in the opposite direction to complete the edge rounding
process of the Si wafer. The edge grinding process is divided into two processes:
rough grinding and fine grinding.
1256 B. Liu

Fig. 63.18 Partial schematic view of the edge rounding principle

Fig. 63.19 Schematic of

notch chamfering

The notch in the Si wafer requires a corresponding edge rounding device. The
spindle on which the Si wafer is clamped is rotated and moves in the Z direction, so
that the center of the notch in the Si wafer is aligned with the center of the form
grinding wheel configuration groove at the front end of the θ-direction high-speed air
spindle and a certain distance is maintained. Then, the X- and Y-direction motors
perform interpolated driving motion so that the Si wafer feeds laterally to reach a
certain distance with the notch grinding wheel (see Fig. 63.19), and then returns in
the opposite direction to complete the notch rounding process on the edge of the Si
wafer. In the process of notch edge rounding, since the notch grinding wheel has a
63 Manufacturing Equipment for Silicon Wafer 1257

small diameter, it must be driven by the high-speed air spindle to achieve the
required process conditions. Table 63.7 lists the main technical parameters of edge
rounding machines.
In most edge rounding machines, the Si wafer is clamped horizontally, while the
axial direction of the spindle supporting the wafer, the grinding wheel spindle, and
the θ-direction notch grinding wheel spindle are in the vertical direction. Consider-
ing factors such as automation and work efficiency, there are currently two types of
edge rounding machines: single-table and double-table. A single-table edge
rounding machine only contains one spindle table for clamping silicon wafers, so
only one wafer can be chamfered at a time. A double-table edge rounding machine
contains two spindle tables for clamping Si wafers, so it can simultaneously perform
chamfering on two Si wafers, thereby improving processing efficiency. Figure 63.20
shows an image of a double-table edge rounding machine. At present, major edge
rounding machine manufacturers include ACCRETECH and SpeedFam.

Table 63.7 Main Parameters Sample indicators

technical parameters of
Si wafer diameter/mm 200, 300
edge rounding machines
OF Flat, notch
Si wafer thickness/mm 0.6–1.0
Grinding wheel diameter/mm 200
Grinding wheel speed/(m/s.) 80
Notch grinding wheel diameter/mm 3
Notch grinding wheel rotation speed/(r/min.) 8000

Fig. 63.20 Image of an edge rounding machine. (Source: CETC45)

1258 B. Liu

Lapping Machines

Si wafer lapping machine, also called double lapping machine, is a type of process
equipment that uses mechanical double-sided lapping to remove sawing marks left
on the Si wafer surface by the slicing process and reduce the silicon wafer surface
damage (SD) layer depth, thereby effectively improving the flatness and surface
roughness of Si wafers.
A lapping machine is generally composed of lapping plates made of ductile iron,
planet carriers, and a device to steadily feed abrasive slurry. The lapping plates are
made of ductile iron, mainly because the spheroidal graphite present in cast iron
(with a typical particle size of 20 to 50 μm) can provide lubrication for the lapping
process. The lapping plates are key components of the lapping machine, so it is
necessary to ensure and maintain the geometrical accuracy (such as flatness and
roughness) of the plates’ surface. In addition, the material adopted to make the
lapping plates should have a uniform hardness distribution (with a hardness of
140 to 180 HB) and should be easy to the conditioning when in use. Grooves are
typically cut on the lapping surface of each lapping plate, the effect of which is to
facilitate the flow of the abrasive slurry on the lapping surface and make it easier to
pick up finished wafers after lapping. These grooves typically have a depth of 10 mm
and a width of 1 to 2 mm. They are arranged perpendicular to each other and the
groove spacing differs based on the experience of the equipment manufacturer.
The operation principles and components involved in lapping are shown in
Fig. 63.21. A planet carrier is a thin component with an outer ring gear (the thickness
of which is less than that of the Si wafer) with one or more holes on the surface, in
which the diameter of holes is slightly larger than that of the silicon wafer. The outer
ring gear of each planet carrier meshes with the outer ring gear of the central gear (also
known as the sun gear) and the annular gear at the outer diameter end of the lower-
lapping plate. This outer ring gear either rotates with the central gear (if the annular
gear of the lower-lapping plate does not rotate) or with the central gear and the annular
gear of the lower-lapping plate according to its internal speed ratio (if the annular gear
of the lower-lapping plate rotates), as shown in Fig. 63.22. Each Si wafer is loaded in a
hole of the planet carrier and is rotated with the carrier as the upper- and lower-lapping
plates rotate and apply a certain lapping pressure on wafer surface. While the planet
carriers rotate between the upper- and lower-lapping plates, a lapping abrasive made
from Al2O3, water, and an active suspending agent is poured. This abrasive forms a
rolling and microcutting action on the Si wafer surface, and grinds away the surface
material of the Si wafer primarily by means of microcrushing. The ideal Si wafer
surface morphology formed by this lapping process is a uniform matte surface
composed of innumerable microscopic scratches [3].
Based on the mechanism of lapping motion, a double-side lapping machine must
involve three basic movements: the relative rotation of the upper- and lower-lapping
plates, the rotation of the planet carriers, and the revolution of the central gear. The
structure of this equipment requires the central gear to rotate about a fixed axis, while
fixed-axis rotation is optional for the annular gear of the lower-lapping plate. The
planet carriers mesh with the central gear and the annular gear of the lower-lapping
63 Manufacturing Equipment for Silicon Wafer 1259

Fig. 63.21 Operation principles and components of the lapping process

plate to form planetary gear rotation, allowing them to rotate and revolve. Usually,
the primary design consideration in choosing the planet carrier diameter is to create
the maximum number of holes on its surface so each carrier can hold more Si wafers.
When double-side lapping machines are designed, the initial premise is to allow for
the maximum number of planet carriers possible, and then the design is optimized to
take the deformation, wear, and motion trajectory of the planet carriers into account.
Almost all double-side lapping machines have the same type of structure, except
in terms of how the planet carriers between the central gear and the annular gear are
installed and removed. Generally, the upper-lapping plate can either be lifted or
1260 B. Liu

Fig. 63.22 Schematic of the lapping plates, central gear, and planet carriers

Fig. 63.23 Image of a double-side lapping machine with a removable upper-lapping plate.
(Source: Lapmaster Wolters) [4]

removed, allowing room for operations involving the planet carriers. Figure 63.23
shows an image of a double-side lapping machine with a removable upper-lapping
plate. The lower-lapping plate or the annular gear can generally be lifted to install
and remove planet carriers. In addition, the driving modes that produce the three
basic movements in the lapping process also differ among different machines. In the
earliest equipment, a driving mode using a single-motor fixed transmission ratio was
adopted. This allowed only one or two simple speed combinations of the three basic
lapping movements, which made it difficult to adjust the technological parameters of
the double-side lapping process. Currently, equipment with an independent driving
mode using four motors (commonly known as a four-way double lapping machine)
enables a wider range of adjustment of technological parameters. The advantage of
this independent driving mode is that the speed of the upper-lapping plate, the lower-
lapping plate, the annular gear, and the central gear can be separately adjusted to
form a speed ratio that produces the optimal lapping effect (lapping removal rate and
63 Manufacturing Equipment for Silicon Wafer 1261

Table 63.8 Main Parameters Sample indicators

technical parameters
Lapping plate diameter/mm 1935
of lapping machines
Lapping zone width/mm 686
Maximum diameter of lapped silicon wafer/mm 450
Minimum lapping thickness/mm 0.5
Maximum lapping thickness/mm 200
Maximum lapping pressure/kgf 3500
Maximum rotation speed of central 50
gear/(r/min.)
Note: 1 kgf ¼ 9.80665 N.

lapping uniformity) on the surface of the Si wafer. Meanwhile, the ratio of the central
gear speed to the other three speeds, such as that of the upper-lapping plate, can be
subject to stepless speed regulation, allowing the planet carriers to move in forward
or reverse rotation to meet lapping process requirements for different materials and
conditioning process requirements for the lapping plates. Table 63.8 lists the main
technical parameters of lapping machines.
The lapping quality of the Si wafer directly affects the quality and overall
efficiency of the subsequent Si wafer polishing process. Therefore, the double-side
lapping process generally uses a combination of rough and fine lapping to improve
the lapping quality of the silicon wafer. The rough lapping process can use lapping
slurry with a larger abrasive grain (15 μm), a higher-lapping pressure, and a higher-
lapping speed (adjusted by controlling the speed of the upper-lapping plate, the
lower-lapping plate, the annular gear, and the central gear). The lapping removal rate
is high and the surface roughness Ra of the silicon wafer after lapping reaches
0.63 μm or less. The fine lapping process can use lapping slurry with a smaller
abrasive grain (3 to 5 μm), a lower-lapping pressure, and a lower-lapping speed. The
lapping removal rate is small and the surface roughness Ra of the silicon wafer after
lapping reaches 0.16 μm or less.
At present, major lapping machine manufacturers include Suzhou HRT Elec-
tronic Equipment Technology Co., Ltd., Hunan Yujing Machinery Co., Ltd.,
SpeedFam, HAMAI, Lapmaster Wolters, PR HOFFMAN, and Kemet.

Wafer Etching Machines

Wafer etching is also known as wafer erosion or thinning etching. After the Si wafer
has been machined by methods such as slicing and lapping, surface damage such as
pits, chips, cracks, and residual stress from machine processing may form on the
wafer surface. A wafer etching machine is a type of process equipment that removes
the damaged layers, residual stress, and contamination on the Si wafer caused from
previous machining by using chemical actions to obtain a clean and shiny Si wafer
surface. Meanwhile, the wafer etching process can also expose defects such as
scratches that are not easily observed during the Si wafer lapping process.
1262 B. Liu

When the Si wafer is chemically etched, it is usually immersed in an alkaline

solution (such as a hot solution of sodium hydroxide or potassium hydroxide) or an
acid solution (such as nitric acid or hydrofluoric acid). This chemical solution reacts
with the Si atoms on the Si wafer surface to form other compounds which are
dissolved in the solution, thereby gradually removing the subsurface damage
(SD) on the Si wafer and releasing the residual stress. The corrosion effect of the
chemical solution is selective and realizes a high removal rate for the Si material in
the SD layer, thereby reducing the subsurface damage and suppressing the extensive
propagation of microcracks in the silicon material. In the operating process of a
wafer etching machine, a certain number of Si wafers are first moved by a transfer
mechanism through the rinsing tank of the equipment, where they are precleaned.
Then the etching treatment is performed in the etching tank, after which the wafers
are cleaned and dried in the drying unit to finish the entire process, as shown in
Fig. 63.24.
Due to Si wafer’s low etch rate, wafer etching machines usually adopt multiple Si
wafers etching method to improve the efficiency. The Si wafers are placed in batches
in a Si wafer carrier (commonly known as a cassette or basket) or a Si wafer holder in
the equipment for simultaneous etching.
Wafer etching machines can generally be divided into two types based on the kind
of chemical solution used: alkaline etching machines and acid etching machines.
Alkaline etching of Si wafers is anisotropic; the etch rate is related to the type of the
Si wafer (P-type or N-type) and the crystal orientation. Surface roughness after
etching is not only related to the type and crystal orientation of Si wafers, but also
is influenced by the condition of the post-lapped Si wafers (such as roughness and
SD depth). Generally, the alkaline etching process is low cost and nontoxic, but it
results in increased surface roughness. Figure 63.25 shows an image of an alkaline

Fig. 63.24 Schematic of the

wafer etching process
63 Manufacturing Equipment for Silicon Wafer 1263

Fig. 63.25 Image of an alkaline wafer etching machine. (Source: CETC45)

Table 63.9 Main technical parameters of alkaline wafer etching machines

Parameter Sample indicators
Wafer diameter/mm 100, 150, 200
Processing capacity (piece/tank) 100 (100 mm silicon wafer)
50 (150 mm or more)
Solution type KOH (concentration  50%, temperature  130  C)
Process tank body QDR rinsing tank, etching tank, and drying tank
Wafer transfer form Automatic robot transfer
Si wafer holder type Nonsilicon wafer box type (PEEK frame)
Solution heating type Online heating
Drying method Hot nitrogen/IPA steam

etching machine, and Table 63.9 lists the main technical parameters of alkaline
etching machines. Although acid etching machines have high etching rates, the
process is difficult to control and will produce toxic gases. In addition, differences
in the etch rate cause the center of the Si wafer to be slightly thicker than the edges,
and the etching consistency between Si wafers is relatively poor. Because of the high
cost of the acid solution used in the acid etching process and rigorous environmental
protection requirements, alkaline etching is often used for etching small-diameter Si
wafers. However, acid etching leaves the surface of the Si wafer free from corrosion
pits.
1264 B. Liu

The ratios of the alkaline and acid solutions used in the Si wafer etching process
and the related chemical reaction formulas are as follows.
Alkaline solution: A metal base is used with a stabilizer, such as a hydroxide
solution, and the reaction formula is

Si þ 2OH þ 4H2 O ! SiðOHÞ2

6 þ 2H2

Acid solution: A HNO3-HF mixture is generally used. The ratio of HF to HNO3 is

between 0.05 and 0.25, and the temperature is controlled at 18 to 24  C. At the same
time, acetic acid is added to buffer the etch rate and improve the uniformity of
etching. The chemical reaction formula is.

Si þ 4HNO3 ! SiO2 þ 4NO2 þ 2H2 O

SiO2 þ 6HF ! H2 SiF6 þ 2H2 O

The total reaction formula is

Si þ 4HNO3 þ 6HF ! H2 SiF6 þ 4NO2 þ 4H2 O

There are many manufacturers of wafer etching machines, including the 45th
Research Institute of China Electronics Technology Group Corporation, Jiangsu
CSE Semiconductor Equipment Technology Co., Ltd., Suzhou Jingmiao Semicon-
ductor Equipment Co., Ltd., JAC, MEI, and Global Zeus.

Polishers

A Si wafer polisher, also known as a chemical mechanical polishing (CMP)

machine, is a type of process equipment for meticulously removing materials on
the surface of the Si wafer to improve the quality of its surface topography and
microroughness. This is achieved by means of a polishing slurry that contains a
chemical solution (usually an alkaline chemical solution), which performs the
corrosive effect, and an abrasive, which has a mechanical grinding effect.
The operation principles and components of a Si wafer polisher are shown in
Fig. 63.26. A polishing pad (a thin porous pad made of a polymer material) is
attached to the upper surface of a polishing table, which can also rotate. The Si wafer
is clamped on the polishing carrier (bonded with an organic wax or clamped by a
polishing head vacuum chuck), which rotates and swings the wafer. At the same
time, the polishing slurry is poured into the area where the polishing pad contacts the
Si wafer. The chemical liquid in the polishing slurry corrodes the surface layer of the
Si wafer into a soft substance, and the nano abrasive (SiO2 or Al2O3) in the polishing
slurry performs the grinding effect. The corroded layer on the silicon wafer surface is
removed by the friction between the polishing pad (cloth) and the Si wafer. The CMP
of the Si wafer is essentially a process of removing microscopic substances from the
63 Manufacturing Equipment for Silicon Wafer 1265

Fig. 63.26 Operation principles and components of a polisher

Si wafer surface in a balanced combination of continuous chemical etching and

mechanical removal to achieve the best polishing effect. The polishing pad condi-
tioner is a mechanism equipped with a brush or an end face diamond grinding wheel.
It can rotate, press down, or swing to clear surface deposits from the polishing pad or
condition the pad’s surface, thereby maintaining the polishing pad’s removal rate.
The Si wafer polishers used in practical applications can be divided into two
types: single-side polishers and double-side polishers. Based on the needs of down-
stream users, Si wafer manufacturers may divide Si wafers with a diameter of
200 mm or less into single-side polished wafers and double-side polished wafers.
Due to the low-processing efficiency and high-processing cost of CMP, a single-side
polished wafer with a diameter of 200 mm or less is generally formed by polishing
one side of a Si wafer that has already been lapped. In the manufacturing process,
single-side polished wafers are generally processed by a multiwafer single-side
polisher, in which multiple polishing heads (loaders) are used at the same time on
a polishing table to improve polishing efficiency and reduce production cost, as
shown in Fig. 63.27.
There is high market demand for double-side polished wafers with a diameter of
200 mm, and these wafers are generally processed by a multiwafer double-side
polisher (referred as a double-side polisher). Double-side polishers are based on
double-side lapping machines, with polishing pads attached on both the upper- and
the lower-lapping plates as well as additional devices for supplying and recycling the
polishing slurry, and multiple wafers polishing can be performed at the same time, as
shown in Fig. 63.28. Figure 63.29 shows an image of a multiwafer double-side
polisher. This type of equipment can polish silicon wafers with a diameter of 100 to
200 mm by using planet carriers with different specifications. Table 63.10 lists the
main technical parameters of double-side polishers.
Most Si wafers with a diameter of 300 mm are double-side polished wafers and
are generally processed by a combination of double-side and single-side polishing.
At present, major manufacturers of double-side polishers include Suzhou HRT
Electronic Equipment Technology Co., Ltd., Hunan Yujing Machinery Co., Ltd.,
SpeedFam (USA), Fujikoshi (Japan), PR Hoffman (USA), Applied Materials
(USA), and AM Technology Co., Ltd. (Korea).
1266 B. Liu

Fig. 63.27 Multiwafer single-side polisher

Fig. 63.28 Schematic diagram of a double-side polisher

Double-Side Grinders

A double-side grinder is a type of process equipment that simultaneously grinds the

upper and lower sides of Si wafers with a diamond grinding wheel tool. It is used as a
replacement for the Si wafer lapping machine in processing 300 mm silicon wafers.
After 300 mm Si wafers are processed by the multiwire saw, it is generally
necessary to use the double-side lapping process to remove the waviness and the
SD layer caused by the slicing process, so as to effectively improve the warpage,
flatness, and parallelism of the single crystal Si wafer. With the adoption of processes
for nodes below 90 nm in IC manufacturing, 300 mm Si wafers have entered the
mainstream, and the requirements for surface topography and microroughness of
these wafers are higher than those of Si wafers with diameters of 200 mm or less.
Traditional lapping processes are no longer able to meet actual application needs due
63 Manufacturing Equipment for Silicon Wafer 1267

Fig. 63.29 Image of a multiwafer double-side polisher. (Source: SpeedFam (USA) Co., Ltd.) [5]

Table 63.10 Main technical parameters of silicon wafer double-side polishers

Parameters Sample indicators
Polishing plate diameter/mm 1114
Batch polished wafer quantity (piece) 15 (150 mm silicon wafer), 5 (200 mm
silicon wafer)
Diameter of polished silicon wafer/mm 100,150,200
Polishing pressure/Kgf 23–100
Maximum rotation speed of the upper and lower 33
plates/(r/min)

to such problems as grinding equipment manufacturing precision, processing cost,

and environmental pollution. Moreover, the increase in the diameter of Si wafers has
reduced the surface topography accuracy of these processes. In the double-side
grinding process, Si wafers are processed one piece at a time, which can improve
the processing yield while maintaining control over the processing quality of each
piece, and the diamond grinding wheel has high grinding efficiency.
The operation principles and components of a double-side grinder are shown in
Fig. 63.30 [6]. The Si wafer is positioned vertically by means of an edge support
mechanism (not shown in the figure), which also rotates the wafer (in both forward and
reverse directions). The front end of each horizontal grinding wheel spindle is fitted
with a cup-type grinding wheel and can move horizontally. These two grinding wheel
spindles rotate at a high speed in opposite directions. They move horizontally in
opposite directions to contact the silicon wafer and start to grind the both sides of
the wafer. Once they grind the Si wafer to the desired thickness through the low-speed
1268 B. Liu

Fig. 63.30 Operation

principles and components of
a double-side grinder

Fig. 63.31 Image of a fully automatic double-side grinder. (Source: Koyo Machinery Industry
Co., Ltd.) [7]

feed movement, the grinding wheel spindles reverts back to their initial
position. Figure 63.31 shows an image of a fully automatic double-side grinder, in
which the wafer loading and unloading operation is performed through the carrier box.
Table 63.11 lists the main technical parameters of double-side grinders.
Since the Si wafer is positioned vertically in the double-side grinder, there is only
one type of this equipment, namely the horizontal structure type. The diameter of the
grinding wheel in a double-side grinder is generally smaller than that of the Si wafer,
so the grinding wheel must rotate at a very high speed and it is easy for vibration to
occur. Because vibration has a significant influence on the quality of the ground wafer,
therefore, double-side grinders adopt a single wafer grinding method. At present, the
main manufacturer of double-side grinders is Koyo Machinery Industry Co., Ltd.
63 Manufacturing Equipment for Silicon Wafer 1269

Table 63.11 Main Parameters Sample indicators

technical parameters of
Si wafer diameter/mm 200, 300
double-side grinders
Grinding wheel diameter/mm 110 (200 mm silicon wafer)
160 (300 mm silicon wafer)
Grinding wheel rotation 5500–6000
speed/(r/min.)
Si wafer rotation speed/(r/min.) 25–35
Grinding wheel longitudinal 25–80
feed/(μm/min.)
Cooling water temperature/ C 21

Single-Side Grinders

A single-side grinder is a type of process equipment for grinding one side (the
front side) of Si wafers with a diamond grinding wheel tool. This equipment, also
known as a wafer grinder, is used to further reduce the surface damage layer depth
(SDD) and improve the total thickness variation (TTV) and surface roughness of
Si wafers. The single-side grinder is mainly used for surface finishing after the
double-side grinding of 300 mm Si wafers. It is also used for surface finishing
after the double-side lapping of 200 mm Si wafers and the surface finishing after
Si wafer etching.
After a 300 mm Si wafer is processed by double-side grinding, a SD layer of a
certain depth still remains on the wafer surface and the wafer has a large TTV due to
the relatively large abrasive grain of the grinding wheel. In order to improve the
abovementioned process indicators and microroughness, the surface of the 300 mm
Si wafer needs to be further finished by the single-side grinding process. Most
200 mm Si wafers are manufactured using the single-side grinding process to
improve their TTV accuracy. Since the single-side grinding process increases the
manufacturing cost of the Si wafers, the single-side grinding process should be
selected as appropriate for the process line based on the final flatness index of the Si
wafers.
The operation principles and components of a single-side grinder (IFG mode) are
shown in Fig. 63.32 [8]. The Si wafer is clamped on the vacuum chuck, which
is mounted on the end face of the chuck table spindle and rotates. The grinding wheel
is mounted on the end face of the grinding wheel spindle and rotates at a high speed.
Under the vertical movement of the grinding wheel spindle, the grinding wheel
contacts the Si wafer for grinding; when the wafer is ground to a certain depth, the
grinding wheel spindle returns vertically and the grinding process is completed.
Single-side grinders are mainly divided into the vertical type and the horizontal
type, which are distinguished by the mounting mode of the chuck table spindle and
grinding wheel spindle (either vertical or horizontal). There are also two different
grinding movement feed modes: creep-feed grinding (CFG) and in-feed grinding
(IFG). The CFG grinding mode requires the diameter of the grinding wheel to be
1270 B. Liu

Fig. 63.32 Operation

principles and components of
a single-side grinder (IFG
mode)

larger than that of the silicon wafer. The Si wafer is clamped on the worktable so that
it can be rotated, and the grinding wheel feeds uniformly to grind the Si wafer to a
certain depth, in which the grinding movement is formed along the cross section of
the Si wafer. In the IFG grinding mode, the diameter of the grinding wheel is
generally equal to that of the Si wafer. The grinding edge of the grinding wheel
(referred to as a cup grinding wheel) features a strip of diamond abrasive of a certain
width that is applied inwardly from the outermost edge of the diameter of the wheel.
This grinding edge moves across the center of the Si wafer to feed along the axial
direction of the wafer while grinding its surface. Since the IFG grinding mode can
measure the Si wafer with a thickness measuring probe to control the grinding
thickness in real time, almost all current mainstream grinders have adopted vertical
structure designs that use the IFG grinding mode. Figure 63.33 shows an image of an
IFG single-side grinder.
The single-side grinders for 300 mm Si wafers mainly use a vertical structure with
IFG mode. In order to further reduce the SDD and residual stress on Si wafers while
improving processing efficiency and precision, most single-side grinders have rough
and fine grinding modes with a combination of rough and fine grinding wheels, in
which the abrasive grain of the rough grinding wheel is larger than that of the fine
grinding wheel. This type of grinder features two grinding systems to achieve rough
grinding and fine grinding, as shown in Fig. 63.34. This type of grinder is also
equipped with three independent sets of chuck table systems integrated on the index
table, which rotates to drive the rotation of three sets of chuck table systems at three
work stations. During the grinding operation, the loading/unloading is performed on
one chuck table system, and the other two chuck tables correspond to the rough and
fine grinding processes. Every 120 rotation of the table can be converted to a new
work station, and so the cycle begins. The layout of this grinder fully guarantees the
coordination among all work stations during its operation and improves the operat-
ing efficiency of the equipment. At the same time, the wafer only needs to be
clamped once to complete both the rough grinding and the fine grinding, which
63 Manufacturing Equipment for Silicon Wafer 1271

Fig. 63.33 Image of a single-side grinder using IFG mode. (Source: CETC Beijing Electronic
Equipment Co., Ltd.)

Fig. 63.34 Rough and fine grinding modes

reduces the number of times that the wafer must be handled and clamped. Since the
rough and fine grinding feed modes use a low-feed grinding speed and a small
grinding force, the grinding area has good cooling and heat dissipation conditions,
and the chip removal process is smooth, thereby further improving the surface
1272 B. Liu

Table 63.12 Main Parameters Sample indicators

technical parameters of
Si wafer diameter/mm 200, 300
single-side grinders with
rough and fine grinding Grinding wheel diameter/mm 200, 300
modes Grinding wheel rotation speed/(r/min.) 1–4000
Grinding wheel feed speed/(μm/min.) 1–999
Grinding thickness detection No contact/online
Grinding mode IFG
Number of chuck tables 3

quality after the silicon wafer is ground. Table 63.12 lists the main technical
parameters of single-side grinders with rough and fine grinding modes.
At present, major manufacturers of single-side grinders for silicon wafers include
CETC Beijing Electronic Equipment Co., Ltd., Disco, Koyo Machinery Industry
Co., Ltd., Okamoto, and Revasum (formerly Strasbaugh).

Edge Polishers

An edge polisher is a type of process equipment that polishes the edge of the Si wafer
using the chemical-mechanical polishing (CMP) method to reduce the roughness
and residual stress on the edge of the wafer.
When the edge of the Si wafer is rounded, due to the grinding effect of the
abrasive on the edge grinding wheel, a damaged layer of a certain depth and a large
degree of surface roughness will always be left on the edge of the wafer, so it cannot
meet the cleanliness requirements of subsequent Si wafer manufacturing processes.
Polishing the edge of the Si wafer can reduce the roughness and contamination on
the edge of the wafer while also eliminating the residual stress from edge machining
and reducing the risk of Si wafer fragmentation.
In practical applications, Si wafers with diameters of 200 mm and 300 mm
generally require edge polishing. As with wafer edge rounding, all parts of the
edges of the silicon wafer need to be processed in edge polishing. Since the Si
wafer has a notch for positioning, the Si wafer edges and the notch edges are
polished separately. Since the Si wafer edges are beveled after edge rounding, the
functions and structure of the edge polisher are relatively complicated.
Si wafer edge polishing is performed using the principle of CMP. Contaminants
such as polishing slurry that remain on the processed Si wafer must be removed by a
cleaning process in a timely manner, so mainstream edge polishers generally include
a postcleaning function.
Polishing the Si wafer notch is a challenge for edge polishers. As shown in
Fig. 63.35, Si wafers that require edge polishing generally have rounded edges
with a “T” shape, which is divided into three parts: the rounded edge front, the
rounded edge side, and the rounded edge back [9]. The notch is also divided into
three parts: the notch front, the notch side, and the notch back, and there is a circular
arc transition among them. In practical applications, the surface type of the notch is
63 Manufacturing Equipment for Silicon Wafer 1273

Fig. 63.35 Schematic of the edge of a silicon wafer

Fig. 63.36 Schematic diagram of the polishing plate edge polishing principle

relatively complicated, and it would be unrealistic to polish the three sides of the
notch separately. Considering that the edge area of the notch is small, a butterfly-
shaped polishing plate is generally used, which directly penetrates into the notch and
applies polishing pressure to complete the notch polishing using the plastic defor-
mation of the polishing pad on the polishing plate.
Si wafer edge polishing is generally carried out using polishing plates as the
operating principle. Each polishing plate has an attached polishing pad and has a
motion module that allows a certain degree of tilt, as shown in Fig. 63.36. The
spindle end clamps the Si wafer through vacuum and rotates around the center of the
spindle. The polishing module is generally composed of four polishing plates,
including an upper-bevel polishing plate, a lower-bevel polishing plate, and two
vertical plane polishing plates. The upper-bevel plate and the lower-bevel plate are
capable of up-and-down and horizontal movement, while the vertical plane plates
can move up and down. Polishing pads are attached to the working surface of the
four polishing plates, which are driven by the driving device to the edge of the silicon
wafer and apply a certain polishing pressure to polish the edges of the Si wafer under
the action of the polishing slurry.
As Si wafers typically need to be cleaned after edge polishing, edge polishers are
automated devices that integrate silicon wafer input, output, notch polishing, edge
1274 B. Liu

Fig. 63.37 Image of a polishing plate edge polisher. (Source: SpeedFam Co., Ltd.) [10]

Table 63.13 Main technical parameters of polishing plate edge polishers

Parameters Sample indicators
Silicon wafer diameter/mm 150, 200, 300
Number of polishing drums 4
Polished silicon wafer diameter/mm 200, 300
Polishing pressure (gf/cm2) 30–200
Upper/lower plate maximum rotation speed (r/min.) 30
Note: 1 gf/cm2 ¼ 0.0980665 kPa.

polishing, and postcleaning and drying. Figure 63.37 shows an image of a polishing
plate edge polisher. Table 63.13 lists the main technical parameters of polishing plate
edge polishers.
Another type of edge polisher uses a polishing drum to polish the rounded edge
front and the rounded edge back at the same time, and then uses the polishing
drum to polish the rounded edge side separately. As shown in Fig. 63.38, the end
of the spindle clamps the Si wafer by vacuum and rotates it around the center of
the spindle. The spindle tilts at a certain angle to align with the “T” tilt angle of the
rounded edge [11]. The axis of the polishing drum spindle is vertical and the
polishing pad is attached to the outside of the polishing drum. The polishing drum
spindle can move up and down as well as horizontally. The polishing drum is
driven by a driving device (not shown in the figure) to the edge of the Si wafer and
applies a certain polishing pressure to polish the rounded edge front of the Si
wafer (direction and position shown in the figure) under the action of the
polishing slurry.
63 Manufacturing Equipment for Silicon Wafer 1275

Fig. 63.38 Schematic of a polishing drum edge polisher

Fig. 63.39 4 Structural drawing of a polishing drum edge polisher

The polishing method shown in Fig. 63.38 can only be used to polish a rounded
edge surface on the Si wafer (such as the rounded edge front of a Si wafer, as shown
in the figure). In order to improve the processing efficiency and reduce the com-
plexity of the equipment, this type of edge polisher is designed with a four-polishing-
drum structure, as shown in Fig. 63.39. A polishing pad is attached to the outside of
each of the four polishing drums and rotates with the spindle of each polishing drum
in the opposite direction of the Si wafer/spindle rotation. The Si wafer/spindle is
tilted, and the four polishing drums are driven by their respective driving devices
(not shown in the figure) to the edge of the Si wafer, where they apply a certain
polishing pressure to polish the rounded edge front, rounded edge side, and rounded
edge back of the Si wafer at the same time under the action of the polishing slurry.
There is also a type of edge polisher with a belt structure, as shown in Fig. 63.40
[12]. The Si wafer rotates while clamped by the spindle. A polishing pad belt within
a tensioning and winding mechanism performs tensioning, polishing belt conveying
and taking up, approaching/retracting, and revolving operations. The polishing
slurry is poured where the polishing belt contacts the Si wafer edge to carry out
1276 B. Liu

Fig. 63.40 Schematic of a belt edge polisher

the edge polishing. Since the Si wafer edge is made up of three parts, namely the
rounded edge front, rounded edge side, and rounded edge back, multiple sets of
tensioning and winding mechanisms are required. Belt edge polishers have better
polishing slurry utilization efficiency, but their structure is complicated. Major edge
polisher manufacturers include SpeedFam and BBS KINMEI Co., Ltd.

Double-Side Polishers

A double-side polisher is a type of process equipment that polishes both sides of a Si

wafer at the same time using the CMP method to reduce the surface microroughness
and improve the global flatness back ideal range (GBIR) and site flatness front least-
squares range (SFQR) of the Si wafer.
In early polishing equipment for Si wafers with a diameter of less than 200 mm,
single-side and double-side polishing processes were optional, depending on the
requirements of downstream users, so multiplate single-side and double-side pol-
ishers were collectively referred to as polishers. With the advent of 300 mm Si
wafers, downstream processes have raised the requirements for the geometric accu-
racy, surface roughness, and surface cleanliness of Si wafers.
The 300 mm wafer polishing process has mainly adopted a combination of double-
side and single-side polishing processes, which has become the standard technological
process. The operating principle and structure of double-side polishers for 300 mm
silicon wafers are basically similar to those of the double-side polishers for Si wafers
with diameters up to 200 mm. However, in double-side polishers for 300 mm Si
wafers, the upper- and lower-polishing plates have a larger diameter, and a maximum
of only three Si wafers can be loaded in each polishing planet carrier.
The number of planet carriers are generally no more than five, as shown in
Fig. 63.41 [13]. Therefore, a relatively small number of 300 mm Si wafers can be
simultaneously processed by double-side polishers. Due to the increased surface
precision requirements after Si wafer processing as well as the enlarged equipment
volume, this kind of equipment is capable of a relatively high degree of manufacturing
63 Manufacturing Equipment for Silicon Wafer 1277

Fig. 63.41 Schematic of the

planet carriers in a double-side
polisher

Fig. 63.42 Image of a double-side polisher. (Source: SpeedFam (USA) Co., Ltd.) [5]

precision and control. In order to reduce the risk of chipping due to manual handling
during Si wafer loading and unloading, some 300 mm double-side polishers are
integrated with an automatic Si wafer loading/unloading unit. Figure 63.42 shows
an image of a double-side polisher. Table 63.14 lists the main technical parameters of
double-side polishers. Major manufacturers of 300 mm double-side polishers include
Suzhou HRT Electronic Equipment Technology Co., Ltd., SpeedFam, FUJIKOSHI,
PR HOFFMAN, and Lapmaster Wolters.
1278 B. Liu

Table 63.14 Main Parameters Sample indicators

technical parameters of
Polishing diameter/mm 1380
double-side polishers
Batch polished wafer quantity (piece) 15 (200 mm), 5 (300 mm)
Polished silicon wafer diameter/mm 200, 300
Polishing pressure/(gf/cm2) 30–200
Upper/lower plate maximum rotation 30
speed/(r/min.)

Single-Side Polishers

A single-side polisher is a type of process equipment that uses the CMP method to
repolish the front side of a 300 mm double-side polished Si wafer in order to reduce
microroughness and haze defects on the surface of the wafer. Because surface
damage defects and surface contamination formed by previous procedures are still
present, when viewed under a microscope, 300 mm Si wafers that have completed
double-side polishing appear to have a layer of haze phenomenon, which can affect
the quality of the subsequent epitaxy process or the performance of the device. A fine
repolishing process is necessary to minimize the haze defects, so single-side
polishing is also called haze polishing. After the 300 mm Si wafers are processed
by single-side polishing, the subsequent manufacturing processes do not involve any
mechanical processes, so single-side polishers are also called final polishers.
Material removal in single-side polishing utilizes the same processing and
removal principles as the Si wafer polisher. Since single-side polishing is fine
polishing, the polishing solution needs to contain fine abrasive to achieve a moderate
removal rate and the corresponding polishing process is generally multiple-stage
polishing. Therefore, the structure of single-side polishing equipment is generally
made up of two or three serial polishing process structures. Figure 63.43 shows the
technological process for a single-side polisher with three serial polishing processes,
which can achieve rough polishing, fine polishing, and ultra-fine polishing results.
The direction indicated by the arrow in the figure represents the process position
sequence of the silicon wafer polishing process. Figure 63.44 shows an image of a
single-side polisher.
In addition, considering the surface contamination on the silicon wafer and the
requirements for the surface topography of the wafer after polishing, single-side
polishers use an open-loop system for polishing slurry in which the slurry is not
recycled. Meanwhile, considering the influence of removal caused by the polishing
pad and the distribution of polishing slurry on the polishing pad, single-side pol-
ishers can theoretically adopt a single-head/single-table (single silicon wafer/single
polishing table) structure (similar to the mode used in CMP equipment), as shown in
Fig. 63.45. In the single-side polishing process, the Si wafer is clamped through
vacuum and held by the retaining ring, which rotates and swings reciprocally with
the polishing head. The pressing mechanism of the polishing head creates pressure
63 Manufacturing Equipment for Silicon Wafer 1279

Fig. 63.43 Process flow chart of a single-side polisher with three serial polishing processes.
(Source: CETC45)

Fig. 63.44 Image of a single-side polisher. (Source: CETC45)

between the Si wafer and the polishing pad as the polishing pad rotates with the
polishing table. The Si wafer’s motion relative to the polishing pad generates
mechanical friction to achieve the removal effect. The polishing pad conditioner
(brush plate) applies a certain pressure and can rotate and swing back and forth to
perform automatic self-sharpening by conditioning the polishing pad, thereby
maintaining the pad’s friction removal performance.
1280 B. Liu

Fig. 63.45 Schematic diagram of the single-side polishing principle

Fig. 63.46 Schematic of a

double-head polishing
structure

Since the polishing slurry in the single-side polishing process uses an open-loop
system, the cost of single-side polishing is high. In order to improve the utilization
rate of the polishing slurry and the processing efficiency of the single-side polisher,
most single-side polishers use a double-head/single-table (double silicon wafer/
single polishing table) structure, as shown in Fig. 63.46.
Based on the number of polishing tables, single-side polishers can be divided into
single-table single-side polishers, two-table single-side polishers, and three-table
single-side polishers. The early single-table single-side polishers use a multihead
(generally four heads) polishing structure, which can significantly improve effi-
ciency and reduce production costs. However, to achieve the automation of pro-
cesses such as rough polishing, fine polishing, and ultra-fine polishing, an automated
Si wafer transfer device needs to be integrated to enable two or more single-table
single-side polishers to be combined. As 300 mm Si wafers are applied in IC
manufacturing at nodes below 65 nm, the quality requirements for Si wafers are
increasing, so three-table polishers have become mainstream equipment on the
market.
63 Manufacturing Equipment for Silicon Wafer 1281

Table 63.15 Main Parameters Sample indicators

technical parameters of
Polishing table diameter/mm 920
single-side polishers
Number of polishing tables 2–3
Number of polishing heads 3–8
Polished silicon wafer diameter/mm 300
Polishing pressure/N 0–2000
Polishing plate rotation speed/(r/min.) 0–120
Polishing head rotation speed/(r/min.) 0–120

Another way to classify single-side polishers is based on the movement path of

the polishing head, by which they can be divided into rotary-type and linear-type
single-side polishers. As shown in Fig. 63.43, all of the polishing heads and
polishing tables of a rotary single-side polisher are arranged around the central
index spindle. The polishing heads (only the first polishing head is shown in the
figure) are rotated to the polishing table of the required station for polishing by the
indexed rotation of the central index spindle. Rotary single-side polishers have a
compact structure. In order to improve production efficiency, current state-of-the-art
polishers with three serial polishing processes feature six polishing heads for simul-
taneous polishing, and two other polishing heads are involved in silicon wafer
loading and unloading. This type of single-side polisher has a total of eight polishing
heads. Three-table/eight-head polishers are the mainstream single-side polishers for
300 mm Si wafers. The limitations on the loading and unloading of silicon wafers in
linear single-side polishers mean that this type of polisher can only be designed with
a double-table/four-head structure. This kind of equipment has low efficiency and
takes up a large amount of space. Table 63.15 lists the main technical parameters of
single-side polishers for silicon wafers.
At present, major single-side polisher manufacturers include the 45th Research
Institute of China Electronics Technology Group Corporation, SpeedFam, Okamoto,
and Lapmaster Wolters.

Final Cleaning Machines

A Si wafer cleaning machine is a type of process equipment for removing contam-

inants such as abrasive particles, organic particles, and trace metals generated on the
surface of polished Si wafers, using physical and chemical cleaning methods to
obtain the required clean surface.
During processing, various contaminants (such as solid abrasive particles, organic
particles, and various metal ions) are generated, which attach to the surface of the
silicon wafers. These contaminants not only affect the quality of the Si wafers during
processing, but may also cause cross contamination and the formation of new
contaminants which are difficult to clean and remove, thus affecting the Si wafers’
final epitaxial quality or device manufacturing quality. Generally, after each proce-
dure in Si wafer processing, there is a cleaning process; the contaminants of a given
1282 B. Liu

procedure are required to be cleaned within that procedure, so as not to affect the
process quality of the next procedure and avoid cross contamination.
In Si wafer processing procedures such as slicing, edge rounding, lapping,
etching, and polishing, cleaning is required at the end of each process to minimize
the contaminants left from that processing stage and meet a certain cleanliness
standard. Since each procedure has a different focus for cleaning away contamina-
tion, the function of the equipment used for each cleaning process is different and it
can be applied as the independent cleaning equipment for use on the wafer prepa-
ration process line. However, etching cleaning is an exception, as the cleaning
function is integrated into the etching equipment.
The final polishing of the Si wafer is the final process of silicon wafer preparation
processing. After polishing, the Si wafer is precleaned, and then the physical
dimensions, resistivity, warpage, flatness, and other properties are visually inspected.
After the wafer passes these inspections, the cleaning procedure begins, which is
known as final cleaning.
Final cleaning is a key process for ensuring the cleanliness of the Si wafer surface.
This procedure can remove fine particles and metal ions on the surface of the Si
wafer to meet the process requirements of surface cleanliness in the subsequent
manufacturing of semiconductor devices. With the increasing requirements for the
surface cleanliness of 300 mm Si wafers, final cleaning equipment technology
continues to develop and the process complexity is increasing.
One type of contamination left on the surface of Si wafers is that which is formed
by the adsorption between contaminant particles and the wafer surface caused by
intermolecular van der Waals forces (VDW). A wide range of particles with large
sizes can be adsorbed by these forces. After the particles have been adsorbed on the
wafer, a relatively large distance remains between the particles and the wafer surface,
the bonding force is weak, and many kinds of contaminants can be physically
adsorbed. It is relatively easy for these contaminants to come off and they can
generally be removed by physical methods (such as ultrasonic vibration, rinsing,
and brushing). Another type of contamination is created by chemisorption, in which
chemical bonds or coordination compounds are formed by electron transfer (ion
bond) or electron pair sharing (covalent bond) between the wafer surface and
contaminants. Chemisorption acts at a close distance with stable bonding, creates a
stable and fixed adsorption force, and only adsorbs certain types of atoms selectively,
so it is difficult to remove this kind of contamination. These contaminants can
generally be removed by chemical methods (such as the RCA method).
The RCA cleaning method was created by Kern and Puotinen et al. at the RCA
laboratory in N.J. Princeton. The RCA cleaning method is a typical, standard wet
chemical cleaning method in semiconductor manufacturing processes. Solutions
used in the RCA cleaning method mainly include the following four types.
(1) SPM (sulfuric/peroxide mixture) solution, also known as SC3 (Standard Clean
3) solution, which is prepared from aqueous H2SO4/H2O2 and needs to be heated to
120–150  C. (2) DHF (dilute hydrofluoric acid) solution, or diluted HF solution, the
temperature of which is controlled at 20 to 25  C. (3) APM (ammonia/peroxide
63 Manufacturing Equipment for Silicon Wafer 1283

mixture) solution, also known as SC1 (Standard Clean 1) solution, which is a

mixture of NH4OH/H2O2/H2O and needs to be heated to 70–80  C. (4) HPM
(hydrochloric/peroxide mixture) solution, also known as SC2 (Standard Clean 2)
solution, which is a mixture of HCl/H2O2/H2O and needs to be heated to 70–80  C.
Final cleaning machines generally use process schemes that combine RCA
cleaning, physical cleaning, and drying. Drying methods include centrifuge drying
(Spin drying) combined with strong convection drying using clean air in the
chamber, Marangoni drying, hot nitrogen (N2) drying, and isopropyl alcohol (IPA)
vapor drying. Centrifuge drying is safe and efficient, but provides poor control of
surface particles on the silicon wafers after they are dried; it is usually used for
drying Si wafers with diameters of 200 mm or less. For 200 mm and 300 mm Si
wafers, isopropyl alcohol vapor drying or Marangoni drying is usually used.
Figure 63.47 shows a typical process flow chart for a final cleaning machine.
Major manufacturers of final cleaning machines include the 45th Research Institute
of China Electronics Technology Group Corporation, JAC, Akrion Systems, MEI,
and Global Zeus.
Figure 63.48 shows an image of a final cleaning machine. Table 63.16 lists the
main technical parameters of final cleaning machines.

Fig. 63.47 Typical process flow chart of a final cleaning machine

Fig. 63.48 Image of a final cleaning machine (Source: CETC45)

1284 B. Liu

Table 63.16 Main technical parameters of final cleaning machines

Parameters Sample indicators
Etched wafer diameter/mm 200, 300
Efficient/ultra-efficient air filtration Built-in
Solution type SC1/SC2/DHF/O3
Megasonic wave 1MHZ
Wafer transmission form Automatic robot transfer
Rinsing tank QDR
Cleaning method Solution circulation overflow and online heating
Drying method Marangoni

References
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Stockbarger method. J. Shaanxi Univ. Sci. Technol. 22(5), 92–99 (2004)
2. Koyo Thermo Systems Co., Ltd. http://www.koyo-thermos.co.jp/english/products/handou/
handou_vf5900.html
3. W. Mingming, Z. Zhaozhong, W. Shaolong, Manufacturing technology of monocrystalline
silicon Wafers. Manuf. Technol. Mach. Tool 3, 72–75 (2005)
4. Lapmaster Wolters GmbH. http://www.peter-wolters.com/en/machines/double-sided-
processing
5. SpeedFam USA. https://www.speedfamusa.com/double-side-machines
6. Z.C. Lia, Z.J. Peia, G.R. Fisher, Simultaneous double-side grinding of Si wafers: a literature
review. Int. J. Mach. Tool Manu 46, 1449–1458 (2006)
7. Koyo Machine Industries CO., LTD. http://www.koyo-machine.co.jp/English/pdf/machine/
Special_3.pdf
8. S.C. Kimff, S.J. Lee, et al., Profile simulation in mono-crystalline silicon wafer grinding.
Korean Soc. Precis. Eng. 21, 26–33 (2004)
9. S. Hakomori, Wafer edge polishing system: US, 6840841B2.2005-01-11
10. SpeedFam Company Limited. http://www.speedfam.com/en/products/edge_polisher.html
11. M. Ohnishi, Edge polisher and edge polishing method: EP, 1000703A2. 2000-05-17
12. S.-H. Ko, Sunnyvale. Methods and apparatus for cleaning a substrate edge using chemical and
mechanical polishing: US, 0207093Al.2008-08-28
13. G. Wenski, T. Altmann, et al., Double-side polishing – a technology mandatory for 300 mm
wafer manufacturing. Mater. Sci. Semicond. Process. 5, 375–380 (2003)
Mask Manufacturing Equipment
64
Baoqin Chen, Boru Feng, and Jesse Jen-Chung Lou

Contents
The Development and Prospect of Photomask Manufacturing Equipment . . . . . . . . . . . . . . . . . . . 1286
Overview of Photomask Manufacturing Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
Photomask Inspection Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
Laser Differential Confocal Microscope, LDCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
Photomask CD Measurement System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
Inspection System for Photomask Defects and Contamination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
Automatic Photomask Inspection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
Photomask Repair System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
Optical Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
Photo-Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
Laser Direct Writing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
DMD-Based Laser Photomask Direct Writing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
Electron Beam System for Photomask-Making . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
Electron Beam Projection Lithography System for Photomask-Making
(EBPLS for Photomask-Making) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
Resist Processing and Cleaning Equipment for Photomask-Making . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
Photoresist Coater for Photomask-Making . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1315
Photoresist Stripper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316
Photomask Duplicator (Photomask Copier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318
Photomask Wet Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319
Photomask Dry Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321
Pellicle Mounting Instrument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322

B. Chen (*)
Institute of Microelectronics (IME), Chinese Academy of Sciences, Beijing, China
e-mail: chenbq@ime.ac.cn
B. Feng
Institute of Optics & Electronics (IOE), Chinese Academy of Sciences, Beijing, China
J. J.-C. Lou
School of Software and Microelectronics, Peking University, Beijing, China
Institute of Microelectronics, Peking University, Beijing, China
e-mail: jesselou@ss.pku.edu.cn

© Publishing House of Electronics Industry 2024 1285

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_64
1286 B. Chen et al.

Photomask Pattern Data Processing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324

Abstract
Photomask manufacturing equipment plays a very important role in IC chip
processing. The improvements of lithography technologies depend on microme-
ter/nanometer pattern transferring and mask manufacturing technologies. Even
NGL (Next-Generation Lithography) technologies such as EUV (Extreme Ultra-
Violet) Lithography, EBL (Electron Beam Lithography), X-ray Lithography, and
IL (Interference Lithography) currently or will rely on advanced photomask-
making technologies. This chapter will mainly introduce mask pattern layout
edit and data processing equipment, mask quality inspection and defects detecting
and repairing equipment, mask direct writing equipment, optical pattern genera-
tors, laser pattern generators (LPG), and Electron Beam Pattern Generators.

Keywords
Mask-making · Optical pattern generator · Photo-repeater · Laser lithography
system · Electron beam lithography system · Mask copier · Pellicle

The Development and Prospect of Photomask Manufacturing

Equipment

In the development of IC industry, the development and progress of photomask

manufacturing technology, photolithography technology, and its corresponding
equipment play a very important role.
For the IC manufacturing, the photolithography process requires a set of photomask
plates with specific geometry patterns, known as the photomask in the industry. A
photomask is a masking template that can selectively block the penetration of light,
radiation, or particles (energetic ions). The photosensitive material-coated photomask
plate of no masking pattern is called blank chrome plate or blank ultrafine dry plate.
Photolithography is a technology to transfer the IC layout pattern of photomask to the
photoresist-coated substrate surface so as to form a patterned corrosion-resistance
photoresist layer through the exposure and development process. This corrosion-
resistance photoresist layer on the substrate can protect the substrate from etching in
the etching process, can block ions in ion implantation process, and can block metal
film etching to form aluminum interconnect in metallization process. Therefore, the
photomask plate is a necessary integral part in the semiconductor fabrication process.
In addition, the patterned silicon dioxide film or metal film with masking function on
the surface of semiconductor substrate is called the hard mask [1], while the patterned
photoresist layer in photolithography is called the soft mask.
Photomask-making process includes the front-end steps of photomask pattern
design, photomask pattern editing, and photomask pattern data format conversion, as
well as the back-end steps by photomask manufacturing equipment for photomask
64 Mask Manufacturing Equipment 1287

pattern exposure, development, etching, cleaning and drying, and photomask defect
inspection and repair.
In early years, photomasks consisted of only two areas; the transparent and
opaque, which were called binary intensity masks (BIM). It is coated on the
emulsion photoplate surface with a photosensitive latex layer (such as silver
halide-containing emulsion). After exposure, development, fixing, and other pro-
cesses, black silver particles are produced by the reduction of silver halide in the
exposed area to form the masking area, while the silver halide in the unexposed area
is dissolved by the fixing solution and leaves only the transparent latex layer.
At present, the photomask mainly adopts chrome plate, also called Chromium Photo
Plate. That is, a chromium metal film is evaporated or sputtered on the glass (or quartz)
substrate and then oxidized to form an ultra-thin CrOx layer on Cr surface, thereafter, a
photoresist layer is coated on the surface of CrOx/Cr/quartz (or glass) substrate to form
the blank chrome plate. The steps of the computer-controlled photomask manufactur-
ing process are as follows; (1) photomask exposure equipment is adopted to expose the
photomask pattern, (2) the patterned corrosion-resistance photoresist layer is formed on
the chromium film surface through the development process, (3) the unmasked chro-
mium film is removed by the etching process. Then the chrome photomask is prepared.
This overall process is called photomask pattern transfer.
Along with the progress of the photolithography technology, the main develop-
ment in advanced photomask manufacturing technology, based on the resolution
enhancement technology (RET) of wavefront engineering technique, includes Phase
shift mask (PSM), optical proximity correction (OPC) photomask manufacturing
technology, Off-axis illumination (OAI), the Sub-Resolution Assistance Feature
(SRAF) technology, immersion lithography technology, etc.
By using the wavefront engineering technique, the resolution of optical exposure
technology can exceed the resolution limit of optical theory and perform the pro-
cessing resolution of subwavelength, half-wavelength, even one fourth wavelength or
one eighth wavelength. The most representative wavefront engineering techniques are
phase shift mask (PSM) and optical proximity correction (OPC) photomask.
There are two kinds of techniques for optical proximity correction (OPC). One
kind is based on the rules of the optical proximity correction (Rules-Based OPC),
that is, according the measured pattern distortion data of proximity effect from a
large number of photomask-making results, a set of photomask pattern correction
rules can be summarized to implement the geometric correction such as serifs on the
proximity effect affected portion of the photomask, or to add extra subresolution
patterns such as scattering bars in the uneven pattern density region. Another kind
optical proximity correction method is based on the diffraction theory model
(Model-Based OPC), namely according to optical diffraction theory model and resist
chemical reaction model of the developing process, the deviation of post-
photolithography between the edge contour of distorted pattern and the original
designed pattern data can be calculated to define the edge placement error (EPE) so
as to implement the pattern correction technique [2].
In recent years, the emergence of the design and manufacturing technology for
double patterning photomasks, collaborative Source-Mask Optimization (SMO)
1288 B. Chen et al.

technology, the design and manufacturing technology of Guide Stencil for Directed
Self Assembly, inverse photolithography-based photomask design and manufactur-
ing technology, computational lithography-based photomask design and
manufacturing technology, etc., are the important methods to further improve the
optical lithography resolution and extend the lifetime of existing optical lithography
equipment.
In short, the progress of the photolithography is dependent on the micro/nano-
pattern transfer technology and the photomask manufacturing technology, even in
the next-generation lithography technology, including extreme ultraviolet (EUV)
lithography, electron beam lithography, X-ray lithography, computational lithogra-
phy, interference lithography, and photomask-less lithography technology, etc., still
directly relies on the advanced photomask manufacturing technology very much.
The advanced semiconductor industry requires the most precision equipment to meet
the fabrication of advanced IC productors. And currently, only one or two equipment
vendors can provide the most advanced photomask-making equipment and photo-
lithography equipment in the world. At present, the high-precision photomask
manufacturing equipment and photolithography equipment adopted in China are
mainly imported from abroad.

Overview of Photomask Manufacturing Equipment

Photomask manufacturing equipment [1], commonly known as photomask plate-

making equipment, mainly consists of the integrated circuit layout editing and
pattern data processing system, and the manufacturing equipment for the reticle or
photomask template of integrated circuits. It includes photomask pattern editing and
data processing equipment, photomask data format conversion system, reticle fab-
rication equipment, optical step-and-repeat system, photomask duplicator (called as
photomask copier), optical pattern generator, laser pattern generator, electron beam
pattern generator, etc. With the development of CAD/CAM technology, the
computer-controlled optical pattern generator has replaced the equipment for the
preparation of reticles.
In early years, photomask-making equipment included a digitizer, a
coordinatograph, an automatic drafter, and a first reduction camera.

1. Digitizer: a pattern data processing system that reads the coordinates (such as
vertex coordinates) which highlights the feature points of the pattern from the IC
design layout, and converts them into an acceptable format for a pattern generator
or other pattern generating system.
2. Coordinatograph: a red ruby film cutting instrument applied to draw the IC design
layout with the original size. According to the design data corresponded rectan-
gular coordinate axis, this instrument uses a drawing pen with a two-dimensional
motion function on the coordinate platform surface to accurately positioning and
draw the IC photomask patterns. A flexible transparent resin substrate with red
ruby film is then attached to the drawing. After the manual cutting and the
64 Mask Manufacturing Equipment 1289

stripping of unnecessary portions of the red ruby film, the original patterned red
ruby film of integrated circuit with a range of magnification is formed. Through
the subsequent initial shrinking process, the original patterned red ruby film of IC
can be made into a reticle. And then through the fine shrinking step-and-repeat
exposure step on the reticle, the master photomask or the working photomask is
fabricated.
3. Automatic drafter: a computer-controlled instrument for drawing the comprehen-
sive layout with colored pens. It can automatically draw the corresponding color
layout of each process layer on drawing paper with a certain magnification ratio,
so as to illustrate the overlapping relationships between each layout layer of the
integrated circuit. This can also facilitate the photomask layout designer to check
the integrity of patterns and overlapping relationships. Later, under the computer
control and according to the input pattern data, the technique for direct red ruby
film cutting and film removal on the paint film or red ruby film-coated flexible
transparent substrate is developed to make enlarged IC original layout.
4. First reduction camera: It is short for primary shrinking system. It applies the
optical imaging principle to zoom out the original patterned image of an inte-
grated circuit in accordance with a certain proportion, and forms image on the
photosensitive film of emulsion plate as a latent image, then through the devel-
opment step to generate a reticle. Usually, the primary shrinking system is a large
track type camera with variable reduction ratios. The original red ruby patterned
film cut with the enlarged IC pattern is pasted on the large light box in the track.
The required magnification ratio of image is achieved by adjusting the distance
between the original red ruby patterned film and the camera.

At present, advanced photomask manufacturing equipment, such as laser and

electron beam pattern generators, are adopted for the fabrication of reticles. These
new pattern generators can directly fabricate working photomasks for aligners or
reticles for the projection lithography equipment (e.g., stepper, scanner), without the
previous required processes of layout drawing, ruby film cutting, layout first reduc-
tion, layout fine reduction, and layout duplication, etc. [3].
Photolithography technology is evolved from the technology of the photographic
exposure and etching process in lithography, and the photomask of photolithography
is just the photographic plate of photography or the lithographic plate in lithography.
In printing industry, lithography, that is, a technique to transfer the pattern of
photographic plate onto the photosensitive material-coated lithographic plate (called
as slate) through a photochemical reaction, so as to form a patterned etching-resistant
protective layer on the lithographic plate, and then with a subsequent etching process
to implement the pattern transfer from the patterned protective layer to the litho-
graphic plate to obtain a patterned lithographic plate for printing. Similar to the
mentioned printing technology, semiconductor manufacturing is a manufacturing
process that transfers the layout of an integrated circuit layer by layer from reticles or
photomasks to a semiconductor chip through a series of photolithography techniques
and corresponding planar manufacturing processes. For the increasingly high-
resolution requirement in photolithography for advanced IC fabrication, it is
1290 B. Chen et al.

necessary to apply advanced electron beam photomask manufacturing system and

nano-beam direct writing system for the reticle fabrication.

Photomask Inspection Equipment

Photomask inspection equipment refers to the key equipment to inspect the pattern
defects, linewidth, and overlaying accuracy of photomask or reticle in the photomask
manufacturing process by using appropriate methods, so as to ensure the fabrication
of high-quality photomask as well as to improve the yield, stability, and reliability of
IC chips in mass production. Therefore, in each process of photomask fabrication
and the entire process of lithography, the quality control of photomask plate mate-
rials and the photoresist materials must be carried out. Meanwhile, it is necessary to
implement a strict quality inspection and testing to guarantee the photoresist coating
process, photomask pattern exposure process, photomask developing process, chro-
mium film etching process, photomask cleaning and baking process, photomask
delivery and packing materials, etc. to meet the standards. In addition, photomask
inspection equipment is also called photomask quality checking equipment.
Photomask quality control mainly includes the flatness and defect inspection of
photomask plate, the uniformity and defect inspection of photoresist on photomask
plate, the exposure and development process of photomask, chromium film etching
process, defect inspection of photomask after cleaning and baking steps, pattern
linewidth, pattern distortion, pattern contrast, line edge roughness, pattern integrity,
overlapping precision between pattern layers, the orthogonality of pattern array,
positioning accuracy, etc.
Photomask quality inspection equipment, mainly includes photomask template
surface inspection system adopted to check the flatness, surface defects, and partic-
ulates of photomask template; photomask comparator system adopted to inspect the
photomask-related overlaying precision, the pattern orthogonality pattern reduction
ratio, the distribution precision of different inserted patterns, etc.; the CD linewidth
measurement instrument adopted for the precision and uniformity inspection of
critical dimension; and photomask defect inspector system applied for the inspection
of various pattern defects on photomask template, etc.
In early years, photomask linewidth measurement equipment and photomask
comparator equipment show very important position in the manufacturing of pho-
tomask and integrated circuit processes. In order to ensure the accuracy of photo-
mask manufacturing and chip processing, it is necessary to perform the inspection of
pattern linewidth, overlaying precision, and defect density for all critical process
steps. Along with the development of the photomask process inspection technology,
the functions of these two devices have already been integrated together in the
advanced automation inspection equipment for mass production, such as automatic
photomask inspection system, photomask CD measurement system, surface defect
and contamination detector (SDCD), etc.
The mainstream automatic multifunction photomask quality inspection system
can perform the mask and chip defect inspection, fine linewidth inspection, precise
64 Mask Manufacturing Equipment 1291

inspection for long-range relative positions, and the automatic scanning inspection
for defect location, data storage, data analysis, output printing, and other functions.
This kind automatic inspection equipment is the necessary equipment for photomask
quality inspection and process quality control in both photomask factories and IC
manufacturing factories.
Photomask inspections in laboratory usually adopt traditional methods. For
example, the high-magnification (500X–1000X) optical microscope is mainly used
for the observation of micrometer grade pattern size. The phase contrast microscope
uses the overlap of images with different color from the left and right eye pieces and
the relative displacement value to measure the pattern linewidth. In addition, both
laser confocal scanning microscope and differential confocal laser scanning micros-
copy, which can achieve the nanoscale resolution for pattern observation due to the
higher resolution of confocal microscope, are good submicron line pattern observa-
tion tools. Also, the optical linewidth inspection instrument with precision scanning,
grating positioning, and laser positioning mechanism is applied to measure photo-
mask pattern linewidth. Furthermore, the scanning electron microscope is the most
powerful inspection tool for nanoscale pattern linewidth in laboratory.

Laser Differential Confocal Microscope, LDCM

Laser scanning confocal microscopy can perform higher image resolution than
traditional optical microscopes in pattern inspection for wafer or photomask. To
compare with atomic force microscopy, electrostatic force microscope, magnetic
force microscope, near-field optical microscope, and photon scanning tunneling
microscope, confocal microscopy has the advantages of no sample preparation
procedure, large measuring range, fast speed inspection, low cost, no damage to
the measured surface, and direct surface profile and morphology measurement for
pattern structures with step height over half of the wavelength, etc.
Laser differential confocal microscopy is developed on the basis of laser scanning
confocal microscopy [4], also known as the heterodyne confocal measurement
system (HCMS). A high-resolution laser differential confocal microscope for pho-
tomask inspection is shown in Fig. 64.1a. Its inspection unit is divided into two parts,
namely, two pinhole detectors, in which one pinhole detector is placed in the front
focal plane of the objective lens and another one is placed in a symmetrical position
behind the objective lens, as shown in Fig. 64.1b. Two measuring laser beams are
respectively passed through these two pinhole detectors which are symmetrically
deviated from the focal plane of the objective lens for the subtraction of two laser
signals. Then the response curve of bipolar differential confocal characteristics with
absolute zero point can be obtained through the differential calculation for the
intensity of response signals. The absolute zero point of the characteristic curve
corresponds strictly to the focus of the objective lens; therefore, the detection
sensitivity along the optical axis direction is improved. The response characteristic
curve is linear within the range of full width at half maximum (FWHM) along the
optical axis of objective lens. When the sample height is within the linear range of
1292 B. Chen et al.

Fig. 64.1 Diagram of high-resolution laser differential confocal microscope for photomask
inspection. (Courtesy of Beijing Institute of Technology)

the differential confocal curve, the 3D morphology information of the sample can be
obtained by a single direct scan on the x-y focal plane, in which the scanning speed is
improved. As the sample height exceeds the linear range, it is necessary to scan the
sample layer by layer, and then perform the data processing on the measured
two-dimensional image to obtain the three-dimensional morphology information
of the sample. This technique can be applied to form the 3D imaging of
micronanostructure [5].
Laser differential confocal three-dimensional imaging technology performs two
measurement methods. One method is to use the zero point of differential confocal
characteristic curve as the original reference point on the inspected pattern for
measurement focusing and positioning, and then apply the three-dimensional scan-
ning technique to scan the pattern structure to achieve the formation of scanning
images. The other method is to implement the microrange imaging along the vertical
axial direction in the linear region of the differential confocal curve, so as to realize
the 3D imaging for this microrange area by combining with the two-dimensional
scanning mechanism, and then extend the scanning range along the vertical optical
axis by using the large-range axial scanning mechanism to achieve the large-range
3D imaging for whole pattern.
Laser differential confocal spectrum scanning imaging/detection technology is to
adopt the laser differential confocal microscopy for the spectral imaging. It adds a
one-dimensional spectral information on the basis of two-dimensional space imag-
ing, mainly adopts the laser differential confocal technology to accurately determine
the focus point of the sample, and obtains the spectral information at this focus point
of the sample, and then scans the sample along the x and y directions to obtain the
64 Mask Manufacturing Equipment 1293

Raman spectral image. The response accuracy of Raman spectroscopy technology in

optical axis can be improved by detecting the material composition and structure
according to the molecular fingerprint characteristics between the spectra. It is
usually applied for the high-precision imaging and detection of microareas.
Therefore, the adoption of laser differential confocal spectral scanning imaging/
detection technology can effectively improve the spatial resolution of the micro-
scope to the scale of 100 nm. Meanwhile, this technology can also perform the
vertical detection function and 3D imaging capability on the scale of tens of
nanometers [6].

Photomask CD Measurement System

The photomask Critical Dimension measurement system is an instrument to measure

the linewidth of Critical Dimension (CD) patterns in lithography and photomask
manufacturing, and can be applied to measure the linewidth uniformity and
linewidth accuracy of critical dimension patterns in the whole photomask or all
chips on the whole wafer. The uniformity and the accuracy error of line width of
critical dimension (CD) patterns are found through the measurement analysis, so as
to guide the improvement of process technology and control the quality of lithogra-
phy technology or photomask manufacturing process. In the early stage, the unifor-
mity and line width accuracy of critical dimension patterns were measured manually
by means of microscope, while in the mass production, the automatic critical
dimension measurement system was used for inspection and data analysis according
to the measured results. For masks or wafers with large critical dimension patterns,
an optical or laser automatic critical dimension measurement system can be applied
to inspect them. For nanoscale patterns of photomask or wafer, it is necessary to
adopt the Critical Dimension Measurement Scanning Electron Microscope system
(CD-SEM) for pattern inspection. In general, the operation method of CD measure-
ment is divided into three types: Automatic Operation Method, Manual Operation,
and Semi-auto Operation. The measured targets include lines, gaps, spacing, holes,
box-in-box, and other pattern types. The analysis of measured results includes
alignment error, image resolution, magnification, measurement accuracy, dynamic
repeatability, linearity, reproducibility, static repeatability, etc.
Note that Critical Dimension (CD) and Feature Size are two different concepts.
The Critical Dimension refers to the dimension of a special inspection pattern set on
the photomask to evaluate and control the process precision for each layer, also
known as the evaluation dimension. Feature size refers to the minimum dimension
predicted by Moore’s law at a certain technology node of IC chip manufacturing
process, such as 28 nm, 16 nm, and 10 nm technology nodes. The linewidth of
critical dimension in the inspection pattern for each photomask layer can be designed
according to the deviation caused by the specific process of each layer in integrated
circuit. Moreover, each edge of the inspection pattern can be scaled appropriately to
1294 B. Chen et al.

offset the possible variation in linewidth caused by the process, which is convenient
to visually observe and inspect the process precision. Therefore, on a set of litho-
graphic photomasks for the same process node, the linewidth of the critical dimen-
sion in the inspection pattern can be different between different photomask layers.
The size scaling of different functional layers can also be different (e.g., metal
1 layer, metal 2 layer, etc.), and the smallest critical dimension in a set of lithography
photomasks (such as the gate length in a CMOS process) reflects the feature size of
the process technology nodes.
Figure 64.2 shows a CD-SEM system for photomask inspection and Fig. 64.3
shows the schematic of a coordinate measurement stage for large area photomasks.

Fig. 64.2 CD-SEM for photomask inspection. (Courtesy of Zhongwei Mask-making Co.)

Fig. 64.3 Schematic of a

coordinate measurement stage
for large area photomasks.
(Courtesy of Qingyi Mask-
making Co.)
64 Mask Manufacturing Equipment 1295

Inspection System for Photomask Defects and Contamination

There are two kinds of tools for photomask defects inspection; one is the Surface
Defect and Contamination Detector (SDCD), which is applied to inspect surface
defect and contamination on photomask, the other one is the photomask comparator
by using of die to design or die to die comparison to inspect the defects of
photomask.
The surface defect and contamination inspection system based on the focused
laser beam scanning is an instrument to inspect the surface defects and contaminants
on photomask. This instrument can distinguish variant types of defects according to
the information from the scattering light of laser beam. Not only the position and size
of defects can be measured, but also functions of defect counting, display, printing
map of defects, density of defects, and defect statistics can be integrated in the
inspection instrument. Based on the Thermal Wave technology, another defect
detector called Subsurface Defect Detection System (SDDS) is applied for wafer
or photomask surface inspection. That is, an Argon laser beam is projected on the
sample surface to generate thermal wave and plasma wave. These wavefronts will
show a slight variation on defects during the propagation. The variation of wavefront
can be detected and analyzed to characterize the surface defects. This SDDS is a
nondestructive and in situ inspection tool.
In addition, there is another defect inspection instrument based on pattern
enhancement, in which the coherent laser light is applied to scan the patterned
images on photomask or wafer to reveal defects. The intensity of diffraction light
on regular patterns and defects are quite different, therefore, defects on photomask or
wafer can be identified. It is understood that the sidewalls of pattern edge on
photomask or wafer are nearly vertical; however, sidewalls of defect edge are
irregular and generate serious light scattering. So, defects can be detected through
the diffraction enhancement or reduction effect with a coherent laser light scanning
on photomask surface. In addition, between the objective lens and the imaging focal
plane, there is a Fourier transformation spatial intensity distribution wave filter
which can block the squaring information but allow the diffraction light induced
by randomly distributed defects permeate the spatial wave filter. To combine the
surface defects and contamination inspection system with the mask defect repairing
system, defects on photomask can be located and repaired according to the
measured data.
There are two kinds of inspection methods for the photomask comparator, that is,
die to die comparison and die to data comparison. Die to die method compares the
video signals from each point of two different dies to find out the location and size of
clear and opaque defects on photomask. Die to data method compares the pattern
imaged on photomask to the designed CAD pattern data to find out the location and
size of clear and opaque defects on photomask.
In early years, mask defect inspection is performed by an optical microscope with
dual photomask stages and a separate view field as a photomask comparator.
Patterned images on photomask or reticle for different layer process were aligned
and overlapped to find out registration error and random defects. Also, to compare
1296 B. Chen et al.

the same pattern of two photomasks can show repeating or random defects generated
from the photomask-making process. Furthermore, there are two methods for align-
ment measurement. The method of images alignment could be manually performed
with magnified patterns to directly measure the alignment deviation between two
photomasks. However, manual inspection by eye viewing could probably lead to
man-made measurement errors. Another alignment method is to measure the coor-
dinate of alignment marks or the CD features with the laser interferometer and do
data comparison with the standard photomask, which demonstrates high accuracy
and wider measurement range.
In mass production, there are two automatic inspection approaches. One is the
pattern comparison between two dies located on different areas of the same photo-
mask to implement the quick inspection. The other approach adopts three colored
video cameras to image three dies simultaneously. Each die image is overlapped
using one of three different colors (Red, Yellow, Blue) to identify defect type, size,
and location. Defect-free patterns show black coloration while defects appear as
color spots due to the absence of one or more colors.

Automatic Photomask Inspection System

The automatic photomask inspection system is an automatic photomask defect and

precision inspection instrument developed on the basis of the surface defect and
contamination inspection instrument. It applies the method of comparison or direct
measurement to automatically inspect the type, position, and size of the defects for
the reticle and magnified fine patterns. The stored inspection data form the basis for
photomask repairing. There are two kinds of photomask inspection methods,
namely, pattern comparison method and pattern-data comparison method. The
pattern comparison method can accurately inspect various defects of photomask
pattern. The pattern-data comparison method can inspect the actual errors and
defects between the photomask pattern and the original design pattern. The key
technologies of photomask automatic inspection include automatic focusing,
imaging by the flying spot scanning of high-resolution laser, dynamic automatic
alignment compensation, and as well as interface with computer and defect repair
system, etc. In general, the inspection modes supported by the automatic photo-
mask inspection system include the inspection of no pattern substrates (for the
inspection of particles, scratches, pinholes, and other defects on the surface of bare
wafers or bare photomask plates), pattern inspection of “Die to Die” type, auto-
matic critical dimension (CD) inspection, measurement of overlapping precision
for photomasks, automatic defect inspection, overall area inspection and custom-
ized area inspection, defect results reinspection (Review), data docking with the
photomask repair system, distributed parallel computing with GPU high-
performance computer, etc.
Automatic photomask inspection systems usually have the following functions:
64 Mask Manufacturing Equipment 1297

1. The resolution of defect can be set: In order to meet the accuracy requirements of
various defect inspections, the capture size of the smallest defect can be set in the
system.
2. The function of partition inspection: The inspection area and noninspection area
in the layout of photomask can be specified to improve the inspection efficiency.
3. The parameter saving and loading of inspection programming (Recipe): The
inspection parameter can be saved as a file, and the existing recipe file can be
loaded in the programming.
4. Automatic alignment and automatic positioning: To simplify the manual oper-
ation, the system provides an automatic one-key alignment function, which can
effectively improve the operation efficiency and complete the positioning auto-
matically before the inspection starts.
5. Efficient and reliable “Z” scans: The system adopts the “Z” scan path for the
rapid inspection and supports the Rescan function under abnormal conditions.
6. Defect comparison: To provide intuitive and easy-to-use defect comparison
function that can be compared with the GDS graphics.
7. Combination of defect results: When some defects are densely distributed (espe-
cially particle defects), these multiple defects can be combined into one defect
through this function, effectively reducing the time of manual confirmation.
8. Defect reinspection (Review): After the inspection procedure is completed, the
system provides one-key defect positioning function to facilitate the reconfir-
mation of defects.
9. Fast and flexible defect classification: The system provides common defect
classification by default and supports the customized classification. In addition,
this system also provides one-key batch defect confirmation function, which can
improve the efficiency of result confirmation.
10. Support multiple formats for defect reports: The system supports the generation
of defect reports in Word, Excel, PDF, and other formats based on the inspection
results.
11. Support KLA defect reinspection function (Review): In order to make effective
use of LA’s system, the defect confirmation of KLA can be completed on this
system, saving the operation time for KLA to perform the defect inspection, and
maximizing the capability of KLA system.
12. Support the docking with photomask repairing system: To support the data
docking with a third-party photomask repairing system. KLA photomask
inspection system combines image scanning technology and advanced image
processing technology to capture image defects on the photomask.

To take KLA photomask automatic inspection system as an example, the main

configuration of this equipment includes the main system (Tera StarFE/IS) and the
plug-in subsystems. There are three kinds of plug-in subsystems as follows.

1. KLA95i: Its main function is to access and analyze inspection data, and to output
inspection report and recipe decoding.
1298 B. Chen et al.

Fig. 64.4 Image of the automatic photomask inspection system. (Courtesy of Zhongwei Mask-
making Co.)

2. The data preparation system (DPS): Its main function is to compare the inspection
results with the database for data processing and recipe decoding.
3. Linear conditioner: To provide stable current for the main system.

The KLA automatic photomask inspection system also provides functions includ-
ing the inspection of photoresist-free photomask plate, binary intensity mask (BIM)
with pellicle, and phase shift mask (PSM).
With the improvement of technology and the increasingly smaller feature size of
ICs, the photomask overlapping problem is solved mainly by improving the expo-
sure positioning accuracy of photomask manufacturing system. The advanced pho-
tomask direct write system and the electron beam photomask direct write system are
equipped with the function of pattern self-inspection for photomask, including the
function of self-checking and self-adjusting for the positioning accuracy of the
photomask patterns after the exposure and development.
Figure 64.4 shows the image of the photomask automatic inspection system.

Photomask Repair System

Photomask Repairing System makes use of the high-energy radiation beam (ion
beam or laser beam) to repair defects on photomask with heat evaporation method or
photochemical vapor deposition method. Photomask repairing process is an impor-
tant method to make defect-free photomasks, and also extend the lifetime of photo-
mask as well as save the cost of photomask-making. There are some clear or opaque
64 Mask Manufacturing Equipment 1299

defects on the patterned chromium film of photomask due to factors of material,

environment, and process in the photomask fabrication. A strict defect inspection
and repairing for photomask is required prior to the photolithography process of IC
fabrication. Defects such as islands, burrs, and line bridges on clear area of photo-
mask should be removed. Pin holes, pits, and broken lines on opaque area should be
filled with metal deposition. In general, Automatic photomask repairing system will
follow the measured data of defects provided by the photomask defect inspection
system to implement the photomask repairing.
At early stage, the feature size on photomask was in micrometer scale; therefore,
manual repair was applied for photomask repairing. Eyebrow pencil was adopted to
dip etchant to remove local opaque chromium defects. For defects close to the
functional pattern, photoresist was applied with eyebrow pencil to cover the func-
tional pattern neighboring to defects, and then the defects were removed by local
etching. In addition, photomask repair microscope with ultraviolet light source and
adjustable shaped aperture was adopted to assist the defect repairing for complicated
defects on photomask. The removal methods for defects covered W/O photoresist
are different. That is, defect of islands, burrs, and line bridges of patterned photore-
sist found after the lithography step of photomask-making could be removed by
means of aligning the adjustable shaped aperture to defects, and then performing the
local exposure and development as well as a sequential local etching to remove these
opaque defects. Furthermore, after the photoresist stripping, opaque chromium
defects of photomask could also be removed by applying photoresist coating,
exposing, developing, and etching for these local defect areas with the assistance
of photomask repair microscope. Large clear areas of defect on photomask could be
repaired by coating red water-soluble glue to block these clear areas. Moreover, it
becomes necessary to refabricate a new photomask for replacing the precision
photomask of many fatal defects due to the repairing cost.
As the feature size of IC is shrunk from micron to submicron, deep submicron, and
even nanometer scale, automatic defect inspection and repair system is required to
perform the precision photomask repairing. A high-energy pulse laser is then applied
to evaporate the residual chromium defects such as islands, burrs, and line bridges. On
the other hand, for defects of pin holes, pits, and broken lines, high-energy thermal
radiation beam is applied to heat up the local clear area for the selective metal
deposition. Currently, focusing laser beam system and focusing ion beam (FIB) system
are adopted to repair opaque type defects and clear type defects, respectively.
In addition, Laser Photomask Repair System is able to repair both opaque type
and clear type defects. Using a high-power laser beam to evaporate the residual
chromium metal, opaque defects can be completely removed. Meanwhile, a laser of
a certain wavelength is applied to have a specific metal organic compound to
generate the metal deposition to fill clear areas. Then the clear type defects are
repaired through the so-called photochemical vapor deposition.
Focused Ion Beam (FIB) mask repair system relies on the positioning sputtering
method to remove opaque chromium defects and also performs the local ion milling
method to abrade the clear area to become opaque for repairing the clear type
defects. Currently, FIB mask repair system made by FEI Company can perform
1300 B. Chen et al.

the opaque-clear repair function for residual opaque chromium removal by position-
ing sputtering and implement the deposition repair function to block clear type
defects, and also can abrade the clear type defects to opaque with the focused ion
beam milling method. In addition, pattern defects on phase shift mask can be
repaired by selectively etching quartz plate with the positioning focused ion beam.
Therefore, FIB system of FEI can perform photomask repairing for both phase shift
masks (PSMs) and binary intensity masks (BIMs). Figure 64.5 shows an FEI
focused ion beam photomask repair system which can repair defects of phase shift
mask. Figure 64.6 shows a schematic of LCVD laser photomask repair system for
large area photomasks.

Fig. 64.5 Focused ion beam photomask repair system made by FEI Company. (Courtesy of
Zhongwei Photomask-making Co.)

Fig. 64.6 Schematic of LCVD laser photomask repair system for large photomasks. (Courtesy of
Qingyi Photomask-making Co.)
64 Mask Manufacturing Equipment 1301

Optical Pattern Generator

Optical Pattern Generator is an exposure system to make reticles with computer-

aided manufacturing. It can generate the designed pattern on the photoresist layer of
the photomask plate by exposure step to achieve the reticle fabrication for photo
repeater or projection exposure system. The pattern size of the reticle for the photo
repeater is ten times that of IC products, while the pattern size of the reticle for the
projection exposure system is four or five times that of IC products.
The optical pattern generator is equipped with a variable mechanical slit aperture
(or a fixed rectangular aperture) and a lens imaging system with a certain reduction
factor (usually 1∶25). Using a computer to coordinate the operation of the flashlight
(or mercury lamp with the shutter) and the movement of the work stage, the IC data
can be sequentially exposed on the photosensitive plate, thus splice a complete
reticle of integrated circuit. The pattern generator adopted in the photolithography
process refers to the photomask exposure equipment, such as optical pattern gener-
ator, laser pattern generator, and electron beam pattern generator, which forms the
photomask patterns on the photosensitive material through various exposure
methods.
Electron beam pattern generator is a circuit module that outputs waveform data
under the computer control and realizes the function of scanning imaging by
controlling the electromagnetic deflection system. Generally, electron beam pattern
generator and micromobile platform are equipped in the electron microscope. To
control the electron beam deflection coil of the electron microscope and the micro-
mobile platform cooperate with each other, then experimental patterns can be drawn
on the photosensitive materials. Due to the lack of precise scanning coordinate
calibration system, precise positioning system, and scanning field distortion correc-
tion system, furthermore, the drift of electron beam is too large, therefore, the
electron beam pattern generator is not suitable for the exposure to the precise layout
of large area.
The optical pattern generator consists of the computer control system, data input
system, dual-frequency laser precise positioning servo system, air floating anti-
vibration isolator, precision stage, automatic focusing system, 25 times optical
reduction lens, mercury lamp and flashing lighting system (exposure light source),
adjustable rectangular rotation aperture system, shutter system, constant temperature
and clean air conditioning cabinet, etc. The specification of parameters is as follows;
the minimum feature size (resolution) produced by the optical pattern generator is
2 μm, the maximum mask size is 7 in., the maximum moving ranges of stage in X and
Y directions are 150 mm, respectively, and the positioning accuracy is
0.25 μm.

Photo-Repeater

Step-and-Repeat system, also called as the Step-and-Repeat Camera or Photo-

Repeater, commonly is known as the optical precision shrinking system for
photomask-making. Its function is to generate repeated specified patterns on the
1302 B. Chen et al.

photomask plate. This Step-and-Repeat system is a photomask exposure system

composed of a high-resolution optical zoom imaging system and a precision posi-
tioning working platform. It reduces the pattern of reticle prepared by the optical
pattern generator to the actual chip size in an appropriate proportion (usually 1∶10),
and exposes the pattern on photoresist-coated emulsion photoplate or chrome pho-
tomask plate by a step-and-repeat method or a different pattern distribution method,
so as to fabricate the photomask plate with pattern array for the contact/proximity
aligners. Step-and-Repeat system consists of computer-controlled system, dual-
frequency laser precision positioning servo system, air floating antivibration system,
precise reticle alignment system, precision working platform, automatic focusing
system, 10X reduction optical lens, mercury lamp lighting system, the shutter
system, and clean air conditioning system with constant temperature, its minimum
exposure feature size (as the resolution) is 1.25 μm, the maximum size for photo-
mask plate is 7 in. The maximum stage movement range is 150 mm in X and Y
directions, respectively, and the positioning accuracy is
0.25 μm.
Step-and-Repeat system has higher accuracy of pattern stitching than the optical
pattern generator, and can perform the function to repeat the pattern splicing by step-
and-repeat method. It can adopt a variety of pattern elements from the “pattern
vocabulary data base” to efficiently stitch large periodic patterns of high precision
(e.g., repeated chip patterns on photomask plate or reticle plate), also can adopt
different pattern elements to stitch all kinds of large complex patterns of high
precision.
The key techniques are described as follows:

1. Precision adjustment technology of equipment: The reduction ratio, pattern

distortion, and alignment accuracy are strictly adjusted, and the error within the
range of 100 mm is less than 100 nm.
2. “Pattern vocabulary” data base preparation technology: It can apply its own high-
precision shrinking splice function to prepare the high-precision “pattern vocab-
ulary data base.” In order to realize the diversity of pattern splicing, various
templates of “pattern vocabulary” can be prepared according to the commonly
adopted photomask patterns, such as various pattern elements and pattern groups
including square, rectangle, triangle, diamond, circle, cross, resolution reference
patterns, and alignment marks. Each “pattern vocabulary data base” contains
pattern elements at the micron, 10 μ, 100 μ, and millimeter scales, as well as
the “pattern vocabulary” template of alignment marks for angle variation.
3. Pattern position correction technology: According to the partition of visual field
method, the independent “pattern vocabulary” of the “pattern vocabulary” tem-
plate could be distributed in different positions of the reticle with certain rules.
Depending on the pattern size, there could be only one complete “pattern
vocabulary” on the article, or also four, nine, or 25 “pattern vocabularies” on
the same reticle. In addition, the correction value of the image on the working
platform can be determined according to its center deviation value with the reticle
(note that the relationship of coordinate system between the reticle and the
64 Mask Manufacturing Equipment 1303

Fig. 64.7 High-precision photomask fabricated with a step-and-repeat system. (Courtesy of

Institute of Microelectronics of Chinese Academy of Sciences)

working platform should be noticed). Figure 64.7 shows a high-precision photo-

mask fabricated with a step-and-repeat system.

Projection Stepper, also known as the Direct Stepper on the Wafer (DSW), is an
equipment to transfer designed patterns from reticle to wafer through the exposure
step. DSW has a basic function similar to that of a step-and-repeat system, that is, the
automatic photomask alignment system, servo controlled working platform system,
dual-frequency laser interferometer precision positioning system, and optical pro-
jection imaging system cooperate with each other to reduce the pattern size of the
reticle, and then form shrank images onto the whole photoresist-coated wafer surface
by step-and-repeat method. Because the DSW has equipped an automatic photomask
alignment system, it can achieve the precise interlayer lithography with aligned
marks. The projection stepper adopts a 5X projection lens for G-line (435 nm) or
I-line (365 nm) wavelength, while the step and scan projection system (also called as
scanner) adopts a 4X projection lens for excimer lasers (248 and 193 nm). The
current mainstream projection stepper is the 193 nm immersion (193i) lithography
system (as 193i scanner).

Laser Direct Writing System

Laser direct writing system, also known as Laser Pattern Generator (LPG), is a
photomask manufacturing equipment that directly scans and exposes photomask
patterns on photoresist by laser beam, as shown in Fig. 64.8. In the traditional laser
direct write system, the scanning mode of light modulation is controlled by the
computer, and the laser beam is projected onto the photoresist layer on the surface of
the photomask plate for direct write exposure, so as to transfer the designed layout
1304 B. Chen et al.

Fig. 64.8 Direct laser writer (courtesy of Heidelberg Instruments GmbH)

pattern to the photomask plate. The laser direct writing system can replace the optical
pattern generator to fabricate the photomask directly on the uniform chrome plate,
and it also performs the function of direct writing pattern on the photoresist-coated
wafer. In addition, it also performs the direct writing function for aligned multi-
pattern layers and the automatic inspection for the accuracy of exposed patterns.
Basic components of laser direct writing system include laser light source system
(He-Cd laser), laser modulation system (laser beam focusing device, beam
expanding device, beam splitter, acousto-optic modulator, and multimirror rolling
scanner), zoom lens and the projection reduction lens system, working platform
control system with precision positioning by He-Ne dual-frequency laser interfer-
ometer, automatically controlled focusing and inspection system, computer control
system, the constant temperature maintaining and compensation system, etc.
Figure 64.9 shows the optical path diagram of the laser direct writing system.
With the rapid development of laser direct writing technology, a variety of laser
imaging systems have emerged.

1. Classified from the structure of the working platform: There are Cartesian
coordinate exposure, polar coordinate exposure, and a combination of both two
coordinate exposures. The traditional laser direct writing system adopts the
Cartesian coordinate mode. Usually, the modulated laser beam is adopted to
conduct the field scan exposure in the transverse direction, and the guide rail of
working platform is applied to conduct the raster scan in the longitudinal direction
with a uniform movement. After the exposure of a scan field is completed, the
system controls the guide rail to move to the next field spacing in the transverse
direction, and then continues to carry out the raster scan in the longitudinal
direction until all patterns across the entire photomask plate have been exposed.
The key technology is to control the positioning accuracy of guide rail to ensure
64 Mask Manufacturing Equipment 1305

Fig. 64.9 Optical path diagram of a direct laser writing system. (Courtesy of Heifei Chip
Foundation Microelectronics Equipment Co. Ltd)

the field splicing accuracy of the exposure patterns. The polar coordinate method
is mainly adopted to expose the photomask pattern of microoptics components,
such as the pattern with a symmetrical center, e.g., wave band plates. The above
one-dimensional linear mobile platform of the laser beam will make the focused
laser beam deviate from the rotation center, so as to control the radius of the
exposed ring. The lower working platform is a precise rotary platform adopting
the air floating rotation shaft device to ensure the stage plane rotating at a constant
speed to achieve the circular scanning exposure. The key technology is to ensure
the accuracy of the center position between the one-dimensional linear mobile
platform of the upper laser beam and the lower rotary platform of photomask
plate.
2. The number of laser beams can be divided into single and multiple beams. The
traditional laser direct writing system is single beam-scanning exposure mode. In
order to improve the exposure efficiency, multibeam laser direct write mode or
multilens exposure mode is usually adopted.
3. The category of exposure mechanism: Because the laser has a good monochromatic
property to fully meet the coherent conditions, so the adoption of laser as the light
source can develop a variety of laser imaging technologies, for mainly example;
focused laser beam scanning exposure technology and DMD-based maskless
digital lithography technology. In addition, there are Laser Interference
Lithography Technology, double-beam photomask pattern modulation interference
1306 B. Chen et al.

imaging technology, Nano 3D Printing Technology with Laser, Femto-Second

Laser Two-Photon Fluorescence Imaging (FLTFI), etc.

The laser direct writing system can be applied to fabricate the large size photo-
mask of flat panel display for the manufacturing of Thin Film Transistor Liquid
Crystal Display (TFT-LCD). This laser direct write system is a special equipment
developed on the traditional laser direct write system. At present, the largest photo-
mask size of flat panel display has reached 2850 mm  3050 mm, so this equipment
requires adopting the high-speed scanning exposure method with multiple laser
heads to improve the photomask manufacturing efficiency.

DMD-Based Laser Photomask Direct Writing System

Digital Micromirror Device (DMD) based on Laser Mask Direct Writing technology
is one of the Optical Maskless Lithography (O-ML2) techniques, which is also called
digital writing for photolithography. It is mainly used for photomask-making and
wafer direct writing. In DMD maskless digital lithography, DMD chip is used as the
digital mask to replace the reticle of traditional projection lithography. Laser light
reflected from the 10 μm micromirror of the DMD is demagnified by the condenser
lens to form a submicron light spot (i.e., pixel) which is then directly projected onto
the substrate. There are nearly a million micromirrors fabricated with MEMS process
in one DMD. For each micromirror, there is a corresponding CMOS static random-
access memory for addressing the micromirror, and also driving the micromirror to
tilt the deflective direction of light element so as to switch the on/off of the light and
adjust the grayscale of exposure. The diagram in Fig. 64.10 shows the exposure
mechanism of DMD. Figure 64.11 shows the structure of a micromirror unit in DMD
fabricated by MEMS process.

Fig. 64.10 A diagram of DMD exposure

64 Mask Manufacturing Equipment 1307

Fig. 64.11 Schematic diagram of optics of direct laser writer based on DMD (courtesy of Heifei
Chip Foundation Microelectronics Equipment Co. Ltd)

There are five methods of pattern exposure on substrate by the DMD lithography.

1. Exposure by joining all DMD demagnified images together to form a complete

pattern
2. Exposure by joining together each image reflected from individual micromirror in
DMD array to form a complex pattern
3. Exposure with step and repeat method to form a complete pattern
4. Exposure with the combination of step and scan method to form a complete
pattern
5. Exposure with the scanning of a focused and trimmed light spot to form a
complete pattern

There are two forms for data input.

1. Laser Direct Writing System by the individual pixel scanning method: Each pixel
of micromirror array implements the photoresist exposure to form image by its
reflecting light from the corresponding micromirror. The images from the
1308 B. Chen et al.

micromirror array are stitched together to form required patterns. The beam step
size (BSS) of scanning for the pixel of micromirror array is controlled by the
computer. To adjust the stitching boundary and control the stitching tolerance of
the overlap between pixels, patterns with smooth corners and line edges can be
obtained.
2. Laser Direct Writing system by the pixel line scanning method: According to the
input of CAD pattern data, micromirror array is modulated by a Spatial Light
Modulator (SLM) to implement the fast and dense programmable phase modu-
lation to form a multipixel pattern in one shot exposure along the scanning
direction. In addition, the grayscale pattern exposure determined by the light
density can be achieved by controlling the pixel number of each line. Fast
scanning exposure is the advantage of such laser writing system; however, the
involved processing data are very huge. The configuration of DMD laser direct
writing system is classified as DMD maskless lithography system, DMD step and
repeat projection lithography system, DMD step and scan lithography system,
and DMD digital photomask lithography system.

In addition to Laser Direct Writing and DMD-based Laser Direct Writing for
photomask-making, there is also Maskless Laser Interferometric Lithography tech-
nology for the fabrication of high-resolution optical grating photomasks. It applies
the diffraction and interference of laser, and holographic imaging theory to realize
Maskless lithography or holographic lithography. Figure 64.12 shows the schematic
diagram for the optics of Maskless Laser Interferometric Lithography. Due to the
monochromaticity and coherence of laser, two laser beams can be focused on the
photoresist surface to form the interference image. As a result, interference pattern of
fringes with alternately bright and dark features are formed in the given unit area by
modulating the light density of laser in interference field. Therefore, large area
pattern of high-resolution optical grating can be formed by joining these interference
pattern units together with the step and repeat method. In addition, one laser beam
can also be split into two coherent beams to generate interference images on
substrate for making a large area pattern of diffraction optical gratings. Furthermore,
two split coherent laser beams can also be modulated with photomask pattern to
generate interference images for a variety of complex feature arrays [7, 8].
Figure 64.13 shows the diagram of interference images formed with two laser
beams and four laser beams, respectively.

Electron Beam System for Photomask-Making

Electron Beam Exposure System is also called Electron Beam Pattern Generator, in
which the electron beam (e-beam) is projected directly onto the photoresist-coated
quartz plate to reveal the desired photomask patterns. There are three kinds of
Electron Beam Systems: the first one is the Gaussian beam (spot beam) type, e.g.,
JBX9500 and EBPG5200, for applications such as direct writing nanometer scaled
64 Mask Manufacturing Equipment 1309

Fig. 64.12 Schematic diagram for the optics of maskless laser interferometric lithography (cour-
tesy of SVG Optronics Co., Ltd)

Fig. 64.13 Schematic diagram of interference images formed with two laser beams and four laser
beams

chips or photomasks; the second one is the type of variable-shaped rectangular

beam, e.g., JBX6AII, JBX3200, and SB350 series, for photomask-making; and the
third type is raster scan with Gaussian beam, e.g., MEBES4700, also for photomask-
making [9].
Variable pattern sizes of electron beam can be formed by shaping apertures of the
Variable-Shaped Electron Beam system to rectangles, triangles, slanted patterns, etc.
1310 B. Chen et al.

The shape and size of the electron beam is varied by the electrostatic deflector in the
electron-optical column. The uniform e-beam is projected on the first rectangular
aperture to generate a large rectangular projection image which then is projected
onto the second shaped aperture to form the shaped electron beam (see Fig. 64.17).
The desired shape and size of electron beam are formed by the overlap of the
projection image of the first aperture to the window of the second aperture. The
maximum shape size depends on the electron-optical column configuration. During
the exposure step, electron beam system defines the shape size of electron beam
according to the optimized unit pattern size partitioned from the designed IC layout.
That is, the big rectangular beam sizes are applied for larger patterns while the small
beam sizes are applied for small patterns. Hence the throughput of e-beam exposure
is increased. Therefore, this kind exposure system is also called Variable Rectangular
Electron Beam Exposure System. The projection image of the first aperture can also
be rotated and projected onto the window of the second aperture to form triangular,
trapezoidal, or other shaped beam patterns [10].
The Shaped Electron Beam Exposure System is also called Fixed Shape Electron
Beam Exposure System. As mentioned above, the electron beam is formed to a fixed
rectangular shape with sizes by shaping apertures. The optimized size of the rectan-
gular beam is adjustable according to the required feature sizes for the exposed
patterns. Data preparation for such fixed beam shape exposure is relatively simple. In
addition to the fixed shapes, to replace the second aperture by a stencil mask with
more characters to shape the electron beam can form various projection images on
the photoresist-coated photomask plate, in which a desired layout pattern is obtained
by controlling the stitching tolerance of all required projection images. That is the
Cell Projection Electron Beam Exposure, which can perform nanometer resolution
and high throughput (see Fig. 64.17).
Raster Scan Electron Beam Exposure is a high-throughput e-beam direct writing
technology, in which the electron beam is scanned over all the area of the photomask
and to implement the exposure by selectively blanking and unblanking the electron
beam to obtain the desired patterns. This two-dimensional scanning exposure step is
determined by the zigzag movement of stage along the X direction and the electron
beam scanning along the Y direction. To control the beam spot diameter and the
beam step size (BSS) for the reduction of field stitch errors can achieve a continuous
pattern. Raster Scan systems can perform the scan at far faster rates, but are less
accurate in beam placement, especially in the case of alignment to existing layers. In
addition, another writing strategy called Vector Scan is also applied for photomask-
making, in which the electron beam is scanned only in the areas to be exposed, and
then jumps from each exposed pattern to the next pattern. In general, for sparse
patterns with little exposed areas, vector scan systems can perform a faster scanning
than a raster scan system for the photomask-making process. Furthermore, multi-
electron beam exposure (MEBE) system is also classified as the Raster Scan Electron
Beam Exposure System in electron beam lithography series, which is made by
ETEC Company of USA. Its higher throughput makes it suitable for photomask-
making [11].
64 Mask Manufacturing Equipment 1311

Figure 64.14 shows the image of JBX 3200MV-Shaped Electron Beam Lithog-
raphy system for photomask-making. Figure 64.15 shows the image of the high-
resolution photomask fabricated by the Shaped Electron Beam Lithography
system.

Fig. 64.14 JBX 3200MV-shaped electron beam lithography system for photomask-making (cour-
tesy of JEOL)

Fig. 64.15 The high-resolution photomask fabricated by the shaped electron beam lithography
system. (Courtesy of Institute of Microelectronics of Chinese Academy of Sciences)
1312 B. Chen et al.

Electron Beam Projection Lithography System for Photomask-

Making (EBPLS for Photomask-Making)

Electron Beam Projection Lithography (EBPL) equipment is a high-speed Electron

Beam Exposure System which is evolved from the Variable-Shaped Electron Beam
system. As mentioned, the projection exposure is implemented onto the photoresist-
coated photomask plate to form latent patterns by using a stencil mask (or called
shadow mask), which performs as the second aperture in e-beam equipment. To
apply stencils with nanometer size windows as apertures, this EBPL can demonstrate
the exposure with nanometer scale resolution and high throughput by a precise
demagnification technology of electron optics, therefore, it has been applied in the
fabrication of nanometer scale chips and advanced photomask-making.
Stencil mask is made of a metal-coated silicon wafer which performs as a rigid frame
to support the whole structure. As shown in Fig. 64.17, patterned windows on the stencil
mask are fabricated with a series of processes such as metal film deposition, lithography
patterning, deep dry etching, etc. Usually, according to the layout requirement of
designed ICs, there are a variety of patterned window elements or units on the stencil
mask. The size and the distribution of windows in the Stencil mask are determined by
the optimization of algorithm for the precise pattern transfer and the higher throughput.
The electron beam permeated the selective window of the stencil mask by the electron
beam deflector is shaped as rectangular, triangular, or polygonal beam, and which then is
demagnified and projected onto the photoresist-coated wafer or photomask plate to form
desired unit pattern. By write and fly method, various unit patterns are stitched together
to form the final latent pattern on the photoresist of photomask plate or the wafer. That is
the pattern formation by projection electron beam lithography technology.
With the concept of beam projection, Electron Beam Cell Projection Lithography
(EBCPL) System is developed. It is an electron beam exposure system of high
accuracy and high throughput, in which EBCPL uses character elements as cells to
stitch complex patterns. The stencil mask performs as the second aperture which
accommodates a variety of character elements (about 100 different elements of
various characters). The number of characters are limited due to the area constraints
of the stencil mask. By allowing over-lapping adjacent characters, more characters
may be put on the stencil mask. This cell projection technology can print some
complex shapes in one electron beam shot, rather than writing multiple rectangles.
A uniform rectangular electron beam shaped by the first aperture is projected onto
a selective character (called as cell) of the stencil mask by the deflector, so as to
generate a demagnified character image on the photoresist-coated photomask or
wafer. This character image can be demagnified with certain ratio by the electro-
magnetic lens to nanometer scale. Common adopted character shapes on the stencil
mask are square, rectangle, triangle, diamond, circle, cross, alignment marks, etc.
The layout of designed IC can be stitched with these selective characters together by
a computer-controlled system. The optimized character selection and image stitching
for patterned layouts can be achieved by the effective algorithm. Currently, EBCPL
has been adopted in the fabrication of nanometer scale ICs. In addition, some large
area pattern can also be formed by repeatedly stitching same feature element.
64 Mask Manufacturing Equipment 1313

Figure 64.16 shows the image of Electron Beam Cell Projection Lithography
System. Figure 64.17 shows the schematic diagram of the operation by Electron
Beam Cell Projection Lithography System.

Fig. 64.16 Electron beam cell projection lithography system. (Courtesy of Advantest)

Fig. 64.17 Schematic diagram of the operation by electron beam cell projection lithography
system. (Courtesy of Advantest)
1314 B. Chen et al.

Resist Processing and Cleaning Equipment for Photomask-

Making

In the fabrication of photomask, a variety of photoresist preparation and clean

systems are adopted to perform surface cleaning, dehydration bake, HMDS adhesive
layer coating, photoresist coating, soft bake, postexposure bake, developing, hard
bake, etching, and drying processes. Stand-alone system is applied to implement
individual process as mentioned above. Also, to integrate all photomask-making-
related process units together can assemble an automatic track system for mass
production line, such as the Automatic Photomask Cleaning Equipment. The men-
tioned photoresist as a photosensitized material can form desired patterns on photo-
mask in lithography step, and also performs as an etch-resistant layer during the
etching process.
Mask Developer is applied for developing the latent image pattern in the photo-
resist after the exposure step. The computer-controlled Photoresist Track Developing
System can implement processes of development, image fixing, plate clean, hard
bake, and photoresist stripping in sequence for postexposed photomask. In addition,
Ultrasonic Photoresist Developing System makes use of the ultrasonic oscillation
generated force to bubble and emulsify the developer to enhance the developing
process.
Photomask Cleaning Equipment, also known as Mask Scrubbers, are systems that
clean the contamination and particles off the photomask. The technology of IC is
continuously developing, then the photomask size for IC as well as TFT flat panel
display becomes larger and the specification of cleanliness for photomask is getting
stricter. Traditional types of manual cleaning and cleaning in tank can no longer meet
the clean level requirements for photomask. However, cleaning processes play an
increasingly important role in yield improvement. Then, automatic spinning with
high-pressure spray mask scrubber is developed to meet the postcleaning require-
ment for the production of larger size photomask plate and related processes, such as
metal film deposition and photoresist coating. Automatic Photomask Cleaning
Equipment is equipped together with multisize mask holders, front side high-
pressure multiple spray nozzles (for DI water, detergent, organic solvent, and hot
DI water), back side high-pressure spray nozzle for DI water, spin dryer, infrared
dryer, and physical scrubbing unit. Therefore, double-side cleaning for photomask
plate can be automatically implemented in one process step.
In addition, there are some customized cleaning equipment, e.g., Chemical
Cleaner, Ultrasonic Cleaner, and Megasonic Cleaner. That is, chemical contamina-
tion on the substrate surface is cleaned with immersion or spray method in the
chemical cleaner. According to the characteristics of contaminants, Sulfuric Acid
and Hydrogen Peroxide Mixer (SPM), Ammonium Hydroxide and Hydrogen Per-
oxide Mixer (APM), or Hydrochloric Acid and Hydrogen Peroxide Mixer (HPM)
are selected as the clean solution.
Ultrasonic Cleaner is a system which generates the oscillation of ultrasonic
acoustic wave in solution to remove the contamination and particles from the
photomask surface. This kind ultrasonic acoustic wave may form a standing wave
64 Mask Manufacturing Equipment 1315

Fig. 64.18 The large area photomask (1300 mmx1500 mmx13 mm) fabrication system including
developing, etching, and cleaning units (Courtesy of Qingyi Company)

on the plate surface, in which some tiny residues of 0.25 μm or less are still
accumulated at the nodes of standing wave. Therefore, Ultrasonic Cleaners are
only applied for larger particle removal. In order to remove tiny and nanometer
scale particulates further, Megasonic cleaning technology is developed. Megasonic
Cleaner adopts the acoustic wave transmitter to generate a traveling acoustic wave
oscillation of 3 MHz (> 0.85 MHz) in the chemical solution. It can produce a
powerful flowing solution so as to efficiently remove the contamination and particles
from photomask surface. The tool can be operated independently or integrated in
track with other mask fabrication units. Figure 64.18 shows a large area photomask
(1300 mm  1500 mm  13 mm) fabrication system including developing, etching,
and cleaning units.
After the DI water rinse step, the residual water and moisture on plate surface has
to be dried off. In laboratory, photomask is usually dried with nitrogen purge, natural
evaporation on the cleanroom bench, or spin dryer. In production line, photomask
needs to be dried off with automatic drying equipment, e.g., spin dryer in the track
after cleaning, centrifugal roller, spin dryer with pure nitrogen sprayer, isopropyl
alcohol vapor evaporator, spin dryer with isopropyl alcohol sprayer, or isopropyl
alcohol displacing deionized water.

Photoresist Coater for Photomask-Making

Photoresist Coater involves the spin coating of a thin photoresist (P/R) film evenly
across the surface of a photomask plate by the centrifugal force which combines with
the surface tension of the photoresist to spread the liquid photoresist coating into a
uniform covering on the plate. The coating process is as follows; (1) The right
amount of liquid photoresist is dispensed onto the center of the photomask plate,
(2) The first low-speed spin cycle quickly spreads the photoresist without throwing it
off the photomask, (3) The second high-speed spin cycle stretches the resist film into
a highly uniform thin film at the desired thickness which determined by a spin-speed
curve of photoresist.
1316 B. Chen et al.

Generally, the configuration of a Photoresist Coater for photomask-making

includes:

1. Spindle with the function of controllable speed: This spindle can precisely control
the spin rate and the spin rate ramp to get a uniform photoresist coating with a
required thickness. For the dynamic dispense, the rotation rate of spindle is about
500–600 rpm to assure a full photoresist covering on the plate, then the quartz
plate is spun rapidly at a spin rate of 4000 rpm to distribute the photoresist
uniformly across the entire photomask plate so as to obtain the desired thickness
of photoresist. In order to maintain a uniform temperature distribution on the
photomask plate, the spindle is either water or nitrogen cooled.
2. Dispenser: According to the size of plate, it controls a certain amount of photo-
resist to be dispensed onto the photomask plate. This unit is also designed with a
suck back feature to prevent unwanted photoresist droplets from depositing on the
plate surface after the dispensing step. For a 5-in. square photomask plate, the
amount of photoresist is about 2 ml.
3. Vacuum chuck: Using vacuum pumps to hold the photomask plate during the
photoresist dispensing and spin coating. However, a smart design of vacuum-free
chunk is also available for some flexible plates. Photomask plates are held in
place by recesses cut into a polypropylene chuck which allows excess photoresist
to be drained away.
4. Rotating lid and drain container: The rotating lid which covers the vacuum chuck
can keep a solvent saturated atmosphere above the plate surface and prevent the
air turbulence-induced nonuniformity during the spin coating. The spun-off
photoresist and solvent are collected in the drain container to reduce the contam-
ination in coater housing.

There are two kinds of photoresist coater for photomask-making, one is compact
spin-coating type, and the other type is the track of photoresist coating and devel-
oping system which can automatically implement the photoresist coating and the
developing process for photomask plate in one system. There are many compact
coater vendors, such as Ossila Ltd. in UK, and Mikasa Co. in Japan.

Photoresist Stripper

Photoresist is used only as a temporary mask for pattern transfer in IC fabrication and
photomask-making processes. Related with the photolithography process, a com-
plete photoresist removal after etching or ion implantation step is a critical process to
assure the yield of subsequent processes in the device fabrication. Therefore, pho-
toresist stripping technology plays an important role in semiconductor device fabri-
cation. There are two methods to remove photoresist layer: wet or dry process. Wet
methods mainly use alkaline solutions (e.g., 2–3% KOH or NaOH) to strip the
positive photoresist while organic solutions (e.g., dimethyl sulfoxide, DMSO) for
the negative photoresist stripping. Acetone is generally not recommended for the
64 Mask Manufacturing Equipment 1317

removal of negative photoresist films because of its high vapor pressure and the high
risk of fire. After the wet stripping step, an oxygen plasma treatment is usually
applied to further clean the photoresist residues. Dry methods apply the plasma of
oxidants, such as O2, H2O, etc., to remove photoresist in which chemically active
radicals oxidize the photoresist to form volatile by-products which are then pumped
out immediately. Oxygen plasma is the most common applied stripper in which
some oxygen molecules are either dissociated to radicals or ionized to ions by the RF
(Radio Frequency) or microwave power source [12]. Thus, chemically active oxy-
gen radicals react with C and H of photoresist polymer to form gaseous CO and CO2,
as well as H2O that are swept away from the chamber. Furthermore, to add a certain
amount of H2O vapor can enhance the oxidation reaction so as to increase the
stripping efficiency of photoresist due to an extra oxidation agent OH from the
water vapor. In addition, for aluminum metal etching, an added H2 can form
hydrogen radicals to extract chlorine on the sidewall and in the photoresist.
Figure 64.19 shows a compact microwave plasma stripper produced by Alpha
Plasma Co. Advantages of microwave plasma stripper include simple operation,
high efficiency, damage-free, low cost, and environment friendly. This microwave
plasma stripper can efficiently remove SU-8 photoresist or stubborn tone reversed
photoresist with the proper mixture of oxygen and argon. Furthermore, to add an
extra fluorine-based gases such as CF4 and C2F6 [13] in O2 plasma can enhance the
stripping ability. For example, SU-8 photoresist can be quickly removed in oxygen-
fluorine-based plasma by the microwave plasma stripper. Moreover, in atmospheric
pressure condition, to apply an RF glow discharging or a strong ultraviolet light
exposure to decompose the photoresist and other organic contaminants are also
classified as dry methods for stripping photoresist or cleaning the photomask plate
surface.
Supercritical CO2 is a newly developed technology which provides excellent
performance as a cleaning solvent in the photoresist stripping and the wafer cleaning
processes due to its unique properties such as low viscosity, high diffusivity, high

Fig. 64.19 A microwave

plasma strippers. (Courtesy of
Alpha Plasma Company)
1318 B. Chen et al.

permeability, and less surface tension. Carbon dioxide at pressures above 1050
pounds per square inch and temperatures above 31  C becomes supercritical. It is
known as supercritical carbon dioxide (SCCO2) which has no liquid-gas phase
boundary and no surface tension occurs, therefore, this fluid acting as a solvent
can penetrate into microstructures to dissolve the photoresist without damaging the
lithography pattern. However, SCCO2 alone is somewhat ineffective, thus it com-
bines with a certain amount of DI water or other chemical agents to enhance the
efficiency. With the appropriate pressure and temperature, the supercritical fluid
mixture will cause the solubility to change over 100 times and perform better
capability to remove the photoresist and residues. This technology has been applied
in the processes of 45 nm node and beyond [14, 15]. The SCCO2 stripper system is
composed of deionized water container, CO2 bottle, mixing chamber, thermal
exchanger for heating the mixed solution, and a novel elevated pressure reaction
chamber. Deionized water container and CO2 bottle are individually connected with
mixing chamber which is connected to the inlet of reaction chamber via the thermal
exchanger. The as-etched photomask is loaded in the reaction chamber while
supercritical CO2 and deionized water (or other stripping chemical agent) are
injected into the reaction chamber to form a supercritical fluid under the appropriate
high pressure and temperature. Thereafter, photoresist and its residue on photomask
plate can be completely removed by this supercritical fluid in the reaction chamber.
In addition, supercritical CO2 can also be mixed with organic and inorganic chemical
agent in the reaction chamber to form a mixed supercritical fluid so as to remove the
photoresist and its residue from the substrate surface. After the end of the photoresist
removal, CO2 can be separated from the dirt and return to its gas phase by depres-
surization or cooling.

Photomask Duplicator (Photomask Copier)

The photomask duplicator or photomask copier is an apparatus to duplicate the

master photomask for submaster photomask or working photomask (also called
working plate). In early years, ultra-fine grain photo plate was used as the photomask
plate for making the master photomask, however, and the pattern layer of this kind of
master photomask was easy to be scratched or damaged. Therefore, the photomask
duplication technique is applied to produce submaster photomask and then working
photomask for the lifetime extension of the master photomask. In addition, it used to
adopt the negative photoresist, thus the duplication steps for pattern transfer are as
follows; (1) First pattern transfer from the master photomask to the submaster
photomask, in which the pattern of submaster photomask is complementary to that
of the master photomask. (2) Second pattern transfer from the submaster photomask
to the working photomask, in which the pattern of working photomask is same as
that of the master photomask. Moreover, if the positive photoresist is applied, same
pattern on the working photomask is obtained with only one direct pattern transfer
from the master photomask.
64 Mask Manufacturing Equipment 1319

During the photomask duplication process, the quality of working photomask is

significantly affected by the optical diffraction effect, the development control, the
roughness of photomask surface, particle defects, etc., therefore, pattern degradation
such as corner rounding, unresolved dense lines, pattern bridging, spots, scratches,
Newton rings, worse resolution, etc. are often observed. These damaged working
photomasks lead to a low yield in device fabrication. Along with the development of
CAD/CAM technology, the quality and the efficiency of photomask-making have
been significantly improved, and the cost of photomask-making has also been
dramatically reduced. Currently, most working photomasks are directly produced
with optical pattern generator, laser pattern generator, or electron beam pattern
generator. The duplication technique of photomask is only adopted for low-end
photomask-making. Especially, for some low-end devices such as pn diodes and
Schottky diodes, contact/proximity printers (also called aligners) are still the main
exposure equipment which require the working photomask (working plate) to be
replaced every five to 25 operations. Thus, the conventional duplication technique
for photomask-making is more cost effective.
The operation of proximity/contact photomask copier is similar to that of the
aligner. The aligner implements the pattern transfer from the photomask to the wafer,
and the proximity/contact photomask copier performs a 1:1 ratio pattern transfer
from the master photomask to the working plate. The master photomask and the
photoresist-coated working plate are pressed together by adjusting the vacuum
pressure between them. In order to avoid the scratch on photoresist, the gap between
master photomask and the working plate is carefully adjusted. Usually, the gap for
contact mode is less than 2 um in the Fresnel diffraction region, and the gap of the
proximity mode in the Fraunhofer diffraction region is about 10–25 μm which is
adjusted by manual, semi-automatic, or automatic methods. During the exposure, the
UV light from the Xe-Hg lamp source is concentrated by an ellipsoidal reflecting
mirror and collimated with optics, and then projected to the fly’s eye-lens (called as
microlens array) and a condenser lens to form a uniform illumination. In addition,
the exposure dose is controlled by the exposure integrator.
Projection type copy is a noncontact technique for the photomask duplication. It
adopts a rectangular light source to scan the master photomask so as to duplicate a
working photomask of 1:1 ratio. The mode of noncontact projection can eliminate
the possible scratches and other damages on working plates and provide photomasks
of better quality. However, the efficiency of photomask duplication is slightly lower.

Photomask Wet Etching Equipment

Chromium is the most popular contrast medium for high-quality photomask-making

due to characteristics of excellent adhesion to glass, stable reflectivity in air, excel-
lent contrast, and high abrasion resistance. Wet etching technology used to be
adopted for the photomask-making of micron scale patterns in IC fabrication. The
exposed Cr metal layer is removed from the photomask by either immersing in an
etchant solution or spin spraying the etching solution that reacts with exposed Cr
1320 B. Chen et al.

metal to form soluble by-products, while Cr layer covered by photoresist is pre-

served. It is a quick, highly selective, and cost-effective process. However, it is
difficult to control feature sizes that are smaller than 1 um. In addition, the
in-diffusion of etchant and the out-diffusion of by-products in solution mainly
determine both etch rate and uniformity of the immersion etching process. A stable
temperature control with the agitation can suppress the loading effect in immersion
etching. Moreover, the spin spraying technique can continuously provide fresh
etchant solution to achieve a better etching performance. Currently, automatic spin
spraying equipment with in-line cleaning function for Cr etching is available for
photomask shops.
Usually, the etchants for chromium film are based on the mixed solution of ceric
ammonium nitrate ((NH4)2Ce(NO3)6) and perchloric acid (HClO4) with a proportion
of deionized water. Perchloric acid (HClO4) is a strong acid in aqueous solution and
serves as an oxidizing agent for the stabilization of the ceric ammonium nitrate
((NH4)2Ce(NO3)6). The chemical reaction formula for the chromium etching with
ceric ammonium nitrate and perchloric acid (TechniEtch Cr01) is [16]:

3 ðNH4 Þ2 CeðNO3 Þ6 þ Cr ¼ CrðNO3 Þ3 þ 3ðNH4 Þ2 CeðNO3 Þ5

where the cerium is reduced from the oxidation stage IV to III and the chromium is
oxidized to oxidation stage III forming as the chromium nitrate Cr(NO3)3 which is
very soluble in water and thus in the chromate etchants during the etching process.
The composition of chromium etchant (TechniEtch Cr01) with ceric ammonium
nitrate ((NH4)2Ce(NO3)6): Perchloric acid (HClO4): water ¼ 10.9%: 4.25%: 84.85%
can achieve an etching rate of about 60 nm/min at room temperature.
Wet etching is a highly selective and isotropic process; therefore, over-etching may
create a visible undercut at edges of as-etched patterns before the photoresist film
stripping. Due to the chromium undercut proceeds with the same speed of Cr film
etching, a 100 nm thick Cr film is associated to 100 nm undercut on both sides of the
etched feature. Hence, the designed opaque feature size should be expanded for positive
photoresist or shrunk for negative photoresist in dimension of a certain amount to
compensate the isotropic etching-induced pattern bias. That is, the wet etching-induced
undercut effect can be taken into account when designing the layout of photomask.
Wet etching was the main technology for early photomask-making; however, the
isotropic wet etching created undercuts and sloped sidewalls will consume about
40% of the critical dimension budget [17]. In addition, the critical dimension is
limited to 1 um on these wet etching process-produced photomasks. It means that the
capability of pattern transfer from these photomasks by a 1X stepper or a 4X scanner
is limited to 1 μm or 0.25 μm on the wafer surface, respectively. Nowadays dry
etching technology plays a major role in advanced photomask-making industry. It
provides a more precise pattern transfer with vertical sidewalls at pattern edges. In
the era of nanometers, e-beam lithography combines with advanced dry etching
technology and can provide nanoscaled photomasks for IC fabrication. For example,
The new Twinscan NXT:2000i DUV (Deep Ultra Violet) scanner can successfully
achieve the fabrication of IC chips using 5 nm and 7 nm nodes.
64 Mask Manufacturing Equipment 1321

Photomask Dry Etching Equipment

Traditional wet etch is still capable of successfully transferring a chrome pattern of

1um scale from the resist into the chrome film. However, additional complications in
the photomask-making process and lower product yields make the wet etch process
less attractive. In addition, the isotropic wet etching created undercuts and sloped
sidewalls will consume about 40% of the critical dimension budget [17]. Therefore,
to apply an etching technology to meet a precise pattern transfer for photomask-
making becomes very urgent. Especially in submicron or nanoscale era, the require-
ments of resolution and critical dimension control for photomask fabrication are
dramatically increasing. Therefore, dry etching process is adopted for advanced
photomask-making due to its anisotropy and the progress of technology. Dry etching
utilizes plasma instead of liquid etchants to remove the Cr film. It is more precise,
controllable, and repeatable compared to wet etching, but a higher cost of ownership
is required owing to the complex configuration in system.
Photomasks are generally Chrome-coated glass templates, with the patterned
photoresist as a masking layer, the pattern can be transferred to the underlying
Chromium/Chromium Oxide layers of the photomask using the dry etching process.
Chlorine, oxygen, and inert gases, e.g., He, Ar, and N2 combination, have been
applied as a standard recipe for chromium etching. In addition, Carbon tetrachloride
(CCl4), oxygen, and nitrogen gas-based process is also applied for chromium
etching. Low-oxygen partial pressure can achieve better etch uniformity. It is
found that the etching rate of Cr film is highly affected by the RF power source,
the composition of etching gases, oxygen partial pressure, and chamber pressure
[17]. The etching rate of Cr films can increase to its maximum value rapidly with
increasing oxygen partial pressure in some range. The adopted recipe needs to be
fine-tuned to achieve the desired results. Furthermore, Phase-Shift Mask (PSM)
technology is applied in advanced photolithography. The alternating phase shift
mask (AltPSM) uses trenches which are etched into the quartz substrate alternating
to nonetched areas. Also, there are areas which are covered with a chrome layer to
reduce the intensity of diffraction light in these regions. The trench etching is
performed by anisotropic dry etching with various recipes of fluorine-based plasmas,
such as CHF3 and Ar, Freon, O2 and Ar, SF6 and Ar, as well as CF4 and CHF3, etc.
The trench depth of AltPSM depends on the exposure wavelengths [18]. For
example, the trench depth is 248 nm for KrF laser and 193 nm for ArF laser,
respectively. In addition, to apply the Bosch etching recipe with the passivation
gas C4H8 and cooling gas He can achieve deep trench patterns on quartz plate.
There are many advantages of dry etching for the photomask fabrication, such as:

1. High resolution: The combination of the physical ion bombardment and the
radical chemical reaction can optimize the etching performance to achieve a
nanoscale pattern transfer.
2. Save the critical dimension budget: The anisotropic dry etching can perform
undercut-free patterns with nearly vertical sidewalls. Therefore, the etching-
induced dimension loss of masking layer is reduced.
1322 B. Chen et al.

3. Compatible with photoresist stripping: The dry etching for Cr metal masking
layer and photoresist layer stripping can be carried out in the same chamber or in a
cluster etching equipment.
4. Good uniformity control and repeatability: The dry etching of the photomask is a
single plate process; therefore, the feature control of etched patterns is much
better than that of wet etching.

In addition, Plasma etching can achieve the pattern reversal process for photo-
masks by adjusting the power level and other parameters during the dry etching step.
For example, the recipe for the conventional Cr metal etching includes CCl4 etching
gas mixed with Ar or air; the pressure of 30 Pa, and RF power of 160 W. As the RF
power is raised to 320 W, AZ photoresist on chromium layer will be decomposed to
react with process gas CCl4 to form a local high density of Cl radicals which
remarkably enhance the etching rate of photoresist and underlying Cr metal layer.
On the contrary, the exposed Cr metal still performs a lower etching rate. Therefore,
a reversal pattern on photomask is obtained.

Pellicle Mounting Instrument

Pellicle Mounting Instrument is a high-precision equipment adopted to attach

pellicles on the reticle or photomask to prevent the particle contamination from the
reticle or photomask surface. For decades, the industry has applied a pellicle on the
reticle or photomask. The pellicle technique for the photolithography is based on a
thin polymer film.
It is well known that the most threat to the reticle or photomask is the particle
contamination. In order to avoid airborne particles or other contaminants landing on
the transparent area of the reticle to form distorted images on the wafer, as well as to
degrade the device performance and reduce the product yield, to mount a pellicle to
the reticle or photomask becomes a standard practice to protect the reticle surface
from any particles. That is, the pellicle is a dust cover to prevent particles and
contaminates falling on the reticle or the photomask in the photolithography equip-
ment to increase the product yield. Pellicles are usually thin polymer films stretched
across an anodized aluminum frame which is attached to the reticle. The typical
height of aluminum frame is 6.35 mm, the same as the thickness of the reticle plate.
Therefore, the pellicle film is held a fixed gap from the reticle surface. It means that
particles fallen on the pellicle surface or the backside of the reticle are several
millimeters away from the chrome patterns which are being imaged. During the
exposure process, the image of these particles will be out of focus on the wafer plane,
and therefore lead to a blurred shadow on photoresist. These blurred images will not
affect the photoresist due to the divergent light distribution.
Material of pellicle for G-line (436 nm) and I-line (365 nm) is high-molecular-
weight Nitrocellulose polymers or Polyester films with a thickness about 0.72 to
1.2 μm. For 248 nm and 193 nm DUV lasers, 1 μm thick amorphous fluoropolymer
such as Teflon is the common material of pellicle. Thin pellicles produce negligible
64 Mask Manufacturing Equipment 1323

Fig. 64.20 MLI8000 pellicle mounting instrument. (Courtesy of Zhongwei Photomask Company)

spherical aberration. These materials must be transparent in the given exposure

wavelength, be low reflective to reduce the interference, be resistant to the radiation
damage, and be mechanically strong when cast as thin films. To optimize parameters
such as reflectivity, refractivity, transmittance, and thickness of thin film Pellicle,
good light transmission through the pellicle can be achieved [19]. Theoretical studies
show that the image intensities are affected by an amount less than 10% by the
pellicle [20]. Before the pellicle was adopted, a daily cleaning and inspection for
reticles or photomasks is required in IC Fab. Both the cleaning process-induced
reticle damages and also more contaminates from the environment will increase the
replacement cost of reticles and reduce the die yield. Now only a simple surface
inspection step for the mask and the pellicle membrane is required to assure the
quality of reticles and photomasks.
Pellicle assembling has to be implemented in an ultra-clean environment to
maintain the cleaning condition of instrument and pellicle materials (normally in a
class 1 clean chamber). Also, in order to reduce man-made contamination, the
pellicle is usually mounted by an automatic instrument with a special reticle holder.
A postmount inspection is required for the quality control. In Fig. 64.20, it shows
images of an MLI8000 Pellicle Mounting Instrument.

Photomask Pattern Data Processing System

In photomask-making process, Data Preparation System is applied to convert the

designed pattern data of GDSII (or other format) into the specific machine format
which could be the acceptable input for exposure equipment. During the data
preparation, pattern data are partitioned and converted according to the exposure
field required by the exposure machine. There are six common software applied to
Data Preparation System for photomask-making:

1. CAD/CAM software [21]: Both the layout design software for photomask of IC
and the data preparation software for photomask-making are called CAD/CAM
1324 B. Chen et al.

software, e.g., SPARC (Scalable Processor Architecture) series for SUN work-
station and IC-CAD of Synopsys EDA system which is a kind of traditional IC
design software. AutoCAD of generic drawing could not be used for the IC layout
design and pattern edit for photomask, as its output format DWG is not compat-
ible with IC process machine. Its output has to be converted to a binary DXF
pattern format for the exposure machine.
2. Layout Editor, L-EDIT [9, 21, 22]: L-EDIT pattern editor is a necessary module
for data editing in mask-making process. This design kit for drawing integrated
circuit layout is developed by Tanner Research Company. L-EDIT pattern editor
comprises of mask layout design and pattern editor modules. It is compatible to
PC operating system with a user-friendly interface.
3. Graphics Editing System Based on Java: It is a pattern editing module called
Stella Vision for Java which is programmed with Java language. It can revise and
correct errors of pattern drawing with AutoCAD, and is necessary to the pattern
editing for the mask-making process of flat panel displays.
4. Data Format Conversion [9, 21]: This software can convert the format of expo-
sure pattern data from one exposure machine into a specific format for another
exposure machine, also can convert CAD format pattern data into the format for
exposure machine. Its main applications are to implement the pattern data
partition for photolithography and electron beam lithography equipment. In
addition, this software is capable of pattern display and pattern inspection.
5. Mask Pattern Data Processing Software [9]: BEAMER is the typical software for
mask pattern data processing. It can implement Boolean operation, pattern data
processing and editing, as well as pattern converting and editing.
6. Editor to Generate Pattern Composed with Cell of Arbitrary Angle and Curve of
Functions [9, 21, 23]: Any complex patterns of polygon and curves generated by
functions can be drawn with this editor module. The editor module can also be
loaded into L-EDIT pattern editor for drawing special shaped patterns according
to various input functions. In addition, this editor module can process commonly
used patterns in batches and load all fonts from Word editor to L-EDIT pattern
editor.

References
1. B. Chen, et al., Development and outlook of microlithography and micro & nano fabrication
technology, National 15th Semiconductor IC and silicon material academic conference in
China, 2007
2. B. Chen, et al., Microlithography and micro & nano fabrication technology, National 13th
electron, ion and photon beam annual academic conference in , 2005
3. B. Chen, Microlithography and micro & nano fabrication technology. Micronanoelectron.
Technol. 48(1), 10–14 (2011)
4. J. Liu, Techniques and Theories of Super Resolving Phase Shift Confocal Scanning Microscopy
and Polychromatic Differential Confocal Scanning Microscopy (Harbin Institute of Technol-
ogy, Harbin, 2009)
5. S. Cheng, Research of Super-Resolution Laser Differential Confocal Pore Size Measurement
(Beijing Institute of Technology, Beijing, 2015)
64 Mask Manufacturing Equipment 1325

6. X. Mao, Research of Technology of Scanning Control Software for Laser Differential Confocal
Microscope (Beijing Institute of Technology, Beijing, 2015)
7. S. Ping, Research on Double-Exposure Technique to Improve Lithography Quality (Institute of
Optics and Electronics, Chinese Academy of Sciences, Chengdu, 2001)
8. X. Bing, G. Wei, L. Chen, Research advances in technology of laser direct writing.
Optoelectron. Technol. Inf. 17(6), 1–5 (2004)
9. B. Chen, Electron beam lithography technology and pattern data process technology. Micro-
nanoelectron. Technol. 48(6), 345–352 (2011)
10. L. Ren, Monte Carlo Simulation of Electron Beam Exposure and Research on Proximity Effect
Correction Technique (Graduate school of the Chinese Academy of Sciences, Beijing, 2002)
11. M. Zhao, Research on Electron Beam Lithography Process Technique (Graduate school of the
Chinese Academy of Sciences, Beijing, 2009)
12. B. Thedjoisworo, D. Cheung, V. Crist, Comparison of the effects of downstream H2- and
O2-based plasmas on the removal of photoresist, silicon, and silicon nitride. J. Vac. Sci.
Technol. B 31(2), 021206 (2013)
13. C. Cardinaud, Fluorine-based plasmas: main features and application in micro-and nanotech-
nology and in surface treatment. C.R. Chimie 21(8), 723–739 (2018)
14. K. Saga, T. Hattori, Wafer cleaning using supercritical CO2 in semiconductor and nano-
electronic device fabrication. Solid State Phenom. 134, 97–103 (2008). https://doi.org/10.
4028/www.scientific.net/SSP.134.97
15. P. W. Mertens, G. Vereecke, R. Vos, Post-etch residue and photoresist removal challenges for
the 45 nm technology node and beyond, in Semiconductor Fabtech, 31st edn. (2006), pp. 86–94
16. Wet chemical etching of metals. www.MicroChemicals.com
17. W. W. Flack, K. E. Tokunaga, K. D. Edwards, Chrome dry etching for photomask fabrication, in
Proceedings of SPIE 1809, pp. 85–96 (1992)
18. B.J. Lin, Phase-shifting masks gain an edge. IEEE Circuits Devices Mag. 9(2), 28–35 (1993)
19. W.N. Partlo, W.G. Oldham, Transmission measurements of pellicles for deep-UV lithography.
IEEE Trans. Semicond. Manufact. 4(12), 128–133 (1991)
20. A. Flamholz, An analysis of pellicle parameters for step-and-repeat projection. Proc. SPIE 470,
138–146 (1984)
21. J. He, J. Xia, Semiconductor Science and Technology (Science Press, Beijing, 2007)
22. R. Sun et al., Tanner IC Design Course (Beijing Hope Electronic Press, Beijing, 2002)
23. H. Yong, Pattern Processing and Data Format Conversion in Microlithography (Graduate
school of the Chinese Academy of Sciences, Beijing, 2002)
Lithography Equipment
65
Rongming He, Jianrui Cheng, and Fan Wang

Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328
History of Photolithography Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
Contact/Proximity Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
The Wafer Stepper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334
Wafer Scanner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337
Immersion Scanner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340
Extreme Ultraviolet (EUV) Lithography System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
Maskless Lithography (ML2) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
Electron Beam Lithography (EBL) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
Nano-Electron Beam Direct Writing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
Proximity Effect Correction Technique for Electron Beam Lithography . . . . . . . . . . . . . . . . . . 1348
Mix-and-Match Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
Processes of Nanometer Fabrication by Electron Beam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
Multiple Electron Beam Lithography System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350
Nanoimprint Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352
Wafer Track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
Coating Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
Developing Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
Baking Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
Wet Stripping System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359

Abstract
Lithography technology is one of the most important processes for IC manufactur-
ing. It determines the smallest feature size that could be achieved by humans in
high-volume manufacturing (HVM). In the past six decades, lithography technol-
ogy has pushed Moore’s law forward by shrinking the feature size from previous
several microns to current technology node of 3 nm. Resist coating, exposure, and

R. He · J. Cheng · F. Wang (*)

Shanghai Micro Electronics Equipment (Group) Co., Ltd (SMEE), Shanghai, China
e-mail: wangf@smee.com.cn

© Publishing House of Electronics Industry 2024 1327

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_65
1328 R. He et al.

development are usually considered as the three crucial steps in the lithography
process, and they are typically achieved by lithography equipment and wafer track
system. This chapter reviews the history of photolithography equipment for HVM
mainly from the aspects of proximity lithography equipment, wafer steppers, wafer
scanners, and immersion scanners, together with EUV lithography equipment.
Also, it introduces the alternatives applied in IC manufacturing such as electron
beam lithography equipment, multiple e-beam lithography equipment, and nano-
imprint equipment. Finally, other equipment for resist coating and develop pro-
cesses such as wafer track and wet stripping are presented.

Keywords
Projection lithography tools · Step-and-scan system · E-beam system · Coating
and developing · Critical dimension · Overlay

Introduction

Photolithography called as optical lithography is the core process to determine the

integration degree of IC chip. The function of this process is to transfer the circuit
pattern from photomask to the photoresist on semiconductor substrate. The basic
principle of photolithography technology is to record the photomask patterns on the
substrate surface by the photochemical reaction of coated photoresist, thus transfer-
ring the designed IC patterns to substrate. As shown in Fig. 65.1, the whole process
includes three steps. Firstly, the photoresist is coated on the substrate surface by the
coating equipment. Secondly, the photoresist coated on substrate surface is exposed
by the photolithography equipment, in which the photomask pattern is transferred to

Fig. 65.1 Basic principle of

photolithography process
65 Lithography Equipment 1329

the photoresist on substrate surface by the photochemical reaction. Finally, the

exposed substrate is processed by the developer equipment to remove (or remain)
photoresist that undergoes photochemical reactions after exposure.
Track and photolithography equipment are the two kinds of equipment that must
be used in photolithography process. Generally, coater and developer are integrated
in track. Photolithography equipment is the most expensive and complex core
system in IC chip production line. Its accuracy determines the key performances
of IC chips such as integration degree and processing speed. Advanced semicon-
ductor production line usually integrates the track directly with the photolithography
equipment for synergic operation. The process time of coating, exposure, and
developing should be accurately controlled to ensure the fidelity of the transferred
pattern.
Photolithography equipment includes photomask type and maskless type.
Maskless lithography equipment, also called direct writing lithography equipment,
is available for the flexible fabrication of special or nonstandard devices. However,
maskless lithography equipment has low production efficiency that is usually used in
prototype IC or photomask fabrication. Maskless lithography equipment can be
classified as electron beam lithography equipment, ion beam lithography equipment,
and laser lithography equipment according to the different radiation sources. In
semiconductor industry, electron beam lithography equipment is mainly used for
high-resolution photomask, prototype IC chip, and special devices; laser direct write
lithography equipment is mainly applied in the fabrication of low-volume but more
varieties products.
Optical lithography equipment can be classified as contact/proximity lithography
equipment and projection lithography equipment, the basic principle is shown as
Fig. 65.2. Although the resolution of contact/proximity image expressed by near-
field Fresnel diffraction theory can reach subwavelength level, the photomask defect
caused by the scratch between photomask and photoresist leads to lower yield of IC
chips. Proximity lithography is more suitable for mass production, however, the gap
between photomask and silicon wafer of proximity lithography equipment must be
maintained over 10–20 μm to prevent the photomask scratch; the resolution can only
reach 5 μm level that limits the applications of proximity lithography equipment.
Based on the far-field Fourier optical imaging theory, the photolithography
equipment adopts reductive projection lens to image photomask patterns onto silicon

Fig. 65.2 Basic principle of contact/proximity/projection lithography equipment

1330 R. He et al.

Fig. 65.3 Definition of

critical dimension

wafers, which can effectively improve the resolution. The realization of high-
resolution projection imaging benefits from the great development of ultraprecision
optical science and engineering technology. At present, projection lithography
equipment has achieved a resolution below one tenth wavelength, which is also
the basis for the IC industry to follow the progress of Moore’s law.
Resolution, overlay, and throughput are the three main specifications to evaluate
the technical and economic level of photolithography equipment.

1. Resolution: the minimal critical dimension in the pattern that can be transferred
from photomask to the photoresist coated substrate by photolithography equip-
ment. In general, resolution is characterized by the half pitch of device pattern. As
shown in Fig. 65.3, the critical dimension is especially referring to the profile of
developed photoresist.
2. Overlay: referring to the deviation between the expected position and the actual
position of transferred pattern. The expected position is generally determined by
the pattern of previous layer or alignment marks.
3. Throughput: the number of wafers per hour or per day processed by the photo-
lithography equipment, usually expressed as WPH (wafers per hour) or WPD
(wafers per day). The throughput determines the economic performance of
photolithographic equipment.

History of Photolithography Equipment

With the continuous increasing of wafer size and the requirement of resolution,
photolithography equipment uses several generations of technology to implement
the pattern transfer to meet the rapid process development. As shown in Fig. 65.4,
the contact/proximity lithography is the first generation of photolithography tech-
nology for the industrial production and then is replaced by projection lithography.
65 Lithography Equipment 1331

Fig. 65.4 Technology development of photolithography equipment

In projection lithography, stepper (step-and-repeat), scanner (step-and-scan), immer-

sion lithography, and EUVL systems are adopted successively.
Contact/Proximity lithography equipment, also known as aligner, has been used
in IC fabrication since the early 1960s. The basic formula of resolution R is

T
R ¼ Kρ λ gþ ,
2

w2
λ<g< :
λ
Here, Kρ is the process factor that is usually Kρ ¼ 1.5; λ is the wavelength of light
source; g is the gap between photomask and coated substrate; T is the thickness of
photoresist; and w is the pattern size of photomask. The highest resolution of aligner
can reach the submicron technology node with the 1:1 ratio of pattern size transfer,
but the resolution is limited by the above formulas. Although the residual photoresist
contamination may damage the patterns of photomask and reduce device yield, the
aligner still performs many advantages in industrial production. Firstly, the photo-
mask has the same size as the substrate and can do complete pattern transfer on the
whole substrate in one exposure. Secondly, the structure of aligner is simple for easy
maintenance and the equipment cost is much lower than other types. At present, the
contact/proximity lithography equipment is still used in the production line of small
size substrates, and is the preferred photolithography method for the micron-level
device fabrication.
Projection lithography equipment, which has replaced aligners since the mid-late
1970s is the major technology in mass production of advanced IC chips. This
1332 R. He et al.

technique projects the circuit patterns of photomask onto the photoresist coated
substrate by an optical system that includes light source, illuminator, and projection
lens. After exposure, circuit patterns are transferred as a latent image on photoresist.
With a follow-up development step, the pattern transfer is completed. In early
projection lithography equipment, the ratio of pattern size on photomask to the
latent image on photoresist was 1:1, in addition to the exposure for the whole
substrate by scanning. With the shrinkage of device critical dimension and the
increase of substrate size, step-and-repeat lithography equipment (stepper) with
reduced magnification lenses has been adopted to replace the 1:1 scanning lithogra-
phy equipment. For technology nodes less than 0.35 μm, more advanced step-and-
scan lithography equipment (scanner) has been developed to adapt the trend of
higher integration degree, bigger chip size, and larger single exposure area. Scanning
exposure mode can expand the single exposure area by using the similar optical
system as stepper. Moreover, the exposure quality can be improved by homogeniz-
ing the specific errors of photolithography equipment, and more error compensation
methods are provided. Scanner is the current photolithography system for the mass
production of ICs with 10 nm technology node. The resolution formula of projection
lithography equipment is

λ
R ¼ K1  :
NA
There, K1 is the process factor and the minimal value is 0.25 based on the partial
coherence image theory; λ is the wavelength of light source; and NA is the numerical
aperture of projection lens.
According to this formula, to enlarge the numerical aperture NA, shorten the source
wavelength λ, and reduce the process factor K1, one can improve the resolution of
projection lithography machine. The available source wavelengths for photolithogra-
phy include g-line (436 nm), i-line (365 nm), KrF (248 nm), ArF (193 nm), and EUV
(13.5 nm). EUV is the ultimate light source that can be used for photolithography
equipment and the shortest wavelength can even reach 6.8 nm. However, EUV
lithography equipment with 6.8 nm wavelength will face enormous engineering
challenges. The marketing price of a commercial EUV lithographic equipment for
the mass production of IC chips is more than 100 million USD, which is the most
expensive and complex equipment in the IC production line. At present, only ASML
in the Netherlands can provide the commercial EUV lithography equipment.

Contact/Proximity Aligner

Contact lithography was emerged in the 1960s and widely applied in 1970s, which
was the dominated photolithographic method in the era of small-scale integrated
circuit (SSI), and mainly used for manufacturing integrated circuit (IC) with the
65 Lithography Equipment 1333

feature size larger than 3.5 μm. Normally, wafer would be placed on a stage of the
contact aligner so that the horizontal and rotational position could be controlled
manually. Operator can observe the position of the photomask and the wafer with the
discrete field microscope simultaneously and aligns the photomask to the wafer by
manually controlling the position of the stage. After finishing the alignment, they
would be pushed together so that the photoresist of the wafer can almost contact with
the photomask directly, following by the exposure process when the microscopic
objective is removed. The light emitted by the mercury lamp is collimated in parallel
to the photomask through the lens, and then the pattern on the photomask could be
transferred to the photoresist layer in a ratio of 1:1 after the exposure due to their
direct contact.
Contact lithography decreases the diffraction effect of light due to the direct
contact of the wafer with photomask, therefore it can achieve the exposure of
small feature size. However, the direct contact of photomask with wafer may
cause scratches on both surfaces because of the friction, which can easily
generate particle contamination leading to fatal defects in the semiconductor
devices. The scratches and particles on photomask surface will shorten the
lifetime of the photomask, reduce wafer yield, and increase the cost of contact
lithography.
Contact lithographic equipment is the most simple and economical optical lith-
ographic type which could achieve the exposure of submicron feature size, thus it is
still used in small batch production and laboratory research so far. In the production
of large-scale integrated circuits (LSI), proximity lithography has been introduced to
avoid an increase in photolithography costs due to direct contact of the photomask
with the wafer.
Proximity lithography was widely used in the era of small-scale integrated
circuits (SSI) (1970s) and the early days of medium-scale integrated circuits
(MSI). Unlike contact lithography, the photomask in proximity lithography has no
direct contact with the photoresist on the wafer but leaves a gap filled with nitrogen.
The photomask would float above the nitrogen, and the gap dimension between them
is determined by the gas pressure of nitrogen. Benefited by noncontact of the wafer
with the photomask, the risk of defects is enormously decreased in the photolithog-
raphy process, thereby reducing the loss of the photomask and improving the wafer
yields. The disadvantage of the proximity lithography caused by the gap in the
meanwhile leads to the wafer to be in the region of Fresnel diffraction, thereby
limiting the further improvement of the resolution for the proximity lithography, so
this kind of lithography is mainly applicable to the production of integrated circuits
with the feature size more than 3 μm.
At present, foreign producers of contact/proximity lithography equipment mainly
include Sousse (SÜSS) in Germany and EVG in Austria. Domestic manufacturers
mainly include the 45th Research Institute of China Electronics Technology Group
Corporation (CEC), the Institute of Optics and Electronics of the Chinese Academy
of Sciences, etc.
1334 R. He et al.

The Wafer Stepper

The step-and-repeat aligners also named as wafer steppers or steppers have domi-
nated the optical pattern transfer in IC fabrication since the later 1980s. A stepper
adopts a reticle which contains the pattern of one chip or more chips in an exposure
field. As shown in Fig. 65.5, the optical projection exposure system of steppers
mainly adopts refractive optics to project the reticle image only onto an exposure
field of the photoresist coated wafer to implement the pattern transfer from a reticle
onto a wafer. The stepper exposes only a small portion of the wafer for each
exposure, therefore, after the previous pattern transfer on an exposure field, the
wafer stage will step to the next location on the wafer to repeat the next exposure. To
date, the maximum field size typically is 22 mm  22 mm, which is limited by the
size of the projection lens. And the reduction ratio of the projection lens typically is
either 5:1 or 4:1.
A wafer stepper consists of several subsystems for the exposure, that is, wafer
handler, wafer stage, reticle handler, reticle stage, reticle library, autofocus and
leveling system, auto-alignment system, illuminator (Hg lamp), reduction lens,
antivibration system, main frame, electronic controller, microprocessor, software,
etc. [1] (see Fig. 65.6).
The typical exposure procedure of a stepper is as follows: the wafer handler loads
photoresist coated wafers to the wafer stage piece by piece, meanwhile, the reticle
handler loads the corresponding reticle from the reticle library to the reticle stage.
Then the autofocus system measures the surface morphology of wafer at multiple
points to determine the height and the tilt angle of the exposure field, these data will
be used as a referrance to adjust the vertical position of wafer so as to focus the whole

Fig. 65.5 Principle of step-and-repeat exposure

65 Lithography Equipment 1335

Fig. 65.6 Schematic of a stepper

exposure field ranged in the depth of focus (DOF). Also, the auto-alignment system
aligns reticle with wafer to ensure that the accuracy of reticle image to exposure field
is within the overlay window, whereupon the stepper exposes the resist coated wafer
with UV light which passes through the transparent areas of the reticle, and then the
wafer stage steps wafer to the next location to repeat the same exposure sequence
again. The stepper will perform the exposure process for all fields on the wafer. Then
the wafer handler immediately unloads this exposed wafer and loads next wafer to
continue the exposure sequence once more. Each step in the exposure process is
shown in Fig. 65.7.
Steppers with Hg arc lamp illumination sources are mainly used for noncritical
layers with a CD of 0.35 μm and above. The increase in chip size along with
advanced technology nodes requires a larger exposure size and an improved optical
illuminator for steppers, therefore an evolutionary exposure equipment called as
step-and-scan system or scanner was developed for CD of 0.25 μm and below. The
scanner is a hybrid system that combines the technology from conventional step-
and-repeat steppers and scanning projection aligners. The present dynamic scan field
size of the scanner is 26 mm  33 mm which is 1.77X to that of conventional
stepper. Moreover, on a dual stage step-and-scan system, the measuring procedure in
1336 R. He et al.

Fig. 65.7 Exposure process flow of a stepper

the focus adjustment (called on-the-fly focus), wafer leveling, and alignment will be
processed at the same time during the exposure step.
Comparing with the scanner, the step-and-repeat stepper system does not equip
with a synchronours scanning controlling system, hence it is more reliable and cost-
effctively. However, the maxium exposure field size is limited to 22 mm  22 mm
only. It is not worthwhile using conventional steppers for larger exposure field sizes,
because more complex lithographic lens design and system modification will
extremely increase the equipment cost. Therefore, the step-and-scan (scanner) sys-
tem gradually replaces the step-and-repeat (stepper) system in advanced technology
nodes of IC fabrication. Nevertheless, there are still two-third noncritical layers and
one-third critical layers in most of advanced ICs, therefore a mix-and-match
approach in optical lithography equipment is arranged to enhance the productivity
and reduce the total manufacturing cost. That is, scanners are adopted to implement
the critical pattern transfer, meanwhile steppers are still adopted to implement the
pattern transfer for noncritical layers.
The step-and-repeat system is currently used in certain applications such as
noncritical IC layers and advanced package (AP) applications in which the CDs
are larger than 0.25 μm.
The first wafer stepper was introduced in 1978 by an American company GCA.
Soon after, Nikon delivered its NSR series stepper in 1980s and dominated the major
marketing share since then. At that time, Canon also joined the competition with its
strength in optics and machinery. Until 1995, these two Japanese companies dom-
inated over 70% of the global marketing share in steppers. ASML of the Netherland
is also one of major stepper vendors, its marketing share keeps growing since 1990
and is ranked as number one by the time of 2002.
For the technology node of 0.25 μm or less, the step-and-scan (scanner) system
shows more advantages both in scanned exposure size and uniformity in exposure.
Therefore, the usage of the step-and-repeat (stepper) system is gradually shrinkaged.
Presently, the newest model of Nikon stepper, which is wildly adopted in noncritical
layers of IC fabrication, has a static field size as large as that of the step-and-scan
system and a high throughput of 200 pieces per hour. Figure 65.8 shows a SMEE
stepper.
65 Lithography Equipment 1337

Fig. 65.8 An image of

SMEE wafer stepper

Instead of the traditional wire bonding packaging, for the technology node of
65 nm or less, advanced packaging technology such as flip-chip technology or
through-silicon via (TSV) 3D packaging are developed to meet the requirement of
increasing I/O density in advanced IC’s packaging applications. The Ultratech, an
US company, introduced a stepper with a refractive/reflective Dyson lens for
advanced packaging (AP) applications, and used to dominate the market for many
years. Recently, the SMEE, a China company, introduced its SSB500 series AP
stepper with all refractive projection lenses in 2009 for applications of advanced
packaging. The productivity and the performance of SSB500 are reaching to the
first-tier level, especially for the high aspect ratio exposure (≧10:1) in thick photo-
resist technology. Therefore, SMEE has owned the AP stepper market share up to
40% all around the world since 2015.

Wafer Scanner

The application of scanner (step-and-scan) lithography equipment began in the

1990s. The available exposure wavelength includes 365 nm (i-line), 248 nm
(KrF), 193 nm (ArF), 193 nm immersion (ArFi), and EUV, which can support all
the current technology nodes and process layers. Unlike the stepper, the single field
exposure of scanner adopts dynamic scanning method so that the mask and wafer
scanning move synchronously during the exposure process. After the exposure of
each field, the wafer loaded on the wafer stage then steps to the next scanning field
position to repeat the scanning exposure again. The step-and-scan exposure action is
repeated many times until all fields of the whole wafer are exposed. The (reduced)
magnification of projection lens in step-scan lithography is usually 4:1. It means that
1338 R. He et al.

Fig. 65.9 The operation principle of step-and-scan exposure

the pattern size of mask is four times the pattern size of wafer, so the scanning speed
of mask is four times that of wafer, and the scanning direction is opposite. The static
field width of projection lens is 26 mm in nonscanning direction and 5~16 mm in
scanning direction, thus the exposure field of 26 mm  33 mm size is formed after
the scanning. The operation principle of scanner is shown as Fig. 65.9.
Compared with stepper, the optical system of scanner has a smaller static field of
projection, which can reduce the manufacturing difficulty of projection lens with the
same imaging performance. Therefore, most of the advanced photolithography
equipment have adopted step-and-scan technology that starts to use from 0.25 μm
process node. In order to meet the production requirements of high throughput and
high yield, the reticle stage (photomask) and wafer stage (substrate) of scanner need
to keep high-speed and high-precision synchronous movement during the exposure
process. For example, in the most advanced immersion lithography system, the
scanning speed of worktable is as high as 800 mm/s, and the corresponding scanning
speed of photomask is as high as 3.2 m/s, as well as the relative dynamic synchro-
nous positioning accuracy is up to nanometer level. Therefore, the design and
development of premium scanner is very difficult. The key techniques that must
be solved include dynamic stability control of the machine frame, high-precision
synchronous motion control, ultralow aberration projection lens, etc. The system
architecture of scanner is shown in Fig. 65.10.
Scanner can support all technology nodes of front-end semiconductor process by
equipping with different types of light sources such as I-line, KrF, ArF, etc. The
typical CMOS process on silicon substrate has adopted scanner technology since
0.25 μm technology node. At present, the EUV lithography equipment used in 7 nm
(and below) technology node also adopts step-and-scan exposure technology. After
some modification for adaptability, scanner can also support the R&D and produc-
tion of many nonsilicon substrate processes such as MEMS, power devices, radio
frequency devices, and so on.
The main manufacturers of scanner equipment include ASML (the Netherlands),
Nikon (Japan), Canon (Japan), and SMEE (China). ASML introduced TWINSCAN
65 Lithography Equipment 1339

Fig. 65.10 System architecture of scanner

Fig. 65.11 TWINSCAN

series scanner, ASML
1340 R. He et al.

series scanner in 2001. As shown in Fig. 65.11, TWINSCAN series scanner adopts the
dual-stage system architecture that can effectively improve the throughput of equipment.
It has become the most widely used lithography equipment in the fabrication of front-
end process layers. Shanghai Micro Electronics Equipment (Group) Co., Ltd. (SMEE)
has developed 90 nm high-end scanner, which has completed the equipment integration
and carried out process tests on the customer production lines. In addition, SMEE is
aiming to develop the first domestic 28 nm lithography machine (SSA/800-10W) to
narrow the gap with the world’s chip-making technology.
The main types of scanners are listed in Tables 65.1 and 65.2.

Immersion Scanner

According to Rayleigh’s equation, increasing the numerical aperture of the projec-

tion lens and reducing the wavelength can further improve the imaging resolution.
Since the highest imaging resolution (half pitch) supported by ArF dry system is
65 nm, therefore, the immersion technique is applied to lithography equipment for
higher resolution below 45 nm [2, 3]. Immersion lithography equipment improves
the numerical aperture (NA ¼ 1.35) of the projection lens and reduce the exposure
wavelength from 193 nm to 134 nm by filling the ultrapure water with the refractive
index of 1.44 between the lower surface of the lens and the upper surface of the
wafer. The whole system architecture of immersion lithography equipment is similar
to the dry scanner system. Due to the introduction of several key techniques related
to immersion, it just belongs to the modification and expansion of dry ArF scanner
system. The principle of immersion lithography is shown in Fig. 65.12.
The advantage of immersion lithography equipment is that with the increasing of
the numerical aperture of the projection lens and the reduction of exposure wave-
length, the imaging performance of lithography equipment is improved to support
the technology node below 45 nm. Compared with the dry imaging system, the
immersion lithography equipment can further improve the effective depth of focus
under the same resolution and contrast requirements. The corresponding formula is

DOFimmersion 1 1  ðλ=pÞ2
¼ :
DOFdry
n n2  ðλ=pÞ2

Based on immersion and combined with multiple patterning and computational

lithography technique, immersion lithography equipment can be further applied in
process nodes below 22 nm. Before the industrial application of EUV lithography
equipment, immersion lithography equipment combined with multipatterning tech-
nology has been widely used to meet 7 nm nodes.
However, due to the introduction of immersion water, the engineering difficulty
of the equipment development is greatly increased. The key techniques include
immersion water supply and recovery, immersion field maintenance, immersion
contamination and defect control, hyper-NA projection lens development, hyper-
NA imaging quality test and control, etc. Due to physical limitation, the theoretical
Table 65.1 Scanner information of ASML, Nikon, and Canon
65

Wafer
Model Resolution Numerical Exposure size Overlay Throughput
Company number Exposure type (nm) Light source aperture Magnification field size (mm) (nm) (WPH)
ASML NXE EUVL 13 EUV 13.5 nm 0.33 1:4 26 mm  300 O2 125
3400B 33 mm
NXE O22 EUV 13.5 nm 0.33 O3 125
3300B
NXT Dual-stage O38 ArF Excimer Laser O1.4 275
Lithography Equipment

2000i immersion 193 nm

NXT scanner 1.35 O1.6 275
1980Di
NXT O2.5 175
1950i
XT Dual-stage O65 0.93 O5 205
1460H scanner
XT O65 0.93 O5 162
1450H
XT O80 KrF Excimer Laser 0.93 O5 205
1060 K 248 nm
XT O80 0.93 O6 180
1000 K
XT 860 K O110 0.8 O12 210
XT 400 K O350 High-pressure 0.65 O35 220
mercury lamp
365 nm
PAS Scanner O90 ArF Excimer Laser 0.75 200 O12 135
5500/ 193 nm
1150C
(continued)
1341
 1342

Table 65.1 (continued)

Wafer
Model Resolution Numerical Exposure size Overlay Throughput
Company number Exposure type (nm) Light source aperture Magnification field size (mm) (nm) (WPH)
PAS O110 KrF Excimer Laser 0.8 O15 145
5500/ 248 nm
850D
PAS O220 High-pressure 0.65 O25 150
5500/ mercury lamp
450F 365 nm
Nikon NSR- Immersion O38 ArF Excimer Laser 1.35 1:4 26 mm  200/300 O1.5 275
S635E scanner 193 nm 33 mm
NSR- O1.7 270
S631E
NSR- O2 200
S621D
NSR- Scanner O65 0.92 O2 230
S322F
NSR- O110 KrF Excimer Laser 0.82 O9 176
S210D 248 nm
Canon FPA- Scanner O90 KrF Excimer Laser 0.86 1:4 26 mm  200/300 O8 200
6300ES6a 248 nm 33 mm
R. He et al.
 65
Lithography Equipment

Table 65.2 Scanner information of SMEE

Model Resolution Numerical Exposure Wafer size Throughput
number (nm) Light source aperture Magnification field size (mm) Overlay (nm) (WPII)
SSA600/ O90 ArF Excimer Laser 0.75 1:4 26 mm  200/300 SMOO15nm 80
20 193 nm 33 mm MMOO25nm
SSA600/ O220 High Pressure Mercury 0.65 SMOO25nm 80
10 Lamp 365 nm MMOO50nm
Author(s): Gang Sun (SMEE)
Reviewer(s): Lifeng Duan(SMEE)
Transiator(s): Zhiyong Yang(SMEE)
1343
1344 R. He et al.

Fig. 65.12 Immersion

technique of scanner

Fig. 65.13 Double

patterning process of
photolithography

minimal process factor K1 is 0.25. Considering the actual engineering capability of

the equipment, the highest resolution of ArF immersion lithography technology is
about 38 nm. In order to meet the requirement of smaller critical dimension, the
performance of immersion scanner is continuously improved by several methods
that include multipatterning technique, high-precision online detection, and holistic
lithography control. At present, immersion scanner can support the 7 nm process
node, which effectively promotes the development of advanced IC manufacturing
technology before the mature era of EUV lithography.
The basic principle of multipatterning technique is shown in Fig. 65.13. In order
to realize the high-density periodic patterning, it is necessary to divide the one-time
lithography process (one layer) into several times lithography process. By means of
multiple lithographic processes of large pitch with small linewidth mask pattern, the
small pitch with small linewidth pattern can be manufactured. Taking the double
patterning technique as an example, after the first lithography, the lithography
process of coating, exposure, developing, etching, and stripping is repeated, thus a
dense pattern of small pitch is formed on the wafer surface.
65 Lithography Equipment 1345

At present, commercial ArFi scanner equipment is mainly provided by ASML

(the Netherlands) and Nikon (Japan). The NXT 1980Di system (the latest model is
NXT 2000i), one of the advanced immersion scanners that is developed by ASML,
sells for about 80 million euros.

Extreme Ultraviolet (EUV) Lithography System

In order to improve the resolution of photolithography and further reduce the

wavelength of exposure light, the extreme ultraviolet (EUV) of excimer light from
10 to 14 nm is selected as the exposure light source. Due to the extreme short
wavelength, only reflective optical systems normally consisting of mirrors coated
with Mo/Si or Mo/Be multilayers is adoptable. Theoretically, Mo/Si multilayer
coated mirror possesses maximum reflectivity of approximately 70% at the wave-
length of 13.0–13.5 nm, while the performance of Mo/Be multilayer is even better at
the short wavelength, which can achieve maximum reflectivity of approximately
80% at the wavelength of 11.1 nm. Through the higher reflectivity of Mo/Be
multilayer, the development of EUV lithography abandons the research on this
kind of coating structure due to the strong toxicity of Be element. On the contrary,
the Mo/Si is more environmentally friendly as result to be applied in the EUV
lithography, therefore 13.5 nm is determined as the wavelength of EUV light source
ultimately.
Laser-produced plasma (LPP) is the major technology to generate extreme
ultraviolet by targeting fused tin droplets into plasma with a high-powered laser.
For a long time, the power and availability of the light source is the bottleneck
restricting the efficiency of the EUV lithography machine, but they are greatly
improved by the master oscillator power amplifier (MOPA), predictive plasma
technology (PP), and the in situ collector mirror cleaning technology.
EUV lithography machine mainly consists of light source, illumination system,
projection objective, wafer stage, photomask stage, wafer alignment system, focus
and leveling system, photomask handling system, wafer handling system, vacuum
system, etc. After EUV light propagates through the reflective illumination system
with multicoated mirrors, it is irradiated on the reflective photomask, and then the
reflected light will be projected on the wafer surface by a kind of reflective imaging
optical system under the vacuum environment. The field of view for object and
image are both ring field, and the full wafer exposure is achieved by step-and-scan
exposure for each chip to increase the yield. ASML’s state-of-the-art NXE series
EUV lithography machine uses the exposure source with wavelength of 13.5 nm,
reflective photomask (inclination at 6 ), all-reflective 4x reduction lens projection
objective system (NA ¼ 0.33) with maximum scanning field of 26 mm  33 mm,
and the vacuum exposure environment.
Compared with the immersion lithography machine, the single-exposure resolu-
tion of the EUV lithography machine is greatly improved, and the complicated
process for forming high-resolution features by multiple patterning can be effec-
tively avoided. At present, the NXE3400B lithography machine with a numerical
1346 R. He et al.

Fig. 65.14 The EUV lithography system from ASML

aperture of 0.33 has a single exposure resolution of 13 nm and a throughput of

125 wafers per hour. In order to meet the further extension of Moore’s law, in the
near future, an EUV lithography machine with a numerical aperture of 0.5 will use a
central obscuration projection objective system with an asymmetric magnification of
0.25X/0.125X, and the field of view for scanning exposure will be reduced from
26 mm  33 mm to 26 mm  16.5 mm, thereby achieving the single exposure
resolution below 8 nm. Figure 65.14 shows the EUV lithography machine produced
by ASML.

Maskless Lithography (ML2) System

Maskless lithography system is classified in two categories:

1. Optical maskless lithography based on spatial light modulator (SLM): such as

DMD (digital micromirror device)-based demagnification projection, laser direct
writer (LDW), zone plate array lithography (ZPAL), surface plasma imaging
system, etc. A series of specific maskless lithography tools based on DMD
technology with their individual special characteristics have been developed.
2. Charged particle maskless lithography (CP-ML2): these direct writing systems
include electron beam lithography (EBL), multielectron beam lithography
(MEBL) based on electrostatic scalable optics, focused ion beam (FIB) direct
writing, writing with charged ink droplets, etc. Electron beam direct writing does
not need to prepare expensive mask and can reduce the R&D time for prototype
devices. Although it can demonstrate the resolution of nanometer scale, the low
throughput still limits its application in mass IC production. MEBL is a possible
solution to work out the low throughput issue. Currently, extreme ultraviolet
65 Lithography Equipment 1347

(EUV) lithography has been applied in sub-10 nm node IC production. It seems

that MEBL can be an option for nanometer lithography as the feature size of
technology node is going down further.

In order to improve the low throughput issue of conventional single e-beam

lithography, multielectron beam lithography is developed with an array of micro-
electron optics columns in which each electron beam can scan independently to write
patters. Challenges for multielectron beam lithography are pattern fidelity in writing
field to ensure the pattern butting accuracy in nanometer scale and avoid the pattern
missing during exposure. The relation between positions of function area pattern and
electron beam writing field should be taken into account during the mask pattern
layout design. Optimization to the writing field position during data fracturing for
MEBL can avoid butting error between writing fields.
Optimizing the array of beamlets of MEBL can increase direct writing through-
put. In addition, there are some other methods to improve the throughput of nano-
scale IC fabrication, e.g., mix and match between photolithography and e-beam
lithography, also called complementary e-beam lithography (CEBL) technique, that
is, with electron beam lithography to implement small feature size patterns while
other large feature size patterns are exposed with current photolithography
technology.

Electron Beam Lithography (EBL) System

Electron beam lithography (EBL) system using the computer input address and
pattern data can control the focused electron beam to directly write circuit layout
patterns on photosensitized layer coated on the substrate surface, thus it is also called
the electron beam direct writer. Electron beam lithography can expose one layer
pattern on substrate to produce micro/nano-structures, can also register several layers
of IC pattern for overlay processes, or mix and match among different lithography
systems.
To implement the overlay of multilayer pattern with electron beam lithography,
registration marks for the registration of electron beam only or mix and match are
processed on wafer surface in advance for the alignment of e-beam direct writing. As
registration marks are scanned over by the electron beam, back scattered electrons
and secondary electrons are emitted and then can be collected by electron detectors.
According to these electrons’ signals, position errors, rotation errors as well as scale
errors of registration marks will be derived, and the compensated data for pattern
writing will be modified according to these errors. Finally, the pattern written by
e-beam will be precisely aligned with the previous pattern on wafer [4].
From the point view of function, there are two types of electron beam lithography.
One is the quick mask making type with high throughput, and another one is high
resolution of nano-scale type which has higher resolution but low throughput. In
general, Gaussian electron beam with vector scan is applied to write nanometer-scale
features. The electron density of e-beam spot is a Gaussian distribution type.
1348 R. He et al.

Therefore, apertures with a small round hole are assembled in the electron beam
column to block the stray electrons to achieve a uniform electron beam with a
suitable small diameter. Different sizes of aperture are chosen to meet the writing
speed and accuracy for process requirement. In addition, according to the pattern size
and accuracy requirement, to implement the mixed electron beam exposure with
different spot sizes of e-beam can significantly increase the throughput.
The scanning field size of e-beam is very small, therefore, the pattern layout has to
be partitioned into several writing fields and converted to the data format of electron
beam exposure machine before the exposure. In order to improve the pattern
stitching accuracy, each writing field will be divided into several subfields. Electron
beam with a width of subfield (e.g., 250 nm) will continuously do scanning exposure
from the corner of the first pattern which locates near to the coordinate origin of
stage. After finishing one subfield exposure, electron beam is deflected to the next
neighboring subfield to continue the scanning exposure until all subfields of the
writing field are exposed. Then the stage moves to the next writing field for exposure
step by step until the whole wafer is exposed. Usually, e-beam with vector scan
exposure is used for nanometer electron beam direct writing system [5].
Several different types of e-beam lithography systems for mass production are
under development for solving the low throughput issue of e-beam lithography; e.g.,
reflective electron beam lithography (REBL), electron beam stepper, proximity
electron lithography (PEL), and multielectron beam lithography (MEBL) [6].

Nano-Electron Beam Direct Writing System

In addition to writing nano-scale pattern directly on photoresist coated on substrate

surface, electron beam lithography can also be used for nano-scale mask making,
e.g., X-ray mask, EUV mask, mask for photo-projection, mask for electron beam
projection, imprint template, block copolymer self-assembly template, etc. Electron
beam direct writing system with vector scan is often used to fabricate nanometer
patterns [7]. Here, electron beam proximity effect correction, mix-and-match lithog-
raphy, e-beam nano-scale fabrication processes, etc. are critical processes and
techniques for nano-scale electron beam lithography [8].

Proximity Effect Correction Technique for Electron Beam

Lithography

In electron beam lithography, incident electrons interact with atoms in solid through
elastic collision or inelastic collision to generate scattering phenomena. It means that
electrons entering photoresist will be scattered to random directions. In addition, some
electrons penetrate through photoresist layer into the substrate to collide elastically
with substrate atoms and will also be further scattered along different trajectories. Part
65 Lithography Equipment 1349

of these scattered electrons with large reflective angle, also known as backscattered
electrons, may reenter into the photoresist layer to induce more extra exposure.
Photoresist exposed by forward scattered electrons and backscattered electrons will
distort the feature size, and that is so-called proximity effect. Based on pattern density
and computer simulation, optimized parameters of e-beam exposure, geometry
induced correction, and e-beam dose correction, the proximity effect of e-beam
lithography can be suppressed to achieve the nano-scale feature size.

Mix-and-Match Lithography

Electron beam lithography with a nanometer scaled e-beam spot size can demon-
strate an ultrahigh resolution for exposure. The minimum scanning step size is about
0.125 nm, however, its exposure throughput is very low. In order to improve the low
throughput issue, mix-and-match lithography techniques are adopted to improve the
throughput, such as the electron beam lithography combined with conventional
photolithography, mixed high/low e-beam currents, combined high/low e-beam
doses, mixed large/small apertures, combined large/small spot sizes, etc.

Processes of Nanometer Fabrication by Electron Beam

Processes and issues related to the nanometer fabrication by electron beam include both
the resist process and the electron beam lithography techniques described as follows [9].

1. Parameters adjustment of electron optics column to optimize the performance of

exposure: including high voltage and beam current density adjustments, etc.
2. Applications of e-beam resist processes: including the optimization the exposure
dose for e-beam resist, applications of high sensitivity and high-resolution
e-beam resist as well development technique of e-beam resist.
3. Manufacturability of pattern design for e-beam lithography: including time-
related manufacturability for e-beam lithography and proximity effect related
manufacturability.
4. Adjustment of e-beam exposure dose to solve the problem of parameter uncer-
tainty for the nano-scale pattern exposure.
5. Issue of sub-20 nm line width exposed with e-beam lithography.
6. Collapse and adhesion issue of e-beam resist with high-aspect-ratio structure.
7. Effects of charge accumulation on insulating substrate during the e-beam expo-
sure: coating film with conductive nanoparticles, the conductive layer could be
washed away with deionized water after the exposure.
8. Reverse-tone issue of e-beam resist under high accelerating voltage and high-
dose e-beam exposure.
9. Accumulated exposure issue induced by secondary electrons, backscattered elec-
trons, X-ray, and other random scattering electromagnetic radiation that generated
1350 R. He et al.

Fig. 65.15 JEOL nanometer

electron beam direct writer.
(Courtesy of JEOL Company)

Fig. 65.16 Raith electron

beam direct writer. (Courtesy
of RAITH Company)

by the electron beam bombardment on the conductive metal film during the
e-beam exposure step.

Figures 65.15 and 65.16 show JEOL nanometer electron beam direct writer and
Raith electron beam direct writer, respectively.

Multiple Electron Beam Lithography System

Electron beam lithography is a technique that uses a focused e-beam to scan the
wafer surface to form latent patterns on photoresist. To still maintain the high-
resolution characteristics of electron beam lithography, multiple e-beam lithography
65 Lithography Equipment 1351

Fig. 65.17 Schematic diagrams of the multiple e-beam lithography

(MEBL) realizes the parallel writing by independently controlling multiple focused

electron beams, thereby increasing the writing speed of patterns on wafer and
satisfying the efficiency requirements of production. There are two major
implementations in multiple e-beam lithography, namely multiple aperture pixel
resolution enhancement technology and multiple beam projection technology, as
shown in Fig. 65.17.
In the technique of multiaperture pixel resolution enhancement, the electron beam
from the e-gun is collimated to form multielectron beams through an aperture array.
These collimated beams then are focused by an electromagnetic condenser to the
specific position of beam blanker array which can control the on and off of each
collimated electron beam. These multiple e-beams are subsequently focused to form
e-beam dot matrix by the projection lens array. Each electron beam passes through
the deflector array to achieve a larger scanning range and thereby fills the gap
between the projection lens arrays.
In the technique of multielectron beam projection, each single e-beam of the
multielectron beam projection is irradiated on the corresponding spatial modulator
device with an illumination system, and then the modulated electron beam is imaged
onto the wafer surface by an individual projection objective. The predefined pattern
can be formed on the photoresist by controlling the on and off of the spatial
modulation device. The stage carries the wafer synchronizing with the spatial
modulation device to realize the scanning exposure of the whole wafer.
1352 R. He et al.

Nanoimprint Equipment

In 1995, Professor Stephen Chou of Princeton University in the USA was the first
scientist to propose the nanoimprint technology. The high-resolution e-beam tech-
nique is employed to print the predefined nanopatterns on the template, and then
molds the polymer material on the sample by pressing the template, thereafter the
polymer is cured in a certain way to complete the pattern transfer. According to
different methods to mold and cure the polymer material, the nanoimprint technol-
ogy can be divided into hot embossing lithography (HEL), UV nanoimprint lithog-
raphy (UV-NIL), and microcontact printing (μCP). In the UV nanoimprint
technology, chemical reaction can occur at room temperature to avoid the overlay
problem caused by the photomask or substrate thermal expansion in the HEL. In
addition, it uses the transparent quartz template, thus the substrate can be directly
observed through the template during alignment, thereby the precision of overlay is
further improved. The schematic diagram of the UV-NIL is shown in Fig. 65.18. The
substrate dispensed with liquid-type imprinting polymer is directly stamped by the
template, and followed by the UV light curing process to solidify imprinting
polymer for molding patterns. Subsequently, the template is separated away to
proceed the etching process. Based on the imprinted patterns molded with the
cured polymer, the pattern of the template is then transferred into the substrate at
the end. UV-NIL equipment usually consists of ultraviolet light source, illumination
system, imprint head, wafer stage, alignment system together with wafer handling
system, etc. The wafer stage transfers the wafer to the imprint head to dispense fluid-
type imprinting polymer. The alignment system is combined with the wafer stage for
field-by-field alignment to stamp the template. Meanwhile, the adjustment of align-
ment is performed in real time during the imprinting process. After imprinting, the
exposure system illuminates the UV light to cure the imprinting polymer and detach
the template at the end. In recent years, the industry has adopted high-order distor-
tion control technology based on microlens arrays, wafer temperature control

Fig. 65.18 The schematic diagram of UV-NIL technology

65 Lithography Equipment 1353

technology, and wafer shape calibration technology to improve the overlay accuracy
of UV-NIL (currently below 5 nm).
Nanoimprint technology has the advantages of low cost and high resolution,
which can implement line width below 10 nm. However, this technology also suffers
from many drawbacks, such as high defect rate, template contamination, and low
overlay accuracy.
At present, major vendors of nanoimprint lithography equipment include Canon
in Japan, EVG in Austria, and Sousse (SÜSS) in Germany.

Wafer Track

Standalone photoresist coater, developer, and baking assemblies are used to apply in
the lithography bay of IC production lines for decades. However, particles contam-
ination, miss operation, and efficiency loss significantly reduced the product yield.
With the automation technology, vendors start to combine the coater unit, developer
unit, and baking unit together to form the wafer track system which can obviously
improve the throughput and efficiency of IC manufacturing. Furthermore, the
integration of wafer track system with the photolithography equipment can further
optimize the process reliability and efficiency for the improvement of product yield.
Therefore, this kind of integration has gradually turned into a standard in 200 and
300 mm IC production lines. The schematic diagram and the main process flow of
wafer track are shown in Fig. 65.19. Recently, wafer track equipped with automatic
film thickness measurement module and CD measurement module for in situ
characterization is also available. The concept of cluster system with kinds of
process modules and in situ characterization modules together to improve the

Fig. 65.19 The schematic diagram of wafer track

1354 R. He et al.

throughput, efficiency, reliability, and yield will be the mainstream in equipment

industry.
Track system is mainly composed of three subsystems: coating unit, developing
unit, and baking unit. By using robotic manipulators, wafers can be transferred and
processed among these subsystems to complete the process of photoresist coating,
curing, developing, and hardening.

Coating Subsystem

The main function of the coating subsystem is to coat a uniform photoresist layer on
wafer surface. It uses a high-precision photoresist pump to accurately dispense
certain amount of photoresist on the wafer center. By accelerating rotation of the
spindle motor, centrifugal force spreads the liquid photoresist to cover the whole
wafer surface with a uniform thickness. The process step is expressed as follows:
(1) transfer wafer from cassette to the vacuum chuck; (2) drip liquid-type photoresist
onto the wafer surface through a pump driving nozzle; and (3) fully cover the wafer
surface with a uniform photoresist by the high-speed spindle motor. The rotary speed
of the wafer is typically between 50 and 8000 rpm (adjustable) with the accuracy of
1 rpm. As shown in Fig. 65.20, the photoresist coating process includes HMDS
primer coating, wafer cooling, photoresist coating, and soft baking.
In order to enhance the adhesion between photoresist and wafer surface, the vapor
of adhesion promoter (HMDS) is sprayed onto the wafer surface at 100–140  C in a
sealed chamber. Meanwhile, harmful volatile substances are discharged by an
exhaust system.
The viscosity coefficient of photoresist is very temperature sensitive. The varia-
tion of wafer temperature affects the uniformity of photoresist thickness signifi-
cantly. Therefore, after the HMDS spraying step, wafer temperature must be
immediately reduced to an appropriate range of 22–25  C by a cold plate unit, and
then cooled down wafer will be applied to the subsequent photoresist coating.
Track system equipped with multiple coating units is available now. Each coating
unit may have one or more photoresist supply modules for coating different photo-
resists. With the increase of wafer size, multiple positions or movable photoresist
nozzles have been adopted. Photoresist thickness is typically in the range of

Fig. 65.20 Process flow of photoresist coating

65 Lithography Equipment 1355

Fig. 65.21 The schematic diagram of a spin coater

Fig. 65.22 Soft bake

assembly

300–3000 nm, and the maximum deviation of film thickness for wafer in wafer and
wafer to wafer is strictly controlled at 2–5 nm. There are two kinds of photoresist
pump used in the dispensing module: single-stage pump and dual-stage pump. The
dispensing module also includes filters, bubble removal, and photoresist suction
back control devices to avoid the particulates. The schematic diagram of photoresist
spin coater is shown in Fig. 65.21.
The coating unit is usually equipped with edge bead removal (EBR) and back side
rinse assemblies which dissolve photoresist at the bevel edge area of wafer and then
wash edge area as well as the back side of wafer.
After photoresist coating, the soft bake is performed in a relatively sealed
environment to solidify the photoresist at 90–180  C for 1–2 min by evaporating
the volatile organic substance in photoresist. Then the wafer is cool down and sent
back to the cassette. Figure 65.22 is an assembly diagram for soft bake.
The uniformity and consistency of photoresist thickness is mainly determined by
the stability and repeatability of spindle speed. Meanwhile, the effective and uniform
spread of photoresist is controlled by the acceleration of rotatory assembly and the
1356 R. He et al.

viscosity of photoresist. In addition, temperature/humidity of the ambience, the

structure of coating chamber, wafer temperature before coating, and soft bake
parameters also affect the coating effect.

Developing Subsystem

The main function of developing unit is to exhibit a patterned photoresist which

corresponds to patterns of mask/reticle through a wet chemical reaction. The process
flow is as follows: (1) dispense the developer solution on wafer surface through the
spray nozzle; (2) implement the development step to reveal patterns; (3) spray DI
water onto wafer surface to wash away dissolved photoresist; (4) DI water rinse and
nitrogen purge patterned wafer at a high spin rate; and (5) hard bake to enhance the
polymerization and adhesion of patterned photoresist. Then the wafer is transferred
to the cassette as shown in Fig. 65.23.
During the developing step, the adjustable rotation speed of the wafer is in the
range of 50–8000 rpm with the accuracy of 1 rpm. Developer solution dispensers of
columnar type, fan-shaped type, rain-curtain type, or fog-like type are applied to
meet the requirement of film thickness and developing scheme for different photo-
resists. During the developing process, the backside of wafer must be protected to
prevent from contaminants of developer residues.
Developing process is a wet chemical reaction that is very temperature sensitive.
Higher temperatures can enhance the chemical reaction rates, which can distort the
pattern dimension and impact the device yield. Therefore, the temperature of devel-
oper solution is usually kept at 23  C by a circulating water bath, in which the
temperature of circulating water is maintained in the range of 20–25  C with the
accuracy of 0.2  C by a heat exchanger.
The following hard baking step is accomplished in an independent unit at a
temperature range of 90–180  C for 1–2 min. Hard bake can further remove the
residual solvent in the photoresist, increase the adhesion between the photoresist and
the wafer, as well as generate more polymerization in patterned photoresist for
enhancing the etching resistance.
Main factors affecting the performance of developing process are developer
composition, developing temperature, developing time, developing mode, baking
temperature, and baking time. After the development step, the pattern inspection
must be implemented to verify the developing quality. Common developing issues
affecting optimal photolithography resolution include incomplete developing,
underdevelopment, overdevelopment, etc.

Fig. 65.23 Development process flow

65 Lithography Equipment 1357

Table 65.3 Heating method, control methods, hot plate structure, and technical parameters
Heating Structure of Control Temperature Temperature
No method hot plate method precision/ C uniformity/ C
1 Heater open PID 1 3
strip
2 Heater closed PID 1 2
strip
3 Silicon closed PID 0.5 1.5
heating
4 Partition closed PID 0.25 1
heater

Baking Subsystem

The purpose of baking is to evaporate the organic solvent in the photoresist film and
enhance the adhesion capability of photoresist on the substrate. Usually, integrating
baking units with the track system can streamline the process integration of coating,
baking, developing, and hardening for the automation. However, to separate auto-
matic baking units from the coating/developing equipment is sometimes an option
for special process requirements in some customized equipment.
The standalone automatic baking equipment are equipped with baking units (hot
plate) only. For 150–300 mm wafer processing, 12–24 baking units are usually
equipped to meet the demand of different processes and production capacity. The
throughput of the equipment is determined by the required time of baking process.
Therefore, the optimal productivity can be improved by adding an appropriate
number of baking units only because of the capability of the wafer transfer unit.
The performance of the baking equipment is determined by the baking temper-
ature, the precision of temperature, and the temperature uniformity of wafer. Baking
temperature achieved by various methods is restricted by the photoresist character-
istics under heating process in the range of 30–200  C. The precision and the
uniformity of temperature are determined by the heating and as well control method,
and the hot plate structure of baking unit. Table 65.3 lists common heating methods,
control methods, hot plate structure, and realized technical parameters.
Volatile substance produced by organic solvents in photoresist during the baking
step is environmentally harmful, Therefore, the baking process is usually
implemented in a relatively sealed chamber to facilitate the collection and discharge
of volatile substances.

Wet Stripping System

Wet stripping equipment for 50–300 mm wafers is mainly used to remove the
residual photoresist from the surface of post-etched wafers. Single-wafer processing
equipment and batch processing equipment are available. For large diameter wafers,
wet stripping equipment gradually plays a major role in IC manufacturing. Usually,
1358 R. He et al.

stripping methods of the single-wafer stripper include the normal pressure washing
method and the high-pressure stripping method. In order to implement the removal
of thick photoresist films, single-wafer stripper is generally equipped with a soaking
unit, which can soak multiple wafers in one time to improve the throughput of
equipment. The process flow of single wafer wet stripping is as follows:

Soaking process is carried out in the soaking tank. Generally, the soaking tank has
equipped with auxiliary heaters and ultrasonic oscillators to enhance the degumming
capability for photoresist stripping. The stripping of residual photoresist is a chem-
ical reaction, so the hot degumming solution can increase the dissolution rate of
photoresist in soaking step. In addition, ultrasonic oscillators with a frequency of
20~40 kHz can not only create many strong local pressure shocks to shed photoresist
from the wafer surface, but also generate a flowing degumming solution to sweep
away dissolved by-products from the wafer surface for the incoming of fresh
degumming solution [10]. The efficiency of ultrasonic degumming process is related
to the temperature and pressure of degumming solution, as well as the frequency and
power of ultrasonic oscillators, etc. Generally speaking, increasing the power of
oscillators can effectively improve the cleaning effect. However, for wafers with
trench patterns or thinner thickness, excessive power may lead to the risk of pattern
damage or even wafer breakage. Hence, a reasonable placement of ultrasonic
oscillators is one of the key considerations for machine design.
Normal pressure degumming washing method is commonly used to remove thin
photoresist films (about 10 μm). That is, to dispense the hot degumming solution
directly onto wafer surface for dissolving photoresist film completely, and then rinse
the wafer with DI water and do spin-drying for wafer. The temperature of hot
degumming solution is generally maintained by a water bath with a temperature of
50~80  C.
High-pressure degumming washing method is usually applied to strip stubborn
photoresist films, or to speed the stripping rate for improving machine productivity.
The degumming solution is pressed with the pressure to 5~20 MPa through a
gas-liquid booster pump, and then delivered through a cylindrical or fan-shaped
nozzle to wash the wafer surface. A large amount of “solution mist” will be
generated as the high-pressure degumming solution impacts the wafer surface,
therefore, a sealing design for the process equipment is also a key factor to be
considered. In addition, wafer rotation is necessary during the entire degumming
process. In case the degumming liquid is continuously sprayed onto the surface of
the rotating wafer, the photoresist stripping effect by the hot high-pressure
degumming solution will be enhanced on the rotating wafer, because the centrifugal
force of high-speed rotation can separate the dissolved by-products or particles from
the wafer surface in time.
Single wafer stripping is a wet process which usually adopts the design of dry-in
and dry-out. In order to avoid the degumming solution being sucked into vacuum
pipelines to cause the corrosion and damage in pipelines of equipment, any vacuum
65 Lithography Equipment 1359

suction related assemblies, such as spin vacuum chuck for wet wafer holding or the
handling robot arms for wet wafer transfer, are not allowed to use.
Degumming solution is quite expensive, and the degumming solution being only
used once still has a strong capability to dissolve photoresist films. Therefore,
stripping system is usually equipped with a solution recycle unit for fully using
the residual dissolving function of degumming solution, also reducing the environ-
mental pollution and suppressing the temperature fluctuation of degumming solu-
tion. Furthermore, the odor of degumming solution vapor is pungent and harmful,
therefore, wet stripping system usually with an exhausting hood is mostly fully
automatic from cassette to cassette for the environment-friendly purpose.

References
1. M. Quirk, J. Serda, Semiconductor Manufacturing Technology (Prentice Hall, 2001)
2. B. J. Lin, Immersion lithography and its impact on semiconductor manufacturing, in Pro-
ceedings of SPIE 5377, Optical Microlithography XVII, 28 May 2004
3. B.J. Lin, Optical lithography – present and future challenges. C.R. Phys. 7, 858–874 (2006)
4. J. He, J. Xia, Semiconductor Science and Technology (Science Press, Beijing, 2007)
5. B. Chen, M. Liu, Q. Xu et al., Microlithography and micro & nano fabrication technology, in
National 13th Electron, Ion and Photon Beam Annual Academic Conference in China, 2005,
pp. 9–23
6. B. Chen, Electron beam lithography technology and pattern data process technology. Micro-
nanoelectron. Technol. 48(6), 345–352 (2011)
7. M. Yu, Research on Key Technologies and Related Mechanism of Electron Beam Lithography
in Micro-Nano System (Harbin University of Science and Technology, Harbin, 2015)
8. Baoqin Chen, Discussion on technology of electron beam nano-lithography, in National
Workshop of Technology of Semiconductor Devices, Industry Development and 6thworkshop
of Micro & Nano Electronic Technology, 2013, pp. 4–6
9. Y. Du, Research on Key Technologies of Photomask for EUV Lithography (University of
Chinese Academy of Sciences, Beijing, 2013)
10. L.C. Jun, Z. Quan, L.C. Xiang, Y.H. Xing, Theory and method of silicon wafer cleaning.
Semicond. Inf. 37(2), 30–36 (2000)
Diffusion and Ion Implantation Equipment
66
Zhaoyang Cheng, Xiaozhen Liu, Junyu Xie, and Zhuliang Zuo

Contents
Introduction to Diffusion and Ion Implantation Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
Horizontal Diffusion Furnace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
Vertical Diffusion Furnace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
Annealing Furnace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
High-Pressure Oxidation Furnace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
Medium-Current Ion Implanter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
High-Current Ion Implanter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
High-Energy Ion Implanter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
Rapid Thermal Processing (RTP) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381

Abstract
Both diffusion and ion implantation equipment are used in the doping process for
IC manufacturing. By introducing impurities into silicon, the type, concentration,
and distribution of the main carriers in the substrate are controlled along with the
conductivity and the polarity type of the substrate. Diffusion equipment is based
on the principle of high temperature thermal diffusion. It has the advantages of
simple structure, high diffusion rate, and high doping concentration. The ion
implantation equipment can precisely control the doping concentration and
junction depth at lower temperature by introducing energetic dopant ions into
silicon substrate. With the advantages of good repeatability and a wide variety of
optional impurities, it has become the main doping technology in current IC
manufacturing. Due to the cost and complex structure, high-dose doping is time-
consuming, and tunneling effects and injection damage may occur. In this

Z. Cheng (*) · X. Liu

Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China
e-mail: chengzhaoyang@naura.com
J. Xie · Z. Zuo
China Electronics Technology Group Corporation (CETC), Beijing, China

© Publishing House of Electronics Industry 2024 1361

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_66
1362 Z. Cheng et al.

chapter, the main types of horizontal diffusion furnaces, vertical diffusion fur-
naces, and ion implantation machines are introduced in detail. In addition,
oxidation furnaces, annealing furnaces, and other process equipment are also
introduced.

Keywords
ULPA · Oxidation · Chamber · Heater · Ion source · Concentration · Beam
intensity · Laser annealing · Target chamber · RTA

Introduction to Diffusion and Ion Implantation Equipment

The diffusion process at high temperatures is a conventional method to introduce

dopants into semiconductor materials to control the polarity, concentration, and
distribution of dopants in substrates, thereby controlling the conductivity and
polarity type of the substrate. Diffusion sources usually are classified as solid
sources, liquid sources, and gaseous sources. Horizontal diffusion furnaces and
vertical diffusion furnaces are main the equipment to drive dopants into semi-
conductors in IC fabrication. The dopant profile is always isotropic in the diffusion
process, in addition, dopant concentration and junction depth cannot be indepen-
dently controlled to achieve the optimal performance of devices. Therefore, very
few diffusion processes are currently performed for advanced IC products. Instead,
ion implantation processes play a major role to introduce dopants in advanced
IC Fabs.
The mechanism of ion implantation is that energetic dopant ions, accelerated by
the EM field, bombard semiconductor substrates directly to get an accurate control
over the concentration and depth of dopants in substrates. Ion implantation can
independently control both dopant concentration and junction depth. In addition, it is
a room temperature process with a layer of photoresist to block the energetic dopant
ions, and the dopant profile is anisotropic to fully reflect the area defined by the
photoresist mask. Also, due to the good reliability and reproducibility of ion
implantation technology, both batch and single-wafer implanters are applied as the
main equipment for dopant introduction in advanced IC Fabs currently.
The ion implanter is one of the most complicated equipment used in IC production
lines. It has several subsystems, including gas system, vacuum system, electrical
system, control system, ion source, ion extraction system, mass analyzer, linear accel-
erator, charge neutralization system, wafer handler, and ion beam stop system. The
whole system can precisely control both the ion dose and the ion energy to implement
the doping process. Usually, the energy of ions is several hundred eVs to MeVorder and
the implanted projection range is 10 nm to several micro-meters. The implantation
doses generally range from 1011/cm2 to and 1015/cm2 for CMOS, however, for Sepa-
ration by IMplantation of OXygen (SIMOX), the dose of oxygen ions is above 4

1017/cm2. According to the requirement of the ion energy and the ion dose in IC
fabrication, ion implanters can be roughly classified into three types: low-energy high-
66 Diffusion and Ion Implantation Equipment 1363

current ion implanters, medium-current ion implanters, and high-energy ion implanters;
those have different applications to meet manufacturing processes [1].
In an ion implantation process, incident ions collide with atoms in crystal to
generate a damaged layer consisting of interstitial atoms, vacancies, and intersti-
tial dopants. Damage effect is related to the ion mass, ion dose, and ion energy.
The damage of crystal lattice increases with the increasing ion dose and ion
energy. In order to achieve the device performance, it is necessary to perform
a thermal annealing process to repair the lattice damage and activate dopants.
Thermal annealing process can provide energy to drive interstitial atoms com-
bining with vacancies for the recovery of crystal structure and also move inter-
stitial dopant atoms to lattice sites. That is, crystal recovery, dopant atom
activation, and dopant atom redistribution happen simultaneously during the
thermal annealing step.
Conventional annealing process is performed by either the horizontal diffusion
furnace or the vertical diffusion furnace at high temperature for about 30 min to
repair implantation-induced crystal damages. However, the furnace annealing usu-
ally cannot remove defects completely and activate dopants efficiently. In addition,
due to the high annealing temperature and long duration of the process, furnace
annealing may easily lead to the serious redistribution of dopants and then degrade
the device characteristics. However, Rapid thermal processing (RTP) can effectively
activate dopants while suppressing the dopant redistribution, therefore, for
sub-micro devices, rapid thermal annealing (RTA) technology is applied instead of
the furnace annealing to well control the thermal budget in advanced IC production
lines currently.
RTP equipment is a single wafer system performing at a certain temperature
(typically 400–1300  C) with a high temperature ramp rate of 150  C/s to 250  C/s
for the post-implantation annealing. The implantation damage can be effectively
annealed out in less than 20 s at 1150  C. It has the advantages of a lower thermal
budget, a small redistribution of dopants, less contamination, and a shorter pro-
cessing time (about 1 min per wafer) compared with the furnace annealing. Addi-
tionally, the RTA process can adopt a variety of energy sources to implement the
annealing process in a time range of several seconds with halogen lamps to several
nanoseconds with lasers. The flexibility of RTA is more convenient for the fabrica-
tion of nano-meter devices [2].
The equipment industry of China for integrated circuit manufacturing is still in
the developing stage. Currently, vendors in China are already capable of supplying
all the equipment for IC fabrication with wafer diameters less than 150 mm. Main
Chinese vendors of diffusion furnaces include NAURA and the 48th Research
Institute of China Electronics Technology Group Corporation. So far, Japan’s
Tokyo Electron Ltd. (TEL) and Hitachi Kokusai Electric (HKE) still dominate the
market of 300 mm vertical diffusion/oxidation furnace equipment in China. The
average price for each single unit is about USD 800,000. Recently, NAURA can
already provide 300 mm vertical furnace systems in small batches.
Most of ion the implanters used in China’s IC production lines are provided by
foreign vendors. These major implantation equipment manufacturers include SPIRE
1364 Z. Cheng et al.

and ISM Tech in the USA; AEA Industrial Tech, Tec Vac., and Tech-Ni-Plant in the
UK; NITRUVID and IBS in France; INASMET and AIN in Spain; MAT in Ger-
many; and DTI Tribology Centre in Denmark. Chinese vendors such as Beijing
Zhongkexin Electronic Equipment Co., Ltd., the 48th Research Institute of China
Electronics Technology Group Corporation, and Kingstone Semiconductor Joint
Stock Company Ltd. can also provide a small number of implanters. Recently,
Zhongkexin has the capability to mass produce implanters with different models
(low-energy high-current, medium-current, and high-energy ion implanters) for the
production line.
Major vendors of RTP equipment are Applied Materials, Axcelis Technology,
Mattson Technology, and ASM in the USA. These companies own about 90% of the
global market share.

Horizontal Diffusion Furnace

The horizontal diffusion furnace is the most popular thermal wafer processing equip-
ment widely used in the front end of line (FEOL) of IC fabrication mainly for wafers
with a diameter of 150 mm or less. It consists of a horizontal furnace main body
including heating elements, the reaction tube (quartz or SiC), the quartz boat, quart
boat paddles, gas delivery system, wafer loading system, and exhaust system. Hori-
zontal Diffusion furnaces are normally implemented in the processes of diffusion,
oxidation, Low Pressure Chemical Vapor Deposition (LPCVD), annealing, as well as
alloying for discrete devices, power electronics, photoelectric devices, and optical
fibers, etc. Main performance factors of the horizontal furnace are as follows; maxi-
mum 200 wafers/batch, larger cleanroom footprint, worse gas distribution due to
paddle and boat hardware, large temperature gradient due to the radiation shadow of
paddle, poor particle control, and difficult to control the furnace ambient. Therefore,
horizontal furnaces normally are applied for non-critical processes especially for
technology nodes larger than 0.5 μm [2].
In addition, conventional thermal diffusion processes are mainly proceeded at the
temperature ranging from 900  C to 1200  C, to incorporate dopants into the silicon
substrate to change both the local polarity and the electrical properties of materials,
and form devices, such as, pn junctions, resistors, capacitors, bipolar transistors, Al
metal gate MOS, etc. However, the dopant distribution and the junction depth are
mutually dependent through the thermal diffusion, and the high temperature process
also induces a serious fluctuation in dopant profile and the junction depth. Therefore,
thermal diffusion processes have been gradually replaced by ion implantation for
advanced IC fabrication in 200 mm and 300 mm production lines.
A schematic diagram of a horizontal diffusion furnace is shown in Fig. 66.1. The
horizontal diffusion furnace can be equipped with a maximum of five furnace tubes
together in one time. More furnace tubes equipped in one system can provide higher
productivity and further raise the utilization efficiency of the clean room.
The main technical parameters of common horizontal diffusion furnaces are as
follows: the operating temperature ranges from 600  C to 1300  C, the length of flat
66 Diffusion and Ion Implantation Equipment 1365

Fig. 66.1 Schematic diagram of a horizontal diffusion furnace

Fig. 66.2 Structural diagram of a horizontal diffusion furnace

zone ranges from 600 to 1100 mm, the temperature accuracy in the center of flat zone
is 0.5  C at 1000  C, the maximum controllable ramp up rate is 15  C/min, while
the maximum controllable ramp down rate is 5  C/min.
The system configuration of the horizontal diffusion furnace is flexible and can
be arranged according to users’ requirements, however, the basic functional units
are almost the same. As shown in Fig. 66.2, the whole system consists of a
purification workbench, a furnace main body, a gas source cabinet, and a control
cabinet.

1. Purification workbench: The procedures of wafer loading and unloading, quartz

boat transfer, and automatic loading/unloading are completed in a clean environ-
ment with horizontal laminar flow.
1366 Z. Cheng et al.

2. Main frame cabinet: This unit includes the detoxifying cabinet, main furnace
body, power supply for heaters, and heat exchanger. It is the core unit to manage
the heat treatment process.
3. Gas source cabinet: This unit includes the gas piping unit, source temperature
controller, gas piping control unit, and exhaust unit. It is used to control the
delivery of process gases.
4. Control cabinet: An industrial main computer is used to communicate with each
micro-controller through a network. Each furnace tube is individually adopted
with an independent control system, which can automatically control parameters
of recipes and the operation of units, such as temperatures, gas flow rates, on/off
of valves, quartz boat transfer, and the running of vacuum pump, so as to enable
the process management of recipes.

Vertical Diffusion Furnace

The vertical diffusion furnace (VDF), also called as a vertical furnace, is a conven-
tional hot wall furnace which generally can process large quantities or batches of
200 mm or 300 mm wafers (about 100 wafers/batch). It consists of five major
systems to a vertical furnace system, that is, process chamber, temperature control
system, wafer transfer system, gas piping system, and the exhaust system. Its main
performance factors include small cleanroom footprint, wafer boat rotation for film
uniformity improvement, small thermal gradient across wafer, less warpage with
horizontally placed wafers, better particle contamination control from top-down
loading design, easy automation with robots for wafer loading/unloading, uniform
gas flow dynamics, easier and quicker change for quartz wares, good wafer-within-
wafer uniformity, etc. Currently, vertical furnaces are adopted in advanced 200 mm
and 300 mm IC Fabs for the deposition of polysilicon and Si3N4 films [2].
In general, the suitable processes implemented with vertical diffusion furnaces are
oxidation processes including dry oxidation, pyrogenic oxidation, dichloroethylene
(DCE) oxidation, and silicon oxynitride (SiON) oxidation, and as well as thin film
deposition processes such as CVD/LPCVD for silicon dioxide, polysilicon, silicon
nitride, and atomic layer deposition (ALD). In addition, metal (copper or aluminum)
annealing processes, metal alloying processes, heavily doping diffusion, and some
high temperature post-implantation annealing for well formation are also
implemented by vertical diffusion furnaces.
The primary technologies of the vertical diffusion furnace mainly consist of high-
precision temperature profile control, particle control, minimized oxygen level
control in mini-environment, system automation control, advanced process control,
and factory automation. The process temperature of the vertical diffusion furnace
normally ranges from 400  C to 1200  C, the temperature accuracy in the center of
the flat zone is 0.25  C even at a temperature of over1000  C where the flat zone
length ranges from 800 to 1000 mm. The ramp up rate of furnace is about 20  C/min
or less. In addition, the mean time between failures (MTBF) is no less than 1200 h,
and the mean time to repair (MTTR) is within 4 h.
66 Diffusion and Ion Implantation Equipment 1367

Vertical diffusion furnaces usually consist of wafer load assembly, stock units,
mini-environment horizontal laminar flow purification systems, automatic transfer
systems, thermal reaction chamber systems, gas boxes, automated control systems,
power supply systems, and other auxiliary assemblies for water cooling, exhaust,
and hazardous gas detection.
The external structure of the equipment adopts a side-by-side design which is a
popular arrangement in the industry. This structure enables the equipment to be
arranged horizontally without gaps between system units so as to shrink its footprint
and reduce the cost of ownership (COO) in the clean room. The system configuration
of a 300 mm vertical diffusion furnace is shown in Fig. 66.3.
The wafer handling assembly is the only mechanical interface between the
furnace and other equipment in the production line, in which it implements all
wafer loading and unloading through robots for process chamber in a vertical
furnace. The 300 mm wafer cassette uses a closed front open unified pod (FOUP),
while open wafer cassettes are used for wafers with a diameter of 200 mm or less.
The stock unit, also called as FOUP storage unit, is responsible for the temporary
storage of FOUPs inside this unit. It manages the wafer transfer among the FOUP,
the FOUP Door Opener (FDO) unit, and storage compartments through a manipu-
lator arm. The clean environment with an internal vertical laminar flow inside the
stock unit is maintained by fan filter units (FFU).

Fig. 66.3 Structural diagram of a vertical diffusion furnace (for 300 mm wafers)
1368 Z. Cheng et al.

The mini-environment system establishes an internal clean vertical laminar air-

flow to control the particle contamination through an ultra-low penetration air filter
(ULPA) and circulating fan units. High pure nitrogen purging system and oxygen
monitors are equipped to control the oxygen content and the pressure level in the
mini-environment.
The thermal treatment system is where wafers are heated for various heating
processes in the furnace. This system consists of a vertical quartz furnace tube which
surrounds wafers for the thermal processing, a heating element with multiple heat
zones, a heating jacket, a temperature control unit, a quartz tower also known as
quartz boat in vertical furnace, a quartz boat lifting unit, and associated components.
In addition, quartz wares have been replaced by SiC wares to reduce the flaking of
deposited films in advanced IC production lines.
The automatic transfer system consists of a FOUP transfer manipulator arm inside
the stock unit and a wafer transfer robot arm in the mini-environment. The FOUP
transfer manipulator arm handles wafers moving in/out from the FOUP to the stock
unit through the FDO assembly, and the wafer transfer robot arm implements wafers
loading and unloading from the FOUP to the quartz boat. The automation control
system includes system software (CTC/TMC/PMC systems) and a complete set of
system control assemblies based on IPC/PLC, as well as touch screen panels, a
remote control power cabinet, monitoring instruments, and peripheral I/O units.
Auxiliary assemblies mainly include exhaust systems, pressure control systems
(including pressure time index (PTI) or vacuum systems), hazardous gas monitors,
and water cooling systems.

Annealing Furnace

In semiconductor manufacturing, there are many processes, such as oxidation,

diffusion, epitaxy, ion implantation, CVD or PVD film growth, and metallization,
that require a specific subsequent annealing treatment after the main process step.
Annealing is normally implemented to repair crystal damages and activate dopants
for ion implantation, to densify dielectrics for CVD grown films, to reduce interface
density and fixed charge density for Si oxidation, to enlarge grain size for polycrys-
talline materials, and to reduce contact resistance for metallization [1, 2], etc. In
addition, H2 annealing at high temperatures for the gettering process is also applied
to form denuded zones for CZ grown silicon substrates.
Conventional furnace annealing, rapid thermal annealing, laser annealing, and
newly developed spike annealing are applied for various technology nodes in IC
production lines. Vertical furnaces and single-wafer annealing equipment generally
are adopted for large-size wafers (diameter  200 mm), while horizontal annealing
furnaces are still applied for small-size wafers (diameter < 200 mm). Annealing
equipment are the most common systems for IC manufacturing. A schematic
diagram of the horizontal annealing furnace is shown in Fig. 66.4, and the diagram
of functional blocks for a three-tube annealing furnace is also shown in Fig. 66.5.
66 Diffusion and Ion Implantation Equipment 1369

Fig. 66.4 Schematic diagram of the horizontal annealing furnace

Fig. 66.5 Diagram of functional blocks for a horizontal annealing furnace

The main technical parameters of annealing furnaces are as follows: the operating
temperature ranges from 500  C to 1280  C, the length of flat zone ranges from
600 mm to 1100 mm, the temperature accuracy in the center of flat zone is 0.5  C at
1000  C, the maximum controllable ramp up rate is 15  C/min, while the maximum
controllable ramp down rate is 5  C/min.
As shown in Fig. 66.5, the conventional horizontal annealing furnace is com-
posed of a furnace main body (including a heating unit, a heat exchanger, a
detoxifying cabinet, and a transformer assembly), a purification workbench, a
control cabinet, and a gas source cabinet. An industrial computer with strong anti-
magnetic, anti-vibration, and anti-interference capabilities is adopted for the
annealing furnace in harsh industrial environments. Each furnace tube has an
independent control unit to manage its individual operation.
1370 Z. Cheng et al.

High-Pressure Oxidation Furnace

The high-pressure oxidation furnace is a special oxidation furnace that provides

high-pressure oxidation gases, such as oxygen or water steam, into the process
chamber to enhance the oxidation rate. Usually, the pressure ranges from 10 to
25 atm (1 atm ¼ 101.325 kPa). Its main function is to increase the oxidation rate and
reduce the thermal budget. The high pressure oxidation process is suitable for the
growth of thick SiO2 film. Due to the safety concerns by the high pressure, it is
necessary to install a stainless steel jacket for the quartz tube chamber.
According to the Grove-Deal model [3], the oxidation rate of silicon is
determined by both the oxidants’ diffusion in the grown SiO2 layer and the
chemical reaction of oxidants with silicon at SiO2/Si interface. For thick oxide
growth, the oxidation rate of silicon is mainly dominated by the physical diffu-
sion mechanism, that is, the concentration of oxidants, thermal diffusion coeffi-
cient of oxidants, the temperature, and the solid solubility of oxidants in grown
oxide layer are the main factors to control the oxide film growth. In which, the
solid solubility of oxidants in oxide through Henry’s law and the ideal gas law [4]
is proportional to the partial pressure of the oxidants in the oxidizing gas.
Therefore, to increase the oxidant pressure in the process chamber can raise the
solid solubility of oxidants inside SiO2, the diffusion-related parabolic rate
constant, and the chemical reaction-related linear rate constant to achieve higher
oxidation rate. Zeto et al. [5] and Katz et al. [6] have described various high
pressure oxidation systems. High-pressure oxidation process provides a tech-
nique to grow thermal SiO2 at lower temperatures and at higher oxidation rates
compared with the conventional oxidation at the atmospheric pressure. For thick
SiO2 layers, such as field oxides or LOCOS, high-pressure oxidation can reduce
the oxidation time at the same oxidation temperature, or reduce oxidation tem-
peratures at the same oxidation time to achieve the required SiO2 thickness. In
general, to increase the pressure by one atmosphere can reduce oxidation tem-
perature by 30  C. Therefore, this method can effectively control the thermal
budget and so as to conform with the trend toward lower temperature processing
which required to suppress the dopant redistribution and maintain the shallow
junction depth for advanced IC devices. Furthermore, regular high temperature
(above 1000  C) oxidation may generate stacking faults in silicon and degrade
the device performance. With the high pressure oxidation at lower temperatures,
the length and density of oxidation-induced stacking faults can be significantly
reduced.
High-pressure oxidation technique brings safety problems and system pollution
issues. In recent years, due to the maturity and diversification of oxidation processes
(such as dry-oxygen oxidation, water vapor oxidation, and wet-oxygen oxidation),
the applications of high-pressure oxidation processes are no longer popular in
advanced IC production lines. A schematic diagram of a high-pressure oxidation
furnace is shown in Fig. 66.6.
66 Diffusion and Ion Implantation Equipment 1371

Fig. 66.6 Schematic diagram of a high-pressure oxidation furnace

Medium-Current Ion Implanter

As mentioned, the ion implanter is the most important doping equipment in

advanced IC manufacturing processes. Compared with the conventional thermal
diffusion process, ion implantation technology performs better dose uniformity
and reproducibility, better thermal budget control, and less dopant redistribution.
In addition, it is a non-thermal equilibrium process so as to introduce the dopant
concentration over the solid solubility to form mixed materials. At present, many
critical doping processes in advanced IC fabrication are implemented by ion implan-
tation technology only, such as ultra-shallow junctions, retrograde wells, smart-cut
Silicon on Insulator (SOI), SIMOX, etc. Ion implantation improves the performance
of IC products while reducing the cost and power consumption in fabrication.
The dose of implantation is expressed as:

tI
D¼
qS

where D is the implantation dose (number of ions per unit area), t is the time required
for the implantation, I is the beam current (mA), q is the unit charge (1.6
1019
coulombs), and S is the implanted area.
Main types of ion implanters for applications in IC fabrication are medium-
current ion implanters (MCI), high-current ion implanters (HCI) (including high-
current ion implanters and super-high current ion implanters), and high energy ion
implanters (HEI). While the dose range for MCI is in the range of 1010–1014/cm2, the
HCI can extend the dose range to 1016/cm2 regime. The ion energy of medium-
current ion implanters ranges from several KeV to about 1 MeV, where the maxi-
mum energy of a single charged ion is about 300 keV, and for multiple charged ions,
higher ion energy can be achieved. The average beam current of MCI is in the range
of 1–5 mA for single charged ions, and less than 1 mA for multiple charged ions. The
ion beam is generated in a Bernas type source [7] or an indirectly heated cathode
source. Medium-current ion implanters can be applied in IC manufacturing pro-
cesses, such as channel formation in depletion mode MOSFETs, n-well and p-well
1372 Z. Cheng et al.

Table 66.1 Technical parameters of medium-beam implanters (Refer from Zhongkexin’s

medium-beam ion implanters)
Parameters Specifications
Wafer diameter 300 mm
Applicable process 90–28 nm
Implantation energy 2–900 keV
Implantation angle 45
Implantation angle accuracy 0.1
Beam parallelism error 0.1
Implantation dose repeatability σ  1% (energy  5 keV), σ  0.5% (energy > 5 keV)
Implantation dose uniformity σ  1% (energy  5 keV), σ  0.5% (energy > 5 keV)

Fig. 66.7 Image of a medium-current ion implanter

formation in CMOS, buried layer formation of Bipolar Junction Transistor (BJT),

anti-punch through implantation, threshold voltage adjustment, channel stop implan-
tation, lightly doped source/drain (LDD) extension, etc. The basic technical param-
eters of medium-current ion implanters are shown in Table 66.1. An image of a
medium-current ion implanter is also shown in Fig. 66.7.
A medium-current ion implanter generally consists of an ion source, an analyzer,
an accelerating tube, a parallel lens, and a process chamber, as shown in Fig. 66.8.

1. Ion source: This unit produces ions which are extracted from the source by the
extraction lens assembly, in which this assembly can provide a certain initial
energy for ions.
2. Analyzer: The extracted ion beam consists of different ions with individual mass.
It is necessary to separate the desired ion from the remaining ions prior to the
implantation step. The mass analyzer acts as an ion filter which combined the
analyzing magnet with an adjustable resolving aperture for the mass resolution
66 Diffusion and Ion Implantation Equipment 1373

Fig. 66.8 Structural diagram of a medium current ion implanter

and optimum beam current. The ions entering this analyzer chamber typically
have the same energy, and the radii of the circular orbital trajectories for different
ions are proportional to the square root of the ion mass. Therefore, only desired
dopant ions can transmit through the aperture to form the beam line while
unwanted ions are rejected.
3. Accelerating tube: This unit generates a longitudinal electric field to accelerate or
decelerate the selected ions, and so as to adjust the ion energy to the required
level.
4. Parallel lens: The lens deflects and focuses a divergent beam to form a nearly
parallel ion beam.
5. Process chamber: The beam of ionized dopant atoms reaches the substrate surface
within the process chamber which is also named as target chamber. Process
chambers of implanters are equipped with wafer transfer module, wafer carrier
module, beam scanning module, wafer cooling controller, charge neutralization
assembly, vacuum system, in situ diagnostic instruments for beam
characteristics, etc.

High-Current Ion Implanter

The junction depth and the dopant profile are essential parameters to semiconductor
devices. As mentioned, the junction depth is determined by ion energy, and the
dopant dose is mainly determined by ion beam current. A major trend for high
current implanters is the increase of beam current toward lower energies for ultra-
shallow junctions. Compared to the medium-current ion implanter, the high-current
ion implanter can provide higher beam currents to reduce the process time and avoid
the carbonization of photoresist. Its ion energy ranges from 100 eV to tens of keV.
The beam current is at the mA level for low energy ion beams and can reach more
1374 Z. Cheng et al.

than 30 mA for high energy ion beams. Normally, high-current ion implanter is
performed to implement heavily doped shallow junctions, such as source/drain of
MOS devices, grid doping, and pre-amorphization implantation (PAI). At present,
high-current ion implanters play major roles in IC fabrication and own the highest
market share among all types of implanters.
Ion sources and extraction assemblies normally produce small sized beam spots
with rough Gaussian profiles of beam density. Presently, several scanning methods,
such as electrostatic deflection, magnetic deflection, mechanical deflection, and
spreading beams, are applied to spread dopants over the whole wafer surface.
However, Gaussian beam spots with obvious edge effects and ripple effects during
the scanning usually affect the dopant uniformity in deep submicron devices.
Especially for high current beams with low energy, the divergency of beam spots
produces significant nonuniformity in dopant profiles. With designed beam optics,
Diamond Inc. [8] developed a technology to spread beam out to form a highly
uniform ribbon beam of about 25 cm length. It is an evolutionary improvement for
high-current implanters. At present, the ribbon beam and the spot beam are main
types used in high-current implanters. Additionally, both the horizontal ribbon beam
design and vertical ribbon beam are available, and the horizontal ribbon beam with a
vertical mechanical scan of a single wafer is the mainstream design. Compared with
the conventional diffusion process, ion implantation technology demonstrates better
uniformity in dopant profiles. The characterization of dopant uniformity is
implemented by measuring the standard deviation of the sheet resistance on the
implanted substrate. The formula used to calculate the standard deviation is

n
2
Ri  R
i¼1
σ¼
ð n  1Þ

where Ri and R are the sheet resistance and average sheet resistance at different
points, respectively, and n is the number of measurements.
The beam uniformity and the transmission of ions are main technical issues for
high-current ion implanters. When using a high beam current, the space-charge
effect leads to a severe beam divergence and increases the ion loss in transmission
[9], particularly in low-energy situations. Therefore, the beam line design should be
as short as possible for the maximum beam transfer and the optimal focusing. By
adopting the ribbon beam scanning technology with an additional specially designed
deceleration unit can effectively improve the beam intensity and the beam uniformity
in the ultra-low energy regime. The technical parameters of high-current ion
implanters are shown in Table 66.2.
The basic structure of a high-current ion implanter is shown in Fig. 66.9. In a
high-current ion implanter, a ribbon beam shaped ion source with a suitable extrac-
tion electrode technology can generate a uniform ribbon beam current. With the ion
beam transmission assembly, the transfer rations of the beam current from the source
to the wafer can be efficiently increased over 80% so far. Furthermore, the trans-
mission efficiency of low-energy ion beams for ultra-shallow junction formation can
66 Diffusion and Ion Implantation Equipment 1375

Table 66.2 Technical parameters of high-current implanters (Refer to Zhongkexin’s high-current

ion implanters)
Parameters Specification
Wafer diameter 300 mm
Applicable process 22–45 nm
Implantation energy 0.1–60 keV
Implantation dose 2
1012 ~ 2
1017 ion/cm2
Energy accuracy <0.1%
Energy contamination <0.05%
Implantation dose reproducibility σ  1% (energy  10 keV), σ  0.7% (energy > 10 keV)
Parameters Specification
Implantation dose uniformity σ  15% (energy  10 keV), σ  1% (energy > 10 keV)
Beam parallelism error   1 (energy  1 keV),  0.5 (energy > 1 keV)

Fig. 66.9 Basic structure of a high-current ion implanter

be improved with equipping a decelerator, and the energy contamination can be

eliminated by electrostatic deflection. The three-dimensional angle parameters of the
ion beam can be detected and controlled to achieve a more fully parallel beam. In
addition, the beam size can be adjusted by means of focusing lenses for more
applications.

High-Energy Ion Implanter

At present, a high-energy ion implanter is capable of providing single-charged ions

with the energy more than 1 MeV and higher energy near to 3 MeV for multi-charged
ions. In high-energy ion implanters, ion acceleration can be achieved by either RF
linear accelerator or DC tandem accelerator technology. DC acceleration is a
1376 Z. Cheng et al.

Fig. 66.10 Basic structure of a high-energy ion implanter

conventional technology used in most high-current and medium-current ion

implanters. This method has the advantage of less energy divergence (less energy
contamination), however, it is difficult to achieve a higher ion beam current. The RF
linear accelerator technology performs better stability and reliability compared with
the DC tandem accelerator technology. Therefore, high-energy ion implanters with
the RF linear acceleration design are currently dominant in the market, such as Eaton
NV-GSD/HE series. The basic structure of a high-energy ion implanter is shown in
Fig. 66.10.
High-energy ion implanters usually adopt the RF acceleration design in the high-
energy accelerating section. The RF acceleration unit of the high-energy ion
implanter is shown in Fig. 66.11. It is mainly composed of a resonator cavity, an
inductor, an electrode, and a quad lens to form an Resistance, Inductance, Capaci-
tance (RLC) circuit. Each terminal of the electrode is equipped with one grounded
quad lens which can focus ion beams. The electrode is connected with a 13.56 MHz
RF power supply. As the ion beam pocket enters to the gap prior to the accelerating
electrode, negative voltage biased electrode starts to pull ions into the electrode at an
accelerating voltage. While the ion beam is inside the electrode, it feels no electrical
field and continuously drifts to the exit terminal, then immediately the positive
voltage biased electrode starts to push the ion beam out further at an accelerating
voltage so as to form an accelerated ion beam pocket. With a linear sequence of
acceleration cavity design, these ion beam pockets are accelerated in each of the
cavities in a pull-push fashion to obtain an expected ion energy.
High-energy ion implanters perform wide applications in IC fabrication, such as
retrograde well, buried layer, and deep junction formation in logic/storage devices,
imaging devices, power devices, etc. In addition to completing deep projected range
implantation, high-energy implanters can also backup medium-current implanters to
implement some processes. The technical parameters of high-energy implanters are
shown in Table 66.3.
66 Diffusion and Ion Implantation Equipment 1377

Fig. 66.11 Schematic of RF

acceleration unit for high-
energy ion implanters

Table 66.3 Technical parameters of high-energy implanter (Refer from Zhongkexin Co.)
Parameters Specification
Wafer diameter 300 mm
Implantation energy 20 keV – 3 MeV
Implantation dose 1
1011 – 1
1014 ion/cm2
Reproducibility and uniformity of implantation σ  1% (dose: 1
1011 – 5
1011 ion/cm2)
dose σ  0.5% (dose: 5
1011–1
1014 ion/cm2)
1378 Z. Cheng et al.

Rapid Thermal Processing (RTP) System

The rapid thermal processing (RTP) system is a single-wafer heat treatment system
that can quickly ramp up the wafer temperature to the required process temperature
levels (200–1300  C) and also cool down the temperature rapidly. The temperature
ramp up/ramp down rate is generally in the range of 20  C/s to 250  C/s. In addition
to a variety of heating sources and a wide range of annealing times, RTP systems can
perform better surface temperature uniformity (mainly for large wafers) and excel-
lent thermal budget control to recover implantation induced crystal damages, espe-
cially for IC devices in nanometer scales. Cluster system with multiple chambers can
run different processes simultaneously, in which the cluster system can integrate
with the photochemical deposition chamber together, such as Photo-CVD, for low
temperature film deposition. In addition, RTP systems can convert and adjust
process gases flexibly, therefore, multi-stage heat treatment processes can be sequen-
tially completed in the same system [1, 2].
Rapid thermal annealing (RTA) system is the right equipment for post-
implantation annealing in advanced IC fabrication. After ion implantation, the
surface crystal structure of semiconductors is damaged by the ion bombardment.
Therefore, a high temperature process is required to repair the damaged crystal
structure and activate dopants to enhance the conductivity, meanwhile, also to
suppress the dopant diffusion. In general, the required temperature to repair lattice
defects is about 500  C, while the temperature to activate dopants is about 950  C.
Obviously, the RTA system can provide enough high temperature level to activate
implanted dopants and keep a suitable short heat treatment duration to suppress the
dopant redistribution, because the RTA system has advantages of a rapid temperature
raise/drop capability and the controllable short process duration. RTA is mainly
divided into the following four categories.

1. Spike annealing: This process is characterized by a rapid ramp up/ramp down in

temperature. In practical applications, the wafer temperature rises rapidly from a
stable standby temperature to a peak temperature and immediately drops after
reaching the peak temperature. It has been found that the activation energy of
annealing (about 5 eV) is higher than that of diffusion (3–4 eV), therefore, the
annealing process is faster than the diffusion process at the temperature over
1000  C. That is, spike annealing is suitable to maximize the dopant activation at
the peak temperature over 1000  C and minimize the redistribution of dopant by a
very short peak time (much less than 1 s) to meet the requirement of advanced IC
products. Spike annealing has demonstrated a good capability to repair
implantation-induced defects and led to better junction quality with lower leakage
current. Currently, spike annealing is widely used in ultra-shallow junction
processes for the technology node less than 65 nm.
The process parameters of spike annealing mainly include peak temperature,
peak residence time, temperature spread, and the resistivity of wafer. For peak
residence time, the shorter, the better. This parameter mainly depends on the
temperature ramp up/ramp down rate determined by the temperature control
66 Diffusion and Ion Implantation Equipment 1379

system. In addition, the selected process gas atmosphere in chamber sometimes

has a certain impact on the ramp profile of temperatures. For example, helium
with a higher diffusion coefficient can facilitate a uniform heat transfer on wafer
and then reduce the peak residence time. Therefore, helium is sometimes selected
to assist in heating and cooling.
2. Lamp annealing: Lamp annealing technology has been widely used in sub-0.1 μm
IC fabrication. As shown in Fig. 66.12, the tungsten-halogen lamp is used as a
heating element which can generate intensive heat flow for rapid thermal
annealing. The lamp array allows wafers to be uniformly heated by the infrared
radiation. Usually, temperature ramp rate is about 75–150  C/sec, thus the ramp
up time of a lamp RTP system to reach the required annealing temperatures of
1000–1150  C is less than 10 s, and the ramp down time is very short by turning
lamps off. For the technology node above 65 nm, the lamp array RTP system can
achieve the junction annealing with minimized dopant redistribution.
3. Laser annealing: For the 45 nm technology node, laser annealing is performed
instead of lamp RTP system. Such as the formation of nickel-silicon contacts for
post-45 nm LSI logic chips, it requires a rapid heating for wafers from 200  C to
over 1000  C in milliseconds. That is, a laser is applied to rapidly raise the surface
temperature of the Si wafer to its sub-melting point so as to highly activate
implanted dopants, and then cool down the wafer surface very quickly, in about
a tenth of a millisecond, to minimize the dopant redistribution because of the high
thermal conductivity of silicon. The advantages of laser annealing are that it is
capable of an extremely rapid ramp up in temperature, sensitive control, and no
filament heating requirement. Basically, there is no temperature hysteresis issue
or filament lifetime issue. However, from the technical point of view, laser
annealing still has problems with high leakage current and residual defects in
devices, so the laser annealing technology affects the device performance yet.
4. Flash annealing: Flash annealing is an annealing technology for applications of
ultra-shallow junctions, in which it uses high-intensity radiation to perform spike
annealing on a wafer at a specific preheating temperature of a range from 600  C
to 800  C. This high-intensity radiation performs a short pulsed illumination to
ramp up the wafer peak temperature reaching the desired annealing temperature
to achieve the dopant activation, and then the radiation is immediately turned off
to minimize the dopant redistribution.

The core technologies of RTP equipment mainly include the design of the
reaction chamber (including the heating source), temperature monitoring technol-
ogy, and temperature control technology. In RTP equipment, most of the heat is
transmitted to cover the wafer by means of radiation. The main radiant energy
sources currently used include tungsten halogen lamps, arc lamps, conventional
resistive heat sources (which are seldom used), lasers, and microwaves, in which
tungsten halogen lamps are the most commonly used heating elements because of
their low cost and long service lifetime. In addition, according to the process
performed, RTP reaction chambers can be divided into three types, namely, cold
wall, warm wall, and hot wall types.
1380 Z. Cheng et al.

Fig. 66.12 Basic structural diagram of the reaction chamber in an RTP system
66 Diffusion and Ion Implantation Equipment 1381

Lamp sets (the power of a single tungsten halogen lamp is 1–2 kW and that of an
arc lamp is tens of kW) are commonly used as the heating source in RTP system. The
design of lamp houses either in array shape shown in Fig. 66.12b or in honeycomb
structure shown in Fig. 66.12c significantly affects the temperature uniformity on
wafer surface [2]. Meanwhile, the reaction chamber design includes the size, the
shape, and the cooling form is also crucial to the performance of the heating system.
Because the wafer is circular and the interior of the reaction chamber is mostly
symmetrical (round shape or hexagonal shape), therefore, the arranged form of lamp
houses is usually in concentric circles. In addition, the lamp houses are divided into
several individual zones arranged by different radius, in which each individual zone
connects an adjustable power controller to optimize the radiation exposure for the
uniform temperature distribution across the wafer. In order to increase the heat
radiation efficiency and compensate the significant heat loss near the outer edge of
the wafer, usually, the lamp houses above outer edge of the wafer are closer to the
wafer than those above the inner area of the wafer.
The accuracy and uniformity of temperature across wafer in RTP system signif-
icantly affects the process yield. Typically, the temperature measurement in RTP
system relies on thermocouples and pyrometers. Thermocouple is a direct contact
sensor which is not suitable to measure the wafer temperature in an RTP system.
Instead, non-contact type sensors, such as pyrometers, usually are applied to monitor
the wafer temperature and feedback signals to adjust the heating power to achieve a
uniform process temperature across the wafer. Here, thermocouple can serve as a
reference to calibrate other temperature sensors, for example, pyrometers.
Heating sources, the arrangement of heating elements, chamber design, materials
applied for chamber and parts, power supply, position of pyrometers, feedback
circuit design, process gases, dissipation of heat flow, wafer sizes, etc., all are
main factors related to the temperature control technology. It is necessary to establish
an accurate mathematical model through lots of experimental data for the tempera-
ture control unit. With the modified simulation model and the continuous experi-
mental implementation, the optimal temperature control design will be achieved.
Figure 66.12 shows the basic structure of the reaction chamber in an RTP system.
RTP equipment gradually plays an important role in the field of advanced IC
fabrication. In addition to a large number of applications in RTA processes, RTP
equipment is also applied in rapid thermal oxidation (RTO), rapid thermal nitridation
(RTN), rapid thermal diffusion (RTD), rapid thermal chemical vapor deposition
(RTCVD), decoupled plasma nitridation (DPN), metal silicide formation, epitaxy,
and other processes, etc.

References
1. H. Xiao, Introduction to Semiconductor Manufacturing Technology (SPIE, 2012)
2. M. Quirk, J. Serda, Semiconductor Manufacturing Technology (Prentice-Hall, Inc, 2001)
3. B.E. Deal, A.S. Grove, J. Appl. Phys. 36, 3770 (1965)
4. A.S. Grove, Physics and Technology of Semiconductor Devices (Wiley, New York, 1967)
1382 Z. Cheng et al.

5. R.J. Zato, N.O. Korolkoff, S. Marshall, Solid State Technol. 22(7), 62 (1979)
6. L.E. Katz, B.F. Howells, L.A. Adda, T. Thompson, D. Carlson, Solid State Technol. 24(12),
87 (1981)
7. I. Chavet, R. Bernas, Nucl. Instrum. Methods 51, 77 (1967)
8. N.R. White, M. Sieradzki, S. Satoh, Nucl. Instrum. Methods B96, 445 (1995)
9. J.H. Feeman, Nucl. Instrum. Methods B74, 357 (1993)
Thin Film Growth Equipment
67
Yang Xia, Peijun Ding, Jinrong Zhao, Bin Yin, and Xiaoping Shi

Contents
Principles of Thin Film Growth and Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Physical Vapor Deposition (PVD) Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390
Chemical Vapor Deposition (CVD) and Epitaxy Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391
Vacuum Evaporator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393
Direct Current Physical Vapor Deposition (DCPVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396
Radio Frequency Physical Vapor Deposition (RFPVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
Magnetron Physical Vapor Deposition (Magnetron-PVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
Ionized Physical Vapor Deposition (Ionized-PVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
Atmospheric Pressure Chemical Vapor Deposition (APCVD) System . . . . . . . . . . . . . . . . . . . . . . . 1406
Low-Pressure Chemical Vapor Deposition (LPCVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Plasma-Enhanced Chemical Vapor Deposition (PECVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
High-Density Plasma Chemical Vapor Deposition (HDP-CVD) System . . . . . . . . . . . . . . . . . . . . . 1410
Metal Chemical Vapor Deposition (Metal-CVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
Atomic Layer Deposition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
Photo Chemical Vapor Deposition (Photo-CVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
Laser-Assisted Chemical Vapor Deposition (LA-CVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
Electron Cyclotron Resonance CVD (ECR-CVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
Metal Organic Chemical Vapor Deposition (MOCVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
Molecular Beam Epitaxy System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426
Vapor Phase Epitaxy (VPE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429
Liquid Phase Epitaxy (LPE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432
Chemical Beam Epitaxy (CBE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
Ion Beam Epitaxy (IBE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1435
Low-Energy Ion Beam Epitaxy (LE-IBE) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436

Y. Xia (*) · B. Yin

Institute of Microelectronics, Chinese Academy of Sciences (IME), Beijing, China
e-mail: xiayang@ime.ac.cn
P. Ding · J. Zhao · X. Shi
Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China
e-mail: peijun.ding@naura.com

© Publishing House of Electronics Industry 2024 1383

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_67
1384 Y. Xia et al.

Spin Coater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439

Abstract
Film growth equipment is one of the critical aspects in the manufacturing process
of integrated circuits. It directly affects the properties of thin film materials such
as consistency and dimensional accuracy. This section describes the basic prin-
ciples of film growth and equipment techniques, including physical vapor depo-
sition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD),
epitaxy system, and spin coater. The context presents a comprehensive and
in-depth introduction of the various subtechnology of mainstream principles
and an overview of the film growth equipment system as well.

Keywords
Thin film · Nanometer structure · High K · Low K · Deposition · Epitaxy · Sputter

Principles of Thin Film Growth and Equipment

The process to deposit a single-crystalline, or poly-crystalline, or amorphous sub-

stance on the substrate surface by either physical or chemical technology is called
thin film growth (or thin film deposition), which emerged in the 1960s and is one of
the critical processes of IC fabrication. It is also an important technical foundation
for electronic, information, sensor, optic, solar energy, and other technologies.
Based on different deposition mechanisms, thin film deposition in IC fabrication
can be divided into physical vapor deposition (PVD), chemical vapor deposition
(CVD), and epitaxy. Table 67.1 classifies different film deposition methods.

Table 67.1 Classification of film preparation methods

Physical process Chemical process
Chemical vapor Atomic layer
Sputtering Evaporation deposition (CVD) deposition (ALD) Epitaxy process
DCPVD Vacuum APCVD Atomic layer Molecular beam
RFPVD evaporation LPCVD deposition (ALD) epitaxy (MBE)
Magnetron PVD Electron beam PECVD Vapor phase
Ionized PVD evaporation MCVD epitaxy (VPE)
Photon CVD Liquid phase
Laser-enhanced CVD epitaxy (LPE)
ECR-CVD Chemical beam
epitaxy (CBE)
Ion beam epitaxy
(IBE)
Low energy IBE
(LEIBE)
MOCVD
67 Thin Film Growth Equipment 1385

In the micron-scale technology nodes, the configuration of CVD normally adopts

the multiwafer atmospheric pressure chemical vapor deposition (APCVD) technol-
ogy with a relatively simple equipment structure to implement the film growth. The
process pressure of APCVD system is about 1 atm. To assemble a conveyor belt in
the APCVD system, it can implement a continuous wafer transfer and a continuous
deposition process. With the increase in wafer sizes, the single-wafer processing
chamber has become dominant. To this end, Applied Materials first introduced the
150 mm single-wafer chamber equipment, that is P5000 CVD system, which has
been placed on permanent display in the American Museum of Natural History as an
epochal milestone. As the wafer size keeps increasing to 200 mm and 300 mm, IC
technology continuously keeps updating. In the submicron technology generation,
low-pressure chemical vapor deposition (LPCVD) systems have become the main-
stream equipment. A lower process pressure is applied to speed the reactant gas flow
in the reaction chamber, thereby improving the uniformity of the deposited film as
well as the capability of step coverage and gap-refilling. Meanwhile, plasma-
enhanced chemical vapor deposition (PECVD) technology has played an important
role in the development of IC technology up to the 90 nm node. Due to the effect of
the plasma, the chemical reaction temperature is significantly reduced, the purity of
the film is improved, and the film density is enhanced. CVD technology is applied
not only for the deposition of dielectric layers and semiconductor materials, but also
for various metal film deposition. Since the 65 nm technology generation era, based
on silicon epitaxial technology, the selective SiGe epitaxy process has been used in
the raised S/D structures to improve the hole mobility of PMOS. In addition, new
high-k gate dielectrics and metal gate processes have been applied in 45 nm tech-
nology nodes to reduce the gate leakage current of MOS devices. And due to the
requirement of ultra-thin thickness for films in 22 nm nodes and below, atomic layer
deposition (ALD) process equipment has also been developed to meet the require-
ments for the ultra-thin film deposition with precise composition control and uniform
film thickness.
In the 150 mm wafer era, physical vapor deposition (PVD) equipment is domi-
nated by the single-wafer chamber configuration. From the perspective of IC tech-
nology development, the requirements for deposit films are more uniform and
denser, strong adhesion onto the substrate, and higher purity, therefore, the adoption
of sputtering equipment has gradually replaced that of vacuum evaporators. With the
development of IC technology generations, PVD equipment must be capable to
deposit a uniform flat film as well as to implement a better step coverage on vias and
trenches of certain aspect ratios. Thus, this development of thin film deposition
processes has required that the operational pressure of PVD chamber be reduced
from several millitorrs to the sub-millitorr range or increased to tens of millitorrs.
And with the long-throw design concept, the distance between the target material
and the wafer has also been significantly increased. These mentioned requirements
have been specified in the configuration of equipment development, such as mag-
netron PVD equipment, radio frequency (RF) PVD equipment, and ionized PVD
equipment, etc. In addition to DC power sources, magnetron PVD equipment also
assembles RF sources to reduce the incident particle energy, thereby reducing the
1386 Y. Xia et al.

device damage on wafer. The newly developed ionized PVD technology has been
widely applied in copper interconnection and metal gate deposition. This ionized
PVD equipment assembles an auxiliary magnetic field on the backside of target to
enhance the plasma density and the sputtering rate, an auxiliary RF power source
inside the chamber to convert metal atoms into metal ions, and a collimator to filter
scattered metal atoms and ions. In addition to the heating or cooling function, the
wafer susceptor connected to a negative bias RF power source can perform the
resputtering to eliminate overhangs and bottom thinning of high aspect ratio struc-
tures. These ionized PVD chambers also tend to combine with MCVD and ALD
chambers to implement the PVD film deposition and the CVD film growth in the
cluster system.
Table 67.2 lists the configurations and characteristics of the reaction chambers of
thin film deposition equipment (data in the table refer to normal process conditions).
Thin film growth has to take into account both the performance and the cost of
ownership for each deposition equipment. Table 67.3 lists the main evaluation
indicators for thin film deposition equipment, and Table 67.4 lists the processes in
which thin film growth equipment is adopted in IC manufacturing. In addition to the
field of IC manufacturing, thin film growth is also widely applied in advanced
packaging, LED manufacturing, MEMS manufacturing, etc.
Many new challenges have emerged in the process development of the thin film
deposition. Therefore, the development of the thin film deposition equipment will
mainly focus on the following directions in the future.

1. The emergence of various new materials promotes the requirements in the R&D
of new equipment and processes.
2. More stringent thermal budget control in device fabrication requires developing
much lower temperature processes for the thin film growth.
3. The emergence of more complex 3D structures in devices requires the deposition
equipment to provide better capability for film step coverage, void-free
gap-filling, and more precise film thickness control in thin film growth processes.
4. In order to control the characteristics of film interface so as to obtain a better
device performance, it requires a higher level of system integration to form a
cluster equipment which can completely implement a set of processes for one
application module. For example, to implement the PECVD SixNy or SixCyNz
deposition with a subsequential low-k dielectric deposition in a cluster thin film
equipment, the metal film deposition of Ti/TiN/Wseed/Wbulk structure for the
contactor metal of device in a PVD/CVD cluster equipment, the thin film etching
with a subsequential photoresist removal in a cluster etching equipment, etc.

In order to meet as mentioned requirements and challenges, manufacturers of thin

film deposition equipment need to continuously introduce or develop new technol-
ogies. These new developments include the introduction of new magnetic films for
new magnetic storage devices, as well as the introduction of MoS2 and WS2 and
other new substrate materials for new 2D devices. The deposition of these new
materials requires more R&D for new equipment and processes. Furthermore, in the
 67

Table 67.2 Configurations and characteristics of the reaction chambers of thin film deposition equipment
Equipment Reaction chamber Substrate
category Film growth source Film growth temp. Growth rate operational pressure holding method Plasma source
Vacuum Evaporation source High temp. growth 10–30 nm/min >103 Torr Suspended Thermal
evaporator (<1500
C) substrate heating evaporation or
holder electron beam
DCPVD Target materials High temp. or <1 μm/min 0.1–10 Torr Heating or DC source (cathode
equipment normal temp. cooling susceptor sputtering)
growth (<600
C)
RFPVD Target materials High temp. or <100 nm/min 0.01–10 Torr Heating, cooling, RF source
equipment normal temp. or RF susceptor (13.56 MHz,
Thin Film Growth Equipment

growth (<600
C) 20 MHz, and

60 MHz)
Magnetron Target materials High temp. or <1 μm/min 0.1–200 mTorr Heating, cooling, DC source
PVD normal temp. or RF susceptor
equipment growth (<600
C)
Ionized PVD Target materials High temp. or <100 nm/min 10–200 mTorr Cooling RF DC source and RF
equipment normal temp. susceptor source
growth (<600
C)
APCVD Precursor 550~1100
C 2–300 μm/h Atmospheric pressure Wafer boat None
equipment
LPCVD Precursor 350~1100
C 0.1–1 μm/h Low pressure, 0.1–10 Torr Wafer boat None
equipment
PECVD Gaseous precursor Low temp. growth <2 μm/min Atmospheric pressure or Heating RF Radio frequency
equipment (room temp. – low pressure, 760 Torr or susceptor or (100 kHz–40 MHz)
700
C) 0.05–5 Torr carrying boat
MCVD Metal inorganic Low temp. growth 4~350 nm/min 1–300 Torr Heating or RF Radio frequency
equipment compound precursor or (<550
C) susceptor (13.56–60 MHz)
metal organic
compound precursor
1387

(continued)
Table 67.2 (continued)
1388

Equipment Reaction chamber Substrate

category Film growth source Film growth temp. Growth rate operational pressure holding method Plasma source
ALD Halide or metal organic <500
C <0.3 nm per Atmospheric pressure: Heating or RF Radio frequency
equipment compound precursor deposition cycle 760 Torr susceptor (13.56–60 MHz)
Low pressure: 0.1–10 Torr
Photon CVD Gaseous precursor 100–300
C 2 nm/min~1 μm/min 0.1–50 Torr Heating susceptor None
equipment
LCVD Gaseous precursor 100–500
C 2 nm/min~100 μm/min 0.1–50 Torr Heating susceptor None
equipment
ECR-CVD Gaseous precursor Normal 20–1500 nm/min 104–101 Torr Heating susceptor Microwave
equipment temperature (2.45 GHz)
300
C
MOCVD Precursor 500–1100
C 1~2 μm/h Low pressure Heating susceptor None
equipment 1–100 Torr
MBE system Solid source or gaseous 500–900
C 0.1~2 μm/h Low pressure Heating susceptor None
source or liquid source 103–1011 Torr
VPE system Solid source or gaseous 550–1100
C 0.5~100 μm/h Atmospheric pressure Heating susceptor None
source or low pressure,
20–100 Torr
LPE system Liquid source or solid 400–500
C 0.1~10 μm/h – Heating base or None
source sliding boat
CBE system Precursor 500–900
C 0.1~2 μm/h Low pressure (<0.1 mTorr) Heating susceptor None
IBE system Solid source or gaseous 400–800
C 10 nm/min–1 μm/min 1010–107 Torr Heating susceptor DC
source
LEIBE Solid source or gaseous 150~900
C 10~500 nm/min 1010 ~ 107 Torr Heating substrate DC
system source susceptor
Spin-on Liquid source Normal Thickness: Normal pressure Normal None
temperature 10 nm~100 μm temperature
vacuum chuck
Y. Xia et al.

Note: 1 Torr ¼ 133.3224 Pa.

67 Thin Film Growth Equipment 1389

Table 67.3 Main evaluation indicators of thin film deposition equipment

Main indicators Notes
Growth rate The growth rate of the film directly affects the productivity of
equipment
Uniformity Includes various uniformities, such as film thickness
uniformity, film resistance uniformity, and so on
Step coverage Includes film coverage for the top, middle, and bottom (corners)
of trenches and vias
Dielectric properties (k value)/ Film (dielectric) insulation properties
leakage current
Work function Important parameter for metal films
Film stress control Includes stress control of single-layer film and multilayer film
Particle control Includes particle control during the wafer transfer and in
growing process
Reaction chamber cleaning The cleaning cycle and the cleaning duration of the reaction
cycle chamber will affect the production efficiency of equipment

Table 67.4 IC manufacturing processes implemented by thin film growth equipment

Device type Main process
Logic circuit Shallow trench isolation (STI), active region, spacer, etch stop layer, metal
gate, self-aligned silicide (salicide), contact, W-plug, Cu barrier and seed layer,
TiN hardmask, Al pad
Storage device String select (SSL) gate, ground select (GSL) gate, common source line/
memory cell (CSL/MC), STI, salicide, W-plug liner and barrier, W-plug, Cu
barrier and seed, TiN hardmask, Al pad
Advanced Through-silicon via deposition, under-bump metallization (UBM),
package redistribution layer (RDL), gold flip-chip bump, solder flip-chip bump, copper
pillar bump
LED AlN buffer layer, GaN light-emitting layer, ITO transparent electrode, silver
reflector, distributed Bragg reflector (DBR), barrier layer, passivation, pad
MEMS AlN buffer layer, piezoelectric layer, sacrificial Layer, insulating layer,
passivation, internal interconnect layer, electrode, active region
Power device Active region, metal electrode, silicide
Panel display T-gate insulating layer, active region, transparent conductive electrode

nanoscale era, many new nanostructures are subject to the stricter thermal budget
control in thin film growth (especially for some conventional films such as SiO2 and
Si3N4), which requires the R&D of new deposition processes (such as those involv-
ing new lower-temperature reaction precursors and recipes) or new growth technol-
ogies (such as plasma-enhanced technology or photo-radiation technology) to reduce
the growth temperature. The emergence of 3D device structures, such as 3D flash
memory and Fin-FETs, require that the surface morphology of films grown on 3D
devices shows a more precise thickness control and better step coverage. Therefore,
ALD technology will provide more applications in the field of these nanoscale 3D
devices in the future.
1390 Y. Xia et al.

Due to new device structures, a more serious challenge of thin film processes has
also emerged. Platforms of thin film deposition will require a higher level in the
system integration to well control the growth between different films. For example,
the deposition of a barrier layer of metal interconnection requires integrating several
different process chambers on the same platform, which presents a more stringent
challenge for the automation control of equipment platforms.
Thin film growth equipment is a high-tech product that combines the most
advanced technologies in a variety of scientific fields. Among various types of
production equipment for IC fabrication, it is relatively more complex, of higher
technical barriers, and frequent in use. An advanced film deposition system with
eight chambers for 300 mm wafers can cost upwards of ten million USD. At present,
the United States, Europe, and Japan are in the leading position in the field of thin
film deposition equipment. The main vendors include Applied Materials and Lam
Research in the United States, ASM in the Netherlands, and TEL in Japan. In recent
years, China has made great progress in this field. The PVD equipment series
independently developed by NAURA Technology Group Co., Ltd. have been
adopted in 28 nm production lines. NAURA’s PVD equipment for 14 nm processes
has entered the process evaluation stage, and PECVD equipment produced by
Piotech Co., Ltd. and NAURA is also adopted in chip and MEMS production
lines. At the same time, thin film deposition equipment produced by NAURA has
also been widely adopted in the advanced packaging, LED, and photovoltaic fields.

Physical Vapor Deposition (PVD) Equipment

Physical vapor deposition (PVD) is a technology by which atoms are transferred

from a source material to the substrate surface by thermal evaporation or sputtering
processes. This is performed using particle bombardment and other physical pro-
cesses, thereby depositing the material to form a film on the surface of the substrate.
PVD can be divided into two types: vacuum evaporation and sputtering.
At the beginning of the development of thin film deposition technology, thermal
evaporation in vacuum was dominant. The principle is to heat the source materials in
a vacuum environment, thereby causing atoms or molecules to escape from the
source material and form a vapor stream. The atoms or molecules in the vapor stream
are then transported to the substrate surface and condense into a solid deposited film.
Thermal evaporation in vacuum is a simple and easily operated process which can
provide the deposited film with high purity, such as aluminum films (Tm: 660
C).
However, for some high-melting temperature materials, such as refractory metals
and oxide materials, electron-beam (E-beam) evaporation method was developed
instead of thermal evaporation method. E-beam evaporation method utilizes accel-
erated electron bombardment to vaporize coating materials to implement the film
deposition on the substrate surface.
For large size wafers in IC fabrication, sputtering technologies are main methods
for the film deposition, in which energetic ions, such as Ar+, impact the target
electrode to dislodge the target surface atoms out and then redeposit them on the
67 Thin Film Growth Equipment 1391

substrate surface to achieve the film deposition. The conventional direct current
physical vapor deposition (DCPVD) method can only be applied for the conductive
targets, while radio frequency physical vapor deposition (RFPVD) can implement
the sputtering of insulating materials. In addition, magnetron PVD is a process to
obtain a better uniformity of deposited films, in which a magnet is installed on the
back side of the target to increase the plasma density at low pressure and enhance
more sputtering on the target material at lower substrate temperature. In order to
improve the step coverage of high aspect ratio topographies, ionized metal plasma
systems have been developed. On the basis of the magnetron sputtering system, an
RF coil is added to ionize sputtered metal atoms to form positive metal ions through
the inductive coupling mechanism, and also a lower bias voltage is added inside the
chamber to orient the metal ions impact the negatively charged wafer surface in a
vertical direction. This ionized PVD equipment is also called as an ionized metal
plasma system which has been applied for copper metallization processes, such as
Ti, TiN, and Cu seed layers. Currently, ionized PVD is widely used in the back-end
interconnection process of advanced IC fabrication.
Metal films are mainly used in the metal interconnection of devices. With the
development of technology, the preparation process of metal films changes very
quickly. With the development of metallization processes, from the early magnetron
PVD to the ionized PVD with better trench-filling ability, and then to the thin metal
film deposition by chemical vapor deposition (CVD) and further atomic layer
deposition (ALD), the step coverage capability and electrical characteristics of thin
metal layers have been significantly improved. To further reduce the RC time delay
of the interconnection, dual damascene Cu metallization is used to replace Al as the
metal interconnection process starting from the 130 nm technology node. The
formation of a continuous Cu seed layer by the PVD step and the subsequent
CVD step has become a standard Cu seed deposition process. Meanwhile, for
W-CVD contact process, a PVD step with a subsequent CVD step is also applied
to form a continuous TiN barrier layer. That is, PVD still plays a major role in
metallization processes.

Chemical Vapor Deposition (CVD) and Epitaxy Equipment

Chemical vapor deposition (CVD) is the process of depositing a thin film on a

substrate surface by mixing chemical gases to cause a chemical reaction. The depos-
ited materials used for the IC fabrication include metal materials (W, TiN, and Co),
dielectric materials (SiO2, Si3N4, phosphorus-doped silica, and boron-doped phospho-
rus-silica), and semiconductor materials (polysilicon and amorphous silicon).
In the main process of the CVD reaction, reactive chemicals flow from the inlet
region of the reactor to the process chamber under the traction of the carrier gas. In
the process chamber, these reactive chemicals react or decompose to form chemi-
cally active precursors which diffuse to the substrate surface, where they are
adsorbed and combined with the nucleation sites on the substrate surface. A chem-
ical reaction then occurs on the substrate surface to complete the growth of the film.
1392 Y. Xia et al.

The surface migration of adsorbed reactive precursors often occurs on the substrate
surface. The existence of the surface migration phenomenon generally results in a
better step coverage in the CVD process. Unreacted reactants and by-products
(formed from surface chemical reactions) flow with the gas stream to the outlet of
the reaction chamber and are discharged.
CVD can be divided into multiple types, including thermal CVD, plasma-
enhanced CVD (PECVD), photon CVD, laser-enhanced CVD, electron cyclotron
resonance CVD (ECR-CVD), and metal organic CVD (MOCVD), depending on the
method used to activate the reactants. Thermal CVD can be further divided into
atmospheric-pressure CVD (APCVD), low-pressure CVD (LPCVD), and metal
CVD (MCVD).
Atomic layer deposition (ALD) is a thin film deposition technology that has
developed rapidly in recent years. Unlike the reaction mechanism of continuous
growth in CVD, ALD carries out the cyclical thin film deposition by periodically
introducing reactive precursors into the reaction chamber. The thickness of the
film grown in the ALD in each cycle is constant, enabling very precise film
thickness control and superior step coverage. Depending on the reaction mech-
anism, ALD can be divided into thermal ALD and plasma-assisted ALD. As
device integration technology advances, ALD will become more widely used in
device processes.
Epitaxy is the process of growing a single-crystalline film on a single-crystalline
substrate such as a wafer. The crystal orientation of the epitaxial film follows that of
the substrate. Depending on the epitaxial growth materials used, epitaxy can be
divided into homoepitaxy and heteroepitaxy. Homoepitaxy means that the grown
epitaxial layer and the substrate are the same materials. Heteroepitaxy means that
the epitaxially grown film material is different from the substrate material, such as in
SOS technology (in which silicon is grown on sapphire or spinel). In terms of epitaxial
growth technologies, epitaxy can be divided into physical epitaxy technology and
chemical epitaxy technology. Molecular beam epitaxy (MBE) is a physical epitaxy
technology. In physical epitaxy technologies, the reaction source is usually a pure solid
source, which is evaporated to a gas by heating, and is then transported to the surface
of the substrate to complete epitaxial growth. The reaction source does not undergo a
chemical reaction throughout this process. Chemical epitaxy technology refers to the
growth of an epitaxial single-crystalline film by means of the chemical reaction of
reactive precursors in the epitaxy process. Chemical epitaxy can be divided into three
types, namely, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), and solid phase
epitaxy (SPE). VPE has good film thickness control capability, low impurity concen-
tration, and high crystal integrity, and is widely used in silicon processes. In a broad
sense, chemical epitaxy can be classified as a type of CVD.
In CMOS semiconductor integrated circuit processes, one of the main applica-
tions of insulating dielectrics is to fabricate the gate dielectric layer of MOS devices.
The gate dielectric materials for CMOS processes with the technology node above
45 nm, SiO2 is used as a CMOS gate dielectric material. As CMOS devices continue
to shrink, high-k dielectric materials have been introduced to replace conventional
SiO2 materials in order to effectively suppress short channel effects, improve gate
67 Thin Film Growth Equipment 1393

electrode capacitance, and reduce gate leakage current in the 45 nm technology

generation. Currently, high-k dielectric materials based on the oxides of Hafnium are
preferred. The preparation process of high-k materials is usually completed using
ALD equipment.
Another major application of insulating materials is the filling of gaps and
trenches to achieve the device isolation. With the development of integrated circuits,
continuous innovations have been made in filling materials and preparation pro-
cesses. Processes have evolved from PECVD, which was used in technology
generations greater than 0.8 μm, through high-density plasma (HDP) CVD used in
90 nm processes and high aspect ratio processes at 65 nm, to flowable CVD (FCVD)
that may be used in the sub-10 nm technology generation. FCVD enables bottom-up
filling to realize dense and carbon-free dielectric thin film growth. In the field of
back-end metal interconnection, dielectric films have also evolved from the original
SiO2 to low-k insulating materials (k  3.2) and ultra-low-k materials (k  2.5) that
can reduce the RC delay with a lower k constant.
In CMOS processes, semiconductor materials such as polysilicon are commonly
used to prepare gate electrodes. Polysilicon was usually prepared by LPCVD equipment
for technology generations of 90 nm or above. In the 90 nm to 65 nm technology
generation, rapid thermal CVD (RTCVD) was developed to improve the process
integration of the gate stack. For process technology of 45 nm and below, the Fermi-
level pinning effect and the polysilicon depletion effect (DE) are avoided by adopting a
high-k material for the gate dielectric and using metal gate electrodes instead of
polysilicon. Metal gate electrodes are also typically fabricated using ALD technology.
For CMOS technology generations below 65 nm, local stress processes in the
source and drain regions can increase transistor speed. This technology is achieved
by embedding a SiGe strained epitaxial layer in the source/drain regions of the
PMOS transistor. Due to the mismatch between the Si and SiGe lattice constants,
when epitaxy technology is adopted to introduce the SiGe epitaxial layer into the
source/drain regions of the PMOS device, a compressive stress is generated in the
device channel region, thereby improving the mobility of holes.
This allows the PMOS to increase its saturation current while maintaining the
same device size, thereby increasing the response speed of the device.

Vacuum Evaporator

Vacuum evaporation is a coating method by which a solid material is heated to be

vaporized or sublimated in a vacuum chamber, and then is deposited on the substrate
surface to form a required film.
Figure 67.1 shows a diagram of a typical vacuum evaporator. The equipment
usually consists of a vacuum system, an evaporation chamber, and a heating unit.
The vacuum system consists of a vacuum piping, vacuum gauges, valves, and a
vacuum pump. Its main function is to provide a required vacuum pressure for the
evaporation. The evaporation chamber consists of an evaporation platform with a
crucible, source heating element and substrate heater, and thermocouples for
1394 Y. Xia et al.

Fig. 67.1 Diagram of a

typical vacuum evaporator

temperature monitoring. The target material to be evaporated (such as Au, Ag or Al

with low-melting points) is placed in the crucible of the evaporation platform. In
order to provide a uniform vapor flux to control the film thickness, a closed loop
feedback design combining the power supply and the temperature monitoring is
embedded in the source heating element to assure a stable temperature during the
evaporation. As shown in Fig. 67.1, the substrate is clamped on the susceptor which
is assembled with a controllable heater to adjust the substrate temperature. Higher
substrate temperature can enhance the migration of deposited atoms on substrate
surface so as to obtain a smoother film surface with a more uniform thickness.
To maintain a stable vacuum pressure during the evaporation process is very
important. The vacuum condition affects the evaporation rate and the quality of the
film formation. Higher chamber pressure will decrease the mean free path of vaporized
atoms or molecules due to the severe collision between vaporized substances and the
background residual gases. Furthermore, some unexpected reaction between them
may form different compounds in the film. Then, not only the film deposition rate is
decreased, but also the film quality is degraded. In case of the external air leakage in
the deposition chamber, extra oxygen-induced oxides and nitrogen-induced nitrides
will seriously damage the film quality. Therefore, the in situ pressure monitoring and
the leak detection assembly unit are necessary for the evaporation system.
For larger diameter substrates, the conventional design of deposition chamber
performed the poor uniformity in film thickness. In order to improve this drawback,
to apply the long-throw concept to increase the distance between the target source
and the wafer susceptor, and also to add a susceptor rotation function, the film
thickness uniformity is significantly improved. However, both the deposition rate
67 Thin Film Growth Equipment 1395

and the purity of films are sacrificed due to a longer vacuum space. In addition, the
utilization efficiency of the evaporation material is reduced either.
Although the vacuum evaporator has several advantages, such as simple struc-
ture, easy operation, and low cost of ownership, it is incapable of evaporating some
refractory metals (e.g., Mo and Ti) and oxide materials (e.g., SiO2). Thus, electron
beam evaporation technology has been developed for substances of high-melting
temperature, in which an electron beam is adopted as a heating source. This method
uses a high-voltage electron beam (usually produced by an electron gun) to bombard
the material to be evaporated. The electrical energy of electrons is transferred to heat
up and evaporate these high-melting point substances to form vapors, which effuse
on the substrate surface to achieve the film deposition. A schematic of an electron
beam evaporator is shown in Fig. 67.2.
Electron gun evaporation is a relatively simple process, in which the electron gun
acts as a hot cathode and the crucible is grounding as an anode. As shown in
Fig. 67.2, the electron beam generated by the electron gun is accelerated by the
electric field force, which provides electrons a relatively high enough kinetic energy,
then this energetic electron beam continuously bombards the material to be evapo-
rated in the crucible. The kinetic energy of electrons is converted into the thermal
energy to melt and vaporize the material in the crucible to form a vapor flux. This
vapor flux effuses to the substrate and performs the film deposition. The evaporation
rate of materials depends on both the melting temperature of materials and the power

Fig. 67.2 Schematic of an electron beam evaporator

1396 Y. Xia et al.

of electron beam. For materials of high-melting temperature, it is necessary to

increase the electron beam power to achieve an acceptable film deposition rate.
The electron beam heating assembly can provide extremely high densities of energy
to raise the temperatures as high as 3000–6000
C, thereby enabling to evaporate
refractory metals or compounds. So far, W, Mo, Ge, SiO2, Al2O3, and some other
materials have been successfully evaporated for high-purity film deposition by the
electron gun evaporation technology. The main disadvantages of this technology are
as follows; (1) the electron beam bombardment generated high-energy ions may
cause substrate damages, (2) this technology is not suitable for the deposition of
compounds, and (3) the generated X-rays are harmful.
At present, electron beam evaporation is mainly applied in the electrode fabrica-
tion of LEDs, as well as other discrete devices and components. So far electron beam
equipment is no longer used for thin film deposition in the main IC production fields.

Direct Current Physical Vapor Deposition (DCPVD) System

Direct Current Physical Vapor Deposition (DCPVD) is also referred to as the

cathodic sputtering or the vacuum DC two-stage sputtering. The target material of
the vacuum DC sputtering serves as a cathode and the substrate serves as an anode.
The plasma for the sputtering in vacuum is formed by ionizing the process gas, such
as argon ions Ar+, etc. These charged ions in the plasma are accelerated by the
applied DC power supply and then bombard the target surface to dislodge atoms out
from the target material. Thereafter, these sputtered atoms with a certain kinetic
energy then move toward the substrate to form a film on the substrate surface. That is
the deposition mechanism of DCPVD, as shown in Fig. 67.3. The gas applied for
sputtering is generally a rare gas, such as argon, so as not to contaminate or react
with the deposited thin film. Due to the atomic radius and the atomic weight of
argon, a higher sputtering effect can be achieved through the better impact energy
transfer by Ar+ ions, therefore, argon is the primary sputtering gas in most of PVD
equipment. The schematic diagram of a DCPVD equipment is shown in Fig. 67.3.
In order to avoid the charge accumulation on the target surface, the target
materials adopted in DCPVD equipment are conductive targets, such as Al, Ti,
Co, etc., because the positive charges carried by bombarded argon ions can be
annihilated immediately through the negative biased conductive target. Therefore,
the sputtering process can keep implementing. Conversely, if the target material is an
insulator, the charge accumulation on target material will terminate the sputtering
process immediately and even damage the power supply. Therefore, in order to
enable the sputtering of insulating materials, Radio frequency (RF) physical vapor
sputtering (RFPVD) technology is developed to implement the sputtering process
for both conductive and nonconductive target materials.
One of the main disadvantages of DCPVD technology is that the ignition voltage
is too high so as to enhance the electron bombardment on the substrate seriously.
Then an effective way to solve this energetic electron bombardment-induced damage
in devices is to apply the magnetron PVD technology. Lately, based on the
67 Thin Film Growth Equipment 1397

Fig. 67.3 Schematic of a DCPVD equipment

fundamental concept of DCPVD technology, many new PVD technologies are

developed for IC fabrication.

Radio Frequency Physical Vapor Deposition (RFPVD) System

RFPVD, which uses RF power as an excitation source, is a PVD technology that can
be applied to deposit a variety of metallic and nonmetallic materials.
Common RF power frequencies used in RFPVD are 13.56 MHz, 20 MHz, and
60 MHz, respectively. The RF power connecting the target alternates between
positive and negative cycles. When the PVD target is in the positive half-cycle of
the RF power supply, the surface of the target material is at a positive potential with
accumulated positive charges, meanwhile, electrons in the process chamber will
quickly drift to the target surface and neutralize these accumulated positive charges.
Electrons continuously accumulate on the target surface to form a negative potential
in this positive half-cycle. When the sputtering target material is turned into the
negative half-cycle of the RF power supply, positive ions start moving toward
the target and neutralize some electrons accumulated on the target surface in the
positive half-cycle. However, the electrons of light mass move much faster than
the positive ions of heavy mass in the RF electric field, therefore, the amount of
positive ions arriving at the target surface in the negative half-cycle are always less
than that of electrons accumulated on target in the positive half-cycle. Owing to the
1398 Y. Xia et al.

same duration of the positive and negative half-cycles, it results in a net amount of
negative charges accumulated on the target surface after a full cycle. Therefore, in
the first several cycles, a stable negative potential is formed on the target surface, and
it is independent of the properties of the target material itself. The mechanism of
negative potential formation on the target surface is very similar to the sheath layer
formation in capacitive-coupled plasma etching. This negative potential level on
either metal targets or on insulating targets is controlled by the RF power supply.
That is, the RF power supply directly controls the ion energy and the sputtering rate.
This RFPVD technology not only solves the problem of sputtering insulating targets,
but also is highly compatible with conventional metal targets. Figure 67.4 shows a
schematic of RFPVD equipment.
Compared to the DCPVD technology, the average target voltage of RFPVD
system is much lower and leads to a lower ion energy for sputtering, in which a
lower ion sputtering rate and a lower film deposition rate are performed. In addition,
the film structure, film characteristics, and sputtering process-induced device dam-
age are directly affected by the kinetic energy of deposited atoms or molecules.
Therefore, advantages of RFPVD technology include better film quality control and
less substrate damage. In order to enhance the sputtering rate to obtain a high-
deposition rate of films, a new configuration of PVD system equipped with DC and
RF power supplies simultaneously is developed. These two power supplies are
simultaneously loaded on the target without interfering with each other by means

Fig. 67.4 Schematic of an RFPVD equipment

67 Thin Film Growth Equipment 1399

of a coupler. With an optimal adjustment for these two power supplies, it is easier for
the RF power supply to enhance the plasma density, that is, the positive ion density is
increasingly generated, but the ion energy is just slightly increased, so as to increase
the deposition rate of films and reduce the device damage.
In early years, RFCVD technology was developed mainly for the deposition of
dielectric films. Compared with the RFPVD technology, CVD technology demon-
strates better capability to implement the conformal deposition for the step coverage;
therefore, most IC processes now have adopted CVD technology to grow insulating
dielectric materials. However, a new configuration for the deposition of ultra-thin
metal films is currently applied in advanced IC fabrication, that is, to combine the
merits of RFPVD technology with DC magnetron PVD technology can significantly
suppress the DCPVD-induced device damage, and also obtain a better control over
the thickness of the deposited ultra-thin film with the low deposition rate of RFPVD
technology. Therefore, the magnetron DCPVD/RFPVD technology is mostly
applied for the deposition of metal gates.

Magnetron Physical Vapor Deposition (Magnetron-PVD) System

Magnetron sputtering is a PVD technology in which a magnet is added on the back

side of the target. The added magnet forms a magnetron sputtering source with a DC
power supply (or AC power supply) system, in which this sputtering source is used
to form an interactive electromagnetic field in the chamber to confine the motion
range of energetic electrons in the plasma inside the chamber, and also create a spiral
trajectory path of electrons to generate more collisions between energetic electrons
and gaseous atoms or molecules (e.g., Argon or nitrogen). This, in turn, raises the
plasma concentration, ultimately achieving increased deposition rate. In addition,
because more electrons are confined near the target surface, the electron bombard-
ment on the substrate is reduced and the substrate temperature is also lowered. One
of the most obvious features of the magnetron PVD compared to the flat plate-type
DCPVD technology is that the ignition discharge voltage is lower and more stable.
Because of its higher plasma concentration and higher sputtering yield, it can
achieve excellent deposition efficiency, a greater range control over the deposition
thickness, and precise composition control, while using a low ignition voltage.
Therefore, magnetron sputtering technology is dominant in current metal thin film
PVD technology.
In the simplest magnetron source design, as shown in Fig. 67.5, a set of magnets
are placed on the backside of the planar target material (outside the sputtering
chamber) to create a local magnetic field parallel to the target surface closely, in
which energetic electrons are drifted by the Lorentz force to move along a spiral
trajectory near the target surface.
As a permanent magnet is fixedly mounted on the backside of the target plate, the
magnetic field distribution on the target surface is relatively localized. In which energetic
1400 Y. Xia et al.

Fig. 67.5 Design of a magnetron source

electrons also locally accumulate near these regions to generate a nonuniform plasma,
thereby, only some specific regions of the target material are sputtered. So, the utilization
of the target material is low and the deposited film is of poor uniformity. Furthermore,
according to a certain probability, some particles of the sputtered metal or other materials
are deposited back on the target surface, where they may agglomerate into clumps to
form defects and contaminants on target surface. Therefore, commercial magnetron
sources are usually designed with a rotatable magnet, as shown in Fig. 67.6b, thereby
improving the film uniformity, the utilization of target material, and the full target
sputtering. Balancing these three factors is very critical. If they are not balanced
appropriately, the sputtering process may only result in good film uniformity but
significantly reduce the utilization efficiency of target material (reduction in target
material lifetime), or it may fail to achieve a full target sputtering or a full target etching,
which can generate particle contamination problems during the sputtering process.
Figure 67.6 shows the scheme of a typical magnetron source design.
In magnetron PVD technology, it is necessary to consider the moving mechanism
of rotating magnet, the shape of the target material, the cooling system for the target
material, the magnetron source, etc. At the same time, it is also necessary to consider
the configuration of the substrate susceptor for wafer holding, such as the clamping of
the wafer and the substrate temperature control. In the PVD process, the wafer
temperature is suitably controlled to obtain the desired crystal structure, grain size,
and orientation, as well as the stable performance. Since the efficient heat transfer from
67 Thin Film Growth Equipment 1401

Fig. 67.6 Design of a magnetron source

the susceptor surface to the wafer backside requires a fully tight contact between them,
therefore, different kinds of wafer chucks are developed. The mechanical chuck,
which has advantages of simple structure and lack of sensitivity to the wafer, can
tightly clamp wafer and susceptor together to achieve a good heat transfer; however,
the wafer edge effect and the worse particle control generated by the mechanical chuck
are main negative issues in the IC fabrication. Therefore, the mechanical chuck has
gradually been replaced by the electrostatic chuck (ESC) for the wafer holding in
sputtering processes. For processes that are not very sensitive to temperatures, the
wafer can be placed on the substrate susceptor without chucking or edge clamping
(with no pressure difference between the upper and lower surfaces of the wafer).
During the PVD process, the surface of the chamber liner and components inside
the chamber will also be covered with deposited material. After several sputtering
cycles, the total thickness of these deposited material will exceed a certain limit
value, so as to generate cracking and peeling off of deposited material, then causing
particle contamination. Therefore, the surface treatment of the liner and other
components inside the chamber is very critical to extend their lifetime. Currently,
both surface sandblasting and aluminum spraying are common methods adopted to
increase the surface roughness and thereby enhance the adhesion of deposited
material on the liner surface.
The design requirements of magnetron DCPVD for off-angle sputtering are relatively
loose because the uniformity of film thickness is primarily dependent on the adjustment
of both the dip angle of sputtering and the rotation of wafer. The main disadvantages of
magnetron PVD are low-deposition rate and low step coverage capability for trenches
and vias, so it is mainly applied to the deposition of flat thin films.
Magnetron DCPVD is the most widely adopted deposition technology, especially
for the deposition of flat thin films, including the metal layer deposition of aluminum
interconnects in IC fabrication, but such applications are rarely adopted in copper
interconnects. Recently, the new application of the flat deposition with magnetron
DCPVD technology is applied again to deposit Titanium nitride hard masks in 28 nm
processes. Figure 67.7 shows a schematic of the design of a heart-shaped rotating
magnetron source. Table 67.5 lists typical magnetron PVD equipment and vendors.
1402 Y. Xia et al.

Fig. 67.7 Schematic of the

design of a heart-shaped
rotating magnetron source

Ionized Physical Vapor Deposition (Ionized-PVD) System

In the conventional PVD process, as shown in Fig. 67.8, due to the nearly
isotropic film deposition, overhang formation on the top corners and film thin-
ning at bottom corners in trench structures are unavoidable. As the feature size of
microelectronic technology continues to evolve to the nanoscale era, the step
coverage of metal films deposited on high aspect ratio through-holes (vias) and
narrow trenches by the conventional PVD equipment becomes much worse. Bad
conformity of metal films will degrade the reliability and the yield of IC devices.
So, it is an increasingly big challenge in the capability of conventional PVD to
reduce overhangs and bottom corner thinning, as the aspect ratio of the vias and
trenches increases.
67 Thin Film Growth Equipment 1403

Table 67.5 Typical magnetron PVD equipment

Equipment
Main producer model Main features
AMAT Endura Cluster system, can integrate various deposition
chambers for a variety of materials, single-wafer
process, can assemble with a heating or cooling
wafer susceptor; mainly used in integrated circuit
manufacturing, also used in metal or dielectric
coating processes for advanced packaging, power
devices, MEMS, and other fields
NAURA Polairs, Cluster system, can integrate various deposition
Flexer, and chambers for a variety of materials, single-wafer
exiTin process, can assemble with a heating or cooling
wafer susceptor; can be used in metal or dielectric
coating processes in integrated circuit
manufacturing, advanced packaging, LEDs, power
devices, micromechanics, and other fields
Beijing Tailong PVD-M Microcluster system, can integrate various
Electronic Technology deposition chambers for a variety of materials;
Co., Ltd. mainly used in integrated circuit manufacturing,
also used in metal or dielectric coating processes in
advanced packaging, power devices, MEMS, and
other fields

Fig. 67.8 Cross section of

typical step coverage over
time in high aspect ratio
contact holes

Thus, ionized PVD technology is developed to solve the step coverage problem.
It first uses various methods to ionize the sputtered metal atoms, and then controls
the direction and energy of the metal ions by adjusting the bias voltage applied to the
wafer, thereby obtaining a stable directional metal ion current for metal film depo-
sition. In this way, it significantly improves the step coverage of high aspect ratio
through-holes and the narrow trenches. Especially, the film thinning near bottom
corners is suppressed. A typical feature of the ionized metal plasma PVD system is
the extra equipped RF coils which implement the ionization of sputtered metal atoms
1404 Y. Xia et al.

Fig. 67.9 Schematic of ionized metal plasma technology

in the chamber, as shown in Fig. 67.9. As the deposition process is performing, a

relatively high operational pressure of the chamber is maintained (about five to ten
times the normal operational pressure). During the PVD step is performing, a second
plasma region is generated by the RF coils, and the concentration of Ar+ ions in this
plasma region increases with the increasing RF power and argon gas pressure. As the
sputtered metal atoms pass through this Argon plasma region, the collision between
metal atoms and Ar+ ions will convert most metal atoms to metal ions, that is the key
mechanism of ionized PVD technology. In addition, an RF bias source connected to
the wafer susceptor (such as an electrostatic chuck) can drive most positive metal
ions moving vertically to the bottom surface of vias and trenches. Furthermore, these
energetic metal ions can resputter not only the wafer surface to eliminate the
overhang formation near top corners, but also resputter bottom metal films to
cover thinning bottom corners. Therefore, a conformal metal thin film deposition
is achieved. The step coverage for high aspect ratio structures is highly improved by
the ionized PVD technology.
The main concept of ionized PVD technology is to obtain a high proportion of
metal ions and thereby form a directional metal ion flow to improve the step
coverage for high aspect ratio structures. Besides the as-mentioned method of adding
RF coils in the chamber to generate metal ions, another method named as self-
ionized plasma (SIP) technology is also developed for generating metal ions in
chamber. The main approaches include increasing the magnetic field strength,
increasing the DCPVD power, and reducing the operational pressure of the
67 Thin Film Growth Equipment 1405

Fig. 67.10 Schematic of the

SIP chamber

magnetron-PVD system. A schematic diagram of ionized PVD technology with the

self-ionized plasma (SIP) technology is shown in Fig. 67.10. It is mainly character-
ized by a strong magnetron source providing a higher magnetic field so as to increase
the ionization rate of metal atoms. The second feature is to adopt the long-throw
concept to increase the distance between the target and the wafer to enhance the film
deposition on bottom surfaces. And the third feature is to reduce the pressure lower
even to an ultra-high vacuum conditions to achieve the self-sputtering of metals
[1, 2] (e.g., self-sputtering of copper for seed layer) in the PVD process. This lower
pressure in PVD chamber can reduce the scattering probability among metal ions,
argon ions, and atoms, thereby ensuring a better step coverage for tiny through-holes
and narrow trenches of high aspect ratios.
Ionized PVD is a newly developed technology in the magnetron DCPVD system.
For example, the deposition process for the barrier layer and the ARC layer in
aluminum interconnects, the adhesion layer of W-plugs, as well as the barrier and
seed layers in copper interconnects are mainly achieved by ionized PVD. For IC
processes with high aspect ratio structures, such as vias and trenches in nanoscaled
devices, the ionized PVD technology has been applied to play a major role in the
metallization step. Furthermore, some ionized PVD systems are also equipped with
various metal CVD chambers to meet the advanced process requirements, such as
the deposition of Ti adhesion layers in titanium ion PVD chamber and TiN barrier
layers in titanium nitride CVD chamber in the formation of high aspect ratio
W-plugs. The configuration of various chambers in a cluster system to implement
a variety of processes is the main trend in equipment development. Table 67.6 lists
main available ionized PVD systems.
1406 Y. Xia et al.

Table 67.6 Typical ionized PVD systems

Main Equipment
producer model Main features
AMAT Endura Cluster system can integrate process chambers for multiple
materials, single-wafer process, can be configured with heating,
cooling, and RF bias can be used for filling high aspect ratio pores.
Mainly used for metal interconnects or dielectric coating processes
in IC manufacturing, advanced packaging, and other fields
NAURA eVictor, Cluster system can integrate process chambers for multiple
Polaris materials, single-wafer process, can be configured with heating,
cooling, and RF bias. Used for metal interconnects or dielectric
coating processes in IC manufacturing, advanced packaging, and
other fields

Atmospheric Pressure Chemical Vapor Deposition (APCVD)

System

Atmospheric chemical vapor deposition (APCVD) equipment refers to the equipment

that, under the environment where the pressure is close to the atmospheric pressure,
delivers gaseous reactants through injectors to the heated substrate surface at a uniform
speed, and then generates a chemical reaction so as to deposit the film on the substrate
surface. APCVD equipment is the earliest CVD equipment, is still widely used in
industrial production and scientific research. APCVD equipment can be adopted for
the preparation of monocrystalline silicon, polycrystalline silicon, silicon dioxide, zinc
oxide, titanium dioxide, phosphorosilicate glass (PSG), borophosphosilicate glass
(BPSG), and other films. Furthermore, APCVD O3-TEOS oxide process has been
wildly applied in STI and interlayer dielectric 0 (ILD0) applications. Figure 67.11
shows a simple schematic diagram of an APCVD system.
An APCVD system typically consists of a gas delivery unit, a heating element
and its electrical control unit, a wafer transfer unit, a reaction chamber unit, and an
exhaust scrubber. The gas delivery unit is applied to control, mix, and uniformly
deliver the reactant gases to the reaction chamber in the equipment. This unit
includes the gas manifolds and gas injectors. Depending on the required specifica-
tion, each gas manifold is designed with different types and quantities of valves
(such as manual valves and pneumatic valves), regulators, filters, and mass flow
controllers (MFCs) to control the on/off of the gas flow rate. The gas injector is
located at the end of the gas manifold where it enters the reaction chamber. Its
function is to ensure that the gas flows uniformly into the reaction chamber and it is
also a key component affecting the quality of the thin film. The heating element
provides the required energy for the chemical reaction, and the typical heating
methods include high resistive heating, RF inductive coil heating, and infrared
lamp heating. Common APCVD systems can be divided into multiwafer systems
and single-wafer systems depending on the wafer number loaded in each reactor.
Moreover, for multiwafer systems, there are vertical reactor type, horizontal reactor
type, and barrel reactor type.
67 Thin Film Growth Equipment 1407

Fig. 67.11 Schematic diagram of an APCVD system

When an APCVD system is operating, it is necessary to heat the substrate to a

certain temperature first, and then to control and adjust the reactant gases uniformly
flow over the substrate surface to perform the film growth on the substrate surface
through the chemical reaction between gases, meanwhile, the exhaust gas passes
through a specific pipeline into the exhaust scrubber. The reaction pressure in an
APCVD system is about 760 Torr which leads to a shorter mean free path for gas
molecules. Thus, there is a high probability of collision between the reactant
molecules, and the homogeneous nucleation is prone to occur in gas phase, so as
to generate particles inside the film and on the film surface. This particle issue is the
main disadvantage of APCVD technology. Frequent preventive maintenance
(PM) and new designed gas inject can suppress this negative effect. The advantages
of APCVD systems include simple structure, no need of complex vacuum assembly,
easy operation, high-deposition rate, high efficiency in production, good process
reproducibility, high throughput, and low cost of ownership. In addition, some
APCVD systems can be modified with a conveyer belt to achieve the continuous
film deposition for multiwafers. For example, Walkins Johnson, an American com-
pany used to provide many conveyer belt-type APCVD systems (e.g., WJ-TEOS
999 and WJ-TEOS 1500) for mass production lines in IC Fabs.

Low-Pressure Chemical Vapor Deposition (LPCVD) System

LPCVD systems use a gaseous raw material to generate a chemical reaction on the
solid substrate surface under conditions of heating (350–1100
C) and low pressure
(10–1000 mTorr), in which the reaction product is then deposited on the substrate
surface to form a film. LPCVD systems are developed on the basis of APCVD, with
the goal of improving film quality, enhancing the distribution uniformity of proper-
ties such as film thickness and resistivity, and raising production efficiency. The
main feature of these systems is that the process gas undergoes a chemical reaction
on the surface of the wafer substrate in a low-pressure heated environment and the
reaction product is deposited on the substrate surface to form a uniform film.
LPCVD systems have advantages in the preparation of high-quality thin films and
can be used for the preparation of thin films such as silicon oxide, silicon nitride,
polysilicon, silicon carbide, gallium nitride, and graphene.
1408 Y. Xia et al.

Compared with APCVD, the low-pressure reaction environment of LPCVD

systems can increase the mean free path and the diffusion coefficient of the gaseous
reactants in the reaction chamber, allowing the reactant gases and the carrier gas in
the reaction chamber to be evenly distributed in a short period of time. This greatly
improves the film thickness uniformity, the resistivity uniformity, and the step
coverage, with little consumption of the reactant gases. In addition, the
low-pressure environment also accelerates the gas transmission speed. The impuri-
ties and reaction by-products diffusing from the substrate through the boundary layer
can be quickly taken out of the reaction zone, and the reactant gases can rapidly pass
through the boundary layer to the substrate surface for reaction. In this way, self-
doping can be effectively suppressed and a high-quality film with a steep transition
zone can be prepared while also improving production efficiency.
LPCVD equipment generally consists of a gas box, a reaction chamber and its
pressure control system, an electrical control system, a transfer system, and an
exhaust scrubber. The main components of pressure control system for the reaction
chamber are a vacuum pump, vacuum controller, vacuum gauge, and valves, which
create the desired low-pressure environment inside the chamber by means of process
control. Heating methods are divided into resistance wire heating, high-frequency
induction heating, and infrared lamp heating.
Based on the number of wafers that can be accommodated in the chamber,
LPCVD systems are divided into multiwafer systems and single-wafer systems.
Multiwafer systems mainly use hot-wall heating systems, while single-wafer sys-
tems mostly use cold-wall heating systems. The biggest difference between hot-wall
and cold-wall systems is the portion that is heated. The hot-wall system provides
heat through a heat source and heats the entire reaction chamber system (including
the wafer, the quartz boat, and the reaction chamber); thus, the reaction chamber is in
a hot-wall state. The cold-wall system only heats the wafer and the wafer susceptor,
while the reaction chamber wall remains in a cold-wall state. The chemical reaction
in the hot-wall system occurs in all parts of the reaction chamber, so there is also a
deposition of reactants on the inner wall of the reaction chamber, which needs to be
cleaned regularly. The chemical reaction in the cold-wall system only occurs on the
heated substrate and substrate tray. At the current stage, LPCVD systems are
increasingly developing toward higher productivity, lower temperature, and new
reaction sources. Table 67.7 lists typical LPCVD systems.

Plasma-Enhanced Chemical Vapor Deposition (PECVD) System

PECVD is a thin film deposition technology with a wide range of applications in IC

fabrication, such as the growth of dielectrics, metal films, and semiconductor
materials. In the plasma process, gaseous precursors collide with energetic electrons
to form chemically active radicals and some ions. Similar to the conventional
thermal CVD process, these active radicals diffuse to the wafer surface and absorbed
onto the surface. Then these absorbed radicals have chemical reactions on the
surface to form a solid film and release gaseous by-products.
67 Thin Film Growth Equipment 1409

Table 67.7 Typical LPCVD systems

Main producer Equipment models Main features
ASM A400, A412 PLUS Multiwafer vertical structure. Suitable for
(Netherlands) polysilicon epitaxial processes involving silicon
oxide, silicon nitride, TEOS, undoping, and in situ
(phosphorus, arsenic, and boron) doping
TEL (Japan) TELFORMULA, Multiwafer vertical structure, with internal and
Alpha- 8SE, and external thermocouple temperature control.
TELINDY Suitable for epitaxial processes involving materials
such as polysilicon, silicon oxide, and silicon
nitride, as well as ALD of high-k materials
HKE (Japan) VERTRON and Multiwafer vertical structure. Suitable for epitaxial
QUIXACE processes involving in situ (phosphorus and
arsenic)-doped polysilicon, silicon oxide, and
silicon nitride
AMAT Centura, POLYgen, and Single-wafer equipment, using cold-wall system
(United Centura SiNgenPlus and low-temperature ceramic heating (below
States) 500
C), can be used for deposition and plasma
activation. Suitable for in situ (phosphorus and
arsenic) doping, polysilicon silicon-germanium,
silicon nitride, and other epitaxial processes
NAURA THEORIS (300), Multiwafer vertical structure with hot-wall
(China) THEORIS (200) chamber, suitable for epitaxial processes such as
those involving polysilicon, silicon oxide, and
silicon nitride

In order to produce more radicals and/or ions, RF or microwave generated

energetic electrons are applied to efficiently knock gaseous molecules to generate
radicals and/or ions instead of the thermal energy used in thermal CVD technology.
Depending on the frequency of power supply for the plasma generation, the PECVD
systems can be divided into two types: RF plasma-type and microwave plasma-type.
Currently, the RF frequency adopted by the industry is 13.56 MHz, in which the
plasma is generated by either a capacitively coupled plasma (CCP) method or an
inductively coupled plasma (ICP) method. The CCP method is usually a direct
plasma reaction method, while the ICP method is either applied in a direct plasma
system or a remote plasma system. Figure 67.12 shows a schematic of a flat plate
capacitively coupled PECVD system.
Generally, due to a short lifetime of energetic electrons, the capacitive coupling is
capable only to provide low-density plasma, thus resulting in the limited dissociation
of the reaction precursor and a relatively low-deposition rate. For inductive coupling
method, the RF power supply drives an alternating current in coils which simulta-
neously generate an alternating magnetic field inside the reaction chamber. Then this
time-varying magnetic field provides an induced AC electric field to drive electrons
forward and reverse rotation in chamber. Due to a longer lifetime of energetic
electrons in this mode, the probability of collision between energetic electrons and
precursors is highly increased, thereby a high-density plasma is generated.
In semiconductor fabrication processes, PECVD technology can provide more
radicals than conventional CVD, that is, it can achieve a higher growth rate at lower
1410 Y. Xia et al.

Fig. 67.12 Schematic of a flat plate capacitively coupled PECVD system

temperatures. Therefore, PECVD is commonly adopted to grow thin films on sub-

strates with metal patterns or other temperature-sensitive structures. For example, in
the back-end of line (BEOL) processes, there is a very strict thermal budget control for
thin film growth because the source, gate, and drain structures of devices were already
formed in the front-end of line (FEOL) process. Thus, PECVD technology is applied
to play a major role in most of BEOL processes for the dielectric deposition related to
the metallization. By modifying the plasma process parameters, thereafter, film den-
sity, chemical composition, impurity content, film hardness, and the stress release of
PECVD-grown thin films can be adjusted and optimized within a certain range.
Table 67.8 lists thin film materials grown by PECVD technology in IC fabrication.
For the 90 nm technology generation of IC fabrication technology, high-density
plasma CVD (HDP-CVD) technology was applied to improve the film density,
trench and gap-filling capability, as well as the growth rate of thin films. In
HDP-CVD, the additional Ar+ bombardment can effectively eliminate the formation
of overhang structures and densify the growing film during the thin film deposition
step, thereby enabling the void-free filling of trenches and gaps. Table 67.9 lists
typical PECVD systems.

High-Density Plasma Chemical Vapor Deposition (HDP-CVD)

System

The high-density plasma-enhanced chemical vapor deposition (HDP-CVD) process

is a special form of the PECVD process. In HDP-CVD, ionized atoms or molecules
have higher energies and perform a stronger bombardment effect when moving
toward the substrate, thereby resulting in sputtering. This sputtering process can
effectively eliminate the overhang structures formed in the process of thin film
deposition, so as to achieve the bottom-up filling of trenches and vias.
67 Thin Film Growth Equipment 1411

Table 67.8 Main applications of PECVD technology in IC processes

Process application
STI filling
Photoresist hard mask
Antireflective coating
Spacer
Premetal dielectric (PMD) liner
PMD deposition
Contact etch stop layer
Contamination protection layer on wafer
back
Intermetal dielectrics (IMD)
Damascene etch and chemical
mechanical polishing (CMP) stop layer
Passivation layer
Materials grown by PECVD
High-density plasma CVD (HDP-CVD) silicon
dioxide and flowable chemical deposition (FCVD)
silicon dioxide
PECVD amorphous carbon (α-C), PECVD silicon
nitride, and PECVD titanium nitride
PECVD silicon oxynitride
PECVD silicon nitride
PECVD silicon nitride
HDP-CVD phosphorus-doped silica
PECVD silicon nitride
PECVD silicon nitride
PECVD silicon dioxide and PECVD low-k dielectric
material
PECVD silicon nitride and PECVD silicon carbide
PECVD silicon nitride

Table 67.9 Typical PECVD systems

Main producer Equipment modelsMain features
AMAT (United States) Producer and Single-wafer cluster system. Can be used for
Centura ultra-low-k dielectric layer thin film deposition in
back-end metal wiring in integrated circuit
manufacturing
LAM Research (USA) Vector Express/ Multiwafer cluster system. Can be used for metal
PF-300T and SPEED tungsten plug and dielectric film deposition in
integrated circuit manufacturing
TEL (Japan) Triase+ SPAi Single-wafer cluster system. Can be used for
dielectric material deposition in integrated circuit
manufacturing
ASM (Netherlands) Eagle Single-wafer cluster system. Can be used for
low-k dielectric layer deposition in integrated
circuit manufacturing
NAURA (China) EPEE Single-wafer cluster system, can be used for
dielectric material deposition in IC and power IC
fields
Piotech (China) PF-300T Single-wafer cluster system. Can be used for
low-k dielectric layer deposition in integrated
circuit manufacturing

In the process of HDP-CVD, film deposition and film sputtering occur simulta-
neously. By adjusting the process parameters, the ratio of deposition to sputtering of
the thin film can be adjusted. The deposition-to-sputtering ratio is a very important
1412 Y. Xia et al.

parameter in HDP-CVD process. If the sputtering is too strong, it may cause damage
to the top corner of the convex structure of the substrate. If the sputtering is too weak,
the overhangs and voids will be formed in the gap-filling process, and the gap will be
formed in the filling step, resulting in a bad gap-filling result. Due to the unique
process characteristics of HDP-CVD, when HDP-CVD is adopted to deposit a thin
film on a patterned substrate, the deposition rate is usually higher in trenches than on
raised bumps. Therefore, the HDP-CVD process is capable of planarization. In
general, thin films deposited by the HDP-CVD method have higher film density
and lower impurity content inside.
Figure 67.13 shows a schematic diagram of the HDP-CVD process. HDP-CVD is
usually implemented through a dual-frequency structure design with source RF and
bias RF, as shown in Fig. 67.14. The source RF is usually an inductive coupling
device with a frequency of approximately 2 MHz, which and is mainly used to
control the concentration of ions. The bias RF is realized by a capacitive coupling
device with a frequency of approximately 13.56 MHz or less which is mainly used to
control the migration of ions to the substrate. This dual-frequency structure design
helps to achieve high-density plasma, while also ensuring good film stability and
high deposition rates.
HDP-CVD silicon dioxide is usually prepared with a mixture of silane and
oxygen/argon gases. The addition of argon in the reaction precursor can increase
the sputtering rate of the HDP-CVD process and densify the deposited SiO2 films.
The deposition process of phosphorus-doped silicon dioxide (PSG) can be
performed by adding phosphine to the reaction precursor.
The silicon dioxide films prepared by the HDP-CVD method are relatively
dense and widely used for the shallow trench isolation (STI) filling of CMOS
integrated circuits from the 130 nm to 45 nm technology nodes. Meanwhile, the
phosphorus-doped silicon dioxide films prepared by HDP-CVD are usually used
in processes such as premetal dielectric filling of the corresponding technology
generation.
With the development of IC technology below 28 nm, the introduction of FinFET
device structure poses a higher challenge to the trench filling technology for device
isolation, and the HDP-CVD technology has been unable to meet the requirements

Fig. 67.13 Schematic of the HDP-CVD process

67 Thin Film Growth Equipment 1413

Fig. 67.14 Schematic diagram of a dual-frequency HDP-CVD dual-frequency system

Table 67.10 Typical available HDP-CVD system

Main equipment Equipment
vendor models Main features
AMAT (United Producer and Single-wafer cluster system. Can be used for ultra-low k
States) Centura dielectric layer film deposition for the back-end metal
wiring in integrated circuit manufacturing

of technological development. Therefore, a new trench-filling technology known as

flowable chemical vapor deposition (FCVD) technology has emerged. FCVD is a
remote plasma deposition technology in which the reactive precursors are introduced
into the reaction chamber through a remote plasma generator to achieve the trench-
filling from bottom to top. FCVD can complete the seamless filling of tiny trenches
and vias to meet the process requirements of 10 and 7 nm technology nodes.
Table 67.10 lists typical HDP-CVD systems.

Metal Chemical Vapor Deposition (Metal-CVD) System

Metal chemical vapor deposition (MCVD) is a kind of chemical deposition tech-

nique that especially refers to the metal-containing precursors, which has the advan-
tage of achieving good step coverage for vias and trenches. MCVD systems can be
divided into two types depending on different reaction activation modes, namely
thermal reaction and plasma enhancement. The latter system can be further divided
1414 Y. Xia et al.

into metal in situ and metal remote types. Figure 67.15 shows the operation principle
of these three types of systems.
Metal thermal reactive CVD is a process in which metal precursors and other
gases (or metal precursors themselves) are stimulated to generate the chemical
reactions (or thermal decomposition) through the substrate tray heating to achieve
the metal film deposition. The structure of this equipment is relatively simple and it
is easy to achieve high step coverage.
The in situ metal plasma-enhanced chemical vapor deposition equipment is
suitable for the deposition of low-impurity metal film with the deposition tem-
perature lower than 400
C in the back-end process of the IC fabrication. It

Fig. 67.15 Schematic diagram of the operation principle and components of MCVD equipment
67 Thin Film Growth Equipment 1415

stimulates the chemical reaction by the combination of plasma ionized and

decomposed precursors with heating energy to achieve the low-temperature and
low-impurity film deposition. Its disadvantage is that it may cause electrical
damage to the substrate, and due to the anisotropy of the plasma, the coverage
of metal film deposition in small vias or on trench steps becomes worse, so there
are certain limitations to its application. Metal remote plasma chemical vapor
deposition equipment can make up some drawbacks for in situ plasma-enhanced
chemical vapor deposition. It first ionizes some part of the reactive gases in the
plasma chamber away from the substrate surface, thereby reducing the barrier
required to stimulate the chemical reaction, so as to reduce the deposition
temperature, film impurities, and substrate electrical damage. This type of plasma
is usually created using inductive coupling. Due to the short lifetime of ions and
atoms, the design of the system’s baffle plate and the selection of chamber
materials are challenging. In addition, the selection of metal precursors has an
important influence on the purity and roughness of the final metal thin film, as
well as the step coverage of the vias and trenches.
The use of gaseous precursors is beneficial to increase and control the flow rate,
so as to improve step coverage and reduce particles; if liquid or solid precursors are
used, a lower vaporization temperature and a higher vapor pressure are required. The
difference between the precursor decomposition temperature and the vaporization
temperature should be greater than 100
C to prevent the predecomposition of
reactants and the generation of particles during the vaporization process. Metal
precursors are classified as either metal inorganic precursors or metal organic pre-
cursors. Common inorganic precursors are fluorides, chlorides, and hydrides such as
WF6, TiCl4, SiH4, and NH3. Commonly applied inorganic precursors are usually
gaseous or liquid, and the deposited metal film will contain a small amount of
fluorine, chlorine, or other inorganic impurities. If a halide is used as a precursor,
the reaction product will be HCl, HF, etc., which will cause corrosion of the substrate
and chamber.
Metal organic precursors are noncorrosive and have a low-deposition temper-
ature, but the deposited thin films are liable to contain carbon impurities. More-
over, these precursors are usually liquid or solid at room temperature with
low-vapor pressure, therefore, it is difficult to control precursor flow and particle
prevention.
The purpose of the earliest application of metal chemical vapor deposition
(MCVD) equipment was to deposit tungsten which was applied to fill the contact
holes on integrated circuits and the word lines on storage devices. The precursors
WF6 þ SiH4 and WF6 þ H2 were used for seed layer deposition and bulk deposition,
respectively. With update of technology, the hole size has become smaller and the
method for depositing the titanium nitride barrier layer in the CVD tungsten process
has been changed from PVD TiN to CVD TiN. The titanium adhesion layer is
deposited before the titanium nitride deposition in the CVD W/TiN/Ti structure for
the contact formation, in order to prevent the corrosion of the titanium adhesion layer
and chlorine containing, that is, inorganic precursor TiCl4 cannot be used for the
deposition of titanium nitride. Therefore, a metal in situ PECVD equipment with
1416 Y. Xia et al.

metal organic precursors, such as Tetrakis(dimethylamino)titanium (TDMAT), etc.,

is adopted for the deposition of titanium nitride. In the preparation of capacitor
electrodes on memory storage devices, the requirements of step coverage, produc-
tivity, and electrical properties of thin films are very high. Metal thermal CVD
equipment was used for the thin film deposition of titanium nitride electrode, in
which the inorganic precursor TiCl4 is still used. In order to improve the stress
lifetime of metal interconnects, after the 28 nm technology generation, cobalt
capping layers were introduced after the chemical-mechanical polishing of copper,
and selective PECVD systems were used for the deposition of this cobalt capping
layer. Due to the roughness of tungsten in the main thermal chemical vapor process,
after the 14 nm technology generation, the tungsten seed layer deposition filled for
contact holes was also converted from the metal thermal chemical vapor deposition
to the in situ metal PECVD, which changes the anisotropy of the surface chemical
composition of tungsten seed layer, so that the main deposition could grow from the
bottom and reduce the gap in the cavity. In the preparation of 3D NAND, the word
lines and plugs were deposited by the combination of atomic layer deposition and
thermal reaction CVD equipment. After the 14 nm technology generation, the
requirements for the roughness of the metal surfaces become increasingly higher
due to the smaller trench size. For thin film applications, metal atomic layer
deposition (ALD) equipment will more often replace MCVD equipment. However,
the productivity of metal atomic layer deposition is usually low. Therefore, for
applications that require thicker metal film deposition, or require relatively high
step coverage, or lack of suitable precursors for ALD deposition, metal chemical
vapor deposition is still a good choice. Table 67.11 lists a typical metal chemical
vapor deposition (MCVD) system.

Atomic Layer Deposition System

Atomic Layer Deposition (ALD) is actually a subclass of chemical vapor deposition

technology that realizes an atomic scale film deposition by the separation of self-
limiting surface absorption step and self-limiting surface reaction step alternatively
in each deposition cycle. Furthermore, the deposited film thickness can be precisely
controlled by the number of deposition cycles. In the self-limiting surface absorption
step of the ALD process, a gaseous precursor is firstly delivered into the reaction
chamber and absorbed onto the exposed areas of the substrate surface through a
self-limiting way. Once the exposed areas of substrate surface are completely
covered, the absorption step of precursor stops and the residual precursor is purged
away from the reaction chamber immediately. In self-limiting surface reaction step, a
second gaseous precursor is then introduced and reacts with the absorbed precursor
to form the desired thin film onto the hot substrate. Again, a following purge is
applied to sweep away the residual second precursor. The sequence of steps in each
ALD deposition cycle is surface absorption/purge/surface reaction/purge. These two
precursors are never present simultaneously in the reaction chamber, but they are
alternatively introduced into the reactor and generate the chemical reaction through a
67 Thin Film Growth Equipment 1417

Table 67.11 Typical MCVD systems

Main Equipment
producer Process applications models Main features
Lam W-plugs, DRAM, and 3D Altus MAX E Each chamber includes four chambers
Research NAND word control lines, series Altus to increase the productivity and
metal contacts, etc. ICEFILL reduce equipment cost. Each substrate
holder can have a different
temperature to facilitate nucleation
and bulk deposition under optimized
temperatures. For RF-enhanced
chemical deposition processes,
separate chambers are required to
provide RF capability
AMAT W-plug, DRAM, and 3D Centura Single-wafer cluster system
NAND word control lines, iSPRINT integrated up to four chambers. The
metal contacts, etc. temperature, pressure, and RF
capability in each chamber can be
independently controlled with the
good process adjustability
Preparation of MOTiN for Endura iLB Cluster system integrated up to nine
W-plug barrier layer chambers for various materials,
including precleaning, physical vapor
deposition of titanium, and metal
CVD of titanium nitride
TEL DRAM capacitor electrode Triase þ TiN Single-wafer cluster system
and 3D NAND bit electrode integrated up to four chambers
Preparation of MO-TiN for Triase þ Ti/TiN Single-wafer cluster system
W-plug barrier layer integrated up to four chambers,
including precleaning, CVD of
titanium, and metal CVD of titanium
nitride
W-plug, DRAM, and 3D Triase þ W Single-wafer cluster system
NAND word control lines, integrated up to four chambers
metal contacts, etc.

precursor-surface interaction mechanism on the hot substrate surface. In each ALD

cycle, the amount of precursors adsorbed on the substrate surface is related to the
density of the reactive sites on the substrate surface. When the reactive sites on the
substrate surface are fully filled, the chemical adsorption on the substrate surface
then stops even if more excessive amounts of precursors are introduced, so this
reaction process is called self-limiting surface reaction. Therefore, the film thickness
grown in each cycle of the ALD process can be precisely controlled and the total
required film thickness can be achieved by the number of deposition cycles. So, the
advantages of the ALD are as follows; (1) To deposit stoichiometric films with large
area uniformity and 3D conformity, (2) To achieve an accurate thickness control,
(3) To deposit films at lower temperatures, (4) To deposit various films on sensitive
substrates (e.g., soft substrates, organic and biological samples, etc.).
1418 Y. Xia et al.

ALD systems typically operate at temperatures below 500
C. Currently,

low-pressure ALD systems are the most common equipment for the atomic scale
film deposition, in which the pressure ranges from 0.1 to 10 Torr. In addition, ALD
systems can be classified into thermal ALD and plasma-assisted ALD (PE-ALD)
systems depending on the power supplies. Thermal ALD systems rely on the thermal
energy to generate chemical reactions for precursors. Usually, the operation temper-
ature ranges from 200
C to 500
C. Figure 67.16 shows the schematic diagram of
the thermal ALD system with a showerhead. The showerhead assembly can improve
the uniformity of precursor distribution on the wafer surface.
Plasma-enhanced atomic layer deposition (PE-ALD) technology based on the
thermal ALD technology can further reduce the process temperature to meet stricter
thermal budget requirements. In addition, the introduction of plasma can increase the
concentration of reactive precursors and then enhance the chemical adsorption onto
the substrate surface so as to obtain higher growth rate for films. Typical deposition
temperatures of PE-ALD equipment range from room temperature to 400
C.
PE-ALD systems can mainly be classified into capacitively coupled (CCP) PE-
ALD-type and inductively coupled (ICP) PE-ALD-type. The schematic diagram of
a CCP PE-ALD system is shown in Fig. 67.17. PE-ALD technology shows advan-
tages such as lower deposition temperatures, densified films, less contamination, and
better conformity. PE-ALD technology has been successfully applied in OLEDs
fabrication, low-resistivity TiN deposition, GaN film growth, etc.
The ALD technology has the advantages of relatively low-deposition temper-
ature, precise film thickness control, good film uniformity, high film density, and
perfect step coverage. Therefore, it is adopted in many fields, such as microelec-
tronics, nanotechnology, photovoltaics, panel displays, optics, sensors, catalysts,
biomedicine, etc. Especially, ALD can still perform the high-quality thin film

Fig. 67.16 Schematic diagram of a showerhead-type thermal ALD system

67 Thin Film Growth Equipment 1419

Fig. 67.17 Schematic diagram of a CCP PE-ALD system

growth at lower temperatures to meet the thermal budget control requirement. For
the technology node of 45 nm or less, conventional silicon dioxide gate dielec-
trics and polysilicon gates of MOS devices have been respectively replaced by
ALD deposited high-k dielectrics (e.g., HfO2, Al2O3, ZrO2) and metal gate
materials (e.g., TiN) in order to reduce the gated leakage current and suppress
the depletion effect of polysilicon gate. In addition, for the technology node of
28 nm, metal ALD has been applied to deposit Cu seed layers for Cu electrode-
position and W seed layers for W-CVD process. Furthermore, various 3D FinFET
structures have been adopted for 22 nm and more advanced technology nodes, the
requirement of thermal budget control in the fabrication processes becomes very
strict, then ALD process is more widely applied to grow a variety of high-quality
thin films with good step coverage. For example, ALD-Si3N4 is used as a device
sidewall insulating layer and ALD-SiO2 is used as a self-aligned hard mask in
self-aligned double patterning (SADP) and also self-aligned quadruple patterning
(SAQP) processes.
2D device structures are very promising to replace some of the current MOS
device structures, such as 2D devices fabricated on MoS2, WS2, and WSe2 2D
materials. ALD process is the most promising technology to grow these ultra-thin
2D films. In addition, the growth of different multilayer structures by the ALD
technology is also straightforward.
ALD is a chemical adsorption reaction process, in which precursors must be
volatile but not subject to decomposition before the surface absorption step, and
most of precursors are very sensitive to oxygen and air. Consequently, available
precursors and substrates are limited, and also the number of different thin films
grown by the ALD technology are relatively limited. Optimization in process and
new precursor development may enhance the applications of ALD. The deposition
1420 Y. Xia et al.

Table 67.12 Typical ALD systems

Main Equipment
producer models Main features
AMAT ISPRINT and Single-wafer cluster system. Adopted in front-end metal gate
Olympia coating processes, metal W-plug processes, and dielectric
deposition processes in the integrated circuit field
TEL Triase+ Single-wafer cluster system. Adopted in metal bonding film
processes, metal W-plug processes, and high-k dielectric
deposition processes in the integrated circuit field
Lam Vector, ALTUS Multiwafer cluster system. Adopted in metal W-plug
Research processes and dielectric material deposition processes in
integrated circuit manufacturing
ASM Pulsar, Single-wafer cluster system. Adopted in high-k coating
Emerald, and processes, metal gate processes, and dielectric film processes
XP8 in the integrated circuit field
NAURA Promi Exlnt Single-wafer cluster system. Adopted in high-k coating
processes as well as metal and dielectric film processes in the
integrated circuit field
KE-MICRO T-ALD, Adopted in processes such as high-k dielectric and
PEALD optoelectronic device passivation in the integrated circuit field

rate of ALD process is very low and this is known to be the major limitation in
manufacturing, so the R&D of ALD equipment for higher throughput is a challenge.
Recently, the space-isolated ALD processes demonstrate potentials in better produc-
tivity. Table 67.12 lists typical ALD systems.

Photo Chemical Vapor Deposition (Photo-CVD)

Photo-CVD can be used to grow various metal, dielectric, and semiconductor thin
films at lower temperatures. The film growth mechanism is that UV photons with a
certain wavelength are introduced into the CVD system to decompose the gaseous
source molecules through the gas phase UV debonding and photosensitizing reac-
tions to form chemically active precursors, which diffuse to the substrate surface and
then achieve the thin film growth. The photosensitizing reactions between absorbed
UV photons and gaseous molecules are very effective to generate active precursors;
therefore, Photo-CVD can perform the thin film growth at low temperature of
100–300
C. The structure of Photo-CVD systems is similar to the conventional
CVD systems except the power source to generate precursors. It is assembled with a
reaction chamber, a gas inlet system, an exhaust system, and a light source system, as
shown in Fig. 67.18. The wavelength of selective UV light source must match the
optical adsorption properties of the gaseous molecules for the particular film depo-
sition. Lasers and lamps are main light sources for Photo-CVD. In addition, UV light
photons irradiating into the chamber through an optical window with a high trans-
mission index can assure a highly efficient UV debonding process. Also, a smooth
67 Thin Film Growth Equipment 1421

Fig. 67.18 Schematic of a photo-CVD system

optical window surface can suppress the film deposition on the window surface to
prevent the incident UV photons from being blocked.
There are two irradiation modes, namely focusing and nonfocusing modes. Also,
the UV light exposure is either parallel or perpendicular to the substrate. In general,
the parallel irradiation mode is applied for large-area film growth.
The main characteristics of photo-CVD are as follows.

1. At lower substrate temperatures of 100
C or even at room temperature, the film

deposition still can be effectively performed, then vapor phase self-doping,
interdiffusion between deposited film and substrate, migration of impurities,
wafer warping, as well as the plasma bombardment-induced lattice damage can
be significantly suppressed.
2. The film deposition is mainly in the surface reaction controlled regime and can
achieve a conformal deposition, therefore, the thickness uniformity, the step
coverage, and electrical properties of films are improved.
3. High intensity of UV photons can enhance the generation of active precursors to
increase the film deposition rate.
4. Photo-CVD technology is compatible to the IC fabrication for the gate dielectric
deposition and the multilayer wiring process of MOS devices. Also, Photo-CVD
has successfully performed the film deposition on some temperature-sensitive
plastic substrates.

Laser-Assisted Chemical Vapor Deposition (LA-CVD)

Laser-assisted CVD (LA-CVD) can be used to grow various types of thin films, such
as metal films, diamond films, diamond-like films, compound semiconductor films,
and insulator films. In addition, LA-CVD can be applied in the IC fabrication-related
processes, such as interconnect and packaging of devices, ohmic contacts, diffusion
barrier layers, photomasks or reticles, circuit repairing, 3D pattern fabrication, and
others.
1422 Y. Xia et al.

The mechanism of LA-CVD is that the reactant gases absorb the laser energy
to perform the chemical reaction and then deposit film on the substrate. The
schematic diagram of a LA-CVD system is shown in Fig. 67.19. Currently, there
are three kinds of lasers commonly used, namely, YAG lasers, CO2 lasers, and
excimer lasers are adopted as the laser sources. YAG lasers and CO2 lasers are
generally used to directly heat the substrate for thermally deposited films. Due to
the high energy of excimer lasers, which are usually used to break the molecular
bonds of source gases through the UV photodecomposition mechanism for the
film deposition.
LA-CVD has the following characteristics.

1. Low deposition temperature: LA-CVD technology can be applied to grow

thin films for most materials at the substrate temperature below 500
C
(or even at room temperature), especially for the temperature-sensitive sub-
strates such as polymers, ceramics, and some compound semiconductors
(e.g., HgCdTe), etc. In addition, LA-CVD process performed at a lower
substrate temperature can reduce the temperature variation-induced deforma-
tion, stress, cracking, interdiffusion, and inclusion in deposited films. As a
result, high-quality films with high-deposition rate can still be achieved at
lower temperature.
2. Fine localized deposition of local selection: LA-CVD technology can provide the
direct writing capability to deposit patterned films. That is, focused laser beam
irradiation raises the substrate temperature locally and generates the chemical
reaction to form patterned thin films only on these selectively heated areas. This
direct writing capability can reduce fabrication steps such as photolithography
and etching for um-scale devices in some microelectronics, optoelectronics, and
MEMS manufacturing.
3. Maskless deposition: the designed patterns can be obtained by direct writing
deposition, and deposition films are formed on the scanned track by laser spot.

Fig. 67.19 Schematic of the LA-CVD system

67 Thin Film Growth Equipment 1423

This LA-CVD process has strong adaptability and can quickly fabricate irregular
shaped devices.

LA-CVD technology shows great potentials in low-temperature thin film growth,

especially for the patterned thin film deposition. In the future, the research direction
of LA-CVD includes the research and development of various high-efficiency and
long-lifetime light sources, optimization in equipment structure and automation, as
well as a variety of suitable gas sources. Due to the high difficulty of LA-CVD
technology, which involves too many subjects, it is still in the laboratory stage.

Electron Cyclotron Resonance CVD (ECR-CVD) System

ECR-CVD is a high-density plasma deposition technology for growing thin films

such as Si3N4, SiO2, diamond films, etc. [3]. The principle is that a 2.45 GHz
microwave source provides the microwave into a magnetic field coil surrounded
plasmon resonant cavity through a waveguide, then the Cyclotron resonance is
achieved as the microwave frequency is adjusted to match the natural frequency of
electrons orbiting along lines of the Lorentz force in the magnet field. The resonance
of electrons happens at the 2.45 GHz for a coupled magnetic field of 875 Gauss;
therefore, microwave energy is strongly absorbed by electrons through the ECR
mechanism. High-energy electrons collide with incoming reactant gases to generate
plasma, and then regain energy by ECR mechanism to continue the plasma gener-
ation. The gyro-radius of electrons is in mm-scale range only. Therefore, a high
density of energetic electrons is sustainable inside the reaction chamber thereby
generating high-density plasma for the thin film deposition. An ECR-CVD system
consists mainly of a vacuum assembly, a gas inlet system, an exhaust system, a
microwave generator, a matching box with waveguide, a magnetic field coil, and a
DC bias or an RF bias source, as shown in Fig. 67.20. There are two power supplies
in an ECR-CVD system in which the 2.45 GHz microwave generator is applied to
generate the high-density plasma inside the chamber while a low-frequency power
supply connected to the susceptor is adopted to drive ions to the substrate surface.
ECR-CVD technology is capable of forming high-concentration plasma ranging
from 1011 to 1012 cm3 at low pressures, whereas the RF plasma-assisted CVD
can only achieve plasma concentrations of less than 1011 cm3.
Therefore, ECR-CVD has advantages in applications over DCCVD and
RFCVD as follows: (1) To grow high-quality films at high-deposition rate,
(2) To minimize the high-density ion bombardment-induced substrate surface
damage by controlling the bias voltage on substrate, (3) To densify the deposited
SiO2 films in gap-filling and trench isolation processes, (4) To obtain thin films
with metastable phase and controllable crystal orientation by highly reactive ions
at room temperature, (5) To minimize the damage in heat-sensitive substrates by a
low-temperature deposition process, such as SiO2 film deposition at the temper-
ature below 300
C. There are some disadvantages in ECR-CVD technology,
such as (1) High equipment cost due to the lower-pressure requirement and a
1424 Y. Xia et al.

Fig. 67.20 Schematic of ECR-CVD system

complicate magnetic coil design for a high-density magnetic field, (2) More
difficult to control the uniformity ECR plasma in process, (3) Optimized chamber
design is still in developing.
For the diamond film deposition, ECR-CVD technology is one of the adoptable
methods currently [3], in which single-crystalline diamond thin films with control-
lable doping level are achieved in spite of the low growth rate. In addition,
ECR-CVD technology has been also applied to deposit some temperature-sensitive
films on II-IV and III-V semiconductor substrates at lower temperatures, such as the
SiOxNy passivation films for HgCdTe devices.

Metal Organic Chemical Vapor Deposition (MOCVD) System

MOCVD technology is mainly used to grow single-crystalline III-V (e.g., GaAs and
GaN) and II-VI (e.g., ZnSe and HCdTe) compound semiconductor films for opto-
electronics and microelectronic devices [3]. At present, MOCVD is also a major
method applied in the preparation of devices with low-dimensional structures such
as compound semiconductor quantum wells, superlattices, and heterojunctions. In
addition, MOCVD is the main technology for the mass production of compound
semiconductor LEDs, lasers, high-frequency devices, and solar cells.
An MOCVD equipment generally consists of a precursor chemicals supply
system, a reaction chamber for the thin film growth, an electrical and automatic
control system, an in situ monitoring system, and an exhaust gas scrubber system.
Figures 67.21 and 67.22 show the schematic diagram of a typical MOCVD system
and the process steps of reaction, respectively.
The reaction chamber is typically made of stainless steel or quartz material with a
graphite susceptor inside for carrying and heating substrates. The temperature for
67 Thin Film Growth Equipment 1425

Fig. 67.21 Schematic of MOCVD system

Fig. 67.22 Schematic of the MOCVD process

deposition is controlled by either resistance wire heating method or RF inductive heating

method in which thermocouples are assembled for temperature monitoring and calibra-
tion. In order to deposit thin films with ultra-thin interface (e.g., 1 nm), electronic mass
flow controllers with ultra-fast bellow-sealed gas-switching valves are adopted to
accurately adjust the flow rate of carrier gas and reactant gases during the MOCVD
reaction. Metal organic precursor sources such as TMGa, TMAl, TMIn, and DIPTe
(di-isopropyltellurium), as well as hydride gaseous sources such as arsine, phosphine,
ammonia, and disilane are commonly adopted in MOCVD technology.
1426 Y. Xia et al.

As shown in Fig. 67.22, the process steps of the epitaxial growth using MOCVD
technology can be summarized as follows: (1) A carrier gas (usually H2, though N2 can
also be used) carries source precursors (the flow rate of precursors is precisely con-
trolled) into the reaction chamber, (2) Source precursors diffuse across the boundary
layer and arrive at the substrate surface, (3) Precursors are absorbed on substrate surface,
(4) Absorbed precursors migrate on the substrate surface, (5) Chemical reaction occurs
to form solid nuclei on the substrate surface, (6) Desorption of gaseous by-products from
the substrate surface, (7) Gaseous by-products diffuse into the main gas flow, (8) Solid
nuclei keep growing to form a continuous epitaxial film onto the substrate. Meanwhile,
the residual gases are exhausted by the exhaust gas scrubber system.
The main advantages of MOCVD technology are listed as follows: (1) Wide
range of applications: It can be used to grow a variety of compound semiconductor
films at low temperatures, especially for various multilayer heterostructural devices.
(2) Easy control of growth: The thickness, dopant profile, composition, and interface
of grown films can be precisely controlled by adjusting deposition temperatures,
precursors, gas flow rates, chamber pressures, and other growth parameters.
(3) Good reproducibility and uniformity: Mass production of MOCVD technology
has been achieved for LEDs, Lasers, high-efficiency solar cells, and high-frequency
devices with good reproducibility and high yield. Thus, the cost of products is
significantly reduced. (4) Automation of MOCVD systems is mature for advanced
quantum well structures.
Recently, high wafer capacity in chamber design of MOCVD system is demanded
to meet the cost down requirement. Therefore, the development trend of MOCVD
system is toward assembling a larger reaction chamber for loading more wafers in
each run so as to meet the mass production. For example, the loading capacity of
current Aixtron’s AixR6 models can load 31 pieces 4-in. wafers in one time.
Moreover, Aixtron has launched the G10-SiC MOCVD system with the size con-
figuration of 9  150 mm and 6  200 mm for silicon carbide epitaxy in 2022.
Consequently, MOCVD equipment with high-capacity multiwafer chamber
becomes a standard in industry. In addition, the adoption of MOCVD technology
to deposit III-V compound semiconductor films at the temperatures above 1300
C
for AlGaN UV LEDs and power devices is another trend for equipment develop-
ment. Table 67.13 lists typical MOCVD systems.

Molecular Beam Epitaxy System

A molecular beam epitaxy (MBE) system is an epitaxial equipment that effuses one
or more speeding beams of atoms or molecules with thermal energy onto the heated
substrate surface under ultra-high vacuum (UHV) conditions. These adsorbed atoms
or molecules migrate onto the substrate surface and then form bonds with the
substrate surface atoms at steps or kinks to achieve the epitaxial growth of film
which is grown with the same crystal structure as the substrate crystal. Generally, the
67 Thin Film Growth Equipment 1427

Table 67.13 Typical MOCVD systems

Main producer Equipment models Main features
Aixtron AIX Horizontal laminar gas inlet, planetary
(Germany) reactor, RF induction heating
Aixtron Crius and CCS Close-coupled showerhead, vertical inlet,
(Germany) multizone resistance heating
Veeco (United K465i, MaxBright MHP, Turbodisc tray with high-speed rotation,
States) Propel Power, E475i As/P, V-groove vertical inlet, multizone resistance
EPIK 700 heating
Tang ProMaxy Multiple (one to four) chambers can be
Optoelectronics configured for automatic continuous
(China) multifurnace operation. Sprinkler
technology and high-speed rotating tray
system technology are integrated, with
resistance wire and matrix self-balancing
temperature adjustment functions
AMEC (China) Prismo Multiple (one to four) independent control
chambers can be configured and the tray can
be rotated at high speed

Fig. 67.23 Structural diagram of an MBE system

beam source forms an atomic beam or a molecular beam by a heating effusion

furnace in which shutters shown in Fig. 67.23 are equipped to control the beam flux,
and the epitaxial film is grown layer by layer along the crystal orientation of the
substrate. MBE is a low-temperature epitaxial growth technology, in which the film
thickness, interface, chemical composition, and impurity concentration can be pre-
cisely controlled at the atomic level. Although MBE used to prepare the growth of
ultra-thin single-crystalline semiconductor films, it has now been applied in a variety
1428 Y. Xia et al.

of material growth, such as metals and insulating materials, III-V and II-VI com-
pound semiconductors, silicon films, silicon-germanium films, graphene films, oxide
films, and organic films.
An MBE system mainly consists of a UHV system, a molecular beam source, a
substrate susceptor with heater, a substrate transmission system, an in situ moni-
toring system, a control system, and a testing system. The vacuum system includes
a combination of vacuum pumps (such as mechanical pumps, molecular pumps,
ion pumps, and cryo-pumps) and a variety of valves. It can create a UHV growth
environment with a typical vacuum level of 108 to 1011 Torr. The main body of
MBE includes three vacuum chambers, namely the sample loading chamber, the
pretreatment and surface analysis chamber, and the growth chamber. The sample
loading chamber performs the sample transfer from the outside to ensure the other
chambers maintaining high vacuum conditions. The pretreatment and surface
analysis chamber, in between the sample loading chamber and the growth cham-
ber, performs the surface pretreatment of samples (high-temperature degassing to
ensure the complete cleaning of the substrate surface) and the preliminary surface
analysis of the cleaned samples. The growth chamber is the main portion of the
MBE system, mainly composed of the source furnaces with corresponding shut-
ters, sample control assembly, cooling subsystem, reflection high-energy electron
diffraction (RHEED) subsystem, in situ monitoring subsystem, and other sub-
systems. In addition, some production type MBE systems have multiple growth
chamber configurations to enhance the throughput. Figure 67.23 shows the basic
structure of an MBE system.
Under UHV conditions (1010 to 1011 Torr), MBE technology can also
deposit the epitaxial silicon with solid Ga (p-type) and Sb (n-type) dopants at
the low growth temperature of 600–900
C. Conventional solid dopants such as P,
As, and B are less applied as doping beam sources in MBE because of the hard
control in vaporization of these elements. The growth chamber of MBE systems
is always kept in an UHV environment, in which the mean free path of effusing
molecules is increased and the surface contamination and oxidation of substrate
are highly suppressed. MBE-grown epitaxial materials show better surface mor-
phology and good uniformity which can achieve the multilayer structures with
different dopants and compositions.
MBE technology enables a reproducible growth of multiple ultra-thin epitax-
ial layers with a steep interface between these epitaxial layers. It has promoted the
growth of III-V semiconductors and other multilayer heterogeneous materials.
For example, GaAs/AlGaAs heterogeneous films grown by MBE technology at
temperatures of 580–600
C and with Be and Si as the p-type and n-type doping
sources, respectively, demonstrate excellent performance. The growth rate ranges
from 0.1 to 2 μm/h. The electron mobility at 77 K is more than 100,000 cm2/Vs,
and the material background concentration is limited to 1014 atoms/cm2. These
films are suitable to fabricate GaAs MESFET, HEMT, HBT, and various new
superlattice devices. At present, MBE systems have become an advanced process
equipment for the fabrication of new-generation microwave devices and photo-
electric devices.
67 Thin Film Growth Equipment 1429

Table 67.14 Typical MBE systems

Main vendors Equipment models Main features
Riber (France) Compact21, Suitable for the preparation of III-V, II-VI, silicon
MBE49, carbide, silicon-germanium, mercury cadmium
MBE7000 telluride, metal, oxide, and other films
Veeco (United GEN10, GEN200, Suitable for the preparation of III-V, II-VI, oxide,
States) GEN2000 and other films
DCA Instruments M600, P600, S800, R&D equipment for the preparation of metal, oxide,
(Finland) P1000 III-V, II-VI, mercury cadmium telluride, and other
films. Production equipment for the preparation of
silicon, germanium, silicon-germanium, oxide,
III-V, and other films
SVT Associates 35-N series, 26-O Suitable for the preparation of nitride, oxide, silicon,
(United States) series, SM-6 germanium, metal, and other films
SKY (China) MBE-400 Suitable for the preparation of metal, III-V, oxide,
and other films

The disadvantages of MBE technology are the low-film growth rate, high vacuum
requirements, as well as the high equipment price and its high operation cost.
Table 67.14 lists main MBE vendors and systems.

Vapor Phase Epitaxy (VPE) System

A vapor phase epitaxy (VPE) system is an equipment to grow a single thin epitaxial
layer or a multilayer structure on substrate, in which gaseous sources are transported
onto the substrate surface and then form a crystalline mono layer or a stacked
multilayer on the substrate through a chemical reaction. The epitaxial layer is either
a homoepitaxial structure (e.g., Si/Si, or GaAs/GaAs) or a heteroepitaxial structure
(such as SiGe/Si, SiC/Si, or GaN/Al2O3). At present, VPE technology has been
widely applied in nanomaterial growth, power devices, semiconductor photoelectric
devices, solar PV, and IC fabrication.
The typical VPE process includes atmospheric pressure epitaxy, reduced
pressure epitaxy (RP Epi), UHV CVD, and MOCVD. Main factors in VPE
technology are reaction chamber design, gas flow pattern and uniformity control,
accuracy and uniformity control of temperature, pressure control, and stability, as
well as particulates and defects control. At present, the required specification for
industrial VPE systems includes larger loading capacity, full automation, and in
situ monitoring of temperature and growth processes. Main types of VPE equip-
ment are vertical system, horizontal system, and barrel system. Resistance
heating, high-frequency (RF) inductive heating, and infrared radiation heating
are heating methods for these VPE equipment. At present, most VPE systems
assemble a horizontal rotary pancake susceptor, which enables good uniformity
of the grown epitaxial film and a large wafer loading capacity. A VPE system
typically consists of a reactor chamber, a heating source, a gas piping panel
1430 Y. Xia et al.

Fig. 67.24 Schematic diagram of a VPE system

assembly, and a control system. The deposition duration of GaAs and GaN
epitaxial films usually is relatively long, therefore, inductive heating source and
resistance heating source are mostly adopted. In the VPE of silicon epitaxy, thick
silicon epitaxial films are mostly grown with the inductive heating source, while
thin silicon epitaxial films are mostly grown with an infrared heating source to
achieve a rapid ramp up/ramp down in temperature. Figure 67.24 shows the
structure of a VPE system.
As an example, in the VPE process of silicon-related materials such as silicon and
silicon-germanium (SiGe) epitaxy, silane (SiH4), dichlorosilane (DCS, SiH2Cl2),
and trichlorosilane (TCS, SiHCl3) are usually adopted as the gaseous silicon sources
for silicon epitaxy, and with added germane (GeH4) and methylsilane (SiHx(CH3)y)
for SiGe compound films. Hydrogen is the reactant gas and also the main carrier gas
in the epitaxial reaction. The VPE process for silicon and silicon-germanium epitaxy
is widely used in advanced IC manufacturing. Some applications are shown as
follows;

1. Blanket epitaxial silicon on silicon substrate: An intrinsic silicon layer with

higher purity and better quality epitaxially grown on a silicon substrate can
improve the performance of ICs and devices. Also, a lightly doped high-
resistivity epitaxial Si layer grown on a heavily doped silicon substrate can
effectively suppress the latch-up effect of CMOS.
2. SiGe epitaxy: In order to meet the BJT device requirements of high-frequency
and high-speed in fields of wireless communication and optical communication, it
is necessary to introduce Ge into Si to form a SiGe epitaxial layer as the base
67 Thin Film Growth Equipment 1431

region of the heterojunction bipolar transistors (HBT). The narrower band gap of
SiGe can reduce the potential barrier for electrons drifting from the emitter to the
base, thereby improving the electron-hole injection rate and the current gain. In
order to match the amplification requirement, a thinner heavily doped SiGe base
can reduce the transit time of carriers in base region so as to increase the cutoff
frequency of HBTs.
3. Selective epitaxial growth (SEG): For the technology node of 65 nm or less, the
size of IC devices is significantly reduced and the junction depth of source/drain
becomes shallower. Then the conventional method to reduce the specific contact
resistance becomes an issue. To apply Si/SiGe SEG in the CMOS source/drain
region is required to reduce the series resistance and enhance the carrier mobility.
There is a small lattice mismatch (4%) between Ge and Si. Therefore, the
technology to enhance carrier mobility by strain layers is adopted for 65/45/
28 nm technology nodes. The SEG SiGe layer is grown only on the source/drain
region of pMOS to generate a compressive stress in pMOS channel, thereby
increasing the hole mobility of pMOS. Alternatively, a single-crystalline silicon
layer epitaxially grown onto the unstressed SiGe layer can generate a tensile
stress on the SiGe layer due to the lattice mismatch, so as to increase the electron
mobility in nMOS channel, thereby increasing the saturation operating current
and improving the response speed of CMOS devices.

Table 67.15 lists vendors and main features of silicon VPE equipment.

Table 67.15 Typical silicon VPE equipment

Equipment
Main producer models Main features
AMAT Centura EPI Single-wafer epitaxy, can be configured with one to three
(United States) 200/300 chambers, can be configured for reduced pressure, includes
infrared heating function, can be used with silicon and silicon-
germanium epitaxy as well as SEG in the power semiconductor
or integrated circuit fields
ASM Epsilon2000/ Single-chamber single-wafer epitaxy, can be configured for
(Netherlands) 3200 reduced pressure, includes infrared heating function, can be
used for n/p film epitaxy and SEG in the power semiconductor
or integrated circuit fields
NAURA SES 630/680A Multiwafer, atmospheric pressure epitaxy, high-frequency
(China) induction heating, can be used for n/p thick film epitaxy
processes in the power semiconductor and integrated circuits
fields
NAURA Esther200C/L Single-wafer epitaxy, can be configured with one to three
(China) chambers, can be configured for reduced pressure, includes
infrared heating function, can be used for n/p thin film/thick
film epitaxy and SEG in the power semiconductor and
integrated circuit fields
1432 Y. Xia et al.

Liquid Phase Epitaxy (LPE) System

A liquid phase epitaxy (LPE) system is a type of epitaxial growth equipment that
melts the material to be grown (such as Si, Ga, As, or Al) and a dopant (such as
Zn, Te, or Sn) together into a metal with a lower melting point (such as Ga or In)
to form a saturated or supersaturated solution, then this saturated solution is
brought to directly contact the single-crystalline substrate so as to precipitate
the solute from the solvent by a gradual cooling process, thus, a layer of
crystalline material is grown on the substrate surface with a crystal structure
and lattice constant similar to that of the substrate. The LPE method was pro-
posed by Nelson et al. in 1963 for the growth of Si thin films and single-crystal
materials, as well as III-IV, mercury cadmium telluride (HgCdTe), and other
semiconductor materials, etc., which can be applied to fabricate various photo-
electric devices, microwave devices, semiconductor devices, and solar cells.
A LPE system typically consists of a gas control unit, a heating component, a
control assembly, a material charging unit, a reaction chamber, and a vacuum
system. LPE systems can be classified into three types depending on the reaction
system adopted: such as horizontal sliding boat systems, vertical dipping sys-
tems, and rotary crucible systems (centrifugal systems). (1) For example, in
Fig. 67.25, the horizontal sliding boat system adopts a horizontal reactor. A
sliding graphite boat having a plurality of tank cells is placed on the substrate
and the tank cells are filled with the raw material solution. The graphite boat is
then slid so that the tank cells containing solution make contact with the substrate
to start the epitaxial film growth under a gradient temperature control. After the
epitaxy is performed, the graphite boat is pushed to scrape off the remaining
solution. (2) The vertical dipping system adopts a vertical growth tube and a

Fig. 67.25 Schematic of a horizontal sliding boat LPE system

67 Thin Film Growth Equipment 1433

vertical heating assembly unit. The saturated raw material solution is placed in a
graphite crucible and the substrate is fixed on a substrate holder. After the
substrate is dipped into the saturated solution, the epitaxial film growth is
implemented either by directly cooling solution or by forming a certain temper-
ature gradient between the solute, solution, and substrate. (3) The rotary crucible
system includes a crucible fixed on a rotatable column. The substrate is placed on
the bottom of the crucible. The epitaxial growth is performed by controlling the
rotation speed of the crucible so that the raw material solution covers or leaves the
substrate surface under the action of the centrifugal force. Figure 67.25 shows a
schematic of a horizontal sliding boat LPE system.
LPE technology can only perform the epitaxial film growth at near thermody-
namic equilibrium conditions. There are many advantages in LPE systems, such
as simple equipment structure, higher growth rate, capable of growing thick
epitaxial layers, epitaxy with high-temperature melting solutions, more selection
of dopants, and capable of growing a single-crystalline film with various dopants.
In addition, the dislocation density of the epitaxial layer is lower than that of the
substrate, no highly toxic or corrosive raw materials or reaction products are
involved during the growth process, and the operation procedure of LPE equip-
ment is simple and safe. However, LPE systems also show certain deficiencies.
For example, it is difficult to control the composition uniformity of the large area
epitaxy and the multielement compound semiconductors, in addition, the require-
ments of purity and quality for the substrate and raw materials are much strict
leading to extremely high costs in epitaxial growth. As the lattice mismatch is
larger than 1% between the epitaxial layer and the substrate, it is difficult to
perform the epitaxial growth. Furthermore, the growth rate of LPE is too high to
grow an epitaxial layer of nanometer thickness. Also, due to the graphite boat
sliding-induced scratches, the surface quality of the LPE grown epitaxial layer is
not so good as that of VPE products.
LPE technology performed a widely progress in the 1970s for the manufacture of
III-V compound semiconductors. The fabrication of many semiconductor devices,
including LEDs, lasers, III-V solar cells, and heterojunction LEDs, was first achieved
by the LPE technology. However, in the 1980s, the popularity of LPE technology did
not continue to grow. In the LED market of As- and P- related III-V compound
semiconductors, LPE technology gradually declined due to the merits of precise
heterostructure control and less substrate dependence provided by MBE and MOCVD
technologies, which replaced most of LPE’s development and production in LEDs,
semiconductor devices, and other fields. However, LPE technology is still adopted in
some applications such as mid-infrared antimony-related III-V optoelectronic devices
(e.g., InSb), some LEDs, and long wavelength detectors. Currently, LPE technology is
considered to have potential applications in the field of large-size and high-deposition
rate materials, especially in the field of silicon solar cells. In recent years, a number of
innovative developments have been made in LPE technology, including new solvents
for LPE, epitaxy under magnetic field, and defect filtration technologies, etc.
1434 Y. Xia et al.

Nowadays, LPE systems are basically home-made equipment which are designed
and assembled by manufacturers or laboratories themselves according to the process
requirements. The temperature control requirements of LPE systems are extremely
strict; therefore, a highly stable voltage source and current source are necessary so as
to provide a uniform and stable temperature distribution during the epitaxial growth.

Chemical Beam Epitaxy (CBE) System

CBE is an ultra-thin film growth technology developed on the base of MBE and
metal organic vapor phase epitaxy (MOVPE). It combines the characteristics of
MBE and MOVPE and can use either III MO sources or V hydride gas sources to
implement the film growth. In the growth of III-V compound semiconductor mate-
rials, this CBE technology introduces the gas sources trimethylgallium (TMGa) or
trimethylaluminum (TMAl) used for MOCVD to replace the conventional solid
evaporation sources Ga or Al used in an MBE system, respectively Meanwhile,
the solid source of V elements is replaced by arsine (AsH3) or phosphine (PH3). For
the growth of IV semiconductors, a hydride can be used as a gaseous source; for
instance, solid silicon source can be replaced with silane (SiH4) or disilane (Si2H6),
and the germanium epitaxial layer can be grown with germane (GeH4). Since the gas
source can be continuously supplied, the flow control accuracy and the control of the
reaction rate are superior to methods that use solid sources. Therefore, CBE has the
merits of the precise gas flow control capability of MOCVD as well as the ultra-thin
interface control and the in situ measurement of MBE.
A CBE system consists mainly of a precise MFC controlled multichannel gaseous
source system similar to that used in MOCVD, and a high-vacuum growth chamber
similar to that of MBE systems. The gas piping system controls the gas flow rate
ranging from several milliliters to hundreds of milliliters with mass flow meters. The
inner surfaces of all stainless steel pipes are electrochemically polished to avoid the
particle accumulation and each joint must be rigorously tested with a leak detector to
prevent toxic gas from leaking. The growth system and monitoring system are similar
to those used in MBE. The substrate is delivered into the growth chamber through a
load chamber and a preparation chamber with independent pumping systems. Com-
binations of cryo-pump, turbo pump, and dry pump are used to achieve a high vacuum
level of less than 0.1 mTorr for the growth chamber. In addition, the growth chamber is
equipped with a liquid nitrogen shielding case in which a circulating liquid nitrogen
flow keeps the reaction chamber cooling for high vacuum. Precision analyzers used in
MBE, such as reflection high-energy electron diffraction (RHEED) analyzers, quad-
rupole mass spectrometers (QMS), and Auger spectrometers, are also equipped in
CBE system to in situ characterize the crystal growth processes including the residual
gas composition, the growth rates, and the details of atomic layer epitaxy.
CBE technology is mainly used to prepare single-crystalline compound semicon-
ductor films and is especially suitable for phosphide material devices. It provides
67 Thin Film Growth Equipment 1435

important applications in growing compound semiconductors with complex struc-

tures, and this technology shows potential to develop the new generation of photo-
electric devices and high-frequency devices. However, there are still some
disadvantages of CBE technology including high-cost vacuum subsystems, the com-
position ratio control of Indium in GaInAs and other materials, as well as the carbon
contamination in III-V ternary compound semiconductors such as GaAlAs. Currently,
MBE companies such as Riber in France and Canon Anelva in Japan have provided
CBE equipment. However, CBE technology is not considered as a sustainable tech-
nology, then many companies have cut off the production of CBE equipment.

Ion Beam Epitaxy (IBE) System

IBE technology can be used to prepare various thin films such as metals, insulators,
semiconductors, oxides, nitrides, organic materials, fluorides, and high-temperature
superconducting materials. The basic principle is that the material placed in a special
crucible with small holes (about 1 mm in diameter) is heated to generate a vapor
flow. Then the vapor effuses into a high vacuum chamber through small holes and
undergoes an adiabatic expansion process, which causes the molecules of the
evaporated material to be coupled into loose atomic clusters. The atomic clusters
pass through an ionization region, which includes a hot cathode and an anode. The
hot cathode generated electrons are accelerated under the electric field and then
collide with the evaporated neutral atomic clusters. Some of these neutral atomic
clusters are ionized to form positively ionized atomic clusters. As shown in
Fig. 67.26, these positively charged atomic clusters pass through the accelerating
electrode by a negative bias between the accelerating electrode and the substrate so
as to deposit onto the substrate surface. Usually, the probability to form a multi-
charged ion is very low, and also the single positively charged clusters have a small
charge-to-mass ratio. Therefore, the space-charge effect on the cluster ion beam is
almost ignored and a high-deposition rate can be obtained. The cluster ion beam
energy and the ionization ratio of clusters can be easily controlled through the
ionization region, thereby allowing to deposit the dense and highly adherent films
onto the low-temperature substrates. IBE demonstrates a low-temperature deposition
capability that is far beyond other epitaxial technologies. The schematic diagram of
IBE system is shown in Fig. 67.26.
The crucible component is covered with a stainless steel jacket, and is equipped
with a heat shield and a water cooling system. The crucible is heated by a resistance
wire and equipped with a temperature monitoring and rare gas control system. The
substrate is placed on a stage with a shielding shutter, and the substrate temperature
monitored by a thermocouple is controlled by heaters or by coolants such as liquid
nitrogen or water. The IBE chamber is connected to the molecular pump system to
avoid the oil contamination in the system.
Although IBE has been used to obtain various high-quality films in experiments,
there are still many unsolved problems in theory, such as the formation mechanism
of clusters, the influence of cluster morphology on the film quality, the relationship
1436 Y. Xia et al.

Fig. 67.26 Schematic diagram of IBE system

between cluster size and film formation, and the interface between the deposited film
and the substrate. Recently, many experiments and theories have been developed to
study these problems internationally. However, most research has only provided
some empirical experimental parameters, so as to further study the mechanism about
the heat transfer and the mass transfer of materials under cluster collision conditions
is necessary.

Low-Energy Ion Beam Epitaxy (LE-IBE) System

LE-IBE technology is applied for low-temperature epitaxy of films such as Si, Ge,
and GaN, and also to grow polycrystalline diamond films. The basic operating
principle is to use a suitable strong ion current source to produce the required
67 Thin Film Growth Equipment 1437

Fig. 67.27 Schematic diagram of a low-energy double-beam ion beam epitaxy (LE-IBE) system

films. The ion source is accelerated and focused to form a beam, a mass analyzer is
used to separate the desired ions from the main ion beam, and then those selected
ions are focused, deflected, decelerated (from high energy to low energy), neutral-
ized (from low-energy ions to neutral atoms or molecules), and finally delivered onto
the substrate surface to perform the epitaxial deposition. Based on the equipment
structure, LE-IBE systems can be divided into single-beam, quasi-double beam, and
double-beam types. In addition, the ion sources generated by LE-IBE systems can
also be divided into positive ion beam, negative ion beam, as well as hybrid positive
and negative ion beam types. The basic structure of LE-IBE system includes an ion
source, a magnetic analyzer, an electrical or magnetic quad lens, an electrostatic
deflector, a deceleration lens, and a UHV chamber, as shown in Fig. 67.27.
Compared to other conventional thin film growth technologies, LE-IBE technol-
ogy has the following features.

1. It can be applied to prepare various materials and suitable to develop new

materials.
2. It is capable of mass separation. This technology can extract required high-purity
material components from the raw material for the deposition.
3. It is characterized by charged ion deposition, so it can perform high-quality
epitaxy at low temperatures for materials that used to be synthesized at high
temperatures, and also for metastable and nonequilibrium nanostructured
materials.
4. It demonstrates diversified functions. The flexible growth modes include single-
beam epitaxial growth mode, double-beam epitaxial growth mode, and the single-
beam-double-beam alternative epitaxial growth mode.
1438 Y. Xia et al.

5. The growth rate is precisely controllable and even the monolayer film growth can
be achieved.
6. It is easy to control the growth process for studying the mechanism and the
surface science of thin film growth. However, the equipment structure of LE-IBE
is extremely complicated and the production efficiency is very low, therefore, it is
still in the experimental research stage. A primary model of LE-IBE system is the
Oxford Ionfab 300Plus, which is a semiconductor equipment combining the
function of ion beam epitaxy and ion etching.

Spin Coater

A spin coater is used for coating photoresist (PR) on the wafer surface. The spin
coater consists of a wafer chuck, a PR dispenser, and an air-bearing spindle. The
substrate is placed on the vacuum chuck that can hold the substrate by a negative
pressure during the high-speed rotation, and the liquid photoresist is dripped on the
substrate surface by a PR dispenser. The rotational speed of the spindle is precisely
controlled to adjust the magnitude of the centrifugal force to achieve the required
thickness of photoresist. Basically, the higher the spin rate, the thinner the photore-
sist layer, and the better the thickness uniformity. In addition, the thickness of the
spin-on photoresist layer is also related to the spin-on duration, the viscosity of the
photoresist, the temperature, and the humidity during the spin coating process [4, 5].
The schematic diagram of the spin coater is shown in Fig. 67.28.
There are two methods to dispense photoresist, namely static dispensing and
dynamic dispensing. In static dispense, the photoresist is distributed onto the center
of the stationary substrate and allowed to spread a certain diameter of the wafer
surface. Then the wafer is spun rapidly to distribute the photoresist across the entire
wafer surface uniformly. The amount used for photoresist dispensing depends on the

Fig. 67.28 Schematic

diagram of the spin coater
67 Thin Film Growth Equipment 1439

IC fabrication processes. In addition, the amount of dripped photoresist to meet the

thickness requirement is mainly related to photoresist viscosity, PR surface tension,
PR drying property, the spin-on rate, the accelerating rate, and the wafer size, When
the photoresist viscosity is high or the substrate size is large, more photoresist is
required to coat the entire substrate uniformly. For dynamic dispensing, the photo-
resist is dripped onto the center of the substrate while the wafer is rotating at a
low-spin rate (about 500 rpm). After the PR is dispensed, the wafer is accelerated
immediately to a high-spin rate of up to about 7000 rpm to spread the photoresist
across the whole wafer uniformly. Dynamic dispensing can suppress the pinhole
formation and use less amount of photoresist as long as the photoresist is spread
quickly on the substrate surface. When there is a poor wetness between the substrate
and the photoresist, dynamic dispensing method can provide better adhesive perfor-
mance than static dispensing method in photoresist spin coating process.
The vaporized solvent in liquid photoresist is evacuated from the exhaust during
the spin coating step. The photoresist thickness and the film uniformity are related to
the exhaust gas temperature and the gas flow rate which can affect the drying
property of PR. Therefore, the faster drying of photoresist near the wafer edge results
in the edge bead because of the higher viscosity of the photoresist near edge areas.
That is, the photoresist near the edge is thicker than the center. A thick edge bead can
cause particulate contamination during wafer transfer step and defocus issue in
exposure process. Therefore, the edge bead of photoresist needs to be removed.
The edge bead removal (EBR) process includes the chemical removal method and
the optical removal method. Chemical EBR is applied in the spin coater. After the
photoresist coating, solvents are injected onto the both sides of the wafer edge while
the wafer is still rotating. Solvents dissolve the photoresist just near the edge area and
wash it away. Optical EBR is applied after the exposure step. It uses a light source to
expose the top side of the wafer edge of a rotating wafer. The exposed edge bead will
be removed during the development step.
At present, representative Chinese spin coaters are the KW-4A model produced by
the Institute of Microelectronics of China Academy of Sciences and the spray type
spin coaters produced by VeriSilicon Holdings Co., Ltd. The spin-on film thickness
can range from 10 nm to 100 μm, and the uniformity is controlled to about 1%.

References
1. Z.J. Radimski, W.M. Posedowsiki, S.M. Rossnagel, S. Shingubara, Directional copper deposi-
tion using self-sputtering. J. Vac. Sci. Technol. B 16(3), 1102–1106 (1998)
2. J. Andersson, A. Anders, Self-sputtering far above the runaway threshold: an extraordinary
metal-ion generator. PRL 102, 045003 (2009)
3. H.O. Pierson, Handbook of Chemical Vapor Deposition, Principles, Technology, and Applica-
tions, 2nd edn. (Noyes Publications, New York, USA, 1999)
4. H. Xiao, Introduction to Semiconductor Manufacturing Technology (SPIE Press, Washington,
USA, 2012)
5. M. Quirk, J. Serda, Semiconductor Manufacturing Technology (Prentice-Hall, New Jersey,
USA, 2001)
Plasma Etch Equipment
68
Yuan Pu

Contents
Introduction to Principles of Plasma Etching and Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442
Types of Plasma Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444
Plasma Etching Equipment Application and Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449
Ion Beam Etching (IBE) Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451
Plasma Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
Reactive Ion Etching (RIE) Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454
Magnetically Enhanced Reactive Ion Etching (MERIE) Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
Capacitively Coupled Plasma (CCP) Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
Inductively Coupled Plasma (ICP) Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
Electron Cyclotron Resonance (ECR) Plasma Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465
Helicon Wave Plasma (HWP) Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
Surface Wave Plasma (SWP) Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472
Atomic Layer Etching (ALE) Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474
Plasma Stripping Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
Dry Cleaning Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
Plasma Etching Equipment Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
Materials Used for Chamber Parts in Plasma Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
The Electrostatic Chuck (ESC) in Plasma Etching Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493

Abstract
This chapter begins with a brief overview of the plasma etching principle, equip-
ment categorization, and their applications. A total of 11 typical plasma etch
techniques and equipment are introduced, including ion beam etching (IBE),
plasma etching (PE), reactive ion etching (RIE), magnetically enhanced RIE
(MERIE), capacitively coupled plasma (CCP), inductively coupled plasma (ICP),
electron cyclotron resonance (ECR), remote plasma source (RPS), helicon wave
plasma (HWP), surface wave plasma (SWP), and atomic layer etching (ALE).
Y. Pu (*)
Advanced Micro-Fabrication Equipment Inc. (AMEC), Shanghai, China
e-mail: bryanpu@amecnsh.com

© Publishing House of Electronics Industry 2024 1441

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_68
1442 Y. Pu

In addition, three major components common to all kinds of plasma etch tool,
cluster platform, reactor material, and electrostatic chuck (ESC) are described. Dry
clean equipment is also included in this chapter.

Keywords
Plasma source · Reactor · Electrostatic chuck · Dry etch · Wet etch · Isotropic
etch · Anisotropic etch · Bias RF power · Source RF power

Introduction to Principles of Plasma Etching and Equipment

There are two types of etching used in integrated circuit manufacturing processes,
namely wet etching and dry etching. Wet etching was widely used in the early days,
but due to its limitations in linewidth control and etching directionality, wet etching
is only used to remove some special materials and clean away residues, while dry
etching is currently used for most processes involving linewidth less than 3 μm. Dry
etching refers to the process of removing materials from the wafer surface using
gaseous chemical etchants, which react with materials on the wafer to form volatile
reaction products that are then evacuated from the reaction chamber. The etchants are
usually generated directly or indirectly from the plasma of the etching gases, so dry
etching is also known as plasma etching.
Plasma is a weakly ionized gas formed by the glow discharge of etching gas
through the application of an external electromagnetic field (e.g., generated by RF
source or microwave source), which includes electrons, ions, and neutral free
radicals. Among these particles, free radicals can directly react with the material to
be etched to complete the etching process, but this pure chemical reaction usually
occurs only in very few types of materials and has no directionality. When ions gain
a certain amount of energy, etching can be done through physical sputtering, but this
pure physical reaction is characterized by a very low etch rate and poor selectivity.
Most plasma etching is done with the combination of free radicals and ions simul-
taneously. In this process, ion bombardment serves two functions: The first is to
break the atomic bonds on the surface of the material to be etched and generate
chemically active dangling bonds on the film surface, thereby increasing the reaction
rate of neutral free radicals. The second is to detach the reaction product deposited on
the reaction interface, so that the etchant maintains full contact with the surface of the
material to be etched to continue the etching process. The reaction products depos-
ited on the sidewalls of etched structures cannot be effectively removed by direc-
tional ion bombardment, thereby blocking the sidewall etching and thus leading to
the anisotropic etching [1, 2]. Table 68.1 lists the types of plasma etching and their
applications.
With the continuous development of integrated circuit manufacturing technology
over the past 30 years, plasma etching equipment has experienced rapid evolution. In
68 Plasma Etch Equipment 1443

Table 68.1 Types of plasma etching and their applications

Mixed physical-chemical
Types of etching Physical etching etching
Main characteristics Good directionality Both directionality and
and low selectivity selectivity are controllable
Equipment example Sputtering etchers RIE etchers
Main applications Surface cleaning Etching of materials
(e.g., holes or trenches
formation in silicon,
oxides, and metals)
Chemical etching
Very poor directionality
and high selectivity
PR strippers
Photoresist removal,
silicon nitride removal,
and oxide mask removal

general, early plasma etching equipment adopted multiwafer design, it means that
the reaction chambers of these equipment, such as barrel etchers, hexode etchers, and
some planar etchers, could accommodate multiple wafers. Due to the requirement of
better precision and uniformity in etching processes for large size wafers, most
etching equipment has adopted the standard of single wafer mode since the advent
of 200 mm diameter wafers. In order to improve the performance of the single wafer
etching system, it is necessary to greatly increase the etching rate to enhance the
throughput, and also perform the etching process in a low-pressure environment for
advanced technology nodes. Therefore, the early stages of the evolution of single
wafer etching equipment were focused on the development of stable and high-
density plasma technology operating at lower pressures. However, in later practice,
it is found that high-density plasma does lead to a high etching rate, but may cause
problems such as device damage and low selectivity, so high density is no longer the
prior goal for the etching equipment. With many revolutionary breakthroughs in
modern integrated circuit technology, such as FinFET and 3D flash memory struc-
tures, these equipment not only have the requirements for etching processes become
increasingly strict, but also the types of processes that involve etching have become
increasingly broad. As a result, in addition to pursuing the improvement in unifor-
mity and precise control for processes, etching equipment has also become more
diversified and specialized to meet the requirements for various applications in its
development.
Etching equipment is a high-tech product created by integrating the most
advanced technologies such as plasma generation, new materials, ultrahigh vacuum,
precision machining, automation, software control, and other fields. It is also one of
the most complicated equipment with high technology barrier for chip production.
The selling price of an advanced etching system with four chambers for 300 mm
wafers may reach as high as five million USD. Currently, the USA and Japan are
leaders in etching equipment manufacturing. Major vendors include Lam Research
and Applied Materials from the USA, as well as TEL and Hitachi High Tech. from
Japan. In the past 10 years, China’s equipment manufacturers have demonstrated
remarkable progress in this field. The dielectric etching equipment, independently
developed by Advanced Micro-Fabrication Equipment (Shanghai) Inc. China (AMEC),
1444 Y. Pu

has been adopted in advanced mass production lines of some large domestic and
foreign chip manufacturing plants. Etching equipment for through-silicon via (TSV)
structures, developed by AMEC, has also been adopted for mass production in
several domestic and foreign packaging factories. In addition, silicon etchers devel-
oped by NAURA Technology Group Co., Ltd. have been adopted for advanced
processes in the mass production lines of Semiconductor Manufacturing Interna-
tional Corporation (SMIC). Meanwhile, in order to meet the requirement of low
damage and high selectivity for FinFET processes, a surface wave plasma etcher
with lower electron temperature has also been developed and the process evaluation
is implementing now.

Types of Plasma Etching Equipment

Aside from ion sputtering etching equipment involving almost purely physical
reactions and photoresist removal equipment involving almost purely chemical
reactions, plasma etching can be roughly classified into two categories according
to differences in the plasma generation and the control technology, namely capaci-
tively coupled plasma (CCP) etching and inductively coupled plasma (ICP) etching.
With these two categories, the types of plasma etching equipment are classified
below according to their structures [3].
For CCP etching, the RF power supplies are connected to one or both of the top
and bottom electrodes of the reaction chamber. Thus, these two electrode plates and
the plasma between them form a capacitor in the simplified equivalent circuit, as
shown in Fig. 68.1a. Its unique feature is that the driving current I1 is in the same
direction as the plasma current I2. This technology first appeared in two configura-
tions. The first was in the configuration of early plasma etching systems, in which the
RF power supply is connected to the top electrode and the bottom electrode
where the wafer is located is grounded, as shown in Fig. 68.2a. As a result, in
these systems the generated plasma can only form a thin ion sheath layer on the

Fig. 68.1 Simplified equivalent capacitive coupling and inductive coupling circuits
 68
Plasma Etch Equipment

Fig. 68.2 Structural diagram of eight typical plasma etching reactor

1445
1446 Y. Pu

wafer surface, and the ion bombardment energy is relatively low due to the weak
electric field in the sheath layer. This etching method is generally adopted for
processes such as silicon etching which uses radicals as the main etchants. The
second configuration is early reactive ion etching (RIE) technology, in which the RF
power supply is connected to the smaller bottom electrode where the wafer is located
and the larger upper electrode is grounded, as shown in Fig. 68.2b. This technique
enables the formation of a thicker ion sheath layer, which is suitable for dielectric
etching processes that require higher ion energies to participate in the reaction. On
the base of early RIE, a DC magnetic field can be added perpendicular to the RF
electric field to create a Lorentz force driving electrons along the E
B direction,
then the spiral moving trajectory of electrons can increase the probability of collision
between electrons and gas molecules, and thereby effectively increase the plasma
density and etching rate. This kind of etching is called magnetron enhanced reactive
ion etching (MERIE), as shown in Fig. 68.2c. The above three technologies have the
same weakness, which is that the plasma density and the ion energy cannot be
independently controlled. For example, in order to raise the etching rate, increasing
the RF power can be applied as a way to increase the plasma density. However, the
increased RF power will inevitably lead to an increase in ion energy, which may
generate plasma-induced damage to devices.
In the past 10 years, designs in capacitively coupled technology have generally
included multiple RF sources, which are either connected separately to the upper and
bottom electrodes or all RF sources connected to the bottom electrode. Through
proper selection of different RF frequencies and the design of electrode area,
spacing, materials, and other key parameters, the plasma density and ion energy
can be decoupled to the greatest extent possible, as shown in Fig. 68.2d. Among the
different RF frequencies, the high-frequency RF source, called as the source power,
is applied to control the plasma density, while the low-frequency RF source as the
bias power is connected to the bottom electrode to control the ion energy. However,
due to the intrinsic characteristics of capacitive coupling, the decoupling effect that
can be achieved by this method is limited. In addition, the kinetic energy loss caused
by ions moving back and forth following the direction of the alternative RF electric
field between electrode plates makes it impossible to obtain high-density plasma.
This situation is particularly evident under low pressure conditions.
For ICP etching, one or more sets of coils connected to the RF power supply are
placed on top of or around the reaction chamber. The alternating magnetic field
generated by the RF current in the coil enters the reaction chamber through the
dielectric window. This alternating magnetic field entering the reaction chamber
generates an induced alternating electric field, which accelerates the electrons to
collide with gaseous molecules and generates the plasma. In the simplified equiva-
lent circuit (transformer), the coil could be referred as the primary winding induc-
tance and the plasma as the secondary winding inductance (Fig. 68.1b), which is
characterized by the fact that the driving current I1 and the plasma current I2 flow in
opposite directions. At low chamber pressures, the plasma density of the etching
68 Plasma Etch Equipment 1447

apparatus based on this coupling method is generally higher than that of capacitive
coupling methods. In addition, the second RF power source is connected to the
electrode where the wafer is placed as the bias power to provide an adjustable energy
level for the ion bombardment. Therefore, the ion density depends on the source
power of the coil and the ion energy depends on the bias power, thereby achieving a
relatively complete decoupling of density and energy, as shown in Fig. 68.2e.
Another type of plasma etching technology known as electron cyclotron reso-
nance (ECR) plasma etching, shown in Fig. 68.2f, was invented even earlier and
remains in use today. Its plasma density and operational pressure range are close to
those of inductive coupling technology and are applied to the same kinds of etching
applications. The difference is that the plasma is generated using an external
magnetic field and an introduced microwave frequency. When the electrons’ cyclo-
tron frequency under the effect of the magnetic field reaches the resonance with the
microwave frequency, maximum absorption of microwave energy is achieved and
the electrons are thus accelerated to create plasma through the collision with gaseous
molecules. By the same mechanism, ion energy is controlled by another bias power
source connected to the bottom electrode where the wafer is located. Since the
internal and external structures of reaction chambers for this technology are fairly
complex, ECR technology has been surpassed by inductive coupling technology,
which has a much simpler structure and has gained wider applications.
During the same period, two other types of technology were developed, namely
helicon wave plasma (HWP) etching (shown in Fig. 68.2g) and surface wave plasma
(SWP) etching (shown in Fig. 68.2h). The former was not commercially successful
due to the complexity of its structure and control system, and the latter was not
widely applied in early years. However, the critical dimension of IC devices has
shrunken consistently in recent years (such as FinFETs) and the device performance
has become increasingly sensitive to the plasma-induced damages, thereby creating
an urgent need for etching technology with near-zero damage. Since SWP can
generate high plasma density close to those of ICP and ECR, but at a much lower
electron temperature, that is, ions in low electron temperature plasma result in lower
or even no plasma damage for devices, therefore surface wave plasma technology
has once again received attentions.
The reaction chamber structures and main technical specifications of the
abovementioned eight types of common plasma etching equipment are listed in
Table 68.2.
Additionally, there is one type of special etching technology that has been devel-
oping rapidly in recent years, known as atomic layer etching (ALE). The mechanism
of ALE is very similar to that of atomic layer deposition. Currently, Lam Research,
Applied Materials, and Hitachi Ltd. have already provided ALE equipment to IC
manufacturers for advanced products of 3D structures, such as nanoscaled NAND
flash and FinFETs. So far ALE technology is still developing and has gained a
growing number of irreplaceable applications in advanced IC manufacturing, the
market of ALE equipment will obviously keep growing in the near future.
 1448

Table 68.2 Reaction chamber structures and main technical parameters of eight main plasma etching equipment
Early Magnetron
Early reactive enhanced reactive Capacitively Inductively Electron cyclotron Helicon wave Surface wave
plasma ion etching ion etching coupled plasma coupled plasma resonance (ECR) plasma (HWP) plasma (SWP)
Equipment type etching (RIE) (MERIE) (CCP) etching (ICP) etching etching etching etching
Upper electrode RF Grounded Grounded + Grounded or RF Inductive coil Microwave and RF drive Microwave
(or upper reaction source magnetic field source connected to cyclotron antenna and
chamber) RF source resonance DC magnetic
magnetic field field
Lower electrode Grounded RF source RF source RF source RF source RF source RF source RF source
(wafer location)
Plasma density/ 108 108 ~ 109 109 ~ 1010 109 ~ 1011 1010 ~ 1012 1010 ~ 1012 1011 ~ 1013 1010 ~ 1012
cm3
Ion energy/eV ~0 <1000 100 ~ 1000 100 ~ 1000 10 ~ 100 10 ~ 100 10 ~ 100 10 ~ 00
Electron >5 >5 >5 >2 >2 >2 >2 ~1
temperature/eV
Reaction chamber >100 50 ~ 500 50 ~ 500 15 ~ 500 1 ~ 50 <1 <10 10 ~ 100
pressure/mTorr
Y. Pu
68 Plasma Etch Equipment 1449

Plasma Etching Equipment Application and Outlook

In integrated circuit production lines, plasma etching equipment is generally classi-

fied into three groups based on the kinds of materials to be etched: silicon etching
equipment, metal etching equipment, and dielectric etching equipment. Traditional
etching of silicon and metal tends to use etching equipment with lower ion energy,
such as inductively coupled plasma etching equipment, because the covalent bond-
ing structure in these materials is relatively weak. However, for the strong ionic
bonding structure in dielectrics, the etching of dielectrics is more suited for etching
equipment with higher ion energy, such as capacitively coupled plasma (CCP)
etching equipment. Due to the increasing specialization and refinement of process
requirements, the diversity of etching equipment, and the application of new mate-
rials, the distinction among the abovementioned classification has tended to become
vague. Table 68.3 lists various processes implemented by the plasma etching
equipment in IC manufacturing. In addition to IC manufacturing, plasma etching
is also widely used in the manufacturing for LED, MEMS, optical communication,
and other devices.
As the integration degree of chips increases, so does the complexity of
manufacturing processes; the proportion of etching process in the whole manufactur-
ing process is also showing an upward trend (see Table 68.4). Therefore, etching
equipment makes up an increasing proportion of total equipment expenditures on a
production line. According to market statistics, the global sales of dry etching
equipment accounted for about 10% of total equipment sales in 2011 and have
increased to 20–25% at present. The growth rates of etching equipment adopted for
different materials being etched have risen and fallen at different stages of
manufacturing technology. For example, when copper interconnect technology
emerged in the 0.13 μm node, the proportion of metal etching equipment decreased
while that of dielectric etching equipment increased greatly. Later, due to the
emergence of multiple patterning technology at 32 nm node and resulting growth

Table 68.3 Main processes implemented by plasma etching equipment in IC manufacturing

IC Type Main processes
Logic STI, polygate, spacer, contact, via, trench, dual damascene, pad, stripping, SMT
circuit etching, SPT etching, and DSL etching
NAND High aspect ratio trench, hard mask, stair step, and channel hole etching
Packaging Thinning, tapered hole and trench, through-silicon via, cavity etching, and plasma
dicing

Table 68.4 Rough estimates of IC manufacturing process steps for each technical node
Process node 65 nm 45 nm 28 nm 20 nm 14 nm 10 nm 7 nm
Number of etching steps 20 30 40 55 65 110 150
Number of total process 1000 1100 1300 1500
steps
Data source: Merchants Securities
1450 Y. Pu

of soft etching applications, the proportion of silicon etching equipment has

increased rapidly [4].
The advantages and disadvantages of etching equipment are mainly reflected in
two aspects: (1) whether various requirements of the etching process can be met to
achieve better electrical performance and higher yield and (2) whether the maximum
output can be achieved at the lowest cost (including equipment as well as consum-
ables such as energy, gases, and reaction chamber consumable parts). Table 68.5 lists
the important parameters checked by manufacturers to evaluate etching equipment.
With the continuous advancements of IC technology, the feature size of devices
keeps shrinking (e.g., linewidths of logic devices are already at 3 nm node). New
structures (e.g., NAND and FinFET), new materials (e.g., high-k dielectric/metal
gates and ultralow-k dielectrics), and new technologies (e.g., copper low-k dama-
scene etching and multiple patterning) are emerging. As a result, the requirements
for etching processes mainly focus on the following aspects: (1) more precise control
of various etching parameters; (2) higher etching selectivity; (3) enhancement of
etching for structures with extremely high aspect ratios; and (4) minimizing plasma-
induced damage to devices. Therefore, main areas of development in etching
equipment include more adoption of pulsed plasma to realize the fine control of
ion energy and its distribution, providing with extremely high ion energy or
extremely low ion energy, as well as the lower plasma charging and optical radiation.
It is necessary to continuously introduce new technologies for etching equipment
to meet the abovementioned new requirements. For example, atomic layer etching
(ALE) technology has been applied to achieve ultrahigh selectivity in self-aligned
contacts (SAC) etching process. Also, surface wave plasma (SWP) etching technol-
ogy has been applied for achieving extremely low plasma damage in etching FinFET
structures, and, moreover, neutral beam etching (NBE) is being adopted in some new
applications. These new technologies represent the development trends in the field of
new equipment. On the other hand, continuous improvement programs (CIP) in
existing equipment are another main approach to develop etching equipment [5].

Table 68.5 Important indicators for evaluating etching equipment

Important parameter Remarks
Etching rate Etching rate directly affects the productivity
Uniformity Including various uniformities, such as etching rate, feature size,
etching profile, as well as wafer edge uniformity in particular
Selectivity Including mask selectivity and under layer selectivity
Profile Including the cross-section angle and shape as well as the roughness
of the etching front
CD control For example, for 10 nm node, the deviation must be controlled within
1 nm
Particle For example, for 10 nm node, the number of particles with a diameter
over 30 nm should be less than10 on a 300 mm wafer
Mean time between Generally, it must be more than 300 RF hours (accumulated time with
clean (MTBC) RF sources turned on, commonly known as “RF hours”)
68 Plasma Etch Equipment 1451

Ion Beam Etching (IBE) Equipment

Ion beam etching (IBE) equipment uses ion beams generated from plasma to
bombard wafers and etch away materials via physical sputtering effect. Figure 68.3
shows the simplified schematic diagram of a typical IBE equipment. The equipment
consists of an ion source, an ion extraction assembly, and a reaction chamber. Argon
or other noble gases are led into the ion source chamber to generate low-temperature
plasma for providing low-energy ions. In earlier times, hot cathode (filament)
technology was applied to produce plasma. More recently, 13.56 MHz RF-driven
inductively coupled plasma (ICP) technology is adopted in most cases, and electron
cyclotron microwave resonance (ECR) plasma technology is also adopted to obtain
higher-density ions. This ion extraction assembly provides a channel to form the ion
beam and guides ion beam into the reaction chamber. This assembly is generally
composed of three grid plates, as shown in Fig. 68.3. The upper grid plate near to the
ion source connects to a positive voltage. The middle grid plate is provided with a
negative voltage, and the voltage difference between these two grid plates deter-
mines the energy of positive charged ions after the acceleration which generated in
the ion source. The lower grid plate near to the reaction chamber is generally
grounded and is applied to improve the ion beam quality and prevent the electron
backflow from the reaction chamber, as well as to keep the sputtering generated
by-products from contaminating the charged grid plates. The quality of the ion beam
is greatly affected by the spacing of these three grid plates, the shape and design of
grid plates, the distribution of through holes on each grid plate, as well as the
curvature of the grid plates and the selection of surface materials. The wafer etching
by the ion beam is implemented in the reaction chamber. This chamber generally
keeps a vacuum pressure of 105 to 106 Torr by a pumping system comprised of a
molecular pump and a mechanical pump. The helium cooling function of the wafer

Fig. 68.3 Simplified

schematic diagram of a typical
IBE equipment
1452 Y. Pu

chuck is applied to absorb the ion bombardment generated heat and control a stable
temperature of the wafer.
The wafer holder can adjust the angle between the wafer plane and the ion beam
to improve the control of the side wall morphology of etched structures and the
radial uniformity of etching. It can also rotate along wafer axis to improve the
axial uniformity of the etch rate. In addition, some advanced IBE equipment
assemble a neutralization function in which an electron source, such as a hot
cathode filament, is placed in the downstream of the extraction assembly to provide
an appropriate amount of electrons for neutralizing part of ions in the ion beam.
This function could reduce the beam divergence caused by space charge effects
and the charge accumulation on wafer surface [6].
Ion beam etching using noble gases is essentially a pure physical reaction and is
also called ion milling. This technology has good etching anisotropy and theoreti-
cally can etch any kind of materials, but it has some disadvantages of low selectivity,
low etch rate, and residues deposition from reaction products. There are two
improvement methods that involve adding a small amount of reactive gases. One
is called reactive ion beam etching (RIBE), in which a small amount of reactive
gases, such as SF6, CHF3, CF4, O2, or Cl2, etc., are added to the ion source along
with noble gases. The other is called chemically assisted ion beam etching (CAIBE),
in which the reactive gas is directly introduced through a jet ring located around the
wafer. In RIBE, the reactive gases are subject to two dissociations to form etching
radicals for chemical etching. One is caused by the electromagnetic field inside the
ion source, and the other is caused by the collision with accelerated ions on the wafer
surface. In CAIBE, the reactive gases only experience the dissociation process
caused by the collision with incident ions, which allows the ion density and the
radical density to be controlled independently.
IBE is mainly applied for etching certain special materials that cannot form
volatile products, such as Au, Pt, Ag, and NiCr. It is also applied for anisotropic
etching of certain organic materials, III-V compounds, and other heterostructure
materials, as well as wafer surface cleaning.
Progress made in other etching technologies, such as capacitively coupled and
inductively coupled plasma etching, which currently dominate the etching equip-
ment market, have greatly improved their etching anisotropy, etching ability for
different materials, and etch rate. As a result, the application of IBE is quite
decreased in mass production lines. However, in the abovementioned mainstream
etching technologies, wafers are directly exposed to the plasma in which the plasma
direct contact mode can cause two unavoidable disadvantages. One is that the
charging-up effect of charged particles (electrons and ions in plasma) on wafer
surface will cause the distortion of etching profile. And another is that the non-
uniform plasma causes spatial variation of instantaneous current or voltage on the
wafer and it in turn leads to the plasma-induced damage (PID) in IC devices. As the
dimension of IC devices are getting smaller and 3D structures are becoming more
common, the influence of these two disadvantages on chip yield is increasing.
Therefore, neutral beam etching (NBE), an etching technology derived from IBE
that dates back to the early 1990s, has attracted more attention in recent years. In
68 Plasma Etch Equipment 1453

short, the extraction assembly in NBE can completely neutralize the ion beams and
allow more accurate control and adjustment for the energy of neutralized ions. The
neutralization mechanism is mainly the charge exchange or the surface recombina-
tion. The former achieves partial neutralization by the charge exchange between the
electron beam and accelerated ions, and the un-neutralized ions are reflected back to
ion source by an oppositely biased grid plate or a magnetic field. The latter
implements neutralization through the recombination caused by the collision
between ions and the grid plate surface [7].

Plasma Etching Equipment

In a general sense, etchants applied in all dry etching processes are directly or
indirectly generated from plasma. While the plasma etching specifically described
is only classified as one form of the general dry etching technologies, in early stages
there were two types of planar plate reaction chamber design for dry etching. In one
design, the electrode plate where the wafer located is grounded as the cold electrode
and the other electrode plate is connected to the RF source as the hot electrode. This
design is called plasma etching mode, in which the area of this grounded plate is
usually larger than that of the hot electrode, and the reaction chamber operates at a
relative high pressure. Therefore, a very thin ion sheath layer is formed on the
grounded wafer surface, as if the wafer is being soaked in plasma. Etching is thus
mainly achieved by the chemical reaction between the radicals in the plasma and the
surface material of substrates, while the ion bombardment energy involved is very
low and shows less effect on the etching process. The other design uses the opposite
arrangement. The wafer is placed on a smaller electrode which is connected to the
RF power source as the hot electrode. This design scheme is called reactive ion
etching (RIE) mode in which the energetic ion bombardment plays a greater role in
the etching process [8].
Figure 68.4a is the schematic diagram of a typical multiwafer planar plasma
etching equipment. The RF source connects to the upper electrode of the reaction
chamber, the lower electrode where wafers are placed is grounded, and the metal
chamber wall is also grounded in most situations. As a result, the total grounding
area is larger than that of the source electrode, and the ion sheath layer on the upper

Fig. 68.4 Simplified schematic diagram of plasma etching equipment

1454 Y. Pu

electrode surface is much thicker than that on the wafer surface, therefore the
upper electrode subjects a higher level of ion bombardment. Both the upper and
lower electrodes have separate cooling circulation functions for removing the ion
bombardment generated heat and controlling the wafer temperature, respectively. As
shown in Fig. 68.4a, etching gases are introduced from the top or side of the reaction
chamber or under the wafer susceptor, and then pass through the wafer surface to
implement the reaction. After that, these gases and by-products are then evacuated
out of the reaction chamber from its outlet at lower part. The reaction chamber has an
operation pressure of 0.1–10 Torr.
Figure 68.4b is the schematic diagram of a barrel-type multiwafer plasma etching
equipment. The reaction chamber wall is made of quartz. The electrodes, in the form
of semicircular columns surrounding the quartz chamber, are connected to a
13.56 MHz RF source and a grounding pad separately, then creating a capacitive
coupling effect and thus generating plasma. Alternatively, the coil can be wound
around the quartz chamber to generate inductive coupled plasma. Multiple wafers
are vertically placed in a quartz boat. Etching gases are introduced into the chamber
from its lower inlets and extracted out from the upper outlets. A cylindrical metal
isolation sheet with dense of tiny through holes, positioned between the wafer and
the chamber wall, is applied to block most of charged particles but only allow neutral
radicals to diffuse into the wafer area to implement the chemical reaction with
wafers. Basically, charged ions are not involved in the reaction. This kind of plasma
etching equipment is the earliest type to be successfully adopted in IC
manufacturing.
With very few or even no ion bombardment, plasma etching equipment is
generally applied for photoresist removal and large area silicon nitride etching
because of its isotropic character and high etching selectivity.

Reactive Ion Etching (RIE) Equipment

Reactive ion etching (RIE) is an etching process involved by radicals and ions
simultaneously, in which the main components of the etchant are radicals and
ions that formed through the dissociation and the ionization of gaseous molecules
with energetic electrons, respectively. Mainly to be dependent of the etching
system design, the radical density is rough to the 1–10% level of the gas density,
while the ion density is about 0.01–5% of the gas density. Radicals reach the
wafer surface and then are absorbed on the surface to chemically react with
surface atoms or molecules to form gaseous by-products. These volatile
by-products desorb from the surface and then are pumped out of the etching
chamber. Usually, this chemical reaction by radicals only will be very slow,
however, with the assistance of ion bombardment on wafer surface in which
ions accelerated by the sheath potential above the wafer surface, the etching rate
will be extremely increased. Main functions of ions are as follows: (1) to break
the chemical bonds between the atoms on wafer surface to form dense dangling
68 Plasma Etch Equipment 1455

bonds that are vulnerable to etchant radicals, so the reaction rate is increased, and
(2) to enhance the removal of accumulated by-products from the surface through
the ion bombardment to expose a fresh surface for etchants, and thus maintain a
continuous etching process. In general, ions are not necessarily reactive in the
chemical reaction of etching, for example, in many cases argon ions are applied to
increase the ion bombardment for enhancing the etching reaction, therefore the
abovementioned etching process should be called ion-assisted etching instead of
reactive ion etching. Although RIE is not an accurate name, it has been
conventionalized and is still in use today [9, 10].
Since ion bombardment is essential for RIE, the main feature of RIE equipment is
the formation of the ion sheath layer. Figure 68.5a is the simplified schematic
diagram for a typical planar RIE equipment with asymmetric electrodes design. As
shown in the figure, the RF source connects to the lower electrode where the wafer is
placed, and its upper electrode is grounded. In order to form a larger sheath voltage
for more energetic ion bombardment on the wafer surface, the area of the lower
electrode is generally much smaller than that of the upper electrode. The chamber is
operated at a relatively low pressure, which is generally 50–500 mTorr. Usually, a
relatively thick plasma sheath will be established on the wafer surface, and the
electric field across the sheath layer could accelerate positively charged ions to an
energy level of 500 eV or above. The wafer holder (or electrostatic chuck, ESC) has
cooling functions to remove the ion bombardment generated heat and maintain a
stable process temperature throughout the etching process. A showerhead plate is
assembled to distribute etchant gases to the wafer evenly. An optical emission based
endpoint detection system is applied to monitor the etching reaction in situ and
determine the endpoint of etching steps. The chamber liner is equipped not only to
protect the chamber wall from the contamination during etching processes, but also
to favor the easy assembling and disassembling for the chamber preventive

Fig. 68.5 Simplified schematic diagram of RIE equipment

1456 Y. Pu

maintenance (PM) process. The quick replacement for the chamber liner in PM step
can greatly reduce the preventive maintenance time to increase the up time of
equipment.
The mentioned RIE is also called diode RIE etching. In order to improve the
control of etching, the second RF power supply for triode RIE is either connected to
the chamber wall, or to the upper electrode of reactor in which the chamber wall is
grounded. Because of its better performance in etching, the triode RIE design was
gradually evolved into so-called capacitively coupled plasma (CCP) etching equip-
ment, which is the one of the mainstream etching equipment commonly used at
present.
Figure 68.5b shows a simplified schematic diagram of a hexode etcher, another
type of RIE equipment developed earlier which once enjoyed great popularity in the
market. Wafers are manually placed on the six sides of a hexagonal cylinder, with
each side holding four wafers, enabling 24 wafers to be processed at a time. The
cylinder connects to the negative biased RF source as a cathode and also the chamber
wall (bell jar style) is grounded. In addition, the area of the grounded electrode is
about twice the size of the area of the cathode in which a higher sheath bias is formed
on the wafer surface. The gas distribution plate located between the chamber wall
and the hexagonal cylinder ejects the reactant gases for etching, and the evacuation
pump is equipped under the bell jar to control the operation pressure ranging from
20–100 mTorr.
As the electric field in the sheath layer is perpendicular to the wafer, the bom-
bardment of accelerated ions mainly breaks the bonding structure of wafer surface
layer and removes some deposits from the wafer surface. Therefore, the etching is
anisotropic. RIE technology is applied well for the etching of dense lines, dense
through holes, and structures with a certain high aspect ratio. Moreover, due to the
physical effects of ion bombardment, RIE can be applied to enhance the etching
performance for materials that cannot be etched effectively by chemical reaction to
form volatile products [11], such as insulators (e.g., SiO2 and Si3N4) and some
refractory metals (e.g., Ta, Mo, and W).
RIE equipment were accepted by etch equipment market in the early 1980s. Since
it equips only one RF source and the chamber design is relatively simple, its
capability has certain limitations in etching rate, uniformity, and selectivity for
advanced IC fabrication.

Magnetically Enhanced Reactive Ion Etching (MERIE) Equipment

Magnetically enhanced reactive ion etching (MERIE) is a type of etching equipment

that improves the etching rate by applying a DC magnetic field to the planar RIE.
During the etching step for advanced technology generations, collisions between
ions and other gaseous molecules will degrade the anisotropy of the etching process
for fine patterns and structures with high aspect ratios. Although a lower pressure can
increase the main free path of ions to suppress the ion scattering, this also leads to a
lower plasma density which will affect the etch rate.
68 Plasma Etch Equipment 1457

Based on the design of the planar etcher, an added DC magnetic field is perpen-
dicular to the direction of the electric field in sheath layer, in which electrons inside
or near the plasma sheath layer will experience a Lorentz force F ¼ qE þ qv
B
(q, charges; v, velocity; E, electric field; B, magnetic field). The direction of Lorentz
force complies with the right-hand rule and is perpendicular to both the electric field
and magnetic field. Electrons will drift in a cycloidal motion along the E
B
direction above the wafer surface (see Fig.68.6). This will prolong the lifetime of
electrons and thus increase the probability of electron-molecule collision, thereafter
it in turn enhances the plasma density. Electron drift caused by the DC magnetic field
will lead to an instantaneous nonuniformity of the spatial distribution in plasma
density, but this problem can be solved through the time averaging method by slowly
rotating the parallel magnetic field. Furthermore, under a low chamber pressure
condition, the magnetic line perpendicular to the chamber wall can also reduce the
electron density loss caused by the collision of electrons with the chamber wall.
Figure 68.7 is the simplified schematic diagram for MERIE equipment. The
design inside the reaction chamber is similar to that of planar RIE equipment.
There are two design types of external magnetic field. In the first design, multiple

Fig. 68.6 Cycloidal motion

of electrons driven along the
E
B direction above wafer
surface by Lorentz force

Fig. 68.7 Simplified

schematic diagram of MERIE
equipment
1458 Y. Pu

Fig. 68.8 Top view diagram of externally applied magnetic field

permanent magnet dipoles are such arranged with a gradual direction change around
the circular chamber so as to form a uniform magnetic field above the wafer. This is
called dipole-ring magnetron (DRM) etcher, as shown in Fig. 68.8a. DRM elimi-
nates the nonuniformity of spatial distribution in plasma density by mechanically
rotating the permanent magnet assembly. This design provides good etching unifor-
mity, but the magnitude of the magnetic field is not adjustable.
In the second type of design, two pairs of Helmholtz coils are equipped around
the reaction chamber to generate a DC magnetic field, as shown in Fig. 68.8b. The
rotational magnetic field for eliminating the spatial nonuniformity of the plasma
density is achieved by setting a phase difference between the driving currents in
these two coil pairs. The magnetic field strength and rotation speed can be
adjusted by controlling the magnitude and phase of the driving current. It becomes
as an RIE etcher with zero driving current, therefore realizes the design of two
modes (RIE and MERIE) in one equipment. However, the etching uniformity is
relatively poor.
The strength of the applied magnetic field is usually 50–200 Gs on the wafer
surface. The plasma density can reach 1010 cm2, and the operation pressure is
50–500 mTorr. In most cases, the magnetic field enhanced effect on the etch rate
decreases with an increasing pressure. MERIE equipment has similar applications as
RIE equipment and is mainly used for the anisotropic etching of dielectric materials.
The etch rate for silicon oxide (SiO2) can reach up to 1 μm/min [12].
MERIE equipment was adopted in etch market in the 1990s, when single-wafer
etching equipment dominated the industry. The main disadvantage of MERIE
equipment is the magnetic field induced the instantaneous nonuniform spatial
distribution in the plasma density. That is, a rotating magnetic field induced voltage
difference or vortex current during the etching process may damage the device
structures, such as the breakdown of gate oxide, or local heating of interconnection
metals [13]. For advanced ICs, fine patterned devices become more sensitive to the
nonuniformity of plasma. Therefore, the technology using magnetic field to
enhance the etch rate has been gradually replaced by parallel-plate RIE technology
with multiple RF sources, namely capacitively coupled plasma (CCP) etching
technology.
68 Plasma Etch Equipment 1459

Capacitively Coupled Plasma (CCP) Etching Equipment

A capacitively coupled plasma (CCP) etching equipment is an etcher that performs

etching by generating radicals and ions in a reaction chamber through the capacitive
coupling of a radio frequency (RF) (or direct current) power source applied to
electrode plates. The etching principle is similar to that of reactive ion etching
equipment.
A simplified schematic diagram for CCP etching equipment is shown in Fig. 68.9.
It generally adopts two or three RF sources of different frequencies, though some
support the use of direct current (DC) power sources. The frequency of the RF source
ranges from 800 kHz to 162 MHz, and the commonly used frequencies include
2 MHz, 4 MHz, 13 MHz, 27 MHz, 40 MHz, and 60 MHz. An RF source with a
frequency of 2 MHz or 4 MHz is usually called a low-frequency RF source, which
connected to the lower electrode where the wafer is located. This low-frequency RF
source is effective for controlling the ion energy, so it is also called “bias power.” An
RF source with a frequency above 27 MHz is called a high-frequency RF source. It
can be connected to the upper electrode or the lower electrode. It is effective for
controlling the plasma density, so it is also called “source power.” A 13 MHz RF
power supply is intermediate between high- and low-frequency RF power and is
generally considered capable of controlling both the plasma density and ion energy,
but both functions are relatively weak. However, it is noted that although the plasma
density and the ion energy can be adjusted separately within a certain range by the
power of RF sources of different frequencies (the so-called decoupling effect), they
cannot be adjusted and controlled with complete independence due to the charac-
teristics of capacitive coupling.

Fig. 68.9 Simplified diagram of CCP etching equipment

1460 Y. Pu

The operation pressure of the CCP reaction chamber used to be between 50 and
500 mTorr, but recently, due to the requirements for etching high aspect ratio
structures, the operation pressure can be as low as 10 mTorr, which increases the
mean free path and reduces the energy loss of ions due to less ion-molecule
collisions. The ion energy usually ranges from 100–2000 eV. For similar reason,
bias source with maximum power of as high as 15 kW has recently come into use to
produce energetic ions with energies of 2 keV or more, thereby enhancing ions’
ability to penetrate vertically into the substrates of extremely high aspect ratio
structures without deflection. Plasma density typically ranges from 109 to
1010 cm3, though with the use of high-frequency and high-power RF sources, it
can reach levels as high as 1011 cm3.
Regarding the mechanical structure of the reaction chamber, aside from the
adoption of showerhead for gas distribution and chamber liners which are widely
used, there are two other commonly utilized concepts. The first is plasma confine-
ment, which refers to a special plasma isolation mechanism to confine the plasma
close to the wafer surface without influencing the evacuation of reactant gases. This
allows more effective and stable plasma generation as well as the utilization of
plasma while reducing the deposition of reaction by-products on chamber bottom
where by-products are difficult to clean. The second concept is a mechanism for the
gap adjustment between the upper and lower electrodes. A device added to adjust the
gap between the upper electrode and the lower electrode in the reaction chamber can
improve the spatial distribution of plasma and gas flow as well as many other
parameters, so as to optimize the entire etching performance. For example, some
etching processes require dielectric etching and photoresist stripping to be performed
by one sequential step in the same chamber. As there is a large difference in the
gases, pressures, and RF powers used in these two etching processes, the gap
between the upper and lower electrodes must be adjusted to achieve the optimal
uniformity for each process. Damascene etching technologies include the etching of
trenches, holes, barrier layers, photoresist, and several different kinds of materials
and morphologies, therefore the gap adjustment of electrodes is especially important
for these etching technologies.
Because ion energy distribution (IED) has a significant effect on the etching
performance of fine features and the damage generation in devices, the development
of techniques for optimizing IED has become a key point in advanced etching
equipment. At present, a number of techniques have already been applied in
production, including multifrequency hybrid power supplies, DC superposition
(DCS), RF combined with pulsed DC bias, and source-bias synchronous pulsed
RF output. [14, 15]
Among the various types of plasma etching equipment, CCP etching equipment
is one of two major types with the widest applications. It is primarily used for etching
processes involving dielectric materials; for instance, in logic chip processes, it is
applied to etch gate spacers and hard masks in the front-end-of-line (FEOL) pro-
cessing, contact holes in the middle end of line (MEOL), and damascene and
aluminum bonding pad in the back end of line (BEOL). In addition, it is also used
for the etching of features such as high aspect ratio slits and channel holes as well as
68 Plasma Etch Equipment 1461

step contact holes in the fabrication of 3D NAND flash memory chip (for example,
in silicon nitride/silicon oxide structures).
The major two challenges for CCP equipment are ion energy control. The first
challenge is to provide extremely high energy for ions to implement the etching
process on high aspect ratio structures (such as channel holes etching and slit etching
for 3D NAND flash memory chips, which require an aspect ratio greater than 50:1).
The present method is to adopt an RF source with maximum power of up to 15 kW to
raise the ion energy. Meanwhile, cooling and temperature control for the reaction
chamber must be constantly improved to effectively remove the heat generated by
high-power RF sources. Besides, the development of new etching gases is necessary
to improve the etching capability. The second challenge is to extremely reduce the
ion energy for high selectivity etching and less device damage. In order to more
accurately control the type of radicals involved in the reaction and the ion energy
distribution to achieve the high selectivity for FEOL etching (such as the etching of
dielectric spacers for FinFETs), it is necessary to improve the pulsing techniques for
both the RF power sources and the injection of etching gases. Therefore, the
adoption of surface wave plasma (SWP) technology as the power source for the
atomic layer etching (ALE) can act as a new etching method, in which SWP
generates ultralow energy ions and the ADL provides the accurate pulsing tech-
niques for both the RF power sources and the alternative injection of etching gases.
Then the ultrahigh selectivity etching can be achieved by ALE technology.
As a critical equipment in advanced IC production lines, CCP etcher is primarily
supplied by Tokyo Electron Limited (TEL) of Japan and Lam Research of the USA.
These two companies account for over 70% market share of the dielectric etching
equipment (valued at about USD 4 billion in 2018). Recently, Advanced Micro-
Fabrication Equipment Inc. China (AMEC) Inc. also provides dielectric etching
equipment. Due to the effective cost the designs combine a unique decoupled technol-
ogy with a high-output dual reaction chamber architecture. A variety of AMEC etching
systems have already been in use in more than 25 production lines of international tier
one chip manufacturers for 7 nm generation mass production and 5 nm generation pilot
production. Fig. 68.10 shows an image of AMEC’s Primo SSC AD-RIE single-
chamber dielectric etching system. Using the popular cluster-style structure, this
equipment can accommodate up to six etch chambers and has already been utilized
for the contact hole etching in the mass production of 16 nm flash memory chips as
well as in critical etching steps to fabricate 3D NAND flash memory chips.

Inductively Coupled Plasma (ICP) Etching Equipment

Inductively coupled plasma (ICP) etching equipment is an apparatus that performs

etching by coupling the RF power to generate plasma in the reaction chamber
through the magnetic field via an RF coil. That is, as an RF current flows into the
coils which will generate a time varying magnetic field inside the chamber, mean-
while, an induced electric field through the inductive coupling is formed instanta-
neously. This inductively coupled electric field will accelerate electrons to collide
1462 Y. Pu

Fig. 68.10 Primo SSC

AD-RIE single-chamber
dielectric etching equipment
produced by Advanced
Micro-Fabrication
Equipment Inc.

Fig. 68.11 Schematic diagram of TCP-type ICP etching equipment and its equivalent circuit

with gaseous molecules to generate high-density plasma. Its etching mechanism is

also classified as the reactive ion etching (RIE) [9].
There are two main types of plasma source design for ICP etching equipment.
One type is transformer coupled plasma (TCP) technology developed by Lam
Research, as shown in Fig. 68.11. The RF coil is positioned on top of a dielectric
window above the reaction chamber, and RF current with a frequency of 13.56 MHz
generates an alternating magnetic field that is perpendicular to the window and
radially divergent centering at the coil axis. This alternating magnetic field penetrates
into the chamber and generates an induced alternating electric field parallel to the
68 Plasma Etch Equipment 1463

dielectric window, thereby dissociating the etching gases and generating plasma.
This design is very similar to a transformer in which the RF coil is the primary
winding and plasma inside the chamber is the secondary winding, therefore it is
called transformer coupled plasma (TCP) source. One of the main advantages of
TCP technology is its scalability. For example, a TCP design for 200 mm wafer can
be scaled up to 300 mm standard by simply increasing the coil size proportionally
while maintaining the similar etching performance.
The other type of plasma source design is decoupled plasma source (DPS)
technology developed by Applied Materials, as shown in Fig. 68.12. Its RF coil is
wound around a dome-shaped dielectric window. The mechanism for plasma gen-
eration is similar to that of the as-mentioned TCP technology, but it was claimed that
the gas dissociation is more efficient and thus results in a higher plasma density.
Since the inductive coupling of energy to the plasma is more efficient than the
capacitive coupling, and the plasma is mainly generated in the region near the
dielectric window, the plasma density is basically determined by the applied power
in the source RF supply connected to the RF coil, while the ion energy gained in the
plasma sheath layer onto the wafer surface is basically determined by the bias power.
Then ion density and energy can be independently controlled and thus the
decoupling is achieved [16].
Generally, the chamber operation pressure of ICP etchers is about 1–50 mTorr
(lower than that of CCP), the plasma density is 1010–1012 cm3 (higher than that of
CCP), and the dissociation rate of etchant gases can reach about 90%. The bias
power is typically less than 100 W and the ion energy may be tens of eV or up to a

Fig. 68.12 Schematic

diagram of DPS-type ICP
etching equipment
1464 Y. Pu

hundred eV (in recent years, the ion energy is often adjusted as low as 10 eV or even
below for some low-energy ion bombardment applications).
The design of RF coils is the critical point to obtain uniform plasma density and
uniform etching. In order to enhance the adjustability of the radial density distribu-
tion, multiple coil design and synchronous source/bias power control technology are
widely used. However, the capacitive coupling caused by the localized high voltage
on coils has always been an issue that ICP etchers need to solve. Although Faraday
shield technology can get rid of capacitive coupling, it comes at the expense of
plasma density and uniformity. Several 3D coil configurations developed by differ-
ent equipment manufacturers can effectively shield the capacitive coupling at a less
expense of the plasma density and uniformity.
In principle, ICP etching characterized by high plasma density and low ion energy
tends to be the chemical reaction. Its etching performance is very sensitive to the
composition of radicals in the plasma. Since the ICP chamber is usually quite large,
the surface condition of the chamber wall (e.g., temperature, type, and thickness of
deposits) has a significant influence on the composition of active radicals. Therefore,
maintaining stable chamber surface conditions is the key point to obtain a highly
reproducible etching. As a result, a wide variety of complex dry cleaning techniques
and procedure flows for chambers have been developed. Normally, cleaning gases
are applied to remove the accumulated deposits created on the chamber surface by
previous etching processes, and then different gases are fed into the chamber to
deposit a controllable and reproducible film onto the chamber wall surface. In order
to achieve a complete cleaning cycle, advanced technologies related to the precise
temperature control for chamber components and the rapid gas switching function
are adopted. In addition, since corrosive gases (e.g., chlorine and hydrogen bromide)
are usually applied to etch metals and semiconductors, the reaction chamber, main-
frame, and wafer transfer channels must be made of or coated with corrosion-
resistant materials.
ICP etching equipment is one of two most widely adopted plasma etching
equipment. It is applied in a variety of etching processes including shallow trench
isolation (STI), germanium (Ge), polysilicon gate, metal gate, strained Si, metal
wires, pads, metal hard mask in damascene, multiple patterning technology, etc. In
addition, as 3D IC, CMOS image sensors (CIS) and microelectromechanical systems
(MEMS) emerge recently, the demand for advanced etching technology in through-
silicon via (TSV), large taper holes and trenches, and deep silicon structure with
various profiles increases rapidly. So far equipment vendors have specifically devel-
oped several etchers for these applications. Their operation mechanism and tool
structure are very similar to those of ICP etchers but with features of high pressure,
high gas flow, and high RF power to achieve the capability of deep etching to tens or
even hundreds of micrometers. For example, a special etching method with a rapid
gas switching function, named as Bosch process, is applied for deep trench etching
in the fabrication of power devices and MEMS devices.
The challenges and improvement for ICP etchers mainly include the following
three aspects:
68 Plasma Etch Equipment 1465

1. Uniformity of critical dimension (CD): Most CD-critical etching processes are

performed by ICP etchers, such as gate structures, STI, and etching in multiple
patterning processes. Since the wafer temperature has a strong influence on the
CD variation during the etching process, the electrostatic chuck (ESC) is there-
fore adopted to keep a stable CD control. The main functional features of an ESC
include good temperature uniformity and repeatability across the wafer, capabil-
ity of multizone temperature control, and rapid temperature ramping up/down.
Especially the multizone temperature control is able to compensate the CD
nonuniformity caused by the previous step (e.g., photolithography). At present,
there are ESCs with over 100 temperature zones on the market.
2. Selectivity in etching: As the device feature size continuously shrink to nanoscale
nodes (especially since the emergence of FinFET), it is extremely critical to
increase the etch selectivity for reducing the loss of underneath layer. Therefore,
etch conditions must be precisely adjusted and controlled to allow the selective
deposition of reaction by-products. At present, relevant research has mainly
focused on controlling the bombardment energy of ions, such as synchronous
pulsing technique of source and bias power, RF waveform modification, high-
energy tail trimming by pulsed DC bias technology, etc.
3. Plasma-induced damage: Advanced IC devices have entered the era of atomic
scale with single electron or few electrons operation, which is extremely sensitive
to the plasma-induced damage. Reducing the electron temperature of plasma is
one of methods to minimize or completely eliminate the plasma-induced device
damage. One example is the adoption of surface wave plasma (SWP) technology
in which the electron temperature of plasma could be as low as 1 eV only.
Moreover, some researches propose the methods for neutralizing positive charges
accumulated on wafer surface by flooding negative ions generated by afterglow in
pulsed plasma, thereby reducing the device damage.

Electron Cyclotron Resonance (ECR) Plasma Etching Equipment

ECR plasma etching equipment is an apparatus which performs etching using the
electron cyclotron resonance effect in an external magnetic field to obtain high-
density plasma under low chamber pressures. This technology was first applied to
the ion source of ion beam etching (IBE) equipment, and ECR technology utilized
for etching processes is earlier than inductive coupling plasma (ICP) technology.
As shown in Fig. 68.13, an electron in a static and uniform magnetic field (B) will
move in a cycloidal motion around the axis of the magnetic field, and its cyclotron
frequency is:

ωc ¼ eB=me

where e is the electron charge and me is the electron mass. The linear electric field of
a microwave can be regarded as two components rotating at the microwave
1466 Y. Pu

Fig. 68.13 Basic principle of electron cyclotron resonance

frequency (ωm) on the microwave polarization plane by the right-hand rule and the
left-hand rule, respectively. When the direction of the magnetic field is
perpendicular to the plane of the electric field and the resonance condition, that is,
ωc ¼ ωm, is satisfied, the component with right-hand rotation continuously gain
energy in the entire rotation cycle, while for the component with left-hand rotation,
the gained energy is canceled out by the energy it loses in the whole rotation cycle.
The overall result is that electrons can gain maximum energy transfer from the
microwave through the resonance mechanism. That is the principle of electron
cyclotron resonance.
Figure 68.14 shows a simplified structural diagram of the reaction chamber in
ECR equipment. The 2.45 GHz microwave emitted from the magnetron propagates
through the waveguide and enters into the reaction chamber through the dielectric
window. The polarization plane of the microwave (i.e., the electric field plane) is
parallel to the dielectric window and the wafer surface, while the electromagnetic
coil placed around the reaction chamber generates a downward DC magnetic field
which is perpendicular to the plane of the microwave field. Only in a certain flat zone
between the wafer and the dielectric window, shown in Fig. 68.14, the magnetic flux
density satisfies the resonance condition of B ¼ meωm/e ¼ 875 Gausses. The
magnetic flux density gradually decreases in the direction close to the wafer. The
size, position, and current design of the electromagnetic coil not only serve to meet
resonance conditions and to determine the suitable position of the resonance zone,
68 Plasma Etch Equipment 1467

Fig. 68.14 Simplified structural diagram of the reaction chamber for the ECR plasma etching
equipment

but also to optimize the plasma uniformity at a specific gas pressure. The lower
electrode where the wafer is located usually is connected to a 13.56 MHz bias RF
power. The ion density is determined by the microwave power, and the ion energy is
determined by the bias power, thereby decoupling of plasma density and ion energy
can be achieved [17, 18].
The operation pressure of ECR etchers normally ranges from 0.1–10 mTorr,
which is lower than that of ICP etchers, but the plasma density can reach to 1011
to 1012 cm3, similar to or higher than that of ICP etching equipment. The bias
power level typically ranges from tens of watts to hundreds of watts. Because its
etching mechanism is similar to that of ICP etching, ECR is also classified as the
reactive ion etching (RIE). As like ICP, ECR is thus applied for the etching of STI,
silicon gate structures, hard masks, and metals too.
The main disadvantage of ECR etchers is due to its control of the external
magnetic field. The multiple coils not only occupy a large space but also lead to
problems in control. In order to improve the magnetic field distribution, a costly
larger chamber is required, and moreover, a strong magnetic field of 875 Gausses on
the wafer surface could generate plasma-induced damage (PID) to devices. As a new
improved arrangement, manufacturers have introduced a UHF-ECR version, which
uses an ultrahigh frequency (UHF) RF power supply at 450 MHz instead of the
conventional 2.45 GHz microwave. The frequency is one-fifth of the original one
and the magnetic flux density could be also reduced correspondingly to one-fifth of
1468 Y. Pu

the original high magnetic flux density, greatly reducing equipment size and com-
plexity as well as the effect of plasma-induced damage. In terms of biased power, a
frequency of 100–400 kHz is currently adopted for RF power sources to suppress the
plasma-induced device damage.

Helicon Wave Plasma (HWP) Etching Equipment

A helicon wave is a special electromagnetic (EM) wave that can propagate in the
magnetized plasma. Helicon wave is capable to convert the RF energy which is
prior fed to a driving antenna into the electrons of plasma chamber. Since the
polarization of such waves propagates in a spiral manner along the direction of
the applied DC magnetic field, they are called helicon waves, and the plasma
generated by such wave is called helicon wave plasma (HWP). The theory of
helicon waves is quite complicated and not easy to describe. Under a fixed
magnetic field, multiple modes of waves could be generated which is determined
by the plasma dispersion eqs. A certain mode of wave could be supported by the
specific antenna design with matched characteristics of DC magnetic field and
shapes of the plasma chamber. Figure 68.15 shows a structural diagram of

Fig. 68.15 Structural diagram of HWP etching equipment

68 Plasma Etch Equipment 1469

HWP etcher [19]. In this figure, the source EM coil creates a DC magnetic field
along the z direction to generate and sustain the helicon wave, and the lower
positioned chamber EM coil is applied to reduce the plasma loss in the reaction
chamber.
The performance of HWP etcher is similar to those of ICP and ECR etchers. They
are all operated at low pressure (10 mTorr or lower) with high plasma density
(1010 cm3 or higher). Plasma is generated at the upper part of the reaction chamber,
in which both bias drifted ions and free radicals flow downward to react with the
wafer. The ion energy is independently controlled by a bias RF power applied to the
wafer chuck.
From the perspective of energy conversion, the relationships among HWP,
ICP, and ECR can be simply revealed as follows. When the applied DC magnetic
field is zero or very small, the HWP antenna converts RF energy to the plasma in
a form that is equivalent to ICP. In case the magnetic field strength matches the
driving frequency for electron cyclotron resonance, the HWP antenna converts
RF energy to the plasma in a form that is equivalent to ECR (but in reality, there
are still some conditions that cannot be met). Compared with ICP and ECR, the
advantages of HWP are mainly described in the following three aspects.

1. The plasma density of HWP is higher than that of ICP: The electromagnetic wave
generated by the ICP coil can only reach the surface of the plasma due to the skin
effect, while a helicon wave can enter into the plasma. Meanwhile, due to the
Landau damping effect, an electric field can be applied to effectively accelerate
electrons by controlling the antenna length to make the phase velocity of the
electromagnetic field equal to the electrons’ thermal velocity (which is supported
by other interpretation models such as TG wave theory). In laboratory experi-
ments with argon gas driven by RF power of 1 to 2 kW, the plasma density
generated by the helicon wave can reach as high as 1013 to 1014 cm3. In real
HWP etchers, the actual plasma density is not as high as mentioned but still about
3–10 times that of ICP etching equipment.
2. Compared to ECR etching equipment, the HWP chamber has a simpler
structure: ERC etcher driven by a 2.45 GHz microwave requires a strong
magnetic field of 875 Gs to match the cyclotron resonance condition, while
HWP etcher only requires a magnetic field of 50–300 Gs, which greatly
reduces the difficulty in implementing the magnetic field. Moreover, a
13.56 MHz RF supply is much cheaper than a 2.45 GHz microwave generator
for the driving power.
3. The plasma density is more uniformly distributed: It is determined by the nature
of helicon waves. In addition, the design of the magnetic field can be customized
for a certain application to optimize the etching uniformity.

The first HWP experiment was completed by Australian scientist Boswell in the
1970s, and the commercialization effort began in the 1990s. Plasma Material
1470 Y. Pu

Technologies Inc. (PMT), a company founded by HWP experts, is dedicated to

applying this technology for etching equipment. The MORI (meaning: m ¼ 0 reac-
tive ion) helicon wave etcher developed by this company once showed good market
potential and went through a long serious of tests. “However, due to mistakes in the
company’s business decisions, there has been no success in commercialization of
this technology” (said by Francis Chen, UCLA professor, expert in plasma research
and the main developer of this HWP). From a technical point of view, the difficulty
of helicon wave mode control and plasma instability are among the important
reasons for its failure. Despite this, due to the advanced nature of this technology,
both the leading equipment manufacturers, Applied Materials and Lam Research,
have invested heavily to purchase the application licenses for the MORI helicon
wave design. Figure 68.16 shows a schematic diagram of MORI helicon wave
plasma etcher. In the figure, the MORI driving antennas are the upper and lower
coils with opposite current directions. This design can activate and support the zero-
order (m ¼ 0) helicon wave mode [20].
There has been ongoing research on helicon waves in the field of plasma research.
More than 2700 related papers have been published in the past 10 years. The
application studied are mainly microfabrication equipment and spacecraft propul-
sion technology related. F. F. Chen [20] predicts that the small permanent magnetic
helical tube developed by his team will be capable to generate a uniform plasma for
large area by applying multiple units, which has great commercial potential in the
future for large-diameter wafers in the IC manufacturing (etching or CVD processes)
and the large panel display manufacturing. Figure 68.17 shows a schematic diagram
of a multihelical tube array design. In addition, recent advances in HWP modeling
and simulation will also provide critical benefits for the HWP antenna design and the
plasma control [20].

Fig. 68.16 Schematic diagram of MORI helicon wave plasma etching equipment
68 Plasma Etch Equipment 1471

Fig. 68.17 Schematic diagram of a multihelical tube unit array design [2]
1472 Y. Pu

Surface Wave Plasma (SWP) Etching Equipment

Surface wave plasma (SWP) etching equipment is an apparatus that utilize the
surface waves formed by microwaves to generate the plasma and perform etching
processes.
As IC feature sizes continue to shrink to nm scales, and especially since the
emergence of 3D FinFET devices, plasma-induced damage (PID) shows an increas-
ing influence on device performance. One of the important factors that cause damage
is the plasma electron temperature. Therefore, minimizing the electron temperature
while maintaining high plasma density has become a key objective to be pursued. As
early as the late 1990s, SWP technology was once widely accepted due to its high
plasma density uniformity. Today, this technology has regained attentions and
applications due to the characteristics of low electron temperature. The mechanism
of SWP generation involves the energy coupling of the electromagnetic waves into
the reaction chamber to generate the plasma through the resonant cavity and the
antenna. When the plasma density at the interface between the dielectric window and
the plasma is higher than the cutoff density of the propagating electromagnetic wave
in the plasma, the electromagnetic wave can only propagate along the interface, that
is the surface wave. The plasma generated from the surface wave excitation has the
following three major advantages.

1. Plasma density similar to those of ICP and ECR can be obtained, but the electron
temperature is lower.
2. The plasma uniformity is high enough and is less affected by the design of the
reaction chamber and surrounding components, thus facilitating the scaling of
chamber dimension.
3. It can operate at a wide range of pressures, which allows more diverse applica-
tions for etching.

There are many surface wave generation technologies. Among them, the most
successful one is the radial line slot antenna (RLSA) technology derived from the
design of satellite antennas. A simplified schematic diagram of SWP etching equip-
ment based on this technology is shown in Fig. 68.18a. A 2.45 GHz microwave is
guided into the mode converter via the matcher and the waveguide tube. This
microwave is changed from TE mode to TEM mode and then is guided to the
antenna unit through the vertical coaxial waveguide tube. The antenna unit is
composed of three stacked flat plates including retardation plate, antenna plate,
and transmission plate. The metal plate in the middle is an antenna plate with a
multiple-slot layout. The slot shape is shown in Fig. 68.18b, and the distance
between slot units is generally equal to the microwave wavelength or half of the
microwave wavelength. The dielectric plate above the metal plate is a retardation
plate for reducing the effective microwave wavelength to match the antenna design
of the feature size. The lower dielectric plate is the ceiling of the reaction chamber.
This dielectric plate carries the surface wave which exposes to the plasma and is thus
called the microwave transmission plate. The plasma density and the electron
68 Plasma Etch Equipment 1473

Fig. 68.18 Schematic diagram of RLSA surface wave plasma etching equipment

temperature reach the maximum values on the ceiling surface and decrease gradually
in the downward direction. The lower electrode where the wafer is located connects
the bias power for providing the ion energy. Similar to ICP and ECR, the ion density
is independently controlled by SW power while the ion energy is adjusted by the bias
power in SWP etcher. The SWP etching reaction is still classified as a form of
reactive ion etching (RIE) [21].
The operation pressure of RLSA surface wave etchers is 5 mTorr to 5 Torr, which
is much wider than those of ICP and ECR etchers. Currently, this technology can be
applied to etch silicon, silicon oxide, silicon nitride, and various organic materials.
The plasma density near the wafer area is high above 1011 to 1012 cm3, and the
electron temperature could be as low as 1 eV only, which is the lowest value
comparing with other available etchers on the market. In order to minimize or
even eliminate the etching-induced damage of FinFETs, as a result, the surface
wave plasma technology has been applied to perform the critical etching process
for advanced FinFET structures.
Since this equipment is mainly used for the front-end-of-line (FEOL) etching, the
requirements for the metal contamination generated during etching are very strict,
and thus the design and the selection of surface coating materials for chamber
components (especially those located near the top dielectric plate) must be persis-
tently improved. In addition, although the overall plasma uniformity generated by
the surface waves is better than that of ICP and ECR, the radial adjustability of the
plasma density must be developed to meet the requirements of different applications
as well as to compensate the plasma inhomogeneity caused by previous process
steps. For example, just like the function of magnetic field in ECR, one or more
additional coaxial magnetic rings are assembled above a suitable distance to the
antenna plate, and the distance relative to the top plate of chamber is controlled by a
stepping motor, thereby enabling to adjust the enhancement of plasma density for the
SWP etching equipment [22].
1474 Y. Pu

Atomic Layer Etching (ALE) Equipment

Atomic layer etching (ALE) technology refers to the etching that can be performed
to the precision of one atomic layer (equivalent to 0.4 nm). This requires the etching
process to be performed uniformly, atom layer by atom layer, and stopped at the
appropriate time and position of the structure in order to obtain an extremely high
etching selectivity. As IC enters the era of 10 nm and 3D structures, improving the
selectivity is the most critical and most difficult requirement to meet.
The concept of ALE evolves from the mature technology that has been widely
used in IC manufacturing, atomic layer deposition (ALD), so its principle is similar
to that of ALD, which is a cyclic process, as shown in Fig. 68.19. Each ALE cycle
can be divided into the following four steps:

1. Surface treatment (reaction A): The etchant a reacts with the surface material of
the wafer. The key point is that this reaction only occurs on the surface of the
material being etched and is self-limiting; that is, the etchant only reacts with one
atomic layer on the surface without effecting the next layer.
2. Conversion step: The excess etchant a is completely pumped out of the chamber
and the other process parameters are adjusted to prepare for the next step.
3. Surface etching (reaction B): The treated surface material reacts with the etchant
b to form volatile products which are moved away from the wafer surface. The
key point is that only one atomic layer on the treated surface is removed and other
materials are not affected.
4. Conversion step: The excess etchant b and volatile products are completely
pumped out of the chamber and the other parameters are adjusted to prepare for
the next cycle step [23, 24].

Based on the abovementioned ALE mechanism, there are a variety of available

ALE methods. Currently, two popular methods are as follows:

1. In the method first adopted by Lam Research, reaction A is done through the
chemisorption and reaction B is implemented through an ultralow energy ion
sputtering. Taking silicon etching as an example, the etchant a is chlorine gas,
each active chlorine atom (radical) in the plasma combine with a dangling bond of

Fig. 68.19 Basic principle of ALE

68 Plasma Etch Equipment 1475

Fig. 68.20 Variations of main parameters of ALE process for silicon etching

the silicon atoms in the most surface layer by the chemical adsorption to form a
Si-Cl bond with a strong binding energy (4.2 eV), this reaction weakens the Si-Si
bond between this Si atom and its three other neighboring Si atoms by reducing
the bonding energy from 3.4 eV to 2.3 eV. The etchant b is argon ions, which
bombard the treated wafer surface under a certain bias voltage. When the bias
voltage is adjusted to make the bombardment energy of argon ion between 2.3 eV
and 3.4 eV, only the weakened silicon atoms on the surface layer will be sputtered
off, while the unweakened silicon atom on the next layer will not be affected.
Figure 68.20 shows the variation of main process parameters in reaction chamber
during the silicon atomic layer etching. This method can be implemented using
existing etching equipment, such as the ALE etcher introduced by Lam Research
is a modified version of its original FlexTM series capacitively coupled plasma
etching equipment with the addition of hybrid pulse technology.
2. In the method adopted by Applied Materials, reaction A is also an adsorption
process, but reaction B is a vaporization process. In the case of silicon oxide
etching, the etchant a is mainly composed of ammonia (NH3) and nitrogen
trifluoride (NF3), which are dissociated into active radicals (such as NH4F or
NH4 FHF) in a remote plasma source. These radicals downward diffuse to the
wafer surface and react with the silicon oxide, generating solid reaction product
(NH4)2SiF6 as well as gaseous NH3 and H2O. This is a self-saturation process. In
reaction B, on the other hand, the wafer is raised vertically to the high-
temperature top plate of the reaction chamber, so as to raise its temperature to
the temperature (about 150  C) that sublimates (NH4)2SiF6 and simultaneously
fills it with a noble gas (etchant b, which does not participate in the reaction) to
facilitate the extraction of sublimated gaseous compounds from the reaction
1476 Y. Pu

Fig. 68.21 Simplified schematic diagram of ALE equipment (SiConi™)

chamber together. Figure 68.21 shows the simplified schematic of applied mate-
rials’ equipment (SiConiTM) using this ALE method.

ALE not only has a very high etching selectivity, but the microloading effect of its
etching rate is almost zero due to the guarantee of self-saturation effect. This is
because only one atomic layer is removed in each cycle on the wafer, no matter
whether the reaction is fast or whether the reaction is slow. In addition, the plasma
used by ALE is quite weak, and some even use remote plasma source (RPS) to make
the reaction chamber without ions. The ultraviolet radiation and charges carried by
the plasma are also very small, so the electrical damage to the device is very small.
ALE technology has a wide range of applications, such as interfacial oxide etching
and FinFET-related etching that require zero damage to silicon surface, trim of
FinFET structure and shallow trench isolation (STI) structure with very little material
removal, spacer etching in multiple patterning process with zero residue, and many
other etching applications for 3D flash and DRAM devices.
However, the application of this technology is still in the preliminary stage, and
the corresponding equipment is still not mature, which is still quite far from the
above ideal ALE applications. For example, reaction A is not completely self-
limiting, that is, it will still affect the next atomic layer to some extent, and
reaction B, in the case of argon ion bombardment, will also damage the underlying
atoms to a certain extent. In addition, its cyclic mode of multiple conversion steps
lead to an extremely low etch rate, which is a major weakness in production
applications. However, due to its huge market potential and the urgency of this
type of equipment for the further development of advanced devices, the development
of related technologies has received great attention, and there are generally four key
research directions listed as follows:
68 Plasma Etch Equipment 1477

1. By the further improvement of RF pulse synchronization technology and using

radiofrequency (RF) waveform modification method to achieve a narrower ion
energy interval and an extremely precise control ability.
2. To achieve the extremely low electron temperature by introducing electron beam
(e-beam) plasma technology.
3. To extract large flow of neutral particles from plasma by using special filtering
technology.
4. To get rid of the pure cycle mode in the etching method, and adopt the combi-
nation of continuous and cyclic methods, or adopt the pure continuous method to
increase the etching rate, but still can maintain an extremely high selectivity.

Plasma Stripping Equipment

Plasma stripping refers to a dry stripping process that uses the radicals generated
from oxygen, nitrogen, or hydrogen plasma to decompose the photoresist to form
volatile by-products on wafer surface. The photoresist is mainly composed of
carbon, hydrogen, and oxygen. It is converted to carbon dioxide, water, and oxygen
after being “burned” by oxygen radicals. This process is similar to the ashing process
in which solid waste is burned by oxygen, so this plasma stripping process is also
called the ashing process. Methods for removing photoresist are divided into wet and
dry methods. For dry stripping equipment, besides those who use plasma sources to
generate radicals, there are also strippers using ultraviolet lights to irradiate ozone
and generate oxygen radicals.
In chip manufacturing, photoresist stripping is necessary in whatever processes
where the photoresist mask is used, such as etching and ion implantation. There are
many different required stripping conditions for various substrate materials, and
these stripping conditions in turn determine the choice of adoptable stripping
equipment. Besides the main necessary radicals for photoresist stripping, the plasma
itself is also accompanied by ultraviolet radiation and a large amount of ions. These
UV photons and ions will damage the gate oxides of MOSFETs by generating oxide
trapped charges inside the gate oxides, thereafter the electrical performance of
MOSFETs could be degraded, such as the threshold voltage (VT) shift, gate leakage
current (IG) increase, and breakdown voltage reduction. Therefore, a remote plasma
source (RPS) is designed to isolate the plasma from the wafer. For processes that are
less sensitive to ions and UV radiation (such as hard mask etching in pattern transfer
and some via etching), traditional plasma etcher (including early barrel-type multi-
wafer processing equipment) can still be applied, in which the wafers can be directly
“soaked” in the plasma. In some cases, PR stripping process even could be
performed in the same etching chamber, so it is called in situ PR strip.
Figure 68.22 shows the simplified schematic diagram of a stripper with the
remote plasma source. It consists of the remote plasma source (upper chamber),
the plasma isolation mechanism, and the reaction chamber in which the wafer is
located. The plasma is generated and confined in the upper chamber. Neutral radicals
and ions which are neutralized by the isolation mechanism in the upper chamber
 1478

Fig. 68.22 Simplified schematic diagram of a remote plasma source stripper

Y. Pu
68 Plasma Etch Equipment 1479

diffuse downstream to the reaction chamber and react with the wafer. These neutral
particles are also called the downstream plasma. There are three main types of
remote plasma source designs, namely ICP driven, microwave driven, and toroidal
source driven. Among them, the ICP design is the simplest and its cost is low, but the
plasma density under high pressure is lower than that of the other two types. Also,
because of the large chamber wall area of the upper chamber, a portion of radicals
may be absorbed on the chamber wall surface and leads to a great influence on the
stability and repeatability of the stripping rate. Microwave and toroidal sources are
normally manufactured by the original equipment manufacturers (OEM). According
to the process requirements, equipment manufacturers then integrate specific plasma
sources into the etching reaction chamber for various applications. The toroidal
source is newly developed and demonstrates the advantage of producing a higher
plasma density. However, its disadvantage is that the manufacture of toroidal tubes is
quite difficult, so as to result in the limited material selection and the poor application
versatility.
The isolation mechanism generally consists of one or more flat plates with
through holes. The size and distribution of these through holes, the spacing between
the plates, and the spacing between the plate and the wafer show a direct impact on
the UV isolation quality and the stripping uniformity. The plate material is typically
metal, which is grounded or connected to a certain voltage to enhance the isolation
and the charge neutralization. The design of the isolation mechanism is the key to
prevent devices from charging-up or UV exposure. In addition, since all the radicals
involved in the stripping reaction go through this isolation mechanism, the stability
of its surface condition (in terms of such factors as temperature, surface roughness,
and chemical passivation) is critical to the reproducibility of the stripping rate. The
stripping process generally needs to be performed under high temperature to enhance
the stripping reaction, so the wafer is placed on a heated susceptor with a temperature
of 100–200  C.
The main gas used for photoresist removal is oxygen. The addition of a small
amount of nitrogen is able to increase the proportion of oxygen radicals, thereby
increasing the stripping rate. For substrate materials (such as low-k dielectrics and
TiN) that need to be protected from oxidation, hydrogen or a mixture of hydrogen
and nitrogen is used instead of oxygen, however the stripping rate is generally
reduced drastically [25, 26]. For photoresists with surface hardened pretreatment
by doping other elements (such as Si) or through a specific etching process, it is
often necessary to add a small amount of fluorine-containing gas (such as CF4) to
increase the stripping rate. Since the radicals participating in the reaction are not
directional, the stripping reaction is essentially isotropic.
In addition to the photoresist removal, plasma strippers can also be adopted to
remove residues from the etching process (residue removal) and scum left by the
photolithography process (descum). In recent years, due to the emergence of 3D
structure devices and the extensive use of multiple patterning processes, so-called
soft etching applications are increasingly applied. The basic requirements for soft
etching include high selectivity, certain degree of etching anisotropy, and small
1480 Y. Pu

amount removal on substance. Some of these applications can also be achieved in

stripper by adding a low bias RF power to the wafer susceptor.

Dry Cleaning Equipment

Wafer cleaning is a process step to remove foreign substances from the wafer surface
without causing damage. The cleaning process is divided into wet cleaning and dry
cleaning. Dry cleaning means that the whole process of foreign substance removal is
completed in a gaseous state, and the equipment performing this function is referred
as the dry cleaning equipment. In addition, some advanced cleaning equipment can
also perform the wafer surface pretreatment for subsequent process or wafer storage.
The foreign substances mainly consist of particles, organics, and metals, which
come from various sources, including residual products from the previous process
(such as polymers left by the etching process) and impurities generated from the
chamber components (such as flakes from damaged coatings and volatile materials
from lubricants), as well as cross-contamination (such as sweat and fibers) caused by
personnel operations, wafer transfer, and the storage environment.
Compared with wet cleaning, dry cleaning has the following five major
advantages:

1. It eliminates stiction damage and collapse induced by the surface tension of liquid
on fine patterns.
2. Less residues are left after the cleaning step and lead to reduce rinsing and drying
steps.
3. It is easy for gaseous cleaning agents to clean structures with high aspect ratios
through the gas phase diffusion to the deep bottoms.
4. It is safer and more environment friendly.
5. Dry cleaning equipment is capable to integrate with other process equipment
together in the same mainframe system to realize the modular operation and
improve the production efficiency.

The mechanisms of dry cleaning to remove foreign substances from the wafer
surface can be classified into three types, as shown in Fig. 68.23.

Fig. 68.23 Main dry cleaning mechanisms

68 Plasma Etch Equipment 1481

Dry cleaning equipment can be roughly classified into the following five types:

1. Plasma cleaning equipment: The cleaning mechanism is completed through

the plasma generated radicals and/or ions reacting with foreign substances on
the wafer surface (such as using oxygen plasma to clean residual polymers left by
the etching process). Alternatively, cleaning process may be performed by using
energetic ions to sputter foreign substances (such as the native oxide removal with
Ar+ sputtering prior to the PVD deposition). The function of this kind of
equipment is very similar to that of photoresist stripping equipment or RIE
etchers.
2. Vapor phase cleaning equipment: This kind of equipment is further divided into
HF vapor type for cleaning oxides, UV/O3 vapor type for cleaning organic
substances, and UV/Cl2 type for cleaning metal compounds. The vaporized
cleaning agent can quickly diffuse into fine structures, and it is very chemically
active. Therefore, the cleaning efficiency is much higher.
3. Cryogenic aerosol cleaning equipment: An inert gas (such as argon or nitrogen) is
cooled down to a gas-liquid mixed state and then is injected through a high-
pressure nozzle into the lower-pressure process chamber. This liquid instanta-
neously expands and is converted into many crystalline fine aerosol clusters,
which thereafter react with the surface particulates and remove them away. This
cleaning method will not lead to additional chemical reactions, corrosion, or
damage on wafer surface. In particular, cryogenic aerosol cleaning technology
generates very minimal damage on low-k dielectrics used in copper interconnect
generations. Figure 68.24 shows a simplified schematic diagram of cryogenic
aerosol cleaning equipment [27].
4. Supercritical fluid cleaning equipment: The cleaning agent kept at a critical
temperature and under a critical high pressure will form an intermediate fluid

Fig. 68.24 Simplified schematic diagram of a cryogenic aerosol cleaning equipment

1482 Y. Pu

Table 68.6 Main applications for dry cleaning

Object Particles Organics Metal compounds Native/Others
Methods - Cryogenic - Ozone - UV/Chlorine - Argon ion
aerosol - UV/Ozone - V/Silicon tetrachloride sputtering
- Laser irradiation - Oxygen remote - UV/Hydrochloric acid - Hydrogen
- Carbon dioxide plasma - Hydrochloric acid remote plasma
vapor plasma

between liquid phase and gas phase, named as supercritical fluid. For example,
carbon dioxide can form as a supercritical fluid at a temperature of about 31  C
and a pressure of 74 atm. Due to its low viscosity and low surface tension, the
supercritical fluid as the cleaning agent shows a high diffusion rate to dissolve and
strip away foreign substances from the fine structure surface without creating
pattern collapse.
5. Other cleaning equipment for removing foreign substances at fixed points: This
equipment generally used together with an instrument that can detect the location
of fine particulates, and it includes technologies such as laser irradiation, atomic
force microscopy (AFM), nano-sweeping, nano-tweezer pickup, etc.

In FEOL processing of IC manufacturing, cleaning steps account for about

20–30% of the total process steps, therefore, the control of cleaning process is
very important to the yield of ICs. Among all cleaning steps, dry cleaning steps
account for about 10% in total advanced processes. With the IC dimension shrinking
and the emergence of 3D structures, dry cleaning technology may play a more
important role in IC fabrication and the market proportion of dry cleaning equipment
will also increase in the future. The main applications of dry cleaning technology are
shown in Table 68.6.
The gaseous cleaning agents of dry cleaning process are not so strong as the liquid
cleaning agents in wet cleaning process, and then results in inadequate cleaning
efficiency, especially for ultrafine particles or metal contamination in advanced
processes. In addition, dry cleaning is not efficient to remove particulates of large
quantity or large area, such as the post-clean for chemical mechanical polishing
(CMP).

Plasma Etching Equipment Platforms

There was no wafer transfer platform in etch equipment system in the early days. The
wafer was sent directly into the chamber in the atmospheric environment, and then
the chamber was pumped down to the required vacuum level for the subsequent
etching. After IC manufacturing entered the era of single-wafer processing, plat-
forms were introduced in order to improve the productivity and meet the require-
ments for the contamination control. In particular, after 300 mm wafers started, the
international industry association, Semiconductor Equipment Materials International
68 Plasma Etch Equipment 1483

(SEMI), established an industry standard of the wafer isolation for wafer fabs, that is
Standard Mechanical Interface (SMIF). Since then, platforms become an assembly
of standard configuration for etching equipment as well as other wafer process
equipment.
Figure 68.25 shows a simplified schematic diagram of a typical platform used for
the etching equipment. It mainly consists of a load port, an equipment front end
module (EFEM), a load lock (LL), a transfer module (TM), and a process module
(PM).

1. Load port: An assembly is usually equipped with two or three front open unified
pods (FOUP) and some are equipped with four or more.
2. Equipment front end module: It is at atmospheric environment with a stable
filtered air flow inside to reduce the possibility of particulates contamination
and other cross-contamination. The main components are an atmospheric robot
and a wafer aligner.
3. Load lock: A load lock chamber is an unit equipped in between EFEM and the
transfer module. The wafer holder inside can hold a number of individual wafers
which are moved to and from between the EFEM and the transfer module. This
load lock allows wafers to be transferred into the transfer module without venting
the transfer module to the atmosphere. Therefore, it has its own high vacuum
pumping system and venting to control the chamber pressure.
4. Transfer module: This module is at vacuum environment to connect multiple
reaction chambers with the vacuum robot which transfers wafers to and from
between the load lock chamber and process chambers.
5. Process module: The reaction chamber is always under vacuum in which the
etching or other fabrication processes are performed.

Fig. 68.25 Simplified

schematic diagram of a typical
etching equipment platform
1484 Y. Pu

Fig. 68.26 Five main types of platforms applied in etching equipment

Figure 68.26 shows five main types of platforms applied in the etching equip-
ment, among which the hexagonal 4xsingle-station type, the quadrilateral 3xdual-
station type, and the quadrilateral 6xsingle-station type are classified as the central
cluster style.

1. Hexagonal 4xsingle-station type: The shape of the transfer module is a regular

hexagonal structure. There are six connection sides in the normal configuration
shown in Fig. 68.26a, four process chambers and two load locks are connected to
the transfer module together. Sometimes five PMs and one LL are also adopted
for special purposes. This is a widely adopted platform. The Centura series
produced by Applied Materials and the 2300 series produced by Lam Research
are both equipped with this hexagonal type.
2. Quadrilateral 3xdual-station type: The TM is a square-shaped structure. As
shown in Fig. 68.26b, three dual-station PMs and one pair of load locks are
individually connected to each side of the main transfer module. The dual station
chamber is designed to process two wafers simultaneously for effectively increas-
ing the throughput (TP). This type is adopted by the Primo series products
by AMEC.
3. Quadrilateral 6xsingle-station type: The shape of the TM is a large square
structure shown in Fig. 68.26c. Each of three sides is individually connected to
two single-station process chambers, and a pair of load locks is connected to the
front side of the TM. Recently, this platform equipped with a total of up to six
PMs has been widely adopted due to its high processing throughput. This
configuration has been adopted by TEL for the Tactra series products and by
Applied Materials for the Centris series products.
68 Plasma Etch Equipment 1485

4. Linear structure type: The shape of the TM is a rectangular structure shown in

Fig. 68.26d, in which three or four process chambers are connected to each long
side of this transfer module. A load lock pair is connected to the front side of this
rectangular transfer module. The vacuum robot can move back and forth linearly
along the long sides. Apart from the advantage of high processing throughput, the
main feature is that the TM can be extended to connect more process chambers.
This allows the equipment to achieve modularization production in which mul-
tiple different process steps could be completed in a vacuum environment.
5. Serial cluster type: As shown in Fig. 68.26e, the design of platforms with clusters
connected in series can also increase the number of process chamber. This type is
adopted by Applied Materials for the Endura sputtering system.

In order to increase the throughput by matching different transfer modules and

process chambers arrangements, vacuum robots are designed in various styles, such
as one arm with one vacuum blade, one arm with two vacuum blades, two arms with
two vacuum blades, arms with or without the move up/down function, etc. Similarly,
there are multiple types of load lock, such as connected load lock pair in which two
LLs connected together with one pumping/venting system only, independent pair,
and a two layer of four LLs design with upper pair and lower pair configuration. The
load lock can also have additional functions such as wafer cooling or preheating,
removing toxic or corrosive gas molecules carried by wafers, and removing photo-
resist. Process chambers connected with the platform can be the same kind of etching
units for the same applications, or the same kind of etching units for different
applications. Even different nonetching process equipment can be equipped in
series to the platform to form an integrated system. The most common form of
integrated system is the combination of etching PMs and photoresist stripping PMs.
Figure 68.27 shows the Primo DsA product manufactured by AMEC. It consists of
two dual-station D-RIE etchers and one dual-station stripper, which has been widely
adopted for aluminum pad etching processes in the mass production lines of a
leading foundry enterprise.

Fig. 68.27 Etching-stripping integrated system (Primo DsA manufactured by AMEC)

1486 Y. Pu

The throughput of an etching equipment is related to several factors. Apart from the
platform structure, it is also directly related to whether the system performs one single
process only or a sequential integrated process, the etching time for each single process
chamber, the pumping/venting speed of the load lock, the transfer speed of the robot,
the number of load ports, the wafer transfer mode (serial or parallel), etc. Besides the
pursuit of high throughput, the development trends for the platform also include
improving the accuracy of wafer transfer, the integration capability of different pro-
cesses, and the environment control for the entire wafer path in the system.

Materials Used for Chamber Parts in Plasma Etching Equipment

The material selection for parts inside the reaction chamber, especially those parts
exposed to the plasma, is an important factor of the equipment design, due to the
materials of parts critically affecting chip defects and metal contamination, as well as
the reproducibility, stability, yield, and production running cost. Apart from basic
electrical and mechanical requirements, the material selection should comply the
following criteria: High purity is needed to prevent contamination; the chemical
composition should be consistent with the etch gas (e.g., fluorine and carbon) or the
etched materials (e.g., silicon and silicon oxide) to avoid the introduction of other
impurities; and the erosion rate of parts in the plasma environment should be low
enough to increase the process stability and the lifetime of parts. Normally, the
conductive materials adopted for chamber parts include silicon, silicon carbide, and
aluminum alloys (e.g., 6061A alloy). The insulating materials include quartz (silicon
oxide), ceramics (aluminum oxide, aluminum nitride, and yttrium oxide), and
anodized aluminum oxide. Table 68.7 lists common materials adopted for chamber
parts in the plasma etching equipment, and the schematic diagram of mentioned parts
is shown in Fig. 68.28.
In some cases, one material cannot meet all the requirements, the choice of
appropriate materials for parts depends on the real circumstance and preference to
achieve a compromised solution. This is especially important for consumable parts.
Taking the most important consumable part in CCP etchers, focus ring that is placed
around the wafer, as an example, if quartz is selected, its high purity will be the most
preferred to achieve the low metal contamination. However, because quartz is eroded
very quickly in fluorine plasma, its lifetime will become too short. Therefore, the
adoption of quartz will not only increase the cost, but also force tool shutdown for
parts replacement very often and lead to reduce the online rate of the equipment. If
aluminum-based ceramics are selected instead, the focus ring’s lifetime will be
lengthened, however, aluminum molecules in ceramics will be sputtered out by
high-energy ions and react with fluorine radicals in the plasma to form nonvolatile
fluorides (e.g., aluminum fluoride AlF3). These fluorides deposited on the device
surface or on the photoresist near the edge of wafer will block the subsequential
removal of reaction products and photoresist. Fluorides-induced particle issue sig-
nificantly affects the wafer yield. A more suitable material is single crystalline silicon
68 Plasma Etch Equipment 1487

Table 68.7 Common materials of chamber parts in plasma etching equipment

Material Features
Quartz (SiO2) High purity, low cost, good thermal
insulation property, and poor
resistance to fluorine-based plasma
Single-crystalline High purity, low cost, good thermal
silicon (Si) conductivity, and poor resistance to
fluorine/chlorine-based plasma
Poly-crystalline Lower purity, lower cost, lower
silicon (Poly Si) plasma resistance (compared with
Si), and convenient for adjusting
conductivity
Silicon carbide (SiC) High purity, high cost, good
thermal conductivity, better
resistance to fluorine/chlorine
plasma than silicon and quartz
Aluminum Adjustable purity, high cost, good
oxide (Al2O3) thermal conductivity, good plasma
resistance, and prone to form
aluminum fluoride contamination
in fluorine-based plasma
Aluminum Adjustable purity, extremely high
nitride (Al3N4) cost, better thermal conductivity
than Al2O3, and good corrosion
resistance
Yttrium oxide (Y2 O3) Adjustable purity, low cost, very
high plasma resistance; usually
applied in the form of surface
coating due to poor solid thermal
conductivity
Anodized aluminum Low cost, poorer resistance to
(Anodized Al) plasma than ceramics, but better
than quartz and silicon
Aluminum (Al) Low cost, high conductivity, easy
in machining, low purity, and poor
resistance to chlorine corrosion
Applications in chamber parts
Dielectric roof, focus ring, window,
other parts for electrical insulation
and thermal insulation, etc.
Upper electrode, focus ring, plasma
confinement plate, etc.
Focus ring, etc.
Upper electrode plate, focus ring,
etc.
Top insulation plate of chamber,
gas sprinkler head, electrostatic
chuck surface of wafer, other
insulation parts, etc.
Dielectric roof plate, gas nozzle,
surface plate of electrostatic chuck,
other insulation and thermal
conduction parts, etc.
Dielectric roof plate, chamber wall
or liner, and plasma confinement
plate, etc.
Electrode surface, chamber wall
and liner surface, etc.
Chamber body, lower electrode and
base of electrostatic chuck, other
electrical conduction parts, etc.

or silicon carbide. However, as shown in Fig. 68.29, cheaper single crystalline

silicon performs a short service lifetime, while expensive silicon carbide shows a
slightly longer lifetime. Each material has pros and cons, therefore the material
selection will depend on the actual operation circumstances. For equipment with
requirements of high usage and high tool online rate, silicon carbide is the right
choice instead of single crystalline silicon. Recently, Yttrium oxide coated ceramic
focus rings are applied in etching systems, however, it is found that yttrium atoms
sputtered out by energetic ions still affect the edge of the wafer and then lead to a
yield loss. Whatsoever, due to its extremely low erosion rate, mature coating
technology, and low cost, yttrium oxide has been applied for other chamber parts
such as the upper electrode plate and upper insulation plate, in which the energy of
1488 Y. Pu

Fig. 68.28 Schematic diagram of chamber parts in plasma etching equipment

Fig. 68.29 Comparison of

etch rates for five common
materials under the same
plasma etching conditions

ions bombarded on the upper electrode is usually quite low and therefore not prone
to sputter yttrium atoms out. Figure 68.29 shows the comparison on the relative etch
rates of five common materials under the same plasma etching conditions.
The R&D of new materials for parts is an important subject for the advanced
etching equipment. For example, anodized aluminum used to be the material for the
upper electrode plate of CCP chamber, however, due to the breakdown of passive
Al2O3 layer and the aluminum metal–induced contamination, then polycrystalline
68 Plasma Etch Equipment 1489

silicon and single crystalline silicon were adopted to replace anodized aluminum
later. Nevertheless, the supply of large-area silicon plates and particles generated
from the black silicon in fluorine plasma environment become new issues. Until the
mid-1980s, the CVD SiC coating method is introduced to solve the “black silicon”
problem successfully and prolong the lifetime of electrode plates, so as to overcome
the barrier to produce large-area upper electrode plates for upgrading the equipment
structure to meet 300 mm wafers. Over the past dozen years, the development of
yttrium oxide coating technology and yttrium-containing ceramics has provided lots
of better choices for upper electrode plates and many other chamber parts. Currently,
more new materials are developing; for instance, graphene has demonstrated excel-
lent electrical and mechanical properties, and also high plasma erosion resistance. It
shows the potential as a promising material for chamber parts of the plasma
equipment.

The Electrostatic Chuck (ESC) in Plasma Etching Equipment

The electrostatic chuck (ESC) is an assembly unit that physically secures the wafer
by applying a Coulomb force and control its temperature. A large amount of heat is
produced during the plasma etching process, and wafer temperature is a key factor
that affects the etching effect and the passivating polymer deposition. Rapid removal
of heat on the wafer and control of temperature within the required range are
fundamental to ensuring successful etching, therefore the ESC is one of the most
important components in plasma etching equipment [28].
In early days, the mentioned functions were achieved by pressing the wafer edge
onto the susceptor using mechanical clamps, which would not only reduce usable
wafer area due to the mechanical contact between the clamp and the wafer edge, but
also cause nonuniform temperature due to the pressure being focused on the edge. In
addition, clamp-induced nonuniform electric field will lead to a low device yield
near the wafer edge. The invention of ESC and the maturation of the required
materials and manufacturing techniques solved the above problems effectively,
and significantly improved the production capability and the performance of micro-
fabrication equipment.
Figure 68.30 is a schematic diagram of an ESC assembly unit and two schemes of
ESC electrode design. The surface of ESC is a flat ceramic plate with electrode
embedded inside, and the gap between the chuck surface and the wafer can be filled
with the thermal conductive gas for heat transfer. The flat ceramic plate is bonded to
an aluminum base, which contains liquid cooling channels. This base is fastened on
the lower electrode with screws. In addition, the electrode designs for ESCs are
monopolar and bipolar types. According to principles of electrostatic attraction,
ESCs can be divided into Coulomb force types and JR (Johnson-Rahbek) types, as
shown in Fig. 68.31.
The Coulomb ESC has a nonconductive dielectric material (with resistivity of
over 1015 Ωcm) between the wafer and the electrode, such as aluminum oxide and
polyimide. When a high voltage of over 2 kV is applied to the electrode, charges of
1490 Y. Pu

Fig. 68.30 Schematic diagram of ESC system and two schemes of ESC electrode design

Fig. 68.31 Coulomb-force-type ESC and JR-type ESC

the opposite polarity are induced on the backside of the wafer, and the wafer is
chucked by the Coulomb force generated from the induced charges. Since there is no
charge movement inside the ceramic plate, the chucking and de-chucking processes
are fairly simple and fast, and is not dependent to the temperature of the chuck.
However, the disadvantage is that the chucking force is relatively weak, thus it is
necessary to apply higher voltages to hold the wafer.
The JR-type ESC has a dielectric material with a certain degree of conductivity
(with resistivity between 109 and 1012 Ωcm) inserted between the electrode and the
wafer, such as aluminum oxide ceramics doped with some TiO2 for this dielectric
layer. When voltage is applied to the electrode, the charges move through the
ceramic to the area near the chuck surface. This reduces the effective distance
between positive and negative charges and then increases the attractive force,
allowing the wafer to be chucked under relatively low voltages. However, since
the chucking and de-chucking involve the charge moving in the ceramic layer, the
charging/discharging process is complex and slow. Furthermore, the resistivity of
ceramics changes with temperature, and that the chucking and de-chucking behavior
is also somewhat affected by the temperature fluctuation of the chuck, thereby
increasing the complexity of control on wafer holding.
68 Plasma Etch Equipment 1491

Fig. 68.32 Relationship

between heat transfer
coefficient and wafer-chuck
distance

Since the heat generated by plasma reactions on the wafer cannot be effectively
transferred by relying on the mechanical contact between the wafer and the chuck
surface alone, the thin gap between the wafer and the chuck must be filled with
helium to enhance the heat dispersion from the wafer. Helium is chosen because it is
light weight and thus has a high molecular velocity, also the heat transfer coefficient
is about six times that of air. When the mean free path of helium molecules is larger
than the thickness of the thin gap, the effective heat transfer coefficient of helium is
proportional to its pressure and inversely proportional to the thickness of the thin
gap, as shown in Fig. 68.32. The thickness of this thin gap is related to the force of
electrostatic attraction, therefore the wafer temperature can be effectively adjusted
via the helium pressure and the applied voltage of the electrostatic electrode.
Additionally, ceramics with a high heat transfer coefficient can be adopted to
increase the heat conduction efficiency. For instance, aluminum nitride has a higher
heat transfer coefficient more than ten times that of aluminum oxide, but the cost of
aluminum nitride ceramic is much higher due to its more complex manufacturing
process.
Figure 68.33 is a schematic diagram showing the wafer chucking/de-chucking
procedure of a unipolar ESC and variations in wafer temperature. Firstly, the source
power is turned on to generate plasma and provide a path for establishing electro-
static force. Secondly, a DC voltage is applied to chuck the wafer in place. Then the
helium valve is opened for the heat conduction and finally bias power is turned on to
start the etching. After the etching step is completed, the above procedure is
performed in the reverse order for the de-chunking of the wafer. In actual operations,
this procedure is a quite complex involving many factors.
For example, the high bias power and the long etching duration will produce the
accumulation of residual charges on the wafer (especially wafers with oxides on the
backside), and wafer de-chunking must be achieved via an additional method such as
applying an appropriate amount of reverse voltage at an appropriate time. Moreover,
1492 Y. Pu

Fig. 68.33 Schematic diagram of wafer chunking/de-chunking procedure for unipolar ESC and
variations in wafer temperature

the condition of the chuck surface (e.g., roughness and deposition of nonvolatile
by-products) will change as ESC aging, which will affect the effective distance
between opposite charges, the effective contact area between the wafer and the chuck
surface, and the charging/discharging speed of the charges. This will lead to the drift
in wafer temperature and chunking/de-chunking properties. The best known method
(BKM) with a sufficiently wide process window must be found via other auxiliary
methods and repeated experiments.
As the etching results of advanced devices (especially post-etch structural dimen-
sions and edge roughness) become increasingly sensitive to the wafer temperature,
the precise control of wafer temperature related to ESC designs has become an
important benchmark for the development of etching equipment. The main devel-
opment directions of ESCs are as follows.

1. Dynamic temperature control: An electric heating device may be added to the

ceramic plate on the ESC surface, which not only provides cooling and thermo-
static functions, but also enables regulation of the wafer temperature as required
during different etching steps. The complexity of ESCs has increased consider-
ably in order to achieve the high-speed heating/cooling over large temperature
spans, with current speeds as high as 1.5  C/s and the temperature zone differ-
ences of over 20  C.
2. Multizone temperature control: In order to achieve the nanometer-level regula-
tion, apart from maintaining high-precision control of uniformity in the etching
process itself, it is necessary to compensate for nonuniformities caused by
photolithography steps, which means that there is a need to control different
areas of the wafer under slightly different temperatures as required. The original
design of two temperature control zones (separated by helium) have been
increased to four zone design (separated by the electric heating device), and the
ESC designs with over 100 zones are currently being developed and perfected
(with the latest designs based on semiconductor cooling mechanism).
68 Plasma Etch Equipment 1493

References
1. M.A. Lieberman, A.J. Lichtenberg, Principles of Plasma Discharges and Materials Processing
[M], 2nd edn. (John Wiley and Sons, Hoboken, 2005)
2. F.F. Chen, J.P. Chang, Lecture Notes on Plasma Processing [M] (Plenum/Kluwer Publishers,
New York, 2002)
3. V.M. Donnelly, A. Kornblit, Plasma etching: Yesterday, today, and tomorrow [J]. J. Vac. Sci.
Technol. A 31(5), 050825 (2013)
4. G. Yin, Invited Presentation in SEMI Industry Strategy Symposium, Half Moon Bay, California
(2017)
5. P.L.G. Ventzek, S. Rauf, T. Sparks, in Handbook of Semiconductor Manufacturing Technology,
ed. by R. Doering, Y. Nishi, (CRC Press, New York, 2008), pp. 21–21
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Press Inc., New York, 1989), p. 391
7. S. Samukawa, The 14th International Conference of Nanotechnology, Toronto (2014)
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demic Press Inc., New York, 1989), p. 339
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2012)
10. J.W. Coburn, H.F. Winters, JVST 16(2), 391–403 (1979)
11. S. Handa, in Plasma Etching: Fundamentals and Applications, ed. by M. Sugawara, (Oxford
University Press, Oxford, 1998)
12. A.V. Vasenkov, M.J. Kushner, JAP 95(3), 834–845 (2004)
13. K. Nojiri, K. Tsunokuni, J. Vac. Sci. Technol. B 11(5), 1819–1824 (1993)
14. T. Kitajima, Y. Takeo, T. Makabe, J. Vac. Sci. Technol. A 17(5), 2510–2516 (1999)
15. S. Banna, A. Agarwal, G. Cunge, et al., J. Vac. Sci. Technol. A 30(4), 040801 (2012)
16. J.C. Forster, J.H. Keller, in High Density Plasma Sources, ed. by O.A. Popov, (Noyes Publi-
cations, Park Ridge, 1996)
17. J.E. Stevens, in High Density Plasma Sources, ed. by O.A. Popov, (Noyes Publications, Park
Ridge, 1996)
18. S. Watanabe, in Plasma Etching Fundamentals and Applications, ed. by M. Sugawara, (Oxford
University Press, Oxford, 1998)
19. R.W. Boswell, Phys. Lett. 30A(7), p457–p458 (1970)
20. Francis F Chen, Plasma Sources Science and Technology, 24 (1), 014001 (2015)
21. C. Tian, T. Nozawa, K. Ishibasi, et al., J. Vac. Sci. Technol. A 24(4), 1421 (2006)
22. S. Samukawa, Appl. Surf. Sci. 192(1–4), p216–p243 (2002)
23. G.S. Oehrlein, D. Metzler, C. Li, ECS J. Solid State Sci. Technol. 4(6), 5041–5053 (2015)
24. K.J. Kanarik, T. Lill, E.A. Hudson, et al., J. Vac. Sci. Technol. A 33(2), 020802 (2015)
25. O. Louveau, C. Bourlot, A. Marfoure, et al., Microelectron. Eng. 73–74, 351–356 (2004)
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Wet Cleaning Equipment
69
Fuping Chen, Xiaoyan Zhang, Xi Wang, Zhaowei Jia, and Yinuo Jin

Contents
Overview of Wet Processing and Wet Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496
Bench-Type Wet Cleaning System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499
Bench-Type Wet Etcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
Single-Wafer Cleaning Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
Single-Wafer Cleaning System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
Nanospray Cleaning [6, 7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
Megasonic Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
Single-Wafer Scrubber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509
Single-Wafer Wet Etcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
Single-Bath Wafer Cleaner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
Cryogenic-Aerosol Wafer Cleaner [11, 12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
Chemical Mechanical Polisher (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
Stress-Free Polish Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
Copper Electrochemical Plating (Cu-ECP) Equipment [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525

Abstract
With semiconductor manufacturing development, it is necessary to perform a
damage-free process to remove particles, native oxide layer, metal contamination,
organic, sacrificial layer, and other residuals from the wafer surface. For the metal
line interconnect, the copper metal layer is deposited by electrochemical plating
on the seed layer. The metal layer and the oxide layer need to be planarized by
chemical-mechanical polish. All these processes could be summarized as the wet
process, which is based on liquid state deionized Water (DIW) or chemistries with
some physical auxiliary mechanism to react on the wafer surface. This chapter
presents an overview for semiconductor industry wet process tools, processes,
and applications, including the following: single-wafer-type scrubber, single-

F. Chen (*) · X. Zhang · X. Wang · Z. Jia · Y. Jin

ACM Research (Shanghai), Inc., Shanghai, China
e-mail: fuping.chen@acmrcsh.com

© Publishing House of Electronics Industry 2024 1495

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_69
1496 F. Chen et al.

wafer wet etch, single-bath wafer cleaner, cryogenic-aerosol wafer cleaner,

chemical mechanical polisher, stress-free polish equipment, and copper electro-
chemical plating equipment.

Keywords
IPA dry · Wet etch · Dry clean · SCCO2 · Cu plating · Polish · Striper

Overview of Wet Processing and Wet Equipment

The wet processing refers to processes which use chemical solutions in the integrated
circuit manufacturing process, including wet process cleaning, chemical mechanical
polishing (CMP), stress-free polishing (SFP), and electroplating.
The wet cleaning process is the use of specific chemical solutions and the
deionized water to clean the wafer surface according to different process require-
ments without causing damage. It involves the removal of particles, natural oxide
layers, organic matters, metal contamination, sacrificial layers, polishing residues,
and other substances during the IC manufacturing process.
Table 69.1 lists the types, sources, and main hazards of substances that are
removed in wet process cleaning.
In order to obtain high-yield and high-performance devices, the above six sub-
stances on the wafer surface must be controlled within the required specification of
the process in the IC manufacturing. At the current stage, the key technology node is
below 10 nm and the standards for controlling the contaminants on the wafer surface
are becoming increasingly stricter, so each process requires a step with a cleaning
procedure.
In order to remove the different substances listed in Table 69.1, it is necessary to
use different chemical solutions in combination with physical methods, depending

Table 69.1 Types, sources, and main hazards of substances removed in wet process cleaning
Type of
substance Sources Main hazards
Particles Environment, produced Affect subsequent lithography and dry etching
in other processes processes, cause device short-circuits
Natural oxide Environment Affect subsequent oxidation and deposition
layers processes, cause electrical failure of devices
Metal Environment, produced Affects the subsequent oxidation process, causes
contamination in other processes electrical failure of devices
Organic Dry etching by-product, Affects subsequent deposition process, causes
matter environment electrical failure of devices
Sacrificial Oxidation/Deposition Affect subsequent specific processes, cause
layers process electrical failure of devices
Polishing Grinding fluid Affect subsequent specific processes, cause
residues electrical failure of devices
69 Wet Cleaning Equipment 1497

on the substances’ physical and chemical characteristics. The types of chemical

solutions required for the removal of different substances are shown in Table 69.2.
In Table 69.2, SPM is a mixture of sulfuric acid, hydrogen peroxide, and
deionized water, mainly used for cleaning away organic matter. SC1 is a mixture
of ammonium hydroxide, H2O2, and deionized water, mainly used for cleaning away
particles. SC2 is a mixture of hydrochloric acid, H2O2, and deionized water, mainly
used for cleaning away metal contaminants. DHF is diluted hydrofluoric acid,
mainly used for etching silicon dioxide. BHF (NH4F þ HF) is a diluted hydrofluoric
acid buffer solution, mainly used for SiO2 etching of patterned wafers. DIO3 is
ozonated deionized water, mainly used for cleaning away organic matters. H3PO4 is
phosphoric acid, mainly used for etching silicon nitride. HF þ HNO3 is a mixture of
HF and nitric acid, mainly used for etching Si. TMAH is tetramethylammonium
hydroxide, mainly used for etching Si. Solvent cleaning solution is mainly used to
remove organic matters in contact with metals.
Depending on different requirements of cleaning processes, the physical assis-
tance methods that can be used together with these chemical solutions mainly
include the rapid liquid circulation, the megasonic wave driving, and the nitrogen
auxiliary spray cleaning.
Since the emergence of IC manufacturing technology, wafer cleaning and film
etching processes have been mainly performed by bench-type cleaners and etchers.
The basic procedure of the technology was developed in 1965 by W. Kern and later
called RCA Clean in 1970 [1]. It completes the wafer cleaning and etching processes
using a combination of multiple chemical tanks, deionized water tanks, and drying
tanks. This process has the advantages of a large process window, simple operation,
and large processing capacity, and has been used until now.
As the linewidth of integrated circuits continues to decrease, requirements such as
particle size and quantity, etch rate and uniformity, metal contamination control,
surface roughness, and wafer single-sided processes are becoming increasingly
strict. As a result, various types of cleaning equipment have been produced succes-
sively, including single-wafer cleaners, single-wafer scrubbers, single-wafer etchers,
single-bath wafer cleaners, and low-temperature supercritical fluid wafer cleaners.
Traditional CMP is the process for polishing the materials on the wafer surface, in
which the material to be polished chemically reacts with the slurry under the
grinding pressure to achieve the planarization of the wafer surface. The surface
materials of the wafer include polycrystalline silicon, silicon dioxide, tungsten, and
copper; each material corresponds to different types of polishing solution. Chemical-
mechanical polishing can polish the uneven surface morphology of the whole wafer
surface to a consistent thickness, which is a global planarization process.
Stress-free polishing (SFP) is the electrochemical polishing technology [2] used
to process the interconnected metal wires of chips in the IC manufacturing process.
This process does not produce mechanical stress on the metal wires. In particular, it
does not cause defects such as deformation or thin film falloff in metal
interconnected structures composed of low-k/ultra-low-k dielectric materials with
small linewidths and very weak mechanical strength. Thus, it will not cause these
interconnected structures to be open-circuited or short-circuited.
 1498

Table 69.2 Cleaning action of different chemical solutions

Chemical solution/Cleaning
action
Type of substances SPM SC1 SC2 DHF BHF DIO3 H3PO4 HF þ HNO3 TMAH Solvent
Particles Suitable Suitable – – – Suitable – – – –
Natural oxide layers – – – Suitable Suitable – – – – –
Metal contamination – – Suitable Suitable Suitable – – – – –
Organic matter Suitable Suitable – – – Suitable – – Suitable Suitable
Sacrificial layers – – – Suitable Suitable – Suitable Suitable Suitable –
Polishing residues Suitable Suitable – Suitable Suitable – – – – –
F. Chen et al.
69 Wet Cleaning Equipment 1499

Electroplating refers to the electrochemical metal deposition technology adopted

to process interconnected metal wires of chips in IC manufacturing. With the
continuous development of IC manufacturing processes, electroplating is no longer
limited to the deposition of copper wires, but also involves the deposition of tin,
tin-silver alloy, nickel, and other metals. However, copper electroplating continues to
be the most commonly used portion.
Wet process equipment is a multidisciplinary and high-tech product that encom-
passes numerous fields, including fluid mechanics, chemical engineering, materials
science, precision machining, electronic control, and computer software. It is the
main production equipment with the highest proportion used in the integrated circuit
manufacturing process.

Bench-Type Wet Cleaning System

A bench-type wet cleaner is mainly composed of an FOUP transfer module, a wafer

loading/unloading transfer module, an exhaust and gas inlet module, a chemical
liquid tank module, a deionized water tank module, a drying tank module, and a
control module. This equipment can clean multiple boxes of wafers at the same time
and is capable of the dry-in/dry-out wafer cleaning. Figure 69.1 shows the layout of
two typical bench-type wet cleaners. The choice of layout is determined by the
location of the equipment in the plant. Type I is generally selected for dry etching

Fig. 69.1 Schematics of two typical bench-type wet cleaners

1500 F. Chen et al.

areas, while type II is selected for diffusion deposition areas. The typical cleaning
process for the post-dry etching is as follows:

SPM ! HQDR1 ! DHF ! OF ! SC1 ! HQDR2 ! DRY

In this process, SPM is applied to remove the organic contaminants from the
wafer surface, hot quick dump rinse 1 (HQDR1) is applied to remove the residual
SPM from the wafer surface, DHF is applied to etch the native oxide film, OF
(overflow) is applied to remove the residual DHF from the wafer surface, SC1 is
applied to remove particles from the wafer surface, HQDR2 is applied to remove the
residual SC1 from the wafer surface, and DRY is applied for wafer drying.
The FOUP transfer module mainly transfers the FOUP to the location of the
FOUP storage area. It is very important to ensure that the wafers enter the same
FOUP before and after the wafer cleaning. The wafer loading and unloading module
moves the wafer from the FOUP and assembles the two boxes of wafer into a group
in a specified manner. There are two types of composition, namely the face-to-face
arrangement of wafers (for the good particle cleaning effect) and the face-to-back
arrangement of wafers (for the good etching control). At present application, wafers
are mainly grouped in a face-to-face arrangement. The wafer transfer module trans-
fers wafers between each process module. The precise control of horizontal position
and the vertical speed of entering the tank for wafers are key control parameters that
directly affect the cleaning effect. The chemical solution tank module is mainly used
for preparing chemical solutions. The tank module is composed of a main tank body,
megasonic generators, pumps, heat exchangers, filters, concentration meters, flow
meters, thermometers, and liquid level gauges; its primary function is to maintain the
precise control of the concentration, the temperature, and the circulation flow of the
chemical solutions, so as to achieve the cleaning process objectives. Specifically,
among these components, the main function of megasonic generator is to enhance
the cleaning effect for removing particles from the wafer surface. Figure 69.2 shows
a schematic of a typical chemical solution tank module.
After the completion of the chemical solution tank process, wafers need to be
cleaned in the deionized water tank in time to remove the residual chemical solution
on the wafer surface to avoid the occurrence of over-etching. There are two main
types of deionized water tanks. One is an overflow (OF) tank which is used for
cleaning after wet etching; the other is the hot quick dump rinse (HQDR) tank which
is mainly used for cleaning after degumming or particle cleaning, and generally is
equipped with a megasonic cleaning function. The drying tank is the key module of
the bench-type wafer cleaner. Its main function is to ensure that particles, water
marks, and pattern damage are not produced on the wafers after the drying step, and
to control the chemical oxide thickness.
The main function of the exhaust and gas inlet module is to control the cleanliness
of the gas entering the process module, while venting the generated chemical gas
mist through the factory emission control system. This can ensure the effect of the
cleaning process while maintaining the safety of personnel. The control module
69 Wet Cleaning Equipment 1501

Fig. 69.2 Schematic of a

typical chemical solution tank
module

mainly completes the wafer cleaning and etching processes according to the config-
ured technological process flow, and uploads the key parameters to the factory data
control system at the same time.
The wet process cleaning for 28 nm [3] and more advanced processes has
increasingly stringent requirements for the allowable number of small particles and
the etching uniformity on the wafer surface while ensuring that the drying process
must achieve nondestructive drying to the patterns. However, for the bench-type wet
cleaner, the difference in the chemical solutions inside the tank, the drying method,
and excessive contact points with wafers have made it impossible to meet these
process requirements. The bench-type wet cleaner has been gradually replaced by
the single-wafer cleaner which currently accounts for approximately 20% of the
steps in the entire cleaning process.
Bench-type wet cleaners are mainly supplied by SCREEN Semiconductor Solu-
tions, Tokyo Electron (TEL) and J.E.T. CO. of Japan, which together account for
more than 75% of total market share. The unit price for this type of equipment is
about USD 3.5 million. SEMES and KCTech of Republic of Korea can also provide
such equipment, mainly for the Korean market.

Bench-Type Wet Etcher

The bench-type wet etcher is mainly composed of a FOUP transfer module, a wafer
loading/unloading transfer module, an exhaust and gas inlet module, a chemical
solution tank module, a deionized water tank module, a drying tank module, and a
control module. This equipment can etch multiple boxes of wafers at the same time
and is capable of the dry-in/dry-out wafer etching.
The main advantage of this etcher is its high productivity. It is suitable for ultra-
high temperature chemical solutions (above 120  C) and can etch the frontside and
the back side of wafers at the same time. The main disadvantages are large
1502 F. Chen et al.

equipment footprint, small precision of film etching control, poor etching uniformity
between wafers, and can only be used for the entire wafer surface etching process.
Due to the increasing requirements for the amount of film etching and the uniformity
of etching, wafer etching requires the in-wafer uniformity of less than 2%, the bench-
type etching can no longer meet these requirements. Therefore, most of the current
thin film wet etching processes are performed by single-wafer etchers. Currently,
silicon nitride thin films are often selected as the sacrificial layers due to their
excellent material properties. After a specific process is completed, all of the silicon
nitride films on the front and the back sides of wafers need to be removed. The
bench-type wet etching using the high-temperature phosphoric acid (H3PO4) as
etchant is the most effective method to meet the requirement of silicon nitride thin
film removal. The process flow for the typical silicon nitride bench-type wet etching
is as follows:

DHF ! OF ! H3 PO4 ! HQDR1 ! SC1 ! HQDR2 ! DRY

In this process, DHF is applied to remove silicon oxide from the wafer surface,
OF is applied to remove residual DHF on the wafer surface, H3PO4 is applied to
etch silicon nitride film, HQDR1 is applied to rinse residual H3PO4 on the wafer
surface, SC1 is applied to remove particles from the wafer surface, HQDR2 is
applied to remove residual SC1 from the wafer surface, and DRY is applied for
wafer drying.
Figure 69.3 shows the schematic layout of a typical bench-type wet etcher. The
bench-type wet etcher and the bench-type wet cleaner use the same equipment
structure design. The biggest difference between these two structures is that the
parameters of the chemical tank of the etcher are more strictly controlled. They are
mainly controlled by the following two key components.

1. High-temperature pump: An appropriate chemical solution circulation flow rate

can ensure the uniformity of concentration and the temperature in the tank.
2. Heater: An efficient chemical solution heating device can ensure the stability of
high-temperature control.

Fig. 69.3 Schematic of a typical bench-type wet etcher

69 Wet Cleaning Equipment 1503

At the same time, specific functions are required for different thin films to be
etched. For instance, the wet etching for silicon nitride films requires the precise
control of the water content and the temperature in the phosphoric acid solution.
The requirements of 28 nm and more advanced processes for the removal of thin
films from wafers are increasingly higher. Not only the control targets of etching
amount and etching uniformity have been improved, but also the requirement for the
roughness of the wafer surface is more stringent. At the same time, some processes
require only the removal of the backside thin film of wafer, which has led to a
shrinking market for bench-type wet etchers (currently accounting for less than 2%
of the entire cleaning process). Currently, Japan’s Shibaura Electronic Corporation
has developed a silicon nitride single-wafer wet etcher to replace the bench-type
wafer etcher.
Bench-type wet etchers are mainly supplied by J.E.T. CO. of Japan, which has a
market share of more than 90%, and the unit price is about USD 3.5 million.
Republic of Korea’s SEMES can also provide such equipment, mainly for the
Korean market.

Single-Wafer Cleaning Equipment

Depending on different process objectives, the single-wafer cleaning equipment can

be divided into three categories. The first category is the single-wafer cleaning
system, for which the cleaning objectives include the removal of particles, organic
substances, natural oxide layers, and metal contamination. The second category is
the single-wafer scrubber, for which the main process is the removal of particles
from the wafer surface. The third category is the single-wafer wet etcher, which is
mainly used to remove thin films. Depending on different process applications,
single-wafer wet etchers can be divided into two types. The first type is mild etching
equipment, which is mainly applied to remove the surface damage layer of the thin
film generated by high-energy ion implantation. The second type is sacrificial layer
removal equipment, mainly used for the barrier layer removal after the wafer
thinning process or the chemical mechanical polishing (CMP).
In terms of overall equipment architecture, all kinds of single-wafer-type cleaning
equipment are similar, generally consisting of a main frame, a wafer transfer system,
a chamber module, a chemical solution supply and distribution module, a software
system, and an electronic control module, as shown in Fig. 69.4.

1. Main frame: This component mainly includes the configuration of the process
chamber and the layout of chambers. Currently, the most common number of
configured chambers is 8 or 12. In order to maximize production capacity,
equipment manufacturers have begun to produce 24-chamber machines. Different
manufacturers have their own solutions for the chamber placement, so as to make
sure that the clean room occupies the least footprint areas while ensuring a short
wafer transfer path and the convenience of the process.
1504 F. Chen et al.

Fig. 69.4 Basic structure of single-wafer wet cleaning equipment

2. Wafer transfer system: This component mainly consists of three parts, namely a
load port, an equipment front-end module (EFEM), and a wafer transfer robot
arm. The load port must meet the wafer transfer requirements. The front-end
module of the equipment is equipped with a high-efficiency particulate air
(HEPA) filter and meets the requirements of different technology nodes for the
particle size control. The wafer transfer manipulator arm is adopted to transfer the
wafers before and after cleaning. It must ensure that there are no particles added
during the transfer process and it must also avoid generating electrostatic charges.
3. Chamber module: The chamber module is the unit where the wafers are cleaned
and dried. The rotary spray method is the basis for the process of the single-wafer
cleaning equipment. In short, the rotary spray method is a process in which
mechanical methods such as motor driving are applied to rotate the wafers at a
relatively high speed. As the wafers rotate, a fluid medium such as a cleaning
solution or an etching solution is sprayed onto the wafer surface, and the
centrifugal action of high-speed rotation is applied to realize the uniform cover-
age and the detachment of the fluid medium over the entire wafer surface.
4. Chemical solution supply and distribution module: There are generally two
models for chemical solution supply systems, the chemical distribution system
(CDS), which is independent of the main unit, and the in-line mixing system,
which is integrated inside the main unit. Both solution supply systems can realize
the automatic mixing of different solutions in different proportions, and they are
69 Wet Cleaning Equipment 1505

mainly used for precise mixing of RCA solutions such as SPM, DHF, SC1,
and SC2.
5. Software system: This system’s main functions include providing a friendly user
interface, allowing the user to determine the process configuration, setting hard-
ware working parameters, providing real-time monitoring of key process param-
eters, and displaying the real-time status of the machine. It also controls the
mechanical and electronic control systems of the machine while providing alarm
functions. When the machine status is abnormal or the process configuration
setting is incorrect, the software will automatically trigger an alarm to ensure the
safety of the production process. This system includes a semiconductor equip-
ment communication standard/general equipment model (SECS/GEM) [4, 5]
factory automation control software system, which is a requirement for semicon-
ductor equipment to enter the 300 mm production line. The function of the SECS/
GEM system is to ensure that the semiconductor manufacturing equipment can
exchange information with the central control system of the production line to
achieve optimal production scheduling and to monitor the status of each wafer in
real time.
6. Electronic control system: The electronic control system is the control brain of the
equipment and guarantees its normal operation.

At present, the main manufacturers of single-wafer cleaning equipment are

SCREEN Semiconductor Solutions and Tokyo Electron in Japan, as well as Lam
Research in the USA. Single-wafer cleaning equipment produced by these three
equipment manufacturers currently accounts for more than 70% of total market
share. The space alternated the phase shift (SAPS) megasonic cleaning equipment
and the timely energized bubble oscillation (TEBO) megasonic cleaning equip-
ment independently developed by ACM Research (Shanghai), Inc. have been
adopted in IC mass production lines in Korea and China. Cleaners produced by
Sevenstar Electronics have entered SMIC’s production lines.
Figure 69.5 shows the single-wafer cleaning equipment developed by ACM.

Single-Wafer Cleaning System

The design of the single-wafer cleaning system is based on the traditional RCA
Clean method. Its purpose is to clean away the contamination such as particles,
organic matters, natural oxide layers, and metal contamination. In terms of process
applications, single-wafer cleaning system has been widely used in the front-end-of-
line (FEOL) and the back-end-of-line (BEOL) processes in integrated circuit
manufacturing, including pre-deposition clean, post-deposition clean, post-etch
clean, post-implant clean, post-chemically mechanical polishing (CMP) clean, and
post-metal deposition clean. The single-wafer cleaning system is basically compat-
ible with all cleaning processes except for high-temperature phosphoric acid
processes.
1506 F. Chen et al.

Fig. 69.5 Single-wafer

cleaning equipment
independently developed
by ACM

As the cleaning process requirements continue to increase, the simple rotary spray
method can no longer meet the needs of the process. In this situation, various
auxiliary cleaning methods have emerged, the most common of which include the
following two.

Nanospray Cleaning [6, 7]

In terms of its cleaning principle, the nanospray cleaning process separately intro-
duces a liquid medium and the high-purity nitrogen gas through each end of a dual-
fluid atomizing nozzle. The high-pressure gas is used as the driving force to assist in
the micro-atomization of liquids into extremely fine droplets, which are then sprayed
onto the wafer surface to achieve the removal of particles.
Japan’s DNS is the first equipment manufacturer to develop and use the
nanospray technology in IC cleaning processes. At present, the often-adopted
liquid media are SC1 and DIW. Figure 69.6 shows a schematic of nanospray
cleaning.
Important influencing factors in the nanospray cleaning technology are the
sprayed droplet size (i.e., the average diameter of the sprayed droplets), the number
of droplets ejected onto the wafer surface, the droplet ejection speed, the spraying
angle, and the ejection height.
69 Wet Cleaning Equipment 1507

Fig. 69.6 Schematic of

nanospray cleaning

The number of droplets and the sprayed droplet size determine the probability that
the sprayed droplets will contact the wafer and the dimension of the patterns that can
be washed. The droplet velocity determines the impact and the removal of contam-
inants on the wafer surface. The spraying angle (the spray is carried out at an angle
closest to both sides of the sprayed beam) and the spraying height (the distance from
the nozzle jet hole to the wafer) determine the spraying coverage area. Therefore,
in the nanospray cleaning process, the most important process parameters are
nitrogen flow and cleaning solution flow. Because this cleaning technology is
based primarily on the physical impact, early designs could not be applied to the
cleaning of patterned wafers. Since 2010, the updated Nanospray2 and Nanospray3
technologies created by DNS have reduced the device damage during the cleaning
step and expanded their range of applications.

Megasonic Cleaning

In 1979, RCA proposed the megasonic auxiliary wafer cleaning process. Megasonic
waves combined with DIW or SC1 are very effective in removing particles while
significantly reducing the amount of chemical solutions used. The effect is especially
obvious for the removal of small-sized particles. In order to obtain a good cleaning
effect and avoid damaging the wafers (especially patterned wafers), it is necessary to
select a specific megasonic oscillation frequency range. Commonly adopted mega-
sonic frequency ranges from 800 kHz to 3 MHz. The megasonic wave is generated
by a megasonic generator, transmitted to the cleaning solution, and then applied to
clean the wafer. A megasonic wave is a mechanical wave that produces periodic
compression or stretching in the liquid medium to which it is transferred. When the
intensity of the megasonic wave in the low-pressure phase exceeds the intrinsic
tensile strength of the liquid, the liquid will be pulled apart to form many cavities.
The dissolved gas in the liquid will diffuse into these cavities and the volume of these
cavities will be gradually enlarged in a cycle. This phenomenon is called the
1508 F. Chen et al.

cavitation effect which can produce significant cleaning effects. Since the boundary
layer thickness is very small in megasonic waves, the movement of these cavities can
generate local fluid flow near the wafer surface. This phenomenon is called micro-
streaming, and the shock wave generated by this micro-streaming and the fragmen-
tation of cavity can remove the particles from the wafer surface.
ACM Research (Shanghai), Inc. has developed the space alternated phase shift
(SAPS) megasonic technology for single-wafer cleaning. By controlling the distance
between the megasonic generator and the wafer, SAPS megasonic technology can
provide a uniform distribution of megasonic energy on the wafer surface to avoid the
megasonic wave induced damage on the surface patterns. Figure 69.7 shows the
schematic of SAPS megasonic technology. The SAPS megasonic technology mainly
uses a fan-shaped megasonic transducer (MegPie) to clean the wafer in which the
megasonic wave is transmitted into the thin solution layer to implement the clean
process on the low-speed rotating wafer surface. The rotational speed of the wafer,
the thickness of the liquid layer, and the position and energy of the MegPie are key
process parameters.
In addition to its good results in removing small particles, SAPS megasonic
technology also has advantages in cleaning wafers with high aspect ratio patterns.
When the pattern on the wafer surface has a high aspect ratio, especially in the
cleaning of TSV structures, the exchange of the chemical cleaning solutions inside
the trench is only determined by the diffusion mode. For high aspect ratio patterns,
the deeper the pattern depth, the longer the diffusion path, therefore the
lower the cleaning efficiency. In conventional cleaning processes, the boundary
layer of the cleaning solution on the wafer surface is relatively thick. Therefore,
based on the diffusion mode, the slow movement of the cleaning solution on the
wafer surface cannot affect the interior portion of patterns and the convection of fluid
cannot be formed. However, the action of megasonic waves can decrease the
thickness of the boundary layer on the wafer surface so that the cleaning solution

Fig. 69.7 The schematic of SAPS megasonic technology

69 Wet Cleaning Equipment 1509

can enter the interior portion of patterns by convection to create a stirring effect,
thereby accelerating the exchange of chemical cleaning solutions and improving the
cleaning efficiency.

Single-Wafer Scrubber

The main processing purpose of the single-wafer scrubber is to remove particles

from the wafer surface. Figure 69.8 shows the structure of a single-wafer scrubber.
In the single-wafer scrubber, there are four common cleaning methods:

1. Nanospray cleaning.
2. Megasonic cleaning. Recently, the megasonic hydrogen-functional water pro-
cessing is developed to remove ultra-tiny particles in the IC cleaning technology.
Functional water refers to a very dilute cleaning agent that infuses special gases
such as H2 and N2 into the deionized water. Due to the little environmental
pollution caused by this cleaning method, the less consumption in process
materials, and the excellent performance of megasonic waves in particle removal
(especially smaller particles), this newly developed megasonic cleaning pro-
cessing has attracted wide attention in the industry, in which hydrogen-functional
water (deionized water with hydrogen gas and a small amount of ammonium
hydroxide) performs particularly well.
Figure 69.9 shows the comparison of the particle removal rates between
ACM’s SAPS MegPie hydrogen-functional water process [8] and conventional
wet cleaning processes. As seen from the figure below, nanospray technology has
a very low removal rate for particles less than 50 nm and its removal rate for
particles of 65–80 nm is about 65%. The removal rate of the bench-type mega-
sonic SC1 process for particles smaller than 50 nm is about 46% and its removal
rate for particles of 65–80 nm is about 74%. The SAPS hydrogen-functional
water process demonstrates a removal rate of about 63% for particles smaller than

Fig. 69.8 Schematic of the structure of a single-wafer-type scrubber

1510 F. Chen et al.

Fig. 69.9 Comparison of particle removal rate of SAPS MegPie hydrogen-functional water
process and conventional wet cleaning process

50 nm and up to 91% for particles of 65–80 nm. Therefore, given the appropriate
megasonic energy and the gas content ratio, the particle removal effect of the
hydrogen-functional water process surpasses that of conventional cleaning
processes.
3. Brush scrubbing. Brush scrubbing is a mechanical cleaning method that removes
particles by means of the friction between the brush and the wafer surface. When
this process is applied to brush the wafer surface, the swing arm can be scanned
back and forth while the brush head is rotated by the motor. In general, the brush
does not directly touch the wafer surface. The most common materials currently
used for brushes include polyvinyl alcohol (PVA) and nylon. The limitations and
challenges of scrubbing technology are focused on two aspects. Firstly, the
cleaning solution must be compatible with the brush material. Secondly, when
the brush is used for cleaning, the downward pressure of the brush and the
rotational speed of the brush head must be precisely controlled to avoid causing
scratched damages to the wafer. Currently, brush scrubbing technology is gener-
ally used for the large particle removal after the mechanical wafer polishing as
well as the particle removal on the back side of wafers.
4. High-pressure fluid jet. High-pressure fluid jet cleaning requires the use of special
high-pressure pumps and high-pressure stainless steel pipelines. The high-
pressure nozzle jet hole are generally formed with a small-diameter flow-limiting
design. The angle of the nozzle can be adjusted according to the specific process
requirements. When a very high-speed water jet flows from the high-pressure
pump through the nozzle of the pipeline to the wafer surface, the effect of liquid
atomization can even be achieved. The shear stress between the high-speed
micro-flow and the wafer can remove particles from the wafer surface. The
cleaning effect of this high-pressure fluid jet method depends on the liquid
69 Wet Cleaning Equipment 1511

pressure and the jet speed. The relatively high liquid pressures currently used has
reached more than 2000 lbf/in.2, but such high pressure can cause damage to the
wafer surface, especially for patterned wafers. Since the high-pressure jet method
does not substantially reduce the fluid boundary layer on the wafer surface, its
removal effect is not ideal for small particles. At present, high-pressure fluid jet
cleaning is gradually withdrawing from the integrated circuit manufacturing
market but it is still widely adopted in processes such as solder cleaning and
high-pressure photoresist removal in the advanced packaging procedures.

Single-Wafer Wet Etcher

The purpose of process of the single-wafer-type wet etcher is mainly the thin film
etching. Depending on the processes in which it is used, it can be divided into two
types: (1) mild etching equipment (for removing the surface damage layer caused by
high-energy ion implantation) and (2) sacrificial layer removal equipment (for
barrier layer removal after wafer thinning or chemical mechanical polishing [CMP]).
The materials need to be removed in this process generally include silicon, silicon
oxide (SiO2), silicon nitride, and metal film layers.

1. Wet etching of silicon: This process includes wet etching of single crystal silicon
or polycrystalline silicon. There are generally two kinds of etching solutions. One
is an acidic etching solution based on a mixture of nitric acid and hydrofluoric
acid. The reaction mechanism of this solution begins with nitric acid oxidizing the
surface of silicon. The SiO2 formed by this reaction is dissolved by the
hydrofluoric acid to form a hexafluorosilicic acid complex. This etching solution
has an extremely high etch rate for silicon and is consistent for each silicon crystal
orientation, making it an isotropic wet etching method. During actual production,
to ensure both the cycle lifetime and etching stability of the solution, the etching
rate of silicon is often adjusted by adding other chemicals such as acetic acid,
sulfuric acid, and phosphoric acid. The second type of silicon etching solution is
an alkaline etching liquid based on potassium hydroxide (KOH) or tetra-
methylammonium hydroxide (TMAH). These solutions have different etching
rates for different silicon crystal orientations, so they are used in anisotropic wet
etching methods. Therefore, they are often used for the processing of special
microstructures in the fabrication of integrated circuits or MEMS.
2. Wet etching of SiO2: The most common SiO2 etching solution is hydrofluoric
acid etching solution. However, since the water in the hydrofluoric acid solution
is relatively volatile, the etching rate is not stable in processes that require long
durations. As such, a buffered oxide etchant (BOE) is introduced in some
processes that require precise control of the etching rate. The etching solution is
composed of hydrofluoric acid, ammonium fluoride (NH4F), and a surfactant.
Among these components, hydrofluoric acid is still the main etchant of SiO2,
while ammonium fluoride acts as a buffer agent to provide fluoride ions that are
continuously consumed during the reaction process, thereby maintaining the
1512 F. Chen et al.

stability of the etching rate. The role of the surfactant is to enhance the wetting of
the wafer surface and improve the etching effect by reducing the surface tension
of the etching solution.
3. Wet etching of silicon nitride: Suitable etching solution for silicon nitride is high-
temperature phosphoric acid (H3PO4; 85% phosphoric acid solution used with an
operating temperature higher than 170  C). Since phosphoric acid has a very low
etching rate for SiO2, it is often used as a film etchant for silicon nitride in
integrated circuit processes.
4. Wet etching of metal film layers: In integrated circuit processes, etching processes
involving metal film layers such as aluminum, copper, titanium, and tantalum are
often encountered. Aluminum wet etching solution is generally prepared by
mixing phosphoric acid, nitric acid, acetic acid, and DI water, and the process
temperature is generally 35–45  C. Copper wet etching solution is generally a
mixture of hydrofluoric acid and nitric acid. In recent years, with the rise of high-k
metal gate (HKMG) processes, SC1 has been used on an increasingly wide range
in the wet etching processes of metal gate materials due to its good etching
selectivity for silicon, SiO2, and hafnium-based HKMG thin films.

In the wet etching process and the hardware design, attentions should be paid to
the following.

1. The wet etching rate can be controlled by changing the concentration and
temperature of the solution. The variation in the temperature and the flow rate
of etching solution tend to cause fluctuations in its performance. The adoption of
a high-precision chemical solution mixing system and an insulation system can
assure the normal operation of the wet etching process.
2. Due to cost impact, the etching solution generally needs to be recycled. The
variation in concentration during the recycling will cause fluctuations in the
etching rate. Therefore, the service lifetime of the solution should be controlled
based on the quantity of wafers and the duration of time for which the solution is
used, and it should be replaced with fresh solution in time. At the same time, the
solution mixing systems are configured with an etching solution auto-dosing
function. When the number of wafers processed reaches a set amount, the
solution mixing system automatically refills the etching solution in the storage
tank and the refilled amount of solution can be set by the operator each time via
software settings. In some key steps of patterned film etching, the control
software automatically adjusts the operation time of each etching solution based
on the cumulative number of processed wafers, and the etching time can be set as
accurate as to 0.1 s.
3. Since the throw rate of the etching solution is not uniform across the wafer surface
and bubbles are often generated during the etching process, these bubbles adhered
to the wafer surface, thereby locally suppressing the etching process and causing
nonuniformity of etching. Therefore, this nozzle driven by a high-precision motor
can be designed to scan the wafer surface back and forth to solve this problem.
The scanning speed of the nozzle is automatically adjusted according to the
69 Wet Cleaning Equipment 1513

difference in etching rate on different areas of the wafer so as to compensate for

the centrifugal force induced nonuniformity in the etching process.
4. Generally, the etching solution is highly concentrated with a strong etching effect.
During the reaction process, chemical fog is easily generated in the reaction
chamber. In case it is not vented in time, the residual chemicals will damage
the wafer surface. Therefore, in the hardware design, it is necessary to consider
the balance between the air inlet and exhaust while enhancing the exhaust
function of the chamber.

Single-wafer wet etchers are further divided into two types: One performs the
wafer frontside etching and the other performs the wafer backside etching.
The overall hardware structure of the frontside etching equipment is the same as
that of a single-wafer cleaning system; the only difference is the chemical used. The
wafer backside etching equipment is generally used for the backside thin film
removal, polysilicon etching on the wafer back, wafer backside thinning, etc. The
biggest difference from the frontside etching equipment is the clamping method.
In the frontside etching equipment, the following two clamping methods are
generally used. Mechanical clamp: The wafer is fixed by a chuck pin driven by a
mechanical force such as an air cylinder, as well as electromagnetic or centrifugal
force. The clamp tightly holds about 1–2 mm width of the wafer outer edge. Vacuum
chuck: This device is operated by the principle of vacuum negative pressure
clamping. This clamping function requires a large contact area with the wafer back
surface, so it is no longer used in the high-end integrated circuit cleaning equipment.
As the die thickness is decreasing, so the backside thinning of wafer is increas-
ingly strict. Actually, as the wafer thickness is less than 300 μm, the conventional
mechanical clamping method is no longer suitable because it can easily cause the
wafer warpage or crack. In addition, some processes require the wafer surface to be
fully protected from solutions, vapors, and chemicals as well as the mechanical
scratch while performing the wafer backside process. Driven by this demand,
noncontact clamping mechanical tools have emerged. Currently, the most widely
used noncontact clamping mechanical tool in the industry is the Bernoulli gripper
which uses airflow to adhere to the wafer without physical contact. Such gripper
relies on the Bernoulli airflow principle. Figure 69.10 shows the structure of the
Bernoulli gripper [9, 10].
As shown in Fig. 69.10, after the manipulator arm loads the wafer into the
chamber, the wafer backside faces up and the frontside faces down. During the
process, the high-purity nitrogen gas with precise flow rate passes through a gas
pipeline under the chuck and a ring hole on the chuck surface, and then continuously
flows into the gap between the wafer and the chuck. According to Bernoulli’s
principle, the higher the gas flow speed in the gap, the lower its pressure inside the
gap, while the slower the gas flow speed, the higher its pressure inside the gap.
Therefore, when the gap between the chuck and the wafer is small, the gas flow
speed inside the gap is increased and the pressure applied to the wafer’s front surface
is increased; when the gap between the chuck and the wafer becomes large, the gas
flow speed inside the gap becomes slower and the pressure applied to the wafer’s
1514 F. Chen et al.

Fig. 69.10 Structural diagram of the Bernoulli gripper

front surface is decreased. During the process, the wafer can be maintained in an
equilibrium position by precisely maintaining the flow and pressure of the N2 gas
source. Although Bernoulli grippers perform obvious advantages, they consume too
much high-purity nitrogen, so this type of clamping is currently only used in the
wafer backside cleaning process.

Single-Bath Wafer Cleaner

The main differences between the single-bath wafer cleaner and the conventional
multi-bath cleaners are that the former has only one tank for the wet process (only
one cassette of wafers is placed in the cleaner at a time), various cleaning processes
are completed in the same tank, and the wafers are mechanically rotated at a high
speed in the rinsing tank. During the rotation process, a chemical solution or
deionized water is continuously sprayed on the wafers to clean the surface of wafers.
The equipment can simultaneously supply a variety of cleaning solutions, such as
SPM (a mixture of sulfuric acid and hydrogen peroxide), SC1 (a mixture of
ammonium hydroxide, hydrogen peroxide, and deionized water), DHF (diluted
hydrofluoric acid solution), SC2 (a mixture of hydrochloric acid, hydrogen peroxide,
and deionized water), and deionized water.
These cleaning solutions are applied to perform the wet cleaning process for
wafers according to certain processes, which can realize different process applica-
tions, such as photoresist removal; metal and dielectric layer stripping and removal,
cleaning away particles, organic residues, and metal contaminants before and after
diffusion; thin film deposition, oxidation, etching, and other processes; as well as
dielectric layer etching, cleaning away residues after chemical mechanical polishing
(CMP), wafer recycling, and other wet processes.
Taking the single-bath centrifugal spray wafer cleaner developed by FSI as an
example, the structure of this equipment is shown in Fig. 69.11.
The cleaning equipment places a plurality of cassettes on a controllable rotating
stage in the tank body. While the stage rotates at a high speed, the chemical solution,
69 Wet Cleaning Equipment 1515

Fig. 69.11 Structural diagram of a single-bath centrifugal spray wafer cleaner developed by FSI

deionized water, and N2 used for the cleaning process are pumped through the spray
column at the center of the top cover of the tank body to be sprayed onto the wafers.
The chemical solutions can also be sprayed out with a N2 pressurization to achieve
better cleaning results. The cleaning sequence in which each cleaning solution and
deionized water are sprayed on the wafers is controllable. After each chemical
cleaning process is completed, the chemical solution is immediately drained out
from the tank body, and the deionized water is introduced into the tank body to rinse
the spray column and the inside of the tank body. Then, the next chemical solution is
introduced. The drain out of different chemical solutions and deionized water is
controlled separately by a multi-way valve, and they are drained to different drainage
pipes or to the recycling container for recycling. After the cleaning is completed, hot
nitrogen gas is introduced to blow-dry the wafers, which combines with the centrif-
ugal force generated by the high-speed rotating stage to achieve a good drying effect.
The mixing and dilution of the chemical solutions is completed online in a
multidirectional combined mixing unit that can mix a variety of chemical solutions,
as well as the mixing ratio and flow rate can be precisely controlled. The chemical
solutions are thoroughly mixed to form a cleaning solution before reaching the spray
column, thereby ensuring the freshness of the cleaning solution when it reaches the
surface of wafers.
The temperature control of the chemical solutions is mainly performed by an
online heater. After they are heated, the chemical solutions are introduced into the
tank body for the process. For the SPM cleaning process, the chemical solutions are
required to be at a very high temperature, generally 120–150  C or even greater than
200  C, when they reach their operation temperatures on the wafer surface. How-
ever, for such high temperature requirements, it is difficult for a single-bath cleaning
system to directly heat the solutions in the tank or by means of a heater, and it is also
difficult to maintain the solutions’ freshness and the effectiveness of their
1516 F. Chen et al.

compositions. Therefore, the single-bath cleaning system uses a heater to preheat the
sulfuric acid to a certain temperature (for example, above 80  C). It then mixes
hydrogen peroxide online and heats the solutions again using the chemical self-
heating effect generated by the mixing of the two chemical solutions. The mixing
ratio, the solution flow rate, the mixing time, and other parameters are controlled so
that they can reach the desired operation temperatures when the solutions flow to the
surface of wafers.
Compared with conventional multi-bath cleaning systems, single-bath cleaning
systems can effectively reduce the consumption of chemical solutions, ensure the
freshness of the chemical solutions when they reach the surface of wafers, and
reduce the cross-contamination between chemical solutions. In addition, compared
with conventional multi-bath cleaning equipment, single-bath cleaning systems
greatly reduce the footprint area of the equipment. At the same time, a variety of
cleaning procedures can be flexibly arranged and also be switched quickly. The
disadvantage is that, because different chemical solutions share the same spray
pipeline and different chemical solutions in the same process tank cannot be
completely cleaned up as they can in the single-wafer cleaning equipment, thus
these systems cannot completely avoid the cross-contamination between chemical
solutions.

Cryogenic-Aerosol Wafer Cleaner [11, 12]

As semiconductor technology node is constantly advancing, feature size is becoming

increasingly smaller. When feature size reaches the nanometer level, it is very
difficult to use conventional DI water or chemical solutions to clean nano-scaled
structures due to the increase in surface tension and the capillary force, and the use of
chemical solutions inevitably causes material loss in nano-scaled patterned struc-
tures. Moreover, wet process cleaning faces many challenges because of the adhe-
sion and other problems caused by the drying process, which are more severe for
nano-scaled patterned structures after the wet cleaning process. Supercritical fluid
technology is an emerging technology developed based on the characteristics of
supercritical fluids. Cleaning processes using supercritical fluids as media provide a
good solution to overcome the above problems caused by wet process cleaning.
Supercritical fluids are fluids in a state above critical temperature and critical
pressure, and they possess properties of both liquids and gases. They are in a dense
gaseous state that is different from typical gases, and their physical properties are
intermediate between those of the gaseous state and the liquid state. Table 69.3
compares the properties of gases, supercritical fluids, and liquids. Supercritical fluids
combine the advantages of liquids and gases: low viscosity, large diffusion coeffi-
cient, low surface tension, and good mass transfer characteristics. They can be used
for cleaning nano-scaled patterned structures; their high density, which is close to
that of liquids, gives them good solubility characteristics that make them suitable
substitutes for liquid cleaning agents. Furthermore, they are very sensitive to the
temperature and pressure near the critical point, so their solubility can be maximized
69 Wet Cleaning Equipment 1517

Table 69.3 Comparison of properties of gases, supercritical fluids, and liquids used in wafer
cleaning
Type Density/(g/cm3) Viscosity/(Pas) Diffusion coefficient/(cm2/s)
Gas (0.6–2)  103 (1–4)  105 0.1–0.4
Supercritical fluid 0.2–0.9 (1–9)  105 (0.2–0.7)  103
Liquid 0.6–1.6 (0.2–3)  103 (0.2–2)  105

Table 69.4 Supercritical properties of commonly used substances

Molecule Critical temperature/oC Critical pressure/atm Critical density/(g/cm3)
H2 239.9 12.8 0.032
N2 147 33.5 0.314
Xe 16.6 57.7 1.11
CO2 31.26 72.9 0.468
C2H6 32.3 48.2 0.203
CF3H 25.9 47.8 0.526
CF3Cl 28.8 38.7 0.579
NH3 132.3 111.3 0.235
CH3OH 240 78.5 0.272
CH3CN 274.7 47.7 0.237
H2O 374.2 218.3 0.135

Fig. 69.12 Phase diagram of

the supercritical CO2 cleaning
technology

by increasing the temperature and the pressure during the cleaning process, and
the solute can be separated and precipitated by lowering the temperature and the
pressure after cleaning.
Table 69.4 lists the supercritical properties of commonly used substances. Among
them, CO2 is a good supercritical fluid with a lower critical temperature and critical
pressure (Tc ¼ 31.2  C, Pc ¼ 7.38 MPa), which makes it easier to achieve automatic
control. Figure 69.12 shows a phase diagram of the supercritical CO2 cleaning
technology. Supercritical CO2 is a physically stable substance that is nonflammable,
1518 F. Chen et al.

Fig. 69.13 The functional blocks of the supercritical CO2 cleaning system

safe, nonetching, low cost, and environmentally friendly. Supercritical CO2 gener-
ally dissolves nonpolar or weak polar substances. Its polarity can be changed by
adding a polar solvent to make it have different solubility properties for different
solutes.
Figure 69.13 shows the functional blocks of the supercritical CO2 cleaning
system. Its operating principle can be summarized as follows: (1) The CO2 tempo-
rarily stored in the container being pressurized by the pump above its critical
pressure (7.38 MPa) while a small amount of co-solvent and cleaning agent are
added. (2) The temperature is then raised to the critical temperature of CO2
(31.2  C), making the CO2 achieve supercritical rotation and increasing the kinetic
energy of the supercritical CO2 fluid so that it is evenly distributed on the wafer
surface. (3) After the cleaning process is completed, supercritical CO2 continues to
flow in so that the CO2 along with the dissolved contaminants enters the separator.
At the same time, the process chamber is depressurized, causing the clean CO2 in the
chamber to be vaporized and discharged. (4) Finally, the CO2 in the separator is
depressurized to achieve the separation and the precipitation of contaminants.

Chemical Mechanical Polisher (CMP)

The chemical mechanical polishing (CMP) process was introduced in the integrated
circuit manufacturing industry by IBM in 1984. It was first adopted for inter-metal
dielectric (IMD) planarization in the back-end-of-line (BEOL) processes, followed
by tungsten planarization through the improvement of the equipment and process,
and then to shallow trench isolation (STI) and the copper (Cu) planarization.
The principle of planarization in the CMP process is to apply the mechanical
force on the wafer surface, while the chemicals in the abrasive liquid (slurry) react
with the wafer surface to increase the removal rate, as shown in Fig. 69.14.
The two most important components of the CMP process are the abrasive liquid
(slurry) and the polishing pad. In the CMP process, the pores of the polishing pad are
69 Wet Cleaning Equipment 1519

Fig. 69.14 Principle of planarization in the CMP process

filled with the abrasive liquid (slurry) at first. Driven by the head, the wafer is rotated
at a high speed and reacts with the slurry and the polishing pad; meanwhile, other
parameters such as the pressure under the head need to be controlled.
Applications of CMP processes in wafer fabrication include STI CMP, poly-
silicon planarization, interlayer dielectric (ILD) CMP, IMD CMP, and copper
CMP.
A CMP system is mainly divided into two units, the polishing unit and the
cleaning unit, as shown in Fig. 69.15. The polishing unit consists of four parts,
namely three polishing platens and one wafer loading and unloading module. The
cleaning unit is applied to clean and dry the wafers, and realize the “dry-in/dry-out”
feature for wafers.
The main process parameters for CMP include removal rate, polishing unifor-
mity, and defect density. The removal rate refers to the total amount of materials that
are polished on the wafer surface per unit time (second or minute). The uniformity is
further divided into within-wafer nonuniformity (WIW NU) and wafer-to-wafer
nonuniformity (WTW NU). WIW NU refers to the ratio of the standard deviation
of a wafer’s removal rate to the average removal rate, while WTW NU indicates the
uniformity of the removal rate for different wafers under the same conditions. For
CMP, the main defects include surface particles, surface scratches, and slurry
residues, all of which will directly affect the yield of the products.
CMP equipment integrates the most advanced technologies in many fields such as
mechanics, fluid mechanics, material chemistry, precision machining, and control
software. It is one of the more complicated equipment adopted in integrated circuit
production and its development is very difficult compared to other equipment. As the
diameter of wafers grows and process complexity continues to increase, the price of
CMP equipment is also gradually rising. In general, a CMP equipment for 200 mm
wafer size costs about USD 3 million, and for 300 mm wafer size costs about USD
4 million. The main CMP equipment vendors are Applied Materials in the USA and
Ebara in Japan, the former accounts for about 60% of the CMP equipment market
and the latter accounts for about 20%. CMP equipment by Hwatsing of China has
been used in SMIC’s production line.
1520 F. Chen et al.

Fig. 69.15 Units of a CMP system

Stress-Free Polish Equipment

The stress-free polish (SFP) process is based on the principle of electrochemical

polishing [2]. The polishing solution is in contact with the copper surface of the
wafer directly. Under the electrochemical reaction, the elementary copper molecules
are replaced by hydrogen ions. These are then electrolyzed in the polishing solution
to form a compound containing copper ions, thereby effectively removing the excess
copper layer on the wafer surface. The chemical reaction formula is:

Cu þ 2Hþ ! Cu2þ þ H2

SFP can adequately solve the scratch damages caused by the mechanical stress
during the planarization of copper interconnect structures composed of low-k and
ultra-low-k dielectric materials. Figure 69.16 shows a comparison between cop-
per/ultra-low-k dielectric (k ¼ 2.2) interconnect structures after polishing in the
CMP process and the SFP process.
A structural diagram of a typical SFP process chamber is shown in Fig. 69.17. In
the process chamber, the wafer faces down and is fixed on the wafer holder. The
holder can move the wafer vertically and horizontally, and also can rotate the wafer.
The wafer is connected to the positive electrode of the polishing power source
69 Wet Cleaning Equipment 1521

Fig. 69.16 Comparison of copper/ultra-low-k dielectric (k ¼ 2.2) interconnect structures after

polishing by the CMP process and the SFP process

Fig. 69.17 Structural

diagram of a typical SFP
process chamber

through a liquid electrode, which serves as an anode, while the polishing nozzle is
connected to the negative electrode of the polishing power source, which serves as a
cathode. By controlling the current or voltage of the polishing power supply, the flow
rate of the polishing solution, as well as process parameters such as wafer leveling
and rotation, it is possible to control the removal rate and the profile of the copper
layer on the wafer surface. In order to control the overall film thickness and the
dishing of patterns on the wafer, the SFP process uses a smart polishing control
system to measure the thickness of the copper layer on the wafer surface and can
automatically adjust the process parameters according to the measured values,
thereby enabling the precise control over the thickness and removal rate.
Features of the SFP smart polishing system include the mechanical movement
control of the wafer, the current/voltage output control of the smart polishing power
source, and the delivery flow control of the polishing solution. After a certain period
of operation, the copper ion concentration of the electrolyte solution increases, then
the copper ions in the polishing solution can be precipitated by the electroplating in a
chemical liquid recovery unit and the precipitated solid copper can be recovered to
1522 F. Chen et al.

Table 69.5 Main technical parameters of the SFP process

Main technical parameters Description
Removal rate Directly affects the productivity
Within-wafer nonuniformity Affects factors such as the surface profile of wafer after the
(WIW NU) process
Roughness Roughness of the copper surface after the process
Dishing Height difference between the copper metal wire and the
dielectric layer outside the pattern
Erosion Height difference between the copper metal wire and the
dielectric layer outside the pattern
Particles Number of particles on the wafer surface after the process

ensure the circulation of electrolyte solution. The main technical parameters of the
SFP process are shown in Table 69.5.
Compared to conventional CMP and ECMP processes, the SFP process is based
on the principle of electrochemical polish, with the only difference being that the
polishing solution is in contact with the wafer surface directly, and there is no erosion
or deformation to the dielectric layer or the barrier layer. Intel’s simulation results
show that when the copper/ultra-low-k dielectric CMP process progresses to the
barrier layer, the polishing pad and polishing abrasives will damage the ultra-low-k
dielectric materials like a wedge does. Regardless of how low the pressure between
the polishing pad and the wafer may be, it will cause scratch damages to ultra-low-k
dielectric materials. The SFP process has been proven not to cause any mechanical
stress during the polishing process, so no matter how big the difference of elastic
modulus may be between the copper conductor and the low-k/ultra-low-k dielectric
material, it will not cause any scratch damage to either of them. The SFP system has
no polishing pad or abrasives, and the polishing solution can be recycled, which not
only lowers the cost, but also reduces the environmental pollution. The advantages
and disadvantages of the SFP process are shown in Table 69.6.

Copper Electrochemical Plating (Cu-ECP) Equipment [13]

The copper electroplating process utilizes the electrochemical principle. The surface
of the wafer, on which a seed layer has been deposited, is used as a cathode and the
entire wafer is immersed in the electroplating solution. The electroplating solution is
an electrolyte mixture containing a high concentration of cupric sulfate, sulfuric acid,
and corresponding additives. The copper ion concentration, the acidity, and the
chloride ion concentration of the electroplating solution determine the quality of
the copper layer on the surface after copper plating. When the copper ion concen-
tration is too high, the roughness of the copper layer will increase; when the ion
concentration is too low, the current density will decrease and eventually result in a
lower deposition rate.
Therefore, in the copper plating process, the above three major components of the
copper plating solution need to be periodically analyzed and monitored. The copper
69 Wet Cleaning Equipment 1523

Table 69.6 Advantages and disadvantages of SFP compared to CMP

Advantages and disadvantages
Compatible with conventional
CMP
No stress
Erosion free
Delamination free
Scratch free
Particle free
Uniform dishing control
Technical scalability
Low cost
Environmental protection
Poor planarization effect
Poor surface roughness
Description
Able to integrate with CMP P1 step and process
(1) No mechanical force
(2) Only the ECMP solution is in contact with the wafer
(3) No reaction with dielectric materials
Features the dishing auto-stop function
(1) Compatible with new barrier layer materials such as
Ru/Co
(2) Suitable for air gap integration processes
(1) No consumables such as polishing solutions or polishing
pads
(2) Electrolyte solution can be recycled
Isotropic process and poor planarization effect
Average: Ra >2 nm (CMP: Ra <1 nm)

ion concentration of the copper plating solution is adjusted by adding deionized

water and chloride ions. In addition, during the semiconductor copper interconnec-
tion process, small amounts of additives are needed to improve the surface mor-
phology of the plating layer and the copper plating effect on patterned wafers.
Additives mainly include accelerators, inhibitors, and surface leveling agents. The
main purposes of mixing these three additives in the copper plating solution are to
reduce the roughness of the copper layer, increase the copper deposition rate in the
vertical direction of the bottom in the trench structure, reduce the copper deposition
rate in the horizontal direction for vertical sidewalls in trench structures to avoid
cavity failure caused by sealing of trench structures, and adjust the copper plating
rate in different pattern density areas to improve the plating uniformity on the whole
wafer. The concentration of the additives also needs to be analyzed and monitored
periodically. Based on test results, accelerators, inhibitors, and surface leveling
agents are added as needed and the temperature of the copper plating solution is
controlled to avoid the accelerated decomposition of additives due to high
temperatures.
At present, most electroplating equipment use a single wafer structure, and the ion
membrane separation technology is also used inside the electroplating chamber to
separate the cathode electroplating solution from the anode electroplating solution,
ensuring that they are cycled independently of each other. Under the action of the
electric field, copper ions can pass through the ion membrane, enabling the copper
ions consumed in the cathode electroplating solution to be replenished in time while
preventing additives and anions from passing through the ion membrane. Fig-
ure 69.18 shows the structure of a horizontal electroplating chamber.
In the process chamber, the wafer is faced down and fixed on a wafer holder. This
wafer holder can move vertically, tilt, and rotate while carrying the wafer. The holder
1524 F. Chen et al.

Fig. 69.18 Schematic diagram of a horizontal electroplating chamber

not only ensures good conductive properties of the seed layer on the wafer surface,
but also prevents the electroplating solution from entering the contact points of the
holder. The contact points of the wafer holder are connected to the negative electrode
of the power supply as a cathode, and the soluble copper block and the anode plate
are connected to the positive electrode of the power supply as an anode. By
controlling the current or voltage of the power source, the flow rate of the electro-
plating solution, the wafer leveling and rotation, and process parameters, it is able to
control the plating rate and the profile of the copper layer on wafer.
The electroplating system is one of the important equipment for IC fabrication; its
performance indicators are as follows: first, the equipment must meet the require-
ments to achieve better electrical performance and higher yield. Second, the equip-
ment must achieve the maximum output at the lowest cost. Table 69.7 lists the main
parameters for electroplating equipment.
The electroplating process is also widely used in advanced packaging, micro-
electromechanical systems (MEMS), and other fields. With the development of
advanced wafer-level packaging technology, the application of electroplating
equipment is gradually increasing. At present, the market share of electroplating
equipment required for advanced packaging field has exceeded that for the front-
end-of-line (FEOL) processes in IC fabrication.
The electroplating equipment used in copper technological processes is a
high-tech product integrating electrochemistry, fluid mechanics, chemical additives,
precision machining, control software, and other technologies. Copper plating
equipment is also one of the more complicated and difficult-to-operate equipment
for IC fabrication. The main equipment vendors are Lam Research in the USA and
Tokyo Electron in Japan. Currently, Lam Research accounts for 90% of the market
share in embedded technology related copper electroplating equipment. The unit
price of this equipment is about USD five million. In the advanced packaging field,
Tokyo Electron has a higher output-to-price ratio and holds about 50% of the market
69 Wet Cleaning Equipment 1525

Table 69.7 Main performance parameters for electroplating equipment

Main parameters Description
Copper plating rate The maximum electroplating rate can directly affect the
productivity
Within-wafer nonuniformity The thickness distribution of copper film across the whole wafer
(WIW NU) has a significant influence on subsequent processes
Roughness Copper surface roughness after the electroplating process
Electroplating chamber Some key components of the copper plating chamber (such as the
maintenance cycle wafer holder, ion membranes, and contact points) require regular
cleaning, maintenance, and replacement. These components are
delicate and expensive, directly affecting the production cost
Reflectivity Surface reflectivity after the process shows the copper surface
quality
Particles Number of particles or defects on the wafer surface after the
process

share due to its vertical electroplating chamber design. ACM Research (Shanghai),
Inc. has mastered and patented core electroplating equipment technology, including
multi-ring anode technology and megasonic auxiliary electroplating technology, and
also has independently developed the Ultra ECP series electroplating equipment.

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Technological University, Singapore, 2011
Metrology and Inspection Equipment
70
Feng Yang

Contents
Metrology and Inspection Equipment: Roles and Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
Overlay Metrology Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530
Critical Dimension Scanning Electron Microscope (CD-SEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
Operation Principle of CD-SEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
Application of CD-SEM in IC Manufacture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
New Challenges for CD-SEM by the Development of Semiconductor Manufacture
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
Optical Thin Film Metrology Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
Optical Critical Dimension (OCD) Measurement Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538
Defect Inspection Equipment of Bright Field Optical Microscope for Patterned Wafer . . . . . . 1542
Defect Inspection Equipment of Dark Field Optical Microscope for Patterned Wafer . . . . . . . 1544
Unpatterned Wafer Surface Inspection Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546
Macrodefect Inspection Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
Electron Beam Wafer Defect Inspection Equipment (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
Defect-Review Scanning Electron Microscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
X-Ray Metrology Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
X-Ray Fluorescence Spectroscopy (XRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
X-Ray Diffraction and Reflectometry (XRD/XRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556
Atomic Force Microscope (AFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
Contact Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
Noncontact Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
Tapping Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
Focused Ion Beam (FIB) Microscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
Fourier Transform Infrared (FTIR) Spectrometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
Film Stress Measurement Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
Curvature Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
X-Ray Diffraction Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
Four-Point Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564

F. Yang (*)
Raintree Scientific Instrument (Shanghai) Corporation (RSIC), Shanghai, China
e-mail: yangfeng@rsicsh.com

© Publishing House of Electronics Industry 2024 1527

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_70
1528 F. Yang

Surface Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568

Abstract
This chapter covers a key part of modern semiconductor chip manufacturing
equipment, metrology, and inspection. It is divided into several sections, each
addressing one specific type of equipment. Each type is presented in terms of the
technology background, working principle and flow, and its application in chip
manufacturing processes. In some sections, typical equipment specifications and
major equipment models and makers are presented. Metrology and inspection
field comprises a large number of equipment types which employ a wide range of
different technologies. Due to limited space, only major and widely used equip-
ment types are covered. To better serve general readers with diverse backgrounds
and disciplines, the authors intentionally limited the use of technical terminology
to suit readers with less technical backgrounds.

Keywords
Process control · Thin film · CD · Yield · Reliability · Defect detection ·
Linewidth

Metrology and Inspection Equipment: Roles and Categories

The metrology and inspection equipment is a general term for assorted measuring
tools and defect inspection tools used in individual steps of integrated circuit
(IC) manufacturing processes. In the chip production line, online metrology and
inspection equipment performs the nondestructive quantitative measurement and the
inspection of silicon wafers under each process step (or after several successive
process steps) to ensure that key physical parameters of the process (such as film
thickness, linewidth, trench/hole depth, and sidewall angle) meet the required
specification, also identify and classify the “killer” defects that may occur, as well
as eliminate unqualified wafers to avoid the work being wasted in subsequent
processes. At the same time, the metrology and inspection equipment can help
engineers find out the deviations or problems of the process equipment in time and
solve these problems in time to ensure the yield and the stable output of the
production line. Another important role of the metrology and inspection equipment
is to help engineers optimize the operating parameters of process equipment (such as
lithography, thin film, etching, and CMP equipment) during the process develop-
ment and trial production stage, and identify defects that affect the chip process
quality, so as to establish the workable process flows with the good production yield.
Therefore, the metrology and inspection equipment play key roles for the IC
production line to enter the mass production stage quickly and to achieve stable
high yield and high economic efficiency.
70 Metrology and Inspection Equipment 1529

There are many types of metrology and inspection equipment used in the process
of manufacturing IC chips. Those equipment most commonly applied in the
front-end chip manufacturing processes can generally be classified into the following
four categories:

1. Detection of particles, residual foreign materials, and other irregularities on the

surface of blank wafers, as well as inspection and classification of defects and
irregularities in device patterns on the device wafers during the processes
2. Measurement of the thickness and physical constants (such as refractive index,
extinction coefficient, composition, stress, etc.) of the thin film materials on
wafers
3. Measurement of critical dimensions (CD) and other structural parameters of
device structures after the exposure and development of photoresist, the etching,
the CMP process, etc.
4. Measurement of lithography overlay errors

In the back-end packaging processes, advanced processes such as flip-chip,

wafer-level package, and through-silicon via (TSV) require the contactless quanti-
tative inspection and measurement for defects/foreign material residues and dimen-
sional parameters of bumps, copper pillars, TSVs, as well as redistribution layers
(RDL), etc.
In the early days of the integrated circuit manufacturing technology, inspections
and measurements were typically performed on pattern-free monitoring wafers. As
the manufacturing processes progress, the value of a single die is getting higher and
higher. In order to obtain the highest possible yield, it is necessary to strictly control
the process consistency between the wafers and between the dies on the same wafer.
Therefore, it becomes necessity to perform the online inspection and measurement of
the devices on wafers during processes, which requires the inspection and metrology
equipment to have intelligent and reliable pattern recognition function such that
areas of interest can be quickly located and inspections or measurements can be
conducted. Subsequently, real-time measurement data are uploaded to central
manufacturing control systems to monitor the quality of process steps and ensure
smooth operation of production lines. For a modern mass production line with 24 h
uninterrupted operation, the total number of inspection and metrology steps is very
large, and the throughput of the metrology and inspection equipment is another key
performance indicator, in addition to sensitivity, precision, and stability.
To cope with different materials and structures used in the manufacturing process
of integrated circuit chips, various technologies are adopted in different metrology
and inspection tools, including broadband (ultraviolet to infrared) optical technol-
ogy, electron beam, laser and X-ray, etc. As the Moore’s law continues to advance,
the physical dimensions of advanced devices are getting smaller and smaller, and the
structures are becoming ever so complex and moving from traditional planar archi-
tectures to 3D architectures (FinFET, 3D NAND, and TSV). Such device technology
evolution constantly poses new challenges to the sensitivity, precision, applicability,
1530 F. Yang

and stability of the metrology and inspection equipment, and provides the impetus
for its own technological development and progress.
In addition to ensuring quick ramp and high yield of chip production, metrology
and inspection equipment is usually adopted to qualify newly installed process tools,
perform regular monitoring tasks on them, and help tool troubleshoot problems as
well as maintain consistency after tool maintenance and repair.
With the device structure shrinking and the increasing complexity of the process,
the metrology and inspection equipment plays an increasingly important role in the
advanced front-end chip production lines. According to the statistics by various
market research firms and the semiconductor industry consortium, the investment in
the metrology and inspection equipment accounts for 10–15% of the total invest-
ment in the entire front-end process equipment. Like all other front-end chip
manufacturing equipment, the suppliers of the metrology and inspection equipment
are mainly concentrated in countries such as the USA, Japan, and Israel. For past
decade or so, a number of Chinese equipment companies that serve advanced
integrated circuit production lines have emerged, including Raintree Scientific
Instruments (Shanghai) Co., Ltd. and Skyverse Limited which specialize in devel-
oping and manufacturing the metrology and inspection equipment.

Overlay Metrology Equipment

In the advanced IC manufacturing process, the optical alignment of the key layers
directly affects the performance, yield, and reliability of the device, so the overlay
(OL) error is one of the most important specifications in the manufacturing process.
As the chip integration continues to increase, the critical dimensions (CD) of devices
become smaller and smaller, the wafer size increases, and the application of double
or multiple patterning lithography of the manufacturing process requires tighter
control of the overlay (OL) error between layers. Therefore, the OL error measure-
ment is a key step in the advanced process control. The OL error is defined as the
plane distance between the center of the nth layer pattern structure and the center of
the n þ 1th layer pattern structure. The measurement of the OL typically involves
determining the center line (CL) of each structure along the x-axis and along the
y-axis. Figure 70.1 shows an example of determining the center line along x-axis [1]:

1
CL ¼ ðx2  x1 Þ
2

Fig. 70.1 Example of

determining the center line
along x-axis
70 Metrology and Inspection Equipment 1531

where x1 and x2 are edges positions defined by the measurement.

At present, there are three common types of OL error measurement systems,
namely optical image–based overlay (IBO) system, optical diffraction–based over-
lay (DBO) system, and scanning electron microscope (SEM)-OL system.

1. Optical IBO system: This is the most commonly applied OL error measurement
system. It obtains a digitized image including two layers of target patterns
through an optical IBO system, and then extracts the edge positions of the target
patterns of each layer based on the digital image processing algorithms, and
further calculates the center position of the pattern of each layer, thereby
obtaining the OL.
2. Optical DBO system: This is a nonimaging overlay OL measurement system. It
uses a specially designed grating target pattern and a light intensity sensor. The
system illuminates a beam of monochromatic parallel light onto the target
gratings on two different layers, uses a pair of light intensity sensors to measure
the intensity of the first-order diffracted beams reflected by the gratings to
different space directions, and then determines the OL by measuring the asym-
metry of the intensities of the two first-order diffracted beams. The advantages of
this system are that it uses fewer optical components, is less sensitive to aberra-
tions, has better repeatability than imaging systems, and is often used in advanced
photolithographic process control.
3. SEM-OL system: It is mainly used for the final OL measurement after etching.
The corresponding target pattern size is smaller, and it is usually designed inside
the device area of chips, not in the scribe-line area. The disadvantage of this
system is that the measurement speed is low.

The most commonly used optical overlay equipment in advanced process control
is the Archer 500 series from KLA-Tencor and the YieldStar S-250 series from
ASML. The Archer 500 series can measure many target patterns with IBO technol-
ogy and DBO technology. The YieldStar S-250 series utilizes DBO measurement
technology. The target patterns can be either 10 μm  10 μm patterns in the device or
30 μm  60 μm patterns in the scribe-line area. The total measurement uncertainty
(TMU) is 0.35 nm. In addition, Hitachi’s CD-SEM CV5000 series utilizes a 30 kV
high-voltage accelerated electron beam to measure micro/nanoscale target patterns in
the device area. All of the equipment meet the overlay measurement requirements of
10 nm process nodes.
The overlay measurement requires optimized design of specific overlay target
patterns, which are typically fabricated in the scribe-line area. As the chip
manufacturing process continues to progress, the size of the target pattern is grad-
ually reduced while the number of edges is also continuously increased to improve
the precision of the overlay measurement. The target patterns used in the imaging
based overlay measurement system mainly include box-in-box patterns, bar-in-bar
patterns, and aims grating patterns; Fig. 70.2a–d shows an example of the section of
the bar-in-bar patterns.
1532 F. Yang

Fig. 70.2 Commonly used overlay measurement target patterns

For the grating pattern of the DBO measurement system, it is assumed that
illuminating Iill is the incident light beam intensity, and I+1 and I1 are the positive
and negative first-order diffracted light beam intensities formed by the grating
reflection, respectively. Figure 70.2e shows the case without OL error (OV ¼ 0,
I+1 ¼ I1), and Fig. 70.2f shows the case with OL (OV 6¼ 0, I+1 6¼ I1). The overlay
target patterns used for the SEM system overlay measurement are shown in
Fig. 70.2g, h. These patterns are small in size and can be fabricated in the same
area as the actual device.
Overlay measurement errors mainly come from the measurement system, the
photolithographic process, and target patterns on the wafers to be tested. The errors
used by the industry for evaluation include tool-induced shift (TIS), wafer-induced
shift (WIS), and TMU [2].

1. TIS: It is the error caused by the asymmetry of the optical overlay measurement
system, mainly including the central tilting of the illuminating system and the
imaging system or lens center off-axis, nonuniform illumination, and aberrations
of the optical lens of the imaging system. The mismatch between the depth of
70 Metrology and Inspection Equipment 1533

focus and 3D pattern structure along with uneven detector response will result in
the asymmetry of the final image. This causes a deviation between the measured
line center and the line center of the actual pattern structure, resulting in the error
generated by the measurement system. The calculation of TIS is obtained by
averaging the overlay measurements of two images at the same position by
rotating the tool from 0 to 180 . In order to eliminate the effects of TIS, a
comprehensive evaluation and a repeated design for the light path are often
required to reduce the complexity of the system and to enhance the alignment
of the overall optical system.
2. WIS: It is the error caused by the center line displacement due to the asymmetry
of the pattern structure used for the overlay measurement on the wafer which is
caused by the device manufacturing process. Process asymmetry is a large
component of the observed measurement errors, and even if the measurement
system is perfect, this systematic error still exists.
3. TMU: This is a measure of the maximum possible error of an overlay measure-
ment system, including four error components, namely dynamic accuracy, TIS
variability, overlay pattern fidelity, and tool-to-tool matching error. In order to
reduce the TMU of the overlay measurement, it is necessary to use a higher
sample measurement density.

Critical Dimension Scanning Electron Microscope (CD-SEM)

CD-SEM is one of the important metrology tools for IC manufacture. It is used for
CD (critical dimension) online monitor and performance monitor of major pro-
cessing tools like scanner and clean track. CD-SEM is also very important during
the new production development process. It is widely used for the optical proximity
correction (OPC) modeling data collection and correction.
Currently major vendors of CD-SEM are Hitachi High-Technologies and Applied
Materials.

Operation Principle of CD-SEM

The Fig. 70.3 shows the imaging principle of SEM. From the cross-sectional views
of samples, we can see the effective area of e-beam action related with the e-beam
incident angle. The pattern edge will always be bright on the SEM image because of
the higher secondary electron generation ratio. Thus we can calculate the pattern line
width from the SEM image.

Application of CD-SEM in IC Manufacture

Different from SEM tool in lab, the CD-SEM for IC manufacture is a high-speed and
full automation machine with a powerful auto-pattern recognition function. These
days, the size of CD measurement pattern may be 10 nm or even smaller, but the
1534 F. Yang

Fig. 70.3 Imaging principle of SEM

Fig. 70.4 Typical flow chart

of CD-SEM auto-
measurement

moving accuracy of wafer stage is still about 1 um. As such, CD-SEM will use
multistep addressing method to improve the accuracy of pattern location. The tool
will try to find a unique pattern for addressing in lower magnification at first, then go
to the measurement position by high accuracy e-beam shift according to the fixed
70 Metrology and Inspection Equipment 1535

offset from the addressing point to the measurement point. Figure 70.4 depicts a
typical flow chart of CD-SEM auto-measurement.
After capturing the image of measurement pattern, CD-SEM will execute CD
measure and upload the results to data management system. In order to show the
actual product performance by more precise data measurement, the algorithm of
CD-SEM measurement also needs the continuous optimization and improvement.
To adapt to the development of semiconductor technology, many new measurement
methods are developed, such as edge roughness, gap, wiggling, overlay, and center
gravity. However, measurement precision and sensitivity to the process variation are
always the key factors for CD-SEM.

New Challenges for CD-SEM by the Development of Semiconductor

Manufacture Process

1. Because of e-beam radiation on the wafer directly, some types of photoresist (e.g.,
ArF resist) will have shrinkage effect, which makes the measured CD value have
a difference with the actual CD before measurement. In order to minimize the
shrinkage effect, therefore, CD-SEM has to improve the scan speed of e-beam to
minimize the radiation time. Lower applied voltage, lower magnification, and
lower scanning frame number can also be helpful, but image quality becomes
worse at the same time. As such, to develop the high-quality image processing
technology to achieve the measurement accuracy of the image is highly
important.
2. With the rapid development of semiconductor industry, the critical dimension
(CD) of technology node becomes smaller and smaller, which requests more for
the resolution and precision of CD-SEM. The solution is to improve the physical
resolution by the optimization of electron optics system, develop a high-quality
image processing technology, and develop an auto-calibration e-beam system for
the stability of long-term operation in CD-SEM.
3. 3D NAND memory technology received much attention in recent years. Now
CD-SEM is not only used for the CD measurement of current processing layer,
but also to check the overlay with bottom layer or to measure the bottom CD of
deep vias/trenches. The solution of improvement is to provide much higher
operation voltage and current for electron beam and modify the signal detector
system so as to collect the secondary electron signal and also the backward
scattering electrons (BSE) signal at the same time.
4. OPC 2D pattern modeling.

To load the GDSII design layout into the CD-SEM system and overlap the actual
SEM image with the GDSII layout by the high accuracy pattern matching function,
then it is able to get the contour file from the SEM image, and send it back to GDSII
modeling system to modify the OPC design.
1536 F. Yang

Optical Thin Film Metrology Equipment

In the IC manufacturing processes, silicon wafers are subjected to multiple deposi-

tion, etch, and polishing steps. To ensure that each process step meets the design
specifications, thin film thicknesses and their properties (such as refractive indices
and extinction coefficients) need to be accurately determined. Based on the principle
of multi-interface optical interference, the optical thin film metrology equipment is
the most commonly adopted thin film measuring tool in the IC production lines. Its
measurement is precise, swift, and noncontact, also damage free or contamination
free to the measured wafers. The optical thin film metrology equipment can measure
transparent dielectric films (such as various oxide thin films, nitride films, and
photoresists), semiconductor films (such as polysilicon films and SiGe films), and
very thin metal or semimetal films (such as TiN films, Ti films, Ta films, and TaN
films).
The optical thin film metrology equipment employs the high-resolution broad-
band spectroscopic technology with a small measurement spot, and the model-based
multiparameter real-time regression algorithm. The design of the optical system
takes into account the focused spot size of the probe beam on the wafer surface,
the reflected flux in the whole spectral range, and the resolution of the spectral
acquisition system, enabling the fast acquisition of the reflected beam spectrum from
a small measurement area in an integral time of milliseconds. Based on adequate
dispersion models of the thin film materials and the principle of multi-interface
optical interference (Fresnel’s equations), the onboard computation software per-
forms the real-time regression analysis on the constituent thin film thicknesses
and/or optical constants to fit the acquired spectrum. As the best fit is reached, the
film thicknesses and/or their optical constants are then determined. To have a
trustworthy result, the acquired spectrum must bear enough sensitivity to the film
thickness and the optical constants. In addition, the fast and accurate numerical
fitting method with flexible and efficient dispersion models is also very critical to the
measurement capabilities of optical thin film metrology equipment. In order to
maximize the throughput of the equipment, a parallel processing scheme is adopted
for the regression calculation, the spectral acquisition, and the wafer handling.
Two types of optical spectrum measurement methods are commonly applied in
optical thin film metrology equipment: ellipsometry and reflectometry. In the
ellipsometry, the light beam from the source is incident on the measured wafer
surface at a tilted angle (near the Brewster angle) via a polarizer and an optical
focusing system, and is reflected by the film surface and underlying interface(s). The
reflected beam then passes through the collecting optical system and analyzer, and
finally is collected by the spectrometer. By constantly rotating either the polarizer or
the analyzer, the spectra of optical field amplitude ratio (tanφ) and phase difference
(Δ) between the P-polarized component (parallel to the incident surface) and the
S-polarized component (perpendicular to the incident surface) of the reflected light
are extracted simultaneously from the spectrometer output. Tanφ and Δ are functions
of wavelength, film thicknesses, and their optical constants, which are determined by
Fresnel equations and material dispersion models.
70 Metrology and Inspection Equipment 1537

Fig. 70.5 Fitting result of ellipsometry spectra

Therefore, by conducting the regression calculation on film thicknesses and/or

dispersion optical constants, it can make the calculated spectra match the measured
pair, and then the values of thin film thicknesses and/or optical constants are
obtained. Figure 70.5 shows an example of the fitting result of ellipsometry spectra.
Because the spectra obtained by the ellipsometry measurement are the optical field
intensity ratio and the phase difference between the P-polarized light and the
S-polarized light of the reflecting light, the influence of temporal variation and
long-term decay in light intensity is eliminated. This results in the higher degree of
precision and stability in ellipsometry measurement. Furthermore, ellipsometry
method can perform the higher sensitivity to the optical constants for films with
ultrathin thickness and complex multilayer thin film structures.
Compare with the ellipsometry measurements, reflectometry makes use of
normal-incidence broadband reflectance spectrum (intensity ratio between reflected
light and incident light) to measure the film thickness. The reflectance spectrum does
not contain any information about the phase change characteristics of oblique
incidence near the Brewster angle as is the case with the ellipsometry. In addition,
a separate reflectance measurement must be done on a standard bare wafer in
advance to characterize the incident light intensity and then construct the reflectance
spectrum of the wafer. Thus, the normal-incidence reflectance is much less sensitive
to the film thickness and optical constants than the ellipsometry measurement, and is
prone to the light source intensity fluctuation, resulting in lower measurement
precision and stability, and limited applications in the front-end processes. Reflec-
tometry based optical thin film metrology equipment is mainly used for thickness
measurement of thicker films and single-layer films.
In order to control the process consistency of wafer-to-wafer and die-to-die, the
measurement of the thin films and/or the optical constants need to be carried out on
the product wafers. The optical thin film metrology equipment is capable of
automatically finding the preset measurement location with its pattern recognition
system to complete the measurement, and uploading the result to the central
manufacturing control system. The above steps can be completed automatically
by the remote control system. The production line terminal can judge whether the
previous process (such as CVD, etching, etc.) is qualified according to the data
collected by the measurement equipment. Furthermore, according to the needs,
1538 F. Yang

it can adjust the process parameters of the corresponding production equipment to

correct the deviation. The obtained data can also be input into the subsequent
etching, CMP. and other equipment, as a reference of final values for the control
of etching, polishing, and other processes. The process of collecting, feeding back or
forward the measurement data, and adjusting the process parameters of the produc-
tion equipment are automatically realized by the advanced process control system
dedicated to the IC production line.
As the development of the IC process moves to finer scales, the area of the chip
used for monitoring is shrinking. Meanwhile, the process technology continues to
advance, thinner films and more various materials are used, along with narrowing
process windows. At the same time, the test area on the chip shrinks. All of these
challenges push the development of the optical thin film metrology equipment move
in the direction of higher sensitivity to the thickness and composition of thin film
materials (especially to multilayer structures), higher measurement precision, and
smaller beam spot.

Optical Critical Dimension (OCD) Measurement Equipment

The IC continues to grow toward increasing the device density and shrinking the
device feature size, and the manufacturing process window becomes smaller and
smaller. Any small variation in process parameters will cause changes in device
feature size, in which the most critical one is the gate linewidth. Any deviation
between photoresist line width after developing and the gate linewidth after etching,
the design feature size will directly affect the performance, yield, and reliability of
the final product, so advanced process control requires inline linewidth measure-
ments, often referred to as critical dimension (CD) measurements.
Due to the limitations of the wavelength of the incident light and the optical
resolution of the microscope objective, traditional CD measuring equipment based
on optical microscope imaging systems has been unable to meet the needs of CD
measurements in advanced process control. Currently, CD-SEM has become an
important CD measurement equipment due to its capabilities of high-precision CD
and linewidth variation measurement as well as line edge roughness (LER) mea-
surement. However, in the CD-SEM measurement, it is necessary to place the tested
wafer in a vacuum chamber, so the measurement speed is very low and the
equipment size is large, therefore it is not suitable to integrate with the process
equipment in the fab. Furthermore, high-voltage charge accumulation may damage
the sample materials, thus CD-SEM cannot effectively measure the linewidth of
poly-gate structure with multiedges, depth of STI, and cross-section profile of lines.
In addition, since CD-SEM can only measure few points of the linewidth each time,
multiple sampling measurements are required to obtain an accurate average
linewidth. Therefore, CD-SEM does not meet the requirements for critical dimen-
sion measurements in advanced inline process control applications. At present,
nonimaging optical CD (OCD) measurement equipment based on the principle of
diffraction optics has become the main tool for the advanced integrated circuit
70 Metrology and Inspection Equipment 1539

manufacturing process, which can accurately measure the critical linewidth and
other surface morphology dimensions of the device, and it shows the good repeat-
ability and long-term stability. A number of device feature size parameters can be
obtained in one time by OCD measurement. Previously, this required a variety of
measurement tools such as CD-SEM, atomic force microscopy (AFM), and optical
film thickness measuring instruments. OCD measurement methods are becoming
more widely used in the process control of the advanced integrated circuit
manufacturing because they are noncontact, nondestructive, also can simultaneously
measure multiple process characteristics, and enable inline measurement.
The optical critical dimension measurement system is a nonimaging linewidth
measurement system. The basic operation principle is shown in Fig. 70.6.

1. Acquiring spectral signals: Based on broadband polarized reflectometry measure-

ment technologies and broadband spectroscopic ellipsometry technologies, as
shown in Fig. 70.7, the broadband light beam is incident on the periodic structure
region of the test sample through the polarizer, and is diffracted by the structures
on the sample. The diffracted light contains the information such as the structure
dimensions and material properties on the sample. The zeroth order reflected
beam in the diffracted light is received by the spectral sensor through the analyzer,
and the signal processing is further performed to form a characteristic measure-
ment spectrum containing the information of the measured sample, in which the
physical presentation form may be reflectance Rs and Rp (reflectance of S-light
and P-light in elliptically polarized light), the description of the change in
polarization state, tanφ and cosΔ, the Fourier coefficients a and b of the polari-
zation state analysis, or the direct output of the Mueller matrix describing the

Fig. 70.6 Basic operation principle of the optical critical dimension measurement system
1540 F. Yang

Fig. 70.7 Broadband spectrum measurement by polarized reflectance measurement and

ellipsometric measurement

scattering process. At present, the spectrum measurement of the mainstream OCD

ranges from 210–1000 nm. For some applications (such as 3D NAND), equip-
ment manufacturers will also extend the spectral range to near infrared (greater
than 2000 nm). In summary, the wider the spectral range, the more applications
are covered.
2. Structure modeling and database building: OCD measurement technology needs
to optimize the design of the reference grating patterns according to the
manufacturing process and structure of the test device. These reference patterns
are usually fabricated in the scribe-line area or embedded in the die area.
According to the basic information of the test sample, such as the 2D or 3D
structure of the device, the materials used, and so on, a high degree of freedom
model is established, and a complex device structure under test is then charac-
terized by a series of geometric parameters, such as width, height (or thickness),
and sidewall angle, as shown in Fig. 70.8. According to the design parameters of
the test device and the system parameters of the measurement equipment, the
theoretical spectrum of the sample represented by the established model is
computed by the electromagnetic field numerical calculation method, such as
the rigorous coupled wave analysis (RCWA) algorithm. By changing each
modeling parameter of the test device with a small step size and within a certain
range, the above electromagnetic field numerical calculation is repeated to obtain
a new corresponding theoretical spectrum, thus creating a simulated theoretical
spectral library. Due to the large calculation quantity of the theoretical spectral
library, it is usually necessary to use a parallel computing server to perform the
offline independent calculations.
3. Spectral matching: Match the acquired measurement spectrum with the spec-
trum in the theoretical spectral library one by one, find a theoretical spectrum
70 Metrology and Inspection Equipment 1541

Fig. 70.8 Example of 2D/3D device structure modeling

that gives the minimum mean square error (MMSE) to the measured spectrum
as the best match, and assign the corresponding parameter combination values
adopted to generate this theoretical spectrum as the final results of measure-
ment. The matching calculation process is very fast and can be performed
synchronously when the OCD measurement equipment acquires the measured
spectrum.

OCD measurement errors mainly come from measurement equipment,

manufacturing processes, and computational algorithms. The existence of these
errors poses great challenges to the accuracy and long-term stability of OCD
measurements. Specifically, these error sources include the following four areas:

1. Equipment hardware containing many subsystems with setting parameters that

are unstable and random during the process of acquiring spectra, potentially
causing noise in the measurement spectrum.
2. Line edge roughness caused by manufacturing process variations.
3. The finite parameters used in characterizing sample modeling are limited.
4. The numerical error from the electromagnetic field numerical computation
algorithms.

At present, suppliers of OCD measurement equipment mainly include

KLA–Tencor Corp., Nanometrics Inc., Nova Measuring Instruments, and Raintree
Scientific Instruments (Shanghai) Co., Ltd.
1542 F. Yang

Defect Inspection Equipment of Bright Field Optical Microscope

for Patterned Wafer

The defect inspection equipment for optical patterned wafer adopts high-precision
optical inspection technology to detect and identify the nm/μm scaled defects and
contaminants on the wafer. Then the inspection results are reported to the IC
manufacturers to reveal the product quality problems of the wafers in different
production nodes and confirm whether the operation of the process equipment is
normal, so as to achieve the goal of improving production yield and saving produc-
tion costs.
The inspection equipment adopts high-resolution optical imaging technology as
the main technical means. Based on the material properties and structural character-
istics of the wafer surface, it performs the precise selection and design for the
illumination and imaging optical systems, the brightness and spectral range of the
light source, as well as the design of the photoelectric sensors. The equipment is
divided into two categories: bright field and dark field. The definition is based on the
relationship between the illumination light angle and the acquisition light angle by a
conventional optical microscope. The bright field means that the illumination light
angle and the acquisition light angle are exactly the same or partially the same, so the
resulting image on the photoelectric sensor is formed by the reflected light in which
the incident light is illuminated on the wafer surface and reflected back by the wafer;
and the dark field means that the illumination light angle and the acquisition light
angle are completely different, so the obtained image on the photoelectric sensor is
formed by the scattered light in which the incident light is illuminated on the wafer
surface and scattered back by the 3D structures of the patterned surface. With the
continuous development of equipment, the definition of bright field and dark field is
also changing. Now, bright field generally means that the illumination light path and
the acquisition light path share the same microscope objective lens near the wafer
end, and the dark field means that the illumination light path and the acquisition light
path are completely separated in physical space.
The optical microscopy system of the bright field optical patterned wafer defect
inspection equipment is designed with the brighter light source, wider spectral range,
higher imaging resolution, larger numerical aperture, and larger imaging vision field.
The main traditional light sources are xenon discharge lamps or mercury vapor
discharge lamps. The latest light source is the laser continuous discharge lamp that
provides a smaller illumination arc scale for higher brightness of light source. The
applied wavelength range of the light source is 180–650 nm. Because of the wide
variety of materials on the wafer surface and the different optical properties of each
material, the wider spectral range provides more selections of stronger signals for
defects in different materials. Generally, the use range of different wavelength in the
optical system is selected by a grating type light filter or a transmission type light
filter. The illumination light path and the acquisition light path in the optical system
are the same at the wafer end, and the light path is separated by a beam splitter at the
light source end and the photoelectric sensor end. The optical system is mainly
composed of lens, and the material of lens is quartz crystal or magnesium fluoride
70 Metrology and Inspection Equipment 1543

crystal. In order to achieve a good optical resolution over a wide spectral wavelength
range, multilayer reflective lenses are added to the optical system to reduce chro-
matic aberration. The maximum numerical aperture can be 0.9 or higher. The
selection of illumination and acquisition angle can be achieved by adding circular
hole, circular ring, or other shaped apertures to the separate illumination and
acquisition light paths, and the effects of the bright field (the same numerical
aperture for illumination and acquisition), grey field (the numerical aperture of the
illumination and acquisition is different but there is an overlap), and the dark field
(the numerical aperture of the illumination and acquisition is not the same) can be
achieved. In the detection of different types of wafers, the defect inspection equip-
ment of bright field optical microscope for patterned wafer can use different config-
urations, that is, the combinations of different optical parameters and system
parameters, and the current number of equipment configurations is more than a
thousand. The optical structure of the bright field optical patterned wafer defect
detection equipment is shown in Fig. 70.9.
During the inspection process, after the wafer is automatically loaded by the robot
arm, the mobile platform holds the wafer by vacuum so that the surface flatness of
the wafer is kept within 10 μm. The pre-alignment is performed to locate the center
position and rotation angle of the wafer by observing the wafer edge and the notch
position, and the fine alignment is performed to locate each die on the wafer with
higher precision by observing the repeated die pattern on the wafer surface. The

Fig. 70.9 Optical structure diagram of the bright field optical patterned wafer defect detection
equipment
1544 F. Yang

mobile platform moves in an “S”-shaped path. During the movement, the optical
system takes pictures at different positions, and the acquired images are stitched
together to form a complete image of the entire wafer through the characteristic
recognition of adjacent overlapping regions. The entire wafer image is divided into
the image of each die according to the repeatability of the die unit. The detection
algorithm of defects is divided into the following two types:

1. The image of each die is compared with the image of the golden die obtained in
advance to identify the difference of the images, so as to obtain the image of
possible defects. Among them, the golden die image can be obtained by the
manually confirmed image from the good die, or can be obtained by combining
any images of the dies.
2. The image of each die is compared with the images of several neighboring dies to
identify the difference of the images, and obtain the image of possible defects.

The calculation and analysis of the images are performed in real time during the
scanning detection process, and the detection and recognition of defects are also
completed at the end of the wafer scanning.
The bright field optical defect inspection equipment for patterned wafers is
applied in the research and development for 10 nm node technology and is widely
used in the production of 14 nm and above processes. The major equipment
suppliers on the market today are KLA-Tencor (39 series, and 29 series)
and Applied Materials (UVision series).

Defect Inspection Equipment of Dark Field Optical Microscope

for Patterned Wafer

The defect inspection equipment of dark field optical for patterned wafer adopts
high-precision optical detection imaging technology to detect and identify the
nm/μm scale defects and contaminants on silicon wafers. The characteristics of the
dark field optical detection is that the illumination light path and the acquisition light
path are completely separated in physical space, so not only the incident angle of the
illumination light and the angle of the acquisition light are different, but also the
nature of the illumination light can be of various types.
The dark field optical microscope system of the optical patterned wafer defect
inspection equipment is designed for better noise control, higher imaging resolution,
higher detection scanning speed, and the like. The light source can be laser light
source, ring light, optical fiber lighting, etc., and the laser light source is mainly
adopted in high-precision applications for the defects in nanometer scale. The laser
light source has an emission wavelength of 193 nm, 266 nm, 355 nm, etc., and the
shorter the wavelength is, the better optical imaging resolution can be achieved.
Generally, it is necessary to have a higher intensity of the illumination for inspection;
however, too high the illumination intensity may exceed the damage threshold of the
wafer materials, so it should be avoided as much as possible. The laser beam is
70 Metrology and Inspection Equipment 1545

illuminated at a tilt incidence angle on the wafer surface to obtain the largest
scattered signal of defect particle, and the optical image acquisition system can
achieve the image acquisition with the maximum numerical aperture and maximum
vision field above the wafer. Due to the coherence of the laser, the periodic pattern on
wafer surface behaves as the periodic grating and produces the diffraction effect.
However, the technique of optical patterned wafer defect detection in the dark field
can perform a better detection effect for patterned surface with periodic arrays. The
periodic structure of the die surface will scatter the incident laser light to some
determined spatial solid angles, so that an adjustable spatial aperture corresponding
to the diffraction angle is placed in the optical path of the acquisition optical system
to effectively block the diffraction light generated by the coherent laser on the
periodic structure, therefore, the background noise of the image is compressed to
the maximum extent so as to obtain a better signal-to-noise ratio of the defect signal.
Figure 70.10 shows the optical structure of the optical patterned wafer defect
detection in the dark field.
The optical pattern wafer defect detection process and detection algorithm for the
dark field are similar to that for the bright field.
The defect inspection equipment of dark field optical for patterned wafer has been
adopted in the production of silicon wafers of 14 nm and beyond. The main suppliers
of such equipment on the market today are KLA-Tencor (Puma series) and Hitachi
High-Tech (IS series).

Fig. 70.10 Optical structure of the optical patterned wafer defect detection in the dark field
1546 F. Yang

Unpatterned Wafer Surface Inspection Tool

The unpatterned wafer surface inspection tool belongs to optical inspection equip-
ment for detecting the surface quality of the wafer and discovering defects on the
wafer surface. The operation principle is that the laser is irradiated on the wafer
surface, and the scattered light is collected through the multiple optical collection
channels. After the surface background noise is suppressed, the multichannel surface
defect signals are extracted by an algorithm, and finally the size and the classification
of defects are obtained. In addition, it can also be combined with other auxiliary
optical detection methods to comprehensively realize microscopic defects and the
macroscopic feature detection (such as surface roughness and large-scale fluctuation
in thickness) on the surface of the pattern-free wafer. The unpatterned wafer surface
inspection tool has a detection accuracy of up to 10 nm and the mass production
detection speed can be more than 75 wafers/h. It is mainly used for surface
inspection of bare wafers and film deposited wafers.
The defect types that can be detected by the unpatterned wafer surface inspection
tool include particle contamination, pits, watermarks, scratches, shallow pits, epi
stacking faults, CMP protrusions, crystalline pits, and slip lines. The system is
mainly applied in the following three types:

1. Chip manufacturers: mainly include IQC, process control (film, CMP, etc.), wafer
backside contamination detection, and equipment cleanliness monitoring
2. Wafer manufacturers: mainly include defect detection in process research and
development, and final inspection process before wafer delivery
3. Semiconductor equipment manufacturers: mainly include defect detection in
process research and development, and process quality assessment of equipment
(such as particle pollution)

The operation principle of the unpatterned wafer surface inspection tool is that the
laser beam is irradiated on a certain area of the wafer surface, and then the laser is
scanned on the entire wafer surface by the combination of the rotation of the wafer
and the radial movement of laser beam; when the laser beam encounters a defect
structure, the defect structure generates a scattered light signal, which is collected by
a large-diameter optical acquisition system and captured by a detector; the defect
position on the wafer surface is recorded, and the position information can synchro-
nize with an image detecting instrument such as an SEM to analyze and judge the
defects.
Through various types of laser feature modulation, multichannel signal acquisi-
tion and comprehensive analysis, and cluster analysis based on defect coordinate
positions, the inspection system can further obtain the types of defects. Laser feature
adjustment includes the adjustment of various illumination modes of the laser and
the adjustment of the polarization directions of the laser. The multichannel signals
are mainly wide field optical channel signals and narrow field optical channel
signals. Taking particle defects and pit defects as an example, particle scattering
70 Metrology and Inspection Equipment 1547

has a strong relative scattering intensity in a wide field and a low relative scattering
intensity in a narrow field; it is exactly on the contrary in case of pits. Particle defects
can be distinguished from pit defects by comparing the relative scattering intensities
of the wide field and narrow field optical channel signals. Similarly, different defects
have different quantifiable characteristics for vertical incidence illumination and
tilted incident illumination. Combined with spatial distribution characteristics, mul-
tiple types of defects on the wafer surface can be classified. In addition, the
unpatterned wafer surface inspection tool usually integrates the differential interfer-
ence contrast (DIC) technique of bright field illumination to detect the difference in
height of the wafer surface, which can be applied to detect macrodefects. The
background intensity of the surface scattering of the wafer is correlated with the
roughness of the wafer surface, so the characteristics such as the wafer surface
roughness can be measured while detecting the defects.
Figure 70.11 shows the optical structure of the pattern-free wafer defect detection
in the dark field.
From the point of view of the detection technology, the optical scattering intensity
of the defect is proportional to the sixth power of the defect size and inversely
proportional to the fourth power of the wavelength. Therefore, the high sensitivity
detection for smaller defects requires shorter optical wavelengths. Existing equip-
ment typically adopts DUV and UV band lasers as illumination sources to ensure
detection sensitivity. Combined with multisource illumination and signal extraction
algorithm optimization, optical intensity and detection speed can be improved. At
the same time, by optimizing the acquisition channel distribution, the aperture of the

Fig. 70.11 Optical structure of the pattern-free wafer defect detection in the dark field
1548 F. Yang

acquisition channel, as well as the acquisition signal, better sensitivity and classifi-
cation effects can be achieved.
The main suppliers of such equipment on the market today are KLA-Tencor
(Surfscan series) and Hitachi High-Tech (LS series).

Macrodefect Inspection Tool

The macrodefect inspection tool is based on optical image detection technology.

Combined with a variety of optical measurement methods, it can achieve detection
of defect greater than 0.5 μm on wafers. There are two detection methods for
macrodefect inspection tools. One method is to image the whole wafer surface.
This optical system can realize one-time imaging detection of the entire 300 mm
wafer surface, and the detection speed is extremely high, as shown in Fig. 70.12. The
other method is to image the partial wafer surface. The optical view field is limited to
the local wafer surface. It has a higher spatial resolution. In this method, the whole
image of the wafer surface is photographed by continuously scanning the wafer
surface. The detection result is obtained by the “die-to-die” comparison and other
image calculation methods, as shown in Fig. 70.13. These two methods adopt
different illumination methods to form the surface image of the wafer through
the reflected light signal of the wafer, and realize the detection and classification of
the scale and shape of the defects combined with the analysis and processing of the
image algorithm. The macrodefect inspection tool can detect patterned or non-
patterned wafers and also is commonly equipped with a higher-resolution micro-
scopic function for defect-review process.

Fig. 70.12 Schematic diagram of optical inspection system for the macrodefect detection with
full-wafer surface imaging function
70 Metrology and Inspection Equipment 1549

Fig. 70.13 Schematic diagram of optical inspection system for the macrodefect detection with
partial surface imaging function

The basic detection principle of the full-wafer surface imaging method is that
the image distribution of the reflected light or the diffracted light generated by
uniformly repeated pattern surface is relatively uniform or periodic; if the image
shows a difference in brightness distribution, it is considered that there are defects
on the wafer surface. Due to the different mechanisms and modes of influence on
the optical process by defects, the characteristics of the image brightness distri-
bution corresponding to each type of specific defect are also different. Therefore,
defects can be classified based on different attributes of the characteristics. For
example, due to the defocusing defect of a complete region caused by the focusing
error of the exposure equipment, and the defocusing defect caused by the dirt on
the back side of the wafer, the images on the light intensity distribution show the
characteristics of rectangular dark regions and small annular dark regions,
respectively.
The basic detection principle of the partial surface imaging method is to perform
high-speed image shooting under the continuous motion of the wafer surface; to
extract a user-defined measurement region by pattern match; and to compare the ROI
in the measurement region according to the rules set by the user. Finally, the
comparison results and test reports are generated according to the classification
rules. The comparison methods between images usually include gray scale compar-
ison and gradient comparison. The equipment typically includes 1 to 20 magni-
fication microscopic imaging optical system, and the detector is an array sensor with
a high-speed transmission interface. The illumination system includes bright field
illumination, dark field illumination, and gray field illumination, of which the dark
1550 F. Yang

field illumination can have multiple illumination angles; the light source can be a
xenon flash lamp or an LED light source.
In macrodefect inspection tool, optical imaging systems are one of the key
portions of detection technology. Since there is no need to detect the characteristic
pattern of the single unit, a high magnification optical lens is not required. There are
three main types of optical acquisition methods for optical imaging systems.

1. Diffraction signal imaging: It mainly collects and images the first-order diffracted
light formed by the reflection of the wafer surface. This method is mainly applied
to detect the defects on the surface of the repetitive structure, such as defocusing
defects.
2. Reflected signal imaging: It usually collects and images the light reflected from
the wafer surface. This method is mainly applied to detect large size defects on the
wafer surface, such as photoresist loss.
3. Scattered signal imaging: It usually collects and images the light scattered on the
wafer surface. This method is mainly applied to detect small size defects on the
wafer surface, such as particle contamination.

The macrodefect inspection tool can include optical systems of different magni-
fications for optimal image resolution. The illumination methods for the detection
are divided into bright field illumination, dark field illumination, and gray field
illumination to meet different image contrast requirements. The illumination optical
system is typically Euler or critical illumination, and telecentric optics systems can
be adopted to achieve more consistent illumination. The macrodefect inspection tool
typically includes a variety of focusing systems that can be applied to focus on
different sample surfaces and multilayer samples. In order to adapt to the smaller
pitch wafer structures, DUV and UV light sources can be adopted to improve the
detection resolution.
The macrodefect inspection tool is mainly used in control of the processes such as
lithography, CMP, etching, thin film, outgoing quality control (OQC) and incoming
quality control (IQC), WLCSP, and FOWLP.
The macrodefect inspection items include the following four categories:

1. Front inspection: including particle contamination, scratches, defocusing defects,

photoresist loss, photomask ID, and alignment errors
2. Back inspection: including contamination and scratch defects on the back side of
the wafer
3. Edge inspection: including coverage, concentricity, uniformity detection of edge
bead removal (EBR), and detection of edge notches and edge cracks
4. Wafer geometry inspection: inspecting the geometry of wafers. The main sup-
pliers of such equipment on the market today are KLA-Tencor (CirCL series),
Nanometrics (Spark series), Rudolph (NSX series), and Ruili Scientific Instru-
ments (FSD series)
70 Metrology and Inspection Equipment 1551

Electron Beam Wafer Defect Inspection Equipment (EBI)

Electron beam wafer defect inspection (EBI) is the front-end process control equip-
ment which uses scanning electron microscope (SEM) to directly detect defects on
patterned wafer surface.
Figure 70.14 is a structural diagram of the EBI equipment. Its core is a SEM
system. A focused electron beam is scanned across the wafer’s surface; returned
secondary electrons and backscattered electrons are collected and converted into
grayscale images corresponding to the surface morphology of the wafer. By
comparing images of different dies on the wafer, or by direct comparison of images
to the chip design layout data, etching process induced defects or design defects
can be found. Unlike conventional laboratory SEM, industrial equipment needs to
meet the requirements of wafer fabs for high throughput while avoiding damage to
wafer devices. Therefore, performance emphasis is placed on higher scanning and
image acquisition rates, larger scanning fields, high-speed sample positioning
capabilities, and satisfactory image quality at low incident voltages. Different
from the extremely high-resolution critical dimension SEM (CD-SEM) and the
defect review SEM, it does not always pursue the highest resolution – its resolution
is consistent with the requirements of inspecting the advanced technology nodes of
the ICs. Equipped with in-line automatic data processing capabilities such as
automatic defect inspection and classification, it becomes fully automated indus-
trial equipment.
Compared to bright field and dark field wafer defect inspection equipment, EBI
equipment offers higher resolution for physical defects (particles, protrusions, brid-
ges, voids, etc.) and unique ability to detect hidden defects through voltage contrast.
For hidden defects such as contact and via open, short, or with excessive resistance
due to internal voids, as well as short-circuited conductor, when bombarded by
electron beam, different potentials are formed on the surface due to different rate of
charge release compared with normal case, resulting at different secondary electron

Fig. 70.14 Structural schematic diagram of an EBI equipment

1552 F. Yang

yields and thus different local gray levels on the image, which can be detected
through image comparison. Although being superior in terms of performance, the
weakness of the electron beam equipment lies in its point-by-point scanning nature,
which determines that its inspection speed is too slow; compared with that of the
optical defect inspection equipment, the gap can be more than a thousand times; and
it is far from meeting the requirements of wafer fabs for inspection throughput.
Therefore, it has yet-to-replace optical equipment in large scale to undertake in-line
inspection tasks and is mainly used for the development of advanced technology
nodes. The current market size of patterned wafer defect inspection equipment is
about 1.8 billion US dollars per year, of which EBI equipment accounts for about
12%. Currently major suppliers are Taiwan’s Hermes Microvision (acquired by
ASML of the Netherlands in 2016) and Applied Materials of the USA. Former
suppliers also included KLA-Tencor of the USA, which first introduced EBI equip-
ment to the market, and Hitachi of Japan.
Due to the limitation of its inspection rate, the main operating mode of EBI
equipment is sampling; the usual practice is to inspect the same small area of each
die on the wafer, including critical areas or hot spots, to obtain the characteristic
defect distribution map of the entire wafer. Operating voltages of around 1 kV are
common to avoid charging the wafer surface and prevent damage to the wafer
material due to excessive electron penetration depth. The maximum operating
voltage is 3 to 5 kV. Based on the need for inspecting some hidden defects and 3D
structures, there has been a recent trend to increase the maximum operating voltage
to more than 10 kV. At the same time, with the gradual reduction of the line width of
the IC, the minimum resolution required for EBI equipment is also shrunken
accordingly; currently it has reached 1–2 nm level to meet the requirements of
16/10 nm technology nodes and beyond.
How to further improve the inspection throughput has always been one of the
most important issues in the development of EBI equipment. Existing commer-
cial products are based on single-electron beam SEM; throughput increase can be
achieved mainly by increasing the current density of the focused electron beam to
support the increase in pixel scan rate while maintaining sufficient image signal--
to-noise ratio. Such measure is difficult to achieve improvement by orders of
magnitude. Another direction is to develop multicolumn array and single-column
multibeam system to achieve parallel operation of multichannel beam scanning
and image acquisition, and significantly improve the image acquisition rate.
However, to achieve inspection throughput comparable to that of optical
defect inspection system, it is necessary to realize the parallel operation of
hundreds or thousands of electron beams, which is a considerable technical and
equipment cost challenge. At present, it seems the first commercialization could
be the single-column multibeam type system with limited number of electron
beams; by dividing a large scanning field into multiple small fields, each small
field scanned by an individual electron beam, fast acquisition of large-size images
can be achieved. Table 70.1 shows commonly used electron beam wafer defect
inspection equipment.
70 Metrology and Inspection Equipment 1553

Table 70.1 Electron beam wafer defect inspection equipment

Main product Reference
lines on sale Manufacturer Key reference performance price
eScan, eP, Hermes microvision, Common operating voltage: US$ four to
PROVision Applied Materials 500–3000 V; common operating eight million
current: 1–200 nA; common pixel
acquisition rate: 100 megapixel per
second; minimum resolution: 1 to
2 nm; scan rate: Square millimeters to
tens of square centimeters per hour

Defect-Review Scanning Electron Microscope

With the continuous development of ULSI technology, especially in the advanced

process by which the critical dimension enters into the nanometer level, defects have
become one of the important factors affecting the product yield. Whether the specific
profile and elemental composition of defects generated in the process can be clearly
observed becomes a key factor to solve the process defects. Therefore, it is necessary
to introduce a defect-review scanning electron microscope in the IC manufacturing.
The defect-review scanning electron microscope is a kind of SEM-OL. It combines
online optical defect equipment and electron beam scanning inspection equipment to
inspect and analyze the defects generated in each key process step of the IC
production. The usual inspection method is to add a defect inspection site after
some key process steps in the production line. The bright field, dark field optical
defect inspection equipment or electron beam defect inspection equipment is first
applied to scan and inspect the wafer surface. According to the comparison of the
graphical signal characteristics in the scanned area, the defect inspection equipment
will discover and mark the coordinate information of the potential defects. The
defect data management system then delivers the defect coordinate information to
the defect-review scanning electron microscope, in which the defects at the
corresponding positions are found according to the imported coordinate information.
Thereafter, to observe the profile and shape of the defects, the size and the back-
ground environment of the defects are obtained by a high-magnification electron
microscope, while the elemental composition of the defects is determined by energy-
dispersive X-ray (EDX) microanalysis to figure out the root cause of the defects and
the related process steps. With the information, the defect improvement can be
effectively implemented and achieved. Figure 70.15 shows the defect inspection
and defect analysis flow chart.
The image formation principle of the defect-review scanning electron microscope
is to emit an energetic electron beam into the wafer surface by an electron gun so that
energetic electrons collide with atoms of materials on the wafer surface to excite
secondary electrons and backscattered electrons, as well as characteristic X-ray and
other signals. The SEM-OL achieves the high-resolution and high-magnification
1554 F. Yang

Fig. 70.15 Defect inspection and defect analysis flow chart

Fig. 70.16 Operation

principle diagram of defect-
review scanning electron
microscope

observations by collecting these electron signals, as shown in Fig. 70.16. The

secondary electron signal and the backscattered electron signal are adopted to
form a surface profile of the observed sample, and the characteristic X-ray signal
is applied to identify the elemental composition of the sample surface or defects.
The defect-review scanning electron microscope consists mainly of a vacuum
system, an electron-optical system, and a signal detection and amplification system.
The function of the vacuum system is to provide a vacuum environment for the
electron gun filaments to generate the electron beam and to prevent the filaments
from being oxidized in the air while increasing the mean free path of the electrons.
The function of the electron-optical system is to generate a scanning electron beam
that excites the physical signals, such as secondary electrons and backscattered
electrons required for imaging. The function of the signal detection and amplification
system is to detect and collect the physical signals excited by the electron beam on
the sample surface, and then amplify these physical signals as a modulating signal
for the imaging system, in which the modulating signal can be converted into a
scanned image of a certain pattern or defect profile on the sample surface with the
cathode ray screen, as shown in Fig. 70.17.
When performing defect analysis, it is not only necessary to obtain a scanned
surface profile image of the sample, but also necessary to know the elemental
composition of the defect so as to more accurately determine which process the
defect comes from. At this time, EDX microanalysis is required for the analysis. The
principle is that when the energetic electrons are incident on the sample, the inner
70 Metrology and Inspection Equipment 1555

Fig. 70.17 Operation principle diagram of defect-review scanning electron microscope

level electrons of the atom are excited to the outer level of higher energy, or the inner
level electrons are directly excited outside the atom, causing the energy of the atom
raised to the excited state. The high-energy state is unstable, therefore this excited
atom will soon jump back to the ground state and emit its specific characteristic
X-rays. Different elements perform different specific characteristic X-rays. By
collecting the energy and intensity of X-ray photons, the type and content of
elements can be identified and analyzed.

X-Ray Metrology Equipment

Two categories of X-ray metrology equipment are used in semiconductor metrology,

i.e., (1) X-ray fluorescent spectroscopy (XRF) and (2) X-ray diffraction and reflec-
tometry (XRD/XRR).

X-Ray Fluorescence Spectroscopy (XRF)

In 1923, George Charles de Hevesy proposed the quantitative analysis of elements

by X-ray fluorescence spectroscopy, but due to the capability limitation of the
element detection technology at that time, X-ray fluorescence spectroscopy was
not practically applied. Until the end of the 1940s, with the progress of X-ray
tubes, semiconductor detectors, and beam splitting technology, this method began
to enter the rapid application and development stage, and soon after X-ray fluores-
cence spectroscopy became a very important test analysis and characterization
method. The principle is that when X-rays are applied to irradiate the test sample,
the test sample is excited to emit the fluorescent X-rays of various wavelengths, in
which these fluorescent X-rays act as the fingerprints of elements. Then the mixed
1556 F. Yang

X-rays are separated by wavelength (or energy) to separately measure and analyze
the individual X-ray intensity of different wavelengths (or energies), so as to achieve
the quantitative and qualitative analysis. The analytical equipment with this function
is called XRF. Because X-rays have specific wavelengths and specific energies, the
instrument is mainly divided into wavelength dispersion type and energy dispersion
type according to the wavelength and energy.
The sample can be qualitatively and quantitatively tested and analyzed by
XRF. In IC manufacturing, it is commonly used for dopant concentration deter-
mination and qualitative analysis of impurity elements. In the qualitative test
analysis, the wavelengths and energies of the fluorescent X-rays for various
elements are also different, so the composition analysis of elements can be
performed. As the wavelength dispersion type spectrometer is applied, the
X-ray wavelength λ for a sample with a specific interplanar spacing can be
determined by the 2θ angle rotation of the detector, so as to determine the
composition of elements. When an energy dispersion type spectrometer is applied
for the analysis, the energy is identified by the channel to determine the type and
composition of elements. However, in the actual test, qualitative analysis can be
performed by the spectral line matching method with the automatic qualitative
recognition algorithm software, so as to obtain qualitative results; when the
composition of elements in sample is too low or the inter-element spectral lines
interfere with each other, it is necessary to apply the manual identification
analysis to analyze elements. As the manual identification analysis is performed,
it is necessary to know the comprehensive information such as the source and
property of the sample in advance to make the judgement. In the CVD on
borophosphosilicate glass (BPSG) for dielectric deposition process of the IC
production, the XRF is commonly applied to analyze and detect the concentration
of boron and phosphorus in the BPSG film.

X-Ray Diffraction and Reflectometry (XRD/XRR)

German physicist Max Theodor Felix von Laue found that when the X-ray wave-
length is close to the spacing of the atomic plane in the crystal, the crystal can act as a
spatial diffraction grating for X-rays. When an X-ray beam is irradiated onto the
substance, the atoms will generate scattered waves due to the scattering of atoms in
the substance. These scattered waves will affect each other and lead to the diffrac-
tion. These diffracted waves are superimposed with each other, and then the intensity
of diffracted waves is enhanced in some directions but weakened in other directions.
By analyzing the diffraction results, the internal structure of the crystal can be
revealed. On this basis, the British physicists Sir William Henry Bragg and William
Lawrence Bragg proposed the famous Bragg equation based on the crystal
diffraction:

2d sin θ ¼ nλ, n ¼ 1, 2, . . .
70 Metrology and Inspection Equipment 1557

where d is the distance between parallel crystal planes, λ is the wavelength of the
X-ray, and θ is the angle between the incident beam and the crystal plane.
The XRD adopts X-ray diffraction principle to accurately measure and analyze
materials, such as the characterization for the crystal structure and stress of sub-
stances. It can also be used for qualitative analysis, quantitative analysis, and
phase analysis of materials. It is widely used in the IC manufacturing and
advanced process development fields. For example, as the single crystal material
test analysis is performed, if the single crystal under test is at different angles from
the incident beam, these crystal planes satisfying the Bragg diffraction will be
detected, and peaks with different diffraction intensities are displayed on the
obtained XRD curves. For amorphous materials, the XRD pattern of the amor-
phous sample only shows some diffused scattering peaks due to the absence of
long-range ordered arrangement of atoms in the internal structure of the amor-
phous materials. With the development of IC technology and the shrinking of
technology nodes, XRD testing technology is more widely used in the R&D of
advanced IC pilot technology and in the production process. For example, in the
technology of SiGe source-drain replacement and high-mobility material (Ge and
III-V) channel replacement, XRD equipment can be applied to analyze the thick-
ness and strain of the epitaxial film.
While the XRR is based on the principle of X-ray reflection; it is very sensitive to
the surface properties of materials and can be used for the nanoscale nondestructive
inspection. The materials that can be tested include crystalline materials and amor-
phous materials. It is an indispensable film property testing method in the advanced
process R&D of IC manufacturing. With the further development of IC technology
and the extension of equipment application capabilities, XRR test analysis has
become more important in the R&D of advanced process and technology. Its main
applications include the following:

1. Measurement of deposited film thickness and interface roughness, and high-

accuracy measurement of layer density
2. Measurement of the structural properties of multilayer films used in HKMG
process integration
3. Measurement and analysis of pore density of low-k film and diameter in the
copper interconnection process

At present, X-ray metrology equipment adopted in IC manufacturing is mainly

produced by manufacturers such as Malvern Panalytical, Thermo Fisher Scien-
tific, and Bruker. The detection accuracy and software analysis capabilities of
measurement equipment produced by these companies are quite different.
Among them, the X-ray fluorescence spectrometer and software produced by
Malvern Panalytical demonstrate good performance and are widely used. The
XRD adopted in the manufacture of ICs is mainly produced by Philips and
Bruker. Among them, the JVX7300 LSI series developed by Bruker for advanced
IC technology integrates with automatic loading system and data processing
1558 F. Yang

software, and it can perform the nondestructive testing and analysis on the small-
sized FinFET devices. It is widely used in advanced process research and
development, with a market price of approximately one million USD.

Atomic Force Microscope (AFM)

AFM was developed in 1986 by Gerd Binning, Calvin Forrest Quate, and Christoph
Gerber, with the atomic-scale resolution. The principle is to use a weak force
between the tip and the atom on sample surface to perform a grating type scan on
the sample surface to obtain the information about the sample. The specific method
is to mount a tiny tip on one end of a micro-cantilever that is very sensitive to the
atomic force, and fix the other end of the cantilever; by using the tip to scan the
sample surface and obtain the sample surface information by a very weak repulsive
force between the tip atom and the atom on sample surface, Fig. 70.18 shows the
operation principle diagram of AFM.
The detection method can detect the physical properties of nano-regions of
various materials and samples in the atmosphere or the liquid environment. At
present, AFM has been widely used in the research and experiment fields of various
nano-related disciplines such as semiconductor, biology, chemical engineering, and
medicine, and has become the basic tool for nanoscience research.
In the manufacture of ICs, AFM can perform physical property tests such as
surface profile scanning, surface conductivity test, electrostatic distribution mea-
surement, and friction force detection. For example, in film growth, CMP, etc., the
roughness of the film surface can be measured by the AFM technology, and the
process stability can also be monitored to control the device performance and
ensure the device yield. There are three commonly adopted scanning modes of
AFM, namely contact mode, noncontact mode, and tapping mode. The test prin-
ciples of these three scanning modes are different, so it is necessary to select
different scanning modes according to the different structural forms of the sample

Fig. 70.18 Operation principle diagram of AFM

70 Metrology and Inspection Equipment 1559

surface to be tested, the characteristics of the materials themselves, and the

research requirements.

Contact Mode

The contact mode means that during the test, the tip is always in slight contact with
the sample surface. Two modes of constant height or constant force are applied to
slide scan the sample surface and a stable, high-resolution image can be obtained by
the contact mode. However, if the sample is too soft in texture, the sample surface is
easily in direct contact with the tip, which can easily cause scratch damages to the
sample. Therefore, the contact mode is generally not suitable for studying samples
such as bio-macromolecules that are easily moved and deformed.

Noncontact Mode

In the noncontact mode, the tip is always above the sample surface and is not in
contact with the sample. It detects the electrostatic force and the van der Waals force
between atoms. This mode can effectively improve the sensitivity of the microscope.
The disadvantage of this measurement mode is that it is easy to image unstably when
the distance between the tip and the sample is too far, which increases the difficulty
of operation, so this mode is usually not suitable for imaging in liquid environments.

Tapping Mode

The tapping mode means that the micro-cantilever is forced to vibrate near its
resonant frequency, and the oscillating tip gently taps on the sample surface. Since
the tip is intermittently in contact with the sample, this operation mode is also
referred to as the intermittent contact mode. This mode can be used in both
atmospheric and liquid environments, with almost no damage to the sample. Fur-
thermore, it performs a large linear operation range which makes the vertical
feedback system highly stable. Therefore, repeated measurements of the sample
can be achieved. A comparison of these three scanning modes of AFM is shown in
Table 70.2.

Table 70.2 Comparison of three scanning modes of AFM

Scan mode Advantages Disadvantages
Contact mode High test speed and high resolution Damage to the sample
Noncontact No damage to the sample Low resolution and low
mode scanning speed
Tapping mode High resolution, no damage to samples, and Slow test
high stability
1560 F. Yang

Focused Ion Beam (FIB) Microscope

In the stage of IC packaging and testing, a large number of focused ion beams (FIBs)
are required to perform the fine positioning and cutting. The basic operation princi-
ple involves the use of electrostatic lenses to focus the ion beam accelerated by the
electric field to a small size for the microcutting of the material. The currently
adopted ion source is liquid metal gallium because gallium has a low melting
point, low vapor pressure, and good oxidation resistance. Under the action of an
applied electric field, liquid gallium is formed to a fine tip. A negative electric field is
applied to extract the gallium ion beam from the gallium tip. The ion beam changes
the beam size through the first-level electrostatic lens and a series of varying
apertures, and then undergoes secondary focusing through the second-level electro-
static lens to focus the ion beam to the sample surface, thereby achieving the purpose
of cutting by the physical collision on the sample surface. In order to meet different
cutting requirements, the industry has also developed focused ion beam equipment
with different ion sources, such as xenon ion source focused ion beam equipment for
the fast and large area cutting, and helium ion source focused ion beam equipment to
reduce ion damage to samples.
Nowadays, the feature size of semiconductor devices is getting smaller, and the
cutting position is getting finer. Therefore, the focused ion beam equipment needs to
perform the real-time observation capability while cutting samples. Ion beam scan-
ning bombards the sample surface to excite secondary electrons and secondary ions
of the material. These particles can be collected for imaging by a detector. Because
the ion beam can damage the sample when it scans the sample surface, thus the
advanced focused ion beam instrument is typically a two-beam system that has both
an ion beam system and an electron beam system. The electron beam is applied to
excite secondary electrons on the sample surface, in which the image is formed by
detecting these secondary electrons. The principle and function are similar to
SEM-OL. When the ion beam cutting is performed, observing the image with the
electron beam system can avoid the ion beam cutting damage, and also effectively
improve the image resolution.
The FIB is also equipped with a variety of auxiliary gas sources, of which the
etching gas source can perform selective etching according to the etching rate of the
different substances by the gas, thereby achieving the accelerated cutting or material
removal. In addition, the electron beam or the ion beam energy is applied to
decompose the organometallic vapor or vapor phase insulating materials for them
to deposit in a specific region. The deposited conductive thin film can be used as a
protective layer for cutting the cross-section, avoiding the ion bombardment induced
damage on the sample surface during the cutting process, and preventing the drift
caused by the charge accumulation effect on sample surface; when the circuit is
modified, the deposited metal film can be used as a conductive wire, and the
deposited nonconductor film can be used as an insulator for isolation.
The main applications of FIB in IC fabrication include wafer fault analysis,
transmission electron microscopy (TEM) specimen preparation, and interconnection
line repairing. The wafer fault analysis is a function to identify the reason of the
70 Metrology and Inspection Equipment 1561

Fig. 70.19 Applications of FIB technology

physical failure for a particular region. In practice, the function of observing while
cutting can be achieved for finding the location where the problem occurs, as shown
in Fig. 70.19a, b. At present, the vast majority of TEM sample preparation is
achieved by FIB, as shown in Fig. 70.19c. When the interconnection line is repaired,
combined with the function of fixed-point cutting and wiring, local interconnection
line modification can be realized, as shown in Fig. 70.19d.

Fourier Transform Infrared (FTIR) Spectrometer

Infrared light is a segment of electromagnetic wave with a wavelength between

visible light and microwave. According to the different wavelengths, infrared rays
are classified into three types: near-infrared, mid-infrared, and far-infrared. Among
them, the mid-infrared rays (wavelength of 2.5 to 25 μm) can accurately reveal
various internal physical and structural features of the molecules. It is the most
effective to explore the chemical composition of substances and understand the
molecular structures. Fourier transform infrared (FTIR) spectrometer is mainly
composed of infrared source (high-pressure mercury lamp and silicon carbon rod),
interferometer, diaphragm, sample chamber, detector, and different infrared reflec-
tors for the qualitative and quantitative analysis of samples.
The basic principle of the FTIR spectrometer test is that the infrared ray emitted
by the light source is split into two beams by the beam splitter, and then is
respectively incident on the fixed mirror and the movable mirror. After being
reflected by the fixed mirror and the movable mirror, it is returned back to the
1562 F. Yang

beam splitter, and the movable mirror is under linear uniform motion. Therefore, the
two-beam infrared ray produced by the beam splitter generates an optical path
difference to form the interference. After the interference light shines on the sample,
the interference light signal containing the sample information is sent to the detector,
and an infrared spectrum in which the absorbance or transmittance variations with
the wave number (or wavelength) is obtained after the signal is subjected to Fourier
transformation. In the FTIR spectroscopy test analysis, the measured original infra-
red interferogram is a time-domain spectrum that is difficult to interpret, therefore it
is necessary to implement the fast Fourier transformation to obtain a function of the
frequency domain spectrum with the wavelength or the wave number. In the IC
manufacturing process, the properties of the film grown on the wafer can be quickly
characterized using an FTIR spectrometer. Common FTIR applications include
measurement of silicon epitaxial film thickness, detection of interstitial oxygen
and substitutional carbon content in semiconductor films, and testing of dopant
content in BPSG films, phosphosilicate glass (PSG) films, and silicon fluoride
glass (FSG) films, as well as the qualitative test analysis for characterizing the
type of chemical bonds and element contents (H, etc.) in various dielectric layers
(SiNx, SiO2, and other films).
At present, FTIR spectrometers used in the IC manufacturing field are mainly
produced by three manufacturers, namely Thermo Fisher Scientific, Perkin-Elmer,
and Bruker. FTIR spectrometers by Thermo Fisher Scientific are available in a
variety of models. Different configurations can be selected according to the user’s
requirements. The flexibility is high, and the configured analysis software demon-
strates a strong performance. After the wafer is loaded onto the test platform, the
wafer level test analysis can be performed. It is useful for the rapid film character-
ization analysis. Therefore, the equipment is widely adopted. Prices range from tens
of thousands to hundreds of thousands of dollars, depending on the configuration
and the applications of the equipment.

Film Stress Measurement Tool

With the development of IC manufacturing processes, the size of wafers is getting

larger and larger, the integration of devices is getting higher and higher, and the
number of thin film layers deposited on the surface of wafers is also increasing. Since
the structure and thermal expansion coefficient of each thin film layer are different,
the stress in the film causes the deformation of the substrate, resulting in the lower
yield of subsequent CMP and the failure of dies. In order to better control the wafer
deformation during the manufacturing process, it is necessary to monitor the stress of
each grown thin film layer, and thus the stress test equipment is widely applied in the
stress test for thin films in the manufacturing process.
If it is distinguished by the direction in which the substrate is deformed by the film
stress, it can be divided into compressive stress and tensile stress, as shown in
Fig. 70.20. When the film and the substrate are subjected to the compressive stress,
the film surface is convex, that is, the film has a tendency to expand outward under
70 Metrology and Inspection Equipment 1563

Fig. 70.20 Deformation and stress of the thin film

the compressive stress; if the compressive stress reaches a certain limit, the film is
curled toward the inside of the substrate, causing the film layer to bulge. When the
film and the substrate are subjected to the tensile stress, the film is forced to expand
outward, the substrate is compressed inward, and the film surface is concave; if the
tensile stress of the film layer exceeds a certain limit, the film may be cracked or even
the substrate shows an upward warpage.
The main sources of film stress are external stress, thermal stress, and internal
stress. Among them, the external stress is caused by an external force applied to the
film; the thermal stress is caused by the difference in thermal expansion coefficient
between the substrate and the film; and the internal stress is mainly caused by the
difference in characteristics between the film material and the substrate material. It
mainly depends on factors such as the microstructure of the film and deposition
defects.
The methods for testing the internal film stress are mainly mechanical methods,
interference methods, and diffraction methods. The first two methods are to obtain
the estimated value of the film stress by testing the curvature of the substrate
caused by the stress before and after the film deposition on the tested substrate, so
these two methods are collectively referred to as the curvature method. In the IC
manufacturing, the internal stress of the film is commonly measured by the
curvature method. The diffraction method is mainly applied to test the change in
lattice constants.

Curvature Method

It is assumed that the film stress is uniform, and the estimated stress value can be
calculated by testing the difference in the bending amount of the substrate before and
after the film deposition. There are three common curvature measurement methods,
namely the cantilever beam method, the Newton ring method, and the interferometer
phase displacement stress test method. The cantilever beam method is commonly
used in IC stress test instrument. The test principle of this cantilever beam method is
that the laser is irradiated at a point on the free end of the cantilever beam, and the
curvature is measured separately before and after the film deposition. The radius of
curvature of the substrate before and after the film deposition is obtained, and thus
the residual stress of the film can be calculated.
1564 F. Yang

Fig. 70.21 Principle of

X-ray diffraction method

X-Ray Diffraction Method

The basic principle of the X-ray diffraction method is that the residual stress in the
sample will lead to a peak position shift in the Bragg diffraction due to the
interplanar spacing stress which is either increased (tensile stress) or decreased
(compressive stress). The peak position of the X-ray diffraction peak is drifted by
the stress, and the magnitude of the peak position shift corresponds to the magnitude
of the stress.
X-rays with a wavelength of λ are applied to irradiate the sample surface at
different incident angles, and X-ray diffraction peaks are received at a certain
angle 2θ, which is the X-ray diffraction phenomenon, as shown in Fig. 70.21. The
wavelength λ of the X-ray, the distance d between the diffracted crystal planes, and
the diffraction angle 2θ follow the Bragg law, namely

2d sin θ ¼ nλ n ¼ 1,2,3, . . .

As the X-ray wavelength λ is known, there is a correspondence between the

measurable diffraction angle and the microscopic interplanar spacing d. When there
is stress in the material, the interplanar spacing d will vary with the relative
orientation of the crystal plane and the stress, so the stress value can be obtained.
At present, stress testers commonly adopted in IC manufacturing are mainly
provided by KLA-Tencor and FSM. Usually, KLA-Tencor’s stress test instrument
is integrated with an automated film thickness gauge. The price of FSM’s stress
testers is typically tens of thousands of dollars to hundreds of thousands of dollars.

Four-Point Probe

Resistivity is an important parameter for characterizing the conductive properties of

semiconductor materials. A low-resistance material with good conductivity has a
low resistivity; on the contrary, a material with poor conductivity (even an insulating
material) has a very high resistivity [3]. Usually, the resistivity is expressed by ρ, and
the most common unit is Ωcm. At room temperature, the resistivity of the
70 Metrology and Inspection Equipment 1565

semiconductor material is between the conductor and the insulator, typically 104 to
109 Ωcm.
When the resistivity of a semiconductor material is tested, a probe method such as
the direct current two-probe method is generally applied to obtain the material
resistivity by measuring the physical size and the resistance of the material. How-
ever, this method is sometimes interfered by the applied current, the contact resis-
tance between the tested material and the probe, and other factors, thus affecting the
test results. Therefore, the industry uses the four-point probe for the resistivity
measurement more frequently. This method is fast, simple, and widely adopted to
measure the bulk materials, thin film materials, as well as diffusion or ion implan-
tation doped layers in semiconductor processes [4].
Figure 70.22 shows the principle of the four-point probe for measuring the
resistivity of the sample. Four probes are arranged in a single-line form and directly
connected to the flat sample surface, and points 1 and 4 are connected to current
sources. A constant current is derived into the sample through the probes, the current
I through the sample is controlled by a separate ammeter, and the voltage U23 of the
whole sample is measured with a voltmeter (or a voltage is applied at both ends of
the sample with a voltage source and an ammeter is connected in series to measure
the current across the sample). Thus, the calculation formula for measuring the
resistivity by the Four Point Probe is

U 23
ρ¼C
I
where C is the probe coefficient of the four probes (in cm), namely

1
1 1 1 1
C ¼ 2π   þ
S1 S1 þ S2 S2 þ S3 S3

when S1 ¼ S2 ¼ S3 ¼ S, C ¼ 2πS.
According to the above formula, the magnitude of C depends on the arrangement
mode of the probes and the probe spacing, regardless of the sample itself. On an
infinitely large sample (i.e., the sample size is much larger than the probe spacing), if

Fig. 70.22 Schematic

diagram of the principle of
four-point probe for
measuring the resistivity of
the sample
1566 F. Yang

the four probes are arranged in a line form and the probe spacing is equal to S ¼
1 mm, then C ¼ 2πS ≈ 0.628 cm. It shall be noted that this formula is applicable on
the premise that the sample thickness (d) and the edge of the sample are more than
4S from any of the four probes. In the actual measurement, if the sample is of finite
thickness, a thickness correction factor

1 U
ρ¼  2πS 23
F1  F2 I
F1 needs to be introduced for correction [5].
If the distance from the probe to the sample edge is comparable to the distance
between the probes, then the position correction factor F2 is also introduced for edge
correction. In addition to measuring the resistivity, the four-point probe is often
applied to measure the sheet resistance of the conductive film and the semiconductor
film. Sheet resistance, also known as square resistance, is adopted to characterize the
resistivity of a semiconductor film sample or a thin doped layer. For thin film
samples, it is usually easier to measure the sheet resistance than the resistivity.
Generally, the relationship between the resistance and the resistivity of a uniformly
doped film is

ρ
Rs ¼
d
where Rs is the square resistance of the film, ρ is the resistivity, and d is the film
thickness.
In general, the four-point probe square resistance tester is an offline monitoring
instrument commonly adopted in the IC industrial production lines, which can be
applied to measure PVD/CVD metal film resistance, and the resistivity or the square
resistance of thin film epitaxial layer after the post-annealing of ion implantation,
also used for daily monitoring the stability of the relevant process equipment.
KLA-Tencor in the USA is currently one of the leading vendors of four-point
probe testers. The company’s Rs series of four-point probe testers are widely used in
IC production lines, with the highest market share. In addition, CDE, FSM, Four
Dimension, and other companies also provide the same type of test instruments, the
price of which varies from tens of thousands of dollars to hundreds of thousands of
dollars depending on the hardware function configuration and customer
requirements.

Surface Profiler

The surface profiler is an instrument to measure the surface morphology of speci-

mens, and the measurement principle is shown in Fig. 70.23. The surface profiler
consists of three modules: signal measurement, signal processing, and signal output.
When the probe gently slides along the specimen surface and encounters the
undulating surface morphology of specimen, the probe then moves up and down
70 Metrology and Inspection Equipment 1567

Fig. 70.23 Schematic diagram of the principle of surface profiler

with the undulation of the unevenness of the specimen surface, and this movement of
the probe can reflect the profile of the sample surface and reveal the entire measured
surface morphology.
According to the type of signal acquisition sensors, the surface profiler is divided
into photoelectric type, inductive type, and piezoelectric type. The main technical
indicators of the surface profiler are as follows:

1. Radius of probe stylus: The smaller the radius of stylus, the higher the test
accuracy. Currently, the radius of probe stylus of mainstream products is
0.7–2.0 μm.
2. Vertical scan range: Current vertical scan range of mainstream products is tens of
nanometers to 1 mm.
3. Probe force: The smaller the probe force, the smaller the damage effect on the
sample surface. At present, the probe force of mainstream products is generally
1–15 mgf.
4. Scan length: Tens of microns to tens of millimeters.
5. Field of view: A few millimeters.
6. Step height repeatability: Less than 0.5 nm.
7. Vertical resolution: Less than 0.5 nm.
8. Sample compatible for measurement: 300 mm wafers.

Compared with other test methods, the surface profiler has the advantages of large
test range, high precision, good stability, and repeatability of measurement results,
and can be used as an auxiliary means for other profile measurement technologies so
as to do the comparison for measurement results. However, the surface profiler also
has the following disadvantages.

1. The probe head has physical contact and interaction with the test specimen, which
causes the probe head to be deformed and worn out, so the measurement accuracy
may decrease after a period of usage.
2. The size of the probe head is limited in order to ensure its mechanical properties
such as wear resistance and rigidity. If the radius of curvature of the probe head is
larger than the radius of the micropits on the tested surface, the probe head cannot
1568 F. Yang

touch the bottom of the pits, which easily causes the measured data to be deviated
from the true value.
3. In order to improve the service lifetime of the probe head, the hardness of the
probe head material is generally very high, so this method is not suitable for the
measurement of precision parts and soft surfaces. Otherwise, it will cause surface
damage to the test sample.

The surface profiler can be used for measurements of etching depth, step height,
and surface profile, such as silicon steps or trench depths in MEMS technology
fields.
The main manufacturers of surface profilers are Bruker and AMBIOS
Technology.

References
1. N.T. Sullivan, S.P. Overlay, K.M. Monahan, Handbook of critical dimension metrology and
process control. SPIE CR52 (1994)
2. B. Bringoltz, T. Marciano, T. Yazic, et al., Accuracy in optical overlay metrology, in Proc. SPIE
9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97781H, (2016)
3. M.B. Heaney, Electrical conductivity and resistivity, in Electrical Measurement, Signal Pro-
cessing and Displays, ed. by J.G. Webster, (CRC Press, 2003)
4. D. Yang et al., Testing and Analysis of Semiconductor Materials (Science Publishing, Beijing,
ISBN: 9787030270368, 2010)
5. Y. Sun, Semiconductor Testing Technology (Metallurgic Industry Press, Beijing., ISBN: 7-5024-
2400-8, 1984)
Packaging and Assembly Equipment
71
Lezhi Ye and Qiangsheng Guo

Contents
Overview of Processes and Equipment for Assembly and Packaging . . . . . . . . . . . . . . . . . . . . . . . . 1570
Wafer Grinders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
Dicing Saws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
Laser Saw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578
Temporary Bonding/Debonding Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582
Wafer Bonders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1583
Wafer Bumping Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
Die Bonders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586
Wire Bonders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587
Flip-Chip Bonders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591
Flux Cleaning Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
Reflow Ovens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595
Molding Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
Electroplating and Wave Soldering Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
Cropping Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
Laser Marking Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1600
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601

Abstract
With the development of advanced packaging technology, More-than-Moore
device has pushed the IC packaging to a more important status. Electronic
packaging is the back-end process in the chip manufacturing, and the equipment
plays an important role in the yield of packaging. The market share of plug-in
packages such as dual in-line package (DIP) has gradually shrunk, while pack-
ages such as flip-chip, fan-out, wafer-level package (WLP), system in package
(SiP), and three-dimensional package (3D) are gradually becoming the

L. Ye (*)
Department of Material and Manufacture, Beijing University of Technology, Beijing, China
Q. Guo
CETC Beijing Electronic Equipment Co., Ltd., Beijing, China

© Publishing House of Electronics Industry 2024 1569

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_71
1570 L. Ye and Q. Guo

mainstream. Bumping, TSV, RDL, and other advanced processes are promoted,
new packaging equipment are constantly being proposed and upgraded. Many
front-end chip manufacturing equipment are used for the back-end packaging,
and there are many special equipment for new processes, such as temporary
bonding/unbonding machine and wafer bonding machine for ultrathin wafer
processing. This chapter introduces the structure, performance, and application
of traditional packaging equipment, and discusses the special equipment used in
advanced packaging.

Keywords
Package equipment · Die bonding · Wire bonding · Dicing saw · Wafer grinding ·
Flip-chip bonding · Wafer bonding · Molding

Overview of Processes and Equipment for Assembly

and Packaging

The manufacturing process of electronic products includes semiconductor device

fabrication and whole system assembly, which is bounded by wafer cutting into
chips, usually dividing the process into the front end and the back end, as shown in
Fig. 71.1. The back-end process includes the chip packaging process and the device
assembly process.
Packaging and assembly can be divided into four levels, namely chip-level
packaging (level 0 packaging), device-level packaging (level 1 packaging), board
card–level assembling (level 2 packaging), and whole system assembling (level
3 packaging) [1]. Level 0 and level 1 packaging are commonly known as the
electronic packaging, while level 2 and level 3 packaging are known as the electronic
assembly. Electronic packaging is applied to place, fix, seal, and protect the die while
enhancing its electricity and heat dispersion performance, as well as connecting the
internal I/O of the die to the pins of the package shell through leads or bumps. It can
also be applied to interconnect multiple dies efficiently and reliably.

Fig. 71.1 Physical implementation process for electronics

71 Packaging and Assembly Equipment 1571

Since the 1950s, electronic packaging has developed from transistor outline
(TO) packages, dual in-line packages (DIP), small outline packages (SOP), plastic
quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA)
packages, and multichip packages (MCP) to system in package (SiP) technology. As
the performance of integrated circuits (ICs) becomes increasingly advanced, techni-
cal specifications are rising, and the ratio of die size to package size is getting closer
to 1. At the same time, the probability of usability and temperature resistance of ICs
are increasing, the number of pins is increasing, and the pin pitch and mass are being
reduced, while reliability and ease of use are improving [2]. Level 2 packaging
connects these pins to other devices through the wires on the PCB. This process
mainly involves through-hole technology (THT) and surface mount technology
(SMT). Due to the outstanding advantages of SMT, it has become the mainstream
technology in the field of electronic production. The development of advanced
electronic packaging emphasizes system design. The various packaging stages
have progressed from independent and decentralized processes to centralized and
unified processes, and from the simple manufacturing to the design-oriented devel-
opment, which means that level 3 packaging is gradually becoming more integrated.
The chip manufacturing and packaging technology of ICs and their performance
levels are closely linked to the capabilities of related equipment. Advanced chips and
packages can only be achieved by the advanced equipment [3]. In the chip produc-
tion and packaging lines, the four elements of equipment, process, materials, and
environment form a relationship of interdependence, mutual advancement, and
common development. In the development of chips and packages, equipment must
be considered firstly. Electronic packaging process equipment refers to equipment
specifically applied in the research, development, and packaging of various elec-
tronic products for substrate preparation, component packaging, board-level assem-
bly, whole system assembly, process and environmental assurance, production
process monitoring, and product quality assurance. The following three aspects
reveal major types of electronic packaging equipment with the widest application
base and scale. These equipment are the most closely integrated with processes and
have the greatest impact on the packaging performance.

1. In the level 0 packaging stage, wafer testing, thinning, and dicing processes are
performed. The major types of packaging equipment corresponding to these
processes are wafer probe stations, wafer thinning grinders, grinding wheel dicing
machines, and laser dicing machines.
2. In the level 1 packaging stage, dies are interconnected and packaged. The main
types of packaging equipment corresponding to these processes are die bonders,
wire bonders, die flip bonders, molding machines, cropping machines, lead
plating machines, and laser markers. The wafer-level chip size packaging
(WLCSP) process must also be completed in this stage, in which the main
types of packaging equipment include ball mounters, wafer bumping equipment,
metal deposition equipment, and lithography equipment.
3. In the level 2 packaging stage, the PCB assembly process is completed. The main
packaging equipment used in this process includes soldering paste coating
1572 L. Ye and Q. Guo

equipment, screen process presses, dispensers, mounting machines, reflow ovens,

crest welders, cleaners, and automatic optical inspection equipment. The sub-
strate for the circuit assembly is also provided in this stage. The corresponding
main substrate process equipment includes vacuum laminators, drillers, through-
hole plating systems, coating machines, steppers, developing machines, etching
machines, screen printers, electro-coppering systems, automatic optical inspec-
tion equipment, and labeling and marking machines.

With the development of technology, the market share of plug-in mounting

packages (such as DIP) has gradually declined, while flip-chip packages, fan-out
packages, wafer-level packages, system in package (SiP), 3D packages, and other
advanced packaging technologies are becoming the main trends. At the same time,
advanced packaging equipment, such as temporary bonders/debonders for ultrathin
wafer processing and wafer bonders, is constantly emerging and being upgraded [4].

Wafer Grinders

The wafer grinder (as the wafer thinning machine) is a grinding equipment with a
diamond grinding wheel mounted on an aerostatic bearing spindle, which is applied
to reduce the thickness of silicon wafers, sapphire substrates, ceramic substrates, and
other processed objects. This equipment feeds its high-speed-rotation wheel at a very
low speed to grind the wafer which holded on the vacuum chuck table so as to make
the wafer thinner. There are two types of wafer grinding machines to meet different
processing requirements, namely the wafer grinding machine (as wafer grinder) and
the wafer grinding and polishing machine (as wafer grinding polisher).
The wafer grinder is mainly composed of a rough grinding system, fine grinding
system, chuck table, chuck table washing system, wafer transfer manipulators,
central manipulator, loading and unloading cassettes, positioning table, wafer
cleaning table, and turntable, as shown in Fig. 71.2. The rough/fine grinding system
is equipped with an aerostatic bearing spindle, which is driven directly by a built-in
high-frequency motor to rotate the diamond grinding wheel at high speed. The chuck
table rotates, and the vacuum suction is adopted to hold wafers on the chuck table.
The chuck table washing system is mainly applied to remove debris from the chuck
table so as to keep it remain clean. The wafer transfer manipulators are mainly
applied to load and unload the wafers from the chuck table, the positioning table, and
the wafer cleaning table. The central manipulator is applied to transfer the wafers
among the wafer cleaning table, cassettes, and positioning table. The cassettes are
mainly applied to load and unload the wafers. The positioning table is applied to
identify the position of wafers and locate them. The wafer cleaning table is mainly
used for cleaning and drying wafers after the grinding so as to remove residual water
and dusts that may affect their transfer. The turntable is mainly applied to transfer
wafers among the station of the rough grinding system, the fine grinding system, and
the loading position through the turntable rotation.
71 Packaging and Assembly Equipment 1573

Fig. 71.2 Typical structure of a wafer grinder

Wafer grinding polisher can automate the entire procedure, from loading, posi-
tioning, packaging, rough grinding, fine grinding, polishing, cleaning/drying, and
protection tape processing to unloading. It is a dry-in and dry-out process. This
operation flow is shown in Fig. 71.3. The whole operation flow of the wafer grinding
polisher is divided into the following nine steps.

1. The central manipulator removes the wafer out from the cassette and places it on
the positioning table.
2. With the wafer in the center of the positioning table, the manipulator moves
evenly to transfer the wafer to the chuck table.
3. Using the turntable to switch the wafer between stations, the wafer is moved from
the loading position A to the rough grinding position D for rough grinding.
4. After the rough grinding step, the wafer is moved to the fine grinding position C
for fine grinding.
5. After the fine grinding step, the fine grinded wafer is moved to the polishing
position B to implement the polishing process.
1574 L. Ye and Q. Guo

Fig. 71.3 Operation flow of

wafer grinder/polisher

6. After the polishing step, the polished wafer is transferred to the unloading
position A.
7. The wafer transfer manipulator moves the polished wafers from the unloading
position A to the wafer cleaning table to clean wafer.
8. The central transfer manipulator then moves the cleaned wafer to the tape
processing system.
9. The tape processing system completes the processes of mounting the dicing tape
and removing the grinding protection tape, thereafter transfers the framed wafer
to the cassette.

A wafer grinding polisher can carry out the loading/unloading, rough grinding,
fine grinding, and polishing processes on the same chuck table. The typical
structural layout is shown in Fig. 71.4. In this type of equipment, a large disk-
shaped turntable equipped with four vacuum chuck tables that can rotate 360

clockwise enables wafers to be sequentially transferred to rough grinding, fine
grinding, polishing, and loading positions on the same chuck tables, thereby
completing the entire grinding and polishing process conveniently. After wafer
grinding and polishing, the wafer is moved to the de-taping and mounting system
by the central manipulator, wherein the grinding protection tape is removed and
the dicing tape is mounted on the wafer for the next wafer dicing process. The
flattening and tensioning abilities of the dicing tape adhered to the frame can
provide support for the thin wafer, thereby providing a perfect solution for the
71 Packaging and Assembly Equipment 1575

Fig. 71.4 Typical structural layout of an integrated grinding and polishing system

transfer of large-diameter wafers with a thickness less than 100 μm and elimi-
nating the risk of wafer breakage during the wafer transfer.
At present, major foreign manufacturers of wafer grinders include Disco and
ACCRETECH of Japan, CETC Beijing Electronic Equipment Co., Ltd. of China. In
addition to their applications in the IC industry, wafer grinders are also widely used
in LEDs, infrared devices, fingerprint recognition devices, optical communications,
and other industries.

Dicing Saws

A dicing saw is a type of equipment that uses a diamond grinding wheel mounted on
an aerostatic spindle to cut or groove wafers, glass, ceramics, and other processed
objects. Figure 71.5 shows a schematic of a wafer before and after the dicing step.
Dicing saws can be classified as semiautomatic dicing saws or fully automatic dicing
saws depending on the automation degree of the equipment.
In the operation of a semiautomatic dicing saw, the loading and unloading of the
processed objects are completed manually, and only the cutting process is performed
in automation. A semiautomatic dicing saw is mainly composed of an aerostatic
spindle, an x-axis guide, a y-axis guide, a z-axis guide, and a θ-axis guide, as shown
in Fig. 71.6. The aerostatic spindle is supported by an aerostatic bearing, and the
1576 L. Ye and Q. Guo

Fig. 71.5 Schematic of the wafer before and after the dicing step

Fig. 71.6 Typical structure of a semiautomatic dicing saw

spindle is directly driven by a built-in high-frequency motor to drive the diamond

grinding wheel at a high speed. The x-axis is generally supported and guided by a
linear guide rail, and the large guide range ball screw, driven by the servo motor to
achieve linear movement, drives the back-and-forth movement of the processed
object on the wafer chuck. The y-axis is generally supported and guided by a linear
guide rail, and a servo motor or stepping motor drives a high-precision ball screw to
achieve precise indexing. If necessary, a linear grating ruler is used for the closed-
loop control to drive the back-and-forth movement of the aerostatic spindle and the
microscope. The z-axis is guided by a linear guide rail, with a high-precision ball
screw driven by a stepping motor to achieve precise height control for raising and
lowering the aerostatic spindle. The θ-axis is generally driven by a direct drive motor
or a stepping motor, which drives the wafer chuck to rotate clockwise and
71 Packaging and Assembly Equipment 1577

counterclockwise around its central axis, so that the cutting path of the processed
objects on the wafer chuck is parallel to the movement direction of the x-axis.
A fully automatic dicing saw enables the automation of the entire procedure, from
loading, position calibration, cutting, and cleaning/drying to unloading. The tech-
nological process for this type of equipment is shown in Fig. 71.7, and the typical
structural layout is shown in Fig. 71.8.
A dicing saw is equipped with one or two sets of aerostatic spindles, and its
operation mechanism is to implement the heavy grinding on wafer surface. When
separating a processed object such as a wafer into smaller chips, the diamond
grinding wheel mounted on the aerostatic spindle cuts at a high speed of 30,000 r/
min or more along the scribing path of the processed object. At the same time, the
wafer chuck to which the processed object is clamped moves at a certain speed in a
reciprocating linear motion along the tangential direction of the contact point
between the diamond grinding wheel and the processed object. The debris generated
during the cutting process is washed away by deionized water. Numerous factors
have a significant influence on the cutting quality of the processed object, including

Fig. 71.7 Technological process of a fully automatic dicing saw

Fig. 71.8 Typical structural layout of a fully automatic dicing saw

1578 L. Ye and Q. Guo

Fig. 71.9 Two-pass dicing processes

the speed and the output power of the aerostatic spindle; the carborundum grain size
of the diamond grinding wheel and the type, thickness, and radius of the bonding
agent; the temperature and flow rate of the coolant; the type of film mounted on the
processed object; and the speed of the x-axis. The inherent brittleness of the material
from which processed objects such as wafers are made and the cutting method of the
grinding wheel inevitably cause front and back mechanical stress on the processed
objects, resulting in quality defects such as front cracking and back cracking at the
edges of the separated units.
With the development of semiconductor technology, more new materials and new
processes are being applied in the wafer manufacturing, which poses great chal-
lenges for the abrasive cutting process. Dicing saws need to adapt to the application
requirements of different materials applied in processed objects. Controlling quality
defects is a critical and difficult aspect of the cutting process. In order to improve
production efficiency and cutting quality, two-pass dicing processes (shown in
Fig. 71.9) have been increasingly adopted. There are various types of two-pass
dicing processes. The method of parallel two-pass dicing uses two sets of aerostatic
spindles to simultaneously create two cutting lines, while the step two-pass dicing
method first uses the blade on the z1 spindle for slotting, and then uses the thinner
blade on the z2 axis for full cutting. The third method is the bevel two-pass dicing
method, which first uses a V-shaped blade on the z1 spindle to gride a groove, and
then uses the blade on the z2 axis for the full cutting.
At present, major manufacturers of dicing saws include Disco and ACCRETECH
of Japan, CETC Beijing Electronic Equipment Co., Ltd. of China. In addition to their
application in the IC industry, dicing saws are also widely used in LED, solar cell,
thermistor, flat panel display, optical communications, and other industries.

Laser Saw

A laser saw is a type of equipment that uses a high-energy laser beam on the surface
or inside of a processed object such as a wafer to create a cut or groove by means of
solid sublimation or evaporation. Based on the type of laser technology utilized,
71 Packaging and Assembly Equipment 1579

laser saws can be classified as dry laser saws or water jet–guided laser saws.
Depending on the degree to which the equipment is automated, laser saws can also
be classified as semiautomatic or fully automatic laser saws.
A dry laser saw is mainly composed of a laser system, an x-y worktable, a
θ-direction rotary table, a z-direction focusing system, and systems for dust removal,
vacuum, and electronic control, as shown in Fig. 71.10. The laser system parameters
are determined based on the laser absorption properties of the materials from which
the processed objects are made. The x-y worktable performs the fast linear recipro-
cating motion and the precise stepping motion, while the θ-direction rotary table is
used for precise alignment of the cutting path of the processed objects, and the
z-direction focusing system is used for fine adjustment of the laser processing focus
and the CCD imaging focus.
Laser processing methods used by dry laser saws are mainly divided into ablation
processing and stealth dicing. Ablation processing refers to a grooving process or a
full-cutting process in which laser energy is concentrated on a small area on the
surface of a processed object such as a wafer in a very short period of time to melt
and vaporize the solids in the cutting path. In the laser grooving process, a groove
with a depth of about one-fourth to one-third of the total thickness of the processed
object is cut on the surface of the object, as shown in Fig. 71.11, and then the
processed object is split along the groove to separate it into dies, as shown in
Fig. 71.12. The laser full-cutting process directly cuts through the entire material
thickness of the processed object and separates it into dies, as shown in Fig. 71.13;
due to the effects of heat, the dies do not automatically separate, so they need to be
separated from each other by the wafer expansion process.
Stealth dicing refers to a processing method in which laser energy is concentrated
inside a processed object such as a wafer. The laser is controlled by means of a
special wavelength so as to only disrupt the atomic bonds of silicon. A metamorphic

Fig. 71.10 Typical structure of a dry laser saw

1580 L. Ye and Q. Guo

Fig. 71.11 Laser grooving

Fig. 71.12 Splitting

Fig. 71.13 Laser full cutting

layer is formed inside the wafer, and the processed objects are separated into dies
using expansion film, as shown in Fig. 71.14 [5].
A water jet–guided laser saw is mainly composed of a laser head, a CCD, a
coupling device, an x-y worktable, a z-direction adjustment system, and a water
circulation system, as shown in Fig. 71.15. The basic principle of water jet–guided
laser cutting is to introduce a laser beam directly above a processed object such as an
ultrathin wafer or MEMS die so that the beam passes through the window of the
focus lens and the water chamber and then focuses on the center of a nozzle. High-
pressure purified water enters from the left side of the water chamber and is ejected
71 Packaging and Assembly Equipment 1581

Fig. 71.14 Stealth dicing

Fig. 71.15 Schematic of the typical structure of a water jet–guided laser saw

through the micropores of the nozzle, producing a water jet with a diameter of
30–100 μm which is coupled with the laser beam. Using the principle of total
reflection at the interface between the water jet and the air, the laser travels along
the water jet to the surface of the material, where it ablates and cuts the wafer only
within the diameter of the water jet, as shown in Fig. 71.16. Typically, the effective
working distance is 1000 times the nozzle diameter.
Dry laser ablation processing is suitable for grooving or full cutting, with
advantages such as a narrow cutting groove, zero contact, and high-speed operation.
However, this processing method has problems related to factors such as material
re-coagulation, heat-affected zones, cracking, and grain strength. Dry laser stealth
dicing can suppress the generation of processing debris, basically causes no damage
to the front/back surface of processed objects, and does not require cleaning, which
makes it suitable for processed objects with poor anticontamination performance and
poor load resistance. Water jet–guided laser cutting has no heat affected zones and
1582 L. Ye and Q. Guo

Fig. 71.16 Basic principle of

water jet–guided laser cutting

does not cause any burn damage to the processed object. In addition, the cutting path
is clean, without slag, burrs, mechanical stress, or contamination.
Currently, major laser saw manufacturers include Disco, JPSA, and Synova, 45th
Research Institute, HG Laser, and Shenzhen Han’s Laser of China. Laser saws are
mainly used to cut photoelectric and semiconductor materials such as silicon wafers,
sapphire wafers, low dielectric constant materials, MEMS, and thin film solar cells.

Temporary Bonding/Debonding Systems

Over the years, computers, communications, automotive electronics, the aerospace

industry, and other consumer products have put forth additional requirements for IC
packaging, such as smaller size, lighter, and thinner form, more functions, and lower
cost. In order to meet these requirements, wafers must be thinned to less than 100 μm
and vertically interconnected by means of through-silicon vias (TSV) to create high-
density 3D multistack packages, thereby taking surpassing Moore’s law using a
different approach [6]. As these thinned wafers are noted for their flexibility,
fragility, and warpage, it is necessary to use intermediate materials to bond them to
thicker carriers. After the back thinning, TSV opening, relaying, and interconnection
processes are completed, external energy (light, electricity, heat, and external force)
is input to disable the adhesive layer and separate the wafers from the carriers. This
process is known as the temporary bonding/debonding process [7]. In short, tempo-
rary bonding/debonding refers to the process of temporarily bonding a wafer to a
rigid carrier (glass or wafer) substrate to carry out thinning and the desired series of
processes.
The main bonding and debonding solutions for temporary bonders are chemical
decomposition, UV debonding, slide-off, thermal decomposition, and ZoneBOND.
The bonding glue which fixes the thin wafer is the key to the temporary bonding
process [7].
71 Packaging and Assembly Equipment 1583

EVG has developed the EVG805 temporary bonding/debonding system, which

includes the thermal slide-off by light exposure, lift-off, edge zone debonding
(EZD), and UV bonding techniques. EVG805 can temporarily bond wafers with
diameters ranging from 200–300 mm. The maximum debonding temperature is
200–300
C. This company has also worked with Brewer Science to develop the
WaferBOND HT wafer bonding adhesive, which is a new high-temperature sprayed
adhesive that can be applied by the spin coating. Mainly used for temporary bonding,
it can be applied to process wafers under high-temperature conditions and the
adhesion can last for a relatively long time [8].
Recently, Japan’s Tsukuba Seiko Co., Ltd. has developed an innovative
E-supporter device for ultrathin wafer bonding and debonding at room temperature.
This temporary bonding/debonding technology is based on the E-Chunk technology.
Ultrathin product wafers with the thickness less than 100 um or warpage wafers can
be easily bonded on the E-supporter by the electrostatic force for the subsequent ion
implantation, metallization, device testing, laser cutting, etc. By using the physical
bonding and debonding technology instead of the conventional tape bonding
methods can reduce the process steps in the packaging and testing as well as avoid
the risk of wafer breaking. So far, several 200 mm and 300 m IC production lines
have adopted this new temporary bonding/debonding technology.
The SUSS XBS200 temporary bonding system supports all key steps in the
temporary bonding process, including release layer formation, bonding, low force
wafer bonding, UV curing, and cooling.

Wafer Bonders

Wafer bonding is a process of permanently bonding a silicon wafer to another silicon

wafer, glass, or wafers of other materials by means of a chemical or physical reaction
[9]. The bonding process takes place under the action of external energy. The
interface atoms of the two wafers react with each other to form covalent bonds,
thereby bonding the wafers and achieving a certain interface bonding strength [10].
Wafer bonding is a key step in MEMS processing [11]. As the materials involved
in the bonding technology become more diverse (such as glass, silicon, and III-V
materials) and process temperatures continue to decrease, the application of this
technology is becoming increasingly extensive [12]. It is also used in industries such
as safety airbag accelerometers, microfluidic devices, WLP, the substrate fabrication
of SOI (Silicon on Insulator) structure, and the thin film transfer of optoelectronic
communication components [13].
Combined with other processes, this technology can also be applied to support
and protect microstructures, achieve connections between mechanical structures or
between mechanical structures and circuits, and construct electrodes and cavities in
MEMS processes.
Wafer bonding processes can be divided into the following four types [12].
1584 L. Ye and Q. Guo

1. Anodic bonding: Bonding between silicon and glass, glass and metal, alloys and
semiconductors, and glass and semiconductors at relatively low temperatures
(200–500
C). The advantage of this type is that an intermediate layer is not
required, the airtightness and long-term reliability of the bonded structures are
good, and the process conditions are simple (it can take place in a vacuum or in a
rare gas or atmospheric environment). In addition, there is little residual stress and
bonding strength is high. It is widely used in MEMS manufacturing.
2. Adhesive bonding: Bonding with a nonmetallic material (such as glass paste or
photoresist) as an intermediate layer. The intermediate layer material is only
applied on the substrate surface, and then the two wafers are bonded together
using a bonder. Adhesive bonding has a wider range of applications and basically
can be used in all areas, including hermetic sealing and interconnections. The
advantage of this method is that the use of intermediate layer material can avoid
defects caused by the irregular surfaces, so this bonding method is not sensitive to
surface roughness. The disadvantage is that the bonding surface only has mod-
erate electrical properties and the transition layer is much thicker than that of
other bonding technologies.
3. Fusion bonding: Two smoothed silicon wafers by a specific surface treatment are
bonded at a specific temperature and pressure, and finally annealed at a temper-
ature of 800–1000
C. This process creates a homogenous bonding and does not
cause problems such as thermal stress due to mismatched thermal expansion
coefficients.
4. Low-temperature wafer bonding: This type of bonding process mainly
includes two methods, namely plasma activation and argon sputtering oxida-
tion. The mechanism of plasma activation is that ions of plasma impact the
silicon surface to energize unstable nonbridged oxygen atoms and make them
leave the bonded silicon atoms so as to form many dangling bonds on the
silicon surface, in which these silicon dangling bonds will enhance the adhe-
sion capability between wafers. The plasma treatment can also destroy and
remove the hydrocarbons from the surface of silicon wafer while increasing
the amount of surface OH bonds, thereby achieving the objective of surface
activation. Usually, low-pressure plasma technology is based on the high-
energy excitation of electrons and ions at a pressure of 10–4 Pa. This method
can be applied for the low temperature bonding between wafers of a variety of
materials, such as between silicon and silicon, silicon and glass, glass and
glass, silicon and germanium, as well as silicon and III-V compounds, and it is
compatible with IC processes. However, its disadvantage is the high cost of
equipment and process.

The major manufacturers of wafer bonders are SUSS of Germany, EVG of

Austria, Suzhou MEMSTools, and SMEE of China. The EVG560 automatic
wafer bonding system [12], which can integrate more than four bonding cham-
bers, can carry out the entire bonding process, including anodic bonding, adhe-
sive bonding, and low-temperature plasma bonding. This system can also bond
300 mm wafers.
71 Packaging and Assembly Equipment 1585

Wafer Bumping Equipment

The wafer bumping process refers to the process of fabricating chip bumps. The
wafer bumping technology used in this process is a key technology in flip-chip
packages and BGA/WLCSP advanced packaging processes. Bumps are links
between the chip and external circuits; in other words, they are I/O channels [14].
There are many types of chip bumps; commonly used types are gold bumps and
solder bumps [15]. During flip-chip packaging, gold bumps are often fabricated by a
thermosonic process. In this process, bump design can be performed based on
soldering requirements and the fabrication can be realized flexibly according to the
design model which allocates the number, density, and how small the spacing of
bumps. This not only ensures the electrical and mechanical properties of the device,
but also reduces material use and workload [16].
The operation principle of wafer bumping equipment is different in which it
depends on the type of bumps that are fabricated. Most wafer bumping equipment
uses a thermosonic process to fabricate gold bumps. The main components of wafer
bumping equipment include an ultrasonic power supply, transducer, wire feeding
unit, wedge, and temperature-controllable fixture. In the wafer bumping process, a
substrate is fixed on a heating stage and the wedge is moved to the top of the bump.
When bonding, gold wire is passed through the hollow body of the wedge to reach
the tip and a tail wire of a controllable length flows out. The electronic flame-off
(EFO) system generates a high voltage to discharge the tail wire, which is instantly
melted by the high temperature generated by the spark. Due to the effect of surface
tension, the end of the melted tail wire rapidly solidifies to form a gold ball, which is
then soldered on the substrate by means of thermosonic bonding. The wedge moves
horizontally to produce a transverse shear force which breaks the gold wire at the tail
of the bump, thereby completing the bumping step. In practice, the diameter of the
gold ball is generally controlled to be two to three times the diameter of the gold wire
[17]. The main configurable parameters of wafer bumping equipment for making
gold balls include bump height, wire tail length, ultrasonic power, ultrasonic time,
bump spacing, ignition height, and number of bumps.
In the process of solder bump fabrication, wafer bumping procedures mainly
include flux coating, solder ball placement, reflow soldering, and inspection. Among
them, the flux coating process involves applying flux to the substrate bonding pad,
which increases the liquidity of the solder balls to ensure the quality of the curing
process and enhances the adhesion of the bonding pad to ensure successful solder
ball placement [18].
At present, popular processes of solder bump fabrication in the industry include
the screen-printing method, pin transfer method, and dot dispensing method. The
diameter of each solder ball is 0.1–1 mm. The smaller the diameter of the ball, the
more difficult it is to place the balls. The wafer bumping equipment used for solder
bumping has three main parts for different processes (printing, loading, and inspec-
tion) and also has two auxiliary parts (loader and unloader). In the printing process,
the flux is uniformly and accurately printed on the electrode positions of the circuit
substrate, which significantly improves the placement rate of the balls and the
1586 L. Ye and Q. Guo

adhesion strength after reflowing. In the loading process, a vacuum tooling head is
adopted to suck the solder balls from the feeder and arrange them neatly without
deformation. The balls are then positioned accurately using the image processing
technology. The solder balls are placed on the substrate, and finally a CCD system is
applied to examine the substrate on which the balls have been placed. The main
technical parameters of this type of wafer bumping equipment include the maximum
ball placement area, the diameter of the solder balls, the number of balls that can be
placed at one time, the time required to complete ball placement, and the accuracy of
ball placement.
The WMB-2000, an automatic wafer bumping system produced by MICSON of
China, is capable of performing the WLCSP process with high-precision screen
printing and microspherical precision placing alignment. This equipment can be
applied to replace traditional electroplated wafer bumping processes and has the
advantages of mass production and a high placement rate. The BM-760S wafer
bumping system produced by Shanghai Athlete FA Corporation uses a HD image
processing system which can detect the presence, size, and position deviation of
solder balls, apply single-point flux, single-point ball replacement, and remove
defective solder balls, etc. Its corresponding substrate size for solder ball process
is 460 mm  260 mm, and it is capable of placing solder balls with diameters
ranging from 0.06–0.3 mm.

Die Bonders

Bonding is the process by which dies are mounted on the package substrate or shell,
and the process equipment used is a die bonder. The dies typically undergo testing on
a wafer fabrication line and defective dies are marked for identification during
subsequent packaging. The die packaging process begins with the separation of
the wafer into individual dies. When a single die is separated from the original wafer,
the die is then mounted on a lead frame or on a die carrier by a loading process. There
are many kinds of bonding materials that can be used in bonding, including
conductive epoxy resin and metal solder.
A die bonder is mainly composed of a bonding table, an adhesive dispensing
system, a bonding head, a vision system, a transfer system, a loading/unloading
module, and a base, as shown in Fig. 71.17. The bonding head performs the picking
and placing of the dies, which is the key step to completing the die bonding process.
The bonding head and the bonding table work together to accurately pick up the dies
from the blue film and then work with the material conveying system to accurately
place the dies on the package substrate where the adhesive is applied. Next, the
pressure is applied to the dies to form an adhesive layer with uniform thickness
between the dies and the package substrate. Vision system is required on the loading/
clamping mechanism of the carrier system and the transfer system to complete the
positioning of the dies and the package substrate, respectively. Then the precise
information about the die position is transmitted to the motion control module so that
it can adjust the control parameters in real time to complete the bonding. The transfer
71 Packaging and Assembly Equipment 1587

Fig. 71.17 Internal structure

of a die bonder

system is responsible for the automatic operation of the conveyor belt in the die
bonding process and mainly includes a loading mechanism, a feeding/clamping
mechanism, and an unloading mechanism. As the main mechanism of the die
bonder, the die transfer mechanism requires a compact and precise structure. Since
the wafers move with a raster scanning motion in the x-y plane, the main component
of the wafer/die feed system is an x-y workstage. When dies are being bonded, the
step of the wafer movement is the distance between two adjacent dies and the
movable range of the x-y workstage must be larger than the wafer diameter itself
so that each die on the wafer can be moved onto the ejector pin and lifted up by the
ejector pin to reach the vacuum pick-up tool [19]. The wafer diameter can be
150 mm, 200 mm, or 300 mm, with international mainstream models currently
using 300 mm wafers. The key technologies for die bonders are machine motion
control, chip picking and placing, and image recognition [20]. For the chip picking
and placing mechanism, high speed and high precision are required.
After years of development, die bonder technology has improved significantly
and 300 mm automatic equipment is already available. The main manufacturers
include ESEC, ASM, and Alphasem. Table 71.1 provides a performance comparison
of typical die bonders.

Wire Bonders

The wire bonding process is a soldering process that connects the bonding pads on
the chip and lead pins on the lead frame with conductive wires, which is the key step
to ensuring the final electrical, optical, thermal, and mechanical properties of ICs
[21]. The wire bonding process has become a dominant method for the wire
interconnection in device package due to its simple, flexible nature, low cost, as
well as the fact that it can be used in a variety of package types [22]. In order to form
the specialized wire of various curved shapes that meet the requirements of different
package types, wire bonding uses ceramic thin tubes to guide the complex high-
speed motion of metal wires in three-dimensional space in order to physically
connect the bonding pads of internal die, which has been bonded on the
 1588

Table 71.1 Performance comparison of typical die bonders

Positional Manufacturing Wafer Chip size/
Company Model accuracy efficiency UPH diameter/mm mm Packaging processes
ASM AD838 25.4 μm 17,000 200 0.150–10.16 BGA, CSPBGA, MLP, QFP, PDIP TQFP,
@3sigma stacked CSP
ESEC 2100sDplus 12 μm 13,000 300 0.25–20 BGA, CSP-BGA, SiP-BGA, FBGA
@3sigma
2008hSplus 25 μm 13,000 150–300 0.254–25.4 QFN, BGA, thinned chip, PBGA, WBL,
@3sigma stacked chip
L. Ye and Q. Guo
71 Packaging and Assembly Equipment 1589

die-attaching substrate or the packaging socket, to the external lead pins on the lead
frame. In the bonding process, mechanical, electrical, software, optical, and imaging
systems must be fully coordinated to automatically complete the positioning. The
electronic flame-off (EFO) system is then ignited to form gold balls. Spatially
complex arc discharge is performed by the x-y-z workstage and the precision
positioning driver. Automatic loading/unloading is performed by the material con-
veying system, finally the wire bonding is completed under the action of ultrasonic
energy, substrate heat, and bonding pressure.
In the semiconductor packaging production line, wire bonders are also called ball
welders, pressure welders, wire bonding machines, or wire binding machines. A wire
bonder is composed of an x-y workstage, a bonding head, a vision system, a material
conveying system, a loading/unloading module, and an equipment base, as shown in
Figs. 71.18 and 71.19. Among these parts, the x-y workstage creates the high-speed
precision motion within the bonding surface that is required to form the complex
wire of curved shapes in the wire bonding process, so it is a key component in the
bonding process. The bonding head moves perpendicular to the bonding surface

Fig. 71.18 Wire bonder

workstage

Fig. 71.19 Bonding head of

a wire bonder
1590 L. Ye and Q. Guo

during bonding and coordinates with the x-y workstage to perform the complex
three-dimensional motions required for wire bonding. It also includes an ultrasonic
transducer, a wire clamp, an electronic ignition rod, and other small mechanisms, so
the bonding head is another key component in the bonding process. The bonding
head is mainly composed of a swing arm, a spindle, an electric motor, and various
small mechanisms. The rear part of the swing arm is connected to the drive motor,
while the front part is fitted with an ultrasonic transducer and a wire clamp. The
middle part of the swing arm is rotated by a spindle which is set by a bearing or leaf
spring, so as to move the wedge tool, the ultrasonic transducer, and the up and down
of the wire clamp. The ultrasonic energy generated by the ultrasonic transducer is
transmitted to the bonding point through the wedge tool (a hollow ceramic tube
through which the gold wire passes) which attached to the top of the ultrasonic
transducer. This forms a new and clean metal interface between the wire and the
bonding pad, thereby welding them together. The wire clamp is closed or opened at
various stages of the wire bonding process to control the wire length and snap the
wire at the second bonding point. The electronic ignition rod is connected to the
negative electrode of the electronic ignition box, and the tip of the rod is made of
high-temperature and corrosion-resistant platinum metal. The electronic ignition rod
is attached to the x-y workstage near the tip of the wedge tool. One side of the wire
clamp is electrically conductive and is connected to the negative electrode of the
electronic ignition box. When the wire clamp is closed, the gold wire is connected to
the positive electrode of the electronic ignition box. The vision system consists of an
optical path, a lighting device, and a camera. A pattern recognition algorithm
processes the image captured by the camera to obtain the starting point and the
ending point of each wire, and undertakes the task of post-weld detection, as shown
in Fig. 71.20. The main process parameters of wire bonders include bonding

Fig. 71.20 Wire bonding arc control

71 Packaging and Assembly Equipment 1591

Table 71.2 Technical performance parameters of representative wire bonders

Bonding
accuracy Bonding Bonding Bonding wire
Company Model (3σ)/μm speed/(ms/wire) spacing/μm diameter/μm
ASM Eagle60Ap 2.5 60 35 15 ~ 76
TwinEagle 3.0 60  two heads 35 20 ~ 75
ESEC WB-3200 2.5 40 30 20
K&S Maxμmultra 2.5 60 35 25.4
Maxμmelite 2.5 60 60 25.4
SHINKAWA UTC-2000 2.5 60 35 20

temperature, bonding time, ultrasonic power, bonding pressure, and curvature con-
trol of wire [23].
At present, the most common fully automatic wire bonders are the Maxμm
produced by K&S and the WB-3200 series produced by ESEC, followed by
products made by other companies such as ASM, SINKAWA, and KAIJO, which
together occupy a considerable share of the market. Table 71.2 lists the technical
performance parameters of representative global wire bonders.

Flip-Chip Bonders

As an advanced chip interconnection technology, the flip-chip packaging has

become the main trend in high-density packaging and chip interconnection. The
top surface of a flip-chip faces down and the bumps on the chip are directly
connected to the bonding pads on the die-attaching substrate. The interconnec-
tion lines are very short and the I/O leading-out terminals are distributed over the
entire chip surface. Flip-chips demonstrate high density, small size, and high
performance. Flip-chip can meet the requirements of electronic products such as
smartphones. Flip-chip technology also enables chip stacking and three-
dimensional packaging processes. The advantages of flip-chip bonding include
solid solder joints, short signal transmission paths, high I/O density, high reli-
ability, and small package size. However, the disadvantage is the high cost. Flip-
chip interconnection technology has three types of bonding processes: the ther-
mal ultrasonic process, which is used with gold bumps; the mass reflow process,
which is used with solder bumps; and the thermal compression process, which is
used with copper pillar bumps [24].

1. Thermosonic process: Similar to wire bonding technology, thermosonic flip-chip

bonding technology uses ultrasonic wire bonding to place gold bumps on the
bonding pads of chip and then mounts the chip upside down on the bonding pads
of die-attaching substrate. The flip-chip is bonded to the bonding pads of
die-attaching substrate under the combined effect of temperature and ultrasonic
bonding force. Because this process uses matured wire bonding technology, the
1592 L. Ye and Q. Guo

Fig. 71.21 Bumps on C4 process flip-chips

bump fabrication process is simple and compatible with most traditional package
equipment and technologies, so it is suitable for chips with low I/O density, such
as LED packages, smart card packages, and SAW filter devices in the communi-
cation field.
2. Reflow soldering process: The most popular process for flip-chip bonding in ICs
is reflow soldering, also known as the C4 (controlled collapse chip connection)
process, as shown in Fig. 71.21. It was created by IBM in the early stages when
IBM developed the technology for bonding chips to ceramic substrates. In the
reflow soldering process, solder bumps are first fabricated on the chips. Next, the
flip-chip is flux-dipped and is attached to the bonding pads on the die-attaching
substrate, and then welding is performed by the reflow oven. This process is
shown in Fig. 71.22.
3. Thermal compression process: The thermal compression bonding process is
generally used for flip-chips with copper pillar bumps, which have higher I/O
density. The bonding pads of die-attaching substrate are coated with aniso-
tropic conductive adhesive, and the chip bumps are bonded to the bonding
pads of the die-attaching substrate by heat and pressure. Compared to tradi-
tional round solder bumps, shown in Fig. 71.23, copper pillar bumps with flat
sidewalls and high aspect ratios as well as smaller microcopper pillar size are
therefore better for chips with fine pitch, large size, and many I/Os (800 or
more). However, the current hot-pressing process is costly and its placement
process requires higher precision. At present, the minimum pitch of mass-
produced copper pillar bumps is 40 μm. The biggest obstacle to the adoption
of thermal compression flip-chip bonding technology is the precision of the
chip bonding equipment. Fine-pitch copper pillar bumps require the placement
precision of the equipment to be within 3 μm. Figure 71.23 shows a solder
bump and a copper pillar bump.
71 Packaging and Assembly Equipment 1593

Fig. 71.22 Technological process of reflow soldering for flip-chips

Fig. 71.23 A solder bump and a copper pillar bump

Typical reflow soldering flip-chip bonding equipment manufacturers include

ASM, Datacon, ESEC, and CETC Beijing. The flip-chip bonders developed by
CETC Beijing can meet the requirements of many flip-chip processes such as
chip-to-wafer, chip-to-substrate, chip-to-lead frame, and chip-to-panel bonding.
They are also compatible with the thermal compression bonding process and good
stability. Table 71.3 lists the technical parameters of typical flip-chip bonders.

Flux Cleaning Equipment

Flux cleaning equipment is mainly used for removing the flux used for the reflow
soldering process of wafer bumps and the flip soldering process of devices with
special chip bumps in IC assembly and packaging processes. Flux cleaning
1594 L. Ye and Q. Guo

Table 71.3 Technical parameters of typical flip-chip bonders

Bonding Working
Company Model precision (3σ)/μm Chip size/mm2 Productivity/(pcs./h) area/mm2
ASM AD9212 10 0.25  0.25 to 4500 ~ 6000 200  200
17.8  17.8
CETC Octopus- 6 0.2  0.2 to 6000 350  350
1300 25  25
Besi Datacon 6 0.2  0.2 to 4000 180  200
8800 25  25
ESEC 10 0.25  0.25 to 5000 150
5003plus 50  50

equipment is suitable for standard 200 mm or 300 mm wafers, with varying device
specifications and dimensions. Flux cleaning equipment is mainly composed of
a frame, a centrifugal cleaning and drying unit, a manipulator arm lifting mechanism,
a preheating tank for solution used in soaking, a preheating tank for sprayed solution,
a deionized water rinsing (DIW) spray preheating tank, a hot nitrogen drying unit, an
electronic control system, a system of pipes and pipe fittings, and a liquid drainage/
exhaust system.
The operation principle of flux cleaning equipment and available cleaning
methods are as follows. (1) In soaking cleaning method, the cleaning solution is
preheated in the soaking solution preheating tank, and then is injected into the
process tank from the tank bottom by the pump to complete the soaking and
centrifugal cleaning process for workpieces. The waste solution is directly drained
into a special factory pipeline. (2) In spraying cleaning method, the cleaning solution
is preheated in the preheating tank, then the solution is sprayed onto workpieces by a
pump, wherein workpieces are loaded in a rotating carrier for cleaning, and the waste
solution is directly drained into the preheating tank for recycling. After the deionized
water is heated in the DIW spray preheating tank, it is injected into the tank to
implement the hot DIW spraying and centrifugal washing, meanwhile the waste
liquid is directly drained into a special factory pipeline. After that, the hot nitrogen
drying unit is used to implement the hot nitrogen drying step, in which a stainless
steel in-line heater is adopted and the adjustable temperature ranges from the
ambient temperature to 100
C.
Flux cleaning equipment features a rotating carrier that can be used for different
wafers and devices, as shown in Fig. 71.24. The components of this rotating carrier
include a spindle, a rotating disk, a wafer box holder, and a movable fixing rod. The
rotary motor is a servo motor with a speed range of 0–1200 r/min. The speed can be
adjusted by changing the settings. There is a manipulator arm that can be lifted up
and down, as well as a transparent door closure which consists of transparent
tempered glass and a sealing ring.
The electronic control system of the flux cleaner is mainly composed of a PLC, a
touch screen, a thermostat, and sensors. Its software performs functions for recording
warning information, history records, and maintenance information.
71 Packaging and Assembly Equipment 1595

Fig. 71.24 Rotating carrier structure

Reflow Ovens

Reflow ovens, also known as reflow soldering ovens, are primarily used in the reflow
soldering process of flip-chip solder bumps for level 0 packaging and the device
surface-mount technology (SMT) process for level 1 packaging.
In the flip-chip reflow soldering process, there are tin solder bumps on the flip-
chip. The chip is flux-dipped and pasted on the die-attaching substrate or the frame,
and then soldered by the heat reflow [24]. This process re-melts the paste-like soft
solder pre-distributed on the PCB bonding pads to achieve the mechanical and
electrical connection with the solder terminals or pins of the components and
devices [25].
Reflow soldering is a real-time control process involving many process parame-
ters, among which the configuration of the temperature profile is the most critical as
it determines the quality of reflow soldering. Temperature profiles that have not been
optimized can cause defects such as incomplete soldering, insufficient soldering,
warpage of components, and an excess of solder balls on the die-attaching substrate
or PCB. When reflow soldering is performed, first, the die-attaching substrate or
PCB enters the heating zone, and the temperature is steadily increased. After
entering the heating zone of 160–180
C, the solvent in the soldering paste is
evaporated away. The flux in the soldering paste starts to wet the bonding pad as
well as the solder joints and pins of the component. Thereafter, the soldering paste
softens, collapses, and covers the bonding pads, thereby isolating the soldered pads
and the pins of components from oxygen; meanwhile, it also preheats the surface
1596 L. Ye and Q. Guo

Fig. 71.25 Ideal temperature profile for the reflow soldering process

mounted component. The substrate or PCB then enters the reflow zone, in which the
temperature is raised rapidly at a rate of 2 to 3
C/s to melt the soldering paste. The
liquid solder undergoes wetting, diffusion, spreading, as well as reflow and mixing,
producing a metal compound at the soldering interface to form solder joints. Finally,
the substrate or PCB enters the cooling zone for the solidification of solder joints.
Figure 71.25 shows the ideal temperature profile for the reflow soldering process.
Reflow soldering ovens can be divided into different types depending on the
heating methods, such as hot plate conduction, hot air, infrared radiation, infrared hot
air, vapor phase, laser, etc. [26] The heat conduction method of reflow soldering
mainly include radiation and convection. The radiation conduction is mainly
achieved by an infrared oven, which has the advantages of high thermal efficiency,
a large temperature gradient, and the ease control over both the temperature profile
and the temperature on the upper and lower surfaces of the PCB during the double-
side soldering. The disadvantage is that the temperature control is not sufficiently
uniform, which may cause problems such as poor soldering and component damage.
Convection conduction is mainly performed by a hot-air oven, which has the
advantages of uniform temperature and good soldering quality, but it is not easy to
control the temperature difference between the upper and lower surfaces of the PCB,
as well as the temperature gradient along the longitudinal direction during the
soldering process. At present, the industry has tended to adopt the hot-air small
convection method. By setting a cooling assembly under the oven, the temperature
gradient of the hot oven in the vertical and longitudinal directions is maintained, thus
satisfying the requirements for specific temperature profiles.
The main reflow oven equipment manufacturers include SUNEAST, SMIC, and
Shenzhen JT Automation Equipment Co., Ltd. (“JT”). The JTE series, JTR series,
and KT series reflow ovens developed by JT shows advantages of stable and reliable
performance, strong temperature control capability, high-temperature control preci-
sion, high production efficiency, as well as effective reduction in energy
71 Packaging and Assembly Equipment 1597

Fig. 71.26 Exterior image of

the JTE-800 reflow oven

consumption and production cost. The exterior image of the JTE-800 reflow oven is
shown in Fig. 71.26.

Molding Machines

Molding machines are mainly used to perform automatic molding in the back-end
process of IC packaging. The molding sealing process mainly includes arranging
chips, preheating, mold pressing, and curing. At present, molding technology is
becoming increasingly automated. Automatic molding systems integrate the pro-
cedures for arranging chips, feeding, preheating, charging, mold pressing, mold
cleaning, glue removing glue, and material recovery, thereby greatly improving the
work efficiency and packaging quality.
For molding, the transfer molding process is the most common method of IC
packaging. Transfer molding refers to the process of fabricating a plastic encapsu-
lated component using pressurization, in which a hot viscous thermosetting material
in a feed compartment is delivered into a closed mold cavity through a channel and a
gate. Figure 71.27 shows the schematic diagram of the transfer molding press. The
operation process is shown in Fig. 71.28 [4].
Molding presses mainly use a PLC to control various valves in the hydraulic
system. The hydraulic module as the core component of the plastic molding press is
controlled through the action of these valves. The speed, flow rate, and pressure of
the mold assembly and injection are controlled by the electromagnetic proportion
valves. The operation process of a plastic molding press mainly includes two stages:
mold assembly and injection molding as follows:

1. Mold assembly: rapid rise of the movable table ! slow rise ! primary pressur-
ization ! secondary pressurization ! mold assembly and clamping ! depres-
surization of the movable table ! slow drop ! rapid drop ! slow speed
drop ! movable table stays in place ! depressurization of the lifting
table ! slow rise
2. Injection molding: rapid drop of the upper plunger lever ! primary slow drop !
secondary slow drop ! third slow drop ! depressurization ! slow rise ! rapid
rise ! slow rise
1598 L. Ye and Q. Guo

Fig. 71.27 Schematic diagram of a transfer molding press

Fig. 71.28 Operation process of a transfer molding press

Key components of the molding press include hydraulic systems, clamping

systems, molds, variable speed/variable pressure control systems, injection molding
heads, and PLC control systems. The key technical requirements of the hydraulic
system include mold assembly pressure, adjustable mold sinking/mold assembly
speed, adjustable injection molding pressure/injection speed, pressure retention, and
smooth speed when products are ejected. The main control process parameters
include mold assembly pressure, transfer pressure, compartment temperature, mold
temperature, and transfer time required to fill the mold cavity.

Electroplating and Wave Soldering Systems

The electroplating production line is applied to electroplate packaged IC lead frames

and connectors, or to do the surface treatment of metal parts. This process treats
packaged IC lead frames and pins with a protective coating layer to increase the
solderability of pins. The post-processing of the packaged frames and pins can be
accomplished by electroplating or wave soldering. The electroplating tank is in the
assembly line form. In this process, cleaning is performed first. Thereafter, the
cleaned lead frame is electroplated in electroplating tanks with solutions of different
concentrations, and then the electroplated lead frames are rinsed again, blow-dried,
and finally put into an oven for drying [4].
In the wave soldering process, cleaning is performed first, and then the cleaned
product is immersed in flux. After that, it is immersed in molten liquid tin alloy for
71 Packaging and Assembly Equipment 1599

wave soldering, and then the soldered product is washed again and dried. The
technological process is: deburring ! degreasing ! deoxidation ! immersion in
flux ! wave soldering ! cleaning ! drying.
Electroplating can cause the so-called “dog-bone” problem, in which there is a
thin area in the middle surrounded by thick areas. The main reason of this
problem is that it is easy to create a charge accumulation effect near edges of
lead frames and connectors during the electroplating. In addition, the electro-
plating solution is also vulnerable to ionic contamination. Furthermore, due to the
surface tension of the molten solder, the wave soldering tends to cause uneven
coating, in which the wave soldering part becomes thicker in the middle and
thinner at the edges.
At present, mainstream electroplating production lines utilize the high-speed
circular vertical lift electroplating method and are very different in structure from
an ordinary electroplating production line. The shifting and lifting of workpieces
in a single tank are no longer carried out; instead, the hangers and workpieces on
the entire production line move simultaneously. Usually, the process tank
arrangement of circular vertical electroplating production line is U-shaped with
multihangers. The number of the multiposition solution tanks is electroplating
process dependent. The mechanical units push the hangers move forward to the
fixed location and implement the go down/up steps to each plating tank. That is,
workpieces are continuously delivered to enter the tanks only through rising,
shifting, and descending steps. The operation speed of equipment is adjustable,
and the steady plating can be achieved with the cushioning device. In addition to
the manual loading/unloading of workpieces, the high-speed circular vertical lift
electroplating production line uses the automatic control to realize high working
efficiency and a wide range of applications, such as degreasing, pickling,
cleaning, electroplating, and rinsing.

Cropping Machine

Cropping machines are mainly used in the cutting, molding, and separating pro-
cesses of the lead frame after the packaging step. This equipment can realize the
automation of the entire production process by integrating automatic feeding, auto-
matic transfer, automatic forming, automatic detection, automatic tube loading, and
automatic material receiving. A cropping machine is mainly composed of five
subsystems: a feeding system, a molding system, a guiding system, a receiving
system, and a dust removal system [4].
Cutting is the process of separating the encapsulated chip from the entire lead
frame, while removing excess jointing materials and protruding resin. The cut
individually packaged chip has a sturdy resin shell with a number of external pins
extending from its sides. Molding is to press these external pins into the designed
shapes that facilitate PCB assembly. Cutting and molding are two different pro-
cedures, but due to the continuity of positioning and movement, they are usually
1600 L. Ye and Q. Guo

completed using the same equipment. They may also be completed separately.
After cutting and molding, the chips are placed in a plastic tube or tray for
transfer.
The main problem with the molding process is the deformation of the pins. For
DIP, because its pins are few in number and relatively thick, the problem is not
serious. However, for SMT picking and placing, due to the fine pitch frame and
large number of pins, it is easy to cause pin non-coplanarity during the pin
molding. One of the reasons for this problem is the human factor; as equipment
becomes increasingly automated, this factor has been greatly reduced. Another
reason is the heat shrinkage stress generated during the molding process [27]. Due
to the different thermal expansion coefficients of the molding sealing compound
and the frame material, there is a difference in the degree of shrinkage during the
cooling process after the molding, which resulting in the frame warping, thereby
leading to problems of non-coplanarity. As the frame pins become increasingly
thinner and packaged modules are also becoming thinner, the problem of packag-
ing modules becomes even more challenging. The way to overcome this issue is
through optimization of material selection, the length of the frame strip, and the
frame shape design.

Laser Marking Machines

Marking (also known as printing) refers to the “printing” of letters and logos on the
top surface of packaged IC modules, including the manufacturer’s information, place
of production, and chip code, for the main purpose of identification and tracking.
There are many ways to complete the marking procedure, the most common
methods are ink marking and laser marking. Ink marking has relatively higher
requirements for the module surface in which there is no contamination. Inks are
usually polymer compounds and needs to be thermally cured or cured using ultra-
violet light. With the development of technology, the ink marking has been gradually
replaced by the laser marking. At present, laser marker is the major marking
equipment adopted in IC production lines.
According to its different working methods, laser marking machines are divided
into fiber laser markers, CO2 laser markers, semiconductor side pump laser markers,
and semiconductor end pump laser markers. Laser marking refers to the use of a laser
beam to generate the desired patterns or texts by making chemical-physical changes
on the surface layer of substances and engraving marks, or by making the surface
material of the device evaporate to expose deeper materials, or by burning off some
substances through light energy [4].
The significant advantages of laser marking are noncontact processing, low
pollution, fast marking speed, clear writing, no wear, long-term use, convenient
operation, and strong anticounterfeiting function. At present, there are three main
methods of laser marking, namely, the masking marking method, linear scanning
marking method, and dot matrix marking method.
71 Packaging and Assembly Equipment 1601

The universal laser markers include lasers, laser cooling systems, optical systems,
automatic loading/unloading systems, high-speed precision guide rails, multi-
function vision inspection systems, precision positioning marking systems, and
tracking and offset compensation marking systems.

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1602 L. Ye and Q. Guo

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Main Common Parts
72
Zhaoyang Cheng, Dongshan Li, Changhua Mou, Jinwei Dong, and
Chunlei Li

Contents
Equipment Front-End Module (EFEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
Robotic Manipulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
Mass Flow Controller (MFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
RF Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
Local Scrubber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
Dry Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
Cryopump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
Turbo Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
Chiller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
Valves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
Gas Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
Electrostatic Chuck (E-Chuck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
Process Chamber Showerhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625
Reaction Chamber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628

Abstract
Common parts are an important basis for the development of the integrated circuit
manufacturing equipment industry. Most of them, such as manipulator, equip-
ment front-end module (EFEM), gas mass flow controller (MFC), gas panel,
reaction chamber, scrubber, chiller, RF source, vacuum pump, and ultraclean
stainless steel pipe (EP class), various pipe valves, quartz components, and silicon
carbide (SiC) components, not only occupy a large proportion of equipment cost
but also plays a very important supporting role in improving the performance
level of integrated circuit manufacturing equipment. In fact, the production and

Z. Cheng (*)
Beijing NAURA Microelectronics Equipment Co., Ltd (NAURA), Beijing, China
e-mail: chengzhaoyang@naura.com
D. Li · C. Mou · J. Dong · C. Li
Beijing NAURA Microelectronics Equipment Co., Ltd., Beijing, China

© Publishing House of Electronics Industry 2024 1603

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_72
1604 Z. Cheng et al.

R&D around these key common parts have formed a very large-scale supply
chain system and economic entity and have created many international
well-known enterprises. In this chapter, we give a detailed description that
focuses on a number of these important common parts.

Keywords
ESD · Aligner · VCR · PTFE · Bernoulli · (MFC) calibration · Exhaust · Leakage
rate · Vacuum · Quartz

Equipment Front-End Module (EFEM)

The equipment front-end module (EFEM) [1] is part of the overall structure of IC
equipment. It is used as a safe and clean mechanical transmission interface between
the production line and the equipment process module; it is mainly used for 200 mm
and 300 mm IC equipment meeting high cleanliness requirements. Usually, the front
end of the EFEM relies on the wafer cassette load port to interface with the
production line; the back end of EFEM is connected to the main function module
of the equipment. The manipulator inside the EFEM is mounted between the wafer
cassette on the EFEM interface and the back-end function module of the equipment,
to realize the wafer transfer, so as to ensure that the transfer process is always in a
clean environment. Among them, the high-efficiency air purifier provides a cleaner
positive pressure microenvironment inside the EFEM relative to the environment
outside the equipment to ensure the cleanliness of the wafer during the transfer in the
EFEM. The aligner is mainly used for the center positioning of the wafer and the
orientation of the wafer notch (the only marked notch on the outer edge of the wafer).
Some EFEMs are also equipped with function modules such as wafer temporary
storage buffer stations and ESD devices. Depending on the configuration, a single
EFEM [2] can cost from tens of thousands of dollars to hundreds of thousands of
dollars.
Brooks Automation and ASYST Technologies are the world’s leading EFEM
suppliers. At present, EFEM has basically adopted a digital network to achieve
stable and reliable inter-module communication and automation control and
achieved the best performance of EFEM while ensuring safety and reliability. In
the future, there are three technical directions for EFEM development: First, under
the premise of ensuring system stability and safety, the space required for EFEM
operation will be further reduced to improve the usage efficiency of ultraclean plants;
second, the speed and efficiency of wafer transfer will be improved to reduce the
production cost; third, the safety of the entire manufacturing process will be ensured,
because any errors in the handling of the wafer in any equipment mean huge
financial loss.
The common EFEM has three forms: two-port, three-port, and four-port. The
configuration of the internal functional structure varies with the equipment require-
ments. However, the internal clean microenvironment, the closed external interface,
72 Main Common Parts 1605

and the reliable transmission of the wafer are the most essential requirements. On
this basis, according to actual needs, it can be equipped with a wafer temporary
storage buffer station, an aligner, an ESD device, and the like. Figures 72.1 and 72.2
are the schematic diagrams and top views of the three-port EFEM structure.

Fig. 72.1 Structural diagram of the three-port EFEM structure

Fig. 72.2 Top view of the three-port EFEM

1606 Z. Cheng et al.

Robotic Manipulator

The robotic manipulator is one of the important components in IC equipment. Its

main application is used for cassette or front opening unified pod (FOUP) transmis-
sion and wafers transfer among different modules inside the equipment. Manipula-
tors are usually composed of controllers, drivers, arms, and end effectors. According
to the number of motion axes, it can be divided into single-axis or multi-axis
manipulators. In general, the more the number of axes, the better the ability to
implement complex functions.
Various manipulators are available as they are widely used in IC industry. There
are a number of well-known suppliers in this field such as Brooks Automation in the
United States; and Yaskawa Electric, Kawasaki Heavy Industries, JEL Corporation,
and Rorze Corporation in Japan. The main suppliers in Korea are Robostar, Robot
and Design (RND), and Kostek Systems. SIASUN Robot (Shenyang) in China has
entered this market recently.
The price of the manipulator varies greatly depending on its functions and
applications. The price of a wafer transfer manipulator is usually between $20,000
and $50,000. But the highest price of a FOUP transfer manipulator is likely to be
close to $100,000.
The types of manipulators used for IC manufacturing field are listed in Table 72.1.
The FOUP transfer manipulator is mainly used for FOUP dispatching and
handling in the transfer storage compartment of the integrated circuit production
line and the FOUP transfer inside the equipment. There are differences in the
structure and functions according to the different requirements of the system.
The wafer transfer manipulator is mainly used for the wafer transfer between
different modules in the equipment. According to the adaptability of the operation
environment, it can be divided into two categories: i.e., atmospheric manipulator and
vacuum manipulator. Because of the high requirement of cleanliness in IC
manufacturing, wafer transfer must be completed automatically by manipulator.
The wafer transfer system controls the manipulator to complete the wafer load and
unload to the designated position according to the preset procedure.

Table 72.1 Types of manipulators in IC manufacturing

Manipulator
No. type Main application Main type
1 FOUP Storage and transfer for FOUP Bottom lifting and top clamping
transfer in equipment or production line (classification according to the way of
manipulator taking and placing FOUPS)
2 Wafer Used for different sites of the Atmospheric manipulator, vacuum
transfer wafer inside the equipment manipulator (classification by
manipulator transfer (FOUP reactor) operating environment)
3 Rewinding Used for the replacement or Single fork and multi-forks
manipulator transfer wafers between or
inside FOUP
72 Main Common Parts 1607

Fig. 72.3 Double-arm

vacuum manipulator

Fig. 72.4 Single-arm

vacuum manipulator

1. Vacuum manipulator: It is used for wafer transmission between different working

stations or different process chambers in vacuum environment during IC pro-
cessing. The functions of a manipulator can be achieved under vacuum (ultra-
clean) condition by means of: (1) use large gap direct drive motor; (2) multiple
motion shafts with coaxial direct driving and vacuum isolation; and (3) accurate
servo control in high vacuum and high clean environment. These methods have
the characteristics of good sealing, small particle pollution, and high transmission
efficiency. According to the number of arms, vacuum manipulators can be
divided into two types: double arm and single arm, as shown in Figs. 72.3 and
72.4.
2. Atmospheric manipulator: It is mainly used for wafer transmission under atmo-
spheric pressure. Atmospheric manipulator uses high rigidity light metal arm,
high performance AC servo system, and high precision harmonic reducer to
achieve the high-speed and stable operation of the overall transmission.
According to the different ways of transmitting wafers, the manipulator arm can
be divided into contact type and noncontact type.

The contact arm is characterized by direct contact between the end effector and
the wafer during transmission. The wafer is usually carried by vacuum adsorption
mode or lifting mode, as shown in Figs. 72.5 and 72.6. Because the contact arm
contacts the wafer surface directly, it is easy to cause defects such as contamination,
1608 Z. Cheng et al.

Fig. 72.5 Vacuum

adsorptive air manipulator

Fig. 72.6 Lifting

atmospheric manipulator

scratches, and warpage on the wafer surface, so the noncontact arm has been applied
in IC equipment with higher requirements.
Noncontact wafer transmission mainly uses the principle of aerodynamics to
realize the noncontact “gripping” of the manipulator to the wafer. The typical
application is the Bernoulli fork [3, 4]. Noncontact manipulators are used more
and more often, because they are less sensitive to wafer materials and shapes,
produce no scratches on the wafer surface, and result in less environmental pollution.

Mass Flow Controller (MFC)

The mass flow controller (MFC) is a precise device for the automation that can be
applied to measure and control all kinds of gases (including N2, H2, CH4, and NH3)
accurately, while the accuracy of MFC measurement is not subjected to the change
of pressure or temperature. Additionally, MFC can achieve flow control according to
the customer’s set point; it has been used in various semiconductor processes such as
diffusion, oxidation, epitaxy, CVD, etching, and so on, for controlling and delivering
72 Main Common Parts 1609

Fig. 72.7 Image of mass

flow controller

processing gases. Similarly, for solar cell production, optical fiber melting, diamond-
like carbon coating, intraocular lens manufacturing, superconducting materials,
nuclear fuel treatment, petroleum industry, chemical industry, fuel cell, and pharma-
ceutical industry, MFC has been applied successfully to meet requirements.
MFC could be designed based on thermal principle, pressure, or Coriolis, and so
on. Among which, thermal-based MFC shows more applications for high sensitivity,
fast response time, high accuracy, and direct measurement.
According to the control signal, MFC could be a digital or an analog type. Based
on digital technology of sensor compensation, digital MFC shows better accuracy,
stability, and response time; and can accommodate with RS-485, DeviceNet, and
ProfiBus communication interfaces. MFC could be integrated in the gas line by
ultraclean VCR, IGS W-type or C-type connectors. For high requirement of accu-
racy, response time, and surface cleanliness in semiconductor market, digital MFC
shows more competitiveness. Figure 72.7 shows the image of an actual MFC
product.
An MFC is mainly composed of flow sensor, flow control valve, and control
circuit, as shown in Fig. 72.8. Typically, the flow sensor is based on thermal or
pressure principle. Solenoid valve or piezo valve could be used as the control valve.
The thermal-base or pressure-base sensor can measure the flow when gases pass
through the MFC. Then sensor signal is amplified and compared by the set point
signal. The control algorithm calculates the control output according to the error and
sends the signal to the flow control valve, which then changes the flow rate by
adjusting distance between the orifice and the plunger, in such a way to act as a close-
loop control system. Table 72.2 shows the main specifications of MFC.
1610 Z. Cheng et al.

Fig. 72.8 MFC structure

diagram

Table 72.2 Main specifications of MFC

No Item Specifications Notes
1 Valve rest NC/NO NO: valve open;
position no power
NC: valve close;
no power
2 Full scale (N2) (0 ~ 1, 2, 3, 5, 10, 20, 30, 50, 100, 200, 300, SCCM: mL/min
and 500) SCCM SLM: L/min
(0 ~ 1, 2, 3, 5, 10, 20, and 30) SLM
3 Accuracy
0 8% SP(30% FS),
0 24% FS FS: full scale
(5% ~ 30% FS)
4 Response time 500 ms ms: millisecond
5 Repeatability
0 2% FS
6 Leak integrity 11011 Pa-m3 /secHe (None)
7 Temperature Zero:
0 02% FS/oC, Span:
0 05% FS/oC
coefficient

MFC product calibration is necessary, as MFC can handle all kinds of gases
which could be toxic or flammable and explosive gases in different applications.
However, for safety and convenience, nitrogen (N2) is normally used for the
calibration. Conversion factor (CF, target gas versus N2) is adopted to calibrate
MFC, which could be obtained by tests.
Well-known MFC suppliers for semiconductor application are Brooks, MKS,
Horiba STEC, Fujikin, and Naura. Currently, most of the IC production line use
digital-type MFC, and the average price is about $2000 per unit.
72 Main Common Parts 1611

RF Generator

Radio frequency electromagnetic (EM) waves are high frequency alternating elec-
tromagnetic waves that can radiate into the space. The frequency range of the RF
power supply adopted in IC equipment ranges from 300 kHz to 300 MHz. RF power
supply is used as a matching power source for plasma generators, and it is mainly
applied to generate plasma in low pressure or atmospheric pressure and is widely
used in RF sputtering, PECVD, plasma etching, and other process fields of the IC
manufacturing processes. Plasmas of different gases perform different chemical
properties; therefore, they are often applied in different process equipment. For
example, the oxygen plasma is highly oxidizing, in which photoresist is oxidized
by oxygen plasma to form volatile gases, thereby achieving the cleaning effect, and
thus, it is commonly used in the degumming equipment; the plasma of a corrosive
gas, such as Cl2 or CF4, has a good anisotropy in RIE processes, and therefore, it is
often used in plasma etching equipment.
Commonly adopted output frequencies of RF power supply are 2 MHz,
13.56 MHz, 27.12 MHz, 40.68 MHz, 60 MHz, etc., and the RF power ranges
from several watts to several kilowatts. Figure 72.9 shows the designed functional
blocks of the advanced switching mode solid-state RF power supply. It is charac-
terized in that an integrated application of the high frequency (100 kHz) switching
rectifying circuit can eliminate the need of bulky power frequency transformer and
provides the driving power for RF drive circuits; compared with traditional linear RF
power supplies, it has the characteristics of low-power loss, low storage energy, and
compact system size, so it is very suitable for plasma processes in semiconductor
thin film deposition equipment and industrial coating equipment.
According to the type of power amplifier used, the RF power supply can be
divided into two types: transistor RF power supply and tube RF power supply.
Compared with the latter, the transistor RF power supply has the advantages of small
size, precise power control, stable output, high frequency accuracy, and no pre-
heating required starting. In the low-power field (less than 2 kW), the tube RF power
supply has been gradually replaced, but the tube RF power supply is significantly
superior to the transistor-type in terms of anti-standing wave ratio, so it is still widely
used in the high-power field (greater than 2 kW).

Fig. 72.9 Schematic diagram of the principle of switching mode solid-state RF power supply
1612 Z. Cheng et al.

The RF power supply is generally composed of an RF power source, an RF

impedance matcher, and an impedance power meter. The RF power source provides
a high frequency sine wave voltage at a fixed frequency; the impedance matcher
mainly adjusts the impedance of the LC network to match the load impedance and
the internal impedance of the RF source to minimize the reflection loss of the RF EM
wave and maximize the output power, so as to ensure that as much RF power energy
as possible enters the input end of the equipment and improve the equipment
performance; the impedance power meter is generally adopted to display the real-
time status of RF impedance matching.
At present, the major RF power supply manufacturers include Advanced Energy
(AE), MKS ENI, ADTEC, COMDEL, SEREN, and VEECO in the United States;
KYOSAN and DAIHEN in Japan; HUTTINGER in Germany; and RFG Series of
IME-CAS in China. The price of RF power supply is generally between $10,000 and
tens of thousands of dollars depending on the power and supporting requirements.

Local Scrubber

The local scrubber is an indispensable auxiliary subsystem in the IC manufacturing.

Its operation principles are to purify the toxic and harmful substances and smokes in
the exhaust gases of the IC manufacturing plant under the reaction of the catalyst, to
achieve the gas emission standards after treatment, so as to reduce the environmental
and air pollution, and eliminate hazardous substances to human health.
The main exhaust components produced in the semiconductor production process
include NH3, HCl, HF, IPA, C3H8O, HMDS, SiH4, H2, AsH3, PH3, B2H6, CH3F,
CHF3, CH2F2, C4F6, C5F8, and other general exhaust gases.
The main features of the local scrubber are: the smoke removal and deodorization
effect are obvious, without secondary pollution; the intelligent regeneration control
system can effectively control the regeneration and reduce the energy loss; and the
purification system can realize the automatic control and operation.
The local scrubbers are classified into combustion, electrical heating, plasma, and
absorption types according to different treatment methods of exhaust gases.

1. The combustion type for exhaust gases treatment is to introduce a combustible

gas such as CH4, or C3H8 with O2 into the treatment chamber, and treat the
combustible exhaust gases by high-temperature combustion at a temperature of
up to 1600  C, thereby effectively treating various combustible exhaust gases,
including perfluorinated compounds (PFC). Since CH4 and C3H8 themselves
have a high risk of catching fire, they must be used with caution.
2. The electrical heating type for exhaust gases treatment is mainly applied to treat
some flammable gases, such as H2, whose combustion products are soluble in
water. Since the heating temperature is 800–1100  C, it is not suitable to treat
perfluorinated compounds (PFC) with excessively high flammable temperatures.
3. The plasma type for exhaust gas treatment is applied to break down the chemical
bond between the gas molecules of exhaust gases with the energetic ion beam, so
72 Main Common Parts 1613

that the target gases are decomposed to unharmful molecules, thereby achieving
the purpose of exhaust gas treatment. This method is suitable for treating some
exhaust gases with relatively stable properties.
4. The adsorption type for exhaust gas treatment adopts an adsorbent to remove
harmful and odorous components in the exhaust gases by physical or chemical
adsorption. However, this method is not efficient for chemically stable exhaust
components.

Since the exhaust gases generated in the IC manufacturing process are basically
mixed gases from equipment, the most reasonable method is to comprehensively
analyze the properties of the mixed exhaust gases that may be generated in various
processes according to the specific process category, and then one performs a
systematic type of selection for local scrubbers.
In order to prevent the exhaust gas treatment from being affected by abnormal
shutdown during the operation of the equipment, the usual adopted method is to use
the mechanism of mutual support and finally connect the exhaust gas outlet of the
local scrubber to the central acid exhaust system of the production line (i.e., the
factory exhaust gases centralized treatment system also as the central scrubber) for
the final purification. This centralized treatment system is bulky, complex, and has an
online monitoring and analysis function. The exhaust gases treated by the system
must meet the standards of emission control.
Figure 72.10 is the schematic of a typical electrical heating type with water
scrubbing-based local scrubber, and Fig. 72.11 is the schematic of a typical com-
bustion type with water scrubbing-based local scrubber. Table 72.3 lists various
types of local scrubbers in IC manufacturing.

Fig. 72.10 Schematic of a typical electrical heating with water scrubbing-based local scrubber
1614 Z. Cheng et al.

Fig. 72.11 Schematic of a typical combustion type water scrubbing-based local scrubber

Table 72.3 Types of local scrubbers for integrated circuit manufacturing

Number Type of local scrubber Treatable gases
1 Combustion SiH4, H2, and perfluorinated compound (PFC)
2 Electrical heating SiH4, H2, and NF3
3 Plasma PFC, STF, and HCl
4 Adsorption AsH3, PH3, HBr, HCl, BF3, Cl, and ClF3

Dry Pump

The dry pump is one of the most important auxiliary facilities in IC equipment field.
It is mainly adopted to provide a vacuum environment for IC equipment and is
widely used in LPCVD, etching, PVD, CVD, and other vacuum equipment. It can
also be used in chemical industry, pharmaceutical industry, food industry (distilla-
tion, drying, defoaming, packaging, etc.), processes that may produce particles and
to prevent contamination of organic solvents or oil, etc. Comparing with traditional
mechanical pumps, dry pumps have the characteristics of high cleanliness, excellent
mechanical performance, high reliability, and minimum maintenance.
According to the different operation principles, dry pumps can be divided into
four kinds: dry screw vacuum pump, oil-free reciprocating vacuum pump, claw
vacuum pump, and oil-free scroll vacuum pump. The operation pressure of the dry
pump ranges from 103 to 103 Torr.
In addition, the structure of dry pumps can be divided into two types: contact type
(including blade type, cam type, reciprocating piston type, diaphragm type, etc.) and
noncontact type (including roots type, claw type, screw type, turbine type, etc.).
72 Main Common Parts 1615

Contact dry pump has a low running speed and is suitable for small capacity and high
compression ratio requirements. The noncontact dry pump has a high running speed
and is suitable for the case of large capacity and low compression ratio requirements.
There are many types of dry pumps with their own characteristics, which can be
selected according to the specific applications. Figures 72.12 and 72.13 illustrate the
operation principle of these two dry pumps.
At present, the manufacturers of dry pumps include VARIAN (the United States),
PFEIFFER (Germany), Leybold (Germany), Edwards (the United Kingdom),
ALCATEL (France), ULVAC (Japan), EBARA (Japan), etc. Dry pumps used in
semiconductors typically cost between $10,000 and tens of thousands of dollars.

Fig. 72.12 Diagrams of operation principle of turbine dry pump

Fig. 72.13 Diagrams of operation principle of screw dry pump

1616 Z. Cheng et al.

Cryopump

A cryopump, also known as condensation pump or cryogenic pump, is a vacuum

pump that condenses and adsorbs gases through a low temperature surface to obtain
a vacuum [5, 6]. The cryopump has the characteristics of cleanliness and no
pollution (no oil), high efficiency, high pumping speed (for all gases), good reliabil-
ity, and high ultimate vacuum. It is widely used in the evaporation, sputtering, ion
implantation, molecular-beam epitaxy (MBE), and other processes in the semicon-
ductor IC manufacturing processes, and it is also widely used in vacuum coating
equipment, electric vacuum devices, high-energy particle accelerators, controlled
thermonuclear reactions, surface analysis instruments, and materials science.
The cold source of the cryopump is generally a cryogenic refrigerator or a
cryogenic liquid. Usually, the cryopump is divided into two types: closed loop
gaseous helium refrigerator cryopump and injection liquid helium cryopump. The
advantages of the closed loop gaseous helium refrigerator cryopump are that it does
not consume helium, it is easy to maintain and operate, and the gaseous helium is
used as the refrigerating medium of the refrigerator. The temperature of the primary
cold plates ranges from 50 to 100 K and its function is to condense water vapor and
precool other gases, and provide radiation shield for the colder cold plates in the later
stages. The temperature of the secondary cold plates ranges from 10 to 20 K and its
function is to condense gases passing through the baffles, such as N2, O2, and
Ar. The inner surface of the secondary cold plates is coated with activated carbon,
in which the small amount of residual gases that cannot be condensed by the cold
plates is adsorbed by the activated carbon. The specific surface area of the activated
carbon ranges from 500 to 2500 m2/g, and it has strong absorption capacity for He,
Ne, and H2 at low temperatures. The cold plates are of surface-polished oxygen-free
copper materials to reduce the emissivity. The pre-pumping pressure of the pump is
1 Pa. Figure 72.14 shows the structure of a refrigerator-type cryopump.
The main parts of the injection liquid helium cryopump include a pump body, a
liquid helium container, and a liquid nitrogen chamber connecting the baffles. The
outer wall of the liquid helium container is double-layered insulation wall, and
vacuum is produced between these two layers to reduce the consumption of liquid
helium. When the pump is operated to 106 Pa, liquid nitrogen and liquid helium are
poured, and the gases are condensed on a condensing plate with a temperature of
4.2 K; after the pre-pumping, the partial pressure of helium and hydrogen can reach
the order of 1012 Pa. The ultimate pressure of the pump can reach 1011 Pa or less.
The research on cryopumps has been started very early in the United States. Its
latest cryopump products have widely adopted the frequency conversion technology
and have initially realized intelligence and networking, such as the On-Board series,
On-Board IS series, and Cyro-Torr series produced by CTI in the United States. In
addition, the technology level of related products of ULVAC in Japan and Leybold in
Germany is also high. Due to the increasing requirements of integrated circuit
processes, non-clean vacuum pumps such as diffusion pumps have been gradually
eliminated, providing an increasing market space for highly clean cryopumps.
72 Main Common Parts 1617

Fig. 72.14 Structure of refrigerator-type cryopump

Turbo Pump

The turbo pump, also known as turbo-molecular pump [7, 8], is a versatile and
reliable vacuum pump that is widely used in etching, deposition, metallization, ion
implantation, and other IC manufacturing processes – turbo pump has become an
important part of IC manufacturing equipment.
The turbo pump works by mechanically compressing the gases so as to drive the
gaseous molecules moving in a specified direction. The pump body is composed of
an electric motor, a rotor, and a stator (connected to the inner surface of the pump
casing). The rotating blades of the rotor and the fixed blades of the stator are spaced
apart from each other, and each set of rotors and stators constitutes a compression
unit. Different types of turbo pumps have different numbers of compression units,
usually 10–40 pcs. When the turbo pump is working, the motor rotates at a high
speed, which drives the rotor to draw the gases from the inlet, and make the gaseous
molecules to obtain the directional velocity by the momentum transfer; the gases
undergo a compression process in each compression unit, and after 10–40 times of
compression, it is driven to the exhaust port, thus achieving high-speed vacuum with
a high compression ratio, as shown in Fig. 72.15.
When the turbo pump rotor rotates, the rotation speed of the blade end needs to be
close to the average velocity of the gas molecules, so that the gas molecules can
obtain the directional velocity by colliding with the rotor blades. Therefore, the turbo
1618 Z. Cheng et al.

Fig. 72.15 Schematic diagram of turbo pump

pump rotor needs to rotate at a very high speed. Normally, the turbo pump rotor has a
rotational speed of approximately 20,000 rpm and a maximum speed of 90,000 rpm.
The exhaust velocity of the turbo pump is proportional to the blade angle. When
the blade angle is large, the exhaust velocity is high, and vice versa. The compres-
sion ratio of the turbo pump is inversely proportional to the blade angle. When the
blade angle is large, the compression ratio is small. When the blade angle is small,
the compression ratio is large. The exhaust velocity of the turbo pump is basically
independent of the type of gases, but when light gases (such as hydrogen, helium,
and so on) are pumped, the exhaust velocity will be reduced. As dry gases are
pumped, the turbo pump can reach the ultimate pressure of 108 Pa, and the turbo
pump can be applied to produce a large gas output and achieve high-speed vacuum
with a high compression ratio.
The initial operation pressure for turbo pump is less than 103 Torr. Therefore, as
the turbo pump is in operation, it is necessary to avoid accidentally exposing the inlet
of the turbo pump to the atmospheric pressure. Otherwise, the blades of the turbo
pump may be bent and collide with each other, resulting in a serious damage to the
equipment; it is also necessary to prevent particles from entering the turbo pump to
damage rotating blades. In addition, any physical vibrations should be avoided,
because the rotating shaft of the turbo pump is precisely balanced. Shocks or
collisions during the operation can cause the rotating shaft to be damaged. In severe
cases, the turbo pump will be seriously damaged. The turbo pump generally does not
require external maintenance and is generally replaced directly when damaged.
Applied turbo pumps were successfully developed in 1955. With the application
of dynamic balance technology, vibration damping technology, magnetic suspension
bearings, aluminum alloy/titanium alloy/carbon fiber and other high-strength mate-
rials, and the advancement in numerical control machining technology, frequency
72 Main Common Parts 1619

conversion technology, control theory and information technology, turbo pumps

have been continuously improved and innovated in structure and performance, and
have also been further enhanced in application development and intelligent control.
At present, the manufacturers of turbo pumps adopted in the IC industry mainly
include Pfeiffer Vacuum in Germany, Edwards in the United Kingdom, Leybold in
Germany, Varian in the United States, ALCATEL Vacuum in France, and ULVAC in
Japan, and the unit price ranges from USD 10,000 to tens of thousands of dollars.

Chiller

The chiller is a temperature-controlling unit via cooled or heated liquid media. Its
operation range of temperature is 5–40  C. Chiller could be classified as two types
regarding the operation range of temperature: one is cooling chiller, whose range is
below the room temperature (RT), and the other is heating chiller, whose range is
above RT.
Cooling chiller consists of three channel loops for: liquid media circulating loop,
refrigerator circulating loop, and cooling water circulating loop. Circulating liquid
media, usually water or ethanediol, is used for the temperature control of target
components. Refrigerator circulating liquid, usually Freon, is used for the tempera-
ture control of circulating liquid media. Cooling water circulating, usually water, is
used for the temperature control of refrigerator liquid media through the heat
exchange between them.
Figure 72.16 is the cooling chiller schematic (SMC, HRS series). Taking cooling
mode as an example, the chiller operation flow is: circulating liquid media flows
through the target component and absorbs its heat. Then the target component is
cooled and circulating liquid media is heated. Thereafter, circulating media is cooled
again when flowing back through the refrigerator circuit loop via the evaporation and
condensation of refrigerator media. Finally, the extra heat captured from the target
component is extracted out of chiller through the heat exchange by cooling water.
In industry, chiller is applied to control the temperature of liquid source and
substrate, which needs higher accuracy of temperature control. Many vendors can
provide production level chillers. In semiconductor area, main vendors are ATS (the
United States), SMC (Japan), SHINWA (Japan), and SMEE (China).

Valves

The valve is a mechanical device installed in the pipeline for controlling the opening
and closing of the pipeline. Its main function is to control the flow, pressure, and
other parameters of the flowing medium in the pipeline. The flowing medium
through which the valve controlled can be liquid or gas.
The valves used in the field of IC manufacturing are divided into hand valves,
solenoid valves, pneumatic valves, and check valves according to different driving
1620 Z. Cheng et al.

Fig. 72.16 Schematic of cooling chiller (SMC, HRS series)

methods; they are also divided into metal valves and nonmetal valves according to
different materials, and divided into gas valves, liquid valves, and vacuum valves
according to the different applications. Furthermore, as shown in Fig. 72.17, most
commonly adopted valves in the IC manufacturing are ball valves, check valves,
pressure reducing valves, diaphragm valves, bellows valves, gate valves, and so
on. The main technical indicators of these valves are as follows.

1. Cleanliness: The inner surface of the valve is electrolytically polished and

finished to the electrolytic polished (EP) level.
2. Sealability: Most of the gases or liquids in the pipelines of IC equipment are
hazardous gases or liquids, so the sealing requirements of valves are very strict,
and the leak rate can reach 109 cm3/s or below at test.
3. Pressure resistance: Since the media in the pipelines are mostly dangerous high-
pressure gases (liquids), there is a pressure resistance requirement for valves.
Some valves are required to have a pressure resistance of several thousand psi
(1 psi ¼ 1 lbf/in2 ¼ 6.89476 kPa).
4. Corrosion resistance: Most of the gases (liquids) used in IC manufacturing are
corrosive, so the requirement of corrosion resistance for valve materials is very
high. For example, metal valves are usually made of 316 L stainless steel, and
nonmetallic valves are usually made of PTFE (Teflon).
72 Main Common Parts 1621

Fig. 72.17 Common valves in IC manufacturing industry

Due to the difference in the pressure, temperature, flow, and physicochemical

properties of the media, the control requirements and usage requirements for the
devices and piping systems are also different. The types of valves commonly used in
IC manufacturing are listed in Table 72.4.
Internationally renowned valve suppliers in the semiconductor equipment indus-
try include Swagelok, Fujikin, HAM-LET, MKS, and VAT.

Gas Panel

The gas system is applied to control and deliver gases in the process equipment for
IC manufacturing. It is the key auxiliary unit of the process equipment, in which
there are three main types:

1. Process gas system: This system is mainly applied for controlling and delivering
high purity gases, toxic and corrosive gases to the reaction chambers for fabrica-
tion processes. It is the most important auxiliary unit in equipment for the
implementation of IC manufacturing. The stability of operation is one of the
key factors required for the process gas system. After the filtering, the acceptable
particle size in pipelines must be less than 0.003 μm, and the leakage rate of
whole pipelines should be less than 109 Pa-m3/s. As shown in Fig. 72.18, the
regulator valves of gas system are applied to keep a stable pressure in pipelines
and are also designed to be easily disassembled and replaced. All pipelines are
1622 Z. Cheng et al.

Table 72.4 Types of commonly adopted valves in integrated circuit manufacturing

Valve type Action Application area
Stop valve Control pipeline opening and Suitable for the operation of frequent
closing opening and closing
Ball valve Control pipeline opening and Suitable for circulation pipes with large
closing diameter and low resistance
Vacuum Control the vacuum of the Suitable for the vacuum control
butterfly pipeline
valve
Check valve Limit circulation direction and Control the mono-directional flow of the
ensure safety fluid and realize the automatic pressure
relief
Relief valve Adjust the pressure of the Suitable for the adjustment of pipeline
circulating medium pressure
Metering Precise control of the amount of Accurate flow control based on the
valve flow of the circulating medium adjustment of valve opening
Gate valve Partition and seal Suitable for the partitioning and opening of
two sealed chambers
Pneumatic Control pipeline opening, Suitable for high sealing requirement for
diaphragm closing, and sealing the gas path or vacuum pipe
valve
Bellows Control pipeline opening, Suitable for high sealing requirement for
valves closing, and sealing the gas path or vacuum pipe
ALD valve Control high-speed opening and Suitable for controlling the high-speed
closing of pipelines opening and closing of the gas path
Nonmetal High erosion resistance Suitable for high corrosion resistance
valve requirements

Fig. 72.18 Schematic

diagram of the process gas
control panel
72 Main Common Parts 1623

made of fully annealed seamless stainless steel (EP level). In order to avoid any
residual contaminants inside the pipelines, standard clean process and high pure
nitrogen purge are necessary for pipelines prior to be assembled in the gas system.
Figure 72.18 is the schematic diagram of the process gas system; the main
components of each gas pipeline include gas filter, handle valve, regulator,
pressure transducer, mass flow controller, pneumatic valve, check valve, etc.,
which are connected with VCRs of C-seal or W-seal. So far, the most popular gas
system is the integrated gas system (IGS) shown in Fig. 72.19. IGS performs high
integration, smaller volume, convenient maintenance, easy modification, etc.
2. Gas system for component driving: It is mainly applied to control the operation
for cylinder, solenoid valve, gas seal ring, gate valve, angle valve, and vacuum
proportional control valve by the gas pressure. That is, this gas system performs
as the gate to control the on/off valves and make the fabrication process going
smoothly. The gas inlet of pipeline is made of high-quality fully annealed
stainless steel (BA level). The back end of each component in the pipeline is
connected to the valve with polyurethane tube. These pipelines should not be laid
with electric cables and wires on the same rack.
3. Purge gas system: Particles are the main yield killer of ICs. Therefore, a contin-
uous supply of pure purge gas can keep a clean environment in the reaction
chamber of equipment, so as to reduce the particle level for better process yield.
Purge gas pipeline is made of high-quality purity stainless steel (BA level). After
the purge gas system is assembled, it is necessary to purge all pipelines with high
flow pure nitrogen gas to make the whole system meet the cleanliness require-
ments before this system is equipped with the main equipment.

Fig. 72.19 Structure

diagram of IGS
1624 Z. Cheng et al.

Electrostatic Chuck (E-Chuck)

The electrostatic chuck (E-chuck or ESC) [9, 10] is one of the most important
components of IC equipment and is widely used in etching, PVD, CVD, and other
equipment. The main functions of the E-chuck are listed as follows:

1. To carry and hold the wafer by electrostatic attraction force.

2. To control the E-chuck temperature with embedded heaters or coolers. Also, to
introduce helium gas for better thermal conduction between the E-chuck and the
wafer so as to well control the wafer temperature.
3. To provide the bias RF power for the wafer during the etching process.

According to the number of electrodes, the E-chucks are divided into unipolar and
bipolar types. Also, based on the operation principle of electrostatic attraction force,
the E-chucks are further classified into Coulomb type (pure dielectric chucks) and
Johnsen-Rahbek (J-R) type (doped dielectric chucks) [11]. Both types of E-chucks
hold the wafer by opposite attraction force of static charges. The Johnsen-Rahbek
(J-R) type E-chucks have a higher attraction force than the Coulomb type E-chucks,
and the dielectric medium usually is a doped aluminum nitride ceramic material with
good thermal conductivity. In general, E-chucks utilize a combination of Coulomb
force and J-R force.
The E-chuck structure generally consists of a chuck substrate, a surface ceramic
dielectric layer with embedded DC electrode, helium channels, multiple temperature
sensors, coolant channels, and an RF leading-in end, as shown in Fig. 72.20.
A DC electrode (slightly smaller than the wafer) is embedded in the ceramic
dielectric layer of the E-chuck (also see Fig. 34 in Sect. 8, ▶ Chapter 7). When the
electrode is connected to a high-voltage DC power supply, polarized charges are
generated on the dielectric surface (for J-R E-chucks, there are not only polarized
charges but also a large portion of mobile charges), while an electric field generated
by these surface charges of the dielectric medium will induce opposite polarized
charges on the back side of wafer. Therefore, the wafer is held on the chuck by the
attractive force.

Fig. 72.20 Structural diagram of the E-chuck structure

72 Main Common Parts 1625

In addition to the DC electrode, there is also an RF electrode leading-in end

embedded in the E-chuck to provide the required RF bias power for wafer pro-
cessing. In addition, coolant channels and helium gas channels for the temperature
control of wafer are also assembled.

Process Chamber Showerhead

The showerhead is a 2D injection component for achieving a uniform distribution of

reaction materials (precursors, gases, or liquids) in the reaction chamber.
Figure 72.21 is the cross-section structure of a typical showerhead. As shown, this
showerhead consists of inlet, buffer chamber, and outlet. Inlet includes numerous
separate pipelines as injection path of precursors. Buffer chamber is a small buffer
zone to uniformly mix precursors prior to the diffusion of precursors into the main
reaction chamber. Outlets, composed of a dozen or hundreds of small holes, are
distributed on a 2D plane to perform a uniform distribution of precursors on the
whole substrate. Compared with the line or point injection, 2D injection showerhead
ensures a better uniform film deposition.
Generally, the design of precursor inlet direction used to be parallel with that of
pipeline path, in which there was always a pressure shock effect to the outlet plane
and the substrate due to the violent pressure change inside the pipeline path. In order
to eliminate this effect, the inlet direction could be modified to be tangential to the
tube path, which means perpendicular to the tube path direction, shown in
Fig. 72.21. Meanwhile, curved inlet gas path also facilitates the uniform mixing of
precursors, which is required for a uniform film deposition. The geometry, volume,
as well as outlet hole’s dimension and distribution of the buffer chamber will impact
on the uniformity of precursor distribution.
Normally, precursor paths inside the showerhead are shared with all precursors,
which mean all precursors firstly mix inside the showerhead prior to the reaction
process. In some particular area, mixing inside showerhead is not allowed regarding

Fig. 72.21 The cross-section

structure of showerhead
1626 Z. Cheng et al.

Fig. 72.22 Cross-sectional structure of dual channel showerhead

the particle and uniformity concerns, in which it requires two or more individual
paths for different precursors. As shown is Fig. 72.22, a dual channel showerhead is
applied in atomic layer deposition (ALD) tool [12]. Two separate precursor channels
ensure no precursor mixing inside the showerhead and maintain a longer lifetime of
showerheads.
Showerhead is commonly applied in plasma-enhanced chemical vapor deposition
(PECVD), ALD and cleaning tools, etc.

Reaction Chamber

The reaction chamber is the main part of the process tool in IC manufacturing;
most process reactions are performed in the chamber. The material, roughness,
particle, mechanical property, thermal property, and etchant resistance of chamber
will significantly impact on the process performance. According to the material,
the chamber could be classified as resin chamber, metal chamber, and quartz
chamber.
For cleaning tool, the operation temperature is lower than 200  C but needs a
higher etchant resistance due to chemical materials. Therefore, the chamber material
is always resin based, such as PFA and PTFE.
For PVD, CVD, and ETCH tools, vacuum is always required, and the temperature
should be moderate (about 800  C). Given that, the reaction chamber mostly
concerns about the mechanical and thermal properties, metal chamber is thus
preferred, such as aluminum alloy, nickel, and stainless steel.
For epitaxy, oxidation, diffusion, annealing tools, high operation temperature is
needed (500–1200 C). Hence, quartz- or SiC-based chamber is preferred, which also
possess a low risk of material contamination.
Per wafer quantity, reaction chamber could be classified as single-wafer chamber
and multi-wafer chamber. As shown in Fig. 72.23, single-wafer chamber can only
72 Main Common Parts 1627

Fig. 72.23 Single-wafer

chamber

Fig. 72.24 Horizontal multi-

wafer chamber

hold one wafer each time, resulting in high flexibility and better process perfor-
mance, but lower throughput; while for multi-wafer chamber, it can result in higher
throughput but not as flexible as single-wafer chamber. In addition, multi-wafer
reaction chamber could be further classified as horizontal type and vertical type, as
shown in Figs. 72.24 and 72.25.
1628 Z. Cheng et al.

Fig. 72.25 Vertical multi-

wafer chamber

References
1. SEMI-101 Guide for EFEM Functional Structural Model. SEMI E Series, Equipment
Communications
2. Equipment Front End Module (EFEM) market report. https://market.biz/report/global-
equipment-front-end-module-efem-market-gm/
3. Bernoulli grip. https://en.wikipedia.org/wiki/Bernoulli_grip
4. P. Vita, B. F. W. Gschaider, D. Prieling, and H. Steiner, Thin film flow simulation on a rotating
disk, European Congress on Computational Methods in Applied Sciences and Engineering
(ECCOMAS 2012), J. Eberhardsteiner et al., Eds., Vienna, September 10–14 (2012),
p. 4446.1–4446.11
5. J.F. O’Hanlon, A user’s guide to vacuum technology, 3rd edn. (Wiley, Hoboken, 2003)
6. K.M. Welch, Capture pumping technology, 2nd edn. (North-Holland Elsevier, Amsterdam, 2001)
7. Working with Turbopumps. https://mmrc.caltech.edu/Vacuum/Pfeiffer%20Turbo/Turbos.pdf
8. M. Audi, S. Giors, R. Gotta, The state of the art in molecular-drag turbo-pump technology.
https://www.vacuum-uk.org/pdfs/vs2/VacPumps/TwisTorr.pdf
9. S. Qina, A. McTeer, Wafer dependence of Johnsen–Rahbek type electrostatic chuck for
semiconductor processes. J. Appl. Phys. 102, 064901 (2007)
10. K. Choi, Y.C. Kim, H. Sun, et al., Quantitative electrode design modeling of an electroadhesive
lifting device based on the localized charge distribution and interfacial polarization of different
objects. ACS Omega 4, 7994–8000 (2009)
11. M.R. Sogard, A.R. Mikkelson, M. Nataraju, et al., Analysis of coulomb and Johnsen-Rahbek
electrostatic chuck performance for extreme ultraviolet lithography. J. Vac. Sci. Technol.
B Microelectron. Nanometer Struct. Process. Meas. Phenom. 25, 2155–2161 (2007)
12. S.M. George, Atomic layer deposition: An overview. Chem. Rev. 110, 111–131 (2010)
Integrated Circuit-Testing Equipment
73
Yanfeng Jiang, Zhiyong Zhang, Kun Yu, and Jianhua Qi

Contents
Overview of IC Testing Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
Logic IC Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
Memory IC Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
SoC Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
Analog/Mixed-Signal IC Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
RF IC Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
Customized Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
Test Instrument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642

Abstract
Integrated circuit (IC) test equipment plays a very important role in the IC testing
industry. IC test equipment mainly includes automatic test equipment (ATE),
automatic probers, and IC test handlers. ICs can be tested automatically by ATE,
which improves the test efficiency and reduces test cost. This chapter focuses on
ATE, which is also a key comprehensive test equipment containing intensive
technology. The basic composition and principle of logic IC, analog / mixed
signal IC, memory IC, RF IC, SoC, and their testing with other types of automatic
test equipment as well as customized test equipment are described in this chapter.

Keywords
Automatic test equipment · SoC test system · Digital test system · Mixed signal
test system · RF test system · Test instrument

Y. Jiang
Beijing Institute of Automatic Test Technology, Beijing, China
Z. Zhang · K. Yu · J. Qi (*)
Sino IC Technology Co., Ltd., Shanghai, China
e-mail: qjhhl@sinoictest.com.cn

© Publishing House of Electronics Industry 2024 1629

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_73
1630 Y. Jiang et al.

Overview of IC Testing Equipment

A qualified integrated circuit (IC) chip, from the initial design to the final product,
requires going through hundreds of process steps. In order to ensure the quality of
chips, timely monitoring is required throughout the whole fabrication process.
Therefore, when the relevant major processes are finished, the corresponding process
parameters of chips should be monitored to ensure the controllability of product
quality. In other words, IC testing runs through the entire IC fabrication processes.
According to different test contents, IC test can be divided into two categories in the
fabrication: the process parameter test and the electrical parameter test. In order to
ensure the production efficiency and save the cycle time in the production line,
usually, only some process-related parameters of critical process steps, instead of all
the parameters, are selected to characterize the controllability and stability of major
processes during the fabrication. However, prior to the IC package step, the whole
electrical parameters of all chips on the wafer are necessary to be centrally tested
again to assure the chip quality and yield. Normally, this testing procedure takes a
longer time to centrally examine all electrical parameters involved in the IC chips;
thus, it plays a key role to assure the quality of IC products.
To speed up the centralized testing of electrical parameters and reduce the testing
cost of ICs, the semiconductor industry has developed relevant Automatic Test
Equipment (ATE) which can automatically complete the parameter testing of IC
by computer control. That is, IC test through the ATE can perform the centralized
testing to verify the electrical parameters of each chip on the wafer, so as to select
qualified chips for the package and ensure the quality of final products.
Figure 73.1 shows a schematic diagram of IC testing with the ATE. The ATE is
controlled by a computer to generate the input excitation signal Uin which is input to
the Device-Under-Test (DUT) through an external connection. At the same time, the
response of output signal Uout is collected at the output end of the DUT and sent to
the ATE data storage unit for the comparison with the prestored ideal output results
so as to judge whether the DUT meets the relevant specifications.
In general, the ATE is expensive and the demand in the test environment is very
strict, so it requires a test site of high standard. Meanwhile, multiple ATEs should run

Fig. 73.1 Schematic diagram

of an automatic testing for ICs
73 Integrated Circuit-Testing Equipment 1631

in parallel to ensure the testing speed and efficiency. Also, special dedicated test
programs are kept developing for various kinds of ICs to ensure the automatic
proceeding. A complete test production line normally contains high-standard test
sites, sufficient test equipment, and satisfactory capability to develop special testing
programs; at the same time, quality assurance systems and skillful engineers in
charge of the testing operation are also indispensable. In addition, with a high degree
of automation in the test production line to achieve all test items required by the chip
specification can enhance the testing efficiency and throughput, and further save the
labor cost and testing cost.
In recent years, global IC test equipment suppliers have continuously been
integrated to form two large companies: Advantest in Japan and Teradyne in the
USA, whose products account for more than 70% global market share of the
semiconductor testing enterprises.

Logic IC Test System

General digital IC test system is the ATE system adopted to test digital logic ICs. The
schematic diagram of a general digital IC test system is shown in Fig. 73.2.
General digital IC test system includes digital master sequencer unit, synchronous
controlling unit, waveform generation portion, waveform digitization portion, DC
portion, and time measurement portion. The digital master sequencer unit sends the
synchronous clock signal to the synchronous controlling unit, making all the units in
the system responding to the synchronous clock. As shown in Fig. 73.2, the
Arbitrary Waveform Generator (AWG) can generate the required waveform for

Fig. 73.2 Schematic diagram of a general digital integrated circuit test system
1632 Y. Jiang et al.

testing, which is converted to the digital waveform by the digitizer. The arbitrary
waveform digitizer (AWD) performs the storage and recording of digital waveform.
In general, the waveform generator generates the waveform signals required for
digital IC testing, which are provided to the Device Under Test (DUT) by an
effective connection, while the response signal is converted into a digital signal by
the digitizer and stored in the ATE. In the system, the DC-related measurements are
achieved in the DC unit, while the time-related measurements (mainly the function
of measuring the time interval) are performed in the time measurement unit.
Digital ICs have the characteristics of various variety, large quantities, and
complex logic relations. Therefore, the development of corresponding digital IC
test systems needs to consider increasing the test speed, the test library, and the test
vector depth. Among them, the method on improving the clock frequency can be
applied to increase the test speed. But in practical application, the multichannel
parallel measurement technology is mostly adopted for the speed enhancement. That
is, multiple DUTs are detected in parallel. Although the number of the required basic
units is increased, which could increase the total equipment cost to some extent, the
measurement time can be shortened and the testing cost can be reduced.
It is very important to add test library to solve the problem of various kinds of
digital ICs. By expanding the test library, each product can be measured specifically.
Thus, not only the test time can be reduced, but also the test coverage can be
increased. For digital ICs with complex logic relationships (such as CPU, et al.), it
is necessary to increase the test vector storage space and store the response results in
ATE to meet the requirements of test functions. In this way, the upgraded ATE with
more storage space can meet the requirements of the test functions.
In practical applications, in order to meet the diversity of the test circuits, the
corresponding extension interfaces should be supplemented, through which the
required test units can be added conveniently when necessary. This scalability is
an important issue in system design, which can achieve the purpose to save the test
resources and increase the test coverage.
At present, the international high-end manufacturers of digital integrated circuit
test systems are mainly Advantest in Japan and Teradyne in the USA. Their product
categories cover the whole series of high, medium, and low-end test systems, with
expensive price.

Memory IC Test System

At present, there are a variety of semiconductor memory ICs, in which different

memory IC chips perform different characteristics. Different in read/write accessi-
bility, there are access (read/write) memory and read-only memory. With the devel-
opment of design technology and processing technology, the main trend of
semiconductor memory ICs is developing toward higher integration, larger storage
capacity, and faster read/write speed.
The basic operation principle of the memory test is to write some data to the
memory IC, and then verify the read back data according to the address of the
73 Integrated Circuit-Testing Equipment 1633

relevant storage unit. If all the read back data and the written data are the same, it can
be determined that the function of this storage unit is correct.
The logic function of the memory IC is relatively simple and does not require
complicated test procedures. However, in order to ensure that the function of each
storage unit in memory IC is able to be detected, the most important feature of the
memory test is the large amount of data for the verification in one time, which
requires the test system to have a larger data throughput. At the same time, one of
the development directions of the memory test is to have faster read/write speed, so
new requirements are also put forward for the test waveform and the operation
frequency.
There is a misleading concept, that is, System on Chip (SoC) test systems are
equivalent to memory test systems. This is not true. Although SoC testing systems
can be adopted to detect memory storage units, it is extremely inappropriate to
confuse the SoC testing system with the memory test system from an industry
perspective. The SoC test system is much more complex than the memory test
system. Many functional blocks in the SoC test system are not available for the
memory testing. In addition, the number of the SoC test channels is much less than
those of the memory test channels. So, the SoC test system is not suitable for the
parallel detection of large-scale storage units. Although the logic function of
the memory chip is much simpler than that of the SoC chip, due to its high
integration and numerous memory cells, it is very time-consuming to detect the
memory cells one by one. Therefore, the Algorithmic Pattern Generator (APG) in
the memory test system becomes very important. The APG can generate a set of
vectors that satisfy the fault test coverage to ensure the test efficiency. The APG
mainly consists of three parts, namely, microprogram controller, address generator,
and data generator. In addition, due to the long test time of memory chips, in order
to improve the test efficiency and reduce the test cost, it is necessary to improve the
test throughput through multiple test heads and parallel tests in the industrial level
test of memory chips. Multitest head means that a test host can connect multiple
probe stations or manipulators for testing at the same time, while the parallel
testing means testing multiple chips simultaneously. At present, there are some
memory chip tests equipped with dual test heads and the capability of 512 parallel
chip testing in the world.
Currently, the global memory market is close to $80 billion, with about 50% of
the market in China. Driven by mobile communications, cloud computing, and
the Internet of Things (IoT), Flash memory applications will continue to grow
rapidly for the foreseeable future. With the booming global market of Flash
memory test systems, it has reached $148 million in 2018. At present, the main
manufacturer of memory test system is Advantest of Japan. Its T5 series
memory test system is very expensive, but it is still the main test equipment
of memory IC manufacturers, as well as the packaging and testing plants in
the world.
Faced with the strong demand for its domestic memory chips and their test
systems, China has begun to develop the design and wafer manufacturing of memory
chips. However, the self-developed memory test system is still not available.
1634 Y. Jiang et al.

SoC Test System

The SoC test system is the automatic test system for testing SoC chips, and its major
suppliers in the world are Teradyne of the USA and Advantest of Japan. Test system
provides the correct voltage, current, sequence, and functional state to the device
under test (DUT), and then it would observe the response to make the pass/fail
determinations by comparing the results of each test item with the predefined
restrictions. The SoC test system mainly consists of the system control module,
direct current instrument, functional/alternating current instrument, mixed-signal
instrument [1], RF signal instrument, mechanical hardware, operation software,
etc. Figure 73.3 shows the functional block diagram of a test system.
The system control module is the control center of the entire test system,
consisting of the high performance computers or workstations. The master control
computer should meet the requirements including high frequency, sufficient memory
and disk capacity, fast reading and writing speed, etc., with basic peripherals and
interfaces of computers such as keyboards, mouses, and monitors, supporting the
communication with other devices like the prober and the handler. There should be
corresponding system control module in the test head to complete the control and
communication between the master control computer and the test system. Usually,
the module also includes the system main clock, controlling signals of relay,
calibration circuits, and so on.
The direct Current Instrument consists of reference voltage supplies (RVS),
device power suppliers (DPS), precision measurement units (PMU), etc. Device
power suppliers provide programmable voltage or current to the device under test,
and it can also measure voltage or current of the chip power pins. As the impedance
causes a voltage drop generated by the routes between power supplies and chip

Fig. 73.3 The functional block diagram of the test system

73 Integrated Circuit-Testing Equipment 1635

power pins, then Kelvin connection is adopted to connect the power supplies with
chip power pins, so that an expected supply voltage can be applied to the chip power
pins. In practice, multiple power channels are connected in parallel to increase the
power supply current. The precise measurement unit is a precise force/measure unit
of voltage/current, which is used for the accurate measurement of DC parameters. It
also has the four-quadrant force/measure capabilities of voltage/current, and its
commonly applied functions are Force Voltage Measure Current (FVMI) and
Force Current Measure Voltage (FIMV).
The functional/alternating current instrument consists of three parts, which are
vector memory unit, timing subsystem, and pin electronics (PE). Vector memory
unit is used for the storage of both the testing excitations and the device responses.
Timing subsystem converts the logic signal (binary code) into an electrical signal
available to the pin electronics, in which timing settings define the period time and
edge time. The PE provides an interface between the internal resources of the test
equipment and the device under test. During the test, the PE provides an input signal to
the device under test and receives its output signal. The PE includes the Driver for
providing input signals, the Voltage Comparator for detecting the output level, Current
Load, and the I/O switch circuit for turning the on/off of the Driver and Current Load.
Figure 73.4 shows the typical block diagram of PE’s architecture. RVS provides the
reference voltage of logic 1 and logic 0 for the Driver and Current Load located at the
PE. These voltage settings include Input Low Voltage (VIL), Input High Voltage
(VIH), Output Low Voltage (VOL), and Output High Voltage (VOH). Some high-end
test systems of digital IC also provide Time Measurement Unit (TMU), which is used
for very accurate time and frequency testing to measure time parameters such as
period, pulse width, rising/falling time, transmission delay, etc [2].

Fig. 73.4 The block diagram of PE’s architecture

1636 Y. Jiang et al.

The mixed-signal instrument mainly includes an Arbitrary Waveform Generator

(AWG) and a Digitizer (DGT). The AWG is adopted to generate signals like sine
wave, triangle wave, etc., with accurate frequency, phase, and amplitude. The AWG
consists of data storage space, DSP, DAC, antialiasing filter, gain, bias regulator, etc.
The DGT converts continuous analog signals into discrete digital signals, including
antialiasing filters, ADC, data storage space, DSP, etc. In addition, the instrument
also needs to have the ability to synchronize analog signals and digital signals.
The RF signal instrument includes multiple independent RF subsystems with
independent RF test excitation and measurement capabilities. Each subsystem has an
RF signal source and multichannel RF ports, which can simultaneously fan out the
RF signals and support the simultaneous transmission or measurement of multi-
channel RF signals. This instrument has the function of baseband I/Q signal mod-
ulation to support the test of various common standard protocols and customized
protocols. In addition, it has the capabilities of fast synthesis and analysis.
The SoC test system provides the users with required software for the test
program development and the mass production, which includes a friendly graphical
interface, complete test program debugging tools, and the broad compatibility.
The main technical specifications of the SoC test system include the amount of
the channels, maximum data rate, vector depth, clock accuracy, resolution and
bandwidth of mixed signals, RF signal frequency, and others. At present, the SoC
test system has capability of supporting thousands of digital channels, with the
maximum data rate greater than 1Gbps, the vector depth exceeding 100 MB, the
10 ps grade accurate clock, the digital and analog signal resolution exceeding 20bits,
the bandwidth on the order of hundreds of MHz, and the RF signal frequency
exceeding 10GHz, which provides a solid foundation for high-end IC product
testing.

Analog/Mixed-Signal IC Test System

Analog/mixed-signal (AMS) IC test system is the automatic test system mainly

designed for analog IC and mixed-signal IC (mainly based on analog and
supplemented by digital) testing. The device under test mainly includes power
management devices (such as linear regulators, pulse width modulation controllers,
charging circuits, DC-DC converters, etc.), high-precision analog devices (such as
operational amplifiers, video and audio amplifiers, filters, phase locks, etc.), data
converters (such as analog-to-digital converters, digital-to-analog converters, etc.),
automotive electronics (such as power amplifiers, various types of drivers, etc.), and
discrete devices (such as MOSFETs, IGBTs, etc.).
At present, the major analog/mixed-signal IC test systems in the world include the
ETS series of Teradyne (including the former Eagle) from the USA, such as ETS88,
ETS364, and FLEX series of Teradyne, ASL1000 series of LTX-Credence from the
USA, STS8200 and STS8250 series of Beijing Huafeng AccoTEST, MTS737 and
MS7000 of Shanghai Macrotest, etc.
73 Integrated Circuit-Testing Equipment 1637

Fig. 73.5 The block diagram of the test system

Figure 73.5 is a functional block diagram of the AMS IC test system. The general
automatic test system includes a digital module, an Arbitrary Waveform Generator
(AWG) module, a Digitizer (DGT) module, a DC module, a Time Measurement Unit
(TMU), etc. The DC instrument and the TMU are usually included in an analog IC
automatic test system. It is usually necessary for the test system to contain other
modules, if the mixed-signal circuit needs to be tested.
The DC instrument is the major module in the AMS IC test system, which is also
called “V/I source (voltage and current source).” It usually has the four-quadrant
capabilities as shown in Fig. 73.6, which can generate both positive voltage and
current, as well as negative voltage and current. In addition, the module has the four
abilities of Force-Voltage/Measure-Current (FVMI), Force-Current/Measure-Volt-
age (FIMV), Force-Voltage/Measure-Voltage (FVMV), and Force-Current/Mea-
sure-Current (FIMI). The measurable indicators of DC instrument testing
capability include voltage and current range, precision, accuracy, measuring speed,
applying speed, transient response, ripple, and so on.
The analog waveform generator module is adopted to generate arbitrary analog
voltage waveforms that meet the test requirements. It usually adopts an Arbitrary
Waveform Generator (AWG) shown in Fig. 73.7, which is more flexible than a sine
wave generator or a function generator. The main characteristics of this module are
synchronous/asynchronous clock, triggering, wave filtering, real-time DSP, etc.
Usually, the module consists of a waveform source memory, a digital-to-analog
(D/A) converter converting the waveform data into an analog voltage, the program-
mable low-pass filter smoothing the stepped analog signal into a continuous
1638 Y. Jiang et al.

Fig. 73.6 The four quadrant

areas represent the current or
voltage value of the DC
module

Fig. 73.7 A typical structure of Arbitrary Waveform Generator

Fig. 73.8 A typical structure of Analog Waveform Digitizer

waveform, a Programmable-Gain Amplifier (PGA) modulating the signal level, the

single-ended-to-differential amplifier output, and a DC bias circuit.
Analog Waveform Digitizer, in contrast to the analog waveform generator,
converts the continuous analog waveform into the digital waveform, and the digi-
tized data will be stored in the waveform capturing memory unit. Figure 73.8 shows
a typical structure of Analog Waveform Digitizer. The programmable low-pass filter
on the input side is applied to limit the bandwidth of the input signal for reducing the
noise and preventing the signal aliasing. The programmable gain amplifier is applied
to modulate the signal level entering the Analog-to-Digital Converter (ADC) to
reduce the effects of noise caused by the quantization error of the ADC [3].
73 Integrated Circuit-Testing Equipment 1639

The traditional analog/mixed-signal IC test system needs a variety of different

function units to meet the requirement of the test resources above. At present, the
advanced test system integrates the function of source supplying, measurement, and
analysis in a single testing channel. It would update the testing conditions by the
dynamic control of test vectors, which extremely improve the efficiency of testing.

RF IC Test System

The RF IC test system based on the IC testing is the automatic test system mainly
designed for the RF circuits. The RF IC test system needs to cover the majority of the
RF devices, not only the low-end devices like RF amplifiers and RF switches, but
also high-end and complicated ones like the RF SoC as well. It needs to ensure that
multiple RF ports can be applied to test the device and cover most standard pro-
tocols, as well as meet digital, mixed-signal, power management, and other test
requirements. The current mainstream RF test systems include the V93000 of
Advantest and UltraFLEX of Teradyne of the ATE manufacturers.
The RF IC test system includes multiple independent RF subsystems with the
independent RF signal excitation for the testing and measurement capabilities. The
RF subsystem is mainly composed of RF front-end, RF signal source, and RF
receiver. The RF front-end has multichannel RF ports, which can simultaneously
output RF signals through the splitter, and support multichannel RF signal to be
simultaneously transmitted or measured. RF signal sources include synthesizers,
attenuators, multiplexers, amplifiers, and Arbitrary Waveform Generators (AWG)
for I/Q signal modulation, which could generate high-precision, low-noise,
low-distortion sine-wave signals, with the function of baseband I/Q signal modula-
tion, and can perform auto-leveling at each target frequency (amplitude auto-
calibration). In addition, the RF signal sources also can provide an extraordinarily
accurate signal, usually used as the clock or local oscillator signal of the device under
the testing. In order to keep a consistent timing relationship with the test system, the
frequency synthesizer is locked to a primary reference clock. The RF receiver
includes an attenuator, an intermediate frequency filter, a band pass filter, a high-
speed waveform digitizer, a high-precision waveform digitizer, a low-noise ampli-
fier, etc. The received RF signal is down-converted for capture and processing.
Figure 73.9 shows the block diagram of the RF IC test system.
The RF IC test system should support variety of common standard protocols and
customized protocol. The analysis software of the test system can provide the full
suite of demodulation and vector signal analyze tools and has the ability of fast
signal synthesizing and analyzing. In the process of testing, the test efficiency would
be improved if it enables multithreading for data upload and compute. That is, while
the test continues, a large amount of test data is uploaded from the test equipment to
the workstation through the dedicated high speed bus for data processing. In
addition, for RF IC test, the function of fast frequency and power conversion, as
well as the low background noise of the test system are also important factors.
1640 Y. Jiang et al.

Fig. 73.9 The block diagram of the RF IC test system

Customized Test Equipment

For mature mass production, the automatic test system has a complete standardized
solution. But for innovative semiconductor products with cost-sensitive and
forward-looking R&D requirements, large standard automatic test systems are
often not the optimal solution, so customized test equipment comes into being.
The customized test equipment designed for cost optimization strategies often
trades off in terms of versatility, flexibility, forward-looking, reducing development
difficulty, cycle, and cost. Test objects are only for specific semiconductor products
or types. For example, the test equipment based on system verification and basic
function verification has been widely adopted in cost-sensitive mass production
testing, which greatly reduces the test cost.
The customized test equipment designed for forward-looking R&D innovative
semiconductor products have multiways of realization. Modular test equipment
based on the universal open PXI platform combined with PXI and GPIB instruments
is an effective research and development solution. The STS series semiconductor test
solution from National Instruments (NI) is a typical case. A complete solution can be
formed by determining test requirements, selecting required instruments or modules,
building hardware and software architectures, interface components, and developing
software and hardware modules for the product test application. Other test
73 Integrated Circuit-Testing Equipment 1641

equipment companies such as Keysight and Rohde & Schwarz (R&S) have launched
customized test solutions, which are also widely adopted in the field of test verifi-
cation for terahertz, millimeter wave, radars, as well as high-speed and high-
precision products.
Different from the digital, analog/mixed-signal or system device testing, besides
the mature electrical test source, the highly concerned MEMS test equipment in
recent years requires more types of testing sources such as sound, light, magnetic
field, force, biology, etc. Due to the wide variety of MEMS products, customized
equipment is widely adopted. There are some typical applications for customized test
equipment, including high-G (gravitational) multiaxis equipment for acceleration or
gyroscope, small-scale test equipment for high-speed rotating head, microphone test
equipment, fully enclosed pressure test equipment, etc.

Test Instrument

Test instruments are often required in the IC test for auxiliary testing and analysis,
including rapid, high-quality testing in design verification, and mass production test.
Commonly adopted test instruments include multimeters, oscilloscopes, power
supplies, signal sources, and signal analyzers. Keysight, R&S, Tektronix, Fluke,
and other international mainstream manufacturers occupy most of the market of test
instruments.
During the IC test and verification, it often needs to use a multimeter, oscillo-
scope, signal analyzer, and other test instruments to confirm the voltage, current,
frequency, amplitude, phase, signal waveform, etc., so as to focus on the concrete
problem and have a deep analysis. Consistent and comparable results would be
obtained in the simulation, prototyping, and design verification phases to optimize
the IC design and speed up the market for IC products.
In the process of mass production test, when the device under test (DUT) has one
or more parameters beyond the capability of the universal ATE, the test instrument-
assisted ATE testing method would usually be adopted, in case the device under test
must have the high-precision power supply which the ATE cannot provide, or the
need to measure a higher voltage that exceeds the ATE range. From the perspective
of cost optimization, usually, the test instrument-assisted ATE testing method can
provide a cost-effective test solution. Compared with the universal ATE, special test
instruments often have the advantages of large range, high precision, and low noise
and also can support the computer-programming control. That is, the main control
computer of ATE connected to the test instruments through GPIB, USB, or other
interfaces can realize the automatic control by programs [4].
For IoT devices that have been highly regarded in recent years but still are very
cost sensitive, therefore, using the low-end ATE with plug-in of signal analyzers is
an effective low-cost test solution. In addition to conventional DC parameters and
functional tests, it can also directly measure the RF-related parameters such as signal
power, gain, harmonic distortion, phase noise, noise figure, error vector amplitude,
etc. It also can perform frequency domain, time domain, and modulation domain
1642 Y. Jiang et al.

signal analysis, so as to quickly verify the signal performance and complete the full
parameter test of the device [5].

References
1. H.Y. Gu, L.R. Zhang, Skillful application of BIN set in wafer testing. Electron. Test 8,
68–73 (2012)
2. Z.R. Zneg, Design and Verification of IC Time Parameter Measurement Unit Based on FPGA
(Dissertation, University of Electronic Science and Technology of China, Chengdu, 2012)
3. D. Wu, Calibration research on digitizer of IC test system. Comput. Digital Eng. 7, 56–59 (2012)
4. Z.P. Yuan, L.Y. Xiang, R.Y. Wang, Design and implementation of RF automatic test system for
micropower equipment in Internet of things. Mod. Sci. Technol. Telecommun. 9, 11–15 (2013)
5. K. Yu, The study of RFIC testing technology. China Integr. Circuit. 3, 41–46 (2015)
 Section IX
Integrated Circuits Materials
Deren Yang, Jingfeng Kang, and Xuegong Yu

Integrated circuit (IC) materials are used in IC manufacturing and are the basis of IC
industry. IC materials include two groups. One is for IC device fabrication itself
(e.g., Si wafers, plastic package materials); the other one is for consumption during
the IC manufacturing (e.g., polishing solutions, image agents). According to the
differences in functions and properties of materials, IC materials can be divided into
four types, i.e., functional materials (basic materials), micro-machining processing
materials, package and structure materials, and process-assisted materials.
IC technology was invented by Jack Kilby (TI) in 1958 and Robert Noyce
(Fairchild) in 1959 and was based on Si material. Single crystalline Si can be
grown by Czochralski technique using high purity polycrystalline Si as feedstock.
After wafer processing including grinding, cutting, lapping, and polishing, Si wafers
can be used for the fabrication of IC devices. Thus, Si wafers are the basic materials
for IC industry. Later, the epitaxial technology of Si and SiGe on polished Si
substrates was developed. In 1960s, buck single crystal and epitaxial layers of
compound semiconductor materials such as GaAs were applied. Meanwhile, on
the basis of IC device fabrication, micro-machining process materials, package and
structure materials, and process-assisted materials were also developed. In 1960s, IC
materials only included about 10 elements; however, in 2019, IC materials include
more than 60 elements applied in the IC production processes.
Currently, IC functional materials mainly are Si and compound semiconductor
materials. The former occupies more than 90% of the market shares. Micro-
machining process materials include photographic mask materials, photoresist mate-
rials, chemical-mechanical polishing materials, and physical vapor deposition mate-
rials. Package and structure materials mainly include lead-frame materials, package
materials, package substrate materials, inner lead wire materials, and bonding
materials. Process-assisted materials are high purity chemical reagents, high purity
gases, precision finishing materials, quartz products, etc.
1644 IX Integrated Circuits Materials

The quality of IC materials is a key for the fabrication of IC devices. Different

materials have to satisfy the requirements of IC devices. For example, functional
materials have to be in perfect crystal structure, less impurities, less defects, excellent
surface accuracy, etc. As IC devices continuously scaled, better quality of IC
materials is necessary in future such as much higher purity, more perfect crystal
structure, stronger mechanical strength, and easier to dissipate heat.
Silicon Materials
74
Deren Yang and Xuegong Yu

Contents
Requirements of Si Materials for ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
High-Purity Polycrystalline Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
Monocrystalline Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Amorphous Silicon Thin Film . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
Nano-Silicon Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
Monocrystalline Si Epitaxial Films . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
Silicon-on-Insulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
Smart-Cut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
Silicon Direct Bonding (SDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
Separation by Implanted Oxygen (SIMOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
SiGe Film on Si Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
Strained Si Film on Si Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
Carbon Nanotubes on Si Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
Graphene on Si Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
Light-Emitting Materials on Si Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663

Abstract
Si is the key material for IC manufacturing. This chapter demonstrates the basic
requirements of Si materials for ICs, from the raw polycrystalline Si to Si
epitaxial film. The control of impurities and defects during the crystal growth is
the most important topic, which gives a serious impact on the performance and
quality of Si materials. Meanwhile, the fabrication methods of other important Si
materials, including amorphous Si thin film, nano-Si, and Si-on-insulator, are also
addressed, which are used in various semiconductor devices. Moreover, the new
materials integrated with Si substrate, like SiGe film, strained Si film, carbon

D. Yang (*) · X. Yu
State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China
e-mail: mseyang@zju.edu.cn

© Publishing House of Electronics Industry 2024 1645

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_74
1646 D. Yang and X. Yu

nanotubes, graphene, and light-emitting materials, are illustrated, and they rep-
resent the future trend of IC materials.

Keywords
Polycrystalline silicon · Monocrystalline silicon · Nano-silicon materials · Silicon
epitaxial films · Silicon-on-insulator · SiGe film · Strained silicon film · Carbon
nanotube · Graphene

Requirements of Si Materials for ICs

CZ Si substrate is the basic material for IC manufacturing, which can be divided into
two groups, i.e., polished Si wafers and Si epitaxial wafers. Normal polished Si
wafer is p-type, (100) crystal orientation, resistivity in 3–6 Ω
cm, 8–12 Ω
cm,
15–25 Ω
cm, etc. The substrate of the frequently used Si epitaxial wafer is a heavily
boron-doped Si wafer. According to the type, integration, and technological condi-
tions of the devices, different Si materials should be selected for the manufacturing
of ICs. In general, polished Si wafers are used in the IC production lines with wafer
diameter of 200 mm and below, and epitaxial Si wafers are used in the 300 mm IC
production lines at 45 nm node and beyond. Polished Si wafers are manufactured
from CZ single crystal Si ingots by rolling, slicing, lapping, etching, polishing,
cleaning, and other processes.
The requirement of wafer quality parameters is increasing with the improvement
of advanced IC technology. The key parameters of Si wafer include resistivity and
radial uniformity, oxygen (O) concentration, carbon (C) concentration, body metal
and surface metal concentrations, oxidation-induced stacking fault (OSF) density,
bulk micro-defect density, site flatness, edge flatness and curvature, nano-
topography, surface particles, etc. Among them, the edge flatness and curvature,
and nano-topography are new requirements of Si wafers for advanced IC
technologies.
Impurities (except dopants) have an important impact on the performance and
quality of Si wafer. (1) Oxygen element (as O) is an unavoidable impurity in CZ Si
wafer, and oxygen atoms in interstitial sites can improve the mechanical strength of
Si wafer. In addition, oxygen atoms can react with silicon atoms to form solid SiOx
precipitates inside the silicon. The proper amount of SiOx precipitates inside Si wafer
can absorb harmful metal contaminants of Si wafer through the gettering mecha-
nism, but excessive SiOx precipitations can cause warpage of Si wafer. Therefore, it
is necessary to control the oxygen content in Si wafer within a reasonable range.
(2) Carbon element (as C) is also an inevitable impurity in CZ Si wafer. For a long
time, C has been considered as a harmful impurity because of its effect on increasing
leakage current and decreasing breakdown voltage of pn junction due to enhanced
precipitation of SiOx. Therefore, the concentration of C is required to be controlled
below 1016 cm3. However, with the decrease of oxygen content in Si wafers for
advanced ICs, the so-called harmful problem of C needs to be reevaluated.
74 Silicon Materials 1647

(3) Nitrogen (N) is a deliberate impurity in Si wafer. It has the advantages of

enhancing the mechanical strength of Si wafer, increasing the ability of intrinsic
gettering, and making the void defects easier to be eliminated. After nearly 30 years
of R&D, N-doped Si wafer has become a kind of Si wafers with excellent perfor-
mance for ICs. (4) Metal impurities are harmful both on the surface and inside the
body of Si wafers. They reduce the carrier lifetime of Si wafer and induce other
defects (e.g., OSFs). Therefore, metal impurities must be eliminated as much as
possible.
Defects in Si wafers have important impacts on the yield of ICs. The main defects
of polished Si wafer include SiOx precipitates, oxidation-induced stacking faults
(OSFs), void defects (void), etc. [1]. The oxygen concentration in Si wafer is
supersaturated at IC manufacturing temperature. After several low- and high-
temperature processes, SiOx precipitates and induced defects (e.g., dislocations
and stacking faults) can be formed. According to the process characteristics of IC
manufacturing, by controlling the oxygen concentration and thermal history of Si
wafer (i.e., related to the growth process of Si crystal), SiOx precipitates can occur
only in the Si wafer body (i.e., below the active region of IC device) for forming bulk
micro-defects (BMD) and playing a role of internal gettering (i.e., the removal of
metal contamination on the surface of Si wafer). OSF is a defect that may occur when
Si wafer is oxidized at 900–1150  C. The surface damage of Si wafer, metal
contamination, excessive oxygen concentration, and grown-in O precipitations in
Si wafer can lead to OSFs. Therefore, the density of OSFs is an important index to
measure the quality of Si wafers.
Void defects, as primary grown-in defects of Si wafer, are formed by the accu-
mulation of vacancy in the cooling process of Si crystal growth and will reduce the
gate oxide integrity of MOS devices. The void defect will appear as crystal-
originated particles (COP) after the Si wafer is cleaned by RCA1 cleaning solution.
In order to eliminate COP in the near surface area of Si wafer (i.e., working area of
IC devices), high-temperature annealing process (about 1200  C) in hydrogen (H) or
argon (Ar) atmosphere is usually adopted. In addition, the perfect Si crystal without
COP can be grown by a special crystal growth process. Table 74.1 lists the main
requirements for Si wafers in the manufacturing process of 28 nm ICs.

High-Purity Polycrystalline Silicon

Integrated circuits (ICs) are on the base of single crystal Si. The raw material is high-
purity polycrystalline Si (or poly-Si) with the purity of 99.999999~99.9999999% or
even higher. According to the purity or application, poly-Si can be defined to be
detector-grade, electron-grade, and solar-grade for using as raw materials for detec-
tors, ICs, and solar cells, respectively. In general, the poly-Si used for solar cells can
be relatively lower purity, while for ICs, it is much more pure, with impurities as low
as ppba (parts per billion atoms). Moreover, poly-Si can be also divided into two
types of rod-like and granular according to the difference of shape and production
processes.
1648 D. Yang and X. Yu

Table 74.1 28 nm IC manufacturing process requirements for Si wafer

Silicon wafer parameters Specifications
General Growth method CZ, MCZ
characteristics Crystal orientation (100)
Electrical and Conductivity type P
chemical properties
Electrical and Resistivity, RRG 8–12 Ωcm, 8%
chemical properties Oxygen concentration, ROG 10–14 ppma, 8%
Structural Carbon concentration 0.18 ppma
characteristics
Minority carrier lifetime 600 μs
Bulk Fe, Ni, Cu maximum 4  1010 at/cm3, 1  1010 at/cm3,
concentration 1  1010 at/cm3
Structural Slip line None
characteristics OSF 100 ea/wafer
Machining BMD 1  107 – 6  109/cm3
characteristics
Machining Diameter 300 mm  0.1 mm
characteristics Thickness 775  15 μm
Front surface TTV 0.7 μm
requirements
Bow 30 μm
Machining Warp 25 μm
characteristics SFQR (26 mm  8 mm) 0.03 μm@PUA100%
Front surface ESFQR (EE ¼ 2 mm) 100 nm
requirements
Front ZDD@148 mm 60 – +15 nm/mm2
Nano-topography (2 mm  2 mm, 9 nm, 24 nm
10 mm  10 mm)
Front surface Surface metal (Na, Al, Ca, K, Fe, 3.5  109 at/cm3
requirements Cr, Cu, Ni, Zn)
Scratches, cracks, and None
contamination
LPD  0.2 μm, 0.12 μm, 0.045 μm 8 ea./wafer, 20 ea/wafer,
105 ea/wafer
Epitaxial Conductivity type P
characteristics Doped elements Boron
Epitaxial resistivity 8–12 Ωcm
Radial variation of epitaxial 5%
resistivity
Epitaxial layer thickness 4  0.2 μm
Radial variation of epitaxial layer 5%
thickness
Notes: 1 ppma ¼ 5.02  1016 cm3

The raw material of high-purity poly-Si is quartz mine with the purity of higher
than 99%. In electric arc furnaces, the quartz interacts with carbon at about 1800  C
to generate metallic Si or metallurgical Si with a purity of 95%~99% by reduction
action. However, for electronic industry, metallic Si contains much more nonmetal
74 Silicon Materials 1649

impurities (e.g., B, P, C, etc.) or metal impurities (e.g., Al, Fe, Cu, etc.). Therefore,
metallic Si is usually used as additive agents in steel industry or plastics industry.
By further purifying metallic Si, high-purity poly-Si can be resulted and used as
feedstock to form single crystalline Si for IC or photovoltaic industry. In general, the
phosphorous (P) concentrations and the boron (B) concentrations in high-purity
poly-Si should be below 0.15 ppba and 0.05 ppba, respectively, while the metal
concentrations less than 1.0 ppba, and the C concentrations less than 0.1 ppma.
There are many different processes to produce high-purity poly-Si. However,
considering the cost, energy consumption, quality, etc., the trichlorosilane (SiHCl3)
reduction process and the silane (SiH4) thermal decomposition process have been
adopted by IC industry to produce poly-Si. (1) The trichlorosilane reduction process,
also referred to as the modified Siemens process, is widely accepted as the main
technique which produces more than 80%~90% poly-Si in the world. This process
uses chlorine hydride (HCl) to interact with metallic Si to first form trichlorosilane
(SiHCl3). By means of multistep rectification, high-purity SiHCl3 is achieved. Then,
the SiHCl3 is put into a reduction furnace and interacts with high-purity hydrogen
(H2) at about 1100  C. In the reduction furnace, the generated high-purity poly-Si is
deposited on the poly-Si cores with the diameter of ~5 mm. Finally, the electronic-
grade poly-Si rods with the diameter of 150–200 mm are formed. (2) The silane
(SiH4) thermal decomposition process is to use SiH4 as an intermediate compound,
which is easy to purify and can be thermally decomposed to poly-Si at relative lower
temperatures. SiH4 can be produced by the interaction of Mg2Si and liquid ammonia
chloride (NH4Cl) or disproportionation of SiHCl3. After multistep rectification,
high-purity SiH4 is put into a reaction furnace where the high-purity poly-Si cores
are heated to above 850  C. Then, SiH4 molecules are decomposed to form SiH2
precursors which are absorbed on the poly-Si core surface to form the poly-Si
deposition on the cores, so that the rod-like poly-Si is formed. If SiH4 is put into a
fluidized bed chamber, it is thermally decomposed on the surface of Si particles as
nuclei. Finally, high-purity granule Si with the diameter about millimeters (mm) is
formed, which is good as feedstock for continuous-charge Czochralski (CZ) crystal
growth technique.

Monocrystalline Silicon

Monocrystalline Si (mono-Si), also called as single crystalline Si, is one kind of

crystalline Si grown on the basis of one single crystal seed. The material possesses
the advantages of perfect crystal lattice, less defects and impurities, and is the basic
material for IC industry. There are two kinds of monocrystalline silicon, namely
float-zone Si (FZ-Si) and Czochralski Si (CZ-Si), depending on the crystal growth
methods. (1) FZ-Si is grown by the float-zone technology, is less machining prop-
erty, and usually is used for wafers less than 200 mm in diameter. The feedstock of
FZ-Si is rod-like high-purity poly-Si. At its bottom of poly-Si rod, a mono-Si seed
with orientation of <100> or <111> is placed. In vacuum or Ar ambient, a radio
frequency reduction coil is placed around the junction of the poly-Si rod and the
1650 D. Yang and X. Yu

seed. Then, the junction portion is molten and becomes a melting zone after heating.
By moving the reduction coil upward along with the poly-Si rod, the melting zone
also moves up. The lower portion of the melting zone is gradually solidified and
becomes mono-Si on the top of the seed. When the coil moves up to the top end of
the rod, the whole poly-Si rod becomes a mono-Si ingot. Meanwhile, impurities will
segregate on the bottom end or the top end of the ingot due to segregation effect.
Thus, the FZ technology not only can produce mono-Si but also purify Si. By using
multistep FZ technology, ultrapure mono-Si can be prepared for detectors. (2) CZ-Si
with the orientation of <100> or <111> is grown by CZ technology as shown in
Fig. 74.1. It can be seen that the outer portion of the furnace is the thermal insulating
layer, and the inner portion is the graphite heater. In the lower portion, the graphite
bracket is put on a fixed holder and can be rotated and moved upwards or down-
wards. Inside the bracket, a quartz crucible is used. In the upper part, a seed shaft can
also be rotated and moved upwards or downwards. All of the components in the
furnace, including graphite and quartz, should be purified so as to reduce impurity
concentrations in CZ-Si. During crystal growth, high-purity Ar gas is usually used as
a protective gas in the furnace. Sometimes, nitrogen gas is also used as the protective
gas.
The main processes for the manufacturing of CZ-Si include poly-Si charge, poly-
Si melting, seeding, necking, shouldering, growth, and ending. Based on the above
main processes, the advanced CZ-Si growth techniques such as magnetic field
Czochralski Si (MCZ-Si), repeated charge Czochralski Si (RCZ-Si), continuous
charge Czochralski Si (CCZ-Si), etc., are developed.

Fig. 74.1 Crystal growth

diagram of Czochralski Si
(CZ-Si) [1]
74 Silicon Materials 1651

The conduction type and resistivity of CZ-Si are the basic parameters. During
crystal growth, dopants offering electrons and holes are doped into Si crystal so as to
satisfy the requirements of IC devices. For p-type CZ-Si, III group elements (e.g., B,
Al, Ga, and In) can be used as dopants, while for n-type CZ-Si, V group elements
(e.g., P, As, and Sb) can be used. For practical applications, the concentration and
distribution of dopants in the crystal ingots should be considered. It is clear that the
segregation coefficient and evaporation coefficient of dopants in molten Si are also
important parameters. Thus, in IC industry, the dopant for p-type CZ-Si generally
is B, while the dopants for n-type CZ-Si are P, As, and Sb.
For the CZ-Si used for IC devices, the minor carrier lifetime is another important
electric parameter. During the manufacture of CZ-Si, in general, any impurities
except for dopants should be avoided. Otherwise, the behaviors and quality of
CZ-Si and their devices are seriously deteriorated. However, O and C impurities
are hard to be completely avoided because they originate from quartz crucibles and
graphite heaters during crystal growth. Therefore, the control of O and C concen-
trations is very important to improve the quality of CZ-Si. Moreover, micro-defects
are another important factor to influence on the quality of CZ-Si and directly reduce
the reliability and yield of devices. For the CZ-Si used for ultra-large-scale ICs
(ULSIs), the main defects are crystal-originated particles (COPs), which should be
reduced and controlled during the crystal growth. To control the defects, the quality
of CZ-Si can be improved by doping nitrogen (N) and germanium (Ge) atoms,
known as “impurity engineering” [2].
After crystal growth of CZ-Si ingots, the processes including truncation, round-
grinding, cutting, lapping, chamfering, polishing, clean, and so on will be carried
out. In final, polished CZ-Si wafers with superfine surface and less metal concen-
trations on the surfaces are prepared for IC industry.

Amorphous Silicon Thin Film

Amorphous silicon (as α-Si) is the Si material consisting of Si atoms randomly

distributed in a disordered network. Compared with mono-Si, α-Si has different
behaviors and contains huge amount of dangling bonds. Its physical property is
isotropic, and its absorbance is one order of magnitude higher than mono-Si. In
general, its quasi-direct bandgap width is adjustable between 1.4 and 2.0 eV by
doping or alloying. After hydrogenation, the bandgap width of α-Si:H is about
1.7 eV. Amorphous silicon is usually formed as thin film. In contrary to crystalline
Si, α-Si has higher lattice potential energy and is in thermodynamic metastable state.
After heat treatment, α-Si thin film can be transformed to nano-Si, micro-Si, or even
poly-Si thin films. By changing the components of alloy or the concentrations of
dopants, its conductivity, bandgap width, and other properties can be adjusted, and
even α-SiGe or α-SiC alloy thin films can be formed.
The fabrication process of amorphous Si (as α-Si) is relatively simple and easy to
be in mass production. Amorphous silicon can be used to produce thin film transis-
tors (TFTs), display devices, solar cells, and so on. As for solar cells, α-Si can be
1652 D. Yang and X. Yu

deposited on flexible substrate (e.g., stainless steel, plastics, etc.); therefore, α-Si
solar cells can be integrated with building directly. However, compared with crys-
talline Si solar cells, α-Si solar cells have lower efficiency and stronger light-induced
degradation due to the disordered lattice structure. [3]
Amorphous silicon can be generated by chemical vapor deposition (CVD) or
physical vapor deposition (PVD) techniques. However, the α-Si generated by
sputtering or other PVD techniques contains too much dangling bonds and
structure defects. It is difficult to dope dopants to form n-type or p-type semi-
conductor materials. Therefore, CVD techniques (e.g., plasma enhanced chemi-
cal vapor deposition (PECVD), hot-wire chemical vapor deposition (HTCVD),
photo-assistant chemical vapor deposition (photo-CVD), etc.) are widely used to
produce α-Si thin films. In industry, the dominate technique to produce α-Si thin
film is PECVD. In the PECVD process, high-purity SiH4 gas with H2 gas is
delivered into the reaction chamber. After thermal decomposition, amorphous Si
thin film is deposited on substrates as shown in Fig. 74.2. It is also possible to use
other gases as Si sources, such as SiHCl3, to generate amorphous Si by chemical
vapor reaction.
Amorphous silicon produced by CVD technique still contains large number of
structure defects, especially Si dangling bonds and Si-Si weak bonds. Si dangling
bonds induce high-density deep level centers in the bandgap of α-Si, which possess
electrical activity and have serious influence on the electrical property. During heat
treatments in the manufacture of devices, the density and structure of dangling bonds
will change so that it is difficult to control the electrical property of α-Si. To resolve
this problem, a high concentration of hydrogen (H) is doped and results in the
hydrogenated amorphous silicon (α-Si:H). For example, the α-Si thin film produced
by PECVD generally contains 10%~15% H atoms. However, if the doped high
concentration H is much higher than the dangling bonds, then there are H-related
defects in α-Si thin film devices, resulting in the deterioration of properties.

Fig. 74.2 Diagram of α:Si thin film fabrication by PECVD

74 Silicon Materials 1653

Nano-Silicon Materials

With the size in the range of 1–100 nm, Si materials are referred to as nano-silicon
(nano-Si), e.g., Si nanoparticles (quantum dots), Si nanowires, Si nanotubes, Si
nano-belt (nano-sheet), etc. Nano-Si materials are currently hot topics in the world
because of their unique electro-optic properties, non-toxicity, and compatible with
ULSI process. In future, nano-Si can be used in ULSI, bio-image, lithium battery,
solar cell, light emit diode (LED), detector, and so on.
Usually, different structures of nano-Si materials produced by different methods
have various properties and applications. (1) Si nanoparticles (Si quantum dots):
Si nanoparticles have two kinds, i.e., freestanding nanoparticles or embedded into
matrix thin film (e.g., SiO2, Si3N4, etc.). While the size is smaller than the Bohr
radius of exciton (~4.9 nm), nano-Si particles have obviously different behaviors
from bulk Si due to quantum confinement, surface, and multi-exciton effects. For
example, the carrier movement in Si nanoparticles will be restricted because of their
quantum confinement effect. Moreover, with the decrease of sizes, the energy
bandgap becomes wider. Freestanding Si nanoparticles could be produced by Si
powder ball milling and chemical and physical methods. Among them, the thermal
decomposition of SiH4 is the main technique. By the assistant of laser, cool plasma,
and aerogel at high temperatures, mass production of freestanding Si nanoparticles
can be realized. Si nanoparticles embedded in matrix can be fabricated by laser
ablation, sputtering deposition, PECVD, reactive vaporization, and other techniques.
For example, during the fabrication of SiO2 thin film, α-Si is simultaneously
deposited. After annealing, the α-Si converts to Si nanoparticles embedded in SiO2
matrix. (2) Si nanowire: Si nanowires can be used as structural units for IC nano-
devices, solar cells, biosensors, and chemical sensors. Si nanowires can be fabricated
by different techniques (e.g., physical vaporization, physical sputtering, physical
etching, CVD, chemical etching, chemical solution, etc.). Among them, CVD and
chemical etching are the main methods. For the Si nanowires produced by CVD
method, they can be formed on Si substrates with Fe/Cu/Ni/Au or other metal as
catalysts through the decomposition of SiH4 and SiCl4 gases at higher temperatures.
Based on the growth mechanism of vapor-solid-liquid (VSL) mode, the diameter and
length of Si nanowires can be controlled by the concentration and flux of SiH4 and
other Si source gases, reaction temperatures, reaction time, particle sizes of metal
catalysts, and so on. Chemical etching method is to put mono-Si wafers into the HF
solution with noble metal ions, or put the metal (Au, Ag, etc.) deposited mono-Si
wafers into HF solution with oxidizing agents (FeNO3, H2O2, etc.). After selective
corrosion on Si wafer surface, large area and directional Si nanowire arrays can be
produced. (3) Si nanotube: Si nanotubes are also worked as building blocks for IC
nano-devices. They have much higher carrier mobility in comparison with bulk Si or
even Si nanowires, because they have larger specific surface area and special ballistic
transport characteristics of carriers. Thus, Si nanotubes not only have broad appli-
cation prospects in IC industry but also in lithium battery, sensors, etc. Unlike the
layer structure of carbon, Si belongs to diamond structure, and it is difficult to form
nanotubes. Thus, templates must be used in order to generate Si nanotubes. One
1654 D. Yang and X. Yu

method is to use an Al2O3 template with nano-holes. By the decomposition of SiH4

and the assistance of metal (e.g., Au) catalyst, Si nanotubes can be formed on the
inner wall of the nano-holes inside the template. After removing the template, Si
nanotubes can be obtained. The other method is to use ZnO nanowires or other
nanowires as “soft template.” After the formation of ZnO nanowires, α-Si layer or
poly-Si layer will be deposited on the outer surface of the wires by means of
chemical synthesis, CVD, physical sputtering, etc. Then, ZnO nanowire templates
are removed by chemical etching or laser ablation technique to obtain Si nanotubes.

Monocrystalline Si Epitaxial Films

Mono-Si (as single crystalline silicon) epitaxial films can be grown on the surface of
mono-Si polished wafers with specific thickness and resistivity. These mono-Si
epitaxial films have the same crystal orientation as the Si substrates and form a
continuous monocrystalline structure. However, some parameters of mono-Si epi-
taxial films, such as conductivity, thickness, and resistivity, can be different from the
substrate according to specific requirements. Mono-Si epitaxial films can be a single-
layer or multilayer structure. Mono-Si epitaxial films are commonly grown by
chemical vapor deposition (CVD) technique in epitaxial reactors. The process
involves placing mono-Si substrates onto a graphite susceptor, heating the susceptor
up to required temperatures using high frequency inductive coil or using IR heating
lamps, and then introducing reactive gases into the epitaxial reactor using hydrogen
as a carrying gas. Gaseous Si-containing compounds referred as stock gas (e.g.,
SiCl4, SiHCl3, SiH2Cl2, and SiH4) react on the substrate surface to form a mono-Si
epitaxial film. A comparison of stock gases for mono-Si epitaxial films is in
Table 74.2.

Table 74.2 Comparison of stock gases for monocrystalline Si epitaxial films

Stock gases SiCl4 SiHCl3 SiH2Cl2 SiH4
Boiling 57.6 31.8 8.3 112
point ( C)
Chemical SiCl4 þ 2H2 ¼ Si þ SiHCl3 þ H2 ¼ Si þ SiH2Cl2 ¼ Si þ SiH4 ¼ Si þ
reaction 4HCl 3HCl 2HCl 2H2
formula
Reaction 1150 ~ 1200 1050 ~ 1180 750 ~ 1150 550 ~ 1000
temperature
( C)
Growth rate 0.4 ~ 1.0 0.4 ~ 2.0 0.4 ~ 3.0 0.1 ~ 0.5
(μm.min1)
Remarks Suitable for thick Suitable for atmospheric Suitable for Suitable for
epitaxial films pressure epitaxial film low-pressure thin epitaxial
preparation and thin films
epitaxial film
preparation
74 Silicon Materials 1655

In order to control the conductivity type and resistivity of the mono-Si epitaxial
films, dopants must be introduced into the CVD system during epitaxial films
deposition process. Diborane (B2H6) is commonly used as p-type dopant gas, and
phosphine (PH3) and arsine (AsH3) are commonly used as n-type dopant gases. After
entering the epitaxial reactor, the dopant gases will be decomposed at high temper-
atures to form dopant atoms (e.g., P, As, and B atoms). Similarly, both Si atoms and
dopant atoms will bind to the Si substrate surface through surface adsorption and
interatomic adsorption, and eventually migrate and diffuse to the most stable sites
(with lowest energy) to facilitate the doping and deposition of mono-Si epitaxial
films. Key parameters of mono-Si epitaxial films include conductivity type, resis-
tivity and uniformity, thickness and uniformity, transition layer thickness, buried
layer epitaxial pattern distortion and pattern shift, epitaxial wafer flatness, disloca-
tion density, slips, haze, stacking faults and pits, etc.

Silicon-on-Insulator

SOI refers to a mono-Si film on an insulator material. Figure 74.3 shows the
schematics of MOS transistor structures on SOI substrate and bulk Si substrate,
respectively. MOS transistors made on SOI materials take advantage of the dielectric
isolation effect derived from the isolation material with respect to the top mono-Si
film. Compared to transistors on bulk Si wafers, transistors on SOI substrates have
considerably lower source-to-drain capacitance, higher speed, and lower power
consumption. Moreover, SOI transistors have unique features in anti-radiation
(insensitive to soft errors caused by α particles or cosmos radiation), high-
temperature resistance (operating temperature up to 300  C), and free from the
reduction of electric current driving capability and subthreshold fluctuations, there-
fore demonstrate excellent performance in low voltage and low power circuit
applications. Nowadays, CMOS technologies based on SOI have been widely
used in the fabrication of high-speed IC products (e.g., SOI microprocessors,
DRAMs, static memories, RF and logic circuits, etc.).
The key to SOI material preparation technology is to form a high-quality mono-Si
film with almost no defect on the insulator. One approach is utilizing insulating
materials (e.g., quartz, glass, or monocrystalline Al2O3 as substrate) to grow a mono-

Fig. 74.3 Schematic of MOS transistor structures on (a) bulk silicon material and (b) SOI material
1656 D. Yang and X. Yu

Si film there by a high-temperature epitaxial process. However, due to the crystal

lattice mismatch and the differences of thermal expansion coefficient between Si and
substrate materials, there are high-density defects in the Si film, which lead to
significant degradation of carrier mobility and lifetime near the interface between
Si and insulator, thus affecting device performance.
There are many techniques for the preparation of SOI based on Si substrate, such
as zone-melting recrystallization (ZMR), full isolation by porous Si (FIPOS), epi-
taxial layer transfer (ELTRAN or EL-TRAN), epitaxial lateral overgrowth (ELO),
smart-cut, silicon direct bonding (SDB) and separation by implanted oxygen
(SIMOX), etc. So far, smart-cut, SDB, and SIMOX are the most promising
approaches for SOI preparation.

Smart-Cut

It combines ion implantation and wafer bonding techniques and includes four steps
as shown in Fig. 74.4. First, 5  1016 cm2 H ions are implanted into the region near
surface of oxidized Si wafer (defined as source wafer) to form a bubble layer at the
depth of implantation. Then, the hydrophilic source wafer is bonded with another
oxidized Si wafer (defined as handle wafer). Thereafter, the bonded wafers are
subjected to two annealing steps. The first annealing temperature is about 500  C,
both the size and the internal H pressure of voids located at the bubble layer of source
wafer will increase during the annealing process, leading to the complete split of
source wafer along the bubble layer. The second annealing temperature is about
1100  C, and the purpose of the second annealing step is to enhance the bonding
between handle wafer and SOI film. Finally, the surface of SOI film is polished by a
chemical mechanical polish (CMP) process.

Fig. 74.4 Schematic of smart-cut technique process

74 Silicon Materials 1657

Silicon Direct Bonding (SDB)

The hydrophilic treatments is performed on a polished Si wafer with a certain

thickness of thermally grown surface SiO2 layer and another polished Si wafer
with a hydrophilic surface SiO2 layer, so that the two wafers are bonded together
by their surface -OH bonding (hydrophilic bonding). Finally, the bonded Si wafers
are annealed at high temperatures (700–1100  C) in N ambient to initiate dehydra-
tion reaction at wafer interface and form Si–O–Si bonding, achieving complete
bonding between the two Si wafers. After wafer bonding process, the top Si wafer
(SOI film) must be thinned to several micrometers (um) or less in order to meet the
application requirements of SOI devices, as shown in Fig. 74.5. Commonly used
wafer thinning methods are CMP process after the grinding and chemical etching
process.

Separation by Implanted Oxygen (SIMOX)

A high dose of O+ ions is implanted into mono-Si wafer surface with certain depth,
then the buried oxide (BOX) is formed and made dense and stable by a high-
temperature annealing. The high-temperature annealing can also repair defects
damaged by ion implantation and restore the integrity of Si crystal lattice, as
shown in Fig. 74.6. During O+ ion implantation at high temperatures, O+ ions will
pass through the top layer of Si wafer and form defects therein. Most of

Fig. 74.5 Schematic of SDB technique process

Fig 74.6 Schematic of

SIMOX technique process
1658 D. Yang and X. Yu

noncrystalline defects can be repaired at high temperatures (self-repairing) to keep

the top Si layer monocrystalline, but many defects still exist in top Si layer.
Therefore, the high-temperature annealing (1300  C) after O+ ions implantation is
necessary to improve the quality of the top Si layer and BOX. Commercial SOI
materials with a diameter of 200–300 mm and the dislocation density <103 cm2
can be achieved by SIMOX technique.

SiGe Film on Si Substrate

SiGe film on Si substrate refers to SiGe epitaxial alloy layer grown on Si substrates.
Early research on Si substrate-based SiGe materials aims to improve the transistor
performance. In heterojunction bipolar transistor (HBT) devices made from SiGe
film on Si substrate, the SiGe layer serves as the base region. Due to the 4% lattice
parameter difference between Ge and Si, misfit-induced stress exists at Si1-xGex/Si
interface. In HBT devices, x is in the range 0.15–0.25, and the epitaxial layer
misfit dislocation density can be higher than 106 cm2. To solve the problem of
high misfit dislocation density, the thickness of epitaxial layer must be controlled
below a critical value.
By introducing Ge into Si epitaxial film, the energy bandwidth of HBT base
region is narrowed, thus significantly improving the electron injection efficiency.
Moreover, SiGe base area can be highly doped (dopant concentration ~1019 cm3) to
achieve a very thin base width (several 10’s of nm) and thereby drastically shorten
the electron passing time through the base region. The device speed can be greatly
improved (with highest working frequency up to 300 GHz) with much lower noise
and power consumption than comparable devices made on Si epitaxial films.
Therefore, devices based on SiGe films fabricated on Si substrate are especially
suitable for applications for high efficiency power amplifier, low phase noise
oscillator, wide band amplifier, etc.
Molecular beam epitaxy (MBE) and chemical vapor deposition (CVD) are two
most widely used techniques of SiGe film materials on Si substrate. MBE techniques
include solid phase MBE and gas phase MBE. SiGe film on Si substrate is prepared
mainly by solid MBE approach, which is a physics process involving the evapora-
tion of Si and Ge atoms. The main process is to vaporize solid Si and Ge sources by
using high energy of electron beam under a high vacuum ambient, and then the SiGe
film is deposited on Si substrate. Compared with CVD technique, MBE technique
has the advantages of low temperature, precise doping control, and high quality of
materials. However, it requires complicate equipment and the high vacuum ambient,
and the efficiency is low for mass production.
There are many methods to prepare SiGe film on Si substrate by CVD technique.
Commonly used methods include low-pressure CVD (LPCVD), rapid thermal
annealing CVD (RTP-CVD), ultrahigh vacuum CVD (UHV-CVD), etc. The process
theory is to deposit SiGe film on Si substrate through the reduction of gas phase
hydride of Si and Ge. So far, the advanced strained SiGe material preparation
techniques are selective epitaxial UHV-CVD and RTP-CVD.
74 Silicon Materials 1659

The device process of HBT using SiGe film on Si substrate is compatible with the
mature Si IC process, therefore low manufacturing cost and high integration can be
achieved. Starting from HBT, devices using SiGe film on Si substrate are becoming
mainstream with SiGe BiCMOS and have rapidly developed toward <90 nm CMOS
and system-on-chip (SoC) integration process, demonstrating applications in high
performance and high-speed ICs.

Strained Si Film on Si Substrate

The strain layer technique is one of many methods to improve mobility of electrons
and holes in the channel of Si MOSFET devices. Under high level of strains, the
mobility of electrons and holes can be improved twice and 2.5 times, respectively.
The strained Si film on Si substrate is an epitaxial mono-Si film grown on a relaxed
SiGe chemical compound. The lattice of strained Si film is “stretched” in direction
parallel to the substrate. By growing SiGe thin film and single silicon thin film on the
single silicon substrate successively, the strained silicon thin film on the silicon
substrate was prepared, as shown in Fig. 74.7.
When SiGe film is grown on the mono-Si substrate, the Ge content is normally
20–30%. Because Ge atoms are larger than Si atoms, the lattice constant of SiGe is
larger than that of Si. With the increase of Ge content, the compressive stress of SiGe
film along substrate direction also increases accordingly. When the SiGe film
thickness is below a critical thickness, the SiGe film is always under a state of
compressive stress. When SiGe film thickness exceeds a critical thickness (usually
several microns), stress relaxation occurs among atoms, resulting in the formation of
a large amount of crystal lattice misfit dislocations. So, stress is released and SiGe
film is relaxed. The critical thickness is the maximum film thickness to maintain
material stability and is an important parameter to characterize the hetero-epitaxial
materials.
When mono-Si film with thickness 1–20 nm is epitaxially grown on the relaxed
SiGe film, due to the fact that the lattice constant of SiGe is larger than that of Si,
mono-Si film is subjected to a tensile stress along the substrate direction, as shown in
Fig. 74.8. The tensile stress can cause the splitting of Si energy band, thus changing
the scattering of Si energy valleys, decreasing the effective mass, and increasing
carrier mobility. By changing the thickness of mono-Si film connecting with SiGe
layer, the stress and related properties of Si film can be controlled and adjusted.
Usually, the thickness of epitaxial mono-Si film is below the critical thickness in
order to induce stress.

Fig. 74.7 Schematic of

strained Si film on Si substrate
structure
1660 D. Yang and X. Yu

Fig. 74.8 Schematic of strained Si film lattice on Si substrate

Fig. 74.9 Schematic of MOSFET structures on strained silicon film

By utilizing strained Si film on Si substrate, the channel of MOSFET device can

be strained so that the carrier mobility can be improved considerably, as shown in
Fig. 74.9. The advantages of such method are that the strained channel of both
pMOS and nMOS can be used simultaneously, and the performance of both pMOS
and nMOS can be improved simultaneously.

Carbon Nanotubes on Si Substrate

Carbon (C) nanotube [4, 5] is an attractive material, which has good electrical
conductivity and variable energy band structure depending on the tube diameter. It
has very good prospective applications in semiconductor industry. The first transistor
based on a single C nanotube is successfully fabricated in 1998. Recently, the
transistor with a channel width smaller than 10 nm has been achieved by C nanotube.
Under an operation voltage of 0.5 V, the current density of C nanotube-based FET
74 Silicon Materials 1661

along the radius direction is five times as large as the Si FET, and the corresponding
on-to-off ratio can reach 105.
At this moment, the basic research on the combination of C nanotube with Si
material to fabricate the devices is still going on. The direct contact of C nanotube
and Si forms a heterojunction with rectification characteristic, which can be used for
the fabrication of diodes and optoelectronic detectors. The Si-based C nanotube can
also be used for nonvolatile random-access memory (NVRAM, or NVM). In the
NVRAM, the memory unit is composited of two nanotube layers that are perpen-
dicular to each other, where the distance between the nanotube layers can be
modulated by an electrostatic field to produce high or low resistances. Meanwhile,
the C nanotubes can be used as the interconnection for ICs. By inserting arrays of C
nanotubes into the via hole, the resistance of via hole can be reduced to less than
10 Ω
cm and the power consumption of interconnects is reduced too. Moreover, in
contrast to Cu filling technology, the formation of C nanotube array contact is very
simple and will not cause the metal contamination problem. Based on these tech-
nologies, the full-functional and parallel process capable Si-based C nanotube
processor can be achieved through the circuit design to avoid the related defect
issues. The C nanotubes can be used as the functional units in various areas of Si
technology from interconnect to processing units. Nowadays, the device feature size
of Si-based ICs has already entered into the era of 10 nm technology. The further
reduction of device size presents significant challenges. One way to extend Moore’s
law is to combine the C nanotube with the Si technology.

Graphene on Si Substrate

The direct contact between graphene and Si can form Schottky junctions that can be
used as a fabrication method for diodes and photodetectors [6]. The Schottky
junction of graphene-Si has good rectification characteristics, but its optoelectronic
responsivity is very weak. Since graphene has the feature of intrinsic semimetal, the
on-off ratio of transistor is relatively lower. Currently, there are two ways to solve
this problem. (1) To modulate the work function of graphene by gate voltage to
increase the potential barrier at the graphene-Si interface and achieve the on-off ratio
of transistor ~105. This kind of device structure overcomes the disadvantage of the
no-bandgap of intrinsic graphene and shows the prospective application of
graphene-Si electronic devices. (2) To fabricate the graphene nano-belt structure
with energy bandgaps. The experimental results indicate that the transistor based on
graphene nano-belt with a width of 30 nm can achieve an on-to-off ratio of 3.6 
106. The performance of the device can be further improved if the bandgap of
graphene is increased by reducing the nano-belt width.
The high-frequency transistor can be fabricated by using the high carrier mobility
property of graphene. The Si-based graphene transistor arrays have a frequency of
100 GHz. Combined with cobalt (Co) silicide nanowires, the frequency of graphene
transistor can be increased to 300 GHz. The theoretical frequency of graphene
transistor is 1420 GHz, which is much more than those based on Si or III-V
1662 D. Yang and X. Yu

materials. The inventor of graphene, Novosclov, predicts that the high frequency
Si-based graphene device is promising to take place III–V devices and practically
applied in the near future.

Light-Emitting Materials on Si Substrate

Combining the mature microelectronic and photoelectronic techniques, Si photonics

(Si photoelectronic integration) has both the advantage of lower cost and higher
density integration of microelectronics, and can present the performance of higher
anti-interference, high transmission speed, and lower power consumption in the field
of photo-electronics. By the generation, transmission, modulation, amplification,
and detection of light on Si wafers, Si photonics can realize the generation, trans-
mission, processing, and storage of information for the next generation IT industry.
Si photonics includes Si-based light emitting, transmission, modulation, detec-
tion, photoelectronic integration, and packaging. Among these major components,
Si-based light-emitting materials and devices are currently the key unsolved
problems, as Si itself does not emit light due to its indirect bandgap. Si-based light
emitting refers to the generation of electrically pumped laser or electroluminescence
(EL) from Si materials or materials on Si substrate at room temperature by means of
IC processes. This EL or laser can be used as light sources for photoelectronic
integration on Si chips. In 1990, Caham first reported that, the photoluminescence
(PL) of porous Si in the visible light range was observed at room temperature [7], in
which porous Si structure could be formed on Si wafer surface through the electro-
chemical corrosion. Since then, lots of research groups have studied Si nanoparticles
embedded in SiO2 or Si3N4 matrix. By changing the sizes of Si nanoparticles, PL and
EL in the different wavelength have been obtained [8]. Moreover, to realize Si-based
light emitting, a lot of methods have been developed on Si substrate, such as
dislocation lighting by ion implantation on Si wafers, rear-earth lighting in SiOx
film, oxide film lighting, Ge/GeSn thin film, quantum dot (QD) or quantum wells
(QW) lighting, organic lighting, compound semiconductor material lighting, and so
on [9]. For example, by high concentration doping and stress adjustment, indirect
bandgap of Ge single crystal thin film on Si substrate was changed to quasi-direct
bandgap structure, so that electric-pumped lasing was observed. By fabricating
InGaAs/GaAs quantum dots on Si substrate, the laser at the wavelength of 1.5 um
with the lifetime more than 100,000 h has been realized. Currently, InP laser diode is
directly bonded on Si wafers to obtain the laser as light sources for the light
interconnection between chips. However, this method is still not suitable to fabricate
the light emitting for photoelectronic integration on chips. Therefore, by means of
defect engineering, energy bandgap engineering, and other techniques, higher effi-
ciency EL or electric-pumped lasing can be achieved on Si substrate at room
temperature.
Light emitting on Si substrate has been one of the important contents in Si
photonics research. To resolve this problem is the key issue to realize Si photonics
or photoelectronic integration. In the future, Si photonics has a broad application
74 Silicon Materials 1663

prospect in microelectronics, computers, telecommunications, sensors, life science,

and new energy applications.

References
1. D. Que, X. Chen, Science and Technology of Silicon Materials [M] (Zhejiang University Press,
Hangzhou, 2000)
2. Y. Xuegong, J. Chen, X. Ma, D. Yang, Impurity engineering of Czochralski silicon. Mater. Sci.
Eng. R. Rep. 74, 1 (2013)
3. D. Yang, Materials for Solar Cells (Chemical Engineering Press, Beijing, 2007)
4. A.D. Franklin, M. Luisier, S.J. Han, Sub-10nm carbon nanotube transistor. Nano Lett. 12,
758–762 (2012)
5. T. Rueckes, K. Kim, E. Joselevich, Carbon nanotube-based nonvolatile random access memory
for molecular computing. Science 289, 94–97 (2000)
6. H. Yang, J. Heo, S. Park, Graphene Barristor, a triode device with a gate-controlled Schottky
barrier. Science 336, 1140–1143 (2012)
7. Y.M. Lin, C. Dimitrakopoulos, K.A. Jenkins, 100-GHz transistors from wafer-scale epitaxial
graphene. Science 327, 662–662 (2010)
8. L.T. Canham, Silicon quantum wire array fabrication by electrochemical and chemical dissolu-
tion of wafers. Appl. Phys. Lett. 57, 1046 (1990)
9. N.M. Park, C.J. Choi, T.Y. Seong, S.J. Park, Quantum confinement in amorphous silicon
quantum dots embedded in silicon nitride. Phys. Rev. Lett. 86, 1355 (2001)
Silicon Wafer Processing
75
Deren Yang, Xingbo Liang, and Xuegong Yu

Contents
Heat Treatment of Crystal Ingot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
Orientation of Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
Cutting Technology of Crystal Ingot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
Slicing Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
Lapping Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
Polishing Technology and Polished Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
Cleaning and Packaging of Si Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676

Abstract
This chapter reviews the Si wafer-processing technology, including ingot heat
treatment, cutting, slicing, lapping, polishing, wafer cleaning, and packaging. The
ingot heat treatment is used to eliminate thermal donors or repair neutron irradi-
ation damage. After the crystal orientation of Si ingot is measured by X-ray
diffraction method, the wafer-making processes start. Nowadays, the blade cut-
ting is gradually replaced by the more efficient wire sawing technology. Then, the
lapping is used to remove the damage layer caused by slicing process. The most
important step is the wafer polishing, for achieving “mirror like” surface with
excellent geometric accuracy for device fabrication. Wafer cleaning is needed to
eliminate the contamination during the former processes, followed by the wafer
packaging.

D. Yang (*) · X. Yu
State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China
e-mail: mseyang@zju.edu.cn
X. Liang
Ql Electronics Co., Ltd., Ningbo, China

© Publishing House of Electronics Industry 2024 1665

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_75
1666 D. Yang et al.

Keywords
Heat treatment · Crystal orientation · Cutting technology · Slicing technology ·
Lapping technology · Polishing technology · Wafer cleaning · Wafer packaging

Heat Treatment of Crystal Ingot

Heat treatment of crystal ingot refers to the thermal annealing of mono-Si ingots
(or Si wafers) for a period of time at given temperatures in certain protective
ambient, in order to improve properties of Si ingots (or Si wafers). Heat treatment
is usually performed in annealing furnace with nitrogen (N) or argon (Ar) protective
ambient. Typical mono-Si ingot (or Si wafer) heat treatments are described below.
(1) Eliminating thermal donor: For mono-Si ingot pulled by Czochralski
(CZ) method [1–3], during the ingot cooling process to room temperature, the
oxygen (O) impurity within Si ingot will form thermal donors at the temperature
range of 350–500
C [4]. The most effective temperature of thermal donors forming
is 450
C. Thermal donor concentration can reach ~1016 cm3 after annealing the
ingot at 450
C for 100 h. The top region of CZ ingot usually stays the longest time at
temperature range around 450
C and also has relatively high O concentration,
therefor having higher concentration of thermal donors than the bottom region of
CZ ingot. Thermal donors lead to the resistivity decrease of n-type Si ingot and
increase of p-type Si ingot. Most of the thermal donors in Si ingot (or Si wafer) can
be eliminated by annealing at 450
C for 30–60 min followed by rapid cooling to
temperature lower than 300
C. If the cooling speed is not fast enough, a small
amount of thermal donors will still remain. For large diameter Si ingot, the thermal
stress generated during the rapid cooling process may cause ingot cracking; there-
fore, the heat treatment of Si wafers is commonly used as an approach to restore the
resistivity. (2) Repairing neutron irradiation damage: Neutron irradiation doping
technique is used in high resistivity float zone (FZ) mono-Si doping and is a nuclear
reaction process [5, 6]. Si element is composed of 28Si, 29Si, and 30Si isotopes (about
3.09%). In the nuclear reactor, after neutron irradiation of Si, 30Si reacts with neutron
to form an unstable isotope 31Si with a half-lifetime of 2.6 h and decays to form a
stable phosphorus (P) isotope 31P. Meanwhile, the neutron irradiation process will
cause mono-Si crystal lattice damage, which can be eliminated by the high-
temperature annealing. The typical annealing temperature is 750–850
C, and the
annealing time is 1–2 h.

Orientation of Crystal

Because of the anisotropy of Si single crystal, many of its properties are related to
crystal orientations. Therefore, it is necessary to precisely control the orientation of
Si ingot or Si wafers in the process of manufacturing (e.g., ingot slice) to meet the
device requirements. “Orientation of crystal” refers to the process of determining the
75 Silicon Wafer Processing 1667

orientation of Si ingot surface, cross section, and the orientation of Si wafers by

certain measurement techniques or methods.
MOS devices generally use (100) crystal-oriented Si wafers, which need to be cut
at such specific crystal orientation. The maximum allowable deviation from the
specified crystal orientation is well defined based on no affecting the characteristics
of MOS devices, usually in the range of 0.5
. Si epitaxial wafers for bipolar
devices generally use (111) crystal-oriented Si wafers as substrates, the substrate
wafer is usually cut with deviation of <111> crystal orientation toward the nearest
<110> direction by 2
–4
in order to obtain a relatively flat Si epitaxy surface.
There are two types of methods to measure the crystal orientation. (1) The first
type of method is based on the visible special patterns formed by reflection of light
from the edge of etched Si crystal defects. (2) Another type of method relies on
measurement by specific equipment and tools, such as X-ray diffraction method.
X-ray diffraction method features high accuracy and has been the most widely used
method to measure the crystal orientation of mono-Si ingot and wafer. The principle
of measuring crystal orientation by X-ray diffraction method is described as follows.
There are a series of parallel crystal planes in single crystalline Si, and the distance
between adjacent parallel crystal planes is d. When an incident beam of X-ray with
wavelength λ reaches the parallel crystal planes, in which the difference of path
distances of X-ray between two adjacent parallel crystal planes is the integer
multiple of X-ray wavelength λ, then the reflected X-ray from the adjacent parallel
crystal planes will have the same phase and generate the strongest X-ray diffraction
intensity. In X-ray diffraction method, the Si ingot or wafer is usually placed on a
rotating device so as to change the X-ray incident angle θ (refers to the angle
between X-ray and specified crystal plane). The angle between the incident X-ray
direction and the X-ray receiver direction is 2θ. When X-ray incident angle θ meets
the X-ray diffraction condition of the desired crystal planes, X-ray receiver shows
the strongest X-ray diffraction intensity.

Cutting Technology of Crystal Ingot

Crystal ingot cutting refers to the process of cutting Si ingots at specified angle or
direction according to different purposes and requirements. The main purposes of
single crystalline Si ingot cutting include cutting off the head (refer to seed crystal
and shoulder of Si ingot) and tail parts of the whole Si ingot as well as the parts of
ingot with diameters beyond the required specification, cutting the whole Si rod into
Si ingots with specified length suitable for slicing, and cutting wafer slabs from
ingots for testing resistivity, O content, C content, crystal defects, etc.
In the early processing of single crystalline Si ingots with diameters of 150 mm or
less, the technology of outer peripheral blade cutting and inner peripheral blade
cutting were used more frequently. With the development of IC technology, the
diameter of single crystalline Si ingot was also increasing. Limited by both blade
diameter and mechanical strength, outer peripheral blade cutting and inner peripheral
blade cutting were gradually replaced by more advanced band saw cutting
1668 D. Yang et al.

Fig. 75.1 Schematic of Si

ingot cutting process

technology. The advanced band saw cutting techniques and equipment are now
widely used for crystal ingot cutting process in the manufacturing of single crystal-
line Si ingots and polished wafers with diameters of 200 mm and 300 mm, as shown
in Fig. 75.1.

Slicing Technology

Slicing refers to the process of cutting single crystalline Si ingots into wafers with
specified thickness and flatness. Slicing process determines the Si wafer warpage
and also has critical influence on subsequent Si wafer processing (e.g., wafer
lapping, wafer polishing, etc.).
There are three types of slicing techniques for Si ingots, i.e., outer peripheral
blade cutting, inner peripheral blade cutting, and wire saw cutting. In the early
processing of single crystalline Si ingots with diameters of 150 mm or less, the
technology of inner peripheral blade cutting was the most used. For inner peripheral
blade cutting, the blade is oriented toward the center of the circle, and the blade
surface is coated with diamond powder. The blade is embedded on the inner circle of
the thin circular metal substrate, and the outer part of the blade is fixed on the rotating
shaft. In the process of slicing, the high-speed rotating blade embedded on the inner
circle contacts and slowly cuts into the single crystalline Si ingot until it is
completely cut off to complete the slicing. Compared to earlier outer peripheral
blade cutting, inner peripheral blade cutting can use thinner blades and has less
cutting loss and higher cutting accuracy. However, during the internal slicing
process, the blades need to be adjusted manually and frequently, so the operator’s
proficiency and experiences are highly demanded.
With the increase of diameter of single crystalline Si ingot, in order to improve
processing accuracy, reduce the loss of slicing slits, and enhance efficiency, wire saw
cutting technology has replaced inner peripheral blade cutting and is widely used in
the slicing of Si ingots of 200 mm diameter and above [7, 8] (see Table 75.1). Wire
saw cutting technology performs slicing by high-speed moving metal wire with
slurry. Very thin metal wires (with diameter less than 120 μm) are precisely wound
on several shafts carved with grooves of specified spacing to form a metal wire net.
The thin metal wires move back and forth at a very high speed and the cutting slurry
is sprayed onto the thin metal wires to facilitate slicing. The cutting slurry is
75 Silicon Wafer Processing 1669

Table 75.1 Comparison of wire saw cutting and inner peripheral blade cutting techniques
Items Wire saw cutting Inner peripheral blade cutting
Cutting mechanism Slurry injected on Diamond powder coated on cutting
metal wire blade
Typical morphology of sliced Wire saw mark Blade mark
surface
Damage layer depth 5–15 μm 20–30 μm
Amount of wafer per cut 200–400 pieces One piece
Loss of cutting slit 130–200 μm 300–500 μm (increase with crystal
ingot diameter)
Minimum thickness of sliced ~200 μm ~350 μm
wafer
Maximum ingot diameter for 300 mm 200 mm
slicing
Total thickness variation (TTV) <15 μm <25 μm
of sliced wafer
Warpage of sliced wafer 5 ~ 15 μm >50 μm

Fig. 75.2 Schematic of Si ingot slicing process

mainly composed of SiC particles and polyethylene glycol suspension. During the
slicing process, single crystalline Si ingot moves slowly downward from the top of
metal wire net and passes through the metal wire net until the ingot is completely cut
off. With high-speed back and forth moving of the metal wires, the SiC particles in
the cutting slurry abrade the Si ingot surface. Because silicon carbide is harder than
silicon, the Si ingot where they come in contact with high-speed moving metal wires
will be worn off. The worn-off Si debris and the heat generated during slicing are
taken away by the slurry so that the slicing process can keep going. When the single
crystalline Si ingot has completely passed through the metal wire net, it will be cut
into many Si wafers with the same thickness as shown in Fig. 75.2.
1670 D. Yang et al.

The key parameters used to evaluate the slicing results include deviation of wafer
crystal orientation and flatness parameters (e.g., total thickness variation-TTV, warp,
bow, etc.). To ensure accurate wafer crystal orientation after ingot slicing process, the
crystal orientation of Si ingot must be measured in advance to determine the correct
ingot mounting position for slicing.
Diamond wire sawing is a new technology of slicing, which can be classified into
two main categories, that is, slicing by resin diamond wire and slicing by electro-
plated diamond wire. Diamond wire sawing has obvious advantages in decreasing
the loss of cutting slits, increasing wafer yield, reducing pollution, etc. This tech-
nology has been widely used for photovoltaic industry.

Lapping Technology

Lapping refers to the process of grinding the Si wafer surface so as to remove the
damaged layer caused by slicing process and to obtain Si wafers with specific
geometric accuracy. In Si wafer manufacturing industry, double-sided Si wafer
lapping process has been widely used. The schematic of double-sided lapping
process for wafers with diameters of 200 mm and less is shown in Fig. 75.3.
During the lapping process, Si wafers are positioned in the pockets of the planetary
plates, which are located between upper lapping plate and lower lapping plate. Driven
by the center gear, planetary plates begin the revolution and rotation so that the Si
wafers move in a relative planetary motion with the lapping plates. Meanwhile,
abrasive slurry is injected between upper and lower lapping plates, and the pressure
is exerted on the Si wafers through upper and lower lapping plates to facilitate the
double-side lapping process of Si wafers. The lapping plates are generally made of cast
iron, and the surface of lapping plate is designed with many perpendicularly
intersected grooves with width of 1–2 mm and depth of about 10 mm to facilitate
the uniform distribution of abrasive slurry and lapping debris discharge. The abrasi-
ve slurry is mainly composed of abrasive particles (Al-oxide and Zr powder with
particle size of 5–10 μm) and abrasive fluid (water and surfactant). The important

Fig. 75.3 Schematic of Si wafer-lapping process

75 Silicon Wafer Processing 1671

Table 75.2 Comparison of double-side lapping and surface grinding techniques

Items Double-side lapping Surface grinding
Applicable silicon wafer 200 μm 300 mm
diameter
Abrasive slurry composition Abrasive particles, water, and Water and surfactant
surfactant
Maximum removing rate 2.0 μm/min 20 ~ 200 μm/min
Surface damage layer depth 1.5 ~ 2 times of the size of abrasive <1.4 μm for rough
particles, 10 ~ 20 μm surface grinding,
<0.4 μm for fine
surface grinding
Total thickness variation (TTV) 2 μm 0.3 μm
of processed wafer
Site flatness (STIR) of 0.14 μm 0.1 μm
processed wafer
Warpage of processed wafer 15 μm 15 μm

properties of abrasive slurry include hardness of abrasive particles, sizes and unifor-
mity, suspension and dispersion effects of abrasive particles in fluids, lubricity and rust
resistance of abrasive fluids, etc. The total removal thickness of double-side lapping of
Si wafers is 60–80 μm, and the depth of surface damage layer is about 1.5 times of the
size of abrasive particles.
In the processing of Si wafers with 300 mm diameters, single wafer surface
grinding technique has been widely used instead of traditional multiple wafer
double-side lapping. The comparison of the two techniques is shown in Table 75.2.
Surface grinding technique uses diamond grinding wheel to grind Si wafer
surface directly. It has the advantages of high processing efficiency, good wafer
surface flatness, low cost, little surface damage, etc. After the single-sided surface
grinding process, the Si wafer surface has many obvious grinding marks, which will
affect the surface nano-topography of Si polished wafer. With the development of
double-side surface grinding technology, systems capable of processing double-side
surface grinding simultaneously on 300 mm Si wafers have been developed to
prevent grinding marks and ensure the good nano-topography of Si polished wafers.

Polishing Technology and Polished Wafer

Si wafer polishing refers to the process of polishing the Si wafer surface by

combined chemical and mechanical means in order to eliminate the micro defects
and the damaged layer of Si wafer surface so as to obtain “mirror like” surface with
excellent geometric accuracy and extremely low surface roughness. Such processed
Si wafer is called Si polished wafer. Si wafer polishing includes wafer surface and
wafer edge polishing. The aim of wafer edge polishing is to reduce the chance of
collision cracking of Si wafer during wafer processing and to reduce particle
adhesion.
1672 D. Yang et al.

Si wafer polishing is a chemical and mechanical process. Before carrying out the
polishing process, Si wafers must be patched to the carrying plates (ceramic plates)
by means of liquid wax adhesion (wax patched) or by means of vacuum adhesion
(wax-free patched) via polishing templates and inserts. During the Si wafer surface-
polishing process, pressure is exerted on the Si wafers abraded by the rotating
polishing pad, and polishing slurry is injected into the abrading interface simulta-
neously, as shown in Fig. 75.4. The alkali components of the polishing slurry react
with Si wafer surface to form soluble silicate. The reaction products are removed via
both the adhesive effect of negative charges from the SiO2 colloidal particles (sizes
of 50–70 nm) in the polishing slurry and the mechanical abrasive effects between Si
wafers and polishing pads. The processes of chemical etching and mechanical
abrading go on alternately and cyclically to realize continuous chemical and
mechanical polishing of the Si wafer surface.
In order to obtain required geometric and surface nano-topographic properties of
polished Si wafers, multiple-step polishing processes are commonly used, for
example, two-steps polishing (i.e., rough polishing – fine polishing), three-step
polishing (i.e., rough polishing – middle polishing – fine polishing), and four-step
polishing (i.e., rough polishing – middle polishing – fine polishing – final polishing).
The process conditions used in each step of polishing are different; their effects and
removal thickness are listed in Table 75.3. The process parameters affecting

Fig. 75.4 Schematic of Si wafer-polishing process

Table 75.3 Process conditions of different polishing steps for Si wafers

Removal
Steps Process Purpose and effects depth
1 Rough Remove surface damaged layer of silicon wafer and 12 ~ 18 μm
polishing achieve required silicon wafer geometric accuracy
2 Middle Obtain low silicon wafer surface site flatness and low 5 ~ 8 μm
polishing surface roughness
3 Fine Prevent “Haze” on polished silicon wafer surface and <1 μm
polishing ensure surface nano-topography
4 Final Improve silicon wafer surface nano-topography <1 μm
polishing
75 Silicon Wafer Processing 1673

Table 75.4 Processing capability of wax-free patched polishing and wax patched polishing
Wax-free patched
Parameters polishing Wax patched polishing
Silicon wafer diameter 125 mm 150 mm 200 mm
Total thickness variation 2 ~ 4 μm 1.2 μm 0.8 μm
(TTV) of processed wafer
Site flatness (STIR) of SFQR: 15 mm  SFQR: 15 mm  SFQR:15 mm 
processed wafer 15 mm, 1 ~ 3 μm 15 mm, 0.5 μm 15 mm, 0.14 μm

polishing results include polishing pressure, slurry components, slurry particle sizes,
slurry concentration, slurry pH value, polishing pad material, pad structure, pad
hardness, polishing process temperature, polishing removal thickness, etc.
For wax-free patched Si wafer-polishing process, the selection of polishing
templates and inserts are key factors to improve polishing accuracy. By comparison,
the wax patched Si wafer-polishing process has higher processing accuracy. The key
lies in the wax coating technology and the control of both the geometry and the
cleanness of the polishing plate surface. Based on different processing requirements,
single-sided wax-free patched polishing process is usually used for Si wafers of
diameters 125 mm or less, single-sided wax patched polishing process is generally
used for Si wafers of diameters 150–200 mm (for technology nodes of 0.5/0.35/0.25/
0.18 μm). The comparison of processing capability of wax-free patched polishing
and wax patched polishing is shown in Table 75.4. For 300 mm diameter Si wafers
(for technology nodes of 0.18 μm and beyond), the polishing processes usually
consist of double-sided rough polishing and middle polishing followed by single-
sided wax-free fine polishing and final polishing. The key technical parameters of Si
polished wafers are shown in Table 75.5 [9].

Cleaning and Packaging of Si Wafer

Device-making processing requires Si wafers with clean surfaces. However, the

surface of Si wafers can be contaminated by organics, metallic ions, and particles
during the wafer process. Si wafer cleaning refers to the process of eliminating
contamination from Si wafer surface so as to obtain ideally clean Si wafer surface.
There are mainly three types of contamination on the surface of Si wafers. The first
type of contamination is organic impurity which comes from wafer cassettes, organic
containing ambient, and chemicals used during wafer processing. The second type of
contamination is metallic ion impurity by adsorbing on the oxide films at Si wafer
surfaces or bonding directly onto Si wafer surfaces via electric charge exchange (like
“electroplating”). The third type of contamination is particle, mainly from Si wafer
processing and chemicals. There are many cleaning processes during Si wafer
processing; among them, the most important one is the final cleaning process
following the polishing, because it directly determines the final cleanliness of the
Si polished wafer surface. The final cleaning process of Si polished wafers usually
 1674

Table 75.5 Key technical parameters of Si polished wafers

ITRS ITRS 1999 ~ ITRS 2001 ITRS 2003 ITRS 2010
Year Before 1998 1999 2001 2004 2007 2009 2010 2013 2014
Technology node 0.35 μm 0.25 μm 0.18 μm 0.13 μm 90 nm 65 nm 50 nm 45 nm 32 nm 28 nm
Wafer diameter/mm 200 200 200 300 300 300 300 300 300 300 450
Diameter tolerance/mm 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2
Wafer thickness/μm 725 725 725 775 775 775 775 775 775 775 775
Thickness tolerance/μm 25 25 25 25 25 25 25 25 25 25 25
Warp/μm <30 <30 <30 <30 <10 <10 <10 <10 <10 <10 <10
TTV/μm <1.2 <1.2 <1.2 <1.0 <1.0 <1.0 <1.0 <1.0 <1.0 <1.0 <1.0
SFQR 25 mm  25 mm <0.3 μm <0.2 μm <0.18 μm <0.15 μm – – – – – –
26 mm  8 mm 90 nm 64 nm 51 nm 45 nm 32 nm 28 nm
Edge exclusion/mm 3 3 3 3 2 2 2 2 2 2
Surface Particle size/nm 120 80 90 90 90 90 90 45 32 32
particles Surface particle/cm2 0.17 0.13 0.13 0.18 0.35 0.18 0.09 0.18 0.18 0.18
Max/(#/Wf) Total 50 40 38 123 238 123 63 126 126 286
0.16/μm 30 – – – – – – – – –
0.12/μm – 50 100 – – – – – – –
0.09/μm – – 38 78 ~ 123 – – – – – –
Critical surface metals/(at/cm2) 1  1010 1  1010 (1.4 ~ 1.8)  1010 1.2  1010 1  1010 1  1010 1  1010 1  1010 1  1010 1  1010
~1  1011 ~1  1011
D. Yang et al.
75 Silicon Wafer Processing 1675

Table 75.6 Typical conditions of RCA cleaning processes [10, 11]

Cleaning
process SC-1 solution ! SC-2 solution ! Drying
Chemicals NH4OH:H2O2: Deionized water HCl:H2O2:H2O Deionized water
H2O rinsing rinsing
Mixing ratio 1:1:5 1:1:6
Temperature 75 ~ 80
C 75 ~ 80
C
Duration 6–10 min 6–10 min
Ultrasonic 15 ~ 200 kHZ 15 ~ 200 kHZ
Megasonic 0.8 ~ 3.0 MHZ 0.8 ~ 3.0 MHZ

adopts multitank immersion chemical cleaning method, known as the RCA cleaning.
Typical conditions of RCA cleaning processes are shown in Table 75.6.
(1) SC-1 solution is used to remove particles and organic contaminations from the
Si surface. It can also remove some metallic impurities. The principle of SC-1
cleaning process is described as follows. The surface of Si wafers is oxidized by
H2O2 to form oxide films and subsequently etched off by NH4OH. The oxidation
and etching processes of Si wafer surface go on repeatedly so that the particles
attached on the Si wafer surface could be removed off into cleaning solutions. Under
both the strong oxidation effect of H2O2 and the dissolution effect of NH4OH, the
organic impurities turn into water-soluble compounds and are subsequently removed
by deionized water rinsing. The strong oxidation capability of SC-1 solution enables
metallic atoms (e.g., Cr, Cu, Zn, Ag, Ni, Fe, Ca, Mg, etc.) to be oxidized into their
corresponding high valence ions, which then react with alkali to form water-soluble
complex compounds, and finally removed by deionized water rinsing. By adding
ultrasonic (for particles with sizes >0.4 μm) or megasonic (for particles with sizes
<0.2 μm) vibrations during the cleaning process, better particle removal effects can
be achieved. (2) SC-2 solution is acidic solution containing H2O2 and HCl, which
has extremely strong oxidation and complexation capability. SC-2 cleaning process
can remove alkali metal ions, metallic ions of Cu, and Au, and metallic ions of Al
(OH)3, Fe (OH)3, Mg (OH)2, and Zn (OH)2. After SC-2 cleaning, the surface of Si
wafer will form a native oxide film with SiO bonding; therefore, the Si wafer
surface is hydrophilic.
Earlier, Si wafer-drying technology is mainly centrifugal drying. In recent years,
based on isopropyl drying technology, many Si wafer-drying technologies utilizing
Marangoni effects [12, 13] have been developed and have been widely used in the
final cleaning process of large diameter Si wafers. To ensure the quality of cleaned Si
wafer surface from recontamination and in the purpose of convenience for Si wafer
storage and transportation, the as-cleaned Si wafers must be packaged. The packag-
ing process of Si polished wafers should be conducted at class 10 or 1 cleanroom
environments. First, the Si polished wafers are placed into packaging boxes of
corresponding sizes. Then, each packaging box is placed into a packaging bag
(inner packaging bag) made of plastic films and subsequently sealed either by
vacuum or with high-purity nitrogen filled. Finally, each Si wafer box sealed with
1676 D. Yang et al.

inner packaging bag is placed into an antistatic packaging bag (outer packaging bag)
made of plastic and metal compound films and sealed by vacuum. The well-
packaged Si wafers are then transferred to the storehouse.

References
1. R. Uecker, The historical development of the Czochralski method. J. Crystal Growth 401,
7–24 (2014)
2. W.C. OMara, R.B. Haber, L.P. Hunt, Handbook of Semiconductor Silicon Technology (Noyes
Publications, 1990)
3. G. Müller, Review: The Czochralski method – Where we are 90 years after Jan Czochralski’s
invention. Crystal Res. Technol. 42(12), 1150–1161 (2007)
4. B.Y. Mao, J. Lagowski, H.C. Gatos, Kinetics of thermal donor generation in silicon. J. Appl.
Phys. 56, 2729–2733 (1984)
5. E.E. Haller, J.W. Ager III, Isotopic effects in solids, in Encyclopedia of Condensed Matter
Physics, (Academic Press, 2005), pp. 43–52
6. I. Obodovskiy, Radiation doping of semiconductors, in Radiation, (Elsevier Inc., 2019),
pp. 337–344
7. E.C. Costa, C.P. dos Santos, F.A. Xavier, W.L. Weingaertner, Influence of diamond wire sawing
parameters on subsurface microcracks formation in monocrystalline silicon wafer, in 25th
ABCM International Congress of Mechanical Engineering October 20–25, 2019, Uberlândia,
MG, Brazil
8. E. Teomete, Mechanics of Wire Saw Machining Process: Experimental Analyses and Modeling
(PhD thesis, Iowa State University, 2008)
9. SEMI M57 – Specification for Silicon Annealed Wafers. SEMI M Series, Wafers and Process
Control
10. W. Kern, D.A. Puotinen, Cleaning solutions based on hydrogen peroxide for use in silicon
semiconductor technology. RCA Rev. 31, 187–206 (1970)
11. RCA Critical Cleaning Process (MicroTech Systems Inc., 2007). https://www.micro
techprocess.com/wp-content/uploads/2018/04/MTS_RCA.pdf
12. L.E. Scriven, C.V. Sternling, The Marangoni effects. Nature 187, 186–188 (1960)
13. W. Fyen, F. Holsteyns, et al., A detailed study of semiconductor wafer drying, in Developments
in Surface Contamination and Cleaning, Vol. 1: Fundamentals and Applied Aspects, ed. by
R. Kohli, K.L. Mittal, 2nd edn., (Elsevier Inc., 2008), pp. 795–854
Defects and Impurities in Silicon Materials
76
Deren Yang and Xiangyang Ma

Contents
Point Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678
Line Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679
Planar Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1681
Bulk Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
Micro-Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
Oxygen in CZ Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
Carbon in CZ Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685
Nitrogen in CZ Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686
Metallic Impurity in CZ Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687
Slip Dislocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
Misfit Dislocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689
Oxidation-Induced Stacking Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690
Epitaxial Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
Induced Micro-Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695

Abstract
This chapter reviews the defects and impurities in Si materials. Most of the
defects in Si crystal originate from point defects, which can be divided into
intrinsic and extrinsic categories. The intrinsic point defects include self-
interstitial atoms and vacancies, and the extrinsic point defects refer to foreign
impurity atoms. These point defects can form bulk defects and micro-defects,
among which oxygen precipitates, voids (COPs), and oxidation-induced stacking
faults are the most important ones. The line defects named after dislocations and
planar defects only exist in some special cases, which often occur during Si
epitaxial and wafer thermal cycles. The important impurity in Czochralski (CZ) Si
crystal is oxygen, which should be as low as possible. The oxygen impurities can

D. Yang (*) · X. Ma
State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China
e-mail: mseyang@zju.edu.cn

© Publishing House of Electronics Industry 2024 1677

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_76
1678 D. Yang and X. Ma

form SiO2 precipitates as the intrinsic gettering sites for metal contaminants.
Meanwhile, the nitrogen doping enhances the formation of oxygen-related SiO2
precipitates and reduces the thermal stability of voids (COPs), and therefore has
been widely used in microelectronics industry.

Keywords
Point defects · Area defects · Micro-defects · Impurity engineering · Slip
dislocation · Misfit dislocation · Oxidation-induced stacking faults · Epitaxial
defects

Point Defects

Point defects are defects existing only at or around a single lattice site, not extending
in space in any dimension [1]. Point defects can be divided into intrinsic and
extrinsic defects. The intrinsic point defects include self-interstitial atoms and
vacancies. A self-interstitial atom is an extra atom that enters into an interstitial
space in the crystal lattice. A vacancy is an empty crystal lattice site where an atom
should be. As a lattice atom in the bulk of crystal migrates to the surface, the
resulting vacancy is called a Schottky vacancy. A nearby pair of a vacancy and an
interstitial atom is often called a Frenkel pair, which is caused when an atom moves
into an interstitial site and creates a nearby vacancy. Vacancies and interstitials can
be thermally generated, and their concentrations are dependent on temperature and
formation energy. At a given temperature, there are always vacancies and interstitials
of certain concentrations in a crystal. Therefore, the intrinsic defects are also called
as thermal equilibrium defects. Point defects can interact with other defects and,
moreover, can influence the impurity diffusion in crystal. Point defects can also
aggregate into extended defects. For example, the interstitials can be condensed into
dislocations or stacking faults, and the vacancies can agglomerate into voids in
single-crystal Si.
The extrinsic point defects refer to foreign atoms in a crystal. A substitutional
impurity atom is an atom different from the bulk atoms, which have replaced one of
the bulk atoms in the lattice. An interstitial impurity atom can easily fit into
the interstitial space in the crystal lattice because it is much smaller than the atoms
in the bulk matrix. In semiconductors, the impurity atoms incorporated to define the
electrical resistivity are generally located at substitutional sites. At a given temper-
ature, the equilibrium concentration of an impurity in the crystal is limited by the
solid solubility. As for the compound crystal, anti-site defects occur when atoms of
different type exchange positions. For example, Ga and As atoms exchange their
lattice sites in GaAs crystal. Such anti-site defects also belong to the point defects.
Regarding Czochralski (CZ) Si used for ICs, the point defects exhibit significant
effects on the crystal performance. For example, the formation of grown-in defects is
directly related to the supersaturation of vacancies and interstitials. During the
crystal growth of Si, both vacancies and self-interstitials with comparable
76 Defects and Impurities in Silicon Materials 1679

concentrations exist in the Si crystal just above the crystal/melt interface. On moving
away from the crystal/melt interface, the two point defects recombine rapidly,
resulting in remarkable concentration gradients approximately proportional to the
axial temperature gradient (G) nearby the crystal/melt interface. Therefore, appre-
ciable diffusion fluxes of point defects directed from the interface into the bulk of
crystal are generated. Simultaneously, the convection fluxes of point defects as
proportional to the growth rate (V) are naturally formed during the crystal growth.
At a certain position distant from the interface, only the defects with the larger flux
survive to be supersaturated, thus generating micro-defects on subsequent cooling,
while the other defect decay swiftly to be under-saturated. Therefore, for Si crystal
growth, a critical V/G ratio (ξcrit) can be used to define which point defects exist in
the crystal. The critical ratio ξcrit as mentioned above can be expressed as follows:

ξcrit ¼ E=kT 2 ðDlm Clm  DVm CVm Þ=ðCVm  Clm Þ

where Dlm and DVm are the diffusivities of interstitial and vacancy respectively at
melting point Tm, and E is the average formation energy of the defects; E ¼ (EI þ
EV)/2. According to the aforementioned expression, ξcrit is calculated to be 1.34 
103 cm2/(minK).
If V/G is larger than a critical value ξcrit, then the convection flux is stronger than
the diffusion flux. In this context, the incorporated point defects are vacancies
because the vacancy equilibrium concentration (CVm) is larger than that of self-
interstitials (CIm). Upon the cooling of crystal, the supersaturated vacancies will be
agglomerated into voids. If V/G is less than ξcrit, then the relative contribution of
axial diffusion is more significant so that the in-flux of self-interstitials are the faster
diffusers prevails. As a result, the incorporated point defects are then self-
interstitials, which will then collapse into dislocation loops during the subsequent
cooling. Both voids and dislocation loops are detrimental to devices; the dislocation
loops are much more harmful due to their larger sizes. Though the voids can be
annihilated by annealing at elevated temperatures, unfortunately, the dislocation
loops cannot be eliminated totally. In principle, the perfect Si crystal with no defects
can be grown as V/G ¼ ξcrit. However, the processing conditions to meet this critical
point are very stringent. Actually, the growth of perfect Si crystal is extremely
difficult. In practical production, the CZ Si crystals are generally grown under the
condition of V/G > ξcrit.

Line Defects

Line defects are named after dislocations, around which the atoms of the crystal
lattice are misaligned. As a crystal is applied with tensile, compressed, or shear
stresses, it will be elastically or plastically deformed dependent on the amplitude of
stresses. In the elastic deformation regime, the crystal will be restored when the
external stress is removed. However, when the external stress exceeds the yield
strength, the crystal will be plastically deformed thus generating dislocations.
1680 D. Yang and X. Ma

The plastic deformation in crystal can be actually viewed as the sliding of one
atomic plane over another, i.e., slip plane. For a given crystal, the slip planes and slip
directions have specific crystallographic forms. The slip planes are usually the planes
with the largest spacing and the highest atomic density. While the slip direction is the
one on the slip planes corresponding to the translation vector of the shortest lattice, in
which the spacing of atoms is the most closest. In reality, the inter-plane slips do not
occur simultaneously in the whole crystal, instead, they always occur within a local
region and then extend. Therefore, the theoretical shear stress for slip is usually a few
orders of magnitude higher than the experimentally observed one.
The dislocations can be categorized in terms of the geometrical relationship
between dislocation lines and slip directions. They may be edge, screw, or mixed
dislocations. The mixed dislocations combine the characters of both edge and screw
types. For dislocations, the Burgers vectors can be used to describe the magnitude
and direction of distortion to the lattice. In an edge dislocation, the Burgers vector is
perpendicular to the dislocation line direction. In a screw dislocation, the Burgers
vector is parallel to the dislocation line direction. In a mixed dislocation, the
dislocation line direction and Burgers vector are neither perpendicular nor parallel.
(1) The edge dislocation features the dislocation line connecting all of the end atoms
on the extra half-plane. Moreover, the dislocation line must not be straight; instead, it
can be curved or folded. Nevertheless, the dislocation line must be normal to the
Burgers vector. (2) The screw dislocation features no extra half-plane and can be
described as a single surface helicoid rather like a spiral staircase. The dislocation
line in a screw dislocation must be straight and is the axis of the screw. The line of a
screw dislocation is in parallel to the Burgers vector. In this context, the glide of the
dislocation is not restricted to a specific plane but occurs within an arbitrary plane in
principle. Generally, it proceeds most readily in the planes with the highest density of
atoms. (3) A dislocation can be a prefect or partial dislocation according to the
relationship between Burgers vector and lattice vector. A perfect dislocation has
a Burgers vector that is equivalent to a unit or units of lattice vector. The motion of a
perfect dislocation leaves behind a perfect crystal. While a partial dislocation has a
Burgers vector that is not a unit or units of lattice vector. Thus, the motion of a partial
dislocation leaves behind an imperfect crystal containing a stacking fault. As a
perfect dislocation is dissociated into two or even more partial dislocations, they
are connected with stacking faults and forming so-called extended dislocations.
(4) The dislocation lines are continuous and can end at the surface of a crystal or
at grain boundaries, but never inside a crystal. Thus, dislocations must either form
closed loops or branch into other dislocations. The dislocations induce the stress
fields which can absorb impurities and point defects.
As for the Si crystals used for ICs as concerned, the dislocations can be intro-
duced due to diverse reasons such as the incompletely removed dislocations in seed
crystal, various disturbances during the crystal growth (e.g., particles dropped on
crystal/melt interface, constituent super-cooling within the melt) and the thermal
stresses caused by temperature gradient [2]. Owing to the invention of necking
technology and adopting the growth strategy under inert atmosphere of reduced
76 Defects and Impurities in Silicon Materials 1681

pressure, the single-crystal Si is usually free of macroscopic dislocations. Neverthe-

less, during the subsequent wafer processes (e.g., slicing, lapping, and polishing), the
dislocations could be introduced at the peripheries or surfaces of Si wafers due to
mechanical stresses. During IC fabrication, the dislocations may also be induced due
to the stresses arising from temperature gradient in furnace operation by the different
thermal expansion coefficient between the deposited film and Si wafer, etc. The
dislocations in Si wafers would be very detrimental to device performances if they
are located within the active regions of devices, generally resulting in a large leakage
current.

Planar Defects

Planar defects in crystals include stacking faults, twins, and grain boundaries [3, 4].

1. Stacking Fault: It is any defect that alters the periodic stacking sequence of
layers. These defects may be a wrong layer inserted into the sequence, a change of
the layer sequence, or a different translation between two subsequent layers. Take
the Si crystal which is of diamond structure as an example, it consists of three
double {111}-planes that are stacked in a regular sequence as
(. . .ABCABCABC. . .). If a {111}-A plane is inserted between the B and C
planes, an (. . .ABCABACABC. . .) structure is created. Such a fault in stacking
sequence is referred to as extrinsic stacking fault. The removal of a plane creates
an intrinsic stacking fault. As for single Si wafers, the stacking faults induced by
the processes (e.g., oxidation and implantation are of extrinsic type), while those
formed during the epitaxy process are of intrinsic type. In reality, the stacking
faults do not extend throughout the whole plane; instead, they are confined to a
local region by dislocations. For example, the oxidation-induced stacking faults
in Si wafers occur on {111} planes intersecting the surface at small regions. The
boundaries of such stacking faults have features similar to edge dislocations.
2. Twin: It is a kind of area defects generated by deformation twinning in which a
region of a crystal undergoes plastic deformation along a particular orientation. In
the simplest cases, a twin boundary is a defect that introduces a plane of mirror
symmetry in the ordering of a crystal. Taking the cubic close-packed crystals, for
example, a twin boundary stacking sequence of . . .ABCABCBACBA. . . can be
formed. The twin boundaries can act as the obstacles to dislocation motion. Under
certain circumstances, twin dislocations are generated when the gliding disloca-
tions intersect the twin boundaries.
3. Grain Boundary: The grain boundary is the interface between two crystal grains.
In a broad sense, grain boundaries refer to various interfaces in non-single-
crystalline solids. The two crystal grains separated by a grain boundary could
be different in crystal direction, lattice constant, crystal structure, and chemical
composition. The simplest and the most common grain boundaries exist in a
1682 D. Yang and X. Ma

single-phase material. In this case, the two crystal grains across a grain boundary
are only different in crystal direction. The grain boundaries in the multi-phase
solids are generally termed as phase boundaries. According to the extent of
mis-orientation between the two neighboring crystal grains, the grain boundaries
can be low-angle or high-angle grain boundaries. The low-angle grain boundaries
or sub-grain boundaries are those with a mis-orientation less than about
10 degrees. They are generally composed of an array of dislocations, and their
properties and structure are a function of the mis-orientation, whereas the prop-
erties of high-angle grain boundaries with mis-orientation greater than about
10 degrees are normally independent of the mis-orientation. In most polycrystal-
line solids, above 90% of grain boundaries are of high-angle.
The grain boundaries in solids have characteristics as follows: (a) The lattice is
seriously distorted around a grain boundary, thus resulting in high boundary
energy. At an elevated temperature, the crystal grains will become coarse and
the grain boundaries will be straightened so that the grain boundary area is
decreased for lower boundary energy. (b) At room temperature, the grain bound-
aries can impede the dislocation motions, thus enhancing the resistance of plastic
deformation. Generally, the smaller crystal grains result in higher mechanical
strength of a material. In contrast, at elevated temperatures, the grain boundaries
become somewhat viscous, which results in the movement of a crystal grain
relative to the other, thus leading to a lowered mechanical strength. (c) The grain
boundaries which are rich in various defects generally act as the fast-diffusing
paths for impurities, enabling the precipitation of impurities and therefore the
formation of new phases. (d) The grain boundaries generally reduce the electrical
and thermal conductivities of a material. (e) The grain boundaries are prone to
thermal corrosion and chemical etching.

Bulk Defects

Bulk defects in crystal include precipitates of impurities and voids. As for

Czochralski (CZ) Si used for integrated circuits (ICs), the main solid SiOx pre-
cipitates formed by agglomeration of tiny SiOx molecules and the voids resulting
from agglomeration of vacancies are the two important bulk defects, which impose
remarkable influences on the manufacturing yield of ICs.
SiOx precipitates are actually the Si oxide (SiOx, x  2) particles that are
generated from the reaction between the Si lattice atoms and the agglomerating
interstitial oxygen atoms. The oxygen impurity is inevitably introduced into CZ Si
due to the adoption of quartz crucible for crystal growth in which the oxygen
concentration is in a supersaturated state. Most oxygen atoms are located in the
interstitial sites of Si lattice. During the thermal processes of IC fabrication, the
supersaturated oxygen atoms form many tiny SiOx structures which will be
aggregated into larger SiOx precipitates. Such result is referred to as the SiOx
precipitation phenomenon, which is an extremely complicated process related to
76 Defects and Impurities in Silicon Materials 1683

initial interstitial oxygen concentration, other impurities, point defects, thermal

history of crystal growth, and the thermal processing conditions (e.g., ambient,
temperature, and time) during the IC fabrication [4]. The SiOx precipitation
consists of two stages (i.e., nucleation and growth). Generally, the nucleation of
SiOx precipitates occurs at relatively low temperatures less than 800  C, while the
growth of SiOx precipitates proceeds at elevated temperatures 1000  C and above.
The SiOx precipitates can be formed via homogeneous and heterogeneous nucle-
ation mechanisms. The homogeneous nucleation is indeed the agglomeration of
supersaturated oxygen atoms onto the Si atoms. In this case, the nucleation rate is
determined by the saturation level and diffusivity of oxygen atoms. The heteroge-
neous nucleation proceeds through the diffusion of oxygen atoms toward other
impurity atoms or existing defects, such as, nitrogen, boron, carbon, germanium,
complexes formed by interaction with point defects, as well as complexes formed
by interaction between vacancy and oxygen. All these defects can be used as
heterogeneous nucleation centers of SiOx precipitates. During the growth of
SiOx precipitates, the punched-out interstitial Si atoms may aggregate into dislo-
cations or stacking faults. If the SiOx precipitates and their induced defects are
located in the bulk or the backside of Si wafer, far away from the active region of
devices, they will exhibit intrinsic gettering effects on detrimental metal contam-
ination and are beneficial to increase device yields. However, the excessive
formation of SiOx precipitates and their induced defects will lead to warpage of
Si wafer. Moreover, if any SiOx precipitates and their induced defects in the active
region device, the leakage current will be remarkably increased.
Voids in Si crystal belong to a kind of micro-defects resulting from the agglom-
eration of vacancies. The type of point defects incorporated into the growing Si
crystal is determined by the ratio of V/G, where V is crystal growth rate and G is the
temperature gradient nearby the melt/crystal interface. As the V/G ratio exceeds a
critical value, the remained point defects are vacancies. Along with the cooling of
crystal, the remained vacancies will be supersaturated, thus agglomerating into voids
which can be manifested as crystal-originated particles (COPs) after RCA SC1
cleaning. The voids in CZ Si are about 100 nm in size and are usually in a
geometrical structure of incomplete octahedron surrounded by {111} planes and
truncated by {100} or {311} planes. The single, twins, and even triple voids can be
observed in CZ Si, depending on the conditions of V/G ratio, cooling rate, co-doped
impurity, etc. Moreover, there is a SiO2 layer generally thinner than 5 nm on the side
walls of the void. The void defects can deteriorate the gate oxide integrity of MOS
transistor and lead to the increase of gate leakage current. Through appropriately
designing hot zone and optimizing pulling conditions for crystal growth, the
so-called perfect Si crystal free of void defects can be grown. Unfortunately, the
process margin for growth of such perfect Si crystal is considerably narrow. In
practical production, the CZ Si is doped with N during the crystal growth. Then,
the N-doped Si wafers are annealed at no less than 1200  C to annihilate the void
defects existing in the near-surface zones of Si wafer, where the active regions of ICs
are fabricated [5].
1684 D. Yang and X. Ma

Micro-Defects

Micro-defects represent the defects formed by the agglomeration of point defects,

impurity atoms, and the extended defects including dislocations and stacking faults
in semiconductors. Generally, the aforementioned defects are of sizes ranging from
sub-micrometers to several tens of micrometers. They are thus named after micro-
defects. The precipitates resulting from the agglomeration of impurity atoms (e.g.,
SiOx oxide precipitates in CZ Si) belong to micro-defects. As such precipitates grow
up to be sufficiently large, stacking faults and dislocations may be induced as the
secondary micro-defects. For the Si crystals used for ICs, the micro-defects formed
by the agglomeration of point defects include the interstitial-type defects (e.g.,
dislocation loops) and vacancy-type defects (voids). (1) The interstitial-type defects
in Si crystals refer to dislocations and stacking faults resulting from the agglomer-
ation of Si interstitials. The primary interstitial-type defects in Si are manifested as
swirl defects which are distributed in a swirling pattern generally related to the
crystal growth striations. The relatively larger swirl defects are called as A-swirl and
the smaller ones as B-swirl. A-swirl defects are substantially dislocation loops due to
the agglomeration of supersaturated Si interstitials. Although such dislocation loops
hardly affect the gate oxide integrity, they will degrade the carrier lifetime, thus
increasing the reverse leakage current and causing local micro-plasma breakdown of
pn junctions. The Si interstitials may aggregate into B-swirl defects as their concen-
tration is relatively small. (2) The vacancy-type defects in Si crystals are manifested
as voids originated from the agglomeration of vacancies as also termed as D-defects.
The voids are also a kind of primary micro-defects in Si crystals.
The micro-defects in CZ Si wafers are like double-edged knife for ICs. Generally,
the active regions of ICs are located on the top surface layer of Si wafers. Unless the
micro-defects exist in the top surface layer of Si wafers, they will not be harmful to
ICs. Definitely, the swirl defects, oxidation-induced stacking faults (OSFs), and
voids must be annihilated through optimized crystal growth and subsequent
annealing processes or, in other means, should be avoided to occur in the top surface
layer of Si wafers in order to increase the yield of ICs. On the other hand, if the
micro-defects are manipulated to occur in the bulk Si wafer, they will exhibit
advantageous effects for ICs. During the fabrication of ICs, the Si wafers are
inevitably exposed to detrimental metal contaminations (e.g., Cu, Fe and Ni) for
ICs. By means of appropriate annealing cycles, the precipitation of SiOx can be
controlled in the bulk of Si wafer with sufficiently high density to induce stacking
faults and dislocations. Such bulk micro-defects can effectively getter and then trap
the metal contaminants and eliminate the harmful effects for ICs.

Oxygen in CZ Silicon

Oxygen (O) in CZ Si wafers is generated from the melt of SiO2 on quartz crucible
inner surface at high temperature. The segregation coefficient of oxygen in Si is always
disputed, but it is generally believed as 1.25. Oxygen concentration in CZ Si is closely
related to the crystal growth conditions, which can be modulated at some level by
76 Defects and Impurities in Silicon Materials 1685

changing hot zone, reducing gas pressure, and tuning the position and rotation rate of
crucible. The application of magnetic field can effectively increase the viscous effect
of Si melt due to the Lorenz force and suppress the Si melt convection. Therefore, the
oxygen concentration in CZ Si can be effectively controlled.
Oxygen in CZ Si is located at the interstitial sites, which can generally be
measured by Fourier transformed infrared (FTIR) absorption spectrum at room
temperature. The conversion factor of 1107 cm1 absorption peak corresponding
to interstitial oxygen is 3.14  1017/cm2. FTIR measurement of oxygen in Si is a
simple, direct, and nondestructive method which is widely used in IC industry.
However, the oxygen in heavily doped Si samples cannot be measured by FTIR
method since the carrier concentration is too high to distinguish the spectral signal of
oxygen. Thus, the oxygen in heavily doped Si is measured by charged particle
activation analysis, gas fusion method, or secondary ion mass spectroscopy
(SIMS) in the industry. The oxygen in CZ Si must diffuse during annealing, with
an activation energy of 2.53 eV in the temperature range of 300–400  C and
700–1200  C. The oxygen diffusion is much faster in the temperature range of
400–700  C, with a main form of oxygen dimer.
The oxygen concentration in CZ Si is usually 1018/cm3, which is higher than its
solubility at 1250  C. Therefore, the oxygen impurities in CZ Si tend to accumulate
to from solid SiOx precipitates during the crystal cooling process or following
thermal cycles. The oxygen impurities can form thermal donors (TDs) in the
temperature range of 300–500  C, which causes the variation of wafer resistivity.
The maximum concentration of TDs is proportional to the cube of interstitial oxygen
concentration. Generally, the TDs can be completely eliminated by annealing at
650  C for 0.5 h. If the annealing time is too long, interstitial oxygen will aggregate
into small precipitates and form another oxygen donor with electrical activity as
referred to as new donors (NDs).
The homogeneous nucleation of solid SiOx precipitates is dependent on the super-
saturation of interstitial oxygen in CZ Si, which tends to occur at low temperatures. The
heterogeneous nucleation of solid SiOx precipitates often occurs at some impurity
complexes or defects, like O-vacancy complex and dislocation. The grown-up of solid
SiOx precipitates is a process of interstitial oxygen atoms diffusing to the nuclei. The
solid SiOx precipitates in CZ Si can be used for the intrinsic gettering (IG) technology in
the IC fabrication process, which is one important part of defect engineering. The IG
technology is usually achieved by high-low-high three-step annealing. Nowadays, some
innovative IG technologies are successfully developed and used in the semiconductor
industry with high gettering efficiency and simple process, e.g., magic denuded zone
(MDZ) (invented by MEMC) and single-step high-temperature annealing IG technology
of N-doped or Ge-doped wafers (invented by Zhejiang University) [6].

Carbon in CZ Silicon

At high temperature, the graphite (C) heater crucible and quartz crucible will react at
the contact interface and generate carbon monoxide (CO). Then, the carbon mon-
oxide (CO) gas is absorbed by the molten Si and incorporated into CZ Si by
1686 D. Yang and X. Ma

segregation effect. High concentration of C will easily result in the swirl defect,
increasing the leakage current of device and reducing the yield of ICs. C atoms are
usually located at the substitutional sites in Si lattice resulting in infrared
(IR) absorption line of 607 cm1 with conversion factor of 1  1017/cm2 for C
concentration. The solubility of C in the molten Si and crystal are 4  1018/cm3 and
4  1017/cm3, respectively, and decreases with the temperature. The segregation
coefficient in CZ Si is 0.07 and leads to the phenomenon that the concentration of C
at the seed-end is smaller than that at the tail. The diffusion of C atoms with an
activation energy of 3.2 eV in Si is much slower than that of oxygen.
Carbon in CZ Si can react with oxygen to form carbon-oxygen (C-O) com-
plexes, which exhibit various absorption lines, like 1026 cm1, 1052 cm1,
1099 cm1, and 1108 cm1. Since some interstitial O impurities can be transferred
to form C-O complexes with carbon atoms, the generation of thermal donors (TDs)
in CZ Si with a high concentration of C is usually suppressed. However, the
concentration of new donors (NDs) is generally proportional to that of C, which
indicates that C enhances the formation of NDs. The C-O complexes can act as the
nuclei of solid SiOx precipitates and enhance the formation of solid SiOx pre-
cipitates at the temperature below 800  C, but it is not the same case at the
temperature higher than 800  C. Nevertheless, the atomic size of C is smaller
than that of Si, which can cause strain in Si lattice and tend to absorb self-
interstitial Si atoms. The increase of C concentration in CZ Si can enhance oxygen
precipitates, effectively serve the capability for intrinsic gettering (IG) of metal
contamination, and improve IC yields and reliability.

Nitrogen in CZ Silicon

With lightly-doped concentration, nitrogen (N) can play an important role in the
improvement of the performance of Czochralski (CZ) Si. The methods of N-doping
include the utilization of N2 gas protection during crystal growth, the introduction of
Si nitride powders in the molten Si, and the N+ implantation. The solubility of N in
molten Si and solid at 1415  C are 6  1018 cm3 and 4.5  1015 cm3, respectively.
Since the segregation coefficient of N in Si is 7  104, the N concentration in CZ Si
crystal is usually smaller than 5  1015 cm3. Most of the N impurities exist as dimer
in CZ Si, and only 1% of them are located at substitutional sites as donor with an
ionic energy of 17 meV. From the room temperature infrared (IR) absorption
spectrum, N dimer usually exhibits 2 lines of 963 cm1 and 766 cm1. The N
concentration can be derived by the line of 963 cm1 with a conversion factor of
1.83  1017 cm2. N dimer diffuses very fast in CZ Si, and its diffusion coefficient is
3 times higher than interstitial oxygen, about 2  106 cm2/s at 1270  C.
Nitrogen can react with oxygen to form nitrogen–oxygen (N-O) complex in CZ Si
with series of absorption lines in mid-infrared (MIR) and far-infrared (FIR) wave-
length ranges. N-O complex is a kind of shallow active donors. By combining the IR
absorption and the resistivity measurements, it can be found that the elimination of
IR lines during annealing will cause the variation in resistivity or carrier
76 Defects and Impurities in Silicon Materials 1687

concentration of CZ Si. High-temperature annealing can annihilate the electrical

activity of N-O complexes. To dope N in CZ Si can suppress the generation of
thermal donors and new donors.
To dope N in floating-zone (FZ) Si can suppress the formation of interstitial
dislocation loops and vacancy clusters. To dope N in large diameter CZ Si can
change the size and density of voids toward easier elimination of voids at high
temperatures [6]. Theoretical calculation indicates that N dimer first combines with
vacancy dimer to form complexes and then further interacts with oxygen to enhance
the formation of solid SiOx precipitations at high temperatures and emit a large
number of interstitial Si atoms. This will consume a lot of vacancies and therefore
result in the formation of dense voids in small size. Since the N-O complexes and
N-vacancy-O complexes can enhance the nucleation of solid SiOx precipitates, the
intrinsic gettering (IG) technology of CZ Si wafer can be achieved by only one
single-step annealing process with reduced IG thermal budget. Meanwhile, the dense
solid SiOx precipitates in small size induced by N-doping have the capability to lock
dislocations and therefore improve the mechanical strength of wafers [7]. The
indentation experimental results indicate the dislocation slipping distance in
N-doped Si wafer is smaller than that in conventional Si wafer after the same thermal
treatments. Thus, N-doping in large diameter CZ Si can suppress the warpage of
wafer and therefore improve the yield of ICs.

Metallic Impurity in CZ Silicon

Transition metal impurities would contaminate the wafer during the device fabrica-
tion, which is detrimental to the yield of ICs. Most of the transition metals (like Cu,
Ni, and Fe) in CZ Si are located at interstitial sites and the rest ones (like Zn, Pt, and
Au) at substitutional sites. The interstitial metal impurities usually have a large
diffusion coefficient as referred to as fast diffusers. The substitutional metal impu-
rities usually need point defects to help the diffusion, which have a small diffusion
coefficient as referred to as slow diffusers. Among all the metal impurities, Cu is the
fastest diffuser, which can diffuse several mm in one hour at room temperature. The
solubility of transition metals in Si is strongly temperature-dependent, with high
solubility at high temperature and low solubility at room temperature. Therefore, the
metal impurities in the wafer contaminated at high temperature tend to precipitate
out or form complex during the subsequent cooling process. The solubility of metals
in Si also increases with the increase of dopant concentration.
The measurement methods of metal impurities in Si include secondary ion mass
spectroscopy (SIMS), deep-level transient spectroscopy (DLTS), haze test, total
reflection X-ray fluorescence analysis (TXRF), surface photovoltaic (SPV), and
microwave photoconductance degradation (MWPCD). The haze test is the simplest
and easiest way by combining the optical microscopy and selective etch after
annealing the wafers, which has been widely applied in industry.
The metal impurities can form complexes with dopants in CZ Si in the case of
lightly metal contamination, like copper–boron (Cu-B) pairs and iron–oxygen
1688 D. Yang and X. Ma

(Fe-O) pairs. These complexes usually have low thermal stability and can be
decomposed in Si by a low-temperature anneal. However, in the case of heavy
metal contamination, metal impurity precipitates will be formed in CZ Si. The
precipitation mechanisms include homogeneous nucleation and heterogeneous
nucleation. The metal impurities prefer to precipitate at the wafer surface, which is
very detrimental to the yield of ICs. Thus, the metal contamination at the wafer
surface should be eliminated during the fabrication of ICs.
In the process of IC fabrication, the gettering technology is usually used to
remove the metal impurities from the device active region under the wafer surface.
Extrinsic gettering (EG) technology can be achieved by introducing certain amount
of crystalline defects on the wafer backside as gettering sites for metal atoms, which
includes poly-Si deposition gettering, sandblasting at the backside, phosphorus
(P) gettering, and aluminum (Al) gettering. Intrinsic gettering (IG) technology is
based on the SiOx precipitates and induced defects inside the Si substrate as metal
gettering sites, which includes high-low-high three-step annealing technology,
single-step high-temperature annealing technology based on N-doped or Ge-doped
CZ Si, and magic denuded zone (MDZ) based on rapid thermal annealing. For both
intrinsic gettering and extrinsic gettering, the thermal dynamic process of gettering
for the metal impurities on the wafer surface can be divided into three phases, i.e., the
release of metal impurities from the device active region, metal impurities diffusion
from wafer surface toward gettering sites, and the capture of metal impurities at the
gettering sites.

Slip Dislocation

The Si crystal of diamond structure is brittle at room temperature. However, it

becomes ductile at temperatures 780  C and above. Therefore, at high temperatures,
silicon crystals can generate dislocations when sufficiently large stresses are applied.
For IC fabrication, there are several high-temperature thermal processes (e.g.,
epitaxy, oxidation, and diffusion). During heating and cooling, the temperature
gradients between the center and edge of the wafer are created, thus producing
thermal stresses. As such thermally generated stresses exceed the yield strength of
Si, dislocations are generated [8]. Because the thermal stress is greatest at the edge of
wafer, dislocations are most readily generated there. If there are mechanical damages
and micro-cracks at the edge of wafer, it will be conducive to the generation of
dislocations. Once the dislocations occur at the edge of wafer, they will slip to the
interior of the wafer along <110> directions and form slip dislocations. Under
certain conditions, the slip dislocations are significantly generated to form disloca-
tion network, whose pattern depends on the crystallographic orientation of the wafer.
If there are numerous and sizable solid SiOx precipitates in the center of wafer, the
slip dislocations may be initiated there. The slip dislocations can be either 60 or
screw ones.
The generation of slip dislocations is related to the factors including the annealing
temperature, heating/cooling rate, diameter/thickness ratio of wafer, and the grown-
76 Defects and Impurities in Silicon Materials 1689

in solid SiOx precipitates in the wafer. In order to avoid the slip dislocations, the
temperature gradients caused by the thermal processes should be minimized. In
practice, the Si wafers are slowly loaded into or unloaded from the furnace by
computerized control. Moreover, the heating and cooling rates are less than 10  C/
min. The temperature for loading and unloading of silicon wafers generally does not
exceed 800  C. More importantly, the mechanical damages on Si wafers must be
removed to eliminate the source of dislocations. With the increase of diameter to
200 mm and above, the edge of Si wafer should also be polished to remove the
mechanical damages. The increase in silicon wafer diameter leads to a remarkable
addition of weight for Si wafers. In order to avoid the slip dislocations caused by the
self-weight, the Si wafers are horizontally placed during the high-temperature
processes for the fabrication of ICs. Even in such case, the Si wafer supporter should
be carefully optimized. Moreover, the horizontal placement of Si wafers puts more
stringent requirement on the warpage. In certain processes such as epitaxy, the Si
wafers are directly in contact with the heating pedestals. In this case, the slip
dislocations are readily generated if the Si wafers are over-warped.
As for CZ Si crystals used for ICs, slip dislocations may be generated during the
crystal growth. The molten Si reacts with quartz crucible to form volatile SiO gas. If
the SiO volatiles were not removed effectively, they would be deposited onto the
walls of the hot zone and crystal-pulling furnace to form solid SiOx particles. Once
the solid SiOx particles drop down into the molten Si and move to the crystal/melt
interface, dislocations will be generated and then propagate into the growing crystal.
Eventually, the Si crystal will lose its dislocation-free growth mode. In order to
effectively remove the SiO volatiles, the CZ Si growth is generally proceeded under
the protective ambient of Ar with reduced pressure, and, moreover, proper gas
conduction shield is installed in the hot zone to expel the volatiles (e.g., SiO).

Misfit Dislocation

In the formation of emitter and collector regions of bipolar transistors and source/
drain regions of MOS devices, high concentrations of dopant (donor or acceptor)
atoms are introduced into Si lattice by means of diffusion or ion implantation [9].
Note that the ion implantation is generally employed to accomplish doping in the
fabrication of ICs. The dopant atoms are normally located at the substitutional sites
in Si lattice. Due to the mismatch in sizes between dopant atoms and Si atoms, the
lattice distortion is somewhat generated. Usually, the mismatch coefficient,
expressed as (lattice atomic radius - impurity atomic radius)/lattice atomic radius,
can be used to describe the mismatch extent of an impurity atom in Si lattice. Note
that the aforementioned atomic radius refers to the tetrahedral radius of an elemental
crystal. Table 76.1 lists the mismatch coefficients of certain impurities in Si. It can be
seen that in the case of B and P with smaller atomic radius than Si, the local Si lattice
is contracted. While Sb has a larger atomic radius than Si, the local Si lattice is
dilated. As is nearly the same atomic radius as Si, the local Si lattice is hardly
distorted.
1690 D. Yang and X. Ma

If a Si crystal is uniformly doped, the lattice distortion will not bring about
stresses and defects. However, for the doping by means of diffusion or ion implan-
tation, the impurity concentration changes remarkably from the surface to the bulk of
Si wafer and results in nonuniform lattice distortion and local stresses. At sufficiently
high temperatures, as the doping-induced stresses are larger than the yield strength of
Si, the so-called misfit dislocations are generated. For example, as B or P is heavily
doped into the Si wafer with a surface concentration higher than 1020 cm3, a large
amount of misfit dislocations appears. In the case of fabricating bipolar ICs, a
Sb-doped buried layer with a surface concentration of ~1020 cm3 is diffused into
Si substrate prior to the epitaxy process. Since Sb has a much larger atomic radius
than Si, massive misfit dislocations are generated in the epitaxial layer onto the
Sb-doped buried layer. If the doping of Sb is replaced by As, then the misfit
dislocations are hardly formed in the epitaxial layer. Generally, the misfit disloca-
tions form dense networks that are parallel to the surface in the region of the highest
dopant concentration gradient. Hence, they usually do not penetrate the junction so
that the electrical properties of transistors are not affected. Note that the larger
mismatch coefficient of dopant atoms leads to a smaller critical doping concentration
for generating misfit dislocations.

Oxidation-Induced Stacking Faults

As a Si wafer is oxidized at temperatures 900  C and above, the stacking faults may
be generated at the wafer surface. Since such stacking faults are induced by oxida-
tion, they are named after oxidation-induced stacking faults (OSFs or OISFs). The
oxidation of Si wafer leads to a layer of SiO2 which exhibits volume expansion with
respect to Si, thus injecting Si interstitials into Si lattice. The local accumulation and
condensation of Si interstitials result in stacking faults. OSFs occur on {111} planes
bounded by Frank partial dislocations with a Burgers vector a/3 <111>, and they are
extrinsic. The OSFs can deteriorate the reverse current–voltage characteristics of pn
junctions and the gate oxide integrity of metal–oxide-semiconductor transistors
(MOSFETs).
OSFs can be divided into surface and bulk according to their nucleation sites.
(1) The surface OSFs are nucleated on the mechanical or chemical damages and
metal (e.g., Fe, Ni and Cu) contaminants on Si surface. After a short period of
preferential etching, the surface OSFs are manifested as the rod-like structure of
uniform length along the <110> direction. The two surface OSFs intersect at an
angle of 60 on (111) plane and are perpendicular to each other on (100) plane. After
an extended period of preferential etching, the surface OSFs exhibit the shapes of
trapezoid and crescent on (111) and (100) planes, respectively. Nowadays, since the
Si wafer cleaning processes are essentially perfect, the surface OSFs are hardly
generated. (2) Bulk OSFs are nucleated on the solid SiOx precipitates underneath the
Si wafer surface. These plate-like solid SiOx precipitates induce a considerably large
strain field, which can readily absorb the Si interstitials generated by the oxidation of
Si. Then, such absorbed Si interstitials condense into stacking faults. Therefore, the
 76

Table 76.1 Mismatch coefficients for several impurities in silicon

Defects and Impurities in Silicon Materials

Impurity element P As Sb B Al Ga In C Sn
Mismatch coefficient 0.06 0.008 0.16 0.248 0.077 0.077 0.231 0.342 0.200
1691
1692 D. Yang and X. Ma

oxygen concentration in CZ Si should be controlled in a reasonable range in order to

avoid the solid SiOx precipitates becoming the nucleation sites for OSFs. After a
short period of preferential etching, the bulk OSFs are manifested as the rod-like
structure of nonuniform length along <110> directions. With an extended period of
preferential etching, the bulk OSFs exhibit the shapes of trapezoid and ellipse on
(111) and (100) planes, respectively. Moreover, the size and density of bulk OSFs are
dependent on the etching time.
The formation and growth of OSFs depend strongly on oxidation temperature,
time, and ambient as well as the orientation and dopant concentration of Si wafer.
The OSF length can be expressed as L ¼ Atn exp.(Q/kT), where L is OSF length, A
is a constant, t is the oxidation time, n ranges in 0.77–0.84, Q is the activation energy
(~2.3 eV), and T is oxidation temperature. The OSF growth rate of <100> 
oriented Si wafer is larger than that of <111>  oriented silicon wafer. This is
because the oxidation of <100>  oriented Si wafer produces much more Si
interstitials. When oxidized at temperatures above 1150  C, the formation of OSFs
is suppressed, and moreover, the existing OSFs will even shrink. For the heavily
doped n-type Si wafers (dopant concentration higher than 1018 cm3), the OSFs are
hardly generated because the vacancy concentration is considerably high in such Si
wafers, in which the oxidation-induced Si interstitials are essentially recombined
with the vacancies. In contrast, for the heavily doped p-type Si wafers, the OSFs are
readily generated due to the high concentration of Si interstitials in such Si wafers.
The OSFs can be significantly reduced if the Si wafers are annealed at high
temperature in N2 ambient prior to the high-temperature oxidation. Even for the
existing OSFs, they can be annihilated by the high-temperature annealing in N2
ambient. Besides, the chlorine (Cl)-containing oxidation ambient is very advanta-
geous for reducing OSFs. OSF is an important quality index, which largely reflects
crystal quality, surface integrity, and cleanness of Si wafers. Generally, the OSF
density of the Si wafers used for ICs should be less than 100 cm2.

Epitaxial Defects

Epitaxy technology is widely employed in the fabrication of epitaxial Si wafers and

bipolar ICs. The primary defects generated in the Si epitaxial layer include slip
dislocation lines, stacking faults, hillocks, hazes, etc. Such defects have deleterious
effects on various device properties, primarily increasing leakage currents in reverse-
biased junctions.

1. Slip dislocation lines are generated primarily due to the nonuniform heating of
the substrate, which leads to the radial temperature gradient and results in thermal
stresses. As such thermally generated stresses exceed the yield strength of silicon,
they can cause slip dislocation lines. Generally, the thermal stress is greatest at the
edge of substrate, where the onset of dislocations occurs. Then, the dislocations
propagate into the center of substrate. Besides the temperature gradient, the
dopant species and concentration, oxygen content, edge rounding of substrate,
76 Defects and Impurities in Silicon Materials 1693

and other factors also affect the generation of slip dislocation lines. For example,
in the case of epitaxy of high-resistivity layer on the heavily antimony (Sb)-doped
Si substrate, the slip dislocation lines are readily generated.
2. Stacking faults in the epitaxial layer can be generated due to several reasons.
Firstly, if there are stacking faults in the substrate itself, these stacking faults have
the potential to propagate into the growing layer. Secondly, there are particles on
the substrate surface. Such particles may remain from the improper cleaning of Si
substrate or may originate from the substrate pedestal and furnace walls. Thirdly,
the native oxide on the substrate has not been completely removed. The stacking
faults initiated from substrate surface can propagate into the epitaxial layer and
situated on {111} planes. For (100)-oriented epitaxial wafers, the stacking faults
are situated on four {111} planes. In this case, the stacking faults in a complete
square or in a partial square can be microscopically observed after preferential
etching. For (111)-oriented epitaxial wafers, the stacking faults are situated on
3 {111} planes which intersect the surface plane with an angle of 70.54 . In this
case, the stacking faults in a regular triangle can be microscopically observed
after preferential etching. By virtue of the geometrical features of stacking faults
as mentioned above, the thickness of epitaxial layer can be obtained by measuring
the length of stacking fault.
3. Bulges on epitaxial layer are generally manifested as pyramid-shaped hillocks
and irregularly shaped spikes [10]. The spikes are usually larger than the hillocks
in sizes. The density of hillocks is dependent on the epitaxy conditions such as Si
source (e.g., SiHCl3) concentration and substrate temperature. Generally, the
higher substrate temperature favors for elimination of hillocks. The spikes are
normally originated from Si particles on the substrate, on which the Si source gas
dissociates thus to deposit poly-Si layers in multiple crystal directions. The
deposition rate on the Si particles may be several times larger than that on the
substrate surface. Therefore, the spikes can protrude significantly from the sub-
strate surface with a height even to 100 μm.
4. Hazes, as revealed by strong reflected light, exhibit as “fog” on the surface of
epitaxial Si wafer. Hazes are manifested as fine pits under microscopic observa-
tion. Hazes may be originated from the oxidation of wafer surface by the oxidant
(e.g., H2O and O2), the metal contamination, or the residual organics on the
substrates. As an epitaxial Si wafer were observed with severe hazes, the epitaxial
layer would be polycrystalline rather than single-crystalline in nature.

Induced Micro-Defects

Induced micro-defects refer to the micro-defects formed in Si wafers during the

fabrication of ICs. The induced micro-defects primarily include the slip dislocations
caused by temperature gradient, the misfit dislocations due to the difference in size
between dopant and Si atoms, the oxidation-induced stacking faults (OSFs), the
implantation-induced dislocations and stacking faults, the haze arising from metal
precipitation, and the solid SiOx precipitates resulting from the agglomeration of
1694 D. Yang and X. Ma

interstitial oxygen atoms. If such induced micro-defects are located within the active
region of ICs, they will be extremely harmful and such situation must be avoided.
Nevertheless, if the induced micro-defects are generated in the bulk of Si wafers,
then they could be beneficial for ICs as gettering sites.
The Si wafers used for ICs are grown by CZ process. Due to the usage of quartz
crucible, the CZ Si wafers generally contain interstitial oxygen with concentrations
in the range of (0.5–2)  1018 cm3. At the processing temperatures of ICs, the
interstitial oxygen is in a supersaturation state. Accordingly, a part of interstitial
oxygen atoms will agglomerate to react with Si atoms to form solid SiOx (1 < x  2)
precipitates during the fabrication of ICs. The formation of solid SiOx precipitates
consists of nucleation stage and growth stage. Generally, the nucleation occurs at
temperatures not higher than 800  C, while the growth proceeds at temperatures
1000  C and above. The growth of solid SiOx precipitates is accompanied by the
emission of Si interstitials. When there are enough such Si interstitials, they con-
dense into dislocations or stacking faults. Conventionally, the solid SiOx precipitates
and their induced defects such as dislocations and stacking faults in the bulk of Si
wafer are referred to as bulk micro-defects (BMDs). During the fabrication of
integrated circuits, the BMDs can provide the internal gettering effect to remove
the detrimental Fe, Ni, and Cu contaminants from the wafer surface and improve the
IC yield. Conversely, the excessive BMDs will result in the warpage of Si wafers,
which is unfavorable for the alignment in the photolithography process of IC
fabrication. Moreover, if the solid SiOx precipitates and their induced secondary
defects are generated in the active regions of transistors, they will increase the
leakage current. Consequently, in order to increase the IC yields, the Si wafers
should be enabled to generate appropriate amount of solid SiOx precipitates and
the secondary defects in the bulk. This requires the Si wafers to have an ideal initial
oxygen concentration and thermal history (related to the crystal growth and subse-
quent cooling process). Sometimes, special impurity is needed to dope into Si crystal
to enhance the precipitation of solid SiOx.
Along with the shrinkage of feature size of ICs, the diameter of silicon wafers
becomes ever larger to reduce the manufacturing cost of ICs. After entering twenty-
first century, the diameter of primary Si wafers has reached 300 mm and it may also
be increased to 450 mm in the future. Such large-diameter Si crystals are generally
grown under magnetic field. Due to the suppression of convection in the molten Si
by the magnetic field, the initial concentration of oxygen incorporated into the Si
crystal can be reduced to some extent, however, which is not favorable for the
formation of BMDs associated with the solid SiOx precipitates, and thus degrades
the intrinsic gettering (IG) capability of Si wafers. Such undesirable condition can be
changed by adding an appropriate amount of N into CZ Si crystal. It has been well
proved that N-doping can enhance the precipitation of solid SiOx in CZ Si wafers
under different conditions. Moreover, N-doping is beneficial to improve the mechan-
ical strength of Si wafers and makes the voids smaller and easier to annihilate.
Owing to the aforementioned merits, the N-doped CZ Si wafers have been widely
employed to fabricate advanced ICs. Besides, the former MEMC Company in USA
invented a so-called MDZ ® process [11] which is an intrinsic gettering process based
76 Defects and Impurities in Silicon Materials 1695

on rapid thermal processing (RTP). In the MDZ ® process, the CZ Si wafers are firstly
subjected to the RTP at high temperatures (e.g., 1250  C) in argon atmosphere to
form a vacancy concentration profile that gradually increases from the surface to the
bulk. Such a vacancy concentration profile enables the formation of the high-density
BMDs and the well-defined denuded zone in the near-surface region in the subse-
quent low-temperature to high-temperature two-step annealing process. Such defect-
engineered Si wafers can meet the requirements of advanced ICs.

References
1. R. Falster, V.V. Voronkov, F. Quast, Phys. Status Solidi B 222, 219 (2000)
2. Y. Wang, S. Chen, X. Dong, Dislocation Theory and its Application (Metallurgical Industry
Press, Beijing, 2007)
3. S. Yang, D. Ding, Fundamental of Crystal Dislocation Theory (Science Press, Beijing, 1998)
4. D. Que, X. Chen, Silicon Materials Science and Technology (Zhejiang University Press,
Hangzhou, 2000)
5. T. Ueki, M. Itsumi, T. Takeda, Jpn. J. Appl. Phys. 36, 1781 (1997)
6. X. Yu, J. Chen, X. Ma, D. Yang, Impurity engineering of Czochralski silicon. Mat. Sci. Eng. R
74, 1–33 (2013)
7. X. Yu, D. Yang, X. Ma, J. Yang, L. Li, D. Que, Grown-in defects in nitrogen-doped Czochralski
silicon. J. Appl. Phys. 92, 188–195 (2002)
8. K. Huang, R. Han, Fundamental of Semiconductor Physics (Science Press, Beijing, 2010)
9. N.G. Einspruch, H. Huff, VLSI Electronics: Microstructure Science Silicon Materials (Aca-
demic Press, London, 1985)
10. M. Lin, Silicon Wafer Technology (Chuan Hwa Sci&Tech Publishing Ltd., Taibei, 1999)
11. MDZ process, http://www.sunedisonsemi.com/index.php?view¼Gettering&11¼27&12¼55&
13¼56. Accessed 01 Jun 2023
Compound Semiconductors
77
Deren Yang, Jingfeng Kang, and Xuegong Yu

Contents
Compound Semiconductor Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
Requirement of ICs for Compound Semiconductor Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698
Fabrication of Monocrystalline GaAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
Thermal Treatment of Gallium Arsenide and Wafer Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
GaAs Epitaxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
Properties of InP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
Fabrication of Monocrystalline InP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
Indium Gallium Arsenic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
Monocrystalline GaN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
GaN Thin Film . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
Crystalline Al2O3 and Substrate Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
Monocrystalline Si-Carbide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
Silicon Carbide Film . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
Compound Quantum Well Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
Compound Quantum Dot Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715

Abstract
Compound semiconductor materials can meet various requirements as advanced
materials for the information era, which can be roughly divided into second- and
third-generation semiconductor materials. The second-generation semiconductor
materials mainly include GaAs, InAs, InP, etc., and are often used to fabricate
high-speed, high frequency electronic devices, and optical electronic devices. The
third generation of semiconductor materials is represented by silicon carbide (SiC),
gallium nitride (GaN), etc., which have large band gap, and are generally used for

D. Yang (*) · X. Yu
State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China
e-mail: mseyang@zju.edu.cn
J. Kang
School of Electronics Engineering and Computer Science, Peking University, Beijing, China

© Publishing House of Electronics Industry 2024 1697

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_77
1698 D. Yang et al.

power electronic devices, high frequency devices, LEDs, and semiconductor lasers.
This chapter focuses on the growth methods, physical and optoelectronic properties
of various compound semiconductor materials, and their substrate materials.

Keywords
Compound semiconductors · GaAs · InP · Indium gallium arsenic · GaN ·
Al2O3 · Silicon carbide · Film · Quantum well · Quantum dot materials

Compound Semiconductor Materials

There are various compound semiconductor (CS) materials with various element
components. The energy band structures of CS materials are diverse as direct or indirect
bandgap, wide bandgap, and high electron mobility materials as greatly desired by
electronic devices. Compared with elemental semiconductors (e.g., Si and Ge), the
number of CS is numerous and rich in physical properties, which can meet various
requirements as advanced materials for the information era. According to the material’s
band gap and the development history, CS materials can be roughly divided into second-
and third-generation semiconductor materials. (1) The second-generation semiconductor
mainly includes GaAs, InAs, InP, and their ternary compounds. They have high carrier
mobility compared with the first generation of elemental semiconductors (i.e., Si and
Ge). Most of them have a direct band gap with high luminous efficiency, which can be
used to fabricate high-speed and high frequency electronic devices used in communi-
cation, radar, electronic countermeasure, and optical electronic devices (e.g., red, green,
infrared LEDs, and laser diodes). (2) The third generation of semiconductor materials is
represented by silicon carbide (SiC) and gallium nitride (GaN), etc., which have large
band gap, high thermal conductivity, high critical breakdown field, high chemical
stability, and radiation tolerance. Therefore, they can be used for power electronic
devices operating under harsh environments (e.g., high temperature, high pressure,
and strong radiation) not achievable by Si devices. Due to the carrier localization-
induced high electro-optical conversion efficiency, GaN is also very suitable for fabri-
cating blue and violent LEDs and semiconductor lasers.
In addition, with the continuous development of techniques for materials growth (e.g.,
MOCVD and MBE), CS with low-dimensional quantum wells (QW), quantum dots
(QD), and new 2-D structures have shown superior materials properties (than Si) and are
promising in new applications (e.g., detectors, solar cells, lasers, and many other fields).

Requirement of ICs for Compound Semiconductor Materials

The demand for semiconductor materials in ICs can be traced back to the
beginning of semiconductor devices. Crystal germanium (Ge) was the first used
to prepare semiconductor devices, and then the Si devices have better thermal
77 Compound Semiconductors 1699

stability and superior performance. As a result, crystalline Si has been widely

used and dominated in IC industry. Compound semiconductor (CS) materials
have obvious advantages over the first generation of semiconductors (i.e., Si and
Ge) in terms of band gap, carrier mobility, and luminous efficiency. The fabri-
cated devices based on CS materials can operate at high temperature and fre-
quency that are not achievable by traditional Si devices. The applications include
microwave devices, ultrahigh-speed electronic devices, high-efficiency LEDs,
and semiconductor lasers.
From the material point of view, in addition to the above basic material charac-
teristics, CS materials have other advantages over element semiconductors in that
they can form compounds with multiple elements through solid solute or mixed
crystals. The energy band structure and the band gap can be tuned by the composi-
tion of elements. On this basis, heterostructures and quantum well structures can be
formed, and the performance of CS devices can be greatly expanded by means of
energy band engineering to modulate the transport and recombination processes of
carriers.
With the continuous improvement of the quality of CS materials and the
manufacturing process of ICs, the applications of CS based devices are also
expanding. In addition to the demanding applications in military electronic equip-
ment, the continuous development of mobile phones and mobile communication
devices also have a great demand for compound semiconductor materials in recent
years. Especially, the rapid development of 5G mobile communication technology
requires mobile terminals to have multi-bands, multi-modes, multi-functions, and
high performance [1]. In general, Si alone cannot meet the optimal performance of
IC. It is necessary to achieve the integration of different materials and devices, e.g.,
Si, germanium silicon (SiGe), gallium arsenide (GaAs), and gallium nitride (GaN) in
the same package and system to achieve the better performance. In addition, with the
rapid development of consumer electronics, not only the Wi-Fi market is larger but
also the wireless control and data connection of household electronic products is
increasing. The wireless of electronic equipment will promote the development and
applications of CS IC technology. At the same time, with the popularity of automo-
tive electronic products such as anti-collision radar, autonomous driving, etc.,
indium phosphide (InP), GaAs, SiGe, and other CS materials with excellent perfor-
mance will play a key role in microwave application. The wide application of the
new generation of optical fiber communication technology and the maturing of
optical communication equipment will further promote the development of CS ICs
rapidly.
From the application point of view, CS materials still need further improve-
ments in the following aspects: improve the crystal quality of CS materials and
fully bring the advantages of material characteristics; carry out research on
heterogeneous integrated substrate materials, especially the integration with
traditional Si devices to achieve high-density integration, miniaturization, and
versatility; develop large area substrates and epitaxial materials with reduced cost
of materials and devices.
1700 D. Yang et al.

Fabrication of Monocrystalline GaAs

Main methods for the growth of monocrystalline gallium arsenide (as mono-GaAs)
include horizontal Bridgman method (HB), horizontal gradient freeze (HGF), liquid
encapsulant CZ (LEC), vapor pressure control CZ (VCZ), vertical Bridgman method
(VB), and the vertical gradient freeze method (VGF).
(1) HB (horizontal Bridgman) method: The growth of mono-GaAs by HB is
illustrated in Fig. 77.1. The left side of the furnace tube is the high-temperature zone
and the right side is the low temperature zone. The quartz tube is located in the
furnace, and the quartz boat on the left side of the quartz tube contains crystal seed
and polycrystalline GaAs. The polycrystalline GaAs is liquid at high temperature,
and the seed is immersed in it. When the quartz chamber moves from the left to the
right, the temperature decreases and the molten GaAs in the quartz tube gradually
crystallizes to form monocrystalline GaAs. The chamber on the right side of the
quartz tube contains solid As and is kept at low temperature in order to maintain the
balance between the As vapor pressure and the decomposition of GaAs. (2) HGF
(horizontal gradient freeze) method: HGF is similar with HB. The difference is
that the quartz tube does not need to move during the growth process, and the growth
is achieved by controlling the temperature of the tube with multiple heaters in the
high and medium temperature zones. The dislocation density of GaAs prepared by
HB and HGF method is very low, and the uniformity is quite good. HB and HGF are
the main methods for massive production of mono-GaAs. (3) The LEC (liquid
encapsulant CZ) method: As illustrated in Fig. 77.2, the LEC was proposed by
E. P. A. Metz in 1962, and J. B. Mullin firstly applied this method to grow mono-
GaAs in 1965. The crucible is commonly made of boron nitride (BN), and boron
oxide (B2O3) is used as the liquid sealing agent. The crucible and crystal seed are
connected to the rotary rod. During the growth process, Ga and As firstly react to
form polycrystalline GaAs (poly-GaAs), which becomes molten after further
heating. At the right temperature, the seed and the crucible are rotated in reverse
so that the seed comes into contact with the molten GaAs, and then mono-GaAs
crystal begins to grow on the seed. Finally, large-size crystal would grow up as the
temperature continuously drops and the seed crystal holder is lifted at a certain
speed. At present, LEC technology is the main method to prepare large-size undoped

Fig. 77.1 The schematic

diagram of the equipment for
HB method [2]
77 Compound Semiconductors 1701

Fig. 77.2 The schematic

diagram of the equipment for
LEC method [2]

semi-insulating GaAs single crystals with controlled carbon (C) content. However,
due to the large temperature gradient, the dislocation density in the crystal is
relatively higher.
(4) VCZ (vapor pressure control CZ) method: VCZ is an improvement of the
LEC method. The biggest difference is that the balance between the As vapor and the
decomposition of GaAs is controlled by the chamber vapor pressure. The crystal
growth can be achieved under a more stable environment, and the dislocation density
is lower at a certain wafer size. (5) VB (vertical Bridgman) method: The VB
equipment is illustrated in Fig. 77.3. This equipment is simple, and the temperature
gradient is relatively small. The density of dislocation in vertical Bridgment grown
GaAs is very low, which is suitable for massive production. Meanwhile, it is not
necessary to change the relative position of the reaction chamber and the heater,
which uses computer program to control the temperature gradient and realize the
relative movement of the solid-liquid interface to achieve the crystal growth. (6)
VGF (vertical gradient freeze) method: VGF is suitable for the preparation of
large diameter, low dislocation density, and high-quality GaAs single crystal, but the
disadvantage is that the crystal growth cannot be monitored in real time.

Thermal Treatment of Gallium Arsenide and Wafer Processing

The production of GaAs microelectronic and optic devices is based on monocrys-

talline GaAs (mono-GaAs) substrates. There are two mainstream methods for the
growth of mono-GaAs substrate, i.e., vertical gradient freezing (VGF) and liquid
encapsulation Czochralski (LEC). The fabrication process of GaAs substrate wafers
1702 D. Yang et al.

Fig. 77.3 The schematic

diagram of the equipment for
VB method [2]

includes cutting, annealing, lapping, polishing, and cleaning. (1) Cutting crystal rod
into wafer is the first step of wafer processing. There are three important aspects
during processing, i.e., accurate orientation, appropriate profile, and minimum kerf
loss. Previously, the inner saw method is used to cut wafers with shortcomings of
low efficiency and high wastage (e.g., kerf loss up to 400 μm). Concurrent wire saw
method for cutting is more effective and hundreds of wafers can be processed
simultaneously. Kerf loss can be reduced to below 100 μm by using Copper-covered
steel wire accompanied with oily mortar. (2) Annealing is required since all sub-
strates are high resistivity material. The undoped crystals with semi-insulating
properties are resulted from the balance of deep-level traps and shallow-level
acceptor impurities. Through thermal treatment at 1050
C in gaseous arsenic
atmosphere, defect density can be significantly reduced to achieve enhanced perfor-
mance. (3) Lapping is a process of removing mechanical damage before polishing
and achieve the high geometric precision. Grinding wheel lapping and mortar
lapping can be carried out according to different requirements. Diamond grinding
wheel plate with cooling liquid is generally used for grinding wheel lapping method,
and glass plate with alumina slurry is usually used for mortar lapping method. In
addition, single-side lapping and double-side lapping are performed on thinner
wafers and thicker wafers, respectively. Wafers after lapping must be treated with
chemical etching and rinsing to further remove lapping process-induced mechanical
damages. (4) Generally, chemical mechanical polishing (CMP) technique is used
as the final polishing of wafers. CMP slurry includes the solution of alkaline oxidizer
containing chlorine (Cl) and colloidal Si. CMP technique takes advantages of both
chemical and mechanical effects to achieve high geometric precision, low damage,
and high surface smoothness simultaneously. The surface roughness must be less
than 1 nm and no defects (e.g., scratches, pits, and hazes). Normally, the rough
polishing process uses pads and agents with stronger mechanical removal ability to
77 Compound Semiconductors 1703

ensure the good geometric precision. Since GaAs is easily oxidized, by using single-
side fine polishing technique as the final polishing, it is easier to remove the GaAs
wafer from the slurry as soon as possible and prevent the process-induced oxidation.
Furthermore, the single-side fine polishing process with strong chemical removal
ability can achieve less mechanical damage and less roughness for GaAs wafers. (5)
Cleaning refers to the electronic-level process of ultraclean cleaning for polished
wafers. At present, the chemical wet cleaning process is mainly used to obtain a
clean surface with ultralow surface particle and impurity concentration. Therefore,
wafers can be used directly by opening the wafer box for ion implantation or
epitaxial growth without any treatment. The key technologies of being used directly
by opening the wafer box are high geometric accuracy, ultralow damage, ultralow
surface particle, high surface purity, and stable surface passivation layer at the same
time, and can maintain its characteristics for a long time.
Due to the rapid development of gallium arsenide devices and circuits, and the
increasing size of wafers, the strict requirements for wafer smoothness, surface
cleanliness, and defect density will continue to increase, and the processing cost
needs to be further reduced.

GaAs Epitaxy

GaAs epitaxial technology began in the 1960s. The defect density of epitaxial grown
GaAs is small with high purity and good consistency. Multilayer homogeneous or
heterogeneous structure can also be grown to meet the requirements of optoelec-
tronic, microelectronics, and other types of devices. The combination of GaAs
epitaxial growth on single crystal substrate has become the core technology of
many device manufacturing. Both vapor phase epitaxial (VPE) and liquid phase
epitaxial (LPE) can be used to grow GaAs epitaxial layer. The VPE growth was
developed earlier, including halogenated VPE method, hydride VPE, and metal
organic chemical vapor deposition (MOCVD). Molecular beam epitaxial (MBE),
as an important compound semiconductor epitaxial growth technology, has been
widely used in the growth of single crystalline films of various compounds,
including GaAs.
Liquid phase epitaxial (LPE) method refers to the method of using supersaturated
solution to grow epitaxial layer on single crystalline substrate. As the earliest GaAs
epitaxial technology [3], it was proposed by H. Nelson in 1963. The reaction is
carried out in the quartz tube. Ga and As source are located on the upper layer of the
graphite boat, and the lower layer is the GaAs substrate. At the beginning of the
reaction, H2 is first passed through the quartz tube to remove air from the inside, and
then the quartz tube is heated to melt the Ga and As reaction source. It is necessary to
maintain for 18–26 h at high temperature to remove possible impurities. Finally,
epitaxial growth began with the decreased temperature after the substrate is loaded
into the graphite boat to make the substrate contact with the melted solution. The
advantages of LPE include fast growth rate, high quality of epitaxial layer, and high
purity. The disadvantage is difficult to control the doping of epitaxial layer and the
1704 D. Yang et al.

composition uniformity of elements in compound semiconductor. Besides, it is not

suitable for growing ultrathin layers with complex structures, such as quantum wells
(QW) and superlattice.
Metallic organic chemical vapor deposition (MOCVD) is a VPE growth tech-
nique that mainly uses metal organic precursors for the epitaxial layer growth of
compound semiconductors [4]. For example, trimethylgallium (TMGa) and arsine
(AsH3) are used as Ga source and As source, respectively, to grow GaAs epitaxial
layer on the sapphire substrate with hydrogen as carrier gas. With the development of
MOCVD technology and the purity improvement of metalorganic source materials,
MOCVD has shown great advantages in semiconductor epitaxial of compounds
such as GaAs. The massive production of various compounds can be grown by
MOCVD. It is also suitable for the growth of heterostructures with thick layers,
complex compositions, and doping, such as multi-junction solar cells. Low-pressure
MOCVD can achieve faster gas switching and reduce the storage effect during the
growth and can achieve steep epitaxial and doping interfaces.
Molecular beam epitaxial (MBE) is a widely used semiconductor manufacturing
technology developed by Bell Labs in 1960s. Under ultrahigh vacuum
(108–1012 Torr), MBE heats each element or alloy to gaseous phases that make
up the single crystalline epitaxial material at a certain temperature and then effuses
them to the heated substrate in the form of a molecular beam. The epitaxial growth is
achieved through the migration of atoms on the substrate surface and merging into
the lattice site. MBE has the following advantages: The growth rate is very low, and
it is suitable to grow ultrathin epitaxial layers with a precise thickness control. Due to
the high vacuum growth environment, the prepared materials have high purity. A
very steep and flat heterogeneous interface can be obtained, which is suitable for the
growth of 2-D electronic gas (2DEG) structures with high electron mobility, high-
quality multilayered quantum wells (QW), and superlattice. Reflective high-energy
electron diffraction (RHEED) can be used for in situ observation and analysis, which
is suitable for the research in epitaxial growth mechanism and surface dynamics.
MBE has been used to grow GaAs epitaxial layers with high purity and low defect
density. This high-quality GaAs is widely used in high electron mobility transistors
(HEMT) and circuits, QW lasers, cascade lasers, infrared detectors, and other
optoelectronic devices. In addition, GaAs epitaxial layers grown at low temperature
with MBE technology have high resistivity. After annealing, lattice mismatch is
greatly reduced, and the crystal quality of epitaxial layers is greatly improved.

Properties of InP

InP is synthesized by Dill in 1910, and its molecular weight is 145.795 with the
density of 4.78 g/cm3 and the microhardness of 435 mm1. InP crystals are fragile
and soft, with a dark gray appearance and metallic luster. At room temperature, InP is
77 Compound Semiconductors 1705

stable in the atmosphere. Its surface oxidation rate is very low. InP begins to
decompose at 360
C.
InP has the zinc blende lattice structure in the atmosphere. Its lattice structure and
crystal orientation are shown in Fig 77.4. The lattice constant is 5.8687 A. As the
pressure increases, the structure of InP can be transformed to the NaCl-type face-
centered cubic structure. At room temperature, it has a direct band gap of 1.35 eV
with the melting point of 1335
K. InP is a direct band gap semiconductor material
capable emitting light of 0. 92 μm. For InP, the electron mobility is up to
4600 cm2/(Vs) and the hole mobility is 15 cm2/(Vs). Its thermal conductivity is
0.7 W/(cmK), which is superior to that of GaAs. InP has potential applications in the
fields of optoelectronics and electronic devices. The operation wavelength of
InGaAsP or InGaAs, which is lattice matched with InP, ranges from 0.92 μm to
1.6 μm. The heterostructures of InGaAsP/InP on InP substrate can be used to
fabricate the light sources and detectors with a very low transmitting loss in the
long-wave fiber-optic communications industry.
During 1970s, InP-based long wavelength laser was developed. During 1980s,
the InP lasers have been widely used in the fiber-optic communications engineering.
It has been found that InP is the only material which can be used to fabricate the
lasers and detectors in the long-distance fiber-optic communications, and it is
becoming increasingly important. InP has very high electron mobility and its lattice
can match with InGaAs very well. It is also the best substrate to fabricate the
microwave devices and high-speed/frequency devices (e.g., HEMT and HBT). InP
also has very high intervalley electron transfer effect which is superior to GaAs to
fabricate the high-speed/frequency device. MESFETs and electro-optical ICs based
on semi-insulating InP substrates have very wide applications. To sum up, InP has
become an important material to fabricate the optoelectronics devices which have
wide and important applications in solid state light emitting, microwave and fiber-
optic communications, guidance/navigation, as well as satellites systems in civilian
and military industries.

Fig. 77.4 The lattice

structure of crystal InP
1706 D. Yang et al.

Fabrication of Monocrystalline InP

The synthesis of monocrystalline InP (mono-InP) crystals is a phase transition

process in which the melt (liquid phase) is transformed into a solid. InP is the
earliest prepared material in III–V compound semiconductors. However, it is diffi-
cult to grow high-quality and large-size mono-InP because the formation of twins
can result in low crystallization rate and poor crystallization quality during the
growth. At present, the size of commercial mono-InP is still small and expensive,
so the application of InP is greatly restricted. The growth of InP is mainly based on
the growth techniques of GaAs and improved according to the growth characteristics
of InP. According to the growth direction, it can be divided into two categories,
horizontal growth and vertical growth. At present, the commonly used methods are
liquid encapsulation Czochralski (LEC) technology, vapor pressure control CZ
(VCZ) technology, vertical gradient freeze (VGF) and vertical Bridgman
(VB) technology, horizontal gradient freeze (HGF) and horizontal Bridgman
(HB) technology, etc.
LEC growth technology was the main method to prepare InP single crystal and
mature to prepare large-size InP single crystal. However, the dislocation density is
much higher due to the large temperature gradient in the growth system. Reducing
the temperature gradient will cause the crystal surface dissociation and leads to
difficulty of crystallization. In order to grow InP with low dislocation density and
high quality, the vapor pressure control CZ (VCZ) technology used in GaAs growth
is introduced into InP crystal growth, which can solve the contradiction in the
abovementioned LEC technology well, but the cost is relatively high, and the
production efficiency is far less than LEC technology.
In the above traditional direct pull growth system, the high axial and radial
temperature gradients make the InP single crystal suffer with large thermal stress
during the crystallization, which inevitably causes an increase of the dislocation
density in the InP single crystal. Therefore, it is difficult to produce high-quality InP
single crystal. In order to solve this problem, vertical gradient freeze (VGF) tech-
nology and vertical Bridgman (VB) technology are used to grow mono-InP. In these
systems, the temperature gradient is smaller and the growth rate is slower. As a
result, the crystal is subjected to less thermal stress. In addition, the chemical ratio of
mono-InP can be accurately controlled during the growth process. Thus, high-
quality mono-InP crystals with very low dislocation density can be produced.
However, these methods suffer from low productivity and high cost.
Among the various improved mono-InP growth methods, liquid encapsulation
CZ (LEC) technology is still the major method for industrial production of various
types of InP monocrystalline, while vapor pressure control CZ (VCZ) technology,
vertical gradient freeze (VGF), and vertical Bridgman (VB) technology are only
used in certain devices that require less residual stress and lower dislocation density.
For InP monocrystalline crystals, the most important thing is to include how to
increase the amount of slices, increase the diameter of single crystal, improve the
quality, and further reduce costs.
77 Compound Semiconductors 1707

Table 77.1 The bandgap, lattice constant, and cutoff wavelength of several III–V family semi-
conductor materials
Material name Band gap/eV Lattice constant/nm Cutoff wavelength/μm
GaAs 1.428 0.56533 0.87
InAs 0.354 0.60583 3.5
GaP 2.25 0.54505 0.55
InP 1.35 0.5868 0.92
In0.53Ga0.47As 0.74 0.5869 1.68

Indium Gallium Arsenic

Indium gallium arsenic (InGaAs) is a ternary compound composed of In, Ga, and
As. It is a III–V semiconductor material with a direct band gap, which is formed
by mixing the GaAs of proportion x and the InAs of proportion 1-x to form an
In1-xGaxAs alloy compound. Since these two materials can be mixed in any ratio, the
band gap of the In1xGaxAs film can be adjusted from 1.424 eV (the band gap of
GaAs at 300
K) to 0.354 eV (the band gap of InAs at 300
K), the lattice constant can
be changed from 0.56534 nm (GaAs) to 0.60585 nm (InAs), and the cutoff wave-
length is changed from 0.87 μm (GaAs) to 3.5 μm (InAs) [5].The forbidden bandgap,
lattice constant, and cutoff wavelength of several common III–V semiconductor
materials are given in Table 77.1.
InGaAs single crystalline thin film can be epitaxial grown on GaAs, InAs, and
InP single crystalline substrates by means of metal organic chemical vapor deposi-
tion (MOCVD), molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), and
liquid phase epitaxy (LPE). In1xGaxAs films, which are generally grown on GaAs
and InAs single crystalline substrates, have properties similar to those of single
crystalline GaAs and InAs substrates, respectively, due to the small lattice mismatch
between the epitaxial film and the substrate. However, the In0.53Ga0.47As film, which
is lattice-matched to the InP substrate, is a semiconductor material that is different
from the GaAs, InAs, and InP single crystalline substrates. At room temperature, the
forbidden bandgap of In0.53Ga0.47As film is 0.74 eV, the electron mobility is
8450 cm2/(V∙s) [6], and the effective masses of electrons and holes are 0.041m0
[7] and 0.051 m0 [8] (m0¼9.111031 kg), respectively. InGaAs films can be used
to fabricate optoelectronic devices such as solar cells, superlattice infrared detectors,
and quantum well lasers.

Monocrystalline GaN

Gallium nitride (GaN) is one of the third-generation semiconductor materials after

Si, Ge, and GaAs, with a wide direct band gap (3.49 eV) as well as excellent
chemical and physical properties including high-temperature tolerance, high
1708 D. Yang et al.

breakdown electric field, and high electron saturation velocity. As a result, it has a
wide range of applications in semiconductor lighting, high-temperature/high fre-
quency electronic, and power electronic devices. GaN crystals are generally the
Wurtzite structures, and there is also a metastable cubic zinc blende structure. The
zinc blende structure, also known as cubic zinc sulfide structure, belongs to the cubic
lattice system with the face-centered cubic (fcc) lattice. The structure diagram is
shown in Fig. 77.5. The Wurtzite structure, also known as the hexagonal zinc sulfide
structure, belongs to the hexagonal lattice system. The structure is shown in
Fig. 77.6.
The growth methods of monocrystalline GaN (mono-GaN) include: ultrahigh
nitrogen (N2) pressure method, solution growth method, ammonothermal growth
method, HVPE, and so on. (1) HVPE is the earliest technique used to prepare mono-
GaN, and the growth system is shown in Fig. 77.7. The GaCl3 produced by the
reaction of HCl gas with high-temperature Ga metal would react with NH3 on the
substrate surface to form GaN. The thick GaN layer is further stripped from the

Fig. 77.5 Zinc blende

structure of GaN

Fig. 77.6 Wurtzite structure

of GaN
77 Compound Semiconductors 1709

Fig. 77.7 HVPE system for GaN epitaxy

substrate by laser lift off process. The advantage of HVPE is that the growth speed is
very fast, and the monocrystalline GaN is of high quality. But there are inherent
defects by the high-temperature reaction and strong corrosion. (2) Ammonothermal
growth method grows single crystalline GaN by adding the seed crystal, polycrys-
talline GaN material, mineralization agent, and other materials into a closed auto-
clave with heating. Although the growth temperature is low in ammonothermal
growth method, the growth rate is slow and difficult to obtain high-purity materials
due to the metal contamination. (3) The high-pressure N solution (HPNS) method
is used to grow GaN by incorporating nitrogen into the molten Ga under high
pressure and form monocrystalline GaN during the cooling down process based on
the supersaturation mechanism. The quality of GaN crystals prepared by HPNS
method is very good; however, the high temperature and high pressure are critical for
the equipment due to the complex control of reaction conditions.

GaN Thin Film

Gallium nitride (GaN)-based electronic and optoelectronic devices are generally

processed on epitaxial films, so the growth of GaN films plays an important role in
the research of the III-nitride materials and devices. At present, the major techniques
of growing GaN films are HVPE, MOCVD, and MBE. Besides, pulsed laser
deposition, magnetron sputtering, and solgel method can also be used to grow
GaN films. (1) HVPE method usually uses sapphire as the substrate and GaN
films can be grown at low cost with a high growth rate of 100–200 μm/h. Compared
with the MOCVD and MBE, the main drawback is the poor film uniformity, thus it is
not suitable for the growth of fine epitaxial structures. (2) MOCVD is the most
widely used method to grow GaN films. Ammonia and TMGa are used as N and Ga
sources, respectively. GaN is formed by thermal decomposition and reaction on the
substrate surface at a temperature around 1000
C. MOCVD method is the most
successful technology for the massive production of GaN devices. (3) MBE epitax-
ial growth technology allows the real-time monitoring of growth process and does
not require high growth temperature. The film uniformity is quite good. According to
the difference of source materials, it can be divided into two ways. The first one uses
1710 D. Yang et al.

molecular beam of Ga metal as Ga source and ammonia as a source of N to form

GaN on the substrate surface. The second way uses Ga metal as Ga source and N
plasma as the source of N. The plasma-generated nitrogen radicals are greatly
activated in the second process, and the growth rate and the quality of GaN films
have been greatly improved.
There have been many studies on the growth and the characterization of GaN
films in the past, but there are still several technical problems not solved yet: how to
grow high-quality GaN films with low-density dislocation on large mismatched
substrates; how to achieve high efficiency in p-type doping; how to reduce the
trapping effect and the reliability issue induced by deep levels in the high resistivity
buffer layer of lateral electronic devices.

Crystalline Al2O3 and Substrate Materials

The dominant component in sapphire is Al2O3, which is composed by three oxygen

atoms (as O) and two aluminum (as Al) atoms in a covalent bond type. The crystal
structure belongs to the hexagonal lattice system. Pure Al2O3 is transparent and
colorless. Due to the presence of a variety of impurity ions, sapphire crystals in
nature can appear in different colors. Sapphire has very good physical and chemical
properties, including high-temperature resistant, antifriction, antiacid and anti-alkali
corrosion, etc. Sapphire is very hard, and the Moh’s hardness is only slightly smaller
than the diamond. The melting and boiling points are 2050
C and 3500
C,
respectively. The maximum operating temperature can be up to 1900
C. Sapphire
is an important industrial material, widely used in national defense, aerospace, laser
technology, civil industry, etc. Sapphire is also an ideal substrate material, playing an
important role in semiconductor light-emitting diodes (LEDs), Si-on-insulator (SOI),
Si-on-sapphire (SOS), and nanostructured films for large-scale ICs.
As one of the most commonly used substrate materials, sapphire belongs to the
trigonal system with hexagonal symmetry. Sapphire preparation process is relatively
mature, low price, easy to clean and treatment, and stable at high temperature. In
addition, the stable production of large-size sapphire substrates is suitable and
achievable. The high-temperature stability is quite good. Especially in GaN-based
LEDs, due to the difficulties and high cost of large area freestanding GaN substrate,
the heterogeneous growth of GaN on sapphire substrate has become the major
choice. At present, the commonly used substrate materials for GaN are sapphire,
SiC, AlN, oxide, Si, and GaAs. Among them, GaN-on-sapphire has overcome other
solutions in both cost and compatibility. The fabrication process on sapphire sub-
strate is mature and stable with good mechanical strength. Moreover, the dislocation
density in epitaxial GaN film could be further reduced with a patterned sapphire
substrate (PSS) and the illuminance efficiency of LED could be as high as 50%.
However, there are still some inherent problems in sapphire substrate, such as: the
sapphire substrate itself not electrical conductive; it is not conducive to the formation
of vertical structure; low thermal conductivity; and the thermal dispersion perfor-
mance is relatively poor for device based on sapphire substrate.
77 Compound Semiconductors 1711

Monocrystalline Si-Carbide

Silicon carbide (SiC), as one of the important third generation semiconductor

materials, is a typical wide band gap semiconductor. The band gap of SiC is an
indirect band gap of 2.3–3.3 eV. There are more than 200 different crystalline forms
in SiC, i.e., homogeneous polymorphism, and the crystal structure can be different
under the same stoichiometry. There are three main cell structures of SiC, namely
cubic cell (sphalerite structure), hexagonal cell (Wurtzite structure), and rhombic
cell, which are expressed by C, H, and R, respectively. There are three locations in
the dense packing system, which are represented by A, B, and C, respectively. As
shown in Fig. 77.8, zinc blende structure is characterized by 3C-SiC or b-SiC if the
order of atomic accumulation is ABC-ABC. . . and the Wurtzite structures are
AB-AB. . ., ABCB-ABCB. . ., and ABCACB-ABCACB. . .., denoted as 2H-SiC,
4H-SiC, and 6H-SiC, respectively. Apart from 3C-SiC, other structures are collec-
tively referred to as α-SiC. The most commonly used SiC crystals for devices are
3C-SiC, 4H-SiC, and 6H-SiC.
At atmospheric pressure, SiC can sublimate directly at 2830
C without forming
a liquid state as shown in Fig. 77.9. In 1955, Lely produced 3C-SiC twins by
seedless crystal sublimation. The quality of crystal obtained by Lely method is
very high, but it cannot grow specific crystal orientation and the growth efficiency
is low. At present, the main growth method of high-quality and large-size SiC
single crystal is the seed sublimation method (PVT method) based on the physical
vapor transport technology, also known as improved Lely method. The method is
briefly described here: SiC powders are heated to over 2000
C in a crucible of the
reaction chamber and then decomposed into gas molecules containing Si and
C. These gas molecules are condensed to the cooler surface of the seed crystal
through the temperature gradient between the source and the seed crystal, thus
growing SiC single crystals.

Fig. 77.8 The crystal structures of 3C-SiC, 4H-SiC, and 6H-SiC

1712 D. Yang et al.

Fig. 77.9 Phase diagram

of SiC

As an important wide band gap semiconductor, SiC has many advantages and is
considered as a power semiconductor material in the twenty-first century. It is
suitable for manufacturing high-power, high-voltage, high-temperature power
devices, and high frequency optical/electronic devices.

Silicon Carbide Film

For electronic device fabrication, it is necessary to grow SiC films with different
doping concentrations and doping types on a specific substrate. Chemical vapor
deposition (CVD), molecular beam epitaxial (MBE), and magnetron sputtering have
commonly been used to grow SiC thin films. Among them, CVD is the most mature
epitaxial growth method. SiC films can be obtained by the heterogeneous epitaxy on
the SiC substrate or on other substrate materials. Compared with the sublimation
growth of SiC monocrystalline (mono-SiC), the chemical vapor deposition (CVD)
method for SiC thin films has lower growth temperature, more perfect crystal
structure with more controllable doping, and growth rate.
The reactive chamber for SiC thin film growth with CVD method is shown in
Fig. 77.10. The reaction tube is quartz with water as coolant and is referred to as cold
wall CVD. The graphite base forms the core part of the reactive tube, and its surface
is coated with special materials to ensure the thermal uniformity during the heating
process. In order to obtain an accurate ratio of C/Si ratio and minimize contamina-
tion, it is very important to select the right coating material. Silane and short-chain
hydrocarbon chemicals are the most commonly used source gases with H2 as the
carrier gas, and these gases pass quickly above the substrate. During the growth, the
short-chain hydrocarbon gas is firstly delivered into the reactor and then the substrate
is heated and kept at a certain temperature slightly higher than the growth temper-
ature for a period of time. A thin SiC buffer layer will form on the substrate. Then
silane is introduced, and the temperature of the reaction tube is maintained at about
77 Compound Semiconductors 1713

Fig. 77.10 CVD method for SiC thin film growth

1300
C, silane and short-chain hydrocarbon molecules would be decomposed at

high temperature, and the generated Si and C atoms are adsorbed on the substrate
surface to form the SiC epitaxial layer eventually.
CVD method has a lower growth rate of epitaxial films, usually several microns
per hour (um/h). In order to increase the growth rate, high-temperature hot wall CVD
method has received great attention in recent years. The higher the temperature, the
more prone the epitaxial nucleation growth process, which can increase the growth
rate. To prepare the n-type SiC epitaxial layers, nitrogen or TMA (trimethylamine)
should be added as the source gas during the reaction, while TMAl (tri-
methylaluminum) is generally used as a p-type doping source. Due to the excellent
properties of SiC, SiC films are widely used in the preparation of high-power devices
including diodes, JFET, and MOSFET.

Compound Quantum Well Materials

Quantum well (QW) would be formed when the thin compound semiconductor
layer, with a film thickness close to the electron de Broglie wavelength, is
sandwiched between two wider band gap semiconductor material. Fig. 77.11
describes the energy band diagram of the QW in the direction of crystal growth.
II–VI or III–V group heterostructures could be grown by MBE or MOCVD to
form a quantum well, in which the electrons would be confined in the thin narrower
band gap semiconductor layer with the thickness close to the de Broglie wavelength
of electron. The compound QW based on heterostructure can be divided into two
categories: One is the lattice-matched heterostructure, and the other is with large
lattice mismatch and a strained layer existing at the interface. The latter is widely
used in QW lasers, avalanche photodiode, modulators, switching devices, etc.
Compound semiconductor (CS) QWs based on AlGaAs/GaAs, GaAs/InGaAs,
GaN/InGaN, and CdTe/CdHgTe present superior electronic and photoelectric
1714 D. Yang et al.

Fig. 77.11 The energy band

diagram of the quantum well
along the growth direction

characteristics. With n-type heavy doping in AlGaAs and lightly doping or undoping
in GaAs, under thermal equilibrium, the electrons could move from the AlGaAs and
accumulate in the triangular quantum well on the GaAs side with the confinement in
the vertical direction to form a 2-D electron gas (2DEG). The mobility of 2DEG in
parallel to the interface is very high due to reduced impurity scattering. AlGaAs/
GaAs heterostructures are therefore widely used in high frequency devices. The
energy band structure could also be modulated by adjusting the Al content of the
AlGaAs layer, and the designed GaAs/AlGaAs multi-QW could be used to fabricate
light refraction devices with fast response and long-lifetime.
For InGaAs on the GaAs, the maximum lattice mismatch can be as high as 7% to
form strained QW. In strained QW, the energy difference between the two highest
heavy holes can be controlled by adjusting the well width, and the energy difference
between the highest heavy hole and the highest light hole can be controlled by
adjusting the axial strain. The device performance and advanced device design can
be achieved by tuning the energy band with the thickness dependent strain status. At
present, strained GaAs/InGaAs structure has been widely used in high frequency and
high-speed devices as well as strained QW lasers and so on.
With MOCVD, the QWs of InGaN/GaN could be grown on the GaN buffer layer
upon sapphire or Si substrate to fabricate blue and green LEDs as well as laser diodes
(LDs) with a high luminous efficiency. At the same time, due to the strong sponta-
neous and piezoelectric polarization effect, high-density and high mobility 2DEG
could exist in AlGaN/GaN and InAlN/GaN heterostructures even without intention-
ally doping, which is supposed to be the candidate material for next generation
RF/microwave and power electronic devices.

Compound Quantum Dot Materials

Quantum dots (QDs) are quasi-zero dimensional materials with three dimensions in
the nanometer scale, and the size of their 3D is nanoscale grade, close to the Fermi
wavelength of electrons. QDs consist of a finite number of atoms or molecules, and
77 Compound Semiconductors 1715

their energy is quantized due to the spatial confinement. It can be composed of a

single type semiconductor material, such as the II–VI group (CdS, CdSe, CdTe,
ZnTe, etc.) or III–V group compound semiconductors (InP, InAs, etc.). It can also
consist of two or more types of semiconductor materials. QDs exhibit very different
physical properties comparing to bulk materials, atoms, and molecules. The photo-
electric properties of QDs vary according to their size and shape. The smaller the size
of QDs, the shorter the wavelength of their emissions. By controlling the size of the
QDs, the spectra of wavelengths covering almost the entire visible light band can be
obtained. Based on the tunable properties of QDs, QDs are widely used in transis-
tors, solar cells, luminescent devices, as well as in quantum computing (QC) and
medical imaging.
II–VI group compound semiconductor QDs have the advantages of high exciton
binding energy and small exciton radius, which can be used for solid-state lighting
and lasers due to their unique surface effect and dielectric limit effect.
The QD materials from III–V group also include binary and multiple compounds,
and the crystal structures can be divided into zinc blende and Wurtzite structures. At
present, QD materials based on InGaAs, InGaN/AlGaN, GaN/AlN, and InGaN/GaN
are widely used with various shapes, e.g., conical, spherical, etc. The preparation
method has a great influence on the characteristics of QDs, e.g., the size, density, and
monocrystalline structure of QDs vary according to the growth method, substrate,
and growth parameters. The optical properties of III–V QDs are superior, e.g., high
luminous efficiency achieved due to the reduced probability of non-radiation com-
bination with the excitons confined in a small space, smaller luminous wavelength
than bulk materials and QWs due to the increase of energy level. In addition, the
coupling between longitudinal optical phonon and excitons also decreases with the
quantum dot size, as a result, the temperature dependence of photoluminescence
energy becomes smaller, and the temperature-induced redshift decreases accord-
ingly. There are strong spontaneous and piezoelectric polarization effects in
GaN-based QD materials; therefore, the redshift of the spectrum is very large.
In addition, quantum devices and computational models based on semiconductor
extensible gate QDs have received great attention in recent years. Quantum bit
encoding through precise control of charge and spin freedom in QDs is considered
to be one of the most possible candidate for the future solid-state quantum comput-
ing [9, 10].

References
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Photomask and Photoresist
78
Deren Yang, Ying Shi, and Xuegong Yu

Contents
Requirements of Photomask Materials and Development for ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
Photomask Substrate Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
Photoresist Applied Chrome Thin-Film Photo-Plate [3, 4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
Phase-Shift Mask (PSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
Extreme Ultraviolet Lithography Photomask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
Hard Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
Photoresist [9, 10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
UV Photoresist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
UV Broadband PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
G-Line (436 Nm) PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
I-Line (365 Nm) PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
Deep UV Photoresist (DUV Photoresist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
EUV Photoresist [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
Next-Generation Lithography Materials [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
Nanoimprint PR [13, 14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
Directed Self-Assembly of Block Copolymer (DSA BCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
Electron-Beam (e-Beam) PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
Photo-Sensitive Polyimides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
Antireflection Coating [15, 16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1741
Ancillaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1741
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742

Abstract
The photolithography is the most critical step for the IC fabrication, among which
the photomask and photoresist are the necessary materials. The photomask is
commonly used as the printing master plate on the photolithography process. The

D. Yang (*) · X. Yu
State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China
e-mail: mseyang@zju.edu.cn
Y. Shi
Integrated Circuit Materials Innovative Alliance, Peking, China

© Publishing House of Electronics Industry 2024 1717

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_78
1718 D. Yang et al.

mask pattern can be transferred on the substrates with the help of the photoresist.
The basic knowledge on the photomask, photoresist, phase-shift mask, DUV
lithography photomask, and DUV photoresist has firstly been introduced in this
chapter. With the development of lithography technology, extreme ultraviolet
(EUV) and mask technology have attracted most attention, concerning the EUV
lithography photomask and photoresist. Then, next-generation lithography mate-
rials have also been prospected. Moreover, photosensitive polyimides, anti-
reflection coating, and ancillaries have also been illustrated.

Keywords
Photolithography · Photomask · Photoresist · Phase-shift · Extreme ultraviolet
mask technology · Photosensitive polyimides, antireflection coating · Ancillaries

Requirements of Photomask Materials and Development for ICs

Photomask, also called mask, is a typically transparent fused silica plate covered
with patterns defined with an absorbing film, commonly used as printing master
plate on photolithography processes in IC fabrication. In mass production, the
more correct term is usually photo-reticle or simply reticle. A set of photomasks,
each defining a pattern layer, is individually selected for exposure. In double
patterning (DP) techniques, a mask would correspond to a subset of the layer
patterns.
The photomask manufacturing process is to convert the original layout data,
designed by integrated circuit design engineers for wafer manufacturing, into rec-
ognizable data formats for laser pattern generators or electron-beam exposure
equipment, so that the original layout can be exposed by the above-mentioned
equipment on the photosensitive material-coated photomask substrate. After a series
of processing processes, such as developing and etching, the graphics are fixed on
the substrate material. It is then followed with inspection, repair, cleaning, and
coating; the mask product is formed and delivered to the IC Fab for wafer
manufacturing.
There is always a long story behind each technology node. The earliest IC of
China was made by traditional photography for pattern transfer, that is, spraying
black paint on the Cu plate paper, manual engraving, then photographing with the
camera. At that time, PR was coated on glass substrates and should be used
immediately before drying, so this is called wet plate process. Later, ultrafine Ag
emulsion plate was developed, which is made by uniformly coating Ag halide
emulsion (photo-sensitive body) dispersed in gelatin as carrier on a clean and flat
photomask glass substrate. It replaced old wet plate process. Meanwhile, lithography
process has gradually developed from the initial manual alignment and vacuum
pressure imaging to contact lithography technology, which would reach 1 um
resolution by using ultrafine latex dry plate process. Dry plate mask has been used
78 Photomask and Photoresist 1719

for a long time for discrete devices and MSI (medium- and small-scale integration)
ICs because of its high sensitivity (to visible light, I line, and G-line), high resolu-
tion, and high contrast.
Contact photolithography mask includes vacuum contact, soft contact, hard
contact, and so on. The mask is directly in contact with the PR layer to achieve
the graphics transfer. Direct contact ensures the reproduction quality of imaging
process; avoids introducing any possible errors of pattern zoom; and has advantages
in specific application areas. Even at 20–22 nm high-tech nodes, NIL (nanoimprint
lithography) [1, 2] has once become a research hotspot, which can be regarded as an
advanced contact mask technology. But in general, due to high contamination during
direct contact of PR to the mask surface, accumulated wear defects would inevitably
affect the lifetime of the mask. Therefore, contact masks are gradually replaced by
projection lithography masks with high durability, high resolution, and easy cleaning
in IC industry.
The application of projection lithography mask is also transplanted from the
printing plate-making technology in printing industry, that is, through the projection
exposure with a prism system in a lithographic lithography machine, the cold light
pattern is transferred to the wafer, thus avoiding the pollution caused by the direct
contact between PR and mask. Early projection lithography masks also used the
same 1:1 pattern transfer ratio as contact lithography masks. With the widespread
application of microlithography technology, they have been developed into reticle
masks, which can be subdivided into 5:1 projection and 4:1 projection in proportion.
In addition, projection lithography masks sizes also can be distinguished as
2.5 inches (or 2.500 ), 400 , 500 , 600 , 700 , 900 , etc. (100 ¼ 25.4 mm). Mask shapes can be
divided into two types: circular and square, of which square shapes are the most
common. At present, the 4:1 projection 600 square mask is the mainstream for IC
lithography.
Projection photolithography masks can also be classified by the material category,
including binary, phase shift mask, and opaque Mo-Si binary on quartz glass, etc.
Moreover, since image distortion induced by projection lithography exposure, i.e.,
optical proximity effect error at different densities, it is increasingly necessary to
simulate the optical proximity effect correction (OPC) in advance and compensate
such image distortion with data model. The associated mask has been defined as
optical proximity effect correction (OPC) mask. In recent years, with the maturing of
extreme ultraviolet (EUV) lithography, the related EUV mask technology has
attracted most attention by IC technology researchers.

Photomask Substrate Material

Photomask substrate material is a basic material of photomask products, mainly

refers to glass substrate coated with opaque material and photo-sensitive material.
Substrate material must have good optical transmittance characteristics, thermal
1720 D. Yang et al.

and chemical stability, smooth surface, no sand inclusions, translucent points,

bubbles, or any other minor defects. Photomask substrate materials include white
crown soda-lime glass, low-expansion borosilicate glass, and quartz glass.
(1) White crown soda-lime glass is a kind of substrate material with good
mechanical and optical properties, easy processing, and low cost. Although its
thermal expansion coefficient (TEC) is relatively higher, the price is only about
one-third of that of low thermal expansion glass. Therefore, it has been widely used
as photomask substrates, which account for more than two-third of total photo-
mask substrate application. The photomask made of white crown glass is mainly
used for micro-fabrication of discrete devices and MSI ICs. (2) Low-expansion
borosilicate glass has better temperature and optical properties than white crown
soda-lime glass. Its TEC is less than half of white crown glass and its transmittance
is very high. Even though its price is slightly higher than that of white crown glass,
it is only one-third of that of quartz glass, so it has attracted much market attention
and occupies a large application field. This material can ensure the dimensional
accuracy of photomask and is suitable to make master masks or relatively high-
precision masks. The consumption of low expansion borosilicate glass substrate
accounts for about one-fourth of the total amount of photomask substrates. (3) Syn-
thetic high purity quartz glass is a kind of high purity silica in glass state. It has
excellent optical properties, i.e., very high transmittance above 90% especially in
short wavelength exposure and its TEC only 1/20 of white crown glass. It is
superior to the former two materials in thermal and chemical stability, absolutely
excellent as the photomask substrate material. It is widely used in the photomask
fabrication of ultra-fine and large-scale ICs. The composition, transmittance, and
characteristics of Photomask Glass Substrate Material are shown in Tables 78.1,
78.2, and 78.3.

Table 78.1 Composition Alkali-lime glass

of photomask glass
Components SLW SL NA LE QZ
substrate material
SiO2 73% 70% 55% 60% 100%
B2O3 – – – 5% –
Al2O3 1% – 14% 15% –
Na2O 15% 8% – 1% –
K2O 1% 9% – 1% –
RO 10% 13% 31% 18% –

Table 78.2 Transmittance Wavelength SL LE QZ

characteristics of
400 nm 92% 92% 92%
photomask glass substrate
material 350 nm 85% 90% 92%
300 nm 2% 17% 92%
250 nm 91%
200 nm 90%
 78

Table 78.3 Characteristics of photomask glass substrate material

Item Characteristic Condition Unit SLW SL NA LE QZ
Temperature Coefficient of thermal 50–200  C 94  107 98  107 43  107 37  107 5  107
characteristics expansion

Humidity Annealing point – C 542 533- 730 686 1120
Photomask and Photoresist

characteristics
Optical Refractive index 1.52 1.52- 1.57 1.53 1.46
characteristics
Chemical stability Weightlessness Di-water 100 C1h % 0.050 0.058 0.014 0.015 0.000
Weightlessness 1/100 N NHO3 % 0.028 0.023 0.040 0.030 0.000
100 C1h
Weightlessness 5% NaOH, 80 C1h Mg/mm2 0.13 0.14 0.10 0.31 0.17
Mechanical Density g/cm3 2.50 2.56 2.87 2.58 2.20
properties Elastic modulus kgf/mm2 7000 7341 9420 7540 7413
Shear modulus kgf/mm2 2870 2980 3730 3250 3170
Poisson ratio 0.22 0.23 0.25 0.16 0.58
Knoop hardness kgf/mm2 540 530 650 657 615
Grind hardness 88 88 160 209 210
Electrical Surface resistance Ω 6  104 1  1010 1  1011 1  1012 1  1019
characteristics Bulk resistivity Ωcm 1  1012 1  1016 1  1014 1  1016 1  1018
1721
1722 D. Yang et al.

Photoresist Applied Chrome Thin-Film Photo-Plate [3, 4]

The uniform chromium (Cr) plate photomask is a uniform Cr plate formed by

evaporating or sputtering a 0.1 μm thick Cr monoxide (CrO) film on the flat
photomask substrate and then coated with a layer of photoresist (PR) or electron-
beam (e-beam) resist (EBR). It has the characteristics of high sensitivity, high
resolution, and low defect density and is an ideal photo-sensitive blank plate to
fabricate micro-photomask patterns. The photosensitivity and resolution of the Cr
plates are entirely determined by the type and variety of PR or e-beam resist coated,
and the required photomask can be obtained by lithography process. In the era of
contact lithography technology, the use of ultrafine latex dry plate process has the
advantages of easy production and low cost, but also has the shortcomings of soft
film surface, easy to scratch, contamination, cleaning treatment difficulties, short
service lifetime and other weaknesses. Relatively, the manufacturing process of
uniform Cr plate is more complex, difficult, and costly, but it has the advantages
of high resolution, low defect, wear resistance, easy cleaning, and longer service
lifetime. It is suitable for making high-precision and ultra-fine graphics. Now it has
replaced the contact latex mask and become the mainstream key material of IC
photomasks. After etching the Cr layer, a homogeneous Cr mask can generate a
simple binary image composed of black-and-white areas. Therefore, this mask type
is also called a binary mask (or Binary Intensity Mask, BIM). As the traditional
penetrating mask, its exposure principle is shown in Fig. 78.1. The black area is
completely opaque, and the white area is transparent. For example, in the exposure
of chemically amplified photoresist, the laser beam passes through the mask to the
corresponding position of the Si wafer, causing PR reaction to produce photo acid,
which is removed or retained by subsequent development process (depending on
whether the PR is positive or negative) to form an image. The optical range of the
uniform Cr mask is very wide, covering G-lines, I-lines, and DUV (Deep Ultraviolet,

Fig. 78.1 Working principle of UV exposure using the uniform Cr photomask

78 Photomask and Photoresist 1723

including KrF wavelength 248 nm and ArF wavelength 193 nm). The wavelength of
laser light source determines the minimum resolution of the technical nodes.

Phase-Shift Mask (PSM)

When the feature size and spacing of the IC pattern reach the wavelength limit of
the exposure light source, the adjacent light intensity of the adjacent patterns on the
traditional uniform chrome-plated plate will be superimposed with each other by the
optical diffraction, resulting in insufficient projection contrast and poor imaging. In
order to increase the limit of exposure resolution, the phase-shift masks (PSM) are
used to improve the contrast of light intensity by using complementary optical phase
difference or phase shift. In addition, the traditional opaque Cr metal layer can be
replaced with a material that is not completely opaque (such as Mo-Si), which has a
certain transmittance and a phase shift difference of 180 . This type mask is called a
half-tone mask (HTM).
The application of phase shift mask (PSM) started with deep ultraviolet (DUV)
lithography technology [5, 6]. Due to different exposure wavelengths of lithography
(KrF at 248 nm and ArF at 193 nm), KrF or ArF phase shift mask with 180 phase
compensation transmittance is used at 248 nm or 193 nm wavelengths, respectively.
ArF PSM mask mentioned here can also be used for immersion ArF lithography that
can extend integrated circuit technology nodes below 10 nm.
According to different forms of optical compensation, PSM can be divided into
Alternate Phase Shift Mask (Alt-PSM) and Attenuated Phase Shift Mask (Att-PSM).
These two different exposure principles are shown in Fig. 78.2. (1) The Alt-PSM is
equivalent to alternatively adding a phase shift dielectric layer (as phase shifter)
between adjacent transparent regions to offset the diffraction between neighboring
light beams, thus enhancing the exposure resolution. In addition, this phase shifter
layer can also be achieved by alternatively etching different depths between adjacent
transparent regions of quartz substrates. (2) Att-PSM directly replaces the conven-
tional opaque Cr layer by a translucent molybdenum-silicon (Mo-Si) layer with
phase opposite to the transparent region, partially compensating the interaction

Fig. 78.2 Working principles of alternate phase-shift mask and attenuated phase-shift mask
1724 D. Yang et al.

between adjacent light beams to improve the exposure resolution. The corresponding
fabrication process is simpler than that of Alt-PSM. Table 78.4 shows the charac-
teristics of Att-PSM masks of HOYA Company in Japan.
Opaque-Mo-Si-on-Glass (OMOG), which is developed on the basic structure of
Att-PSM blank material, is a kind of black-and-white mask similar to binary mask,
also known as Super Binary Intensity Mask (SBIM). The original phase shift layer of
Mo-Si compound is treated to be completely opaque and no longer has the function
of shift compensation, and the ultra-thin Cr layer in the middle of blank is mainly
used as the pattern transfer layer (hard mask). Unlike the conventional binary mask,
the black areas of OMOG are an opaque thin Mo-Si compound material rather than a
chrome layer, which can effectively reduce mask 3D errors. Moreover, the ultra-thin
Cr middle layer can support thinner photoresist to achieve higher exposure limitation

Table 78.4 Characteristic specifications of HOYA PSM optical blank

Characteristic Specifications AXQ 6025 2C AXQ 6025 0.5 T
Quartz Thickness/mm 6.35  0.10 6.35  0.10
Flatness/μm 2.0 0.5
Cr Type AR8 TF11
Thickness Average/nm 105  5 48  5
Uniformity/nm 5 5
Reflectivity Average (12.5  1.0)% (19.5  1.0)%
@365 nm @193.4 nm
Uniformity 1.0% 1.0%
Defectivity Pinhole-free Pinhole-free
(3.0 μm) (1.0 μm)
Mo-Si Type K63A A61A*
Phase shift Average (181  2 ) (181  2 )
@248.4 nm @193.4 nm
Uniformity 2.5 2.5
Transmittance Average (5.3  0.3)% (6.1  0.3)%
rate @248.4 nm @193.4 nm
Uniformity 0.2% 0.2%
Thickness Average/nm 93 69.5
Uniformity/nm 2.6 2.5
Reflectivity 18%@248.4 nm 20%@193.4 nm
Defectivity Pinhole-free Pinhole-free
(1.0 μm) (0.15 μm)
Photoresist Type FEP171 FEP171
Thickness Average/nm 400  10 200  10
Uniformity/nm 7 7
Defectivity 0.3 ~ 1.0 μm: 17 0.2 ~ 0.3 μm: 20
1.0 ~ 2.0 μm: 2 0.3 ~ 1.0 μm: 10
2.0 μm: 0 1.0 μm: 0
78 Photomask and Photoresist 1725

and minimize the micro-deformation errors introduced by etching process, as well as

obtain better critical dimensional uniformity and graphic fidelity. Therefore, under
allowed exposure limit of lithography, a smaller mask error effect factor (MEEF) can
be achieved for superior lithographic quality and product yields.

Extreme Ultraviolet Lithography Photomask

Extreme ultraviolet photolithography (EUV) technology [7, 8] (wavelength at

13–15 nm, generally 13.5 nm) has been developed for many years and finally
used at 7 nm node manufacturing since 2019. Considering its very short exposure
wavelength and strong material absorption in EUV exposure environment, tradi-
tional penetrating lithography mask is no longer applicable; instead, reflective
masks with multilayer stacked structure of reflective optical system (e.g., interme-
diate layers, top cover layer (Ru), and absorption layer TaN, etc.) are used.
Intermediate layer of EUV mask is a multilayer structure composed of Mo and
Si with high reflectivity to EUV radiation. As the EUV radiation at about 13 nm is
similar to X-ray characteristics, there is minimum distortion of pattern transfer
during reflective lithography, so that high-quality pattern resolution could be
achieved. A comparison between the penetrating and EUV reflective masks is
shown in Fig. 78.3.
EUV mask requires high thermal stability and anti-radiation technology due to
the large amount of energy accumulation in lithography process [8]. However, it is
still unavailable for EUV reflective masks to be protected by traditional pellicle
mounting, there are difficulties in mask storage, transportation, and exposure

Fig. 78.3 Comparison of conventional transmission photomask and EUV photomask

1726 D. Yang et al.

process. Currently, the application of EUV masks is combined with photomask

inspection, cleaning, and repair equipment to avoid defects on the chip caused by
contamination or other reasons during the exposure process. As a result, the main-
tenance cost of related process, masks, and equipment is very high. It demands the
R&D for more durable pellicle techniques.
EUV lithography technology was originally considered for 65 nm technology
node in 2005, but the development is slow especially the EUV light sources for
sufficient power and reliability due to various technical challenges. After years of
efforts, the EUV lithography technology is finally used in IC manufacturing at 7 nm
node in 2019 and is expected to be continuously progressing for the future 5 nm node
and beyond.

Hard Mask

Hard mask refers to all kinds of hard semiconductor processing materials used in
etching process to replace polymers or other organic “soft” anti-etching materials
(e.g., PR). This concept, in fact, belongs to different technological field in semi-
conductor industry compared with photomasks in microlithography technology.
Figure 78.4 shows an application of hard mask materials. As the feature size of
semiconductor chips is shrinking, the sharp increase in the height-to-width ratio (that
is, aspect ratio) of PR makes the etching more difficult, and the etching deviation,
uniformity, and sidewall angle are difficult to control. Thus, a relatively thinner hard
mask layer is introduced as an intermediate transition layer for pattern transfer, the
etching process is transformed into a double process step from PR layer to hard mask
and then to etching layer. This can eliminate difficulties in the etching process and
achieve nearly ideal etching results. Currently, it is a common and mature etching
technique in IC manufacturing. Generally, hard mask layer is formed by chemical
vapor deposition (CVD) or physical vapor deposition (PVD). There are many kinds
of hard mask materials, including amorphous carbon material, silicon dioxide,
silicon nitride, etc., which are characterized by thinner thickness and better etching
resistance.
The hard mask corresponds to the soft mask material, which is generally a thick
adhesive layer, and is commonly called photoresist directly. In addition, in some
cases, because the finished chrome photomask material is hard, it is sometimes called
a hard mask material.

Fig. 78.4 Application of thin hard mask

78 Photomask and Photoresist 1727

Fig. 78.5 Working principle of photoresist

Photoresist [9, 10]

Photoresist (PR) is a photo-sensitive material, in which the photoactive compound

will undergo chemical reactions under the irradiation of light, resulting in a change in
the dissolution rate of the material. Its main role is to transfer the pattern from the
reticle to the substrate. As shown in Fig. 78.5, the complete process can be com-
prised of the following steps: (1) Apply the PR to the substrate, the excess solvent is
removed through a soft bake step. (2) The substrate is exposed through a reticle, so
that chemical reactions occur in the photosensitive components of photoresist on the
exposed region. (3) Post-exposure baking is performed, and finally, the PR is
selectively removed by a developer (for a positive PR, the exposed region is
removed; for the negative PR, the unexposed region is removed). Thus, the pattern
transfer from the reticle (mask) to the substrate is realized.
The components of the photoresist (PR) mainly include the resin, the
photo-sensitive component, the trace additive, and the solvent. The resin provides
mechanical properties and etch resistance; the photo-sensitive component undergoes
chemical reactions under illumination, causing the dissolution rate to change; the
trace additive may includes dyes, cross-linkers, etc., to improve the performance of
the PR. The solvent is used to evenly dissolve these solid materials. Currently widely
used PR can be classified into conventional PR and chemically amplified PR
according to the photo-chemical reactions. Lithography can also be divided into
ultraviolet (UV), deep ultraviolet (DUV), extreme ultraviolet (EUV), electron beam,
ion beam, and X -ray according to the wavelength of light. PR is more accustomed to
use its wavelength or light source to name it as shown in Table 78.5.

UV Photoresist

UV photoresist (PR) refers to a PR sensitive to a wavelength between 280 nm and

450 nm. According to the wavelength of light, it can be classified into UV broad-
band, G-line (436 nm), and I-line (365 nm) PRs. The resolution of I-line PR can
reach 0.35 μm, which is the workhorse in microelectronics and ICs. Also, the most
versatile type of PR is.
1728 D. Yang et al.

Table 78.5 Photoresist types, application fields, and characteristics reference table [9, 10]
Photoresist type Application field Feature description
Ultraviolet Ultraviolet Semiconductor discrete The manufacture of devices such
broad- broadband device as diodes and triodes. The process
spectrum positive line width is large (>5 μm), which
photoresist photoresist requires excellent process window
of the photoresist. A phenolic
resin is used as a resin, and a
compound having an absorption
peak at long wavelength is used as
a photosensitive component.
Ultraviolet Ultraviolet Integrated circuit Bumping, rewiring RDL
broad- broadband package (redistribution layer), silicon TSV
spectrum positive photo (through silicon via), and other
photoresist resist processes. A thicker photoresist
film thickness (20–100 μm) is
required, and the photoresist is
required to have a fast photospeed
or good resistance to the plating
solution. Resolution requirements
are not high (>10 μm).
LED light-emitting Positive photoresists for LED chip
diode fabrication are similar to those
used in semiconductor discrete
devices.
LCD liquid crystal For LCD Array, touch panel
display manufacturing, according to
different applications, it is divided
into positive photoresist for TN/
STN-LCD and TFT-LCD. The
former has lower resolution
requirements (>15 μm), while
resolution for the later application
is high (>5 μm), and it requires
good coating performance and
faster photospeed (100 ms).
Ultraviolet Semiconductor discrete The cyclized rubber is used as a
broadband device resin, and the double azide
negative compound is a cross-linking
photoresist agent, which has low resolution
(>5 μm), but needs to have good
wet etch resistance.
Integrated circuit Used in bumping, rewiring
package (RDL), and other processes, is an
acrylate based negative
photoresist. It has good light
transmittance and can maintain
good profile and high photospeed
under a thick film thickness; the
resolution requirement is not high
(>5 μm).
(continued)
78 Photomask and Photoresist 1729

Table 78.5 (continued)

Photoresist type Application field Feature description
LED light-emitting Used in LED chip manufacturing,
diode mainly use phenolic resin as resin.
It is generally used in the lift-off
process to form electrode. This
type of photoresist has inverted
trapezoidal profile, high
sensitivity (<250 ms), and high
resolution (2–3 μm).
MEMS Such photoresists mainly use
microelectromechanical epoxy resin as a resin, the
system resolution requirement is not high
(>10 μm), the thickness
requirement is 20–100 μm, it has
large aspect ratio, good thermal
stability, and excellent mechanical
properties.
G-line G-line Semiconductor discrete The manufacture of devices such
(436 nm) positive device as diodes and triodes. A phenol
photoresist photoresist resin is used as a resin, and a
compound having an absorption
peak near the G-line is a
photosensitive component. The
resolution is higher than UV
broadband photoresist, which can
reach the micron level.
Integrated circuit Bumping, rewiring RDL
package G (redistribution layer), silicon TSV
(through silicon via) and other
processes. A thicker photoresist
film thickness (20–100 μm) is
required, and the photoresist is
required to have a fast photospeed
or good resistance to the plating
solution. Resolution requirements
are not high (>10 μm).
G-line G-line LED light-emitting LED chip manufacturing, use
(436 nm) positive diode phenolic resin as resin, film
photoresist photoresist thickness is within 2 ~ 3 microns,
and the resolution is around
5 micron.
LCD liquid crystal High-generation TFT-LCD
display manufacture, use phenolic resin as
resin, a compound has absorption
peak around 436 nm used as
photosensitive component,
resolution (<5 μm), require good
slit coating performance and fast
photospeed (100 ms).
(continued)
1730 D. Yang et al.

Table 78.5 (continued)

Photoresist type Application field Feature description
Integrated circuit For non-critical layers of low-end
(IC) G-line positive integrated circuit processes,
photoresist G-line positive photoresists
require higher resolution
(approximately 1.0 μm) and good
process window, especially
exposure latitude (EL) and depth
of focus (DOF), with both dry
etch resistance and implant
resistance.
G-line LED, integrated circuit G-line negative photoresist is
negative similar to ultraviolet broadband
photoresist negative photoresist, use phenolic
resin as resin. The main difference
is that the photo-acid generator
has stronger absorption at 436 nm.
I-line I-line positive Integrated circuit (IC) Like the G-line photoresist, based
(365 nm) photoresist on Novolac/DNQ system, which
photoresist is characterized by high
resolution. The main difference
from the G-line photoresist is that
the photosensitive component’s
absorption peak is around 365 nm,
and the phenolic resin structure is
also different; I-line photoresist
with 0.5 μm resolution for
non-critical layers; high-
resolution I-line photoresist with a
resolution of 0.35 μm for critical
layers; thick film photoresist
(thickness 3–5 μm) for
passivation layer.
TFT-LCD Similar to G-line photoresist, it is
based on Novlac/DNQ system,
which is used to fabricate LCD
arrays. The resolution
requirement is not critical, around
2 μm, but the uniformity of the
coating, trace metal, and particle
requirements are higher than
normal TN/STN-LCD
photoresist, photospeed
requirement is less than 70 mJ.
LED substrate The patterned sapphire substrate
(PSS) process has been widely
adopted in LED fabrication. This
advanced process requires an
I-line stepper, and thus, an I-line
photoresist is used. Requires
photoresist to have strong
(continued)
78 Photomask and Photoresist 1731

Table 78.5 (continued)

Photoresist type Application field Feature description
resistance to dry etching,
resolution 1 ~ 2 μm.
I-line negative Integrated circuit (IC), A negative photoresist platform
photoresist LED based on phenolic resin.
Compared with the broadband
negative photoresist, the
absorption peak of the photo-acid
generator is around 365 nm.
DUV DUV Integrated circuit KrF positive photoresist is
(248 nm) (248 nm) manufacturing sensitive to KrF (248 nm)
photoresist positive wavelength, use hydroxyl styrene
photoresist polymer as the resin, and a photo-
acid generator with absorption
peak around 248 nm used as
photosensitive component, and
the acid generated by PAG acting
as catalyst and thus has a chemical
amplification effect. This type of
photoresist is characterized with
fast photospeed (~30 mJ), high
resolution (down to 110 nm), can
be used in 0.13 μm–0.35 μm
technology node, combined with
resolution enhancement
technology, can be used in
0.11 μm or even 90 nm
technology node.
DUV DUV Integrated circuit KrF negative photoresist is similar
(248 nm) (248 nm) manufacturing as KrF positive photoresist, the
photoresist negative main difference is that the photo-
photoresist acid generated by the photo-acid
generator catalyzes the cross-
linking reaction in the exposed
area, thus form a negative pattern;
the resolution can also reach
0.13 μm; mainly used in some
special processes.
ArF ArF positive Advanced integrated ArF positive photoresist is
(193 nm) photoresist circuit manufacturing sensitive to ArF(193 nm
photoresist (dry) wavelength), use acrylic polymer
as the resin and a rigid molecular
group is introduced to increase the
etch resistance and a photo-acid
generator with absorption peak
around 193 nm used as
photosensitive component, and
the acid generated by PAG acting
as catalyst and thus has a chemical
amplification effect. This type of
photoresist is characterized with
(continued)
1732 D. Yang et al.

Table 78.5 (continued)

Photoresist type Application field Feature description
fast photospeed (~30 mJ), high
resolution, can be used for
65 nm–90 nm, combined with
resolution enhancement
technology, can be used in 45 nm
process; another requirement is
line width uniformity (LWR)
<4 nm.
ArF positive Advanced integrated ArF immersion photoresist is
photoresist circuit manufacturing similar as ArF positive
(immersion) photoresist, the resin and photo-
acid generator structure need to be
further optimized to achieve
higher resolution ~38 nm, and the
photo-acid generator absorption
peak is still near 193 nm, still
using chemical amplification
technology. Fast photospeed
(~30 mJ), combined with
resolution enhancement
technology, can be used in
32/28 nm technology node; if
multiple patterning technology is
used, 20 nm/14 nm process can be
realized; another requirement is
line width uniformity (LWR)
<2.5 nm.
EUV EUV Advanced integrated EUV is an exposure light source,
(13.5 nm) (13.5 nm) circuit manufacturing which uses chemical amplification
photoresist positive technology. Unlike traditional
photoresist 248 nm and 193 nm photoresists,
all components in the photoresist
are absorbed by EUV, and the acid
generation mechanism is more
complicated. The photoresist has
a lower outgassing during
exposure. As a candidate for next-
generation lithography, EUV
photoresists are expected to be
used in process nodes of 10 nm
and below.
Electron- Electron- Lithography mask An electron beam is used as an
beam beam fabrication exposure light source, and an
photoresist photoresist acrylic resin is a film-forming
resin. The resolution is up to
nanometer, and the photospeed
requirement is 30–60 μC/cm2.
78 Photomask and Photoresist 1733

UV Broadband PR

It refers to a class of photoresist with the full spectrum of a high-pressure mercury

lamp as the exposure wavelength; it has relatively lower resolution and mainly used
for discrete devices, ICs and LED chips, LCD, and touchscreen manufacturing. UV
broadband PR is divided into positive and negative PRs. (a) Broadband
UV-positive PR mainly uses Novolac/DNQ system. The photo-sensitive component
(as photosensitizer) can form hydrogen (H) bonds with the phenolic resin to reduce
its dissolution rate in the developer. Under the light exposure, photosensitizer can
form carboxylic acid with phenolic resin and promotes the dissolution rate of
phenolic resin, thus form dissolution rate contrast between exposed and unexposed
area. According to the different applications, the types of phenolic resins, photosen-
sitizer, and additives in UV broadband positive photoresist are also different. Such
PR can be used in many applications such as semiconductor discrete devices, IC
packages, LEDs, and LCDs. Discrete devices mainly refer to a diode, triode, power
bipolar, power MOSFETs, etc. Semiconductor packaging PR is mainly used in the
bumps process (i.e., bumping), redistribution layer (RDL), and through-Si-via
(TSV). In these processes, the resolution of PR is not critical (>10 μm), but thicker
(20–100 μm) PR and much faster photospeed are required. At the same time, the
photoresist is required to have a high sensitivity and is not corroded by the plating
solution. PR for light-emitting diode (LED) is similar to PR for discrete device
manufacturing, except that the LED manufacturing uses a dry etch process and
requires the PR with good etch resistance. PR for liquid crystal display (LCD) can be
divided into different applications for TN/STN-LCD and TFT-LCD. Due to the
different process requirements, the composition of the two photoresist is different.
The resolution of the PR for TN/STN-LCD manufacturing process is relatively low
(>15 μm) and uses sodium hydroxide/potassium hydroxide (NaOH/KOH) as a
developer. The TFT-LCD manufacturing process requires a high resolution
(>5 μm) for the PR with a good coating performance and a fast photospeed. (b)
Broadband negative PR has three main types: One is conventional negative PR, in
which cyclized rubber acts as the resin and azides as photosensitizer and cross-linker.
The second type PR is based on the chemically amplify mechanism (CAM)PR to use
phenolic resin as film-forming resin. It belongs to the negative photoresist from the
reaction mechanism, but the supporting reagent used is the same as the positive
photoresist. The third type is based on the free radical polymerization or ring-
opening cross-linking mechanism to use acrylate or epoxy resin as film-forming
resin. It is characterized with good transparency and fast photospeed. These negative
photoresists are mainly used for discrete devices, IC packaging, LEDs, and MEMS
in the fabrication process. Broadband negative PR for discrete devices is a conven-
tional negative PR. It uses cyclized rubber as resin and azide as cross-linker, in which
the resolution is not critical, but need good wet etch resistance. Broadband negative
PR for IC packaging is based on acrylate polymer. It has good transparency, allowing
it to form good profile and faster photospeed at thicker PR films. The UV broadband
negative PR used for LED chip fabrication is based on phenolic resin, which is
mainly used to form the electrode in lift-off process. This photoresist has inverted
1734 D. Yang et al.

trapezoidal profile and is characterized with fast photospeed and good resolution.
The UV broadband negative PR for the MEMS fabrication is based on epoxy resin.
This kind of photoresist has high cross-link density which can form a high aspect
ratio profile with excellent thermal and mechanical properties.

G-Line (436 Nm) PR

G-line (436 nm) PR refers to a PR using 436 nm wavelength light as the exposure
light source and can be classified into positive and negative PRs. G-line positive PR
is similar as UV broadband PR, i.e., it is based on Novolac/DNQ platform and
usually using stepper as the exposure tool. The main difference between G-line and
UV broadband PR is that the photosensitizer for G-line must have strong absorption
at 436 nm. Also, G-line PR has certain requirements for the content of metal ions
(fewer metal ions) as needed for IC manufacturing. G-line positive PR for discrete
devices is similar to UV broadband positive PR but better resolution and process
window due to changes in exposure mode. G-line positive PR for IC processes
requires higher resolution (about 1.0 μm) and greater process window especially in
exposure latitude (EL) and depth of focus (DOF). Due to the use of dry etching and
ion implantation in IC manufacturing, the photoresist is required to have better
etching resistance. G-line negative PR uses phenolic resin as film-forming resin
and is mainly used in the lift-off process of integrated circuit manufacturing and LED
chip manufacturing. The composition is similar to the UV broadband negative PR
with the main difference in the stronger absorption at 436 nm by photo-acid
generator.

I-Line (365 Nm) PR

I-line PR refers to PR using 365 nm wavelength light as the exposure light source. It
is the main type of PR in the IC manufacturing with resolution up to 0.35 μm. It is
widely used in 600 and below wafer fabrication lines. I-line also has a significant
portion of layers in 8” IC manufacturing. Like the G-line PR, the I-line positive PR is
a Novolac/DNQ system with higher resolution (than G-line). The main differences
of I–line PR from G-line PR are the chemical composition and structure of phenolic
resins, photosensitizers, and additives. In addition to p-cresol and m-cresol, a third
structural unit is introduced into the phenolic resin to improve the contrast between
the exposed and unexposed areas, as well as the molecular weight distribution of the
resin is narrower by the fractionation technique. The distribution of light intensity in
the photoresist is more uniform by using the photosensitizer skeleton with better light
transmission, and by using additives such as dissolution promoters or dissolution
inhibitors, the sensitivity of the photoresist can be controlled more precisely. The
I-line PR for ICs and advanced packaging processes can be divided into three
categories, i.e., standard I-line PR with a resolution of 0.5 μm for non-critical layers,
high resolution of 0.35 μm for critical layers, and thick film PR (film thickness 3–5 μm)
78 Photomask and Photoresist 1735

for passivation layer. I-line positive PR is also widely used in patterned sapphire
substrate (LED PSS) process for LED fabrications in which the PR is required to
have strong resistance to dry etching by improving the mechanical properties of the PR
resin. On the other hand, the PSS process requires higher resolution and better
sensitivity of the photoresist (R < 1.5 μm, Eop < 150 mJ). The negative PR of I-line
mainly includes the negative system of phenolic resins. It is mainly used in the lift-off
process of IC and LED chip manufacturing. Compared with UV broadband negative
photoresist, the photo acid-producing agent in I-line negative photoresist has stronger
absorption at 365 nm.

Deep UV Photoresist (DUV Photoresist)

DUV photoresist (PR) refers to PR using wavelength between 180 nm and 260 nm
light as exposure source. It can be subdivided to KrF (248 nm) and ArF (193 nm)
PRs depending on the wavelength of light sources. For ArF PR, it can be further
divided to ArF PR and ArF immersion PR based on the exposure tool types. The
resolution of KrF PR is around 130 nm and ArF PR is around 45 nm. If using multi
patterning technology (MPT), the resolution of ArF immersion PR can reach 7 nm
and ArF PR is a key material for advanced IC manufacturing at 14 nm node and
beyond. (1) KrF PR refers to the PR using KrF laser as the exposure light source. It
is the first PR using chemical amplification mechanism (CAM) [11, 12] with main
components of polymer, photo-acid generator, additive, and solvent. Upon expo-
sure, photo-acid generator generates photoacid, and then, the photoacid catalyzes
the de-blocking or cross-link reaction of the polymer during the post-exposure
bake (PEB); this reaction achieves a difference in dissolution rate between exposed
area and unexposed area, thus transfer the pattern to the substrate in the following
development process. This CAM gives KrF PR higher sensitivity (30–50 mJ) and
good resolution (0.13–0.35 μm) and if combined with resolution enhancement
techniques (RET), it can be used at 90 nm technology node. KrF PR use poly-
hydroxystyrene as polymer, sulfonium, or iodonium as photo-acid generator
(PAG). For positive photoresist, the photoacids generated in the exposed area
can catalyze the de-blocking reaction of polymers to form phenolic hydroxy or
carboxylic acids which makes the polymer easy to be dissolved in the developer.
For negative photoresist, these photoacids generated in the exposed area can
catalyze the cross-link reaction of polymers to form dense cross-link structures
that are hardly dissolved in the developer. (2) ArF PR is a photoresist with ArF
laser as exposure light source, which also uses chemical amplification technology.
That is, the photoacid generated by the photoacid generator under 193 nm light
catalyzes the de-blocking or cross-link reaction on the film-forming resin during
the post-exposure bake (PEB) process. This reaction results in a difference in
dissolution rate between the exposed and non-exposed areas and then transfers
patterns to the substrate in the following development process.
ArF PR can be further divided into ArF dry PR and ArF immersion PR based on
the exposure tool type. ArF dry PR can be used in 90 nm, 65 nm, and 45 nm
1736 D. Yang et al.

technology nodes. ArF dry PR use PMMA type polymer as resin, iodonium, or
sulfonium as photo acid generator (PAG). It works on the same principle as KrF
(248 nm) photoresist. For positive ArF dry PR in the PEB step, PAG generates
photoacid to catalyze the chain scission reaction of polymer, and then form carbox-
ylic acid to make the exposed area more soluble in the base developer, while for
negative ArF dry PR in the PEB step, the photoacid can catalyze the cross-link
reaction to form dense cross-link network leading to the exposed area hard to be
dissolved in developer.
ArF immersion PR is similar as ArF dry PR, but the difference is that in
immersion lithography, water is filled between lens and PR, so it is necessary to
ensure that the components in the photoresist are not dissolved by water, and the
contact angle between the photoresist and water should be as large as possible to
improve the throughput of the lithography process. To meet the above performance
requirements, it can be achieved by adding a top coating in the process and using
macromolecular photo acid generators and additives in the photoresist. 193 nm
immersion lithography is widely used in IC manufacturing at 32 nm, 28 nm,
14 nm, as well as 10 nm nodes and beyond.

EUV Photoresist [10]

EUV photoresist (PR) refers to PR using EUV (13.5 nm) as exposure light source.
Currently, the main focus is to further improve the PR sensitivity, reduce line edge
roughness, and outgassing of the PR system. Based on ITRS, for high volume
manufacture, EUV PR need to meet: (1) high resolution, (2) fast photospeed,
(3) low line edge roughness and less outgassing, and no contamination to exposure
system. As a next-generation lithography, EUV is already used in manufacturing for
7 nm node and beyond.
EUV PR can be classified to chemical amplification (CA) [11, 12] system,
molecular glass, and metal oxide types: (1) Conventional CA type PR is charac-
terized with high photosensitivity as an advantage for EUV lithography (with
limited source power). However, it has line edge roughness issues caused by the
acid diffusion and the resolution not meeting requirements; and it is subject to
further optimization. (2) Molecular glass was developed to solve the issues of
chemical amplification PR, in which the main component is small molecules with
protective groups. It can form homogeneous and non-crystalized photoresist films
by the spin-coating method and perform good thermal stability (>150  C), but
molecular glass PR suffers from pattern collapse especially for small features.
Therefore, it needs further optimization. (3) Metal oxide type PR has higher
density and better absorption cross section for EUV light, it also performs less
outgassing, no contamination to exposure system, and high etch resistance during
the pattern transfer step. However, the photosensitivity of this type of PR is very
slow and need further optimization. Fig. 78.6 illustrates a common EUV MG/PAG
bonded structure.
78 Photomask and Photoresist 1737

Fig. 78.6 A common EUV MG/PAG bonded structure

Fig. 78.7 Heat curing nanoimprint schematic

Next-Generation Lithography Materials [10]

The following is photoresist (PR) materials for next-generation lithography, includ-

ing nanoimprint materials, block copolymers for directed self-assembly process, and
electron-beam PRs.

Nanoimprint PR [13, 14]

Nanoimprint PR includes two types of PRs, i.e., thermal curing and UV curing types
shown as in Figs. 78.7 and 78.8 respectively. The thermal curing type uses a stamp to
transfer the pattern and followed by thermal curing the PR, then use dry etch to
transfer the pattern to substrate. Another type is UV curing type which uses a UV
light to cure the PR and then uses the dry etch to transfer the pattern to the substrate.
The main components of nanoimprint PR include acrylate polymer, photo-initiator,
cross-linker, additives, and solvent.
1738 D. Yang et al.

Fig. 78.8 UV-curable curing nanoimprint schematic

Fig. 78.9 Graphics-based self-assembly

Fig. 78.10 Self-assembly based on chemical substrate

Directed Self-Assembly of Block Copolymer (DSA BCP)

Directed self-assembly use the polarity differences between the two segments of
block copolymer to form ordered structures. Based on the phase separation condi-
tion, it can be classified to grapho-epitaxy and chemo-epitaxy as illustrated in
Figs. 78.9 and 78.10, respectively. The basic principle of self-assembly is to induce
fragments with different properties to arrange themselves by physical and chemical
78 Photomask and Photoresist 1739

methods, and achieve the purpose of photolithography according to different etching

rates of different fragments. The main focus is to design the block copolymer with
necessary polarity and etch rate differences. DSA is reported to be used in quantum
devices, magnetic storage, nanowire, and photonics applications.

Electron-Beam (e-Beam) PR

Electron-beam photoresist (e-beam PR) refers to PR using electron beam as expo-

sure source. Due to its short wavelength, high energy, and small beam size, electron-
beam lithography can perform excellent resolution and has been widely used in mask
manufacture. PMMA type resin is the main component of e-beam PR. It undergoes
the chain scission when bombarded by electrons, which makes the exposure area
easy to be dissolved by the developer. The main challenge of e-beam lithography is
low throughput caused by its direct write nature, not suitable for the mass production
of ICs. There are studies of multiple e-beam (multibeam) lithography which may
improve the throughput of e-beam lithography.

Photo-Sensitive Polyimides

Photosensitive polyimide (PSPI) resin is a polymer chain with imide ring and
photosensitive group, which has excellent thermal stability and good mechanical,
electrical, chemical, and photosensitive properties of organic materials. PSPI resin
can be cross-linked or decomposed under ultraviolet, X-ray, electron-beam, or
ion-beam irradiation, and can form thin-film patterns on the surface of the substrate
through the mask plate. At the same time, because the process of using PSPI resin to
form film patterns on the substrate is relatively simple, the production cost is low.
Therefore, the PSPI resin has been widely used in the manufacture and packaging of
VLSI, micromachinery, and other fields. For example, the photo-patterned and
thermally cured PSPI film can act as a thermal stable and electric insulating dielectric
layer in the multilayer structure or a passivation coating layer for ICs. PSPI should
possess not only the great film properties (e.g., mechanical strength and toughness,
electric insulating and dielectric properties, dimensional, and adhesive properties),
but also photolithographic performance (e.g., photosensitivity, resolution, develop-
ing and rinsing, imidization temperatures, etc.).
According to the convex and concave shapes of the photolithographic images
obtained after exposure, PSPI can be divided into negative-tone (n-type PSPI) and
positive-tone (p-type PSPI) similar to standard PRs. The general photo-patterning
process involves four steps: (1) Spin-coating PSPI resin onto the substrate surface
such as Si wafer; (2) Prebaking and exposing to UV light (I-line and/or G-line)
through a mask, transferring the pattern information to the PSPI layer; (3) Develop-
ing; either the exposed or unexposed area is selectively removed by dissolution to
form a patterned layer; (4) Thermal curing; the developed pattern on exposed PSPI
was converted into the polyimide one.
1740 D. Yang et al.

After the UV exposure, the cross-linking reaction occurred on the exposed zone of
n-type PSPI resin, and the solubility of the exposure zone in the developer decreased
significantly. Therefore, after the exposed PSPI was developed and cured, the
convex lithographic pattern could be obtained. On the contrary, for p-type PSPI
resin, the solubility of the exposure zone in the developer is significantly enhanced
due to the chain scission reaction. Thus, after the development and curing steps,
concave lithographic pattern can be obtained.
According to the different preparation methods, negative PSPI resin can be
divided into ester n-type PSPI, ionic n-type PSPI, and self-sensitizing n-type PSPI.
Most of n-type PSPI are based on polyimide precursor poly(amic ester) (PAE) in
which photo-reactive methacrylate groups are linked to the carboxylic acids through
the ester linkage via the covalent bond (ester n-type PSPI) or acid-amine ion linkage
via the ionic bond (ionic n-type PSPI). The photo-chemistry mechanism of pattern
formations is different. In the case of ester n-type PSPI, methacrylate groups can
react in a radical polymerization by UV irradiation. Conversely, a “charge separa-
tion” mechanism is considered in the ionic n-type PSPI, in which charge-transfer
complexes are formed between the poly-amic acid and the photo-radical initiator in
the exposed area upon UV exposure. The photo-radical initiator is usually photo-acid
generator (PAG) or photo-base generator (PBG), which can photo-chemically gen-
erate a strong acid or a base upon UV irradiation. Then at relatively low tempera-
tures, heat treatment can perform the conversion from the precursor to a robust
structure. In addition, the self-sensitized PSPI resin is cross-linked by the substituted
alkyl group on the amido group in the main chain of the polyimide resin and the
carbonyl group of the benzophenone structural unit, thus reducing the solubility of
the resin in the solution developer, so as to obtain the convex lithographic pattern.
According to the different kinds of photosensitizers, positive PSPI resins can be
divided into o-nitrobenzyl ester PSPI, cyclobutylamine resin PSPI, and
diazonaphthoquinone sulfonate PSPI. (1) o-nitrobenzyl ester PSPI resin: The work-
ing principle is that the o-nitrobenzyl ester photosensitive groups are decomposed into
carboxylic acids and aldehydes under the ultraviolet light, and the polyamide ester
resin connected with o-nitrobenzyl ester photosensitive groups on the main chain can
transform the ester group into carboxylic group after the UV exposure, which signif-
icantly improves its solubility in alkaline aqueous developer. After the alkaline
solution development and curing, the exposed region is completely dissolved while
the unexposed region is preserved, thus forming a positive convex lithographic
pattern. (2) Cyclobutylimide resin PSPI: The working principle is that polyimide
resin containing cyclobutyl group is decomposed by the light irradiation, so that the
solubility of the exposure zone in the organic developer is enhanced, therefore, a
positive convex lithographic pattern is obtained. (3) Diazonaphthoquinone sulfonate
PSPI resin: It is composed of polyamide ester resin and photosensitizer which can
form organic carboxylic acid compound under the light irradiation. That is, with the
UV light irradiation, the diazonaphthoquinone sulfonate group (DNQ) decomposes to
form organic indenic acid, which obviously enhances the solubility of the resin in the
exposure area with the alkaline aqueous developer, so as to obtain a positive convex
lithographic pattern. PSPI have been extensively employed in the micro-electronic
78 Photomask and Photoresist 1741

manufacturing and packaging (e.g., passivation and buffer coating layer on ICs,
interlayer dielectric layers in multilayer structures, BGA/CSP/WLP, etc.), as well as
buffer-stress coatings in IC packaging by EMC.

Antireflection Coating [15, 16]

Antireflection coating refers to a thin coating under or over PR layer; it was used to
reduce the reflected light at interfaces of PR/air and PR/substrate for suppressing the
influence of standing wave effect on the photoresist (1) The top antireflection
coating (TARC) is coated at the top of the PR. The main function of the TARC
layer is to eliminate the light reflected from the top surface of the photoresist, prevent
the impurities in the air from diffusing into the photoresist, reduce the influence of
the film thickness on the performance of the photoresist, and improve the uniformity
of the line width of the photoresist. Its performance requirements include matching
the refractive index of the photoresist and being easily soluble in the developer.
(2) The bottom antireflection coating (BARC) [17] is coated under the PR for
reducing light reflection at the substrate/PR interface. Barc layer can prevent the
diffusion of impurities on the substrate to the photoresist, and its performance
requirements include high absorption coefficient, insolubility in the photoresist
solvent, and lower etching rate than the photoresist.
Antireflection coating is generally used with 248 nm DUV photoresist or 193 nm
DUV photoresist, usually composed of polymer resin, dye, thermal acid generator,
solvent, and so on. However, the composition of the antireflection coating used for
248 nm and 193 nm photoresist is different, and the absorption peak of the dye used
is also different.

Ancillaries

Ancillaries refer to chemicals used with PR in the lithography process of integrated

circuits. It mainly includes adhesion promoter, thinner, edge bead remover (EBR),
developer, and stripper. (1) Adhesion promoter: HMDS (Hexamethyl disilylamine)
is a main chemical applied to substrate before photoresist coating. It will turn the
substrate surface from hydrophilic to hydrophobic by reacting with the surface
hydroxyl on substrate, thus improving the adhesion property of photoresist to the
substrate, as well as reduce adhesion-related defects and improve the wet etch
resistance. (2) Thinner: Thinner is a chemical used to dilute PR, mainly for
adjusting PR viscosity to obtain different film thickness. The main component is
PR solvent, like PGMEA, PGME, EL, MAK, etc. (3) Edge bead remover (EBR): It
refers to chemicals used to clean the edge and backside of wafers. During spin
coating, PR will become thicker at wafer edge and even splash to the backside of the
wafer. If not cleaned properly, these PR will move with wafers in the following steps
and increase particles and contamination to both wafers and tools. Main components
of EBR are solvents such as PGMEA, PGME, EL, etc. It needs to match the solvents
1742 D. Yang et al.

used in photoresist. The edge bead remover can dissolve the photoresist quickly and
has the characteristics of high purity and low particle content. (4) Developer:
Developer refers to chemical used to remove the unwanted PR on the wafer. For
positive PR, the developer is aqueous organic basic solution such as TMAH, NaOH;
for cyclized rubber-based type negative PR, developer is organic solvents. (5) Strip-
per: Stripper refers to chemicals used to remove PR after development and subse-
quent processes such as wet etch, dry etch, implantation, etc. These process steps
may cause structural changes in the photoresist and result in difficult to remove PR;
thus, stripper needs to have strong solubility to PR. Its basic components are organic
solvent and organic amine additives, commonly used stripping solvents include
N-methyl pyrrolidone (NMP), dimethyl sulfoxide (DMSO), and so on.

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Auxiliary Material in Process
79
Deren Yang, Maojun Wang, and Xuegong Yu

Contents
Immersion Fluid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
High-Purity Specialty Gases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
Precise Processing Materials for Si Wafers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
Quartz Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
Quartz Diffusion Tube . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
Quartz Crucible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
Quartz Bell Jar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
Quartz Boat/Basket/Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
Ultra-pure Chemicals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1757
Cleaning and Etching Chemicals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
Chemical Mechanical Polishing Slurry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
Chemical Mechanical Polishing Pads and Conditioning Discs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
Doping Reagents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764
Aluminum Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1765
Titanium Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
Key Characteristics of Ti Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
Fabrication of Ti Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
Tantalum Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
The Specific Requirement of Ta Target [9, 10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
Fabrication of Ta Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
Copper Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
Precious Metal Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
Application of the Precious Metal Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1772
Fabrication of the Precious Metal Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1772
Recycle of the Precious Metal Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1772
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1773

D. Yang (*) · X. Yu
State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China
e-mail: mseyang@zju.edu.cn
M. Wang
School of electronics engineering and computer science, Peking University, Beijing, China

© Publishing House of Electronics Industry 2024 1743

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_79
1744 D. Yang et al.

Abstract
The auxiliary materials used for the IC manufacturing have many kinds of
categories, which basically include high-purity special gases, precise processing
materials for Si wafers, quartz products, ultra-pure chemicals, chemical mechan-
ical polishing materials, and metal targets. Among them, the immersion fluid with
high refractive index filled the gap between the final projection lens and the wafer
in immersion lithography, acts as an additional liquid lens, which can improve the
special resolution of photolithograph. The special gas with purity greater than
99.99% is necessary for the film deposition. Quartz products are indispensable
accessories, mainly including quartz diffusion tube, quartz crucible, quartz bell
jar, and quartz boat/basket/bracket. Ultra-pure chemicals commonly used in IC
manufacturing have more than 30 kinds, like various acids, alkali, organic
solvents, oxidizing reagents, etc. Besides, the polishing slurry, pads, and condi-
tioning disc are necessary for the wafer polishing, as well as the aluminum,
titanium, tantalum, copper, and other precious metal targets are used for electrode
contacts and interconnects.

Keywords
Auxiliary materials · Special gases · Quartz products · Ultra-pure chemicals ·
Chemical mechanical polishing materials, metal targets

Immersion Fluid

The immersion fluid is a kind of liquid with high refractive index used to fill the gap
between the final projection lens and the wafer surface in DUV immersion lithog-
raphy. The liquid acts as an additional liquid lens, working with the optical system to
achieve nm-scale exposure linewidth as shown in Fig. 79.1. The immersion fluid is
the main feature distinguishing the immersion lithography from traditional dry
lithography with only air as the medium between the projection lens and the wafer.
In the development of lithography technology, reducing the wavelength of laser
source has been always used as the most effective way to improve the exposure
resolution. However, after the successful application of 193 nm wavelength laser in
lithography technology, the following technology of 157 nm wavelength runs into
unsolved problems by lens manufactures. Therefore, 193 nm immersion lithography
is proposed to achieve higher exposure resolution. The medium between the pro-
jection lens and the wafer in the traditional 193 nm dry lithography machine is the air
with a refractive index of about 1, corresponding a numerical aperture (NA) of about
0.93. The exposure linewidth cannot be smaller than 65 nm. However, in the 193 nm
immersion lithography tools, the immersion technology inserts an liquid into the gap
between the lens and the wafer surface, instead of the air gap, For example, ultra-
pure water is a kind of immersion fluid with a refractive index of 1.44, which can
improve the NA to about 1.35, and reduce the exposure linewidth to 45 nm. In
79 Auxiliary Material in Process 1745

Fig. 79.1 The schematic diagram of immersion lithography machine

addition, the exposure light is more easily to converge on the photoresist (PR),
increasing the exposure depth of focus (DOF) due to the raise of the NA, so as to
increase the clear range of etching and improves the lithography quality.
At present, the immersion liquid used in commercial immersion lithography is
ultra-pure water without bubbles, which has good transmittance and high refractive
index for 193 nm wavelength. It is insensitive to the temperature variations, and not
easy to react with the lens material. In addition, water has a relatively low viscosity,
which benefits high-speed scanning. However, because the immersion liquid acts as
the last lens in the optical path, it must be highly pure, homogeneous, and stable. In
order to meet the exposure requirements, it is necessary to transform the semicon-
ductor fab water into immersion liquid by a fluid treatment system with an efficient
and reasonable decontamination process. So that dissolved oxygen, TOC, particle
content, and many other parameters can meet the requirements of cleanliness index.
Meanwhile, suitable designs of the pipeline and flow-components are required to
avoid secondary pollution during the treatment and transportation of the immersion
liquid, and to achieve accurate, continuous, and unfluctuating immersion liquid
supply. Furthermore, during the actual exposure process, the filling of the immersion
liquid may induce new defects (e.g., contamination caused by the precipitation of
photoresist in the immersion liquid, air bubbles introduced during initialization and
scanning process, local temperature rise of the flow by the exposure, etc.). The defect
sources will affect the uniformity of the immersion flow field, resulting in the
discontinuous refractive index of the liquid, and lowering the exposure quality.
Therefore, in the actual exposure process, the immersion liquid needs to be updated
in real time to maintain a high cleanliness and uniformity of the immersion liquid. In
addition, because of the strong viscous shearing effect caused by the high-speed
scanning of the wafer to the immersion liquid, it is easily to make the flow field
boundary unstable and cause leakage, so the boundary constraint and control of the
immersion flow field are also crucial [1].
1746 D. Yang et al.

Increasing the refractive index of the immersion liquid may be the most direct and
effective way to develop higher resolution in the immersion lithography. Therefore,
optical modification of the immersion liquid and development of the second-
generation and third-generation high refractive index immersion liquid has become
hot topics in the field of the immersion lithography. When salt or naphthene series
are added to the immersion liquid, the refractive index can be increased to 1.65 and
the NA can be increased to about 1.5. By adding nanoparticles into the immersion
liquid [2], the refractive index can be increased to 1.8 and the NA to about 1.7.
However, due to the change of uniformity and flow characteristics of the immersion
liquid after optical modifications, it presents new challenges to the preparation and
control of the immersion liquid. Currently, the above techniques are still in research
stage.

High-Purity Specialty Gases

Specialty gases are widely used in large-scale ICs, light-emitting diodes (LEDs), flat
panel displays (FPDs), and other electronic device manufacturing. The usage in
these applications is approximately 1/3 of all materials consumed. Generally, the
special gases used in various manufacturing processes, especially the ones in direct
contact with wafers, are called high-purity special gases, or high-purity electronic
grade gases. The most notable characteristics of this type of gases are their high-
purity level and safety hazards. Since they are used in front-end-of-line (FEOL)
processes such as chemical vapor deposition (CVD), etching, ion implantation
(IMP), and epitaxy, the content of impurities in the gas directly affects wafer quality
and yield. Thus, the basic requirement of gas purity is generally higher than 99.99%
(4N), and will further increase with ever scaling advanced technology nodes.
Another key feature of special gases is the safety hazards of high pressure, flamma-
bility, corrosion, extreme toxicity, etc. Therefore, the safety requirements for gas
cylinders, including valves, are very strict and demanding. Tables 79.1 and 79.2 list
the gas purity and package requirements for commonly used specialty gases.
There are approximately 30 most commonly used high-purity special gases. They
can be categorized into three groups based on their chemical properties:

(1) Alkylate Gases: Majority alkylate gases consist of metal and hydrogen atoms,
such as silane (SiH4), phosphine (PH3), arsine (AsH3), germane (GeH4), etc. The
chemical formula can be represented as MxHy or MxHyXz, where M ¼ metal,
H ¼ hydrogen, and X ¼ other functional groups. This group of gases is well
suited for chemical vapor deposition (CVD), diffusion, and ion implantation
processes due to its unique properties. Under relatively mild conditions
(i.e., moderate temperature, energy input, pressure), these gases can be
decomposed into required components or dopants for thin film formation.
More importantly, the decomposed by-product, hydrogen, or other highly vol-
atile species, can be easily removed from the wafer surface, and thus not creating
any negative impact to wafer performance as well as the equipment. This group
79 Auxiliary Material in Process 1747

Table 79.1 (I): The usage, purity and package requirement of high-purity specialty gases
Purity
Gas name Application (>¼) Cylinder type Valve type
SiH4 Chemical vapor 99.9999% 47 L, 450 L DISS632
deposition
SiH2Cl2 Chemical vapor 99.9% 47 L DISS636
deposition
WF6 Chemical vapor 99.999% 10 L DISS638
deposition
N2O Chemical vapor 99.9995% 47 L, 450 L DISS712
deposition
NH3 Chemical vapor 99.999% 47 L DISS720/
deposition CGA660
SiF4 Chemical vapor 99.999% 47 L DISS642
deposition
PH3 Chemical vapor 99.9996% 47 L DISS SA-A
deposition sub-atmospheric
Si2Cl6 Chemical vapor 99.9999% 18 L 1/4VCR
deposition
C3H6 Chemical vapor 99.95% 47 L JIS 22-14L
deposition
SiH(CH3)3 Chemical vapor 99.99% 47 L DISS632
deposition
HCl Chemical vapor 99.999% 47 L CGA330/JIS
deposition 26-14-OR
HF Chemical vapor 99.999% 47 L JIS 22-14-OR
deposition
He Chemical vapor 99.9999% 47 L DISS718
deposition
1%PH3/N2 Chemical vapor 99.999% 47 L DISS632/
deposition CGA350
5% B2H6/N2 Chemical vapor 99.999% 47 L DISS632
deposition
5%H2/He Chemical vapor 99.9999% 47 L DISS724
deposition
10%CH4/Ar Chemical vapor 99.99% 47 L DISS724
deposition
GeH4/H2 Chemical vapor 99.998% 47 L DISS632/
deposition CGA350
20%F2/N2 Chemical vapor 99.9% 47 L JIS 22-14-OR
deposition
NF3 Etch/clean 99.99% 47 L, 450 L DISS640
CF4 Etch/clean 99.9997% 47 L DISS716
CO Etch 99.996% 47 L DISS724
HBr Etch 99.999% 47 L DISS634
CO2 Etch 99.999% 47 L,450 L DISS716/
CGA320
CH3F Etch 99.99% 47 L DISS724
(continued)
1748 D. Yang et al.

Table 79.1 (continued)

Purity
Gas name Application (>¼) Cylinder type Valve type
SiCl4 Etch 99.9999% 47 L JIS 22-14R
BCl3 Etch 99.999% 47 L DISS634
CHF3 Etch 99.999% 47 L DISS716
CH2F2 Etch 99.998% 47 L DISS724
Cl2 Etch 99.999% 47 L DISS634
C4F6 Etch 99.5% 47 L CGA724
C2F6 Etch 99.999% 47 L DISS716
SF6 Etch/clean 99.99% 47 L DISS716/
CGA590
C4F8 Etch/clean 99.999% 47 L DISS716
CH4 Etch 99.9999% 47 L JIS 14 L
4%H2/N2 Etch 99.9999% 47 L DISS724
BF3 Ion implantation 99.9% 2.2 L 1/4VCR
sub-atmospheric
PH3 Ion implantation 99.9997% 2.2 L 1/2VCR
sub-atmospheric
AsH3 Ion implantation 99.9995% 2.2 L 1/2VCR
sub-atmospheric
Xe Ion implantation 99.995% 47 L CGA580
GeF4 Ion implantation 99.9% 2.2 L 1/4VCR
sub-atmospheric
1.2%He/N2 Photolithography 99.9999% 47 L DISS718
3.5%Ar/ Photolithography 47 L DISS718
10ppmXe/Ne
0.95%F2/3.5% Photolithography 47 L DISS728
Ar/Ne
1.25%Kr/Ne Photolithography 47 L DISS718
0.95%F2/1.25% Photolithography 47 L DISS728
Kr/Ne
a
47 L cylinder size includes 44–49 L type, 450 L cylinder is also called Y cylinder

of gases is also widely used in red, yellow, and blue light-emitting diodes (LEDs)
manufacturing, especially for AsH3, PH3, and NH3 in GaAs, GaP, GaN, and
GaAsP formation using MOCVD process.

Alkylate gases in CVD reaction:

SiH4 þ Δheat ! Si ðthin filmÞ þ H2

SiH4 þ N2 O þ Δheat ! SiO2 ðthin filmÞ þ N2 þ H2

Alkylate gases in ion implantation:

79 Auxiliary Material in Process 1749

Table 79.2 (II): Impurity type and content of commonly used high-purity specialty gases [3, 4]
High-purity specialty gases
NF3 nitrogen N2O nitrous WF6 tungsten AsH3
SiH4 silane trifluoride oxide hexafluoride arsine
Impurities 99.9999% 99.9% 99.9995% 99.9995% 99.9995%
DIFF/CVD Etch/Clean DIFF/CVD DIFF/CVD IMP
<¼ (ppmv) <¼ (ppmv) <¼ (ppmv) <¼ (ppmv) <¼ (ppmv)
H2 20
N2 0.5 126 3 0.5 2
O2/Ar 0.06 110 1 0.5 1
CH4 0.04 0.5
CO 0.08 25 0.1 0.5 0.1
CO2 0.05 16 0.5 0.5 0.5
THC 0.1 0.1
(C2–C4)
H2O 0.5 1 2
Si2H6 0.5
Disiloxanes 0.05
NH3 0.1
NO2 0.1
NO 0.1
CF4 564 0.5
HF 1 1
SF6 24 0.5

AsH3 þ e ! Asþ ðdopantÞ þ H2

PH3 þ e ! Pþ ðdopantÞ þ H2

Alkylate gases are almost all possess the hazardous properties of flammability,
explosiveness, highly toxicity, and high pressure as listed in Table 79.3. The safety
requirements for gas equipment and the operations are very high. Under normal
circumstances, the gas cylinders in use are required to be stored in certified gas
cabinets. The gas cabinet consists of multiple high-pressure valves, regulators,
gauge/transducer, cycle purge unit, etc. It has the capability of pressure regulating
(normally reducing the pressure), cycle purging, leak testing, isolation, and emer-
gency shut-off. It is also equipped with various sensors for toxic, flammable and
corrosive gases, and corresponding scrubbers. In addition, the gas cabinet must be
maintained under sub-atmospheric pressure and with sufficient ventilation. When
replacing cylinder, dual operators are required, and self-contained breathing appa-
ratus (SCBA) and other personal protection equipment (PPE) must be worn.
Sub-atmospheric gas delivery technology is presently used for processes which
require higher safety protections, such as in ion implantation process. Commonly
1750 D. Yang et al.

Table 79.3 Physical and chemical properties and safety classification of alkylate gases
AsH3 PH3 SiH4 GeH4 NH3
Molecular 77.9 34 32 76.6 17
weight (MW)
Boiling point 62.5 87.7 112.1 88.1 33.4
b.p. ( C) at
1 atm
Melting point 116.8 133.8 185 165.9 77.7
m.p. ( C)
Gas density 3.228 1.408 1.3 3.174 0.705
(g/L) @21.1  C
Liquid density 1.321 0.491 0.43(40  C) 0.859 0.602
(g/ml) @25  C
Vapor pressure 15 35 CT -3.5  C 39 10
(VP) (atm)
@25  C
Threshold limit 0.05 0.3 5 0.2 25
values
TLV (ppm)
Lower 4.5 1.2 1.4 2.8 15
explosion limit
(LEL) (%)
Upper explosion 78 98 96 98 25
limit (UEL) (%)
Safety class 2.1;2.3 2.1;2.3 2.1;2.3 2.1;2.3 2.3;8.2
(UN-14,
UN-16)
Safety hazard Toxic, Toxic, Toxic, Toxic, Toxic,
flammable spontaneously spontaneously explossive corrosive
flammable flammable
CT critical temperature, 1 atm ¼ 101.325 kPa.

Fig. 79.2 Illustration of adsorption based sub-atmospheric technology

used technologies include SDS ®, Uptime™, AGS, etc. The adsorption based
sub-atmospheric technology and its safety features are illustrated in Fig. 79.2.
Adoption of these technologies can minimize the possibility of significant toxic
gas leaking, e.g., the leak rate can be reduced by as much as 100,000 times as
compared to conventional high-pressure cylinders [5] as illustrated in Fig. 79.3.
79 Auxiliary Material in Process 1751

Fig. 79.3 Leak rate comparison between sub-atmospheric and high-pressure gas sources: 100,000
times difference

(2) Halogenated Gases and Other Gases: The specialty gases including Fluorine
(F), Chlorine (Cl), Bromine (Br), and Iodine (I) are called halogenated gases.
Since most of these gases used in IC manufacturing contain F, they are also
generally called fluorinated gases or F containing gases. The most notable
characteristics of this kind of gas is that the halide element has a strong chemical
reactivity. Under the conditions of high temperature or electric potential, halo-
genated gases will produce corresponding plasma or radicals which react with
Si, silica, Si-nitride, metals, and other materials to form corresponding volatile
gases, that can be removed from the wafer surface and/or internal chamber
surface of the equipment tools. Therefore, this group of gases is particularly
suited for dry cleaning and etching processes in IC manufacturing. Typical
cleaning gases include NF3, SF6, CF4, C2F6, C3F8, and ClF3. The etching
gases have more variations, but mostly consist of fluorocarbon compound,
such as CF4, CHF3, CH3F, CH2F2, C2F6, C4F6, C4F8, C5F8, etc. The fluorine/
carbon (F/C) ratio is an important parameter for this kind of gases. By adjusting
the fluorine/carbon ratio, the etching rate, selectivity, anisotropy, and uniformity
can be altered or optimized according to process requirement. In addition to the
etching process, several fluorinated molecules such as BF3, GeF4, and SiF4 are
also used for the ion implantation process.

Dry etch reaction of fluorinated gases:

CF4 þ e ðelectric potentialÞ ! 2F þ CF2 ðplasma or radicalsÞ

SiO2 þ 4F ! SiF4 ðgasÞ þ O2 ðgasÞ

SiO2 þ 2CF2 ! SiF4 ðgasÞ þ 2CO ðgasÞ

Halogenated gases are not as toxic as alkylate gas, but their high-pressure nature
still poses significant safety risk (Table 79.4), thus the safety measures of its
equipment and operating procedures are basically the same as the standard of
1752 D. Yang et al.

Table 79.4 Physical and chemical properties and safety classification of halogenated gases
NF3 SF6 CF4 C4F8 ClF3
Molecular 71 146 88 200 92.5
weight (MW)
Boiling point 129 50.7 128 5.98 11.5
b.p. ( C) at
1 atm
Melting point 206.7 63.9 184 40.2 83
m.p. ( C)
Gas density 2.94 6.05 3.64 8.28 3.729
(g/L)
@21.1  C
Liquid density 1.2 1.32 1.3(80  C) 1.442 1.785
(g/ml) @25  C (70  C)
Vapor pressure CT 22.5 CT 45.5  C 1.68 1.5
(VP) (atm) 39.3  C
@25  C
Threshold limit 10 1000 / / 0.1
values
(TLV) (ppm)
Lower / / / / /
explosion limit
(LEL) (%)
Upper / / / 18.7 /
explosion limit
(UEL) (%)
Safety class 2.3 2.2 2.2 2.2 2.3, 8.2
(UN-14,
UN-16)
Safety hazard Toxic Nonflammable Nonflammable Nonflammable Toxic,
corrosive
CT critical temperature

alkylate gas. One of the drawbacks of using fluorinated gas is its by-product,
perfluorocarbon chemicals (PFC), as considered as the major global warming gas.
With the strengthening of environment protection measures, etching and cleaning
gases such as C4F6, and F2, which are relatively more environmentally friendly, will
be more widely utilized [6, 7].
In addition to alkylate and halogenated gases, there are a few gases used by
photolithography process in IC manufacturing. They are also called laser gases, such
as Fluorine (F), Krypton (Kr), and Neon (Ne) based mixtures, 0.95%F2/1.25%KrNe,
3.5%Ar/10ppmXe/Ne, etc. The usage of laser gases is limited but they are indis-
pensable. There are some other gases that do not belong to above gas groups from
chemical property point of view, such as N2O, NO, epitaxial gases SiCl4, SiHCl3,
SiH2Cl2, PCl3, etc. These gases are used in various processes with the same
requirements of purity, safety package, as well as operating procedures.
79 Auxiliary Material in Process 1753

Precise Processing Materials for Si Wafers

Nowadays, the grinding process is mainly double-side grinding, and its working
mechanism is physical and mechanical removal. The commonly used abrasives are
the powders of silicon carbide (SiC), diamond, Alumina (Al2O3), or boron carbide
(BC), and their sizes range from 10 nm to tens of μm (Fig. 79.4). In application,
certain dispersing agents are required to be added to make those abrasive powders
well dispersed in water. In the grinding process, the polishing discs are commonly
made of Cu and Epoxy/Resin with large areas to hold multi Si wafers.
After grinding, the Si wafers require some further polishing treatments to achieve
better surface conditions. The polishing process normally has three steps: rough
polishing, edge polishing, and fine polishing. Those polishing slurries are made of
nano-sized SiO2 particles, water, and the corresponding chemical formula, which is
usually used under alkaline conditions. (1) In coarse polishing, both sides of the
wafers require to be polished. With the help of the chemical and mechanical
polishing, the rough slurries remove micrometer-level thickness (um) of Si from
the wafer surface to minimize the non-uniformity of wafer thickness. Post rough
polishing, the warpage needs to be under control and no serious surface damages or
scratches are observed on wafer surface. As results, surface roughness is at the level
of nanometers (nm) and the concentration of metal ions on the silicon surface
reaches a certain standards. The consumption of rough slurries is very large, in
order to save costs, generally need to be recycled. Currently, the major suppliers are
Fujimi, Nitta Hass, Hitachi Chemical in Japan, Dow Chemical in USA, ACE in
Korea, etc. (2) In edge polishing, the main purpose of edge slurries is to achieve a
high degree of smoothness on wafer edges. The consumed amount is much less than
that of rough slurries. The main suppliers are often the same as the rough slurry
suppliers. (3) Fine polishing is the last step in the polishing process. It has very
stringent requirements for the atomic lattice arrangement, defects, and the concen-
tration of metal ions on the wafer surface. Therefore, it holds very high standards on
the raw materials of fine polishing slurries, e.g., good control of the metal ion

Fig. 79.4 Picture of abrasive

powders for grinding
1754 D. Yang et al.

concentration, size distribution, surface morphology, and purity in slurry formula-

tion. The final polishing slurries cannot be recycled in usage. Fujimi in Japan is
taking a leading position at both technology and market shares. In addition,
polishing pads are another important consumable in the polishing process. The pad
is normally made of foamed poly-urethane. As a result, hardness, compressibility,
groove morphology, and depth all have impacts on the final polishing performance.

Quartz Products

In IC manufacturing process, quartz products are indispensable accessory products,

mainly including quartz diffusion tube, quartz crucible, quartz bell jar, and quartz
boat/basket/bracket.

Quartz Diffusion Tube

The quartz diffusion tube is mainly used for the oxidation and diffusion processes in
the IC chip production line. This kind of quartz diffusion tube usually adopts the
continuous melting molding process. The purified quartz is sent to a continuous
melting furnace, and then through the high-temperature melting and drawing method
to form desired quartz tube.
Quartz lathe is a necessary equipment for the processing of quartz diffusion tubes.
The producing process is that the two ends of the quartz diffusion tube are clamped
on the lathe, in which the whole pipeline is kept concentric by mechanical rotation,
and the middle area is equipped with a different number of blowlamps. Under the
operator’s control, the temperature of the flame is adjusted, and the tube is shaped to
the requirements. At present, the maximum diameter of quartz diffusion tube can
reach 800 mm with a length of up to 3500 mm. In the processing of the quartz
diffusion tube, the hot-processing glass lathe is generally used for sealing, shaping,
and diameter resizing steps, and then the ball joints, TC (thermal couple) tubes, and
flanges are welded by the hand lamp hot processing. In order to improve the
temperature resistance of quartz diffusion tubes, a high-temperature coating process
is usually used to coat SiO2, SiC, Al2O3, or other material on the surface of the quartz
diffusion tube by using a lathe, as shown in Fig. 79.5. The quartz diffusion tube can
be intermittently or continuously used at a high temperature of 1280–1300  C, and
the service lifetime of the quartz tube also improved.

Quartz Crucible

As shown in Fig. 79.6, it is a quartz crucible, which can be divided into quartz
crucible for single crystal silicon and for casting polycrystalline silicon (as poly-Si).
(a) The quartz crucible for single crystal Si is a voltaic arc quartz crucible
produced by using high-purity quartz sand and is used for the growth of straight
79 Auxiliary Material in Process 1755

Fig. 79.5 Quartz diffusion

tube high-temperature coating

Fig. 79.6 Quartz crucible

pull single crystal silicon. It has strong resistance to thermal vibrations, anti-
crystallization, and extremely low heat transfer and dielectric loss characteristics.
It can be used continuously at 1450  C. In order to avoid the crystallization of quartz
crucible during the crystal pulling process, it is generally sprayed with strontium
carbonate (SrCO3) on the surface of the quartz crucible, so that the quartz crucible
will rapidly form a uniform and dense β-square quartz layer on surface during the
crystal pulling process. This β-square quartz layer can ensure the smooth crystal
pulling process of the single crystal Si. The diameter of the quartz crucible for
straight-pulling single crystal Si is generally between 400 mm and 600 mm. (b)
Quartz crucible for casting poly-Si is a quartz ceramic crucible made of high-
purity fused silica. It has strong thermal stability, corrosion resistance, as well as
compression/deformation strength, and is generally used in the production of poly-Si
ingots in the solar photovoltaic industry. It can be used at 1600  C high temperatures.
In order to prevent the quartz crucible used for casting poly-Si from being dissolved
during the crystal growth and resulting in an increase of oxygen (O) concentration in
1756 D. Yang et al.

the poly-Si ingots, a Si3N4 coating is usually applied to the inner wall of the quartz
crucible.

Quartz Bell Jar

The quartz bell jar is shown in Fig. 79.7. Generally, the quartz bell jar is used
together with the quartz pedestal and the vertical quartz boat, and is mostly used for
the epitaxial process of semiconductor IC chip production. The epitaxial furnace
generally adopts a vertical structure, and the quartz bell jar is placed outside of the
vertical quartz boat, and the quartz pedestal is used as a support. The quartz bell jar is
generally sealed directly by a glass lathe, and the top of the quartz bell jar can be
divided into a dome, a flat top, a flange butt joint, etc. After necessary cleaning
treatment, the gas pipe, nozzle, and other accessories are welded in the quartz bell jar
by manual operation. Then, to grind it according to the requirements of flatness and
parallelism by grinding lathe, and the grinding surface must be flat to ensure the
sealing of the flange is good and no air leakage occurs. At present, the size of
domestic quartz bell jars and their supporting products can reach 300 mm. In order to
improve the thermal insulation performance of the bell jar, the quartz flange is
generally made of a milky white quartz material, which can make the heating
temperature uniform, thereby greatly improving the yield of the chip.

Quartz Boat/Basket/Paddle

Quartz boats are generally used in the diffusion, oxidation, CVD processes of Si
wafers, as shown in Fig. 79.8. Since the quartz boats are directly in contact with the
single crystal Si wafers, the purity and precision requirements of quartz boats are
quite strict. In the process of quartz boats, graphite mold is used for positioning, and
it also needs to go through spot welding, full melting welding, fire polishing, and

Fig. 79.7 Quartz bell

79 Auxiliary Material in Process 1757

Fig. 79.8 Quartz boat

other processes. For large-size, high-precision quartz boat products, a 3D measuring

instrument is also required. Different IC chip production lines have different require-
ments for quartz boats. As a carrier of the quartz boats, the quartz paddles can be
used to send the quartz boats into or out of the quartz diffusion tube, in order to avoid
secondary pollution, and other tools are also prohibited from contacting the diffusion
furnace tube. Usually, a quartz paddle can hold 3–5 quartz boats at a time. The quartz
baskets are mostly used for pickling and ultrasonic cleaning processes of Si wafers,
and also used as a support for Si wafers. The quartz basket is welded after being
grooved on a quartz rod, or directly assembled and welded with quartz sheets and
handles, and the specifications are different.

Ultra-pure Chemicals

Ultra-pure chemicals, also referred as high-purity chemicals, are electronic-grade

chemicals used in IC manufacturing. Ultra-pure chemicals have ultra-high purity and
ultra-high cleanliness with stringent requirements on the environment cleanliness
during manufacturing, package, transportation, and usage. There are more than
30 kinds of ultra-pure chemicals commonly used in IC manufacturing, including
various acids (e.g., sulfuric, hydrochloric, nitric, and phosphoric acids), alkali (e.g.,
ammonium hydroxide, potassium hydroxide), organic solvents (e.g., acetone, iso-
propanol), oxidizing reagents (e.g., hydrogen peroxide), etc. These chemicals have
been widely used in the wafer cleaning and etching processes.
Due to the great impact of ultra-pure chemicals on the final IC products, yield,
and reliability, the IC industry strictly controls the concentration of trace impurities
in ultra-pure chemicals, mainly including metallic impurities, in-liquid particles,
1758 D. Yang et al.

Table 79.5 Summary of SEMI standards of ultra-pure chemicals

Metallic In-liquid particle Particle concentration
SEMI grade IC node impurity size (μm) (count/ml)
C1 (Grade 1) >1.2 um 1 ppm 1.0 25
C7 (Grade 2) 0.8–1.2 um 10 ppb 0.5 25
C8 (Grade 3) 0.2–0.6 um 1 ppb 0.5 5
C12 (Grade 4) 90 nm–0.2 um 0.1 ppb 0.2 a

Grade 5 <90 nm 0.01 ppb a a

a
Due to the limitations of in-liquid particle measurement, particle size and count are to be discussed
upon between manufacturer and user

anion impurities, etc. In order to build up the global standards of ultra-pure

chemicals, the Semiconductor Equipment and Materials International (SEMI)
established the chemical standardization committee of SEMI in 1975 to formulate
and standardize the international unified standards of ultra-pure chemicals. The
SEMI standards of ultra-pure chemicals are continuously updated according to IC
technology scaling and actual development of ultra-pure chemicals. For every ultra-
pure chemical, the SEMI standard consists in multiple technical standards (named as
“specification”) and maximum two guiding standards (named as “Guide”).
Table 79.5 summarizes the international SEMI standards of ultra-pure chemicals
based on IC technology nodes, which emphasizes the key impurity types in ultra-
pure chemicals and the related specifications. The above table is just a brief summary
of the SEMI standards for the most commonly used ultra-pure chemicals. The
specific specification of a particular chemical may differ from the values listed in
the table. In addition, it should be noted that IC makers often have special require-
ments for the ultra-pure chemicals. In this case, the specifications of the ultra-pure
chemicals are often decided by negotiations between chemical suppliers and users.
As can be seen from Table 79.5 clearly, the high-end IC manufacturing requires
higher purity chemicals. At present, the world’s most advanced IC production
technology has reached 10 nm and below, which undoubtedly needs tightened
requirements for the quality of ultra-pure chemicals. The worldwide chemical
manufacturers also continue to increase the investment in R&D of ultra-high-purity
chemicals as required for future generations of IC. Technological advances will also
prompt the International Organization for Standardization of SEMI to continuously
improve existing standards to meet the development of IC industry.

Cleaning and Etching Chemicals

Cleaning and etching chemicals are usually formulated mixtures of two or more
chemical reagents with a predefined mixing ratio. They are mainly used in wet
cleaning and etching processes of IC manufacturing. When using the ultra-pure
chemicals mentioned in the previous section in IC manufacturing, these ultra-pure
79 Auxiliary Material in Process 1759

chemicals can be used alone or in combination as a mixture for the specific process
steps. For example, the well-known standard clean 1 (SC-1) is a mixture of H2O2,
ammonium hydroxide (NH4OH), and ultra-pure water in a certain proportion, which
is widely adopted to remove particulate contamination from wafer surfaces. How-
ever, the cleaning and etching chemicals are formulated and mixed by the chemical
manufacturer according to a proprietary formula and blending ratio and supplied to
IC manufacturers for direct use. The chemical manufacturer owns the intellectual
property rights of the chemicals.
Compared with the ultra-pure chemicals, the main characteristics of the cleaning
and etching chemicals are high technical content and strong technological compat-
ibility. Most of the cleaning and etching chemicals are designed for a particular
cleaning or etching process in IC manufacturing. At the same time, different IC
manufacturing processes and technology nodes will impose different quality and
process requirements of these cleaning and etching chemicals. The cleaning and
etching chemicals mainly include photoresist stripper, post etch polymer removal,
post Cu CMP cleaning solution and etchant, etc. As proprietary mixture, in general,
the physical and chemical properties of these cleaning and etching chemicals are
difficult to be quantitatively measured by ordinary instruments, and their effective-
ness can only be evaluated by means of process application and qualification.
Table 79.6 lists some cleaning and etching chemicals commonly used in IC
manufacturing.

Chemical Mechanical Polishing Slurry

Chemical Mechanical Polishing (CMP) slurry is one of the key materials applied in
the CMP process of IC manufacturing. CMP Slurry is made of nano-size abrasive
particles, various chemical agents, and deionized water. To meet specific require-
ments of certain polishing process and removed materials, different kinds of abrasive
particles (SiO2, Al2O3, CeO2, etc.) and various chemical agents (metal complexing
agents, inhibitors, oxidants/reductants, dispersing agents, and other agents) are
applied in the formulation of CMP slurries. The final packaging of CMP slurry
products is shown in Fig. 79.9. Based on their applications, CMP slurries are widely
used in front-end-of-line (FEOL) and back-end-of-line (BEOL) process steps of IC
manufacturing (e.g., Fin Field-Effect Transistor (FinFET), shallow trench isolation
(STI), W-plug, Cu dual-damascene, etc.). Along with the scaling of process tech-
nology nodes, the number of CMP process steps increases to 20–30. The removed
materials include different metals (Co, Al, W, Cu, Ta, etc.) and non-metal materials
(SiO2, Si3N4, Si etc.). The required corresponding slurries have also become more
complex, and the requirements for the polishing effect to be achieved by the slurries
have also been increasing.
Moreover, CMP slurries are applied to the process of through-Si-via (TSV) for
advanced packaging technology, where the slurry requirements are quite different
due to the differences in processes and removal materials. In the year 2022, the
1760 D. Yang et al.

Table 79.6 Cleaning and etching chemicals commonly used in IC manufacturing processes
Chemical Chemical
category name Major components Applications and features
Photoresist Positive-tone Amines, organic solvents, Amines provide alkaline
stripper photoresist corrosion inhibitors, etc. environment for the solution,
stripper which can section the long
chain of phenolic resin, the
main component of positive
photoresist. Organic solvents
dissolve the decomposed
molecules. Corrosion
inhibitors will adsorb on the
metal surface and prevent
metal corrosion
Negative- Organic bases, organic After exposure, the
tone solvents, corrosion molecular chains of negative
photoresist inhibitors, etc. photoresist undergo strong
stripper crosslinking reaction.
Organic alkali decomposes
highly crosslinked poly-
methyl methacrylate and
polyimide into small
molecular compounds.
Organic solvents dissolve
the decomposed molecules.
Corrosion inhibitors will be
adsorbed on the metal
surface to prevent metal
corrosion
Post etch Amine-based Amines, organic solvents, The typical process
polymer post etch corrosion inhibitors, water, temperature is up to around
removal polymer etc. 70  C, featuring good
(aluminum removal cleaning efficiency for post
interconnect) etch clean in aluminum
interconnect. Corrosion
inhibitors can effectively
protect aluminum line from
corrosion. The chemical is
expensive and requests extra
IPA or NMP intermediate
rinse
Fluorine- HF (NH4F, NH4HF2, or Mainly used in batch-spray
based post other fluorides), pH buffer, tool and single-wafer tool
etch polymer organic solvents, corrosion with much lower process
removal inhibitors, water, etc. temperature for post etch
clean in aluminum
interconnect. The fluorine-
based post etch polymer
removal can be rinsed
directly with ultra-pure
water without any
intermediate rinse
(continued)
79 Auxiliary Material in Process 1761

Table 79.6 (continued)

Chemical Chemical
category name Major components Applications and features
Post etch Fluorine- HF (NH4F, NH4HF2, or The chemical is expensive
polymer based post other fluorides),pH buffers, with good cleaning
removal etch polymer organic solvents, Cu performance and large
(copper removal corrosion inhibitors, water, process window for Cu
interconnect) etc. interconnect post etch
cleaning. Corrosion
inhibitors can inhibit the
etching of copper
interconnect by cleaning
solution
Peroxide- Ammonia fluoride, organic After pre-mixed with
based post amines, water, heterocyclic hydrogen peroxide, the
etch polymer compounds, etc. chemical is able to remove
removal polymer residue and
partially or fully etch TiN
metal hardmask at the same
time. To maintain a stable
clean and etch performance,
the chemical is not recycled,
and is discharged directly
after a single-pass cleaning
Post Cu CMP Post Cu Complexing agent, Used for post copper CMP
cleaning CMP corrosion inhibitor, cleaning. The particles on
solution cleaning surfactant, pH regulator, etc. the wafer surface can be
basic effectively removed in the
solution alkaline solutions. Corrosion
inhibitors can reduce the
etching of copper lines and
insulating materials.
Surfactants can improve the
surface wettability and
cleaning efficiency
Post Cu Organic acids, complexing Organic acids and
CMP agents, surfactants, etc. complexing agents can
cleaning effectively remove metallic
acidic impurities on the wafer
solution surfaces, and surfactants can
improve the surface
wettability and particle
removal efficiency
Etchant Monocrystal HF, HNO3 (with or without The etch rates of
(polycrystal) the addition of H2SO4, monocrystal or polycrystal
silicon H3PO4) silicon can be controlled by
etchant the chemical concentration
or process temperature. The
surface morphology of the
etched silicon can be tuned
by the addition of H2SO4
and H3PO4
(continued)
1762 D. Yang et al.

Table 79.6 (continued)

Chemical Chemical
category name Major components Applications and features
High- H3PO4, additives Additives are able to
selectivity increase the etching
H3PO4 selectivity of silicon nitride
to silicon dioxide, and
inhibit the deposition of
reaction byproducts onto
wafer surfaces
Aluminum H3PO4, HNO3, CH3COOH Aluminum is oxidized by
etchant HNO3 and then dissolved by
H3PO4. CH3COOH acts as a
buffer solution to stabilized
aluminum etch rates
Etchant Copper H2SO4(or H3PO4), H2O2 The copper etching rate is
etchant (or other oxidants, such as fast. It is mainly used for
potassium persulfate, edge copper removal after
potassium bisulfate) copper plating and bump
UBM layer wet etching
Buffered HF, NH4F (with or without It is suitable for silicon
Oxide surfactants) dioxide wet etching with
Etchant photoresist pattern.
(BOE) Surfactant can improve the
surface wettability and
micro-roughness of silicon
wafer after etching

Fig. 79.9 Picture of final

packaging of CMP slurry
products

global CMP slurry market was valued at USD 1.58 billion, and the market size is
expected to increase to USD 2.54 billion by 2029, with a compounded annual
growth rate (CAGR) of 7.0%. There are more than ten manufacturing companies
79 Auxiliary Material in Process 1763

in the world. Cabot Microelectronics takes the leading position and holds ~35% of
the market. The second tier of suppliers includes US based companies (e.g., Air
Products as Versum Materials now and Dow Chemical) and Japan based companies
(e.g., Fujifilm, Fujimi, and Hitachi Chemical). Their market shares vary from 5% to
12%. Anji Microelectronics, as a domestic slurry supplier in China, has a market
breakthrough in this field. In 2015, Anji has realized the localization of slurry
products in China and started to enter the international market.

Chemical Mechanical Polishing Pads and Conditioning Discs

CMP pads are also important consumables in CMP processing. The main functions
of CMP pads are to provide friction forces and carry slurries during the polishing
process. It is one of the key factors to impact the polishing performance parameters,
such as polishing rate, uniformity, planarity, and defectivity. CMP pads are made of
polyurethane with special foaming and caking processes. According to the require-
ments in various CMP processes, the material formulation and manufacturing
processes can be adjusted to make the pads with different hardness, foam sizes,
compressibility, as well as the grooving patterns and depth. Fig. 79.10 is a sample
image of CMP pads. Nowadays, the main international pad supplier is Dow Chem-
ical with a global market share of ~80%. Cabot Microelectronics holds the second
position with a market share of ~10%. Chendu Times Lifu Technology Co., Ltd. has
begun to realize the localization of polishing pads, and its products have entered the
mainstream IC manufacturing companies in China. CMP conditioning disc is
another important consumable part in CMP processing. With the continuous
polishing process, the surface physical and chemical conditions of polishing pads
are constantly changed with time, which will lead to the reduction of polishing

Fig. 79.10 A sample picture

of CMP pads
1764 D. Yang et al.

Fig. 79.11 Picture of

samples of conditioning discs

efficiency and quality. Therefore, CMP discs are applied to keep conditioning the
pad surface to ensure the stability and repeatability of the polishing process. On
CMP discs, diamond particles are embedded on the substrate of metal plates. The
size, shape, and array pattern of diamond particles all can have impacts on the results
of conditioning. Figure 79.11 shows the sample image of conditioning discs. The
market of CMP conditioning discs is shared by 3M (USA), Saesol (Korea), Kinik
(China Taiwan), and other companies.

Doping Reagents

Semiconductors with completely perfect crystal structure are called intrinsic semi-
conductors. At room temperature, the concentration of carriers in intrinsic semi-
conductors is very low, resulting in poor conductivity and electronic properties. The
carrier concentration and conduction type of intrinsic semiconductor can be altered
by doping a certain amount and a certain kind of impurities into the intrinsic
semiconductor for the purpose of making various electronic devices. These doped
impurities are known as doping reagents or simply as dopants. After the high-
temperature activation, the doped impurity atoms take the place of the substrate
atoms to occupy the lattice position and increase the concentration of electron or hole
carriers; thereby the conductivity of the substrate is modulated. There are mainly two
approaches for semiconductor doping: High-temperature diffusion and ion implan-
tation. (1) Doping by high-temperature diffusion, the impurity atoms diffuse into the
substrate from a gas source or a deposited layer on the wafer surface. With this
method, the distribution of impurity concentration in the semiconductor is charac-
terized by high surface and low in the substrate body, and the specific distribution of
impurities is mainly determined by the doping temperature and diffusion time.
(2) Ion implantation doping is a technique in which neutral doping reagents are
first dissociated to form doped ions, and then these doped ions are implanted into
79 Auxiliary Material in Process 1765

Table 79.7 Doping Doping reagents Purity and package requirements

reagents commonly used in
B11 enriched B11F3 Purity >3N, safety delivery source
IC manufacturing
AsH3 Purity >5.5N, safety delivery source
PH3 Purity >5.5N, safety delivery source
BF3 Purity >3N
SiF4 Purity >3N, safety delivery source
GeF4 Purity >3N, safety delivery source

semiconductors in the form of ion beams by accelerating electric fields. The impurity
concentration has a maximum value in the semiconductor with the Gaussian distri-
bution, and its specific distribution behavior is mainly determined by ion mass and
the electrical field. Ion implantation doping can better control the doping profile and
concentration, and is more suitable for advanced IC devices. With the development
of integrated circuit technology, the diffusion process can no longer meet the
requirements for the manufacture of integrated circuits with small feature linewidth,
so advanced ion implantation technology is needed. In recent years, some other
doping technologies have emerged, such as plasma immersion ion implantation
doping (PIIID), projective gas immersion laser doping (P-GILD), rapid vapor-
phase doping (RVD), which are mostly used in thin film transistors, ultra-shallow
junction, and other special processes. The dopants used for elemental semiconduc-
tors are mainly group III and V elements or compounds, and the dopants used for
compound semiconductors are mainly group II and VI elements or compounds. The
purity of dopant usually reaches 99.9% (3N) or even 99.999% (5N). In addition,
because most dopants are highly toxic gases, a safe negative pressure packaging
technology, i.e., Safe Delivery Source (SDS), must be adopted. Borane, Arsine
(AsH3), and Phosphine (PH3) are the three most widely used dopants. In addition,
SiF4, GeF4, Diborane (B2H6), BBr3, and POCl3 are also important doping reagents.
Doping reagents commonly used in IC manufacturing are shown in Table 79.7.

Aluminum Targets

Aluminum (Al) targets are a kind of the vacuum sputtering targets, which is a key
material used for the metal conductor lines in ICs. According to the chemical
content, Al target could be made of pure Al or Al alloys, which includes Al-Si
alloy, Al-Cu alloy, Al-Ti alloy, etc. The purity, in general, ranges from 99.99% to
99.9995%. According to the different shapes, Al targets are divided into planar Al
targets and rotary Al targets. According to the different structure, Al target can be
divided into welded Al target and one-body type of Al target. According to the
different wafer sizes, the Al target is divided into 150 mm, 200 mm, 300 mm, etc.
The larger the wafer size for coating, the higher the requirements for the raw material
of Al target used for sputtering.
1766 D. Yang et al.

Fig. 79.12 Typical aluminum targets

In the process of Al target fabrication, the first step is purification. The low purity
aluminum is purified by electrolysis, segregation, etc., and the purity of 99.999% and
above high-purity aluminum block is obtained. Then the high-purity Al block is cast
by vacuum smelting to obtain a certain size of high-purity aluminum ingot. The
impurity content, macroscopic grain structure, internal defect level, and other indi-
cators of high-purity aluminum ingot need to be controlled strictly. Due to the rough
and large grain of the original high-purity aluminum ingot, it cannot be directly used
for the production of sputtering targets. It is necessary to fine-tune the internal grain
size of the material and optimize the grain orientation through a series of thermal
mechanical process such as forging, cross rolling, and heat treatment, so as to obtain
the sputtering target blank that meets the requirements. Then through brazing,
electron beam welding, diffusion welding and other ways to weld the target blank
with different alloy backplates, and after that, according to the drawings for precision
machining. Finally, the high-purity aluminum sputtering target was obtained by
automatic cleaning and vacuum packaging in the clean room. For the one-body
type of Al targets, the welding step is eliminated (Fig. 79.12).

Titanium Targets

Titanium (Ti) targets are made of high-purity Ti with certain process steps. It is used
in the PVD process to deposit Ti thin film as the barrier layer for Al conductor lines.
79 Auxiliary Material in Process 1767

Key Characteristics of Ti Targets

(1) Appearance: The Ti targets must be cleaned in clean room to ensure particle free
surface. The surface roughness also needs to be controlled to a certain level to meet
semiconductor requirement after the finish machining. (2) Internal defect control:
No defect, such as particles, voids, cracks etc., is allowed inside the Ti targets. (3)
Composition: Ti target is made of pure Ti or Ti-alloy. Ti-alloy target includes Ti-Al
target, Ti-N target, Ti-B, etc. The purity ranges from 99.9% to 99.999%. (4) Grain
size: Grain size of Ti target need to be fine and uniform. In general, the average grain
size is less than 50 μm. (5) Texture: The preferred crystal orientation of the titanium
target is < 002 >, and the proportion of this crystal orientation should be 35%.
(6) Geometric size: The size of Ti targets varies with different applications. In
general, the diameter ranges from 200 to 460 mm.
Ti target has one-body type and welded type. The manufacturing of the one-body
type target does not have the welding step, and it is made from high-purity Ti
workblank directly. Welded titanium target is to weld the titanium target workblank
with the backplane; the common welding methods include brazing and diffusion
welding. Welding backplane materials include copper and copper alloy backplane,
aluminum and aluminum alloy backplane, etc. After welding, the ultrasonic detec-
tion is applied to ensure that the connection between the target and the backplane has
a certain bonding strength to avoid debonding or cracking problems during the
sputtering process. The bonding quality requirements are shown in Table 79.8.

Fabrication of Ti Target

Pure Ti target is made through thermo-mechanic processing (TMP) with casting

ingot, while the Ti Al alloy target is usually made with powder metallurgy method.
As-casted high-purity Ti ingot is processed through forging, rolling, and heat
treatment to achieve certain dimension and the desired microstructures. Machining
is further applied to make the final product. After those thermo-mechanic processing
treatments mentioned above, the Ti target should have fine and uniform grain size
and dominate preferred texture, which can meet the requirements of titanium target
in sputtering process. The yield loss during these processes on the as-casted ingot is
quite significant (e.g., the yield loses during melting and oxidation, and machining
loses during forging and rolling). Therefore, the overall yield is around 80%.
Regarding some Ti-alloy targets, such as TiB2 and TiAl, they have relatively poor
deformability and can be easily cracked during forging. They are usually made
through powder metallurgy method. Metal powders and some additional materials
are well mixed. By hot pressing or hot isostatic pressing to achieve the bulk

Table 79.8 Bonding Bonding method Bonding ratio One-body defect

quality control for Titanium
Solder bonding 95% 2%
targets [8]
Diffusion bonding 98% 1%
1768 D. Yang et al.

Fig. 79.13 Typical Ti targets

workblank, which will be further processed to get the titanium alloy target. By using
powder metallurgy method, the workblank of target can be made with one-body step
only and lead to good yield and convenience in alloy element adding. Therefore,
powder metallurgy is the most preferred method for making Ti-alloy targets. The
challenge of powder metallurgy method includes the purity of powder, homoge-
neousness of alloy elements, density, and the internal defect rate. Typical Ti targets
are shown in Fig. 79.13.

Tantalum Targets

Because of the good electrical conductivity and thermal stability, Tantalum (Ta) is
used as the barrier layer for Cu interconnects in IC chips to prevent the diffusion of
copper atoms into the silicon substrate. In the sputtering process, Ta targets are
always used together with Ta rings to improve the step coverage quality of deposited
films and the utilization efficiency of tantalum targets.

The Specific Requirement of Ta Target [9, 10]

The purity of Ta targets has three levels: 99.95% (3N5), 99.99% (4N), and 99.995%
(4N5); and the individual purity level for different Ta targets have separate
79 Auxiliary Material in Process 1769

Table 79.9 Grain size Impurity level Grain size specification/μm

specification for Tantalum
99.95%(3N5) 150
target
99.99%(4N) 100
99.995%(4N5) 100

Table 79.10 Bonding Bonding type Bonding ratio Maximum single defect
quality
Solder bonding 95% 2.5%
Diffusion bonding 98% 1%

specification for fab customers. Ta targets must be made through fine machining with
good surface quality. During the thermo-mechanic processing of Ta targets, it is quite
often to generate multi-layer microstructures. Besides, voids are also quite common
defects in Ta ingots. A qualified Ta target should have no multi-layer microstructures
or voids. In addition, the grain size should match the requirements as shown in
Table 79.9, and the hardness usually ranges from 60 HV to 110 HV. Ta targets could
be bonded with the backing plates by using welding or diffusion welding methods.
The welding quality must follow the standard as shown in Table 79.10. The diameter
of Ta targets for IC manufacturing ranges from 200 mm to 460 mm with the
thickness of 6–10 mm.

Fabrication of Ta Targets

Some typical Ta targets and Ta rings are shown in Fig. 79.14. Ta targets are usually
made through thermo-mechanic processing method with casted ingots or powder
metallurgy method with Ta powders. (a) High-purity Ta ingot is used as raw material
for thermo-mechanic processing. Microstructures and bulk dimensions of
workblanks are developed through rolling and annealing processes. Further machin-
ing is applied on the bulk workblanks to form the Ta targets. Vacuum electronic
beam melting is usually used for the Ta melting process. With proper equipment and
well-designed process, the purity of Ta ingots could reach as high as 99.995%.
Variable direction rolling followed with annealing is usually conducted for Ta targets
in order to achieve fine and homogeneous grain size and microstructure, which is
critically required for Ta target sputtering process. (b) As for powder metallurgy
method, Ta powder is certainly used as the raw material. Formation is achieved
through hot pressing or hot isostatic pressing process; followed with machining, bulk
Ta is fabricated into Ta targets. By using powder metallurgy method, multi-layer
microstructures can be effectively avoided, which indicates more homogeneous
microstructure compared to those developed through thermo-mechanic processing
method. However, because of the relatively high-oxygen and -impurity level in Ta
powder, Ta targets made through powder metallurgy usually has higher impurity
level than those made through thermo-mechanic processing. Moreover, densification
1770 D. Yang et al.

Fig. 79.14 Typical Ta targets and Ta rings

is also an important and challenging task for powder metallurgy process of Ta

targets.

Copper Targets

Copper (Cu) targets have two major groups: pure Cu targets and Cu-alloy targets.
For pure Cu targets, there are four purity levels: 99.99% (4N), 99.995% (4N5),
99.999% (5N), and 99.9999% (6N), in which 4N and 6N are mostly used. Cu-Al and
Cu-Mn alloys are usually used for the semiconductor targets. With adding small
amount of Al and/or Mn into pure Cu, the electron migration (EM) and stress
migration (SM) of Cu atoms can be reduced and the corrosion resistance would be
improved.
According to the shape, there are flat and rotary Cu targets. The flat Cu targets
have different shapes of circular, rectangular, square, etc. While the rotary Cu targets
are tubular shapes. Typical Cu targets are shown in Fig. 79.15. Cu target workblank
is usually prepared through molten casting process or powder metallurgy. High-
purity Cu ingots developed through vacuum medium frequency induction furnace
are further processed through rolling and annealing to achieve proper sizes and
microstructures. Afterward, fine machining is applied to get the Cu targets. Similar
as Ta targets, the fabrication of Cu targets also includes variable direction rolling and
annealing to ensure fine and homogeneous grain sizes and microstructures as
required in the sputtering process. The powder metallurgy process uses Cu powder
79 Auxiliary Material in Process 1771

Fig. 79.15 Typical Cu targets

as the raw material. CIP (cold isostatic pressing), HP (hot pressing), or HIP (hot
isostatic pressing) might be used to get the Cu target workblanks followed with
machining. According to the structure, Cu targets have two types: one-body type and
welded type. The one-body type Cu targets are fabricated from the blank material
directly, while welded Cu targets need to bond the target workblanks with the
backing plates using welding technologies (e.g., mechanical occlusion, solder
welding, and diffusion welding). The backing plate material includes Cu and
Cu-alloy, as well as Al and Al-alloy. Ultrasonic inspection is used to confirm the
quality of welding to prevent any de-bonding or cracking issues happened during the
sputtering process.
With the development of IC industry, the requirements on Cu targets is getting
more critical, which includes: How to achieve the ultra-high purity Cu material, how
to design the preferred microstructures of Cu targets for longer lifetime, how to
reduce the influence of twin crystal by adjusting the plastic deformation and the
thermal mechanical process methods, and how to improve the finish machining
process on the large Cu target surface. These issues are all the directions for future
improvement of Cu targets.

Precious Metal Targets

In the IC industry, precious metals, such as Gold (Au), Silver (Ag), Platinum (Pt),
Ruthenium (Ru), and their alloys, etc., are used as the silicide of contact layer
between conductor lines and the Si substrate, also as the backside metallization of
the Si wafers. In recent years, with the development of the VLSI wafer manufactur-
ing and advanced chip packaging technology, precious metal has been more widely
used ever in the semiconductor industry.
1772 D. Yang et al.

Application of the Precious Metal Target

The applications of the precious metal targets in the semiconductor industry have
been shown in Table 79.11.

Fabrication of the Precious Metal Targets

(a) Target fabrication: For those precious metals with low melting temperature
(e.g., Au, Ag, Pt, and alloys), vacuum melting could be used to form workblank
ingots with certain sizes. The thermal mechanical process method (e.g., rolling)
would be used to further process workblank ingots into targets. For those with high
melting temperature (e.g., Ru and its alloy), the powder metallurgy method is
applied to form the target workblank by using hot pressing or hot isostatic pressing.
(b) Microstructure control: For Au, Ag, Pt, and their alloy, the grain size and grain
orientation are controlled by certain thermal mechanical process and followed heat
treatment process, while for Ru and its alloy, the grain size is controlled by the
powder grains and the sintering process.

Recycle of the Precious Metal Targets

The utilization efficiency of the target is quite low in IC industrial. In general, there
are 70% of the target materials remaining on the used target. The used target and the
accessed material during the target fabrication should be recycled and reused. The
used precious metal target and the scraps can be recycled by physical and chemical
refining methods. (a) For the physical method, machining process is applied to
pretreat the surface of the used target, followed by the acid cleaning to remove the
residue contamination to get the pure precious metals. For used Ru targets, mechan-
ical crushing is applied firstly, followed by acid cleaning to remove the impurity,
especially the Iron (Fe) and Chromium (Cr) that are introduced during mechanical
crushing. After being dried, the hydrogen reduction deoxygenation process is used
and the magnet is used to further remove residual iron. At the end, sifting method is

Table 79.11 Applications of precious metal sputtering targets in semiconductor [11]

Target
material Properties requirement Application
Ag Purity  4N, Grain size  50 μm Wafer back metallization,
conductor line
Au Purity  4N, Grain size  50 μm Wafer back metallization,
conductor line
Pt and Purity  4N, Grain size  50 μm Wafer back metallization,
alloy conductor line
Ru and Impurity  4N5, Grain size  50 μm, Wafer back metallization,
alloy Density > 99% conductor line
79 Auxiliary Material in Process 1773

used to have the recycled Ru powder. (b) The chemical method is normally used to
recycle and purify those used precious metal alloy targets and scraps. Firstly, the
used precious metal alloy targets and the scraps are dissolved into the solution by
chemical reaction. Precious metals can be separated out from the solution using the
chemical deposition method. After that, the secondary purification is carried out by
extraction, adsorption, distillation, and other methods. At the end, through the
thermal decomposition or hydrogen reduction, high-purity precious metal is
collected [11].

References
1. Y. Wei, Advanced Photolithography Theory and Application for ULSI Circuits[M] (Science
Press, Beijing, 2016)
2. L. Bremer, R. Tuinier, S. Jahromi, High refractive index nanocomposite fluids for immersion
lithography [J]. Langmuir 25(4), 2390–2401 (2009)
3. Semiconductor Products Catalog Version 4.3, Matheson Trigas
4. Air Product and Chemicals Inc., Catalog, 2015 325–13-188-GLB-Dec15
5. W. Karl Olander, Lupng Wang, Low Pressure Sources: Benefits and Drivers for adoption, Gases
and Technology, Nov/Dec, 2002
6. R. Chatterjee, R. Reif, The evaluation of hexafluoro-1,3-butadiene as an environmentally
benign dielectric etch chemistry in a medium-density etch chamber, in Electrochemical Society
Proceedings, (2002), pp. 99–113
7. S. Siegele, D. Hage, F. Siegele, On-site generation of high purity fluorine as a safe and
economical alternative for CVD chamber cleaning. FutureFab Int 13, 107–116 (2002)
8. Ministry of Industry and Information Technology of the People’s Republic of China, High
purity sputtering Titanium targets for semiconductor application, YS/T 893-2013[S] Beijing
(2013)
9. Ministry of Industry and Information Technology of the People’s Republic of China, Tantalum
Sputtering Target: YS/T 1024-2015[S] (Standards Press of China, Beijing, 2015), p. 10
10. J.F. Zheng, B.Z. Hu, G.Q. Yang, et al., Status of High purity Tantalum sputtering target
manufacturing [J]. Hunan Nonferrous Metals 32(4), 54–56 (2016)
11. J. He, M. Chen, X. Zhu, et al., Application and fabrication method of high purity precious metal
sputtering targets used in semiconductor [J]. Precious Metal 34(S1), 79–83 (2013)
Package Structure Materials
80
Deren Yang, Tong Yuan, and Xuegong Yu

Contents
Lead Frame Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776
Cu-Based Lead Frame Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776
Iron-Based Lead Frame Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
Plastic Packaging Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
Ceramic Packaging Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
High-Temperature Co-Fired Ceramic (HTCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
Low-Temperature Co-Fired Ceramic (LTCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
Metal Packaging Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
Traditional Metal Packaging Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
New Metal Packaging Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
Ceramic Substrate Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784
Organic Packaging Substrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787
Precious Metals and Their Bonding Wires as Internal Lead Materials . . . . . . . . . . . . . . . . . . . . . . . 1787
Gold (Au) and Au Alloy Bonding Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787
Silver (Ag) Bonding Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
Gold-Silver (Au-Ag) Bonding Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Silver (Ag) Alloy Bonding Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Cu, Cu-Alloy, Al, Al Alloy Bonding Wires as Inner Lead Materials . . . . . . . . . . . . . . . . . . . . . . . . . 1791
Cu Bonding Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791
Palladium (Pd)-Plated Cu Bonding Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1791
Cu-Alloy Bonding Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792
Aluminum (Al) and Al Alloy Bonding Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1793
Electrically Conductive Adhesives (ECA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1793
Die Attach Adhesives (DAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795

D. Yang (*) · X. Yu
State Key Lab of Silicon Materials, Zhejiang University, Hangzhou, China
e-mail: mseyang@zju.edu.cn
T. Yuan
China Electronics Materials Industry Association, Beijing, China

© Publishing House of Electronics Industry 2024 1775

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_80
1776 D. Yang et al.

Solder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
Under-Fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1797
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799

Abstract
This chapter reviews the package structure materials. First of all, the lead frames
are introduced as carriers for IC chips. Then, the electronic packaging materials
are illustrated, including metal, ceramic, and plastic packaging materials. It is
worth noting that the organic packaging substrates have two types, i.e., rigid
substrates and flexible substrates. Next, the metal bonding wires are illustrated,
including copper, alloy of copper, aluminum, alloy of aluminum bonding wires,
and inner leads materials. Finally, the electrically conductive adhesives, die attach
adhesives, solder, and under-fill materials are addressed.

Keywords
Lead frames · Metal packaging materials · Ceramic packaging materials · Plastic
packaging materials · Organic packaging substrates · Metal bonding wires ·
Electrically conductive adhesives · Solder · Under-fill

Lead Frame Materials

Lead frames are used in semiconductor packaging as carriers for IC chips. Lead
frame materials should meet the following characteristics: (a) good thermal conduc-
tivity; (b) high strength, stiffness, and formability; (c) low thermal expansion
coefficient, good matching, brazing property, corrosion resistance, heat resistance,
and oxidation resistance; (d) good smoothness, small residual stress, and no defor-
mation after processing; and (e) easy to be stamped and processed. There are two
kinds of lead frames materials: copper (Cu)-based and iron (Fe)-based lead frame
materials.

Cu-Based Lead Frame Materials

According to the alloy elements, the Cu-based lead frame materials can be divided
into five series, such as Cu-Fe, Cu-Cr, Cu-Ni-Si, Cu-Sn, and Cu-Zr. They also can be
divided into high conductive, high strengthening and medium conductive, and high
strengthening and high conductive Cu alloys according to the properties of the alloy.
(a) High conductive Cu alloy: The Cu content in the composition of high conduc-
tive Cu alloy is more than 99%, and the strength is medium or low. The most
commonly used Cu alloys are KFC-1/2H, C1220, C19210, etc. Table 80.1 is the
performance table of high-conductivity Cu alloy materials commonly used. High
conductive Cu alloy is generally used in situations which required high conductivity
and heat dissipation (e.g., power device lead frames and connecting strips, TO-92
80 Package Structure Materials 1777

Table 80.1 Performance of common high conductive Cu alloy materials

Coefficient of
Tensile thermal
Material strength Hardness expansion Conductivity Softening
type (MPa) Extensibility (%) (HV) (106/K) (%IACS) temperature ( C)
KFC-1/ 355 ~ 430
5 100 ~ 130 17.5
85 450
2H
C1220 275 ~ 346
5
80 16.6
80 320
C19210 294 ~ 412
5 100 ~ 130 17.7
90 420

Table 80.2 Performance of high strengthening and medium conductive Cu alloy materials
Coefficient
Tensile of thermal Softening
Material strength Hardness expansion Conductivity temperature
type (MPa) Extensibility (%) (HV) (106/K) (%IACS) ( C)
c194-H 410 ~ 480
5 130 ~ 145 17.6
60 480
CAC92 410 ~ 570
4 140 ~ 180 16.6
10 520

Table 80.3 Performance of common high strengthening and high conductive Cu alloy materials
Coefficient
Tensile of thermal Softening
Material strength Extensibility Hardness expansion Conductivity temperature
type (MPa) (%) (HV) (106/K) (%IACS) ( C)
C7025 600 ~ 725
5 180 ~ 220 17.6
35 /
KLF-125
500
8 187 ~ 210 17.0
30 525
c194-ESH 500 ~ 570
5 150 ~ 170 17.4
60 /
EFTEC64T 490 ~ 530 10 160 ~ 195 17.0
70 /

discrete device lead frames, etc.), the Cu strips used are thicker (
0.2 mm). The lead
frames are usually produced by stamping process. (b) High strengthening and
medium conductive Cu alloy: The most commonly used high strengthening and
medium conductive Cu alloy is C194 alloy, i.e., high tensile strength more than
400 MPa, hardness more than 120 HV, and medium conductivity (more than 10%
ICAS). Table 80.2 is a performance table of high strengthening and medium
conductive Cu alloy materials commonly used. Most IC lead frames and thin discrete
device lead frames use this material. The lead frame can be produced by stamping or
etch process, the thickness of Cu strip material is 0.1 ~ 0.3 mm. (c) High strength-
ening and high conductive Cu alloy: The representative Cu alloys for high
strengthening and high conductive IC lead frames are C7025, KLF-125, A194-
ESH, EFTEC-64T, etc. as shown in Table 80.3. High strengthening and high
conductive Cu alloys are generally used in thin profiles (material thickness less
than 0.2 mm), e.g., multirow TSSOP, MSOP, TQFP stamping frames, and QFN
etched frames.
1778 D. Yang et al.

Table 80.4 Performance table of 42Ni-Fe alloy materials commonly used

Coefficient of
Tensile thermal Softening
Material strength Extensibility Hardness expansion Conductivity temperature
type (MPa) (%) (HV) (106/K) (%IACS) ( C)
42Ni-Fe 680 ~ 720
8 200 ~ 215 4.2
3 /

Iron-Based Lead Frame Material

Fe-based lead frame materials are mainly 42Ni-Fe alloy and iron lead frame
materials. (a) 42Ni-Fe alloy: 42Ni-Fe alloy contains 42% Ni and the rest is Fe,
and it is characterized by high strength (about two times as much as regular
common Cu) and good toughness as shown in Table 80.4. At the same time, its
thermal expansion coefficient (TEC) is small (close to IC chips) as beneficial to
the subsequent packaging. However, its thermal and electrical conductivity is low
and not suitable for products with power consumption requirements. Currently,
the material is mainly used in ceramic packaging with high reliability require-
ments and thin precision plastic sealing lead frame with thickness of 0.1–0.2 mm.
(b) Fe lead frame material: The price of iron (Fe) as lead frame material is much
lower than that of Cu alloy and 42Ni-Fe alloy, but the disadvantages are that the
electrical and thermal conductivity are poor and it is not corrosion resistant, so it
can only be used in low power products and need special surface treatment
technology (i.e., electroplating). The material used in the production of Fe lead
frame is mainly SPCC, SPCD, and SPCE cold rolled steel strip with hardness of
115 HV–150 HV and thickness 0.2–0.4 mm.

Plastic Packaging Materials

Electronic packaging materials are usually divided into metal, ceramic, and plastic
packaging materials. The plastic packaging materials own >90% market shares due
to its low cost, light weighting, minimized size, large scale production, etc. Plastic
packaging materials include the epoxy molding compounds (EMC) and flip-chip
under-fills. EMC is used to protect IC chips from external environments, specifically
from external physical impacts (e.g., pressure, heat, UV ray, etc.) as well as external
chemical attacks (e.g., moisture alcohols, etc.), and maintain the electrical insulation
properties and the form of easier mounting IC packages on PCB.
EMC is a solid material at room temperature, which is composed of many raw
material ingredients to meet the requirements on reliability, physical properties, and
mold ability. The typical ingredients include epoxy resins, phenolic resins, fused
silica as filler, silane coupling agents, curing promoter, flame retardant, and release
agent. The ingredients are mixed and kneaded at elevated temperature into a
homogeneous mixture in a kneader or roll mixer, then cooled into a sheet shape
80 Package Structure Materials 1779

which was then pulverized. The powdery materials are then palletized into pellets for
the suitable injection molding. EMC usually is used to encapsulate IC chips in the
injection-molded package within the lead frame. The injection molding process
includes four steps: (1) IC chips mounted on substrate, lead frame, or interposer
are placed in the cavities of a heated mold; (2) the mold is tightly sealed, EMC is
molten by microwave heating and fed into each cavity through the mold pot under
the plunger pressure; (3) the molten EMC compressed in the cavity is completely
cured at elevated temperature to form the thermosetting material; and (4) the mold is
opened and the molded IC packages are released. The injection molding temperature
is usually set at 170–180  C with a curing time of 60–120 s.
With the progress of IC packaging technology in high density, smaller size, and
lighter weight, EMC has been developed into different products (e.g., rapid curable
type, high thermal stable type, low-stress type, etc.). As the increasing attention to
environmental issues (e.g., environmental protection, recycle, and reuse), an envi-
ronmentally friendly EMC has been developed that can withstand lead-free soldering
and not contain halogen or antimony (Sb) flame retardants.
Under-fill is usually used to redistribute the thermos-mechanical stress as
created by the CTE (coefficient of thermal expansion) mismatch between the
IC chips and organic substrate for enhancing the packaging reliability. The
conventional under-fill relies on the capillary flow of the under-fill materials as
applied after the flip-chip interconnects formed. The resin flows into the gap
between the chip and the substrate by a capillary force. A typical capillary under-
fill is composed of liquid epoxy resin mixture and micron-sized silica fillers.
Although the capillary under-fill is still the main packaging technology for flip-
chip devices, it will face big challenges for larger chip size and smaller gap
between the chips and substrate. Hence, other under-fills (e.g., no-flow, molded,
and wafer-level under-fills) have been developed.

Ceramic Packaging Materials

Ceramic packaging materials have the advantages of good moisture resistance, good
linear expansion coefficient, and thermal conductivity, as well as excellent compre-
hensive performance. They can form airtight packages like metal, but their price is
lower than metal. At present, ceramic package materials that have been actually
produced and developed are mainly high-temperature co-fired ceramic materials
(HTCC) and low-temperature co-fired ceramic materials (LTCC). HTCC and
LTCC have become the most important materials in the field of modern ceramic
packaging. Currently, HTCC is relatively mature and occupying dominant position
in ceramic packaging market. However, LTCC is an important development. With
continuous progresses of materials and process, the advantages of LTCC will be
more obvious, but it cannot completely replace HTCC yet. Various ceramic pack-
aging materials are shown in Fig. 80.1. Properties of ceramic packaging materials are
shown in Table 80.5.
1780 D. Yang et al.

Fig. 80.1 HTCC ceramic packages [1] and manufacturing process of ceramic packaging materials [2]

High-Temperature Co-Fired Ceramic (HTCC)

HTCC refers to the co-fired ceramics which sintered at temperature greater than
1000  C. By using alumina (Al2O3) and aluminum nitride (AlN), the sintering temper-
ature is generally higher than 1500  C. Due to its high sintering temperature, HTCC
cannot use low melting point metal materials (e.g., Au, Ag, Cu, etc.). Instead, HTCC
needs to use high melting point metal materials (e.g., W, Mo, and Mg). However, these
high melting point materials have lower electrical conductivity leading to the significant
signal delay, so not suitable for high-speed or high-frequency circuits. HTCC has many
advantages (e.g., high structural strength, good thermal conductivity, good chemical
stability, and high wiring density) and has wide applications in high-power circuits. The
80 Package Structure Materials 1781

Table 80.5 Properties of ceramic packaging materials [3, 4]

Properties LTCC HTCC
Material Cordierite; Alumina AlN
MgO,SiO2,Al2O3;
Glass composite;
SiO2,B2O3,Al2O3
PbO2,SiO2,CaO,Al2O3
Crystal ceramic
Al2O3,CaO,SiO2,
MgO,B2O3
Sintering temperature 850–900  C 1500–1600  C 1600–1800  C
Conductor Au, Ag, Cu, Pd-Ag W, Mo-Mn W, Mo-Mn
Conductor sheet resistance 3–20 mΩ/□ 8–12 mΩ/□ 8–12 mΩ/□
Dielectric dissipation factor 15–30  104 5–15  104 20–30  104
Dielectric constant (1 MHz) 5–8 9–10 8–9
Resistor 0.1 Ω-1 MΩ – –
Shrinkage
X,Y 12  0.1% or 0 12–18% 15–20% or 0
Z 17  0.1% 12–18% 15–20%
Repeatability 0.3–1% 0.3–1% 0.3–1%
Line width 100 μm 100 μm 100 μm
Diameter of via 125 μm 125 μm 125 μm
Layer 33 63 8
CTE 3–8 ppm/ C 6.5 ppm/ C 4.4 ppm/ C
Thermal conductivity 2–6 W/m.K 15–20 W/m.K 180–200 W/m.K

commonly used HTCC packages mainly include Al2O3 multilayer ceramics and AlN
multilayer ceramics.
Alumina HTCC is a mature electronic packaging material. It is made of 92–96%
alumina (Al2O3) and 4–8% sintering additives, sintered at 1500–1700  C. It has
mature technology, low cost, lower thermal conductivity (than AlN), and good
flexural strength. However, alumina HTCC has the following disadvantages: (1)
high dielectric constant with slower signal transmission speed; (2) high electrical
resistivity with higher signal transmission loss; (3) the low thermal conductivity
makes it difficult to meet the needs of high-power electrons; and (4) the TEC is quite
different from that of Si and limits its use in large IC chips. Aluminum nitride (AlN)
HTCC is a newly developed high thermal conductivity (ten times that of alumina
HTCC) electronic packaging material, also with matched thermal expansion coeffi-
cient with Si, high mechanical strength, and excellent electrical performance. It is the
preferred material for power electronic packaging. However, AlN HTCC also has the
following shortcomings: (1) high resistivity of wiring conductors with high signal
transmission loss; (2) high co-firing temperature with high energy consumption; (3)
higher dielectric constant than LTCC; and (4) screen printed resistors and other
passive components not available due to the high-temperature co-firing process.
Though AlN HTCC has shortcomings, it still has more advantages than alumina
HTCC and has a good prospect in the field of ceramic packaging.
1782 D. Yang et al.

Low-Temperature Co-Fired Ceramic (LTCC)

It refers to co-fired ceramics and glass ceramics with sintering temperature below
1000  C. It can use Au, Ag, Cu, and other metals with low melting point and high
conductivity as conductor materials. It can be sintered in air at lower cost and good
properties, e.g., the low dielectric constant leading to low loss at high frequency as
suitable for RF, microwave, and millimeter wave packages and module. After the
invention by Hughes Company in 1980s and years’ development, LTCC has formed
a complete material system, including crystallized glass and glass ceramics, but main
shortcomings of LTCC materials are low thermal conductivity and low mechanical
strength.

Metal Packaging Materials

Metal packaging materials have the advantages of high mechanical strength, good
heat dissipation, and electromagnetic shielding. They are widely used for power
devices and mainly include traditional and new metal packaging materials.

Traditional Metal Packaging Materials

They mainly include Cu, Al, Kovar alloy, Invar alloy, W, Mo alloy, and so on. Most
metal packages need to be compact, moisture resistant, good adhesion and thermal
matching with chip material, and no harmful gas producing at high temperature and
low pressure. (1) Cu and Al: Cu has a conductivity of 1.72 μΩcm and a thermal
conductivity of 401 W/mK. It is the most ideal packaging materials from the point
of heat transfer and electrical conductivity. However, its thermal expansion coeffi-
cient (TEC, or CTE) is very high and leads to large stress in the ceramic substrate. Al
and its alloys are easy to process, and have high thermal conductivity. They are
commonly used as package materials for ICs. However, their TEC are very high
(quite different from those of Si and GaAs) and lead to stress buildup and devices
failures during thermal cycles of devices operation, as shown in Table 80.6. (2) W
and Mo: The TEC of Mo is 5.35  106/ C and matches well with Kovar and Al
materials. Its thermal conductivity is quite high at 138 W/mK. It is often used as a
base for airtight packages used in medium and high power density metal packages.
W has the similar TEC as Si and GaAs, and its thermal conductivity is good, so it can
be used as a support material for chips. However, W and Mo are expensive and not
suitable for mass production. In addition, they are not suitable for aerospace appli-
cations because of their high density. (3) Steel: The thermal conductivity of No.10
steel is 48.8 W/mK, about three times of Kovar alloy. Its TEC of 12.6  106/ C
does not match with ceramics and IC materials, but it can be used for soft glass
compressed packaging in corrosion-resistant sealed packages. (4) Kovar: The TEC
of Kovar alloy (Fe-29Ni-17Co) is similar to that of Si, GaAs, alumina, beryllium
80 Package Structure Materials 1783

Table 80.6 Properties of common chips, substrates, and metal packaging materials [5]
Density CTE Thermal conductivity
Material (g/cm3) (106/K) (W/m.K)
Si 2.3 4.1 150
GaAs 5.3 6.5 44
Al2O3 3.6 6.9 25
BeO 2.9 7.2 260
AlN 3.3 4.5 180
Cu 8.9 17.6 400
Al 2.7 23.6 230
Steel 7.9 12.6 65.2
Stainless steel 7.9 17.3 32.9
Kovar 8.2 5.8 17.0
Material Density CTE Thermal conductivity
(g/cm3) (106/K) (W/m.K)
W 19.3 4.45 168
Mo 10.2 5.3 138

oxide (BeO), and AlN. It has good weldability and process ability, can match and
seal with borosilicate glass, and widely used in low power density metal packaging.
Its disadvantages are low thermal conductivity, high resistivity, and high density. (5)
W-Cu and Mo-Cu: In order to reduce the TEC of Cu, Cu and materials (e.g., Mo
and W) with smaller CTE can be formed as W-Cu and Mo-Cu composites. These
materials have high electronic and high thermal conductivity, and also can integrate
the characteristics of low TEC and high hardness of W and Mo. The TEC of W-Cu
and Mo-Cu can be adjusted according to the relative content of compositions to
serve as the base and heat sink of packages. However, the disadvantage of W-Cu and
Mo-Cu is their high density.

New Metal Packaging Materials

As single metal packaging material does not have all aspects of desired require-
ments, instead, metal matrix composite (MMC) may meet most of the requirements.
MMC are new packaging materials and have both the characteristics of matrix and
composite materials. According to the requirements of materials, the components of
the composites and their reinforcement modes can also be flexibly selected. MMC
materials are mainly micro-reinforced and especially suitable as substrates and
packages for power ICs, microwave ICs, millimeter (mm) wave ICs (MMIC),
MCM, and high-current power modules. According to the types of reinforcements,
there are continuous, discontinuous, in situ, and laminated MMCs. According to the
types of matrixes, there are Al matrix, Cu matrix, Ag matrix, Be matrix, etc. Among
them, AlSi and Al/SiC materials are the most prominent as shown in Table 80.7. (1)
AlSi packaging materials: The properties of Al/Si alloy are very well, 15% lighter
1784 D. Yang et al.

Table 80.7 Properties of AlSi and Al/SiC metal packaging materials [5]
Density Thermal conductivity
Materials Content (g/cm3) CTE(106/K) (W/mK)
Al/SiC Al þ (50–70%)SiC 2.8–3.0 6.5–9.0 220–230
Cu/W W þ (10–20%)Cu 15.6–17.0 6.5–8.3 180–200
Cu/Mo Mo þ (15–-20%)Cu 10.0 7.0–8.0 160–170
Al/Si 60%Al þ 40%Si 2.5 15.4 126

weight than pure Al, one-third of Kovar, and one-sixth of Cu/W. It is a promising
packaging material and widely used in the packaging for microwave and millimeter
wave IC modules. The thermal conductivity of the compact Al/70Si alloy is 120 W/
mK, and the TEC at 20  C is 6.8  106/ C. It is suitable for EMI/RFI shielding. In
addition, Al/Si alloy prepared by spray forming has the characteristics of homoge-
neity, isotropy, good machining, as well as easy plating and welding properties.
Recently, Al/Si alloys are mainly used as microwave/RF packages, photoelectric
packages, power device substrates, high-frequency circuit carriers, radiators, and
heat sinks. (2) Al/SiC packaging materials: Al/SiC is an Al matrix composite
widely used in metal packaging. It consists of 30–70% SiC particles and 70–30%
Al or Al alloy. Its TEC can be adjusted by varying the percentage of components.
Al/SiC composites with slight increasing of SiC content, TEC of Al/SiC can
decrease gradually from 23.2  106/ C of Al. The thermal conductivity of
Al/SiC material (@70% SiC) can be higher than 170 W/m.K with TEC about 7 
106/ C, which can achieve good thermal matching, minimize the stress at the
junction of chip or substrate, and provide ten times higher thermal conductivity
than that of Kovar alloy, thus no heat sink is needed. Since the density of Al and SiC
is small, the density of Al/SiC material is also very small, e.g., the density of Al/SiC
material with 70% SiC is only 2.79 g/cm3. These properties make it an ideal material
as sealed packages, especially for space applications.

Ceramic Substrate Materials

Ceramic substrates, also known as ceramic plates, are based on electronic ceramics,
forming a sheet-like material to support the film circuit elements and external
mounting elements, as shown in Fig. 80.2. Ceramic substrates are common substrate
material for electronic packaging (Table 80.8). Compared with plastic and metal
substrates, there are some advantages: (1) Good insulation and high reliability.
High resistivity is the basic requirement of electronic components to substrates. In
general, the higher the resistance of substrates, the higher the packaging reliability.
Ceramic materials are generally covalent compounds, and their insulation perfor-
mance is excellent. (2) Small dielectric coefficient. Ceramic materials have low
dielectric constants and low dielectric loss for reducing signal delay and improving
signal transmission speed. (3) Low thermal expansion coefficient (TEC or CTE).
Covalent compounds generally have high melting point with smaller TCE and low
80 Package Structure Materials 1785

Fig. 80.2 Ceramic

substrates [6]

Table 80.8 Properties of some ceramic substrate materials [7]

Thermal Coefficient of Flexural Dielectric
Ceramic conductivity Resistivity thermal expansion strength constant
materials (W/mK) (Ωcm) (ppm/ C) (MPa) (1 MHz)
Alumina 22–40 >1014 6.5–7.2 300–385 8.5–10
(Al2O3)
Aluminum 140–220 1012–1014 4.8 200–300 4–10
nitride (AlN)
Beryllia 280–290 4.5  1015 6.27–10.3 140–200 6.7
(BeO)
Si-Carbide 70–270 >1014 2.8–4.6 450 –
(SiC)

thermal mismatch. (4) High thermal conductivity. According to heat transfer

theory, the theoretical thermal conductivity of BeO, SiC, and AlN ceramics in
cubic system is as good as that of metals. Therefore, ceramic substrate materials
are widely used in the fields of aviation, aerospace, and military applications with the
need of high reliability, high frequency, high temperature, and high hermetically.

1. Basic requirements of ceramic substrates: (a) Electrical: low dielectric con-

stant, low dielectric loss, high insulation resistance, high breakdown voltage, high
temperature stability, and humidity stability. (b) Thermal: high thermal conduc-
tivity, good heat dissipation, thermal expansion coefficient matching with the
components to be assembled, and excellent heat resistance. (c) Mechanical: high
mechanical strength, good processing performance, suitable for fine and multi-
layer fabrication process, smooth surface, small deformation, no warpage, no
micro-cracks, etc. (d) Others: good chemical stability, easy metallization, non-
hygroscopicity, nontoxicity, and low cost.
2. Manufacturing methods of ceramic substrates: It is very difficult to manufac-
ture high-purity ceramic substrates. Most of the ceramics have high melting point
and high hardness which limits the possibility of mechanical processing of
ceramics. Therefore, glass with low melting point is often doped in ceramic
substrates for fusing or bonding, making the final products easy to be machined.
1786 D. Yang et al.

The manufacturing processes of Al2O3, BeO, AlN, and other ceramic substrates
are very similar. They are all ground into powder with a diameter of several
microns (μm), mixed with different solvents, dispersants, sintering aids, and
organic binders, and then ball milled to prevent agglomeration and make the
composition uniform, after which thin ceramic green sheets are formed, and
finally sintered at high temperature. At present, there are several ceramic forming
methods such as powder compaction, extrusion, tape casting, and injection
molding. In recent years, tape casting has been widely used in LSI hybrid IC
substrates production due to its easy formation of multilayers and high production
efficiency.
3. Metallization method of ceramic substrates: The surface and interior of the
ceramic substrates can be metallized to form circuits which can be used to carry
components and connect the input and output terminals of the circuits. Common
metallization methods include thick film, thin film, co-firing, and DBC.
4. Typical ceramic substrate materials: There are many kinds of ceramic sub-
strates, but the commonly used ones are Al2O3, BeO, SiC, AlN, mullite, etc. (a)
Al2O3: So far, alumina ceramic substrates are the most widely used substrates in
the electronic industry. It has low cost, excellent comprehensive performance,
good air tightness, high reliability, and rich in raw materials. There are typical
95–99% Al2O3 ceramic substrates with different shapes for HIC (hybrid IC)
substrates, packaging substrates, and multilayer circuit substrates. Tape casting
method is often used in their processing. (b) BeO: beryllium oxide (BeO) is the
highest thermal conductivity ceramic material with very good electrical insula-
tion, dielectric, and mechanical strength, e.g., low dielectric constant suitable for
high-speed circuits, and high thermal conductivity for high-power circuits. Espe-
cially in high-power semiconductor devices and circuits, high-power microwave
vacuum devices, and nuclear reactors, BeO is always the mainstream ceramic
material. However, due to the toxicity of BeO powder as environment hazard,
BeO materials are banned in Japan and Europe and can only be imported from the
USA. BeO is gradually being replaced by AlN. (c) AlN: The main characteristics
of AlN ceramic substrate are high thermal conductivity (more than ten times of
Al2O3), matching TEC with Si, high strength, lightweight, and nontoxic. It has
broad applications in MCM and is a new generation packaging and substrate
material. (d) Mullite (3Al2O3-2SiO2): It is one of the most stable crystalline
phases in Al2O3-SiO2 binary system. It has the advantages of good chemical
stability, thermal stability, high-frequency characteristics, and is light weight.
Compared with Al2O3, although its mechanical strength and thermal conductivity
are slightly lower, but its dielectric constant is also low for good signal transmis-
sion speed. Its TEC is low for reducing the thermal stress of LSI chips. The
differences of CTE between the Mullite material and metal conductor materials of
Mo and W are small, so the stress between Mullite and metal conductors is low
during co-firing. (e) SiC: It is a strong covalent compound. Its hardness is second
only to diamond and cubic boron nitride (BN). In addition, compared with other
materials, its thermal diffusivity is larger and the TEC is closer to Si. However, its
shortcoming is high dielectric constant (e.g., 40 at 1 MHz and 15 at 1 GHz) and
80 Package Structure Materials 1787

low insulation voltage. When the electric field strength reaches several hundreds
of voltages per centimeter, SiC will quickly lose its insulation and become
breakdown. Under low-voltage operation, SiCs are mostly used as packaging
substrates for devices and VLSI required for high heat dissipation.

Organic Packaging Substrates

Organic packaging substrates include two types: rigid substrates and flexible sub-
strates. (1) Rigid substrate come in several configurations, two layers (2 L), four
layers (4 L), and six layers (6 L) of circuits which are interconnected by the plated-
through holes (PTH) technology. Blind holes or vias are also used as interconnects
for high-density substrates. The basic building blocks of 2 L substrate are cores of
Cu clad laminates (CCL), in which the surface of glass fabric is coated with an
electrically insulating organic resin and then sandwiched between two Cu foils to
form the CCL structures. Several plies of impregnated fabric, referred to as prepreg,
may be used to achieve the desired thickness of the core. The fabric itself may be
woven from glass fibers of varying thickness and thread counts to provide more
options to control the CCL thickness. The 4 L substrate which starts with a CCL is
laminated on both sides with prepreg and Cu foils to yield four layers of Cu. A more
complex 4 L substrate can have buried PTHs to increase wire-ability. The process
flow essentially follows the 2 L substrate. The patterned core with PTHs is laminated
and processed like a standard 4 L substrate. A 6 L substrate processing starts with a
patterned 2 L core on to which prepreg and Cu foil are laminated to form the 4 L
core, followed by patterning. After this, lamination with prepreg and Cu foil is
repeated to form 6 L core. (2) Flexible substrates are usually based on polyimide
films. As a rolled polyimide dielectric film, it can be metallized in a continuous form,
either by pressing the polyimide dielectric film with adhesive layers and Cu foils on
both sides, or by sputtering a seed layer on both sides of polyimide dielectric film and
then followed by roll-to-roll Cu plating. Very fine traces and spaces can be produced
on the polyimide dielectric film because the metal film was thin and smooth. Most
flexible substrate are either single-layer metal or two-layer metal with PTHs. 1 þ
2 þ 1 type structures are also available now, but the volume is still low. In addition,
liquid crystal polyester (LCP) film can be used as the dielectric film to produce 2 L
substrates or multilayer flexible substrates for high-frequency applications.

Precious Metals and Their Bonding Wires as Internal Lead

Materials

Gold (Au) and Au Alloy Bonding Wires

Since a ball is formed at the tip of the wire before each bonding, the Au bonding
wires are also called Au ball bonding wires. The purity of Au bonding wire is above
99.99%, while for the Au alloy bonding wires, the purity of Au is about 99.9% or
1788 D. Yang et al.

Fig. 80.3 Au bonding wire and Au alloy bonding wire products

99%, or above 60% (mainly of two types, 60% and 80%). The diameter of Au
bonding wires ranges from 15–50 μm, in extreme, 10 um in diameter can be found.
The length of Au bonding wires can be 500 m, 1000 m, 2000 m, 3000 m, or even longer
on a standard spool. Due to different doping elements and doping amounts, Au alloy
bonding wires can be grouped as three main types: low-loop, median-loop, and high-
loop bonding wires. Under the same elongation, Au alloy bonding wires have higher
breaking load than that of Au bonding wires, thus lower loop can be formed with higher
strength, which makes Au alloy bonding wires more suitable for ultrafine pitch and
multiple-layered packaging of chips. For Au bonding wires, due to its high thermal and
electrical conductivity, homogeneous mechanical properties, and stable chemical prop-
erty, it can be used with various wire bonders and bonding processes. When manufactur-
ing Au bonding wires, ultralow level of other elements can be mixed with high-purity
Au, then through melting, casting, drawing, and thermal refining, certain length of wire
is eventually winded on a standard metal spool. While for Au alloy bonding wires, other
elements are added during melting steps. Au and Au alloy bonding wires are mainly
used in IC and high-power LED packaging applications with high reliability (HiRel).
They are used to the connection between die and lead frame or between die and bracket
by wire bonder. The Au and Au alloy bonding wire products are shown in Fig. 80.3.

Silver (Ag) Bonding Wires

Ag bonding wires are also called Ag wires, developed to replace Au bonding wire
because of the lower cost. The diameter of Ag bonding wires ranges from 18–30 μm,
and the length ranges in 500 m or 1000 m on a standard metal spool. Ag bonding wires
have excellent electrical, mechanical properties, and weldability, but easily to be
oxidized or sulfurized, thus rare gas protection is required during the bonding process.
Ag bonding wires are manufactured through doping, melting, casting, drawing, thermal
refining, and winding processes. Currently, Ag bonding wires have partially replaced Au
80 Package Structure Materials 1789

Fig. 80.4 Silver bonding

wire products

bonding wires in LED packaging industry, especially for dual in-line packages (DIP)
and other low-end products. It is used to connect the die and the bracket with the wire
bonder. Ag bonding wire products can be seen in Fig. 80.4.

Gold-Silver (Au-Ag) Bonding Wires

Au-Ag bonding wires are also called Au-plated Ag wires. Usually, the coating thickness
of Au is between tens of nm to hundreds of nm, the diameter of Au-Ag bonding wire
ranges from 18–30 μm, and the length can be 500 m or 1000 m on a standard metal
spool. The Au-Ag bonding wires have better electrical and mechanical properties than
that of Ag bonding wires. Furthermore, the Au coating can help preventing Ag from
been oxidized or sulfurized, but also improve wire bond-ability with chip pads or
brackets, thus make the bonding more reliable. Rare gas protection is required for
both wire manufacturing and bonding processes. When manufacturing Au-Ag bonding
wires, Ag wires are made with certain specifications first, then plated with Au. Same as
manufacturing other bonding wires, thermal refining and spooling are required. Au-Ag
bonding wires have partially replaced Au bonding wires in LED packaging industry for
the interconnection between chips and brackets. Bonding is done by wire bonder, and
most times for dual in-line package (DIP) and surface-mounted devices (SMD) prod-
ucts. Au-Ag bonding wires are much cheaper than Au bonding wires. Although it is
more reliable than Cu bonding wire, it is still less reliable than Au bonding wires. The
Au-Ag bonding wire products are shown in Fig. 80.5.

Silver (Ag) Alloy Bonding Wires

Ag alloy bonding wires (also called Ag alloy wires) usually have the diameter ranges
in 15–50 μm and the length in 500 m or 1000 m on a standard metal spool. The
composition of Ag alloy bonding wires can be divided into 88%, 92%, 95%, 97%,
1790 D. Yang et al.

Fig. 80.5 Gold-silver

bonding wire products

Fig. 80.6 Silver alloy

bonding wire products

and so on. These Ag alloy bonding wires have excellent electrical and heat conduc-
tivity, chemical stability, and homogeneous mechanical properties. They are softer
than Cu or copper-palladium (Cu-Pd) bonding wires and more suitable for chip
packaging applications with thin pads. They also have better resistance to oxidation
and sulfurization than Ag bonding wires. In manufacturing, other elements can be
added to the high-purity Ag, then through alloying, casting, drawing, and thermal
refining, certain length of Ag alloy wire is eventually winded on a standard metal
spool. Ag alloy bonding wires are mainly used for ICs or high-quality LED pack-
aging. It is used to connect between die and lead frame by wire bonder. Rare gas is
needed during the manufacturing and bonding processes. Ag alloy bonding wires are
more expensive than Ag and Cu-Pd bonding wires, but cheaper than Au bonding
wires. In the IC packaging industry, Ag alloy bonding wires are mainly used in the
package products with a large number of pins (ultrafine pitch) and to replace Cu-Pd
wire bonding to avoid oxidation or crater defects. With the development of Ag alloy
bonding wires, more and more Au bonding wires in different applications can be
replaced. Ag alloy bonding wire is shown in Fig. 80.6.
80 Package Structure Materials 1791

Cu, Cu-Alloy, Al, Al Alloy Bonding Wires as Inner Lead Materials

Cu Bonding Wires

The purity of Cu bonding wire is above 99.99%, and its diameter ranges from
18–50 μm and the lengths are 500 m, 1000 m, 2000 m, or 3000 m on standard
metal spools. Comparing with Au bonding wires, Cu bonding wires are at lower cost
with better mechanical (e.g., hardness and stiffness), thermal, and electrical proper-
ties, and slower formation of intermetallic compound (IMC). With these advantages,
Cu bonding wires have replaced Au bonding wires in some applications with less
reliability requirements. Cu bonding wires can be divided into three groups: regular,
soft, and ultrasoft Cu wires. The ultrasoft Cu wires have less tensile strength and
stiffness than the regular one, and is more suitable for chip packaging with thin
bonding pads. In manufacturing of Cu bonding wires, low-level other elements are
added to ultrahigh pure Cu, through melting, casting, drawing, and thermal refining;
a fixed length of Cu wire is finally wound on a standard metal spool. During all the
manufacturing steps, Cu needs to be protected from being oxidized. Cu bonding
wires are mainly used as packages of discrete semiconductor devices (interconnec-
tion between die and lead frame) and some in LED packages. Wire bonder is used for
Cu wire bonding, and the protection gas (e.g., forming gas and inert gas) is required.
Because Cu is easy to be oxidized and its stiffness is too high, regular Cu bonding
wires are only suitable for chip packaging with thick bonding pad or with less pin
numbers. Products of Cu bonding wires are shown in Fig. 80.7.

Palladium (Pd)-Plated Cu Bonding Wires

Pd-plated Cu bonding wires have Pd coating with the thickness of 10–200 nm. The
diameter of the Pd-plated Cu wires ranges from 18–30 μm and the length is 500 m,
1000 m, 2000 m, and 3000 m, respectively, on standard metal spools. Pd coating is

Fig. 80.7 Cu bonding wire

products
1792 D. Yang et al.

Fig. 80.8 Palladium-plated Cu bonding wire products

not only used to protect Cu from been oxidized, but also improves better bond-
ability and reliability of the connection between Cu wires and chip pads or between
Cu wires and lead frames. Protection gas is needed during the manufacturing or
bonding processes. For manufacturing, Cu wires with certain specifications are
formed first, then Pd is plated on Cu wires, after that, through drawing, thermal
refining, and winding, final product is achieved. Pd-coated Cu bonding wires are
used in some of IC packages and middle or low-end LED packages, it is now
replacing Au bonding wires step by step. By using wire bonder, Pd-plated Cu
bonding wires are used as interconnection between chips and lead frames or between
chips and brackets. Due to more resistance to oxidation, better bonding robustness
than Cu bonding wires, and cheaper than Au bonding wires, the Pd-plated Cu
bonding wires will be more widely used with the development of wire bonder and
the optimization of bonding processes. Pd-coated bonding wire is shown in
Fig. 80.8.

Cu-Alloy Bonding Wires

Cu-alloy bonding wires (also called Cu alloy wires) have the diameter of 15–50 μm
and the length in 500 m or 1000 m on standard metal spools. Cu alloy bonding wires
have excellent electrical and thermal conductivities, homogeneous mechanical prop-
erties, and stable chemical properties. Compared with Cu bonding wires, it has better
resistance to oxidation. While comparing with Pd-plated Cu wires, although it is
cheaper, it has comparable electrical, mechanical, and bonding properties. In
manufacturing, other alloys are added to high-purity Cu raw material first, then
through alloying, casting, drawing, and thermal refining, a fixed length of wire is
lastly winded on a standard metal spool. Cu alloy bonding wires are mainly used in
IC or LED packages with relatively high reliability (HiRel) requirements. It is used
for the connection between the die and lead frames, and wire bonder is used for the
bonding process. Same as Cu bonding wires, protection gas is required during the
manufacturing and bonding processes. Because of its low cost of ownership (COO),
it is currently replacing Pd-plated Cu bonding wires and Ag alloy bonding wires in
80 Package Structure Materials 1793

Fig. 80.9 Aluminum bonding wire and aluminum alloy bonding wire products

IC packaging. With the development of manufacturing processes, Cu alloy bonding

wires can replace Au bonding wires step by step.

Aluminum (Al) and Al Alloy Bonding Wires

Al and Al-alloy bonding wires are usually called Al bonding wires. Because its
composition difference, it can be divided into two groups: pure Al and Si-Al bonding
wires. The purity of pure Al bonding wire is 99.99% or above and its diameter ranges
from 75–500 μm, while the length is 100 m, 200 m, 300 m, 400 m, etc. on standard
plastic spools. For the Si-Al bonding wires, the purity of Al component is 99% or
above, in which the percentage of Si is about 1%. The diameter ranges from
20–50 μm, and length is 1000 ft or 2500 ft (1 ft ¼ 0.348 m) on standard metal
spools. Al bonding wires have excellent electrical and mechanical properties, and
can be used with various ultrasonic wire bonder. In manufacturing, other elements
are added to pure Al first; through melting, casting, drawing, thermal refining, and
testing processes, final product is wound on plastic spools with fixed length. Pure Al
bonding wires are used in packaging of high-power devices, while Si-Al bonding
wires are mainly used for interconnection between dies and lead frames or between
dies and brackets for circuit-on-board (COB) applications. Manufacturers is keeping
on developing new Al alloy bonding wires with high recrystallization temperature,
high strength, as well as high resistance to heat and corrosion to make it suitable for
the high-density packaging of small-dimensional power devices. Al bonding wire
and Al-alloy bonding wire are shown in Fig. 80.9.

Electrically Conductive Adhesives (ECA)

ECAs are composed of polymeric adhesive matrices and electrically conductive

fillers, in which polymeric matrices provide excellent mechanical and adhesive
properties and the fillers provide electrically conductive properties. The polymeric
1794 D. Yang et al.

adhesive matrices are usually thermosetting resins, especially epoxies and silicones,
which forms a three-dimensional (3D) cross-linked structures after the curing under
specific thermal conditions, and the conductive fillers are usually metal particles
(e.g., Au, Ag, Cu, Fe, Al, Zn, Ni, etc.) or graphite, carbon black, etc. Among them,
metal Ag is widely used in the preparation of conductive adhesives because of its
excellent electrical conductivity and antioxidant stability. These particles are usually
spherical with 1–3 μm in size.
According to the curing temperature of the matrix resin, the conductive adhesive
can be divided into two categories: low-temperature curing and high-temperature
curing. The performance stability of the low-temperature curing conductive adhesive
is poor, and the electrical properties of the packaged electronic devices are prone to
deterioration during the storage process at room temperature. In the process of high-
temperature curing, the surface of metal conductive particles will undergo the
oxidation reaction, so the curing time is required to be as short as possible to
avoid that the electrical properties of the conductive adhesives cannot meet the
design requirements. At present, the most widely used conductive adhesives are
cured in an environment below 150  C, so that the temperature resistance of
electronic devices and the adopted temperature are easy to match, and the mechan-
ical properties are excellent.
There are two types of ECAs: an-iso-tropically conductive adhesives (ACAs)
and iso-tropically conductive adhesives (ICAs). (1) ACAs provide unidirectional
electrical conductivity in the vertical or Z-axis direction, which is achieved by
using relatively low-volume conductive fillers (5–20%). The low-volume load is
insufficient for inter-particle contact and prevents the electric conductivity in the
X-Y plane of the adhesive. The Z-axis adhesive, in film or paste form, is interposed
between the two surfaces to be connected. Applying heat and pressure to this stack-
up causes conductive particles to be trapped between opposing conductor surfaces
on the two components. Once electrical continuity is achieved, the dielectric
polymeric matrix is hardened by a chemical thermosetting cross-linking reaction.
The hardened dielectric polymer matrix holds the two components together and
helps maintain the contact pressure between the component surface and the
conductive particles. (2) ICAs are also composed of polymeric adhesive resins
and conductive fillers. The conductive fillers provide the electrical conductivity
through contact between the conductive particles. Epoxy resins are most com-
monly used in thermosetting ICA formulations because of its superior balanced
properties, and Ag powder is the most popular conductive filler. In some commer-
cial ICAs, a solid delay curing agency (as delay hardener) is used to achieve the
desirable delay at room temperature. In order to achieve high electrical conductiv-
ity, the filler volume fraction in an ICA must be equal to or slightly higher than the
critical volume fraction (>25%–30%). High loading level fillers can lead to the
deterioration of the mechanical integrity at adhesive joints. Hence, the challenge in
formulating an ICA is to maximize conductive filler content to achieve high
electrical conductivity without adversely affecting mechanical performance.
ECAs are mainly used in electrical interconnections, e.g., bumped flip-chips for
CSP/BGA, SMT, and high-frequency applications.
80 Package Structure Materials 1795

Die Attach Adhesives (DAA)

DAAs are mainly used as adhesives between IC chips and substrate. DAA plays a
key role in the reliability and performance of IC packaging. DAA usually includes
polymeric adhesive resin and filler. There are two types of DAA: die attach pastes
and die attach films. (1) Die attach pastes: It consists of polymeric adhesive resins
(e.g., epoxy, polyimide, poly-acrylate, or Si resins, etc.) and fillers (e.g., Ag, Al, or
silica, etc.). The filler is uniformly dispersed in the polymeric adhesive resin with
adequate flow properties for workability at room temperature. After thermally cured,
the thermoset resin and the IC chip are fixed on the lead frame. Major die attach
pastes are conducting Ag pastes (i.e., Ag filler and epoxy resin) with the Ag filler of
unique flake-type shape and an average diameter of 2–10 μm. An insulating filler
paste such as silica paste is also used for advanced packaging (e.g., BGA and
stacked-CSP) in order to keep the insulation between IC chips and electrical pattern
on a polymer substrate. (2) Die attach films: It is composed of a thermoplastic resin
and a filler, which have become the key technology to realize excellent reliability,
high performance, high speed, high density of devices, as well as smaller and thinner
packages. The die attach films can be attached at low temperature under low pressure
and short curing time (within several seconds), showing excellent package crack
resistance during the reflow soldering. The die attach process includes a die attach
machine for die attach films, which is completely different from the process of a die
attach paste. In order to improve the package crack resistance, the die attach films are
prepared and derived from a modified polyimide base resin with hydrophobic
structure, thermosetting epoxy resin, and Ag filler with 40% of loading. The water
absorption is only one-sixth as that of a current Ag paste, and peel strength is eight
times larger than that of the current Ag paste. A low-stress die attach film was also
developed and derived from a modified polyimide base resin with hydrophobic
structure, poly-siloxane linkage, thermosetting epoxy resin, and silver filler.

Solder

Solder is the filling metal for soldering. During soldering process, the melting solder
will wet the base material and fill the joint gap. Then there will be an inter-diffusion
between solder and base material and finally the soldering is realized [8]. Solders are
used as the interconnection material for electronic packaging (e.g., lead bonding, die
attach, sealing processes, etc.). The main functions of solder are mechanical con-
nection, electrical connection, thermal dissipation, etc. Solder is mainly used for lead
welding, chip welding, shell sealing, and so on.
To meet the needs of soldering technique and soldering joint properties, solder
should meet the following requirements [9, 10]: (1) melting temperature of solder
below the base materials; (2) good wetting and spreading characteristics with base
materials; (3) joint interface having certain mechanical strength and stable physical
and chemical properties; and (4) moderate cost with little rate metals and noble
metals.
1796 D. Yang et al.

Traditional solder is Pb-Sn solder system, which is widely used due to stable
material system, low melting point (the melting point of 63Sn-37Pb eutectic solder is
183  C), unique solder-ability and process-ability, and low cost. With the strength of
environmental protection consciousness, governments have put forward the require-
ments of green electronic manufacturing and lead-free electronic products, which
have promoted R&D on lead-free solder. To meet the basic requirements of general
solders, lead-free solder should follow these: (a) no new contamination will be
introduced; (b) the melting point is close to 63Sn-37Pb, as well; (c) compatibility
with existing solder process; and (d) good process-ability.
The major newly developed and used lead-free solder are Sn-based solders. The
representative lead-free solder alloys include: binary systems (e.g., Sn-Ag, Sn-Au,
Sn-Cu, Sn-Bi, Sn-Zn, Sn-In, etc.) and ternary systems (e.g., Sn-Ag-Cu, Sn-Ag-Bi,
etc.). Table 80.9 shows main characteristics of lead-free solders which may replace
traditional Pb-Sn solders. At present, Sn-Ag-Cu solders are the most popular lead-
free solder systems. Solder powder is the main component of solder, the composi-
tion, proportion, shape, particle size, and the surface oxidation rate of solder alloy
have great influence on solder properties. The fabrication methods of solder powder
include chemical reduction, electrodeposition, mechanical processing, alloy atomi-
zation, etc. At present, most lead-free solder powders are produced by atomization
method.
Solders are widely used at different level for electronic packaging, which
include die attach, assembly, sealing, BGA solder, solder bump of flip-chips,
etc. (1) The form of solder in different applications needs to be considered

Table 80.9 Lead-free solders may replace Sn-Pb solders

Eutectic
Solder temperature ( C) Features
Sn-based binary Sn-3.5Ag 221 High mechanical strength and
systems creep resistance
Sn-0.7Cu 227 High mechanical strength
Sn-57Bi 139 High soldering fluidity
Sn-51In 120 High solder-ability
Sn-9Zn 199 High mechanical strength
Sn-5Sb 245 High mechanical properties
Sn-80Au 278 High corrosion and creep
resistance
Sn-Ag based ternary Sn-3Ag- 217.2 High mechanical properties and
systems 0.5Cu solder-ability
Sn-3.9Ag-
0.6Cu
Sn-3.8Ag-
0.7Cu
Sn-Ag-Bi 137.1 High soldering strength
Sn-Ag-In 114 High soldering strength
Sn-Ag-Zn 216.4/193.7 High wettability
80 Package Structure Materials 1797

according to requirements of welding interface materials, metallization layer,

soldering temperature, and so on. For different application, the main forms of
solder types mainly include solder preform, solder paste, solder ball, solder
bump, etc. Solder paste is a complex material system composed of solder powder,
flux, and other additives. Usually, solder powder is main component, which
generally accounts for 80–90% of total solder paste volume. The additives are
mainly for adjusting the paste viscosity and activating welding surface, etc. (2) In
IC packaging, the packaging of devices with high requirements for package heat
dissipation (such as power devices) usually adopts solder for the chip bonding.
The form of solder could be preformed solder or solder paste. Conventional
solder systems for chip bonding include Au-Sn, Ag-Cu, Sn-Pb, etc. Using solder
for chip bonding needs metallization layers on the backside of the chip. (3) Dur-
ing SMT assembly process of lead frame packaging and BGA packaging, the
solder paste is printed onto the printed circuit board (PCB), and the soldering
between electronic components and PCB is performed through the reflow
welding process. (4) In the metal package, ceramic package and other packages
that have air tightness requirements for components, the sealing of metal, ceramic
shell, and cover plate can also be welded with solder.

Under-Fill

Under-fill is used to fill the gap formed by the solder ball connection between the
flip-chips and substrates. The chips, solder bumps, and substrates are tightly adhered
together by the under-fill, which can effectively reduce the stress generated on the
solder joints caused by the mismatch of the TEC between the chips and substrate for
improving the thermal fatigue lifetime of the solder joints [11, 12]. The ingredients
of under-fill usually consist of epoxy resin, curing agent, accelerator, inorganic filler,
coupling agent, toughening agent, etc. The performance of the under-fill contains the
curing procedure, flow-ability, thermal-mechanical, contact angle, surface tension,
water absorption, adhesive strength, thermal-cycling aging, etc.
According to the different processing procedures, the flip-chip under-fill process
can be divided into the conventional flip-chip capillary under-fill process, the
no-flow under-fill process, and the wafer-level under-fill process. (1) Conventional
flip-chip capillary under-fill process: It is the most mature and most widely used
under-fill technology in manufacturing. It relies on the capillary force to draw the
under-fill materials into the small gap between the chip and the substrate. The under-
fill material is then cured. Figure 80.10 schematically shows the process steps of flip-
chip with capillary under-fill [13]. It is applied after the flip-chip interconnects are
formed. In this process, separate flux dispensing and cleaning steps are required
before and after the assembling of the chip, respectively. After the chip is assembled
onto the substrate with a subsequent bump reflow step, the under-fill material is
usually needle-dispensed with “L” shape along one side of the die, and then flows
underneath the die and fills the gap through the capillary effect. After that, the under-
fill material is cured to form a permanent solid composite by heating the assembly at
1798 D. Yang et al.

Fig. 80.10 Conventional capillary flow under-fill process

an elevated temperature. However, as the increasing in chip dimensions and I/O

counts as well as the decreasing in gap distance and pitch sizes for future IC
packaging, these will block the flow of under-fill materials at the bottom and cause
problems for the capillary under-fill process, including the reduction of packaging
efficiency, and also serious the reliability issue introduced by gas bubbles during the
capillary process.
(2) No-flow under-fill process: It was invented to alleviate the problems associ-
ated with the traditional capillary under-fill process. The no-flow under-fill process
dispenses the liquid under-fill material onto the substrate prior to the placement of
chip. Then, the chips are aligned and placed onto the bonding sites, compressing the
liquid under-fill material and forcing it to flow outward to the edge of the chips until
the solder bumps contact the substrate pads. This novel no-flow process eliminates
the flux dispensing and flux cleaning steps, avoids the capillary flow of under-fill
material, and also combines the solder bump reflow and under-fill material cured into
a single step. Obviously, this process provides a significant reduction in process steps
and time saving, improving both productivity and cost competitiveness as shown in
Fig. 80.11. (3) Wafer-level under-fill (WLU) process: In the process of WLU, the
under-fill materials are applied directly either onto a bumped wafer or a wafer
without solder bumps using a proper printing or coating method. The under-fill
material is then solidified by drying the solvent or partial curing. Next, the wafer is
diced into single chips, and these diced chips are then picked, aligned, and placed
onto the substrate using the standard SMT assembly equipment. When the assembly
goes through the reflow oven, the semisolid self-fluxing under-fill material will melt,
flow, and provide the fluxing capability to allow the solder to wet the Cu pads. The
process is briefly schematically shown in Fig. 80.12. Wafer-level packaging (WLP)
has been growing continuously in IC packaging due to its low cost in batch
manufacturing and the potential of enabling wafer level test and burn-in.
80 Package Structure Materials 1799

Fig. 80.11 The no-flow under-filling process steps

Fig. 80.12 Schematic of wafer-level under-filling process steps

Inorganic SiO2 filler plays an important role in tailoring the overall performance
of under-fill materials. Filler size, morphology, surface chemistry, and loading have
significant impact on the performance of the under-fill materials. The filler used in
the under-fill material is usually spherical silica particles due to their good fluidity.
Typically, the size of the filler used is less than one-third of the gap between the
substrate and the chip. The micron (μm)-level sized spherical SiO2 particles are
usually used in conventional capillary under-fill process. Compared with um-level
sized SiO2 filler, nano-level sized SiO2 filler showed higher optical transparency
because the filler size is smaller than the wavelength of visible light, which meets the
requirements of wafer-level packaging process. For molded under-fill materials,
nano-level sized SiO2 can be used as a filler for further reducing its coefficient of
thermal expansion. Nano-level sized SiO2 plays an important role in improving the
overall performance of under-fill materials, and their use in under-fill materials
instead of micro-level sized SiO2 has become a new development trend.

References
1. https://www.ngkntk.co.jp/product/semiconductor_packages/htcc.html
2. http://www.cnledw.com/info/newsdetail-25424.htm
3. Z. Xiaohong, H. Ming, Z. Guozhu, Research status and Prospect of new electronic packaging.
J Jiamusi University (Natural Science Edition) 23(3), 460–464 (2005)
1800 D. Yang et al.

4. M.A. Occhionero, Aluminum silicon carbide (AlSiC) for thermal management solutions and
functional packaging designs, in Proceedings of SPIE – the International Society for Optical
Engineering, January, (1998)
5. S. Zhuoshi, Present situation and development trend of metal packaging materials. Electron
Packag 5(3), p6–p15 (2005)
6. http://china.makepolo.com/product-picture/100752824087_0.html
7. L. Ju, Discussion on high power LED heat dissipation technology. J Yichun University 36(6),
46–49 (2014)
8. H. Manko, Solder and soldering, 2nd edn. (McGraw-Hill, New York, 1979), pp. 23–24
9. J.W. Evans, D. Kwon, J.Y. Evans, A Guide to Lead-Free Solders: Physical Metallurgy and
Reliability (Springer, London, 2007), pp. 1–25
10. T. Minbo, Electronic Package Engineering, the, 2nd edn. (Tsinghua University press, Beijing,
2003)
11. S.H. Shi, C.P. Wong, Recent advances in the development of no-flow underfill encapsulants-a
practical approach towards the actual manufacturing application, in Proceedings of the 49th
Electronic Components Technology Conference, vol. 770, (San Diego, 1999)
12. C.P. Wong, L. Wang, S. Shi, Novel high performance no flow and reworkable underfills for flip-
chip applications. Mater. Res. Innov. 2, 232 (1999)
13. L. Daniel, C.P. Wong, Materials for Advance Packaging [M] (Springer, London, 2016)
 Section X
Basic Research and Frontier Technology
Development of Integrated Circuit
Xing Zhang, Jun Xu, Longxing Shi, and Lifeng Liu

Introduction

At present, basic research and frontier technology development in the field of

integrated circuit are very active. New device structures, new materials, and new
technologies emerge one after another. A series of major breakthroughs have been
made in design, manufacturing, packaging, testing, and other related fields, promot-
ing the rapid development of integrated circuit technology.
This section mainly focuses on the important topics in research which has made a
systematic progress, and is expected in the next 5–10 years evolving into the
industrial applications; such topics and projects include the new structure device,
novel integrated circuit, new material, advanced integrated circuit manufacturing
technology, new integration and interconnection, nanoscale device model and sim-
ulation, flexible semiconductor device, integrated micro system technology,
advanced characterization and testing technology, etc. Through reading this Section,
readers can systematically understand the current research frontier and its hotspots in
integrated circuit technology.
Non-traditional New Structure Devices
81
Yimao Cai, Jun Xu, Renrong Liang, Qianqian Huang, and
Zongwei Wang

Contents
Gate-All-Around (GAA) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Tunneling Field-Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805
Impact Ionization MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
Spin Field-Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
Negative Capacitive FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
Magnetoresistive Random-Access Memory (MRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812
Spin-Transfer Torque Magnetoresistive RAM(STT-MRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
Phase-Change Random Access Memory (PCRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Resistive Random Access Memory (RRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819
Memristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1821
Quasi-SOI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826

Abstract
With the rapid development of the integrated circuit (IC) process technology, IC
device technology has made great advances. A variety of new structural and new
principle devices are proposed to meet the needs of device technology and
application development. This chapter focuses on the introduction to
non-traditional new structures and new principles of logic and storage devices
for the ultra-low power consumption application, such as gate-all-around (GAA)
device, tunneling field-effect transistor (TFET), negative capacitive FET, magne-
toresistive random-access memory (MRAM), phase-change random-access
memory (PCRAM), resistive random-access memory (RRAM), etc. The structure
and working principle of the devices are described. It is expected the new devices

Y. Cai (*) · Q. Huang · Z. Wang

Institute of Microelectronics, Peking University, Beijing, China
e-mail: caiyimao@pku.edu.cn
J. Xu · R. Liang
Institute of Microelectronics, Tsinghua University, Beijing, China

© Publishing House of Electronics Industry 2024 1803

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_81
1804 Y. Cai et al.

play an important role in the field of ultra-low power consumption application in

the future.

Keywords
GAA · TFET · Impact ionization MOS · Spin field-effect transistor · Negative
capacitive FET · MRAM · RRAM · PCRAM · Memristor · Quasi-SOI devices

Since the IC process enters the 22 nm technology node, the MOSFET, as the core
device of the IC, has gradually transited from the traditional bulk silicon planar
structure to the FinFET three-dimensional structure and the fully depleted silicon-
on-insulator (FD-SOI) structure. FinFET and ultra-thin SOI device technologies are
expected to extend to technology nodes of 7 nm and beyond.
However, with the development of the demand for ultra-low power IC, new
structured devices with high energy efficiency and ultra-low power consumption
are also important candidates for future IC technology.
This section mainly introduces the logic and memory devices with new mecha-
nisms and structures from the perspective of ultra-low power consumption applica-
tions, some of which have already been applied on a small-scale.
It is expected that these new technologies will be further developed in the next
5–10 years. Some technologies may be complementary to high-performance CMOS
technologies and play a unique role in the field of ultra-low power consumption
application.

Gate-All-Around (GAA) Device

A gate-all-around (GAA) device (transistor), also known as a ring gate transistor, is a

special structure MOSFET, as shown in Fig. 81.1a. The feature is that the gate
electrode completely surrounds the channel region of the device [1], so that the gate

Fig. 81.1 Schematic of two gate-all-around devices

81 Non-traditional New Structure Devices 1805

has the strongest control over the device channel. In general, GAA can be used to
improve the off-state leakage characteristics of a MOS device with ultra-short
channels (e.g., when the channel length is less than 10 nm). A GAA device works
in much the same way as a conventional planar MOSFET. The source-drain current
in the channel of a GAA can flow either in the horizontal direction or in the vertical
direction. For example, in a multi-layer NAND type nonvolatile memory
(3D NAND Flash memory); multiple GAA transistors with vertical channels are
often connected in series [2, 3]. When the diameter of the channel surrounded by the
gate electrode is reduced to the nanometer scale, it can also be called a nanowire
transistor (NWT) [4], as shown in Fig. 81.1b. The driving current of the gate
all-around device is mainly limited by the channel size. If the channel diameter is
too large, the gate electrode will lose the advantage of having strong channel control
capability, resulting in a deterioration of the off-state characteristics of the device.
Therefore, if it is necessary to increase the driving current of a GAA device, a
structure of multiple identical devices connected in parallel is usually used.
The channel material of a GAA device can use a conventional semiconductor
material such as silicon or germanium, or a novel one-dimensional nanowire mate-
rial such as carbon nanotubes (CNT); the gate dielectric can use silicon dioxide, but
also high dielectric constant materials such as hafnia, alumina, or zirconia to further
improve the gate electrode’s ability to control the channel. In addition, when using a
“ring-gate transistor” to refer to a GAA device, it is necessary to distinguish it from
another MOS device, which is actually still a planar device whose gate electrode
layout is a closed ring shape. The source and drain of the closed ring shape MOS
device are located inside and outside of the annular gate electrode.

Tunneling Field-Effect Transistor

Tunneling field-effect transistor (TFET) is a gated p-i-n structure operated by band-

to-band tunneling (BTBT) mechanism [5]. Figure 81.2 shows the schematic dia-
grams of typical TFET structures. One of the most important features of TFET
structure is that the doping types of source and drain regions are opposite, which
differs from conventional MOSFET.

Fig. 81.2 Schematic diagrams of typical TFET structures

1806 Y. Cai et al.

Fig. 81.3 Device operation principle of TFET

In conventional MOSFET, the carriers are thermally injected over an energy

barrier, while the injection mechanism in TFET is an interband tunneling process
of charge carriers by controlling the band bending of the channel region by means of
the gate voltage, as shown in Fig. 81.3. Taking n-TFET as an example, in the
off-state, there are still no available empty states in the channel region for electrons
tunneling due to the higher conduction band edge of the channel than the valence
band edge of the source. The off-state current of TFET is much smaller than the
conventional MOSFET and dictated by the reverse-biased p-i-n current. With the
gate voltage increasing, the energy band in the channel region is pulled down. When
the conduction band edge of the channel is located below the valence band edge of
the source, there is an energy window for electrons tunneling from the source into the
empty states of the channel, and thus the interband tunneling can be switched on
abruptly. Since the high-energy part of the source Fermi distribution is effectively cut
off for the electrons, the switching process of TFET can be much steeper than that of
conventional MOSFET, and the sub-threshold slope of TFET can be lower than the
thermionic limitation of 60 mV per decade at room temperature in MOSFET [6].
To further improve the TFET device performance, researchers have proposed
various novel device designs, such as heteromaterial gate TFET [7] and T-shaped/
Multi-finger gate Schottky barrier TFET [8], etc., which provide the possibility of
TFET technology to become a realistic successor in the future.

Impact Ionization MOS

Impact ionization MOS (I-MOS) is a kind of MOS device that uses a high electric
field between the source and drain regions to cause the carriers’ impact ionization
multiplication effect to achieve a low sub-threshold slope [1]. A typical structure is
shown in Fig. 81.4. I-MOS device implemented on the SOI substrate is actually a
gate-controlled PIN diode in reverse bias. When the applied gate voltage is relatively
low, no inversion layer is formed in the intrinsic region under the gate, and the
effective channel length is the length of the entire intrinsic region. The lateral electric
81 Non-traditional New Structure Devices 1807

Fig. 81.4 Schematic of an

I-MOS device structure [9]

Fig. 81.5 Complementary structure of the I-MOS devices [9]

field between the source and drain is weak and electrical breakdown will not happen
across the channel. The transistor is in the off state. When the applied gate voltage is
relatively high, an inversion layer will be formed in the intrinsic region under the
gate, so that the effective channel length of the device (the length of the remaining
intrinsic region) is significantly shortened. At this time, the lateral electric field
established by the source-drain voltage across the shortened intrinsic region is
significantly enhanced, so that the breakdown electric field of the channel material
is reached to cause an avalanche strike. Through the carrier’s impact ionization
multiplication effect, a large source-drain current is formed and the device is in the
on state. Since the avalanche multiplication effect of impact ionization has a positive
feedback, both theoretical analysis and experimental results indicate that it is possi-
ble to make the sub-threshold slope of the device at room temperature lower than the
ideal value of 60 mV per decade or 60 mV/dec [10, 11].
The I-MOS device can be implemented either on an SOI substrate or on a
conventional bulk silicon substrate. In addition, the n-type impact ionization MOS
device can be changed into a p-type by changing the gate electrode position, so that a
complementary I-MOS device structure and circuit can also be realized as shown in
Fig. 81.5.
1808 Y. Cai et al.

Spin Field-Effect Transistor

Spin field-effect transistor (spin-FET) is a new type of microelectronic device that

not only uses the charge properties, but also the spins of electrons. According to the
principle of quantum mechanics, in addition to the charge property, electrons also
have the less known spin characteristic that is the inherent spin angular momentum.
Therefore, with an externally applied magnetic field, the moving electrons are not
only affected by the Lorentz Force, but also by the coupling between the intrinsic
magnetic moment and the external magnetic field. Using both the charge and spin
attributes of electrons to carry information, especially introducing the spin property
into semiconductors, the new device was developed as spintronic devices.
The spin-effect transistor (spin-FET) proposed by S. Datta and B. Das of Purdue
University in 1990 is a typical spintronic device [12], as shown in Fig. 81.6. The
device is based on a heterostructure formed between ferromagnetic metal and
semiconductor material. It can be regarded as a field-effect transistor with both the
source and drain regions using ferromagnetic metals. By varying the gate voltage,
the spin-polarized electrons’ Rashba movements within the indium gallium arsenide/
indium aluminum arsenide (InAaAs/InAlAs) two-dimensional electron gas channel
are changed so that the channel conduction characteristics are changed. Introducing
the electrons’ spin properties into semiconductor devices, the charge and spin
properties can be perfectly combined to achieve more flexible information acquisi-
tion, amplification, transmission, and storage.
Spintronic devices provide a new insight for the development of new ultra-high
speed, low power consumption, and multi-functional semiconductor devices
[13, 14]. At present, the main problems of spin field effect transistors are that after
the spin-polarized electrons from the ferromagnetic metal are injected into the
semiconductor through ohmic contact or Schottky contact, the spin polarizability
is fairly low, the driving ability is comparatively weak, and the anti-interference is
relatively poor, etc.
With the rapid development of VLSI technology, the feature size of semiconduc-
tor devices has been continuously scaled down and has now entered the nanometer
scale. Compared to the charge properties, the spin properties of electrons will have

Fig. 81.6 Schematic of the

spin-FET structure [12]
81 Non-traditional New Structure Devices 1809

more unique advantages in many aspects, such as faster information processing,

lower energy consumption per unit operation, higher integration density, etc. There-
fore, it is expected that spintronic devices will become more and more important in
future information technology industry.

Negative Capacitive FET

The subthreshold slope (SS) is an extremely important indicator of MOSFET

devices. Decline of SS can reduce leakage current and power consumption without
changing the device performance [15]. The SS theoretical minimum of conventional
MOSFETs at room temperature is 60 mV/dec [10, 11], and negative capacitive
FETs (NC-FETs) offer the possibility to break through this theoretical limit [16].
Figure 81.7 shows the schematic structure of a conventional MOSFET.
A NC-FET is a kind of transistor whose insulator is replaced of a right thickness
with a ferroelectric insulator, which will provide a negative capacitance and act as a
step-up voltage transformer, thus amplifying the gate voltage, enhancing gate con-
trol, and reducing the SS.
The dielectric materials can be polarized by external electric fields which makes
the capacitance smaller than the vacuum capacitance, while the ferroelectric material
polarizes spontaneously. Similar to the ferromagnetic materials, the polarization of
the ferroelectric materials can be reversed when the external electric fields change,
yielding hysteresis loops and equivalent negative capacitance.
From the energy point of view, the relationship curve of the Gibbs free energy and
the electric polarization of a capacitor is a parabola opening to the top, whose
opening and size are determined by the capacitance. In contrast, ferroelectric mate-
rials have two stable equilibrium states and an unstable equilibrium state at zero
(i.e., one peak and two valleys on the energy-polarization curve). Therefore, the
curve near zero can be approximated as a parabola opening to the bottom, thus
indirectly showing the characteristics of the negative capacitance (as shown in
Fig. 81.8).
In 2015, experiments exhibited the “inductance”-like time dynamics of the
ferroelectric polarization, confirming the negative capacitance characteristics of

Fig. 81.7 schematic

structure of a traditional
MOSFET
1810 Y. Cai et al.

Fig. 81.8 Hysteresis curve of ferroelectric materials and free energy-polarization curve of linear
capacitor and ferroelectric materials [16, 17]

ferroelectric materials. Although the characteristics of the negative capacitance of

ferroelectric materials is unstable, when connecting the ferroelectric materials in
series with another capacitor (with a larger capacitance), in theory, the whole system
can become stable without hysteresis.
There will be processing problem if the gate material is directly replaced by
ferroelectric materials. As shown in Fig. 81.9, the gate dielectric of negative capac-
itive FETs consists of a ferroelectric layer and a linear insulating layer, which brings
new design requirements. On the one hand, the capacitance (CFE) of the ferroelectric
layer should be smaller than that of the linear insulating layer (Cox) so that the whole
dielectric layer exhibits a negative capacitance characteristic. On the other hand, the
total capacitance in series with the ferroelectric layer (CMOS) should be larger than
of the ferroelectric layer capacitance (CFE CFE) to eliminate the hysteresis of the
ferroelectric material.
81 Non-traditional New Structure Devices 1811

Fig. 81.9 Schematic

structure of a negative
capacitive FET and the
ferroelectric layer capacitor
design window [18]

Negative capacitive FET is one of the methods to break through the fundamental
lower limit of the subthreshold slope. Compared with other methods (such as TFET),
it has following advantages: it does not change the channel transport mechanism of
the MOSFET, and can be compatible with various technologies that attempt to
improve the performance of the MOSFET devices by channel engineering; from
the processing point of view, it just needs to replace or insert a ferroelectric layer into
the gate dielectric layer, and is compatible with the existing MOSFET processes.
Negative capacitive FETs can reduce the operating voltage of the devices while
ensuring high performance and low power consumption [19], and have great appli-
cation potential.
In 2008, Salahuddin et al. first proposed the concept of Negative capacitive FETs
theoretically, which use the negative capacitance characteristics of ferroelectrics to
“amplify” the gate voltage, thereby reducing the subthreshold slope of the devices
[16]. In the same year, Salvatore et al. successfully integrated a thin ferroelectric
layer into the gate stack of a standard MOS transistor for the first time and break
through the subthreshold slope limit of 60 mV/dec at room temperature (up to
13 mV/dec). In 2015, Khan et al. measured the “inductance”-like transient response
of ferroelectric materials by applying pulses, and experimentally confirmed the
negative capacitance characteristics of ferroelectric materials; continued in 2016,
1812 Y. Cai et al.

Khan et al. connected the gate of FinFET with an external ferroelectric capacitor,
which demonstrated the possibility of using negative capacitance gate materials in
short-channel devices [19].

Magnetoresistive Random-Access Memory (MRAM)

Magnetoresistive random access memory (MRAM) with non-volatile characteristic

emerged in the 1990s. Compared to traditional RAM technologies, MRAM has an
access speed similar to that of static random access memory (SRAM); its integration
density is comparable to that of dynamic random access memory (DRAM) and
consumes lower power. In terms of reliability, MRAM has nearly infinite endurance
of read/program cycles and is faster than Flash memory. With these advantages,
MRAM has become one of the key candidates for future general-purpose memory
[20, 21].
Data in MRAM stores in the magnetic medium rather than in the form of charge
or current, which is fundamentally different from DRAM. The storage unit of the
MRAM mainly includes a magnetic tunnel junction (MTJ) and a transistor
connected in series therewith.
The MTJ has two typical structures. One structure consists of stacked four layers
with different materials corresponding to specific functions as shown in Fig. 81.10
[22]. The uppermost layer is used to store information, where the stored information
can be programmed and erased by the direction of the magnetic moment; the second
layer serves as a tunneling barrier, which is a very thin non-magnetic material; the

Fig. 81.10 (a) Typical MTJ with a reference layer pinned by an antiferromagnetic pinning layer.
(b) Typical MTJ characteristic
81 Non-traditional New Structure Devices 1813

third layer is the reference layer with ferromagnetic property; the lowermost layer is
the pinning layer with antiferromagnetic properties, which is used to couple the
reference layer to a certain polarity. In this configuration, the reference layer is
pinned to a particular magnetic polarization by the coupling effect exerted by the
pinning layer. The tunnel barrier acts as isolation between the reference layer and the
storage layer to prevent unwanted mutual coupling effect, thus the polarization
direction of the storage layer can only be programmed by applying a certain
excitation. The stored information “0” and “1” is determined by whether the
magnetization alignment is anti-parallel or parallel.
Another structure of the MTJ unit is shown in Fig. 81.11. This structure contains
only three layers including storage layer, non-magnetic isolation layer, and pinning
layer. The pinning layer usually has stronger magnetism so that the magnetic
moment can be maintained in a fixed direction permanently while the magnetic
polarization of the storage layer can be altered by the applied external excitation. The
discrimination of the “0” or “1” state can be achieved by the alignment of the
magnetic moment direction between the storage layer and the pinning layer.
The simplest way to read data from MRAM is accomplished by comparing the
read current across the MJT in different storage states. Each MTJ unit is serially
connected to a transistor as a selector to form a memory cell, as shown in Fig. 81.12a.
To access the data from one cell, the selective transistor is activated to connect the

Fig. 81.11 Simplest MTJ

structure [23]

Fig. 81.12 Structure and data access/programming of MRAM cell. (a) Conventional MRAM cell.
(b) STT-RAM cell [23]
1814 Y. Cai et al.

cell to power supply and ground, respectively. Due to the existence of the tunnel
magnetoresistance, the resistance of the cell can be modified by altering the relative
orientation of the magnetic polarization between referent layer and storage layer.
Thus, the stored data can be obtained by measuring the different currents of the two
different resistance states. Generally, if the polarization directions of the two plates
are the same, the memory cell exhibits a low resistance, and the data is considered as
“1”; conversely, if the polarization direction of the plates is opposite, the cell
resistance will be high, and this means “0.”
In principle, there are two ways to write data into an MRAM cell, either by
applying an external magnetic field or by applying an external current. Magnetic-
field writing method uses both write lines and bit lines arranged at the right angle to
MRAM cells to generate specific magnetic field, and program the magnetization of
storage layer either match or against that of the reference layer. Current writing
method uses the spin-transfer torque (STT) to flip the free layer to complete the data
write, as shown in Fig. 81.12b.
The conventional MRAM adopts the magnetic field writing method. As described
above, the two terminals of each memory cell are respectively connected to a pair of
mutually perpendicular write lines, as shown in Fig. 81.13. The magnetic field
induced by the currents flow through the bit line and the write line changes the
polarization direction of the plate, thereby writing data to the memory cell. This type
of writing requires a large current to generate the corresponding magnetic field,
leading to high power consumption, which is one of the main shortcomings of
MRAM. Also, when the feature size of the memory cell is further scaled to a certain
range, the magnetic field generated by programming the selected cell will overlap
and interfere adjacent cells, causing potential false-programming. This issue is also
referred to as half-select or crosstalk problem, which severely limits the spacing of
the MRAM cells and imposes constraints on the scaling potential.
The main development roadmap of MRAM is summarized below: In 1989, IBM
scientists discovered the giant magnetoresistance (GMR) effect in some thin-film

Fig. 81.13 Write crosstalk issue in the MRAM array [20]

81 Non-traditional New Structure Devices 1815

structures. In 2000, IBM and Infineon began joint research and development of
MRAM. In 2003, 128 kbit MRAM chip was successfully fabricated with the 180 nm
process. In 2004, Infineon announced 16 Mbit MRAM prototypes based on 180 nm
process. In 2006, Freescale began selling 4 Mbit MRAM products. In 2008,
Freescale stripped MRAM to a new company called Everspin. In 2009, Everspin
began selling 100 KB MRAM chips to Siemens. In 2014, TDK demonstrated 8 MB
STT-MRAM prototype chip [24].

Spin-Transfer Torque Magnetoresistive RAM(STT-MRAM)

In 1996, Slonczewski [25] and Berger [26] predicted the spin-transfer torque effect
(STT-effect) in theory for the first time. In 2000, Katine et al. first confirmed the spin
transfer torque effect by experiments and proved the feasibility of magnetoresistive
random access memory (MRAM) based on STT-effect [27]. In 2005, Sony success-
fully manufactured 4 kbit STT-MRAM. Then, Hitachi successfully produced 2 Mbit
STT-MRAM in 2007. In 2008, IBM announced the results of statistical research on
STT-MRAM. In the same year, Toshiba first produced STT-MRAM based on
perpendicular magnetization. In 2010, Hynix successfully fabricated 64 Mbit
STT-MRAM based on the 54 nm CMOS technology. In the same year, a 4 kbit
STT-MRAM array based on perpendicular bit switching has been fabricated by
IBM. In 2011, Samsung reduced the feature size of the perpendicular STT-MRAM
to sub-20 nm. In 2012, Everspin Technologies produced the first STT-MRAM
product with a 64 Mbit capacity based on a 90 nm CMOS process; this chip is
compatible with DDR3 memory controllers and entered the market in 2015. In 2014,
TDK-Headway produced 8 Mbit STT-MRAM chips for automobiles applications.
The basic structure of the STT-MRAM is a magnetic tunnel junction (MTJ),
which consists of three parts: the storage layer, the insulation layer, and the reference
layer. The storage layer, also known as the recording layer and the free layer, is a
layer of ferromagnet for recording information, mainly composed of materials such
as CoFeB. The insulating layer, also known as the tunnel layer, is a thin insulating
layer of about 1 nm. Its main function is to provide a medium for changing the state
of the storage layer by using spin-polarized tunneling current. MgO, AlOx, and TiO
are the main materials for insulating layer because of their significant tunneling
magnetoresistance effect (TMR effect). The reference layer is a layer of magnetore-
sistive layer, and its magnetic anisotropy is quite high, so that its magnetization
direction does not change during the operation of the device, so as to provide a fixed
reference magnetization direction. Figure 81.14 shows a typical structure of the
STT-MRAM [27].
STT-effect is the basic physical principle of STT-MRAM, which can be explained
by a free electron model, as shown in Fig. 81.15. As can be seen, a
non-ferromagnetic layer separates two ferromagnetic layers. Because of spin-
dependent scattering, the electrons in ferremagnetic layer will become spin-polarized
along the magnetization when current flows through this ferromagnetic layer. Then,
when the spin-polarized current goes into the other ferromagnetic layer, the
1816 Y. Cai et al.

Fig. 81.14 A typical

structure of the STT-MRAM

Fig. 81.15 Free electron model of STT effect

conduction electrons undergo spin exchange with the electrons responsible for local
magnetization to generate a local exchange field along the magnetrization. As a
result, around this local exchange field, the spin of the transmitted electrons proceed
incoherently. So, the current repolarize along the magnetization in a very short
distance (~1 nm). Therefore, the momentum difference between incoming and
outgoing currents produces a torque, which is called the spin-transfer torque,
because of momentum conservation [25, 26].
STT-MRAM is mainly divided into in-plane STT-MRAM; in-plane STT-MRAM
with PPMA (partial perpendicular magnetic anisotropy), perpendicular MTJ
(P-STT-MRAM), dual MTJ (DMTJ), and thermally assisted STT-MRAM. The
DMTJ structure is shown in Fig. 81.16. In recent years, STT-MRAM technology
has been rapidly developed, performance has been continuously optimized, and new
STT-MRAM products have entered the market.

Phase-Change Random Access Memory (PCRAM)

Phase-change memory (PCM) or phase change random access memory (PCRAM) is

one of the candidates in the fields of emerging non-volatile memories. The earliest
research on phase change materials can be traced back to the 1960s [28]. In the 1970s
81 Non-traditional New Structure Devices 1817

Fig. 81.16 The structure of DMTJ [27]

Fig. 81.17 Structure of PCRAM and schematic of applied electric stimuli [30]

and 1980s, researchers from industrial and academic fields focused on GeSb (GS),
SbTe (ST), and series of chalcogenide. After that, they gradually focused on GeSbTe
(GST) [29]. Unlike the crystallization of phase segregation in GS or ST materials,
GST occurs with congruent crystallization, which lays the foundation for the appli-
cation of phase change memory later on.
As shown in Fig. 81.17, the basic structure of PCRAM is a sandwich-like
structure consisting of a metal layer as top electrode, a phase change material
layer, and a metal layer as bottom electrode. The phase change material layer can
undergo transitions between crystalline state and amorphous state by applying
external conditions (such as electrical stimuli). The mechanism of the transition is
related to the accumulation of Joule heat caused by the applied electrical stimuli to
reach the transition temperature. A heat generating filament (heater) is added to the
sandwich-like structure to accelerate heat accumulation for phase change [30].
Transitions of PCRAM include two kinds of processes. One describes the change
from crystalline to amorphous (reset process); the other describes the change from
amorphous to crystalline (set process). For the phase change material, the crystalline
state corresponds to the electrical low resistance state; while the amorphous state
corresponds to the high resistance state. For the reset process, the phase change
1818 Y. Cai et al.

Fig. 81.18 Relationship

between reset current and
cell area

region (also called the programming region) is initially in a crystalline state. If an

appropriate current pulse is applied, the corresponding region can reach the melting
point and become amorphous. After the current pulse is quickly removed, the region
is maintained in an amorphous state. For the set process, the phase change region is
initially in an amorphous state, and if an appropriate current pulse is applied thereto,
the phase change region can be brought to a sufficient temperature so as to be
converted into crystallization.
The relationship between the reset current of the phase change memory cell and
the cell area is shown in Fig. 81.18. The reset process is the most energy-consuming
process of PCRAM operations. How to reduce the reset current to decrease the
power consumption of PCRAM is still one of the important research directions.
From the view of the phase change mechanism, in order to reduce power consump-
tion, it is needed to make the memory accumulate heat more easily and reach the
melting temperature without being simply dissipated. On the one hand, structural
optimization can be considered, the conductive channel of the heat generating layer
is designed to be narrower, or the contact hole of the bottom electrode is made
smaller, so that the current density strongly increases the heat accumulation in the
region, as shown in Fig. 81.19a. Structural optimization can also be applied by
wrapping the phase change region with a thermally insulated material to improve
heat utilization, as shown in Fig. 81.19b. Both of the structural optimization methods
do not reduce the required energy density for phase transition. On the other hand,
there are proposed studies aiming to modify the phase change mode by controlling
the interface of the material to reduce the energy required for phase change, thereby
reducing power consumption and improving the durability of the device
(Endurance) [31].
Intel released a message in 2009 that it can implement multi-layer PCRAM arrays
and prepare 64 Mbit test arrays, as shown in Fig. 81.20. The results were published
in the same year at the International Electron Devices Meeting (IEDM) [32], which
81 Non-traditional New Structure Devices 1819

Fig. 81.19 Two methods of

structural optimization for
PCRAM

Fig. 81.20 Physical

characterization of PCRAM
by Intel in 2009

demonstrates the potential of PCRAM industrialization. In July 2015, Intel

announced at its official website that it has jointly developed the 3D Xpoint structure
with Micron. It is reported that its main storage unit is also PCRAM.

Resistive Random Access Memory (RRAM)

Resistive random access memory (ReRAM or RRAM) are sort of electronic devices
which can store information by changing the critical materials’ conductivity through
electric field or voltage. In the 1960s, S. R. Ovshinsky et al. found the reversible
resistance switching phenomenon in some dielectric material films. After that, in the
1990s, researchers began to develop novel non-volatile memory based on that
1820 Y. Cai et al.

phenomenon. There are various kinds of inorganic and organic materials having
conductivity switching properties, among which transition metal oxides, like, have
obvious advantages in characteristic and manufacturability.
The general structure of RRAM is “metal-dielectric-metal,” as shown in
Fig. 81.21. The basic operations include “Set” and “Reset.” “Set” means applying
voltage or current to the electrodes at both ends of the device which makes its
resistance decreasing, corresponding to write signal “1” in this device; in this
process, the voltage which triggers the switching is called. On the other hand,
“Reset” means applying voltage or current to the electrodes at both ends of the
device which makes its resistance increasing, corresponding to write signal “0” in
this device; in this process, the voltage which triggers the switching is called. In
some cases, the very first “Set” operation of the initial device needs a slightly larger
voltage than subsequent “Set” operations. To distinguish these two kinds of voltage,
the very first “Set” operation is always called “Formatting.”
Based on the operation strategy, RRAM can be simply divided into two catego-
ries: unipolar and bipolar, as shown in Fig. 81.22. Unipolar RRAM has the same
polarity between and, which means resistive switching can be realized by using just
one single polar voltage and can simplify the circuit design. In contrast, bipolar
RRAM has to depend on two different polarities and to switch, which increases the

Fig. 81.21 The general

structure of RRAM

Fig. 81.22 Unipolar RRAM (a) and bipolar RRAM (b)

81 Non-traditional New Structure Devices 1821

complexity of circuit design; however, this kind of device is relatively stable and has
better cycling characteristic plus lower switching power consumption.
Due to the severe challenges faced by Flash, like high-operation voltage, reli-
ability, and the scaling-down issue, RRAM is considered to be a promising novel
non-volatile memory (NVM) because,

1. RRAM’s structure and fabrication process are simple and easy to realize 3D
integration which can improve storage density;
2. The processes to deposit metal electrodes and dielectric layers are compatible
with standard CMOS processes which can meet the needs of both embedded
storage and independent storage;
3. Low operation voltage (usually below 3 V) has obvious advantages over Flash
which can effectively reduce peripheral circuits’ area and power consumption;
4. RRAM can achieve multilevel storage in a single device which can further
improve storage density.

In recent years, RRAM based on transition metal oxides has shown excellent
performance and developed rapidly. In 2013, SanDisk and Toshiba reported a
32 Gbit RRAM prototype in 24 nm process [33]. In 2015, Panasonic released a
2 Mbit TaOx-based embedded RRAM array in 28 nm process, which cycling
endurance was up to 105 times and data retention was over 10 years under 85  C
[34]. In 2016, Y. Hou et al. found that HfOx-based RRAM still exhibited good
switching characteristic at 10 nm or less, which shows excellent scaling-down
potential [35].

Memristor

The concept of “memristor” was first proposed by Leon O. Chuan [36] of the
University of California, Berkeley – after studying the relationship between voltage,
current, flux and charge, after which he argued that besides the three basic compo-
nent, resistor, inductance, and capacitor, there is also the fourth component, as shown
in Fig. 81.23. Memristor is sort of circuit element that reflects the relationship
between flux and charge. Unlike resistor, memristor can reveal the previous charge
flowing information after disconnected, that is, the memory trait of memristor. In
2008, HP’s researchers first reported a practical nanoscale-memristor, which offered
a new method to investigate memristor. Compared with conventional Random-
Access Memory, memristor have better scaling-down ability, faster erase/write
speed and lower power consumption, and based on these superior performance,
memristor are expected to become the new generation of non-volatile memory. In
addition, memristor’s structure and working mechanism are very similar to the
synapse and neuron, which make it suitable to construct hardware Artificial Neural
Network (ANN). Last but not the least, because of its unique nonlinearity, memristor
can be used to generate chaotic signals in circuit and utilize in encrypted
communication.
1822 Y. Cai et al.

Fig. 81.23 Relations among

the four electronic
components [37]

Fig. 81.24 General structure (left, a) and the I-V curve (right) of Memristor [37]

Memristor is of two-terminal element with Metal-Insulator-Metal (MIM) struc-

ture. It consists of a top electrode (TE), a bottom electrode (BE), and (a) dielectric
material layer(s) (S-L) between the two electrodes, as shown in Fig. 81.24a. Metal
electrode material can be a traditional metal, such as Au, Pt, Cu, Al, etc. The
materials of dielectric layer mainly include binary transition metal oxides, perovskite
compounds, solid electrolyte materials, organic materials, etc. When a certain
voltage is applied on the two electrodes, the dielectric layer will switch between
two stable resistance states (low resistance state and high resistance state). The I-V
curve of the memristor is shown in Fig. 81.24b, one can find that memristor has
obvious hysteresis characteristics.
81 Non-traditional New Structure Devices 1823

There are types of memristor [38]. Based on the resistance switching mechanism,
memristor can be simply divided into four types: Conductive Filament (CF), Inter-
face Barrier, Charge Trapping/Detrapping, and Insulator-to-Metal Transition (IMT).
In recent years, memristor has made so many astonishing progresses: in 2008, HP
Laboratory developed a TiO2-based RRAM device and linked RRAM to memristor
for the first time [37]. And in 2010, the Boolean logic operation function of
memristor was demonstrated. In 2013, Thomas Andy’s team introduced memristor
in chip design to mimic biologic synapses. In 2016, based on memristor, IBM Zurich
Research Center made the world’s first artificial nanoscale stochastic phase change
neurons [39]. In the same year, Joshua Yang’s team, at the University of Massachu-
setts Amherst, invented a new type of memristor – diffuse memristor – to imitate
biologic synapse’s molecular dynamics characteristics and critical functions [40].

Quasi-SOI Devices

The quasi-SOI MOSFET proposed by Peking University is a planar device with a

novel source/drain structure fabricated on a bulk silicon substrate [41]. Compared
with traditional bulk planar devices, the quasi-SOI MOSFET has stronger ability to
suppress short channel effects and junction leakage, which is comparable to ultra-
thin body SOI (UTB-SOI) devices. On the other hand, the quasi-SOI MOSFET is
superior to UTB-SOI devices in aspects as self-heating, parasitic capacitance, total
irradiation dose (TID), process variations, and process compatibility.
The most distinguishing structure feature of a quasi-SOI device from a conven-
tional bulk one lies in the L-type dielectric layer which wraps most of the source and
drain regions so that these regions are separated from the substrates physically, as
shown in Fig. 81.25. The junction depth of the LDD is defined by the distance h1
between the upper surface of the oxide layer and the silicon surface; consequently,
the short-channel effect can be suppressed. Additionally, the recessed source and
drain junction depth Xj can be flexibly designed; therefore, the ion implant energy
and thermal budget for impurity activation can be relaxed.
Compared with traditional bulk planar devices, quasi-SOI MOSFET has a stron-
ger ability to suppress short channel effects and junction leakage, which is compa-
rable to UTB-SOI devices, as shown in Fig. 81.26. On the one hand, the quasi-SOI
device reduces the drain-channel coupling by the L-type dielectric layer and the
highly doped substrate. Therefore, the quasi-SOI device can effectively suppress the
drain-induced barrier lowering (DIBL) effect. On the other hand, due to the main
region of source-drain is enclosed with insulation layer, the shared charge between
the source/drain region and the substrate is reduced, so that a better subthreshold is
effectively improved and thus the subthreshold slope can be achieved. Moreover,
due to the isolation of the insulation around source/drain, it can effectively reduce the
tunneling current between the source/drain region and the highly doped substrate,
which brings a larger flexibility for multi-Vth design.
1824 Y. Cai et al.

Fig. 81.25 (a) Schematics of device structure of quasi-SOI MOSFET; (b) SEM cross-sectional
structure of 70 nm quasi-SOI MOSFET device [42]

Fig. 81.26 Electric field

distributions along with
channel direction of UTB SOI
and quasi-SOI [43]

Quasi-SOI MOSFET has better heat-dissipating ability than UTB-SOI devices.

Because the channel is directly connected with the substrate, the generated heat in
quasi-SOI MOSFET can quickly flow away through the substrate. Moreover, quasi-
SOI MOSFET has faster speed due that there is no scattering effect from the buried
SiO2 layer.
Quasi-SOI MOSFET has superior high frequency characteristics compared with
UTB-SOI devices. The benefit comes from the recessed source/drain structure in
quasi-SOI MOSFET which can effectively reduce the parasitic capacitance and
obtain a higher cut-off frequency (ft) and maximum frequency (fmax). In contrast,
the raised source/drain structure brings a large excess parasitic capacitance for
UTB-SOI devices, as shown in Fig. 81.27.
81 Non-traditional New Structure Devices 1825

Fig. 81.27 Fringe capacitance [44] of quasi-SOI (a) and UTB SOI (b)

Fig. 81.28 Parasitic leakage current by TID in quasi-SOI (left) and UTB SOI (right). Top panel
shows vertical view and bottom panel shows the cross-sectional view [45]

Quasi-SOI devices have superior ability to suppress the total ionizing dose (TID)
effect compared to both UTB-SOI and bulk devices. The mechanism of device
performance degradation reduced by TID is the trapped positive charges generated
by ion radiation which can form current leakage paths in an oxide layer. For
UTB-SOI devices, the leakage path is generated at the channel/buried oxide interface
and the channel/STI sidewall interface, while for bulk devices, the leakage path are
mainly distributed at the channel/STI sidewall interface and source/drain junction/
STI sidewall interface. The leakage path can only be generated at the channel/STI
sidewall interface in a quasi-SOI MOSFET, attributed to that the channel of the
quasi-SOI device is directly connected to the substrate, so there is no leakage
channel due to the positive charge of the buried oxide layer trap, and the L-type
oxide layer can as well block the leakage path at the source/drain junction/STI
sidewall interface, as shown in Fig. 81.28.
1826 Y. Cai et al.

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New Type ICs
82
Nanjian Wu, Huaxiang Lu, Yongpan Liu, Leibo Liu, and Baoyong Chi

Contents
Artificial Neural Network (ANN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830
Brain-Inspired Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
Reconfigurable Computing Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833
Terahertz Integrated Circuit (THz IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
Quantum Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836
Cognitive Radio Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839
Nonvolatile Logic Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841
Biomedical Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844

Abstract
With the rapid development of artificial intelligence, Internet of things, big data,
and other new applications, the demand for high-performance and energy-
efficient computing hardware is growing. Traditional integrated circuits (ICs)
processors based on von Neumann architecture face performance bottlenecks
due to the memory wall effect. New integrated circuits with novel chip architec-
ture and new principles are being proposed and studied. In this chapter, new type
ICs are briefly introduced and discussed, including brain-inspired chip,
reconfigurable computing integrated circuits, terahertz integrated circuit, quan-
tum integrated circuit, and cognitive radio integrated circuits. The characteristics
and application of the new IC technology are also addressed.

N. Wu (*) · H. Lu
Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China
e-mail: nanjian@red.semi.ac.cn
Y. Liu
Department of Electronic Engineering, Tsinghua University, Beijing, China
L. Liu · B. Chi
Institute of Microelectronics, Tsinghua University, Beijing, China

© Publishing House of Electronics Industry 2024 1829

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_82
1830 N. Wu et al.

Keywords
Artificial neural network (ANN) · Brain-inspired chip · Reconfigurable
computing integrated circuits · Terahertz integrated circuit · Quantum integrated
circuit · Cognitive radio integrated circuits · Nonvolatile logic integrated circuit ·
Biomedical chip

Artificial Neural Network (ANN)

Artificial neural network [1, 2] is proposed basing on the research achievement of

modern neuroscience. It analogs the human brain neural network from the point of
information processing, builds up the neuron model, and establishes well-behaved
network through certain interconnections of numerous artificial neurons. It is a
dynamic nonlinear system characterized by distributed storage and widely paralleled
cooperative processing and has the feature of fault-tolerance, self-organization, self-
adaptation, self-study, and evolution which obtain more advantages in the field of
complex function approximation, optimization, classification, and clustering than
the traditional computer structure. With the human brain’s ability to image thinking
and associative memory, the neural network can solve many problems that are
intractable for current computer architecture.
Modern neural network is originated from McCulloch and Pitts’s pioneer work in
1943. They proposed MP model, a mathematical model of neuron that is still used
today. In 1949, psychologist Hebb proposed the Hebb rule that can change the
connection strength of neurons. In 1957, Rosenblatt developed perceptron, the first
pattern recognition device with the feature of learning neural network. However, the
research on neural network sank into a low tide in 1969 for the skepticism of two
authoritative scholars M. Minsky and S. Papert; it was pointed out that in their book
Perceptron that single-layer neural network cannot even realize the simple logic
function of XOR and the multilayer neural network may not be feasible. Until 1982,
it is Hopfiled who successfully solved the NP-hard traveling salesman problem
through a fully connected neural network model that made the neural network
enter the stage of flourish development. The feed-forward neural network was very
popular in 1990s with the proposal of BP (back-propagation) algorithm which
enables network to learn rules from large training samples and to predict and
judge the future situations. But with the limitations of BP algorithm, at this time
feed-forward neural networks were usually shallow models with only one hidden
layer which cannot solve the complex big data problem in practical applications. In
2006, Hinton proposed deep learning algorithm [3] that solved the problem of
effectiveness for deep neural network. Thus, deep neural network is widely used
in the field of image recognition, speech recognition, machine translation, and many
other fields. It has better effect comparing with the traditional algorithms and brings
a new climax to artificial neural network.
Now, there are two main methods to implement artificial neural network. One is
to simulate the network by software basing on the existing von Neumann
82 New Type ICs 1831

architecture digital computer. Another is full hardware implementation. It is flexible,

easy to use and low cost to simulate the network by software. But due to the feature
of von Neumann architecture and the inevitability to carry out the numerous
paralleled computing of neural network through serial fashion that cannot take the
artificial neutral’s advantages of distributed storage and widely paralleled coopera-
tive processing. In addition, the software needs numbers of computer cluster to
simulate large-scale neural network. Google’s deep learning system Google Brain is
based on 1000 of 16-core computers. Although with outstanding ability, the energy
consumption is very huge.
Full hardware implementation of the neural network means to map the neural
network to physical entity by microelectronic and optics technologies. At present,
microelectronic technology is the most effective method to implement neural net-
work for its high precision, strong anti-noise ability, program controllability, and
mature techniques. The largest synapse computing chip so far, SyNAPSE [4]
released by IBM, is implemented by microelectronic technology. It consists of
256 million programmable synapses and one million programmable neurons and
only consumes 1 J energy for 46 billion times synapse computing. It is one of the
biggest CMOS chips with 5.4 billion transistors. During its biologic real-time
computing, its power consumption can be as low as 70 mW which is several orders
of magnitude lower than modern microprocessors.
In order to implement high-density and low power consumption artificial network
to adapt to the increasing application requirements, new materials and devices like
memristor and phase-change memory are being developed continuously. In August
2016, IBM officially announced the successful development of the world’s first
nanometer-scale stochastic phase-change neuron. It uses phase-change materials to
store and process data and can be applied to pattern recognition and association
discovery in big data and the high-speed low-power unsupervised machine learning.

Brain-Inspired Chip

Many applications have been powered by the fast-developed machine learning

algorithms and the availability of massive amounts of big data, including image
classification, speech recognition, language processing, and game playing. However,
there is a daunting challenge that the capabilities of central processing units (CPUs)
cannot meet the requirements of computation tasks of machine learning algorithms.
The graphics processing units (GPUs) are heavily used in the AI field due to its
massive parallel processing capability, which speeds up the training process signif-
icantly. On the other hand, the GPU is originally designed for graphics processing
but not tailored for AI algorithms, resulting in a large waste of computer power.
Therefore, many innovated AI accelerators have been introduced to speed up the
processing of neural network dedicatedly. A performance bottleneck is normally
encountered as the separation of the processing unit and memory due to the memory
wall effect, which leads to a constraint of computing efficiency.
1832 N. Wu et al.

Drawing the inspiration from the human brain, neuromorphic engineering [5] has
become a unique approach in developing novel chip architecture, aiming to explor-
ing bio-inspired principles. Different kinds of circuits, including analog circuits,
digital circuits, and analog–digital hybrid circuits, have been used to implement the
neuromorphic chips. Among them, digital circuits are most popular due to the
advantages of flexible design, online programming and modulation, high-precision
storage, immunity to noise, mature routing technologies, and well-developed elec-
tronic design automation (EDA) tools, providing powerful support for circuit design.
Therefore, brain-like chips based on traditional silicon technology based on digital
circuits have drawn much research attentions.
Currently, the landmark chip in the neuromorphic field is the TrueNorth [6],
which was released in August 2014. The chip aimed to provide an energy-efficient
platform for spiking neural network (SNN). It consists of 4096 processing cores with
256 artificial neurons in each core, simulating one million neurons and 256 million
synapses. TrueNorth can support up to 50 neuronal models, including the 20 most
prominent behavioral features in spiking neurons. In addition, the system operates in
an event-driven mode, which greatly reduces the power consumption. Despite 5.4
billion transistors on chip, TrueNorth only consumes 70 mW typically, which is
significantly lower than that of traditional CPUs under the similar transistor count.
Other famous neuromorphic chips include ARM-based SpiNNaker from the
University of Manchester [7], BrainScaleS from the University of Heidelberg [8],
and Neurogrid from Stanford University [9]. Significant progresses have been made
in China as well. For example, a customized neural network accelerator, named
Cambrian, was jointly designed by the Chinese Academy of Sciences and the French
Inria. Tsinghua University developed Tianjic chip, which can not only accommodate
machine learning algorithms, but also support neuroscience-inspired models (e.g.,
spiking neural network) and their hybrid networks. The chips of Prophecy and
Darwin were reported by the Chinese Academy of Sciences and Zhejiang University,
respectively.
In recent years, a research direction in neuromorphic field is utilizing novel nano-
devices to emulate the neurons and synapses for the development of high-density,
high-performance neural network, as shown in Fig. 82.1. Among the nano-devices,
the memristor has shown a lead in neuromorphic emulation due to its excellent
shrinking capability, non-volatility, intrinsic dynamics, and simple manufacture
structure [10, 11]. A wide variety of materials can be used to act as the resistive
switching layer in memristors, including titanium oxide, hafnium oxide, tantalum
oxide, silicon dioxide, and the 2D materials. By using the characteristics of multiple
resistance states of memristor and its responses to the pulse width or pulse amplitude,
the biological learning rules, such as spike-timing-dependent plasticity (STDP),
could be achieved [12]. Compared with previous silicon-based synapses, memristor
synapses exhibited improved power consumption, simple emulation of neural
dynamics, reduced synaptic area, and less design constraints, providing more free-
dom in learning rule simulation.
Besides, phase-change memory (PCRAM) and magnetic memory (MRAM) can
also be used for the simulation of synapses and neurons. China has also made great
82 New Type ICs 1833

Fig. 82.1 Schematic illustration of artificial synapses using memristors in neural networks

progresses in the fabrication of nano-devices and actively contributed to the

neuromorphic research field. In short, the brain-inspired technology evolves fast,
and cross-disciplinary researches are required.

Reconfigurable Computing Integrated Circuits

Reconfigurable computing is a computational structure that maps computational

tasks to a spatial engine and that can be flexibly changed after being fabricated
into silicon [13]. In 1960, Professor Gerald Estrin of University of California, Los
Angeles, proposed the original concept of reconfigurable computing, establishing a
theoretical basis for reconfigurable systems that a computer is composed of a master
controller and a set of reconfigurable hardware units with varying functions [14].
Under the management and monitoring of the master controller, the reconfigurable
hardware units achieve an accelerated processing of the tasks by using
reconfiguration and tailoring functions based on the characteristics of the tasks.
Because the semiconductor technology was very backward at the time, the theory
has not continued to develop since its introduction. Since the 1990s, with the
continuous advancement of microelectronics technology and increasing number of
integrated transistors on a single chip, reconfigurable computing has regained
attention and attraction from industry and academia. In 1999, Andre Dehon et al.
1834 N. Wu et al.

of University of California, Berkeley defined reconfigurable computing as a specific

computer organization [15], which mainly has the following two characteristics:

1. It can be customized after chip fabrication. After the “silicon implementation,”

the computation and interconnection functions of the chip can still be changed
according to the demands of the software.
2. It can map algorithms or tasks to the processing element arrays and schedule
executions according to certain rules. This feature belongs to the spatial mapping,
which is fundamentally different from that of traditional processors, which use
instruction-driven and time-multiplexing computing units.

A reconfigurable computing processor (RCP) is a processor that performs oper-

ations in a reconfigurable manner. Figure 82.2 shows the software and hardware
organization of a reconfigurable computing system. As shown in Fig. 82.2a, the
hardware of the reconfigurable computing processor consists of the reconfigurable
datapath (RCD) and the reconfigurable controller (RCC) that is based on a program-
mable finite state machine. The reconfigurable data path is generally composed of a
large number of reconfigurable processing elements (RPEs), which logically consti-
tute one or multiple one-dimensional, two-dimensional, or even three-dimensional
reconfigurable cell arrays (RCAs). Figure 82.2b shows the architecture of the
compilation system corresponding to the hardware architecture. The compiler trans-
lates software programs that are written in a high-level programming language into
configuration contexts that can be executed by a reconfigurable computing

Fig. 82.2 Software and hardware organization of the reconfigurable computing system [13]
82 New Type ICs 1835

processor. These configuration contexts specify the function, interconnection, and

execution order of each RPE in the RCD. Read by RCC, the configuration contexts
are used to control the operation and execution of the RCD. Note that once the
design of the reconfigurable computing processor is completed, its architecture is
fixed (the reconfigurable computing processor is an integrated circuit that cannot be
changed once it is fabricated), but the software can be constantly changed. Once
compiled, a piece of software can generate a set of configuration contexts that can be
executed by reconfigurable computing processors, and the desired results can be
obtained by running the configuration contexts on the reconfigurable computing
processor.
The reconfigurable computing processors can be classified into hybrid-grained,
coarse-grained, medium-grained, and fine-grained processors, according to their
granularities (i.e., the bit width of the reconfigurable processing unit and the inter-
connection). Generally, if the bit width of a processing unit is 1–4 bits, it is
considered to be fine-grained, 4–12 bits are considered to be mid-grained, and
12 bits or more (generally 16 bits or 32 bits) are considered to be coarse-grained.
The hybrid granularity refers to that the processing unit of the reconfigurable
computing processor has at least two different granularities. If classified according
to the reconfiguration patterns, the reconfigurable computing processors can be
classified into dynamic configuration and static configuration. The static configura-
tion is generally time-consuming, and the configuration and the computations cannot
be performed in parallel. The configuration of the processor can only be completed
by suspending the computation. In addition, the reconfigurable computing proces-
sors that support dynamic configuration usually also support partial configuration,
which means that one part of the reconfigurable element arrays is performing
computations while another part is under configuration [16, 17]. This is also called
dynamic partial configuration.
The reconfigurable computing processor has both the high energy efficiency of an
application-specific integrated circuit and the high functional flexibility of an
instruction-driven general-purpose processor.

Terahertz Integrated Circuit (THz IC)

Terahertz wave refers to electromagnetic wave from 0.1 THz to 10 THz. A more
rigorous definition restricts the frequency range within 0.3 THz to 3 THz. The
unique characteristic of terahertz signal makes it attractive in fields such as high-
speed communication, high-resolution phase array radar imaging, non-destructive
diagnose, hazardous object detection, and material recognitions. Terahertz integrated
circuit (THz IC) is the solid-state circuit and system which can generate, detect, and
transfer terahertz signals. The development of THz IC has led to implementation of
more compact, low-power terahertz communication and imaging system which
helps terahertz technique enter into more application areas.
In early time, most THz ICs were implemented with III-V compound semicon-
ductor such as GaAs or InP. The reason is that devices fabricated with these materials
1836 N. Wu et al.

offer high mobility, low noise, and high driving capability which overwhelms their
Si-based counterparts. However III-V semiconductor technology also owes several
drawbacks such as being not compatible with commercial Si CMOS technology,
high cost, and lacking of large-scale integration capability. With progress of Si-based
CMOS, MOS devices shrink significantly and operation frequency of such devices
has now reaching into the THz region. As a result, Si CMOS THz ICs are now
available. These ICs are mainly applied in THz communication and imaging
systems.
In research of terahertz communication ICs, STMicroelectronics reported tran-
sistor fabricated by 0.13 μm SiGe technology. The transistor fT reached 410 GHz
under room temperature. IBM successfully implemented NMOS transistor with fT of
485 GHz. University of Florida reported Schottky diode with fT of 2 THz by 130 nm
CMOS. With progress in Si-based terahertz devices, several building blocks and
THz communication systems were invented. UC Davis reported a 260 GHz
low-noise amplifier with 65 nm CMOS; Wuppertal University reported a terahertz
source of 0.53 THz in 0.13 μm SiGe CMOS. Research groups UC Irvine and UC
Davis cooperated and implemented a 300 GHz frequency synthesizer with 90 nm
SiGe CMOS [18]. Researchers from Hiroshima University reported a 17.5 Gb/s
transmitter chip with 40 nm CMOS [19].
In terahertz imaging ICs, the key issue is how to build terahertz detector with
Si-based CMOS. Detector with Schottky diode and NMOS transistor were proved to
be effective. Terahertz signal can be self-mixed and down converted into DC signal
for detection by using the nonlinearity of both devices. In 2011, CEA-LETI-
MINATEC in France reported 3
4 imaging array with 0.13 μm CMOS. Operation
frequency of this array was from 0.3 THz to 1 T Hz. Clear tree leaf images were
obtained [20]. In 2012, Wuppertal University reported a 32
32 imaging array
sensitive to 0.7–1.1 THz radiation [21]. The above image arrays are all far-field
oriented. In 2016, research group also from Wuppertal University reported a near
field 0.55 THz imaging chip with 0.13 μm SiGe CMOS and gathered ultra-fine
resolution image [22] (Fig. 82.3).

Quantum Integrated Circuit

The continuous scaling down of the transistor gate length in the semiconductor ICs
results in the fact that the quantum effects become more apparent, and it is thus
difficult for transistors to work properly. On the other hand, the serial processing
chips based on von Neumann’s principle are difficult to solve complex mathematical
and applied problems. To overcome these two bottlenecks in the ICs, development of
novel parallel processing ICs based on quantum mechanics principles and effects
may be an inevitable approach.
At present, many countries in the world are actively promoting the research of the
quantum ICs. The quantum ICs can be divided mainly into the following two types:
One is new quantum IC based on some quantum effects and can process information
82 New Type ICs 1837

Fig. 82.3 Potential application of THz ICs

efficiently (type I); another one is quantum IC based on the quantum principles and
can perform parallel computing and storage (type II).
The type I quantum IC adopts quantum effects partially and uses the single
electron or spin to represent the logic signal. The type I ICs include quantum cellular
automata (Fig. 82.4) [23], spin-based logics (Fig. 82.5) [24], and single-electron
circuits [25]. The circuit operates in a new paradigm of ground-state computing.
First, it excites the circuit system into a state with higher energy by setting an input,
and then, it lets the system relax to the ground state by a controllable method. Finally,
we can find the solution to the posed problem by observing the configuration of the
electrons or spins. The circuit can exhibit low-power and parallel computing. These
quantum integrated circuits are still in the stage of the circuit architecture design,
system simulation, and unit circuit fabrication. Further research and development of
the nano-process technology, new algorithm, and effective circuit operation method
are needed.
The type II quantum ICs are the key circuits in the quantum computer and can
perform parallel computing and storage operation on the principle of quantum
mechanics [27]. The quantum computer has super parallel processing capability
and the potential to solve complex mathematical problems in which the computa-
tional complexity increases exponentially with the number of variables. The qubit is
1838 N. Wu et al.

Fig. 82.4 (a) Quantum

cellular automata cell and
(b) majority gate [23]

Fig. 82.5 Single spin NAND

logic gate [24]

a basic unit that represents quantum information. It is different from the bit with
0 and 1 logic states in classic logic circuits and usually takes the linear superposition
of two basic states for information processing.
The quantum computer can consist of some basic quantum gates: a one-qubit gate
and a two-qubit controlled NOT (CN) gate. The quantum computer with N qubits
operates in the following method: First a linear superposition of 2 N basic states is
input; then, some quantum operations are performed according to algorithm; finally,
a new linear superposition of 2 N basic states is output and read out. It is different
from classic computer and a closed coherent system in which quantum information
82 New Type ICs 1839

processing is reversible. The most famous quantum algorithm is the large number
prime factor quantum decomposition that was proposed by P. Shor, an American
Bell Laboratory scientist. It makes us realize the potential of quantum computing to
solve complex mathematical problems and promotes the rapid development of this
technology.
Quantum dot spin logic gates, superconducting quantum logic circuits, and ion
well quantum circuits have been developed in experiments. Recently a tunable, long
coherence hybrid qubit in a five-electron GaAs double-quantum dot was demon-
strated experimentally [26]; a silicon qubit device made with an industry-standard
CMOS fabrication process was reported [27]; a genuine 12-qubit entanglement in a
superconducting processor was verified [28].

Cognitive Radio Integrated Circuits

Cognitive radio was proposed for wireless communication by Joseph Mitola III in
the late 1990s based on the idea of software-defined radio (SDR) [29]. It utilizes a
spectrum cognitive device to cognize unoccupied frequency resources in a specific
area. Since the frequency resources allocated to authorized users may not be
occupied at a specific time in that area, it is possible to dynamically use these
unoccupied frequency resources to communication, thereby avoiding the vacancy
of frequency resources. Cognitive radio could improve the utilization rate of fre-
quency resources and relax the demand for increasingly scarce frequency resources.
The key of the cognitive radio network is dynamic spectrum management, which
includes the following steps: The spectrum cognitive device first cognizes the
unoccupied frequency resources in a specific time and a specific area, and the
spectrum characteristics are analyzed to dynamically configure the parameters of
the communication device based on some management rules, thereby occupying
these frequency resources to establish reliable communication. During the commu-
nication, the cognitive radio device should monitor the occupied frequency
resources. Once it is detected that the authorized user will use the frequency
resources, the cognitive radio will immediately stop the communication and release
the occupied frequency resources to the authorized user. After that, the cognitive
radio device would search new available spectrum resource to establish the commu-
nication again.
As the hardware key of cognitive radio system, cognitive radio IC realizes the
cognition of unoccupied spectrum resources at a specific time and in a specific area
and configures the parameters of highly reconfigurable wireless transceivers or
software-defined radio transceivers according to dynamic spectrum management.
A typical circuit to realize spectrum resource cognition is shown in Fig. 82.6a.
A reconfigurable narrowband receiver converts the received signals from the antenna
within a particular communication channel from radiofrequency to intermediate
frequency or digital domain and then uses the spectrum sensing algorithm such as
energy detection, matched filtering, or cyclostationary feature detection to determine
whether the spectrum resource in that specific communication channel is occupied.
1840 N. Wu et al.

Fig. 82.6 Cognitive radio circuits [31]: (a) narrowband spectrum sensing; (b) Nyquist rate
wideband spectrum sensing; (c) sub-Nyquist rate wideband spectrum sensing

In order to cognize the spectrum resource occupancy in multiple communication

channels, it is necessary to configure the operation frequency of the narrowband
receiver in a time-division multiplexing manner. The challenge in this implementa-
tion is how to achieve high receiver sensitivity to detect weak signals, while
maintaining high linearity to avoid the influence of strong interference signals
outside the communication channel. Cognitive time, implementation complexity,
and power consumption are also the key issues during the receiver design.
Another typical circuit to realize spectrum resource recognition is wideband
spectrum cognition, which can cognize the spectrum resource occupancy in multiple
communication channels at a time, resulting in improved cognitive rate [30]. It can
be further divided into an implementation based on a wideband receiver front end
and an implementation of multiple parallel narrowband receivers. The implementa-
tion based on the wideband receiver front end is similar to Fig. 82.6a, but the receiver
link supports much wider bandwidth. The receiver will receive the wideband signals
from the antenna and convert them from radio frequency to intermediate frequency
and then into digital domain by an analog-to-digital converter (ADC). After that, the
spectrum resource occupancy in multiple communication channels is simultaneously
detected by a wideband spectrum sensing algorithm such as Fourier or Wavelet
transforms. In this implementation, the receiver RF front end should cover a wide
82 New Type ICs 1841

enough frequency band and the analog-to-digital converter should have a high
enough sampling rate. In the implementation of multiple parallel narrowband
receivers, each narrowband receiver only receives the signals within a particular
communication channel and detects whether the spectrum resources in that commu-
nication channel are occupied with the spectrum sensing algorithm such as energy
detection, matched filtering, and cyclostationary feature detection, as shown in
Fig. 82.6b. Multiple parallel narrowband receivers can simultaneously cognize the
spectrum resource occupancy in multiple communication channels. Compared with
the narrowband implementation in Fig. 82.6a, the cognitive time is greatly reduced,
but the implementation complexity is significantly increased.
Furthermore, subsampling sequences that facilitate reconstruction can be used to
cognize spectrum information, based on the principle of signal sparsity or compress-
ibility in wide frequency band. This method decreases the sampling rate requirement
and reduces the hardware complexity, as shown in Fig. 82.6c, where the RF front end
is similar to Fig. 82.6a or b and not shown in the figure.

Nonvolatile Logic Integrated Circuit

Nonvolatile logic IC is a kind of logic IC based on nonvolatile devices, which has the
characteristics of no data loss on power outages. Conventional logic circuits store
data in devices such as CMOS registers and lose data when powering off. Nonvol-
atile logic integrated circuits utilize nonvolatile flip-flops (NVFF) to keep data from
being lost when power supply is off. Figure 82.7 shows a typical nonvolatile flip-flop
based on ferroelectric capacitors [32]. Its circuit structure consists of a master–slave
flip-flop and a nonvolatile memory unit. When the circuit works normally, the
nonvolatile memory unit is isolated, and the circuit functions the same as a conven-
tional flip-flop. When power outage happens, the control signal backs up the data
stored by the flip-flop to the nonvolatile memory unit. When the power supply is
restored, the data in the nonvolatile memory unit are restored to the flip-flop.
Nonvolatile flip-flops are the key units for data backup and recovery of nonvolatile
logic integrated circuits. Figure 82.8 shows a nonvolatile processor (NVP)
constructed by the abovementioned ferroelectric nonvolatile flip-flops [33].

Fig. 82.7 A nonvolatile flip-flop based on ferroelectric capacitors [32]

1842 N. Wu et al.

Fig. 82.8 A photograph of THU-1010 N nonvolatile processor chip [33]

Benefiting from the built-in nonvolatile memory units, nonvolatile logic ICs
feature zero static power consumption, high-speed/low-energy data backup/recov-
ery, and high reliability and can be widely used in a variety of low-power, high-
reliability applications.
Typical application areas include the following: (1) Energy harvesting systems:
Energy collected from the environment is characterized by intermittent supply and
large fluctuations. The use of nonvolatile logic ICs helps improve system perfor-
mance and reliability while reducing the overhead of data backup and recovery.
Energy harvesting systems based on nonvolatile logic ICs are suitable for human
health monitoring, Internet of things, security monitoring, and other fields. (2) Power
management: With the reduction of IC feature size, static power has exceeded
dynamic power and has become the main source of circuit power consumption.
Nonvolatile logic ICs have zero standby power consumption and high backup/
recovery speed, making them suitable for fine-grained power gating. (3) High-
reliability applications: Nonvolatile logic ICs have the characteristics of no data
loss on power supply failure and can cope with system reliability and security risks
introduced by power outages, so that they can be applied to fields such as finance,
military, and hardware security.
In 2007, Rohm Semiconductor designed a counter circuit based on ferroelectric
flip-flop [34], which was the first nonvolatile logic IC verified in fabricated chips. In
2012, Tsinghua University cooperated with Rohm Semiconductor to release the first
nonvolatile processor chip [33], which was designed and manufactured in 0.13 μm
ferroelectric technology and achieved data backup/recovery speed in the microsec-
ond range. In 2013, the Massachusetts Institute of Technology and Texas Instru-
ments cooperated to design a ferroelectric flip-flop with power gating [35] and
developed a nonvolatile FIR filter based on it. In the same year, Texas Instruments
82 New Type ICs 1843

released a nonvolatile processor of ARM-Cortex M0 architecture based on ferro-

electric flip-flops [36]. In 2014, Tohoku University and NEC Corporation released a
nonvolatile processor based on STT-MTJ devices [37], which achieved nanosecond-
level data backup/recovery speed. In 2016, Tsinghua University in Beijing and Tsing
Hua University in Hsinchu jointly released a nonvolatile processor based on resistive
devices [38], which had the function of adaptive data backup and recovery. With the
development of various new nonvolatile memory devices, future nonvolatile logic
ICs will develop in the direction of low power consumption, high performance, and
high integration. Nonvolatile memory devices will not only be used for data storage
in nonvolatile logic circuits, but also be used to achieve the integration of storage and
computing, which is expected to evolve into a new computing architecture.

Biomedical Chip

With the increasing demand for health care, along with the development of neural
engineering and the deepening of neuroscience research, a kind of biomedical chip
based on IC technology has emerged, which is specially used to transmit and process
electrophysiological signals such as neural electricity, electrocardiogram, or electro-
encephalogram. In the direction of the signals they transmit, the recording IC and the
stimulation IC are the two main categories of biomedical chips.
Microelectrode array (MEA) is a typical representative of a biomedical chip. It is
mainly used for recording the activity of tissue sections or cultured cells in vitro. The
chip integrates hundreds or even thousands of recording electrodes [39]; the circuit
behind each electrode contains an amplifier, a filter, and other analog front end
(AFE). When electroactive cells such as myocardial cells or neurons are covered on
the electrodes, a large number of cells’ electrical activities can be recorded at the
same time.
Another type of in vivo biomedical chip is mainly used to record EEG, EMG,
ECG, or measure impedance [40]. Its main function is to carry out pre-amplification,
analog filtering, and analog-to-digital conversion of the electrophysiological signals
extracted from the electrode [41]. Some IC or chips for the collection of electro-
physiological signals even include radiofrequency emission functions [42]. Biolog-
ical electrical signal is usually very low in amplitude. For EEG, for example, its
amplitude is usually only several to dozen microvolt. At the same time, the signal is
always disturbed by noise caused by the activity or motion of the wearer. The front-
end amplifier of this kind of special integrated chip often has high input impedance,
usually to suppress noise to back-end circuits from an organism. In the signal
transmission chain, the main function of analog filtering is to filter the noise signal
from the sensor according to the characteristics of the collected biological signal.
Usually, low-pass filtering and notch filter are used to eliminate the motion artifact
interference and power frequency noise. Analog-to-digital converter converts the
amplified and filtered signals into digital signals, which is the main component of
biomedical chips and determines the overall performance of chips to a great extent.
The common high-performance and high-precision converters used in biomedical
1844 N. Wu et al.

Fig. 82.9 Eight-channel neural recording IC dice and its appearance after package [43]

chips include SAR ADC and sigma-delta ADC. Depending on the application, the
conversion accuracy is often 12 bits or higher. At present, ADS1298 and ADS1299
have been commercially available from TI. Other chips, such as Neurosky’s
BMD101, integrate amplification with simple signal processing circuits.
Figure 82.9 shows a special eight-channel neural signal acquisition chip, whose
main function is to realize the neural signal acquisition in the implantable bladder
repair system. The main components of the chip are ADC, amplifier, and digital
interface. The slope integration via ADC for a step-by-step conversion is the core of
the system. The main advantages of this architecture are high precision, low power
consumption, and small chip area.
At present, the main problem of biomedical analog front-end chip is that the
performance has to be a tradeoff among acquisition accuracy, acquisition perfor-
mance, and power consumption. More and more applications of EEG and ECG put
forward higher and higher requirements for the precision and performance of the
chips, and meanwhile, wearable and portable devices put forward strict limits on the
power consumption. Therefore, the main goal of the design of biomedical analog
front-end chip is to improve the architecture and circuit parameters to obtain lower
power consumption and minimize the size. Of course, reliability and stability are
necessary requirements.
Some functional electrical stimulators used to regulate or repair organ functions,
such as cardiac pacemakers, deep brain stimulators, cochlear implants, artificial
retinas, and other devices, are good candidates of biomedical chips.

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New Materials Used in IC
83
Yunyi Fu, Tianli Duan, and Hongyu Yu

Contents
Diamond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1848
Graphene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
Graphene-Like Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1852
Nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
Carbon Nanotubes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
Germanium-Tin (GeSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857
Quantum Wire Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
Topological Insulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862

Abstract
Integrated circuit (IC) material technology is the important foundation of IC
technology development. The development of IC technology is accompanied
by the research and application of new IC materials. New and emerging IC
materials need to be introduced to advance IC technology. Meanwhile, the
application of new materials opens new fields for IC technology. There is a
wide range of materials for different device applications, such as logic device,
memory device, optoelectronic device, etc. This chapter mainly focuses the
emerging research materials for IC device application, such as diamond,
graphene, carbon nanotubes, nanowires, etc. The material properties, potential
applications, and recent progress of new IC materials are also addressed.

Y. Fu (*)
Institute of Microelectronics, Peking University, Beijing, China
e-mail: yyfu@pku.edu.cn
T. Duan · H. Yu
Southern University of Science and Technology, Shenzhen, China

© Publishing House of Electronics Industry 2024 1847

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_83
1848 Y. Fu et al.

Keywords
Diamond · Graphene · Nanowires · Carbon nanotube · GeSn · Quantum wire
materials · Topological insulator

Diamond

Diamond is a kind of carbon material, which belongs to allotropic material. Its

electronic orbital hybridization mode of carbon atom is sp3, its crystal structure is
cubic structure and space group Fd3m. In diamond, each carbon atom forms covalent
bonds with its neighboring four carbon atoms, and the cell is tetrahedral structure.
Carbon atoms are located at four vertices of tetrahedron. The lattice constant of the
single cell is 0.357 nm (300 K). The tetrahedral cell structure is stacked repeatedly to
form compact diamond crystal [1].
Usually, pure diamond is extremely transparent, but if it contains impurity atoms,
it can show different colors (green, yellow, brown, blue, purple, orange, etc.). Its
color depends on the type and content of impurities. Common diamond crystals are
cube, tetrahedron, octahedron, rhombic dodecahedron, and so on.
Diamond is very stable, and it is very difficult to react with other chemical
reagents at room temperature. Even at high temperature, it will not react with
hydrofluoric acid, hydrochloric acid, and nitric acid. Only when it is buried in
molten KNO3, Na2CO3, and NaNO3 melt, or when it is boiled in mixed liquid of
K2Cr2O7 and H2SO4, or when it is heated above 850
C in air, the surface of
diamond is slightly oxidized. But compared with graphite, diamond is metastable.
In vacuum or anaerobic environment, diamond will change to graphite above
1700
C. In air, the transition temperature is lower (about 700
C). The ignition
points of diamond in oxygen and air are in the range of 720–800
C and 850–1000
C,
respectively [2, 3].
Natural diamond is extremely rare. It is usually synthesized artificially. There are
two main synthetic methods: high temperature/high pressure (HTHP) and chemical
vapor deposition (CVD). The former prepared diamond is at high temperature
(>1500
C) and high pressure (>110 Pa) and with low yield; limited size of diamond
synthesized and doping is difficult. The latter decomposed methane at high temper-
ature and hydrogen, and its carbon groups could deposit on substrates or epitaxy
diamond films on heterogeneous substrates, resulting in high purity and high doping
efficiency. Moreover, wafer-scale single crystal or polycrystalline films can be
prepared, and P-type and N-type diamonds can be obtained. Figure 83.1 shows
diamond wafers [4] grown heteroepitaxially on iridium/sapphire surfaces [6].
Because of its unique molecular structure, diamond has excellent physical prop-
erties, such as optics, mechanics, acoustics, thermology, and electricity. Because the
covalent bond between carbon-carbon in diamond is very strong and four valence
electrons are saturated to form bonds, its hardness and melting point are extremely
high. The density of natural diamond is 3.15–3.53 g/cm3, the melting point can reach
3550–4000
C, and the hardness is about four times that of corundum and eight
83 New Materials Used in IC 1849

Fig. 83.1 Heteroepitaxy

growth of diamond wafers [6]

Table 83.1 Important physical properties of diamond [3]

Property Value Comparison
Mechanical hardness (GPa) 80–100 SiC:40
Thermal conductivity (W/cm K) 5–20 Ag:4.3, Cu:4.0, BeO:2.2
Fracture toughness (MPa sqrt(m)) 5.5 SiO2:1, SiC:4
Young’s modulus (GPa) 1050 SiC:440, Graphite:9
Coefficient of thermal expansion (ppm/K) 1.2 SiO2:0.5
Refractive index 2.41@590 nm Glass: 1.4–1.8
Transmissivity 225 nm-far IR –
Coefficient of friction 0.05–0.1 (in air) Teflon:0.05
Bandgap (eV) 5.4 Si:1.1, GaAs:1.43
Electrical resistivity (Ωcm) 1012–1016 A1N: 1014
Density (gm/cm3) 3.51 Si:2.32, Cu:8.89

times that of quartz; it has high refractive index (2.418@500 nm), strong dispersion
(0.044), extremely high reflectivity, and its appearance is colorful and shiny; the
transmission spectrum ranges from X-ray to microwave, except for a part of near
infrared. The diamond has a very high thermal conductivity (> 2000 wm1K1),
which is about 25 times as high as copper in liquid nitrogen temperature region and
5 times as high as copper at room temperature. The thermal expansion coefficient is
very small, 0 at 38.8
C and 5.6  10–7 at 0
C. Diamond is a wide bandgap
semiconductor with a bandgap of 5.47 eV and a very high breakdown field strength
(5–10 MV/cm), which is significantly higher than that of 4H-SiCd (3 MV/cm) and
GaN (5 MVcm). The electron’s and hole’s mobility are 4500 and 3800 cm2V1s1,
respectively. Due to the photo-phonon energy is very high (Eopt ¼ 160 meV), the
hole mobility can still reach 2000 cm2V1 s1 and 1000 cm2V1 s1 even at 400 K
and 500 K. The electron and hole saturation velocities are 0.85–1.2  107 cm/s and
(1.5–2.7)  107 cm/s, respectively [1–5]. Some physical properties of diamond are
listed in Table 83.1.
1850 Y. Fu et al.

Diamond has a wide bandgap, it has excellent optical properties, doping ability,
high carrier mobility and saturation speed, and high breakdown field strength, thus
diamond can be applied to devices working at high temperature, high power, and
harsh environment, such as Schottky-pn diode (SPND), radio frequency field-effect
transistor (RF-FET), double junction transistor (BJT), surface acoustic wave (SAW)
devices, and micromechanical systems (MEMS). At the same time, because of its
excellent thermal conductivity, it can be used as heat dissipation materials in
electronic packaging and substrate materials of chips [1, 4, 5].

Graphene

Graphene was discovered by A. Geim and K. Novoselov of University of

Manchesterin, UK. It is a single atom layer crystal of graphite with a thickness of
only 0.34 nm. It is the thinnest two-dimensional material known and can be
preserved in ambient atmosphere for a long time. The two scientists won the 2010
Nobel Prize in Physics for their discovery of graphene. Since the discovery of
graphene, scientists from different disciplines have stepped into this field to study
its molecular structure, electronic structure, physical and chemical properties, and
applications.
Graphene lattice structure is a planar hexagonal lattice or two-dimensional
honeycomb structure, as shown in Fig. 83.2a. Because of the strong C-C covalent
bond, four electrons in each carbon atom are hybridized by SP2 mode. The electrons
in unhybridized PZ orbital form π bonds, and the adjacent π bonds form large π
bonds. The electrons can move freely within the π bond. Graphene is a semicon-
ductor with zero bandgap. Its conduction band and valence band are adjacent to the
six vertices of the first Brillouin region, namely Dirac point. The conduction band
and valence band are completely symmetrical with respect to Dirac point, and their
electronic and hole properties are identical. Each carbon atom contributes a pz orbital
electron, so that the valence band is occupied completely, while the conduction band
is empty. Therefore, the Fermi plane is exactly on the plane where the conduction
band and valence band touch each other, as shown in Fig. 83.2b and c. The
dispersion relation near the Dirac point is linear, i.e., E(κ) ¼ ℏvF|κ|, where κ ¼
k  K, vF is Fermi velocity (~106 m/s), the effective mass of the electron and hole is
zero, and its behavior follows the relativistic Dirac equation. The carrier is called a
massless Dirac Fermion, as shown in Fig. 83.2d [7–9]. The doping type of graphene
is determined by the position of Fermi level EF, which is n-doped when EF is in
conduction band and p-doped in valence band.
Graphene has excellent electrical, thermal, and mechanical properties. The main
features are revealed as follows.

1. It has a unique band structure, which is usually a semi-metal with zero bandgap.
Its bandgap can be adjusted by size limitation effect or electric field. That is, the
bandgap of graphene can be opened by preparing graphene into nanoribbon
structure, or double or triple-layer graphene transistor applying voltage on its
83 New Materials Used in IC 1851

Fig. 83.2 (a) The lattice structure of graphene with two atoms A and B in each cell. (b) The three-
dimensional band structure of graphene. (c) The dispersion relationship near the Dirac point.
(d) The relationship between density of states and energy [10, 11]

back and top gate at the same time. The amplitude modulation of bandgap can
reach 0.4 eV.
2. The mean free path of carriers in graphene is close to micron scale, and the mean
free path of carriers is larger than 2 μm when the carrier concentration is
~1012 cm2.
3. It has extremely high room temperature carrier mobility (measured up to 2 
105 cm2V1s1), which is much higher than InSb (~7.7  104 cm2V1s1),
and the mobility for both electron and hole is the same.
4. Graphene has high conductivity (>6  106 S/m) and high current density
(108A/cm2), which is 2–3 orders of magnitude higher than that of aluminum
and copper conductors.
5. It has very high thermal conductivity (3080–5150 Wm1K1). The thermal
conductivity at room temperature is much higher than that of copper
(401 W m1 K1), gold (318 Wm1K1), and silver (420 Wm1K1).
6. Graphene conductor has no skin effect, and the parasitic capacitance and prox-
imity effect can be greatly reduced.
1852 Y. Fu et al.

7. Graphite has excellent mechanical properties. Graphene is harder than diamond,

its strength is 100 times higher than that of steel, its Young’s modulus is close to
1.0 Tpa, its fracture strength is about 40 N/m, and it has good elastic ductility
(which can be extended to 120%). Graphene with both rigidity and flexibility is
expected to be used in the field of flexible electronics [7–11].

At present, great breakthroughs have been made in the synthesis and transfer of
graphene. By using chemical vapor deposition (CVD) technology, a single- or multi-
layer graphene films can be prepared and transferred to any substrate surface.
Importantly, its technology is compatible with silicon-based technology. Graphene
can be directly processed by micro/nanofabrication technology (photolithography
and oxygen ion etching) to form the required shape or structure, directly forming
carbon-based electronic devices and interconnects, and even integrated circuits, the
processing technology is basically compatible with silicon-based process [9].
Graphene-based nanoelectronic devices have made significant progress [10, 11].
Based on carbon materials researches are reported for quantum dots, p-n junctions,
surface acoustic wave devices (SAW), field emission devices (from DC to HF),
photo-detection devices (photodetectors exceed 1 THz and the graphene photode-
tector is firstly applied to 10 Gbit/s high-speed optical communication in 2010), and
radio frequency graphene-based field-effect transistor (RF-GFET, cut-off frequency
reached 427 GHz). Especially RF-GFETs can work normally in extremely cold
environment (e.g., outer space). Using graphene transistor, metal inductance, and
wiring, a wafer-level graphene analog IC is fabricated one time on the wafer. Based
on the logic circuit of variable barrier graphene transistor, the logic circuits of
inverters and semi-adders are successfully developed. Carbon-based devices have
extremely high carrier mobility, lower noise, and higher power. They are expected to
be the key materials for the construction of new millimeter wave devices and
circuits. They can provide new technologies and methods for the development of
high-tech detectors, high-frequency broadband communication technology, and
high-resolution imaging technology.

Graphene-Like Materials

Graphene-like compounds are commonly referred to as two-dimensional layered

compounds similar to graphene. They are also called van der Waals crystals because
of the van der Waals force binding between layers. Sometimes they only refer to
two-dimensional single-atom layered crystals with hexagonal structure and Dirac
cone band dispersion. The rise of graphene-like research originates from graphene.
Because graphene is a zero bandgap semiconductor, the existing methods of opening
energy bandgap (e.g., making graphene nanoribbons) can significantly damage its
electrical properties (especially carrier mobility), which prompts researchers to find
new graphene-like materials such as silicene, germylene, phosphene, and MoS2,
WS2, SnS2, and BN. In recent years, the research is mainly focused on silicene and
MS2 [12–15].
83 New Materials Used in IC 1853

Silicene is a monoatomic silicon crystal film. It is a new isomer of silicon. Its

lattice structure is hexagonal honeycomb. Because it is very easy to bend, it is often
curved. Its lattice constant is not fixed and the ratio of two hybrids (sp2/sp3) is
variable. The characteristics of silicone [12–15]: (1) Compared with graphene, its
band structure is similar to that of graphene, and the Si-Si bond exhibits sp2-like
hybridization characteristics. There are π bonds and π* bonds at K point in the first
Brillouin region, i.e., Dirac cone. (2) The energy bandgap is zero, but its bandgap can
be continuously adjusted by electric field (0–1.03 V/). (3) Fermions are massless
(because the bands of conduction and valence bands are linear). (4) Silicene nano-
ribbons have a strong antioxidant capacity. In oxygen, the oxygen concentration
required to start oxidation is much higher than that required to start oxidation on
silicon surface (104 times higher). (5) There is a topological phase transition: If an
electric field is applied on the silicone nanoribbon, it will make topological phase
transition, that is, from the topological insulator to the energy band insulator, by
adjusting the electric field to the critical state, helical zero modes will occur any-
where in the silicone plane, and the region will become a quantum wire or dot
surrounded by the topological insulator energy band insulator. (6) Compatible with
the silicon-based process: Because it belongs to silicon-based materials, its process is
compatible with silicon-based process.
Although some scientists predicted the presence of silicene, it has only recently
been experimentally prepared. At present, the main preparation methods are:
(a) epitaxy growth of silicone on boride surface: first, ZrB2 (conductive ceramics)
is epitaxially grown under ultrahigh vacuum, and then (0001) ZrB2 can be epitaxied
spontaneously through annealing; (b) deposition of silicone on Ag single crystal
surface: under ultrahigh vacuum, silicene nanoribbons can be grown on Ag (001),
(011), and (111) surfaces. All the silicene nanoribbons are parallel to {Ī 10} direction
and have a width of 0.8 or 1.6 nm. The study of physical and chemical properties of
silicone materials has just begun, and various strange properties may be found,
which have potential applications in nanoelectronics [12–15].
MoS2 is a hexagonal crystal system. The single layer of MoS2 consists of three
layers of atoms: the middle layer is Mo atom layer, the upper and lower layers are S
atom layer, forming a “sandwich” layer structure. The in-plane is covalently bonded,
and the interlayer is van der Waals force bonded. The interlayer spacing of multilayer
MoS2 is 0.65 nm [16–18].
Bulk MoS2 crystals have indirect bandgaps. As the number of layer decreases, the
bandgap of the crystal changes. Single-layer MoS2 crystals have direct bandgaps,
while the bandgap of graphene-like MoS2 crystals is adjustable. With the increase of
layers, the bandgaps decrease, usually the range of change is in the range of
1.29–1.90 eV. The electron mobility of MoS2 is about 100 cm2/Vs, which is much
lower than that of silicene, but higher than that of amorphous silicon and common
organic semiconductors. At present, the main preparation methods are: mechanical
exfoliation, chemical vapor deposition, and so on.
Monolayer and multilayer MoS2 have unique crystal structure and band structure,
unique electrical, thermal, mechanical, and optical properties, and rich reserves,
nontoxic, harmless, and low price. It will have great applications in the fields of
1854 Y. Fu et al.

electronics and photoelectronics, such as light emitters, lasers, photodetectors, solar

cells, flexible display and display screen, etc. [16–18].

Nanowires

Nanowires are quasi-one-dimensional nanostructured materials. These semiconduc-

tor materials include germanium, silicon, compounds, oxides, and metals. At pre-
sent, semiconductor nanowires are mainly used in nanoelectronic devices. Their
doping types, compositions, and sizes can be controlled in synthesis, and they are
compatible with silicon-based micro/nanotechnology. Therefore, they have unique
advantages in nanoelectronic field [19–21].
The common semiconductor nanowires are Si nanowires, GaN nanowires, InP
nanowires, etc. The main preparation methods are physical evaporation (PVD) and
chemical vapor deposition (CVD). Single nanowires usually grow along a certain
crystal direction (e.g., <111>) with smooth surface, and the fluctuation of the
nanowire surface is at atomic scale. The whole nanowires are usually single crystal,
but not all semiconductor nanowires are like this, some may be bi-crystals. Some
semiconductor nanowires have defects in their microstructures, such as grain bound-
aries, stacking fault, etc. The growth and morphology of nanowires are closely
related to the above defects [20–23].
Semiconductor nanowires (Si, GaN, etc.) can be used to fabricate nano-
electronic devices, such as field-effect transistors (FETs), inverters, and light-
emitting diodes using semiconductor. Compared with carbon nanotubes, they
have more advantages in integration. It can be attributed to two reasons: first,
different from carbon nanotubes, the size and electrical properties of semiconduc-
tor nanowires can be accurately controlled in the synthesis process. Secondly, the
devices and arrays of cross-shaped semiconductor nanowires can be easily
obtained by directional assembly technology, and the devices can be integrated
in the nanoscale range. However, the integration of carbon nanotube devices is still
limited by the traditional lithography process, and the positioning of carbon
nanotubes is very difficult [21–23].
In addition to the semiconductor nanowire itself as device building blocks, the
axial and radial heterojunctions or core-shell structures of semiconductor nano-
wires provide more abundant structures for the fabrication of nanoelectronic
devices. Axial heterojunctions, such as GaAs/GaP nanowire heterojunctions, can
be obtained by controlling the composition and doping of one-dimensional nano-
wires. In addition, radial nanowire heterojunctions can also be obtained by hetero-
epitaxy growth of crystals. A typical example is the Ge/Si core-shell structure
(as shown in Fig. 83.3) [21]: First, high-quality gate oxide shell is coated on a
single-crystal semiconductor core. For example, the surface of the silicon nanowire
(core) is very easy to oxidize forming a thin layer of SiO2 by thermal oxidation or
chemical vapor deposition. The second is to prepare high-quality gate oxygen
outside the core of a single-crystal semiconductor, and then deposit the gate
electrode layer on the surface of the gate oxide. For example, heavy-doped
83 New Materials Used in IC 1855

Fig. 83.3 Schematic diagram

of core-shell structure of
semiconductor nanowires [21]

amorphous silicon layer is deposited on the surface of Si/SiOx core-shell structure

as gate electrode. The third is multilayer core-shell structure, similar to
two-dimensional semiconductor superlattice and two-dimensional electron-hole
structure, which uses interlayer to separate doping layer from effective conductive
channel (core), such as using intrinsic GaAs nanowires as core and interlayer,
separately. The coaxial core-shell structure can overcome the structural defects of
traditional gate oxygen and backgate, and can be used to design and fabricate
various high-performance coaxial nanowire devices.
Semiconductor nanowires can be assembled into cross-arrayed structure. The
assembly method is as follows: Multi-nanowires are firstly aligned in parallel by
using microfluids and PDMS microchannel template. Then, the template is rotated
to 90
; the cross-arrays can be fabricated by repeating the above process. The size
of cross-junction is small, has high integration and convenient assembly of nano-
wire cross-junctions, and it is not limited by lithography technology. By means of
assembly method, a large number of cross-shaped PN junctions can be made from
nanowires, and then various complex electronic devices can be assembled through
bottom-up technology. For example, various logic gates, such as or AND, OR and
NOT, can be fabricated by using cross-shaped PN junctions formed by p-Si
nanowires and n-GaN nanowires. A variety of logic devices ( AND, NOT, or
NOR), XOR, semi-adder, and decoder can be fabricated using PN junctions and
their arrays.

Carbon Nanotubes

The carbon nanotube (CNT) was discovered in 1991 by S. Iijima, a scientist from NEC
Corporation of Japan. Its molecular structure is a hexagonal grid structure, each carbon
atom is connected with three adjacent carbon atoms, and the carbon atoms are mainly
SP2 hybridized. It can be regarded as a coiled and seamless tube of graphene sheet,
1856 Y. Fu et al.

whose shape is determined by the diameter and helix angle, which in turn depends on
the chiral vector: Ch ¼ na1 þ ma2, where a1, a2 are unit vectors and n, m are integers.
Helix angle (θ) is the angle between chiral vector Ch and a1. According to the structure
of CNTs, CNTs can be divided into three types: armchair, zigzag, and chiral.
Single-walled carbon nanotubes (SWCNTs) have unique band structure
[24–28]. Compared with single-layer graphite, the difference is mainly in the
edge condition. Along the axis of the tube, like single-layer graphite, the wave
function satisfies the periodic boundary condition and the wave vector (k) is quasi-
continuous, but in the circumferential direction perpendicular to the axis of carbon
nanotubes, the wave vector should satisfy: kCh ¼ 2πli, where li is an integer. The
nanoscale |Ch| value results in discontinuity of the wave vector k perpendicular to
the axis of the tube. In the first Brillouin region of graphene, the value of K falls on
a set of parallel lines with spacing of 2π/|Ch|, and the valence band and conduction
band degenerate at the six vertices K of the first Brillouin region. When the parallel
line passes through K point, the carbon nanotubes are metallic, otherwise they are
semiconductor. For armchair carbon nanotubes (n, n), the curling direction (Ch) is
along the x-axis, so kx is discrete. Because kx ¼ 0 is always permissive and the
straight line of kx ¼ 0 passes through the K-point, armchair carbon nanotubes are
always metallic regardless of the value of n. For zigzag (n, 0) or helical carbon
nanotubes (n, m), it is metallic only |m-n| ¼ 3q, where q is an integer, while other
carbon nanotubes are semiconductor; one-third of all carbon nanotubes are metal-
lic. If the diameter of carbon nanotubes is very small and the bending of carbon
nanotubes is intense, the degenerate position of valence band and conduction band
(K point) will move along ky direction, resulting in small bandgap of metallic
carbon nanotubes, but this does not affect the bandgap of armchair-type metallic
carbon nanotubes.
The energy bandgap of carbon nanotubes is inversely proportional to the diam-
eter, Egap ¼ 2γ0ac-c/d (γ0 is the C-C tight binding overlap energy, ac-c is the nearest
neighbor C-C atom distance (0.142 nm), and d is the diameter of nanotubes). And the
properties of nanotube can be controlled by adjusting the diameter.
Carbon nanotubes (CNTs) have excellent electrical properties because of their
unique crystal and electronic structures: (1) high carrier mobility (>105 cm2/Vs);
(2) long mean free path of CNTs. The carriers transport in nanotube is ballistic and
no scattering with impurities and phonons is observed, in addition with low power
consumption; (3) ideal one-dimensional conductor with two sub-bands participating
in the conduction band; (4) all carbon atoms of carbon nanotubes are saturated and
bonded, so there is no interface between carbon nanotubes (channel) and gate
oxygen, such as Si and SiO2, and no special passivation treatment is needed. High
k gate dielectrics can be chosen as gate oxide; (5) high thermal stability, no
electromigration problem, and the current density can be up to 109 A/cm2. It is
two orders of magnitude higher than the corresponding metal conductors such as
aluminum and copper [25–28].
In recent years, a variety of nanoelectronic devices have been developed using
carbon nanotubes, the most typical of which are junction devices and field-effect
transistors (FETs). Intramolecular junction devices can be obtained by doping
83 New Materials Used in IC 1857

Fig. 83.4 Electron

microscopic photographs of
carbon nanotubes computers
[31]

single-walled carbon nanotubes, while rectifier diode junction devices can be

constructed by crossing semiconducting and metallic carbon nanotubes. There exists
Schottky barrier at the contact between carbon nanotubes and metal electrodes.
Carriers can cross the barrier by means of hot electron emission and tunneling.
Recently, ballistic transistors can be obtained by changing the source and drain
electrode materials, selecting high work function (5.1 eV) and metal (Pd) with good
wettability with carbon nanotubes. The open state of the transistors is metallic. The
conductance is close to quantum conductance (4e2/h) [27, 29, 30].
Breakthroughs have also been made in carbon nanotube circuits. In 2001, the
Ph. Avouris group of IBM Watson Research Center in the USA and C. Dekker
group in the Netherlands reported successively on the work of logic circuits. Carbon
nanotube transistors were used as logic elements, and various logic circuits were
assembled on the same chip using resistance-transistor logic circuits, including
inverter, NOR, static random access memory (SRAM), and ring oscillator. In 2006,
the Ph. Avouris research group developed the logic circuit of carbon nanotubes again.
Using electron beam lithography technology, six CMOS inverters with 12 p-and
n-type field-effect transistors were fabricated on a individual 18 μm long single-
walled carbon nanotubes, and five of them are used to realize the ring oscillator. In
2013, Stanford University successfully developed a carbon nanotube computer
(Fig. 83.4) using high-density carbon nanotube parallel arrays, which can count and
sort integers simultaneously and also can run 20 commercial MIPS instructions [31].

Germanium-Tin (GeSn)

As a near-infrared band optical communication medium, Si-based optoelectronic

integrated devices became a research hotspot gradually since 2004. As an indirect
bandgap semiconductor, the detecting and luminous efficiency of Si is very low. The
1858 Y. Fu et al.

bandgap of Ge is suitable for the near-infrared band. Moreover, the detecting and
luminous efficiency of Ge is higher than Si and it is compatible with Si IC process.
Therefore, the Ge-on-Si materials and devices are studied extensively.
The bandgap of Ge is quasi-direct. For increasing the occupation probability in Γ
valley, heavy doping is needed when Ge is applied to optoelectronic device. But it
will lead to strong effect of free carrier absorption. By doping a certain amount of Sn,
GeSn alloy is able to lower the bandgap of Ge, thus lowering the doping concentra-
tion and enhancing the detecting and luminous efficiency. The bandgap variation of
GeSn with Sn concentration is shown in Fig. 83.5 [32].
For GeSn alloy, the equilibrium solid solubility of Sn is less than 1%, so GeSn is
metastable when Sn concentration is more than 1%. In addition, Sn tends to separate
out from Ge, thus low preparation temperature is needed. Now the GeSn film is
prepared by MBE [33] or UHV CVD [34].
Since the bandgap of GeSn is suitable for the near-infrared band, the optoelec-
tronic devices made by GeSn can be used to emit, detect, or modulate the light of
such band.
The detection efficiency of Ge optoelectronic devices will decrease rapidly
when wave length is larger than 1550 nm, so it cannot be used for detection of
L band (1565–1625 nm) and U band (1625–1675 nm). By 2% concentration
doping of Sn, the GeSn alloy is able to detect all band, the detection efficiency of
which is ten times higher than Ge. The common GeSn optoelectronic detector is a
GeSn/Si heterojunction PiN diode, the cross-section of which is shown in
Fig. 83.6 [35, 36].
GeSn luminous devices include laser and LED, the present research focuses on
GeSn laser. Comparing with III-V compound laser, the cost of GeSn laser is much
lower. Ge laser is useless for too large threshold current. The typical GeSn laser
structure is shown in Fig. 83.7 [32].
In addition, GeSn alloy can also be applied to light modulator and quantum well
modulator.

Fig. 83.5 The bandgap

variation of GeSn with Sn
concentration. EL: bandgap of
L position; E0: bandgap of Γ
position
83 New Materials Used in IC 1859

Fig. 83.6 Two kinds of GeSn optoelectronic detectors

Fig. 83.7 The cross-section

of GeSi laser

Quantum Wire Materials

The traditional energy band theory is not suitable as the thickness of material and the
electron free path (around tens of nanometers) are comparable. Whereas, the quan-
tum mechanical properties will show up obviously and the electron energy is
discontinuous which has to be described by independent energy level.
According to the density of state (DOS) formula of quantum wires (m* refers to
effective mass of electron, ħ is Plank constant divided by two, and E refers to energy
of electron), as shown in Fig. 83.8a, the dimensions in x and z directions of the
quantum wires (QWRs) are well matched with electron free path. Thus the motion of
electrons is limited in x and z directions with quantum properties but is free to move
in y direction.
Schematic diagram on electronic state density of QWRs is shown in Fig. 83.8b.
The electron energy has separate sharp peaks in x and z direction.
QWRs include semiconductor nanowires, oxide nanowires, and carbon nano-
tubes. They are usually fabricated by V-groove which is proposed by E. Kapon [37].
QWRs are formed by molecular beam epitaxy (MBE) and metal-organic vapor
phase epitaxy (MOVPE) based on the principle of increasing growth rate of
V-grooved bottom.
Moreover, QWRs by ridge-groove and sidewalls have also been developed and
applied.
1860 Y. Fu et al.

Fig. 83.8 The quantum wire

energy equation. (a)
Schematic diagram of QWRs.
(b) Schematic diagram of
electronic state density
according to the quantum wire
energy equation

Because of T-shaped quantum wire at the edge of cleavage, growth methods such
as monoatomic step-like substrate type [38] and corrugated high-index substrate type
[39] are proposed. In particular, nanotubes are typical QWRs which are generally
produced by arc discharge method and laser ablation method.
Strong Coulomb correlation and suppression of electron scattering are the distinct
properties of QWRs, which could be used in the optoelectronic devices such as low
threshold semiconductor lasers and high-mobility field-effect transistors.
Nowadays, with the scaling of field-effect transistors (FET), many issues arise.
Such as, channel length scaling leads to drain induced barrier lowering (DIBL)
which leads to smaller threshold voltage and weaker gate control capability.
If QWRs are used as channel, the carriers are confined in the channel between
source and drain, gate control capability and carrier mobility are improved effectively.
In 2016, Science reported that carbon nanotubes have been used in one-nanometer
transistors and improve the devices characteristics [40].

Topological Insulator

According to conduction properties, materials can be divided into conductors, semi-

conductors, and insulators. Among them, the insulator can be further divided into
energy band insulator, Mott insulator, and Anderson insulator. The topological
insulator belongs to energy band insulator. When under low temperature and micro-
scale, its surface is conductive as metals due to the “topological” nature of electron
structure. The unique transport mechanism makes it a revolutionary new generation
of information material [41].
The study of electron topological states originated from a series of major exper-
imental and theoretical breakthroughs in the 1970s and 1980s. Under low temper-
ature and microscale, the two-dimensional electron gas shows obvious quantum
mechanical effects, that is, the measured value of Hall conductance can only be an
integral multiple of e2/h (e is the basic charge and h is the Planck constant). The
quantum Hall conductance is extremely stable and is hardly affected by scattering
sources such as impurities.
83 New Materials Used in IC 1861

The integer quantum hall conductance can be written as the sum of the flux of the
Berry curvature occupying the energy band in the first Brillouin zone (TKNN
number, Thouless-Kohmoto-Nightingale-den Nijs number) multiplied by the phys-
ics constant e2/h. The TKNN number must be an integer based on differential
topology. This integer is mathematically named after the famous mathematician
Shiing Shen Chern, called Chern number. The Chern number is a topological
invariant belonging to the energy band and can be used to explain the stability of
the quantum Hall current.
The integer quantum Hall effect (IQHE) has a highly stable supercurrent, but the
strong magnetic field and extremely low temperature it requires limit its application.
Searching for topological insulators that do not require a magnetic field has become a
scientific research target.
In 1988, Professor D. Haldane demonstrated for the first time a simple theoretical
model to show that a topologically nontrivial system can be realized without a
magnetic field [42], which is very instructive for subsequent research. This work is
carried out in two systems, the quantum anomalous Hall effect (QAHE) and the
quantum spin Hall effect (QSHE). However, the conditions for realizing the QAHE
are very demanding, so research in this direction is progressing slowly. Until 2010,
Xi Dai, Zhong Fang, and Shou-Cheng Zhang firstly proposed that the QAHE may
exist in the magnetically doped topological insulator film Bi2Se3/Bi2Te3 [43]. In
2013, the Qi-Kun Xue’s group observed the QAHE in the above system for the first
time [44], which caused great concern at home and abroad. In 2016, American
scientists David Thouless, Duncan Haldane, and Michael Kosterlitz were awarded
Nobel Prize in Physics for their contributions in topological phase transition and
topological material theories.
Compared with the QAHE, the research on the QSHE has made a breakthrough.
The earliest theoretical model of Z2 topological insulators was built based on
graphene. However, unfortunately, this theoretical model cannot be realized exper-
imentally, since the spin-orbit coupling effect of carbon atoms is too weak. This is
also the reason why scientists began to search for QSHE in materials composed of
heavy elements. In 2006, Shou-Cheng Zhang’s research group built a
two-dimensional model based on the energy band of HgTe to generate the Z2
topological phase. According to this model, they predicted that the spin-orbit
coupling of CdTe/HgTe/CdTe quantum wells is strong enough to produce QSHE.
This prediction was confirmed by M. König et al. in 2007. However, due to the
complexity of the quantum well structure, it is desirable to search for
two-dimensional topological insulators in intrinsic materials.
Another advancement of topological insulators is the discovery of three-
dimensional Z2 topological insulators. The earliest observed three-dimensional
topological insulator is Bi1-xSbx, a semiconductor alloy with strong spin-orbit
coupling. However, the Bi1-xSbx series are inconvenient to prepare because they
are alloys with small bandgap and complicated structures. Later discovered Bi2Se3
and Bi2Te3, which belong to the second-generation three-dimensional topological
insulators, possess many better properties and thus have more application
potential [45].
1862 Y. Fu et al.

Fig. 83.9 Landmarks during development of topological insulators

At present, China leads the world in the field of topological insulators. Although
topological insulators possess broad application prospects, searching for more topo-
logical insulator systems and increasing their operating temperature are still the
targets of researchers. Figure 83.9 lists landmarks during development of topological
insulators.

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45. H. Zhang et al., Nat. Phys. 5, 438–442 (2009)
Advanced IC Manufacturing Processes
84
Hanming Wu, Jesse Jen-Chung Lou, Hong Xiao, Yimao Cai, and
Yuancheng Yang

Contents
Low K Dielectric and Air Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
Plasma Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
Nanoimprint Lithography (NIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
Directed Self-Assembly Lithography (DSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1870
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1872

Abstract
MOSFETs continue scaling following the Moore’s law in order to improve device
performance at reduced power and cost. The scaling has driven the integrated
circuit (IC) industry toward a number of major technological innovations espe-
cially in advanced IC manufacturing processes. This chapter introduces some key
IC processes including the low K dielectric and air gap for the interconnect
technology, plasma doping process for conformal doping, and ultra-shallow
doping. The new lithography technologies of nanoimprint lithography and
directed self-assembly lithography for nanoelectronic device fabrication are
briefly introduced. The characteristics and their application of the advanced
processes are addressed.

H. Wu (*)
School of Micro-nanoelectronics, Zhejiang University, Hanzhou, China
e-mail: hanmingwu@zju.edu.cn
J. J.-C. Lou
School of Software and Microelectronics, Peking University, Beijing, China
Institute of Microelectronics, Peking University, Beijing, China
H. Xiao
KLA-Tencor, Milpitas, CA, USA
Y. Cai · Y. Yang
Institute of Microelectronics, Peking University, Beijing, China

© Publishing House of Electronics Industry 2024 1865

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_84
1866 H. Wu et al.

Keywords
Low K dielectric and air gap · Plasma doping · Nanoimprint Lithography (NIL) ·
Directed Self-assembly Lithography (DSA)

Low K Dielectric and Air Gap

In integrated circuit (IC), millions of transistors are connected by conductor lines,

in which a dielectric constant k is proportional to the effective capacitance. To
increase the frequency in new technology node demands the lower RC delay. So to
lower the k value is one of the key technologies in IC industry. Since the lower k
value results in the lower capacitance, the frequency can then go the higher.
Therefore, it is necessary to adopt the low k materials to replace SiO2 and
minimize the parasitic capacitance that is proportional to k value [1]. It is obvious
that low k materials (k < 4) and ultra-low k material (k < 2) would play an
important role in future ULSI manufacture, especially for high-speed and
low-power products.
Doping fluorine is the most effective way to reduce k value at the current
industry. Many materials’ k value can be significantly decreased by fluorine
doping. The k value depends on the dopant ratio of fluorine. Porous dielectric is
the only one material that can be applied to ultra-low k and becomes a main stream
ILD material in devices of nanoelectronics and microelectronics. The porous low
k material is a dielectric material that contains air gaps. The material can be
usually fabricated through spinning on or chemical vapor deposition. The porous
is created by means of either gasification or designed solution. In other words, the
k value depends on the micro-bubble in the low k materials. The lower k value
means there are more bubbles in the material. It is known that the mechanical
property becomes worse when the number of bubble goes up. The limit value for k
is one in vacuum. It seems reasonable to fabricate a big air gap between two
conductor lines and make the k close to one, the so-called “air gap technology”
[2]. In manufacture, the “hand in the air” property of CVD process should be well
designed to make the air gap in the thin film with the lowest k value. This
technology is successfully used in Intel 14 nm product and contributes 17%
performance improvement. More application is expected in more advanced tech-
nology nodes in future.

Plasma Doping

Plasma doping is a dopant introduction technology primarily based on plasma

immersion ion implantation (PIII) process. PIII is a low-cost method of ion implan-
tation and has great potential for the fabrication of IC devices. It has a relatively
84 Advanced IC Manufacturing Processes 1867

Fig. 84.1 SEM image of a

conformally doped deep
trench by PIII process with
dopant gas BF3. Wafer bias
was
10kv and chamber
pressure was 5 mTorr [3]

divergent ion implantation angle under the pressure range of mTorr; therefore,
conformal doping and ultra-shallow doping can be performed. Notably for high
aspect ratio deep trench structures, PIII technology can achieve a very uniform
distribution of doping concentration around the side walls and bottoms of deep
trench structures. It can also form an ultra-shallow junction along the top surface,
side walls, and bottom surface of trenches as shown in Fig. 84.1 [3]. Traditional ion
implantation technology cannot reach these advantages. PIII technology is increas-
ingly used in various areas of semiconductor and metallurgical industries. IMEC and
Intel have adopted PIII processes in the 32 nm planar CMOS structure to form ultra-
shallow junctions. Furthermore, the PIII process is also adopted below the technol-
ogy node of 22 nm to dope multiple gates of FinFET at a relatively divergent ion
implanted angle.
With proper reaction gas (e.g., BF3, B2H6, PH3, and H2) being introduced,
high-density plasma is generated in the reaction chamber through an ICP or ECR
system. The wafer is in series with a negative voltage pulse modulator which
provides a pulse with minimum rise and fall times in voltage as compared to the
pulse duration for fully accelerating ions with entire bias voltage while
implanting the wafer surface. As the wafer is immersed within the high-density
plasma, it will be bombarded by ions at a large divergent angle. The desired
junction depth can be obtained by controlling the negative voltage of the pulse
modulator which determines the energy of the implanted ions. The ion dose can
be determined by adjusting the period and number of pulses. As shown in
Fig. 84.2, since the pulse voltage has formed a negative electric field that can
attract positive ions on all surfaces of the wafer, positive ions can be bombarded
onto the upper surface, side wall surface, and bottom surface of the high aspect
ratio deep trench to uniformly form a conformal doping distribution. Traditional
ion implantation machines can precisely select the required single ion source and
1868 H. Wu et al.

Fig. 84.2 Ion implantation driven by the negative bias

ion energy by controlling the magnetic field intensity. However, the PIII gener-
ated by ICP or ECR cannot screen the required single ion source. For example,
multiple ions such as BFþ þ2 + +2
2 , BF2 , BF , BF , etc., can be simultaneously pro-
duced from BF3, resulting in energy contamination of ion implantation.
PIII presents the following advantages: (1) it can generate a high implantation
flux to reduce the time needed for heavy doping processes; (2) it can produce low
energy and high concentrations of ion sources to form ultra-shallow junctions and
reduce ion implantation-induced crystal defects; (3) it can achieve a uniform dose
rate with good conformity to optimize the performance of 3D FinFET or deep trench
structure features; (4) PIII system design is simple and the running cost is econom-
ical; (5) PIII is a low-temperature with high throughput process.
To reiterate, PIII technology has been applied to the doping process for CMOS
with the technology node below 22 nm. For the hydrogenation of polysilicon TFT
panel process, PIII has been used to decompose H2 to form high concentrations of
hydrogen radicals to passivate interfacial defects in the grain boundary, increas-
ing the mobility of carriers and improving the performance of TFT transistors [4].
In SmartCut’s SOI wafer preparation, PIII replaces conventional hydrogen ion
implantation to improve the productivity of SOI wafers and reduce production
costs [5]. In addition, oxygen plasma immersion ion implantation (O-PIII) has
also been applied in the dental implant technology. A TiO2 oxide layer can be
grown on the surface of titanium through the O-PIII process, which can increase
the adhesion between the dental implant material and bone forehead while also
improving the hardness of the titanium [6].
84 Advanced IC Manufacturing Processes 1869

Nanoimprint Lithography (NIL)

The nanoimprint lithography is also known as nano-scale print. This technology was
proposed by Stephen Chou, Professor of Princeton University. This technology can
transfer the micropatterns from the template to silicon wafer. On the template, there is
premade nano-scale pattern. While on the silicon wafer, there is polymer layer on the top
surface. By means of high temperature and high pressure, the patterns on the template
are transferred to the wafer with the same scale. This process accuracy only depends on
the template resolution, instead of the limitation of physical wavelength. Because there
is no wavelength limitations, NIL technology can support to fabricate the patterns with
CD smaller than 5 nm. The process cost is lower and efficiency higher than conventional
lithography because there are no mask and lithography equipment costs. Besides, there
is a large application scope that covers nano-device, biochip-lab, micromixture and
microreactor, ultra high-density memory, mico-optical device, etc.
There are three kinds of NIL, i.e. Heat enhanced-NIL (HE-NIL) or thernoplastic
NIL (T-NIL) include the following processes: (a) mold fabrication: a designed
accurate pattern is formed by using e-beam or some other technologies on Si or
SiO2; (b) imprint: some thermoplastic polymer, which is heated to a criteria glass-
transition temperature, is applied to cover entirely wafer. The stamp-like imprint is
conducted with the mold. Hereafter, polymer is cooled down to below the glass-
transition temperature and the stamp is removed; (c) pattern transfer: the selected
area is removed by etch process.
Photo-NIL (P-NIL) is based on UV curable polymer technology. The process
flow is quite similar to HE-NIL, but the process is under room temperature while
hardening by UV light. (a) Mold fabrication. Instead of Si or SiO2, quartz is
preferred material because UV can go through. The designed pattern is fabricated
by e-beam or other technology; (b) UV-sensitive resist covers the whole wafer;
(c) apply the mold onto the wafer and expose the wafer to UV light and harden the
resist; (d) pattern transferred by plasma etch or other etch technologies.
Recent literature indicates that the P-NIL technology is developed rapidly by
means of flash imprint. Thereafter, the resolution is significantly increased.
Micro-contact NIL (M-NIL) process flow: (a) Mold fabrication: it is similar to
two other MIL technologies; (b) imprint: the mold needs to be immersed in mer-
captan reagent before imprint. The imprint process makes the mercaptan react to
golden layer on substrate to form self-assembling single molecular layer that suffi-
ciently resist the following etch process; (c) pattern transfer: wet etch is applied to
remove the area that is not covered by golden layer.
The advantage of the M-NIL is quick, low-cost, and no cleaning environment
required. Also, there is no requirement to the flatness of the wafer surface. The
technology can be expended to different materials surfaces. The disadvantages are
the wet etch process usually causes the CD not as narrow as dry etch. However, this
negative effect can be controlled only by process optimization, including the chem-
ical concentration distribution on the mold.
1870 H. Wu et al.

Directed Self-Assembly Lithography (DSA)

Directed self-assembly lithography is an enhancement method of the existing lithog-

raphy technology which guide “photoresists” (mostly “block copolymers,” BCPs) to
self-assemble high-density pattern arrays by substrate pre-patterning. As a result, the
pitch of the optical lithography pattern can be further reduced.
DSA technology combines the advantages of image controllability of optical
lithography and high-density pattern arrays of self-assembly, and it is compatible
with 193 nm immersion lithography and is expected to push it to the limit.
Therefore, it is a promising candidate for the sub-10 nm technology nodes.
Unfortunately, however, DSA faces a big challenge of high defect density
(Fig. 84.3).
As a self-assembled material compatible with semiconductor processes,
BCP is formed of two or more chemically distinct and thermodynamically
incompatible chain blocks which are connected by covalent or supramolecular
bonds. The self-assembly of BCPs is a phenomenon that after a heat treatment,
the originally disordered BCP film spin-coated on a substrate can phase-separated
to form a periodic pattern. Taking the A–B diblock copolymer system as an
example, the volume fraction of the block A determines the final self-assembled
phase such as spherical, columnar, dendritic, and sheet-like, as shown in
Fig. 84.4 [8].
A nanowire arrays with a half pitch about 12 nm, which breaks through the
resolution. Limit of the 193 nm immersion lithography can be obtained by selecting
a BCP system with a suitable block length, such as poly(styrene-b-methyl methac-
rylate) (PS-b-PMMA) [9].

Fig. 84.3 SEM images of lamellae-forming PS-b-PMMA films that are (a) self-assembled on
chemically neutral substrates and (b) directed to assemble on striped chemical patterns [7]
84 Advanced IC Manufacturing Processes 1871

Fig. 84.4 Schematics of thermodynamically stable diblock copolymer phases. The A–B diblock
copolymer, such as the PS-b-PMMA molecule represented at the top, is depicted as a simple
two-color chain for simplicity. The chains self-organize such that contact between the immiscible
blocks is minimized, with the structure determined primarily by the relative lengths of the two
polymer blocks (fA) [8]

Although the conventional BCP self-assembly is able to achieve ultra-high-

density patterns, it cannot be directly applied to the semiconductor process because
the pattern is random and uncontrollable (typically fingerprint-like). Therefore, the
self-assembly directional technology has been proposed to overcome these chal-
lenges. By pre-patterning the substrate, the BCPs can be guided to form pattern
arrays with uniform orientation during the self-assembly process. There are two
main directing methods – the structure-limited direction (grapho-epitaxy) and the
chemically selected direction (chemo-epitaxy) [9]. In grapho-epitaxy, trenches
with a certain orientation and a certain width are formed on the substrate by
photolithography, so that the BCPs are self-assembled according to the orientation
of the trenches under the limitation of sidewalls, as shown in Fig. 84.5a. In chemo-
epitaxy, a self-assembled region with a certain orientation is defined by optical
lithography on a material that can selectively adsorb BCPs, thereby realizing the
orientation of BCP self-assembly, as shown in Fig. 84.5b.
1872 H. Wu et al.

Fig. 84.5 Process flow of (a) grapho-epitaxy and (b) chemo-epitaxy [9]

References
1. H. Xiao, Introduction to Semiconductor Manufacturing Technology (Prentice Hall, Columbus,
2001)
2. Y. Liu, H. Wu, Air gap isolation and fabrication method, Patent number: ZL02118928.5, 2013-
11-12
3. X.Y. Qian, N.W. Cheung, M.A. Lieberman, et al., Nucl. Instrum. Methods Phys. Res. B55,
898–901 (1991)
4. I.F. Husein, S. Qin, Y.Z. Zhou, et al., Nucl. Instrum. Methods Phys. Res. B 121, 226–230 (1997)
5. F.J. Henley, M.I. Current, A new SOI manufacturing technology using atomic layer cleaving, in
Semiconductor Fabtech, 12th edn., (2002), pp. 201–205
6. C.H. Yang, Y.T. Wang, W.F. Tsai, et al., Clin. Oral Impl. Res 22(12), 1426–1432 (2011)
7. J. Shengxiang, W. Lei, L. Chi-Chun, et al., Prog. Polym. Sci. 54-55, 76–127 (2016)
8. S.B. Darling, Prog. Polym. Sci. 32(10), 1152–1204 (2007)
9. G. Roel, D.P. Rincon, S. Arjun, et al., J. Photopolym. Sci. Technol. 26(6), 779–791 (2013)
New Technology in Integration
and Interconnection 85
Zheyao Wang and Xue Feng

Contents
3D Interconnect Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874
TSV-Based 3D IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875
On-Chip Optical Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878

Abstract
Three-dimensional (3D) integration is a new integration technology that verti-
cally stacks many layers of chips and electrically connects the layers using
through-silicon-vias (TSVs), improving the chip integration density and reducing
the power consumption. 3D integration has been emerging as a key technology
for integrated circuit (IC) industry and received great attentions. TSVs process
technology is used to form the 3D integrated structures. On-chip optical inter-
connect is developed to achieve data transmission on a large-scale IC chip with
the photonic integrated circuit, aiming to break the capacity bottleneck of the
current copper-based interconnection technology. This chapter introduces the
fabrication process, structure, and main advantages of TSVs, 3D integration,
and on-chip optical interconnect technology. The future develop trends of these
technologies are also addressed.

Keywords
3D interconnect · TSV-based 3D integration · On-chip optical interconnect

Z. Wang (*)
Institute of Microelectronics, Tsinghua University, Beijing, China
e-mail: z.wang@tsinghua.edu.cn
X. Feng
Department of Electronic Engineering, Tsinghua University, Beijing, China

© Publishing House of Electronics Industry 2024 1873

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_85
1874 Z. Wang and X. Feng

3D Interconnect Technology

Three-dimensional (3D) interconnects, also called vertical interconnects or through-

silicon-vias (TSVs), are interconnects that pass through the whole thickness of a
wafer/chip to electrically connect the devices on the two sides of the wafer. TSVs are
mainly used in 3D integrated structures to route the electrical signals between
neighboring chips.
Figure 85.1 shows the configuration of a typical copper (Cu) TSV. It consists of a
Cu plug, a dielectric insulator, and a combination of an adhesion layer/a diffusion
barrier/a Cu seed layer sandwiched in-between the Cu plug and the insulator.
Cu TSVs can be fabricated with various manufacturing processes [1], based on
the application needs. Typical Cu plug-based TSV manufacturing process is as
follows: After the IC fabrication processes are competed, deep reactive ion etching
(DRIE) is employed to etch deep blind vias in the IC wafers. After a conformal
silicon dioxide insulator is deposited on the via sidewalls normally by subatmo-
spheric chemical vapor deposition (SACVD), a thin adhesion layer, a thin diffusion
barrier, and a thin Cu seed layer are sequentially deposited on the insulator by PVD.
Then super-conformal Cu electrodeposition (electroplating) is used to fill the deep
vias with Cu plugs. After the Cu overburdens on the wafer surfaces are removed and
planarized by chemical-mechanical polishing (CMP), the wafer is temporarily
bonded with a carrier wafer. The device wafer is then thinned from the backside
by mechanical grinding/polishing to expose the Cu plugs, followed by dry etching of
the wafer, depositing a planar insulator, and etching the insulator on the ends of the
Cu plugs. Finally, the carrier wafer is de-boned after the device wafer is permanently
bonded onto another device wafer.
With the limits of mechanical strength, manufacturability, and heat dissipation,
TSVs should have a proper aspect ratio such that the chip sizes that are consumed by
the TSVs are minimized. Typically, TSVs should have an aspect ratio in the range of

Fig. 85.1 Configuration of a

typical TSV
85 New Technology in Integration and Interconnection 1875

5:1–10:1; lower aspect ratios need either thin wafers that suffer from poor strength or
large TSV diameters that consume large chip areas, whereas higher aspect ratios
significantly impose the technical difficulty and cost for TSV fabrication.
The technical challenges in fabricating high aspect ratio TSVs lie in depositing
conformal insulators and defect-free adhesion layers/diffusion barriers/Cu seed
layers, as well as super-conformal filling of Cu plugs in high aspect ratio blind
vias with fast rates and free of void formation. Conformal SiO2 insulators in high
aspect ratio blind vias can be deposited by SACVD using tetraethoxysilane
(TEOS) þ ozone (O3) at around 400  C, which can achieve conformality more
than 50% at blind vias with aspect ratios up to 10:1 while maintaining good
deposition rates and acceptable dielectric properties. Deposition of adhesion
layers/diffusion barriers/Cu seed layers are implemented by ionized PVD (iPVD),
which can deposit continuous and defect-free thin metal layers in blind vias with
aspect ratios up to 10:1. Super-conformal Cu filling is necessary to achieve high
filling rates and void-free Cu plugs, which depends on electroplating baths with
complex additives such as accelerators, inhibitors, and levelers, as well as proper
electric current forms such as pulse periodical reverse currents. The complex addi-
tives and the current forms allow blind vias with aspect ratios up to 10:1 and even
higher to be filled without void formation.
The most concerns in 3D and TSV applications include the heat dissipation,
thermomechanical reliability, fabrication complexity and compatibility, cost, and
electromagnetic compatibility. To improve the reliability, cost, and manufacturabil-
ity, various conductor and insulator materials as well as TSV configurations have
also been developed. For example, heavily doped polysilicon, silicon, tungsten,
nickel, or carbon nanotubes (CNT) have been used as TSV conductors [2, 3], and
polymers and air gaps have been used as insulators [4–6].

TSV-Based 3D IC

TSV-based 3D integration is a technology that vertically stacks many layers of chips

and electrically connect the layers using TSVs, such that the third dimensions
(vertical direction) can be employed to improve the integrity, reduce the power
consumption, minimize the chip sizes, and improve the functionality powered by
heterogeneous integration [7–9], as shown by Fig. 85.2. TSV-based 3D integration
was initiated since the end of the 1980s by several institutions including Tohoku
University, ASET Japan, Fraunhofer IZM, IMEC, MIT, IBM, et al. Currently, a large
variety of IC products such as CMOS image sensors, MEMS sensors, FPGA,
memory, and processors have adopted TSV-based 3D integration technology, and
it has been emerging as a key technology for IC industry to maintain the technology
advances.
TSV-based 3D integration needs the following fabrication technologies extra to
IC fabrication, such as TSV fabrication, wafer thinning, wafer temporary bonding,
and permanent bonding. A typical 3D integration involves: (1) deep hole etching in a
device wafer; (2) depositing insulators, adhesion layers, diffusion barriers, and Cu
1876 Z. Wang and X. Feng

Fig. 85.2 Schematic illustration of TSV-based 3D integration of chips

seed layers on the sidewalls and the bottom of the holes; (3) filling the holes with Cu
plugs using electrochemical deposition; (4) bonding the device wafer with a carrier
wafer after fabricating RDLs and bonding metal pads on the device wafer; (5) thin-
ning the wafer backside and etching back to expose the Cu plugs from the backside
of the device wafer; (6) fabricating dielectric insulator, RDLs, and bonding metal
pads on the wafer backside; and (7) permanent bonding the device wafer with
another device wafer after aligning, followed by de-bonding the carrier wafer.
It should be noted that various fabrication sequences could be employed for
specific applications, and according to the TSV sequence relative to the CMOS
processes, 3D integration can be classified into three categories, via-first, via-middle,
and via-last [10]. Each category has its own features and advantages and is applica-
ble to different applications. For example, via-middle technology can achieve small
diameter and high aspect ratio TSVs but is only suitable for IC manufacturers;
instead, via-last technology can be adopted by outsourced assembly and test
(OSAT) companies but can offer only large diameter and low aspect ratio TSVs.
The main advantages of 3D integration include:

1. Reduce the length of interconnects: 3D integration is able to shorten the total

length of the interconnection, such that the performance can be improved by
reducing the interconnect delay and the power consumption can be minimized by
avoiding the use of huge number of relays.
2. Improve the data transfer rate: High-density TSVs can improve the data transfer
rate significantly. For example, the data transfer rate of HBM2 that uses more than
5000 TSVs between four layers of DDR4 DRAM chips reaches as high as
256GB/s, which is more than seven times higher than that of DDR5.
3. Reduce the chip areas: Integration in the vertical direction can remarkably reduce
the chip areas with the same integration. For example, HBM saves PCB areas as
85 New Technology in Integration and Interconnection 1877

Fig. 85.3 Mass products using TSV or 3D integration technologies (Yole Development)

high as more than 90% while achieving a 60% improvement in bandwidth and
50% reduction in power consumption.
4. Improve the integrity: 3D integration is able to improve the integrity by stacking
multiple chips without the need of continuous shrinkage in critical dimensions.
For example, 3D stacking DRAM or NAND flash has boosted continuous
increase in integrity.
5. Allow multifunctions powered by heterogeneous integration of different technol-
ogies: The multi-chips to be integrated can be fabricated by different technologies
and even on different substrate materials, so that RF, optoelectronic devices,
MEMS, sensors, memory, and processors can be integrated vertically [9].

These attractive advantages make 3D integration wide applied in various areas,

and since Toshiba batch produced the first TSV-involved CMOS image sensor in
2008, 3D and TSV technologies have been widely used to develop mass-produced
CMOS image sensors, MEMS and sensors, DRAM, flash, power devices, RF and
wireless chips, as well as logic and memory integration, as shown in Fig. 85.3 [11].
With the fast development in the industrial chain, 3D integration will find many other
applications in emerging areas such as artificial intelligence, 5G communications,
auto driving, data and cloud centers, as well as many others [12].

On-Chip Optical Interconnect

On-chip optical interconnect is also known as intrachip optical interconnect. It refers

to achieve data transmission on a large-scale integrated circuit chip with the photonic
integrated circuit, which includes light generation, modulation, transmission, and
1878 Z. Wang and X. Feng

detection modules. The research goal is to tackle the capacity bottleneck of the
current copper-based interconnection technology in terms of interconnect density,
energy consumption, clock and signal timing, as well as interconnect latency
[13, 14].
Due to the bosonic nature, photons are much more predominant than electrons to
carry information, especially in very short distance interconnection. Firstly, light
wave is a kind of electromagnetic wave with higher frequency. Thus, it can support
higher transmission rate than copper wire since the cross talk and reflection related to
modulation rate can be omitted with high-speed modulation (tens of GHz). Mean-
while, due the parallel characteristics of light wave, data transmission of multiple
channels can be supported simultaneously in the same optical transmission link.
Thus, an optical transmission link could achieve higher connection capacity with
lower power consumption. Furthermore, the transmission latency of an optical
transmission links can be much lower than that of copper wires since there is no
the restrictions of RC relaxation process in optical fiber or waveguide [13–15].
International Technology Roadmap for Semiconductors (ITRS) predicts that optical
interconnection technology will replace copper wires to achieve global interconnec-
tion within multicore processors.
The research of on-chip optical interconnection based on silicon optoelectronic
devices can be traced back to R.A. Soref’s pioneering work in the 1980s. Since then,
researchers have been aiming at the integration of photonic devices and electronic
devices on the same chip. The whole research has witnessed the stages of proofs of
principle, discrete devices, hybrid integration, and is now moving towards mono-
lithic integration and heavily integrated electronic/photonic circuit [17].
Since 2008, the research of on-chip optical interconnection has become a hot
topic. Famous microelectronics giants, including Intel, IBM, Sun Microsystems,
NEC, and HP, have carried out intense research on this topic [16]. In 2015, IBM, in
collaboration with the University of California, Berkeley, and MIT, has demon-
strated the first processor chip with optical interconnection [18]. Seventy million
transistors and 850 photonic devices have been fabricated on a 3 mm  6 mm silicon
substrate by 45 nm standard CMOS process. Logical operation, storage, and optical
interconnection functions have been achieved simultaneously on a single chip.

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Modeling and Simulation of Nano-devices
86
Fei Liu, Yijiao Wang, Lang Zeng, Gang Du, and Xiaoyan Liu

Contents
Technology Computer-Aided Design (TCAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882
Monte Carlo Simulation for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
Quasi-ballistic Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
Nonequilibrium Green’s Function (NEGF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886
Molecular Dynamics Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887
First Principles Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
Density Functional Theory (DFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889
Atomic Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890

Abstract
Modeling and simulation of nano-devices can be used to study and predict the
performance of the nanoscale devices and play an increasingly important role in
understanding the working mechanisms of devices and improving their perfor-
mance. Since the MOSFET device size shrinks to nanoscale, the performance of
nano-devices is increasingly affected by various quantum effects and nanoscale
material properties. Quantum theoretical simulation methods based on quantum
effects have been developed to research the new nano-devices. This chapter
describes several modeling and simulation methods of nano-devices, including
Monte Carlo simulation, nonequilibrium Green’s function (NEGF), molecular

F. Liu · G. Du
Institute of Microelectronics, Peking University, Beijing, China
Y. Wang · L. Zeng
Institute of Microelectronics, Beihang University, Beijing, China
X. Liu (*)
Silicon Storage Technology Inc. (SST), Shanghai, China
Institute of Microelectronics, Peking University, Beijing, China
e-mail: liuxiaoyan@pku.edu.cn

© Publishing House of Electronics Industry 2024 1881

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_86
1882 F. Liu et al.

dynamics simulation, first principles method, density functional theory, and

atomic device simulation. The basic principle of simulation methods and appli-
cation potential are briefly introduced.

Keywords
Technology computer-aided design (TCAD) · Monte Carlo simulation ·
Nonequilibrium Green’s function (NEGF) · Molecular dynamics simulation ·
Quasi-ballistic transport · First principles method · Density functional theory ·
Atomic device simulation

Technology Computer-Aided Design (TCAD)

Technology computer-aided design (TCAD) mainly refers to semiconductor process

simulation and device simulation, which is a branch of EDA (electronic design automa-
tion) technology [1]. TCAD can be divided into three levels from the perspective of
function: the bottom level is process simulation, such as ion implant and diffusion, etc.;
the intermediate level is device simulation, from which electrical properties, such as
transfer characteristics, can be obtained based on basic physical characteristics; and the
top level is the establishment of compact model, which means extracting parameters for
the compact model from the device simulation results and apply them to the subsequent
circuit simulation. Well-known commercial TCAD tools include Sentaurus by Synopsys,
Athena and Atlas by Silvaco, and Csuprem and APSYS from Crosslight Software.
TCAD originated in the late 1960s and 1970s and was mainly used for the
analysis of bipolar transistor. In the mid-1980s, field effect transistors gradually
became the mainstream of digital integrated circuits due to their excellent miniatur-
ization and lower power consumption. It was during this period that TCAD was
greatly developed. One-dimensional process simulation and two-dimensional device
simulation were indispensable auxiliary work for device reduction and design. In the
era of CMOS, two-dimensional process simulation was closely combined with
device simulation, and TCAD had once again achieved a revolutionary develop-
ment, laying a foundation for all kinds of TCAD tools today.
At present, at the process simulation level, mainstream commercial software can
complete the simulation of a variety of standard process, such as ion implantation,
diffusion, oxidation, etching deposition, lithography, CMP, SOI, etc., and even inter-
connections. In the aspect of device simulation, with the introduction of multi-gate
devices, three-dimensional (3D) simulation becomes dominant. A three-dimensional
device structure and its grid layout generated by TCAD are shown in Fig. 86.1.

Fig. 86.1 3D device

structure and its grid layout
generated by TCAD
86 Modeling and Simulation of Nano-devices 1883

For device-level simulation, users can conduct electrical simulation based on

either self-defined device structure or previous process simulation. With continuous
reduction of the feature size of devices, quantum effect has become more and more
serious, which is clearly reflected in the device simulation. At the beginning,
classical drift diffusion model was adopted with quantum correction model, and
then semiclassical Monte Carlo engine and Poisson-Schrodinger engine are devel-
oped. The simulation results become more and more accurate but time-consuming.
For compact model establishment, device simulation results can be used to extract
parameters for compact models, such as widely used BSIM, and run SPICE simu-
lations. Users can also choose to use mix-mode to build a small-scale circuit, like
SRAM, to run circuit simulation directly from device level.

Monte Carlo Simulation for Device

All macroscopic observables in physics can be considered as the statistical average

of the corresponding microscopic quantities. For a system of identical particles, the
state of the ensemble can be described by a single particle distribution function. The
Boltzmann transport equation is a dynamic equation used to describe how the
distribution function changes with time in the external action field (electric field,
magnetic field, temperature field, etc.) and is one of the most important equations in
nonequilibrium statistical mechanics. For quasi-classical transport, solving the
Boltzmann equation and obtaining the distribution function of carriers is an impor-
tant approach to obtain the transport properties of carriers in semiconductor mate-
rials. The Boltzmann equation is a complex integral-differential equation, which is
difficult to solve directly. In fact, the existence and uniqueness of the Boltzmann
equation solution are still not well solved.
Monte Carlo simulation for device [2–4] is a method of numerical integration
using probability and statistics, and is a statistical method for directly solving the
Boltzmann equation. Using the Monte Carlo method, the movement of particles in
real space and k space at any time can be tracked, by dividing the motion process of
particles into two processes of free flight and scattering. In the Monte Carlo method,
the motion of carriers is decomposed into a series of free flight and scattering
processes, and is repeated until the carrier moves for a long enough time to achieve
the convergence of the state of the entire system. The final distribution function can
be obtained by counting the number and state of carriers in each phase space. The
essence of the Monte Carlo method is to handle stochastic processes with random
numbers, for the process associated with scattering can be represented by random
numbers. The scattering process in semiconductor has mechanisms such as ioniza-
tion impurity scattering and lattice scattering, the correlation of which one electron
energy and wave vector severely exacerbates the complexity of Monte Carlo
processing.
Monte Carlo device simulation method is an effective method to simulate nano-
scale semiconductor devices with unsteady-state transport properties. The quantum-
corrected Monte Carlo device simulation method can be used to simulate device
1884 F. Liu et al.

characteristics associated with quantum tunneling transport. The Monte Carlo device
simulation method is reliable and intuitive in calculating carrier transport, so it has
been widely used in the simulation of nanoscale semiconductor devices and gradu-
ally been one of the standard methods for studying nanoscale semiconductor
devices [5].
Directly solving the Boltzmann transport equation without any assumptions is the
advantage of the Monte Carlo method, which can accurately describe transport
phenomena in micro- and nanoscale devices and consider the effects of various
scattering mechanisms conveniently. However, its shortcoming is the large amount
of calculation. Due to a statistical method based on stochastic process, the intrinsic
noise is large, and it is difficult to give the subthreshold characteristics of the device.

Quasi-ballistic Transport

With the continuous development of integrated circuit technology, the number of

transistors integrated on a single chip has reached more than ten billions. At the same
time, the research work has also reached below 5 nm which is the physical limit of
the device channel length. In such a small-scale device, the nature of carrier transport
changes from the original drift diffusion to the quasi-ballistic transport.
In semiconductor devices, carriers have two modes of motion, free flight and
random scattering. If the mean free path is much smaller than the actual device size,
carrier transport is dominated by frequent random scattering, which can be regarded
as drift diffusion. If the mean free path is compatible to the device size, the transport
of carriers is dominated by free flight, which actually achieves quasi-ballistic
transport [6].
In long-channel devices, carriers will be subject to frequent scattering during the
transit of the channel. The drift-diffusion model (DDM) or fluid dynamics model
(FDM) based on scattering balance can well describe the transport of carriers in
actual devices. While in nanoscale devices, the nature of carrier transport begins to
change and carriers are less scattered during the transit of the channel, DDM or FDM
based on scattering balance cannot describe carrier transport in actual devices since
the transport of carriers in the channel is already a quasi-ballistic transport. If the
device size is further scaling down, the time for carriers to cross the channel is much
less than the scattering time, the carriers will not be subject to any scattering during
the transit of the channel, and the device will achieve ballistic transport [6]. The
ballistic transport of the device will be a common goal of device design. However,
since the actual device always has more or less random scattering, it is more
important to study the quasi-ballistic transport characteristics of the device.
A series of studies on the quasi-ballistic transport characteristics of nanoscale
semiconductor devices have been carried out worldwide. Early research focused on
modeling ballistic transport of nanoscale semiconductor devices. In 1994, Natori
made a detailed analysis of the ballistic transport transistor and gave the current-
voltage relationship [7]. Although this method considers quantum transport and can
86 Modeling and Simulation of Nano-devices 1885

be used to analyze the ballistic transport characteristics of the device, it cannot study
the quasi-ballistic transport characteristics of the device. In 2003, Lunstrom gave a
charge transfer model for quasi-ballistic transport based on stream processing [8].
The model is very simple in form and can better reflect the transport characteristics
of nanoscale semiconductor devices. However, it is impossible to make an accurate
analysis of the quasi-ballistic transport characteristics of the device due to many
assumptions.
Since the Monte Carlo simulation method can simulate a small amount of
scattered carrier transport, the Monte Carlo simulation method is commonly used
to analyze the quasi-ballistic transport characteristics of devices. The quantum
transport models such as the nonequilibrium Green’s function mainly use the
Hamiltonian to describe the device structure simulated. The interaction between
carriers and the interaction between carriers and phonons are added to the Hamilto-
nian of the device through perturbation. The quantum transport model describes the
device from the bottom up, which strictly handles multibody interactions, The most
rigorous description of the device can be obtained using a quantum model, the cost
of which is the large amount of calculation being its shortcoming. Currently, the
device simulator of the quantum transport model generally ignores the interaction
between carriers and phonons, and only considers the case of ballistic transport.
Even so, it requires a very large amount of computation, usually needs a supercom-
puter to complete the calculation. If phonon scattering is added, not only the amount
of calculation will increase sharply but also the parallel efficiency of the calculation
will be greatly affected [9]. Figure 86.2 gives a comparison of carrier transport
models for semiconductor devices.

Fig. 86.2 Comparisons of carrier transport models for semiconductor devices [10]
1886 F. Liu et al.

Nonequilibrium Green’s Function (NEGF)

The conventional simulation method for semiconductor materials and devices, like
drift-diffusion model (DDM) method and Monte Carlo (MC) method, can be called
semiclassical method since these methods are a mixture of quantum theory and
classical theory. In these semiclassical methods, the carriers are still treated to be
some kind of real particles. For the effect of crystal periodic potential, it is described
by energy band and scattering rate in the Monte Carlo method while is included in
the effective mass and mobility in the drift-diffusion method. The semiclassical
method emphasizes that the carriers are particles, but ignores that the carriers are
also waves. Thus, the semiclassical method cannot deal with pure quantum phe-
nomenon like tunneling since tunneling is dominated by wave nature of the
carriers [11].
Nonequilibrium Green’s function (NEGF) can deal with quantum transport and
it is totally based on quantum theory. Comparing with distribution function,
the carriers’ Green’s function includes more information of the system. Thus, if
the Green’s function is available, the entire information about the device is
obtained. The calculation of NEGF starts from the Hamiltonian of the system
while the external force field (like electrical field, magnetic field, and temperature
distribution) is treated as perturbation. For semiconductor device simulation,
generally the simulation region is divided to be three parts: the semi-infinite left
contact, the finite length device channel region, and the semi-infinite right contact.
For the simulation, the Hamiltonian of the finite length device channel region
should be written while the semi-infinite left and right contacts are treated as
perturbation. The impact of the perturbation of the semi-infinite left and right
contacts on the device performance is calculated by self-energy of the semi-infinite
left and right contacts. It is the key point for the device simulation that how to get
the self-energy of the semi-infinite left and right contacts. The inclusion of the
phonon scattering in the simulation is also treated as phonon self-energy. Combine
device Hamiltonian and perturbation self-energy (phonon scattering, left and right
contacts, and gate contact), and one proceeds a self-consistent iterated calculation,
the nonequilibrium Green’s function can be calculated, and thus, the performance
of the device is attained [12].
The quantum tunneling effect, the confinement effect, and other quantum phe-
nomenon as well as phonon scattering are intrinsically included by nonequilibrium
Green’s function simulation. So, comparing with semiclassical simulation method,
the NEGF method has unexampled advantages. However, the computation burden of
NEGF simulation is tremendous. Even for ballistic calculation, the computation
burden is already very large. If phonon scattering is considered, the computation
burden is even larger. Fortunately, the NEGF calculation can be paralleled with very
high efficiency. Also, there are some fast calculation method for the NEGF simula-
tion, for example, the mode space method and recursive Green’s function (RGF)
86 Modeling and Simulation of Nano-devices 1887

proposed by Purdue University and low-rank approximation (LRA) method pro-

posed by Peking University and Purdue University.

Molecular Dynamics Simulation

Molecular dynamics is a computational method that can study the dynamic evolution of
a system at the atomic or molecular level. The simulation method simulates the
trajectories of atoms and molecules by solving Newton’s equations of motion of the
multi-body system composed of nucleus and electron. According to the Born-
Oppenheimer approximation [13, 14], the motion of nucleus and high-speed electron
can be considered separately. In 1957, Wainwright and Alder first solved the state
equations of gas and liquid using molecular dynamics simulation under the hard sphere
model [15] and studied the macroscopic properties of the system through the micro-
scopic movement of molecules. Although analytical theory can partially explain the
experiment, it often neglects some details due to assumption of many approximations.
By use of molecular dynamics simulation, the microscopic details of the atomic motion
of the system can be observed, and then more detailed information of the system can be
obtained, which can effectively make up for the shortcomings of the experiment. With
the rapid development of computer hardware and software technology, the calculation
speed of molecular dynamics gets faster and its advantages get more obvious including
low cost, fast computing speed, wide applicable scope, high accuracy, and the micro-
details. Molecular dynamics simulation has been widely used in physics, electronics,
materials, chemistry, chemical engineering, life science, and other fields. Empirical
potential, boundary conditions, and ensemble descriptions are required for molecular
dynamics simulation [16]. In molecular dynamics simulation, it is very important to
determine the potential function between atoms. Because the potential function between
atoms has many forms, so the corresponding potential parameters should be adopted
according to different research objects. Potential parameters can be determined by
experimental fitting, quantum mechanical calculation, and Monte Carlo method. Notice
that molecular dynamics simulates a system with a finite number of particles, but the
properties of the system can still be described by the laws of statistical physics.
Molecular dynamics method can be used to calculate the kinetic process of atoms
under external field. Therefore, microscopic mechanisms related to devices can be
studied by using molecular dynamics method, such as material growth, material pre-
diction, ion implantation, and microscopic mechanism of nano-devices. For example,
Onofrio et al. used molecular dynamics method to simulate the atomic motion of
resistive materials under electric field and pointed out that the time needed for the
change of resistive state ranged from hundreds of femtoseconds to nanoseconds [17].
The molecular dynamics process of the formation and breaking of conductive filaments
in resistive memory is shown in Fig. 86.3. Merchant et al. have used molecular
dynamics method to study the DNA sequencing of graphene nanopores [18].
1888 F. Liu et al.

Fig. 86.3 Molecular dynamics simulations of filament formation and dissolution in resistive
memory [18]

First Principles Method

As the size of transistors in integrated circuits shrinks and reaches the nanoscale, the
performance of electronic devices is increasingly affected by various quantum
effects and atomic-scale material properties. First principles calculations play an
increasingly important role in studying the properties of materials, understanding the
micro-mechanism of devices, and improving the performance of devices. First
principles calculations are known as an ab initio method based on quantum mechan-
ics, directly solving the Schrodinger equation of a multiparticle system composed of
nucleus and electrons. It does not need any empirical parameters, only from the atom
types and coordinates of atoms, to obtain electronic structures of materials, so as to
further obtain all kinds of physical and chemical properties of the system. In theory,
the properties of any material can be calculated by first principles, but the actual solid
material is a multi-body system composed of a large number of electrons and
nucleus. It is obviously unrealistic to directly solve the Schrodinger equation with
such a large number of particles and a large number of independent variables, so
approximations are necessary.
First principles calculations are mainly based on three basic approximations to
solve the Schrodinger equation of a multiparticle system: nonrelativistic approxima-
tion, the Born-Oppenheimer approximation [13], and Hartree-Fock approximation
[14, 15]. According to relativity, the mass of an electron moving at high speed is
related to its velocity, while in the nonrelativistic approximation, the electron mass is
approximated to its stationary mass. In the absence of an external field, the Hamil-
tonian of a solid material includes the kinetic energy of electrons and nucleus in the
system, as well as the interaction energy among these particles. The nuclei mass is
much larger than electron mass, so nuclei moves much slower than electron, and the
nuclei only vibrates near its equilibrium position. Under the Born-Oppenheimer
approximation, the motion of nuclei can be separated from the movement of
86 Modeling and Simulation of Nano-devices 1889

electron. When considering the electron’s movement, the nuclei can be assumed as
static. Therefore, the electronic Hamiltonian has only three items: electronic kinetic
energy, electron-electron Coulomb interactions, and electron-nucleus potential
energy. Although in the Born-Oppenheimer approximation, the electron motion of
a multiparticle system can be separated from the nuclei motion, the Schrodinger
equation of electrons is still a multiparticle equation because of the interaction
among electrons. The Hartree-Fock approximation simplifies the multiparticle
Schrodinger equation to a single electron equation, which greatly simplifies the
calculation. The Hartree-Fock approximation averages the interaction among elec-
trons, so that each electron moves in an effective potential of all other electrons and
nucleus, and each electron state can be described by a single electron wave function.

Density Functional Theory (DFT)

Density functional theory (DFT) is a quantum mechanical method to study the

electronic structure of multi-electron system based on the Hohenberg-Kohn theo-
rems [16], which is based on Tomas-Fermi model and includes the following two
theorems.
Theorem 1: The external potential (and hence the total energy) is a unique
functional of the electron density. The ground state density function of the
interacting multi-body system is the basic variable determining the ground state
physical properties of the system. The ground state wave function is a functional of
the ground state density, and all ground state physical quantities are functional of the
ground state density.
Theorem 2: For a given external potential, the ground state electron density
minimizes the total energy.
Hohenberg-Kohn theorems are strictly based on quantum mechanics theory but
do not give a detailed method to calculate the ground state electron density. DFT can
be implemented in a number of ways, and the Kohn-Sham method is widely used
today [19]. In 1965, W. Kohn and L. J. Shen proposed the use of noninteracting free
electrons as an auxiliary means to replace the interacting multi-body system, namely
Kohn-Sham method. The proposed method makes DFT become a widely used
method to calculate electronic structures. In order to avoid the difficulty of directly
solving the Schrodinger equation with electron interaction, Kohn-Sham method
solves one electron effective equation, and all the interaction terms between multiple
bodies are put into the density functional of the exchange correlation. The exchange
correlation terms play an important role in the calculation of the ground
state properties of multi-electron systems by the Kohn-Sham method. The exchange
correlation functional depends on the charge density distribution in the whole space,
so it is very difficult to solve it directly. Currently, there is no accurate formula.
The approximation methods mainly include local density approximation [19] and
generalized gradient approximation [20, 21]. It is necessary to discretize the wave
function or charge density to solve the Kohn-Sham equation numerically and
convert the equation into matrix form. At present, the commonly used discretization
1890 F. Liu et al.

method is to expand the wave function under the basis function. Although infinite
basis functions are required for theoretical proof, only a finite number of base
functions are needed for practical operation. Therefore, the choice of base functions
determines the accuracy of the calculation.
DFT is widely used in studying physical properties of materials, such as mechan-
ical, thermal, electrical, and optical properties [22], so that people can effectively
evaluate the application of materials in devices. For example, Ashton et al. predicted
826 stable two-dimensional layered materials by using DFT [23], which is of great
significance for finding channel materials suitable for transistors. The first principles
quantum transport method based on DFT and the nonequilibrium Green’s function
can calculate electron and phonon transport, as well as the photon’s influence on
electron transport from the atomic structure of nano-device [24], and is widely
applied in the study of molecular devices, spin devices, heat transfer devices,
semiconductor devices, etc.

Atomic Device Simulation

Atomic device simulation is developed from nonequilibrium Green’s function sim-

ulation. Since the shrink of the semiconductor devices to be in the atomic region, the
whole devices contain only several tens or hundreds atoms, and it is possible for
atomic device simulation.
In NEGF method, the impact of the crystal periodic potential on carriers is
included by device Hamiltonian. The device Hamiltonian has different levels, and
it can be written by effective mass approximation or tight-binding approximation.
The atomic device simulator is one kind of simulator that utilizes atomic orbitals (for
example, the tight-binding orbitals) to write the device Hamiltonian and do the
following device performance calculation. For silicon material, it is required for
10 atomic orbitals (if spin is considered, 20 atomic orbitals are required) to accu-
rately write the Hamiltonian. Thus, the computation burden for atomic device
simulation is huge; typically super computation is needed to complete the simula-
tion. The most famous atomic device simulator is OMEN developed by Mathieu
Luisier and the following version NEMO5 developed by Purdue University.
Since the computation burden of the atomic device simulation increases largely
with the increase of atom number, the atomic device simulation can only deal with
small size device.

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Flexible Semiconductor Devices (FSD)
87
Yi Shi, Yun Li, and Sai Jiang

Contents
Stretchable Inorganic Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
Foldable Silicon Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
Flexible Thin-Film Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
Organic Field-Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
Flexible Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
Flexible Substrate Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
Flexible RFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904
Flexible Micro-electromechanical Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
Organic Semiconductor Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
Organic Heterojunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Organic Light-Emitting Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910
Organic Photodetectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
Organic Solar Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913

Abstract
Flexible semiconductor devices refer to electronic devices made of organic/
inorganic materials on flexible substrates. Compared with traditional semicon-
ductor devices, flexible ones intrinsically exhibit good flexibility, can adapt to
various working environments. Due to the attractive advantages of foldability and
ductility, flexible semiconductor devices have been extensively studied in the
fields where traditional devices are difficult to be applied, such as flexible
displays, radio-frequency identification tags (RFIDs), flexible sensors, and flex-
ible memories. In this chapter, typical flexible semiconductor devices are briefly
introduced including stretchable inorganic semiconductor devices, foldable sili-
con integrated circuit, flexible thin-film transistors, and flexible substrate

Y. Shi (*) · Y. Li · S. Jiang

School of Electronic Science and Engineering, Nanjing University, Nanjing, China
e-mail: yshi@nju.edu.cn

© Publishing House of Electronics Industry 2024 1893

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_87
1894 Y. Shi et al.

technology. Their characteristics, challenges and application prospects are also

addressed.

Keywords
Stretchable inorganic semiconductor devices · Foldable silicon integrated circuit ·
Flexible thin-film transistors · Organic field-effect transistors · Flexible memory ·
Flexible substrate technology · Flexible RFID

Stretchable Inorganic Semiconductor Devices

Stretchable inorganic semiconductor devices are fabricated through a specific pro-

cess, by which the electronic devices and stretchable connection parts are deposited
or transferred onto a flexible stretchable substrate, so that the devices can still
maintain high device performance under the effects of bending and stretching.
Many devices fabricated on polymer flexible substrates only have a bending
capability of a few centimeters of curvature, and their applications are subjected to
small bending curvature and stress. Fabricating more stretchable devices will pro-
mote the rapid development of sensors, flexible displays, medical electronics, etc.
One of the technologies is embedding inorganic electronic devices and extensible
spring-like cables together onto a flexible substrate [1].
The core idea of this device fabrication process is to fabricate the electronic
devices and the stretchable connection parts independently, and to connect them
subsequently by flip-chip soldering, which is commonly known as the CINE (Com-
bination of INterconnects and Electronics) technology. It can be divided into the
following three steps:

1. Prepare metal solder joints and stretchable connecting wires by conventional

micro-machining technology
2. Transfer the contact solder joints and stretchable wires to flexible substrates by
using the soluble adsorbents as the transfer medium
3. Solder functional electronic devices on metal solder joints by flip-chip technology

With the above steps, a common stretchable inorganic semiconductor device can
be realized. At the present stage, as an emerging electronic technology, the devel-
opment of the stretchable flexible electronic device is still in its infancy. It is mainly
used to improve the structure of silicon matrix, making up for the drawbacks of
silicon-based chips, so that electronic devices are equipped with many characteris-
tics, such as good flexibility, shock resistance, light and thin body, etc., and cost less
to fabricate [2]. Diagram of the stretchable device proposed by Rogge’s research
group is shown in Fig. 87.1.
Stretchable and flexible electronic devices are likely to give rise to a wide range of
applications. For example, in the field of biomedicine, to achieve the accurate
diagnosis and drug delivery, electronic devices are required to be deformed with
87 Flexible Semiconductor Devices (FSD) 1895

Fig. 87.1 Diagram of the

stretchable device proposed
by Rogge’s research group [3]

human body changes. In addition, it is also widely used in artificial electronic skin,
portable-wearable electronic devices, and other fields. The technology can be used to
prepare sensor-based wearable electronic devices to continuously and dynamically
monitor various physiological data of human body. With the rapid development of
inorganic and organic materials, as well as the improvement of the manufacturing
process, the stretchable flexible electronic devices will also be rapidly developed,
and the application of the corresponding functional devices is bound to be associated
with all aspects of life, thus to having a significant impact.

Foldable Silicon Integrated Circuit

Foldable silicon IC refers to the integrated circuit made of stretchable and foldable
silicon material. Such devices can maintain their electrical performance under
intense mechanical deformation conditions, such as bending or folding, lateral
stretching, compression, kneading, etc. Its lightweight, collapsible, and stretchable
properties enable many novel applications. The electronic devices directly integrated
by foldable silicon IC can be applied to biological systems, medical prostheses, and
monitoring instruments.
Silicon integrated circuits have long been fabricated on hard silicon-based sub-
strates. In recent years, with the development of flexible devices based on nanoscale
materials and structures, scientists have found that most organic and certain inor-
ganic electronic materials are flexible on plastic or steel foil substrates, but cannot be
stretched or folded. Therefore, using silicon materials, single crystal silicon arrays,
and flexible substrates, researchers combined multi-layer neutral mechanical plane
layouts with logic gates, oscillators, differential amplifiers, and other elements in
integrated circuits to develop high performance single crystal silicon CMOS ICs
[4, 5]. Single crystal silicon is utilized because of its excellent electrical properties,
such as high electron- and hole-carrier mobility. At the same time, enormous
commercially available silicon wafers provide the required ultra-thin wafer materials
1896 Y. Shi et al.

Fig. 87.2 Foldable silicon IC [5]

for cost-sensitive applications or SOI wafers. The researchers spin-coated PMMA

and polyimide (PI) substrates onto silicon wafers and obtained ultra-thin Si-CMOS/
PI integrated circuits through transfer printing, reactive ion etching, etc. Better
folding and stretching properties, as shown in Fig. 87.2, provide possibilities for
the design of medical instruments for flexible applications.
Nanoscale flexible electronics focus on increasing the stacking density of elec-
tronic devices, while preparing flexible ICs using nanoscale transistors remains
challenging. The researchers integrated nanoscale circuit on ultra-thin silicon wafers,
where the ring oscillators possess a 16 ps delay at 0.9 V [4]. Through spalling
technology, researchers transferred ultra-thin wafers onto flexible substrates to
improve the device mechanical flexibility. They adopt mainstream silicon processing
technology to produce ultra-thin flexible ICs with high complexity and low cost.
Foldable silicon ICs are expected to have a wide range of applications, including
wearable health-monitoring and securing systems, “smart” surgical gloves with
integrated electronics, and electronic eye detectors with focal plane array hemispher-
ical substrates.

Flexible Thin-Film Transistors

Flexible thin-film transistor (TFT) is a special kind of metal-oxide-semiconductor

field-effect transistor (MOSFET) fabricated by depositing an active semiconducting
thin films on flexible substrates. Semiconductor materials used in flexible TFTs
include organic (small molecules, polymers, etc.) and inorganic (graphene, etc.)
semiconductors. Due to their attractive advantages of low cost and foldability,
flexible TFTs are ideally suited in the fields where inorganic FETs are difficult to
be applied, such as flexible displays, low-cost radio-frequency identification tags
(RFIDs), and flexible sensors [5].
In 1962, P.K. Weimer invented the first inorganic semiconductor TFT. In 1990,
the TFT using organic semiconductors material as active layers was realized. By
2004, researchers succeeded in the preparation of IGZO TFT with the flexible
87 Flexible Semiconductor Devices (FSD) 1897

Fig. 87.3 Sectional view of

four structures of TFTs (a)
top-gate top-contact structure,
(b) top-gate bottom-contact
structure, (c) bottom-gate
top-contact structure, and (d)
bottom-gate bottom-contact
structure

substrate at room temperature. The progress indicates the development of flexible

TFTs has broad prospects.
The structure of a flat flexible TFT is shown in Fig. 87.3. A flexible TFT is mainly
composed of a substrate, gate insulator, semiconducting layers, and electrodes. The
realization of the flexibility requires special demand on materials and fabrication
technology used in each part of the devices.
Substrate materials affect the ductility and fabrication technology of flexible
TFTs. At present, there are polyethylene terephthalate (PET), polyethelene naphtha-
lene (PEN), polyimide (PI), and other polymers, among which PET has been widely
investigated and used because of its great advantages such as low-cost fabrication
and high transparency. The gate insulating layers with a high dielectric constant are
required to maintain insulating properties under various mechanical deformations
such as bending and stretching. Considering that the semiconducting layers are
deposited on the insulating layers, a surface pretreatment will improve the unifor-
mity of the semiconductor films and speed up the carrier transport in conducting
channels. Therefore, appropriate gate dielectrics are highly preferred for the efficient
enhancement of device performance. The existing flexible insulating materials are
mainly constituted of biomaterials (such as cellulose, peptidoglycan), organic poly-
mers (such as PVA, PMSQ, PVP, PI, and PMMA), inorganic polymers (such as
Al2O3, SiNx, and SiO2), organic/inorganic hybrid materials, etc. Semiconductors
used in flexible TFTs are stable and deformable while able to maintain high carrier
mobility. Organic semiconductors commonly used in TFTs are p-type small-molec-
ular and polymeric materials, such as pentacene, phthalocyanines and coordination
compounds, and oligomeric materials represented by oligo-polythiophene. On the
other hand, for n-type organic semiconductors, their application in devices is limited
due to the instability in air. N-type organic semiconductors for high performance
organic TFTs include phenyl dithiadiazole derivatives, fullerene (C60), C70,
1898 Y. Shi et al.

tetracarboxylic acid materials, and so on. In addition, metal oxides semiconductors

(such as IGZO, ZnO), graphene, and carbon nanotubes can also be used as semi-
conductors in flexible devices. Contact properties are of great significance for
designing strategies to optimize organic TFTs. For example, specific electrode
materials and modification layers should be employed at the molecule/metal inter-
face to change the work function of the metal and realize ideal energy level
matching, thus enhancing the charge injection into semiconductors. Generally, the
source and drain electrodes are fabricated using Au. ITO or Al is used as the gate
electrodes. Besides, PEDOT: PSS, graphene, SnO2, and ZnO are employed as
transparent electrode materials.
The biggest differences between flexible TFTs and traditional semiconductor
devices are flexibility and ductility, which place greater demands on mechanical
properties of materials, and provide definite guidance toward future development of
flexible TFTs. The major challenges in this field mainly include the following
aspects.

1. For semiconductor materials, more stable n-type organic semiconductors need to

be synthesized for high-performance organic complementary logic circuits.
2. Secondly, as for flexible substrates, it is necessary to accelerate the development
of high corrosion resistance, high temperature resistance, high transparency, low
cost, and flexible materials as well as low-temperature processing technology.
3. To find the insulating material with high dielectric constant, research on low-cost
and low-temperature processing should be taken into account, thus improving
device performance.

The image of the flexible TFT arrays is shown in Fig. 87.4.

Organic Field-Effect Transistors

An organic field-effect transistor (OFET) is a field-effect transistor, which adopt

organic semiconductor as its channel material. OFETs are widely used in the
production of large-area flexible equipment and have potential applications in
many fields such as detectors, batteries, and energy storage equipment.
There are six common structures of organic field-effect transistors, as shown in
Fig. 87.5 [7]. The bottom-contact structure and top-contact structure (Fig. 87.5a and b)
are different in the distribution of the semiconductor and source/drain of the transistor.
Organic semiconductors are susceptible to air and moisture, the performance will
degrade after being exposed in air for a long time. Devices with top-gate structure
(Fig. 87.5c and d) can effectively solve the problem of performance degradation. The
vertical structure (Fig. 87.5f) is more suitable for operation at high frequencies than
other structures. At present, double-gate structure organic field effect transistors
(Fig. 87.5e) have also been widely studied. The gate adjustment of these devices has
the function of adjusting the on-state current and the on-voltage, which enable the
dual-gate structure to be widely used in inverter.
87 Flexible Semiconductor Devices (FSD) 1899

Fig. 87.4 Flexible TFT arrays

[6]

Fig. 87.5 Six structures of OFET [7]. (a) top-contact structure; (b) bottom-contact structure; (c)
top-gate top-contact structure; (d) top-gate bottom-contact structure; (e) double-gate structure; (f)
vertical structure
1900 Y. Shi et al.

Fig. 87.6 OFET sensors used

in the hand electronic skin [8]

The above six structures of OFETs have similar operating principles. When a voltage
is applied to the gate, current will be generated between insulator and semiconductor.
The drain-source current will not rise until the number of charge carriers increases,
eventually causing the field effect transistor to be “turned on.” This type of device
generally has two modes of operation: the saturation mode and the linear mode.
The core component of OFETs is semiconductor materials. Based on different
chemical and physical properties, OFETs materials are divided into three categories:
the first one is organic small molecular compounds, such as C8-BTBT and C60; the
second one is low-molecular-weight polymers, such as oligomeric thiophenes; and
the third is high-molecular-weight polymer, such as HT-poly trialkyl thiophene [5].
In recent years, organic field-effect transistors have been widely applied on flexible
and large-area sensors. For example, pressure sensors are used in the artificial
electronic skin [8]. Figure 87.6 shows an array of organic field-effect transistor
sensors utilized in the hand electronic skin.
The development of OFETs faces the problems of high manufacturing costs due
to special preparation requirements, short device lifetime, and limited types. It is
necessary to further optimize the structure of OFETs to improve their performance.

Flexible Memory

Flexible memory usually refers to electrical memory devices based on organic thin-
film transistor (OTFT) structure, which has broad application prospects in flexible
storage and advantages of certain flexibility, ductility, and compatibility with
87 Flexible Semiconductor Devices (FSD) 1901

traditional processes, non-destructive reading, and easy integration with other elec-
tronic devices.
Transistors are divided into top-gate and bottom-gate devices according to the
position of gate electrode [9]. Generally, due to the limitation of fabricating tech-
nology, the electrical performance of the bottom-gate devices is better. Moreover,
according to the positions of the source and drain electrodes, the bottom-gate devices
are divided into bottom-contact and top-contact structures. Generally, top-contact
devices exhibit outstanding memory performance due to the functional layers with
better conductivity.
The writing and erasing processes in flexible memories are usually realized by
modulating the charge or resistance of devices. The charges can be trapped or
released by the charge-capturing center such as nanocrystals doped in the gate
materials on the flexible substrates under a certain gate voltage; the resistance of
conducting channels can be efficiently modulated by the polarization of ferroelec-
trics (such as P(VDF-TrFE), MXD6, PZT, BST) or electrets (such as PVA, PMS, RS,
KDP, TGS) in gate dielectrics.
A floating-gate OTFT memory consists of two gate electrodes and a programmed
voltage applied between the gate and source electrodes. Charges are injected by
thermal emission or tunneling and captured on a floating-gate film, thus completing
data storage process. Moreover, due to the isolation effect of the dielectric layer on
the floating gate, the trapped charges are well maintained so that non-volatile storage
is realized. When the applied voltage is reversed, the charge escape from the floating
gate and the data storage is erased.
In these devices, the ferroelectric capacitor memorizes ON and OFF states
when positive and negative pulses with amplitudes exceeding the coercive
voltage are applied. In a memory resistor that controls the conductance of
semiconductor by using ferroelectric material, the polarization field is formed
in the organic ferroelectric layer at certain gate voltage, which induces charges
with opposite polarity at the ferroelectric/organic semiconductor interface and
consequently forms the conducting channel between drain and source electrodes.
Significant current is generated by applying certain drain bias, which is defined as
“1” state. When applying opposite gate voltage, devices would be set to the off
state, closing the conducting channels, which is defined as “0” state. Moreover,
by virtue of the intrinsic coercive field of ferroelectrics, states are well maintained
even if the gate voltage is removed, such process is the storage of “0” and “1”
states.
In 2004, the first OTFT memory with polymer as gate insulator was reported [10],
which maintain the data more than 3 h at the gate voltage of 2.5 V, indicating that
great progress has been made in OTFT memory with electret polymer of PVA as gate
insulator (Fig. 87.7). Afterward, the OTFT memory using bilayer polymer electret-
coated SiO2 dielectrics was fabricated successfully.
OTFT memory has received intensive attention during the development of
flexible thin film memory. At present, high performance devices have been fabri-
cated exhibiting attributes such as low operating voltages below 2 V, more than 103
endurance cycles, and long data retention time of hundreds of hours [11]. Due to the
low carrier mobility of organic semiconductors, flexible TFTs with relatively high
1902 Y. Shi et al.

Fig. 87.7 Field-effect

memory based on PVA [10]

performance are constituted of organic and inorganic materials. Great efforts are
required to further improve the device performance, such as reducing the operating
voltages, speeding up the switching processes, exploiting fundamental physical
mechanisms, and increasing the endurance cycles.

Flexible Substrate Technology

Flexible substrate technology is usually referred to building electronic devices on

flexible materials based substrate such as plastic and stainless steel. Flexible
substrate technology has been widely applied into organic electroluminescent
devices, field effect transistors, etc., to achieve novel functions. Burrows [12]
applied the flexible substrate technology to flexible displays as early as 1997. As
a current research hotspot of electronic devices, flexible substrate technology
presents attracting advantages such as lightweight, portability, and flexibility.
Therefore, flexible substrates are expected to achieve more emerging
applications [13].
At present, flexible substrate mainly comprises the following five aspects: plastic
substrates, metal substrates, glass substrates, paper substrates, and bio-composite
substrates.

1. Plastic substrates: There are mainly three types of materials, amorphous high
glass transition temperature polymers (such as PCO, PNB), amorphous polymers
(such as PES, PC), and semi-crystalline thermoplastic polymers (such as PET,
PEEK). Because of advantages of transparency, durability, and low cost, it has
broad application prospects.
2. Metal foil substrate: Metal material exhibits relatively poor light transmittance.
Due to this limitation, metal substrate is generally used in flexible light-emitting
87 Flexible Semiconductor Devices (FSD) 1903

display, which requires low light transmittance [14]. For large flexible devices,
this material cost too much, while it is expected to show great potential in smaller
flexible devices. The stainless steel substrate presents strong heat resistance,
which is much higher than other flexible substrates. Therefore, flexible metal
foil substrate shows broad application prospects in flexible devices operating at
high temperatures.
3. Ultra-thin glass substrate: As a kind of hard material, glass presents flexibility to
some degree when it achieves ultra-thin thickness. Hence, ultra-thin glass sub-
strate is capable of being a kind of flexible substrate material. Through the state of
art process, the thickness of ultra-thin glass is less than 50 μm, and the device
produced exhibits good flexibility. At the same time, the ultra-thin glass exhibits
good light transmittance, surface smoothness, thermal stability, and insulation.
However, the disadvantage of flexible glass substrate is poor suppleness.
Although it achieves certain flexibility after thinning treatment, flexible glass
substrate is prone to crack after repeated bending, and crack defects are likely to
form at the edge during the cutting operation as well. In 2002, Andreas Weber
et al. [15] realized a thin glass-polymer substrate with good physical and chemical
stability properties and mass production.
4. Paper substrate: The flexible paper substrate presents numerous advantages such
as lightweight, high flexibility, recyclability, etc. The electronic device fabricated
with paper substrate has attracted extensive attention in recent years. Though
plastic substrates have similar properties, paper substrates show a lower coeffi-
cient of thermal expansion. Figure 87.8 shows a flexible light-emitting device
made with different types of paper substrates [16].
5. Bio-composite film substrate: Its advantages include bendability, low thermal
expansion coefficient, and high light transmittance. Therefore, biocomposite film
substrates are the spotlight of current research in the field of organic
optoelectronics [17].

Fig. 87.8 Three kinds of paper flexible substrate illuminating devices

1904 Y. Shi et al.

These flexible substrates provide similar performance and are flexible enough to
realize more applications than conventional non-flexible substrates. For most appli-
cations, it is important to reduce the manufacturing cost of flexible substrates.
Flexible substrate technology is the foundation of flexible electronic devices and
definitive factor for device performance. It plays an essential role in the research of
flexible electronic devices.

Flexible RFID

Flexible electronic labels are stretchable electronic labels prepared by flexible

materials. An electronic label can be referred to as a “transponder.” It is small in
size, thin in texture, flexible, long lasting, compatible with many materials, and has
important applications in radio frequency identification (RFID) systems. The RFID
system consists of two resonant circuits. The information exchange and energy
transfer between them are completed via electromagnetic coupling. The resonant
circuit inside the reader excites a magnetic field around it. As the electronic label
approaches, the microchip on the electronic label begins working and starts com-
munication with the reader.
The flexible electronic label has simple structure, consisting of a small semi-
conductor chip and a fixed inductor. There are two types of electronic label: active
label and passive label, depending on the way to get energy. Active label contains
power source inside. It has large storage capacity and wide range of applications.
Passive label does not contain power source inside, extracting the energy needed
for work from electromagnetic induction. It is affordable and has a long service
lifetime [18].
The flexible electronic label is a new type of flexible electronic device. The
flexible chip is the core of a flexible electronic label. Electronic chips are often
programmable. As organic electronics becomes a hot research field, flexible chips
are gradually becoming cheaper and more affordable. The researchers have selected
polyimide (PI) as the flexible substrate and reduced its roughness via spin coating.
After cleaning, sputtering, and photolithography, the loop antenna was used to
obtain a novel flexible electronic label with “visual security” function [19]. In
addition, as an electromagnetic coupling element, the inductor acts as an “antenna”
in the electronic label. Therefore, the researchers had prepared a flexible thick film
inductor to optimize its performance, which made possible the realization of flexible
electronic labels [18].
The fabrication and performance improvement of flexible electronic labels have
profound impact. First, flexible electronic labels help to make full use of the volume
shape and significantly increase the effective use of density. Second, low-cost
flexible electronic labels will enable RFID technology in applications such as item
monitoring, vehicle monitoring, supply chain management, production line automa-
tion, motion timing, electronic payment, etc. Figure 87.9 shows a flexible electronic
label that can be used in temperature measurement.
87 Flexible Semiconductor Devices (FSD) 1905

Fig. 87.9 Flexible electronic label for temperature measurement [20]

Flexible Micro-electromechanical Systems

Flexible micro-electromechanical systems (MEMS) technology refers to such pro-

cess that fabricates the devices, which process physical, chemical, and biological
signals on a chip based of flexible materials, through micro-machining process, and
constructs complex micro-systems via device integration or circuit integration [21].
There are a large amount of applications of flexible MEMS, such as artificial retina
chips, medicine flexible temperature sensors, and flexible tactile sensors commonly
used in robot research. Flexible MEMS is similar to general electromechanical
systems, which integrates signal control, processing modules, sensors, as well as
actuator modules.
Silicon-based integrated circuits are dominating in the field of microelectronics,
due to their impeccable manufacturing processes and excellent performance. How-
ever, in recent years, flexible electronic devices based on flexible plastics and thin
metal substrates have emerged and attracted wide research interests. Flexible devices
exhibit the advantages of ductility, flexibility, high efficiency, and low cost, which
make them possess broader application prospects and make up for the inflexibility of
silicon-based circuits.
The artificial retina chip is based on flexible micro-electromechanical technology.
The principle is to place the microelectrode array fabricated by micromachining on
the retina. The external scene stimulates the photodiode to generate photocurrent into
the microelectrode. The current on the microelectrode stimulates the residual normal
optic nerve cells on the retina and finally produces artificial vision, as shown in
Fig. 87.10 [22]. However, the silicon-based chip too rigid to match the normal shape
of the retina and is prone to displacement. This displacement motion would cause
irreversible damage to the retina. Luckily, the flexible MEMS system adapts to the
shape of the retina and improves this dilemma effectively.
Another example is wearable tonometer. Medically, the cause of diseases such as
glaucoma may be high intraocular pressure. However, the existing measurement of
intraocular pressure requires special instruments from the professional hospitals,
which restricts the prevention and treatment of glaucoma significantly. By applying
1906 Y. Shi et al.

Fig. 87.10 Artificial retina chip based on flexible MEMS

the flexible MEMS technology, the pressure sensor will be fabricated on a hemi-
spherical flexible substrate using a micromachining process to produce a wearable
tonometer, which enables real-time monitoring of intraocular pressure
successfully [23].
Generally speaking, MEMS sensors on flexible substrates will bring essential
changes to sensor applications in medical, robotics, aerospace, marine, and other
industries, resulting in lower cost, smaller size, lighter weight, and more flexible
detection, thus improving their performance quickly.

Organic Semiconductor Materials

Organic semiconductor materials (OSMs) are organic materials with conductivity

between that of organic conductors and organic insulators, generally of 10
10
102S/
cm. With the following characteristics, such as easy processing, relatively low
processing temperature, low cost, and large-scale preparation, organic semiconduc-
tor materials are of great interest as a promising class of materials for electronic
applications, including flexible devices, field effect transistors (FETs), photodetec-
tors, light-emitting diodes, solar cells, and so on.
In 1977, MacDiarmid and Heeger from the USA and Shirakawa from Japan first
catalyzed the synthesis of conductive polymer polyacetylene at Pennsylvania Uni-
versity of the USA. The results showed that polyacetylene could be changed into
good conductor by proper doping [24]. In 1982, Ebisawa et al. first applied
87 Flexible Semiconductor Devices (FSD) 1907

polyacetylene as a semiconductor material to field effect transistors [25]. In 1987,

Tang of Kodak Company in the USA used organic semiconductor materials as
electron and hole transport layer to fabricate organic light-emitting diodes
(OLEDs) [26], attracting wide attention for organic materials in the field of opto-
electronics. Since then, organic semiconductor materials have developed rapidly in
field effect transistors, solar cells, and flat panel displays.
OSMs are classified into polymer materials and small molecular materials
according to the size of molecules. At present, molecules with π-conjugated systems
are mostly used in OFETs and can be divided into n-type and p-type materials.
N-type organic semiconductors are mainly small molecular materials, such as C60,
metal phthalocyanines containing electron-withdrawing substituents, etc., as shown
in Fig. 87.11. Scientists pay more attention to understanding p-type materials, since
they exhibit relatively better stability and device performance, which include poly-
mers (such as polythiophene and its derivatives), oligomers, small molecular mate-
rials (pentacene, polycyclic molecules), and so on, as shown in Fig. 87.12.
For the conducting mechanism of organic semiconductors, there is perfect and
unified theoretical model so far. Instead, only general conducting mechanisms are
proposed for specific experimental phenomena. At present, there are four charge
transfer models mainly proposed, which are hopping transport, band theory, polaron
model, and multiple trap capture and release model (MTR). The hopping transport
model refers to the carrier hopping from a local state to an adjacent local state when
the thermal energy is large enough. The theory of energy band refers to the carrier
transporting in the form of plane wave in the whole crystal lattice with relative
delocalized state; the properties of the carrier can be explained by the theory of

Fig. 87.11 Common n-type

organic semiconductor
materials
1908 Y. Shi et al.

Fig. 87.12 Common p-type

organic semiconductor
materials

energy band. The polaron model refers to the formation of polarons resulted by the
strong coupling between carriers and lattices, whose distortion is caused by the
acceptance or loss of electrons of molecules in crystals when charges transport in
semiconductors. The MTR model refers to the following process: carriers are
normally in the local state, but when there is enough thermal energy, they decay
from the localized defective state to the extended band [27].
At present, there are still some problems to be explored about organic semicon-
ductor materials, such as the discussion of the applicability of molecular theory and
band theory, questions about quantum effects such as quantum dots and quantum
wells, research on low-dimensional, understanding of the ordered structure growth
process and research on its interface science.

Organic Heterojunctions

Organic heterojunctions are devices in which two organic semiconductor materials

with different energy levels form a junction structure. The heterojunction effect
brought by organic heterojunctions has given researchers a novel perspective on
the development of high-performance organic electronic devices. In recent years,
organic heterojunctions have become the focus of research by virtue of public
attention in organic solar cells and organic light-emitting diode.
Organic heterojunctions can be divided into two categories based on the types of
junction: homojunction and heterojunction. In homojunction, both sides are semi-
conductor materials of the same conductivity type, including n-n, in which carriers
are electrons, and p-p, in which carriers are holes. On the contrary, the two sides of
the heterojunction are semiconductor materials of different conductivity types, such
as p-n junctions. According to the difference of the Fermi level, the p-n junction can
be divided into depletion type in which the Fermi level of the p-type semiconductor
is lower than that of the n-type semiconductor, and the accumulation type in which
87 Flexible Semiconductor Devices (FSD) 1909

Fig. 87.13 CuPc and F16CuPc band diagrams under flat band conditions (a); ideal CuPc and
F16CuPc heterojunction interface electronic structures (b) [28]

the Fermi level of the p-type semiconductor is higher than that of the n-type
semiconductor. Inorganic p-n junctions are generally depleted junctions, while
organic p-n junctions are generally cumulative junctions [28]. Take the p-n junction
composed of CuPc and F16CuPc (Fig. 87.13) as an example. In the flat state, the
Fermi level of F16CuPc is lower than that of CuPc. When the two semiconductors are
in contact with each other, electrons will migrate from a semiconductor with a small
work function (CuPc) to a semiconductor with a large work function (F16CuPc) until
the Fermi level of both sides is the same and the system reaches equilibrium. Thus,
electrons and holes are accumulated in F16CuPc and CuPc, respectively, and an
organic semiconductor heterojunction is formed accordingly.
Currently, research on organic heterojunction faces many challenges, such as
adjusting the threshold voltage of a transistor, preparing a normally on type or
bipolar transistor, and integrating heterojunctions in the logic unit of a circuit. For
example, in the F16CuPc/CuPc field effect transistor, the heterojunction effect
induces carrier accumulation in the organic film. When VGS ¼ 0, current flows
through the channel, and a normally-on mode of operation is observed [29]. In
addition, the heterojunction effect facilitates efficient transmission of electrons and
holes at the heterojunction interface, realizing a bipolar organic transistor. It is found
that the carrier mobility of the heterojunction transistor prepared by F16CuPc and
BP2T is higher than that of the transistor prepared by using BP2T or F16CuPc alone
[30]. In the logic circuit, the bipolar heterojunction transistor is an important
component of the inverter, which has higher noise tolerance and better dynamic
response as well. At the same time, it also simplifies the design process of logic
circuit [31]. In the future, organic heterojunctions are promising due to their possible
applications in organic thin film transistors, organic photovoltaic cells, organic
sensors, etc.
1910 Y. Shi et al.

Organic Light-Emitting Diodes

An organic light-emitting diode (OLED) is known as a novel light-emitting device,

which adopt organic material to fabricate a conventional light-emitting diode.
Organic light-emitting diodes are considered to be an important flat panel display
technology because of their fast response speed, low cost, easy fabrication in large
areas, simple manufacturing process, and adjustable color through molecular
design [32].
The structure of OLED is shown in Fig. 87.14. When DC voltage is applied to the
diode and a potential difference is formed between anode and cathode, generating
current from anode to cathode. In this process, holes move from anode to cathode,
and electrons move from cathode to anode. They meet in the organic composite
emitting layer in order to form a hole-electron pair. It attenuates and emits energy in
the form of light, which is macroscopically represented by diode light [33].
The organic light-emitting diodes can be divided into direct current and alternat-
ing current driving modes according to the driving method. Since the voltage
direction does not change during direct current driving, among the excess electrons
and holes that did not form electron-hole pairs, part of the holes or electrons will flow
to cathode and anode, and the rest part will accumulate at the EML/HTL interface.
On the other hand, the positive half cycle of the AC drive is consistent with the DC
drive, but in the negative half cycle, the voltage applied across the diode is reversed,
causing the electrons and holes that previously accumulated at the EML/HTL
interface to change direction and flow toward anode and cathode. Therefore, the
number of holes and electrons remained at the electrode is reduced, weakening the
electric field. When the next positive half cycle comes, the effect of the reverse
electric field force is reduced, making it easier to form electron-hole pair and
resulting in relatively high transfer efficiency [34].

Fig. 87.14 Device structure

of a typical organic light-
emitting diode
87 Flexible Semiconductor Devices (FSD) 1911

Organic light-emitting diodes have the advantages of environmental protection,

energy saving, and long life, and have broad application prospects.

Organic Photodetectors

Organic photodetectors are devices that use organic materials as sensitive materials
to detect optical signals. Organic photodetectors have the characteristics of low
temperature and fast operation, large area fabrication and flexibility. They are
utilized in many applications, such as large area displays and curved surfaces
detection. At the same time, they also have a broad application prospect in the
field of biology and medicine.
In 1989, F.F. So et al. devised organic thin films by using small organic molecule
perylenetetracarboxylic dianhydride (PTCDA) [35]. They deposited the film
between Si substrate and ITO and succeeded in fabricating organic-inorganic pho-
todetectors. Subsequently, organic polymer detectors and organic thin film multi-
layer visible light detectors with high bandwidth were produced. In 2008, Ramuz
et al. developed visible region detectors with polythiophenes (P3HT) as donor and
fullerene derivatives (phenyl-C61-butyric acid methyl ester: PCBM) as
receptor [36].
According to the device structure, organic photodetectors are divided into
two-terminal devices and three-terminal devices. Two-terminal devices include
organic photodiodes and organic photoconductors, while three-terminal devices
include organic phototransistors. The working principle of organic photodetectors
involves photovoltaic effect, but the devices need to be applied negative bias to
broaden the depletion layer of PN junctions, which is different from photovoltaic
devices. As light shines on, electron-hole pairs will be generated in the absorption
region, whose width is related to the incident light intensity. The generated electrons
and holes move rapidly to the electrodes in the depletion layer, and photocurrent will
be generated as long as the external circuit is connected. However, the carrier
diffusion rate outside the depletion layer is low, which affects the response speed
and restricts its application in high frequency devices. Photoconductive detector is a
kind of detector with simple structure, which utilizes photoelectric effect. External
illumination generates electrons and holes within semiconductor materials. As they
move toward the contact electrodes at both ends, photocurrent appears [37]. Organic
phototransistors are capable of detecting light intensity and wavelength by detecting
the variation of source and leakage current of the transistor when external light
shines on semiconductor layer of the transistor.
Semiconductor photodetectors usually adopt direct bandgap materials as sensitive
materials, because they have high stimulated absorption rate. Nowadays, the main
characteristics of organic semiconductor materials in organic photodetectors are high
absorption coefficient, variety of materials, low charge mobility, and high
anisotropy [38].
Organic photodetectors are convenient to modulate, capable of integration, selec-
tive to light wave band, simple to fabricate, and yielding high quantum efficiency.
1912 Y. Shi et al.

Besides, there exit various choices of organic semiconductors. The research hotspot
of organic photodetectors is developing new materials and optimizing device struc-
ture to improve sensitivity and charge collection efficiency.

Fig. 87.15 Electron donors

commonly used in organic
solar cells

Fig. 87.16 Commonly used

electron acceptors in organic
solar cells
87 Flexible Semiconductor Devices (FSD) 1913

Organic Solar Cells

Organic solar cells (OSCs) are novel devices, which apply organic semiconductor
materials with photosensitive properties to solar cells. Being similar to inorganic
solar cells, the working principle of organic solar cells is based on the photovoltaic
effect of PN junctions. However, organic solar cells have unique advantages: low
cost, easy producing process, and capability of fabricating large-area flexible
devices, which have attracted worldwide attention and become a spotlight for
development and research [39].
The principle of OSCs bases on the photovoltaic effect of organic semiconductor
PN junctions. The battery absorbs photons under sunlight. When the energy of the
photons is sufficient to excite the valence electrons into free electrons, free holes
electrons are generated correspondingly, thereby forming a hole-electron pair.
Within a heterojunction which consists of different types of semiconductor material,
the heterojunction dissociates the holes and electrons. Organic p-type materials serve
as electron donors, possessing a higher and highest occupied molecular orbital
(HOMO) to inject holes; organic n-type materials act as electron acceptors with
lower and minimum unoccupied molecular orbital (LUMO) levels, which is ideal to
inject electrons. Figures 87.15 and 87.16 are common organic electron donors and
acceptors.
Improving the efficiency of OSCs is a key issue among current research. Focusing
on the source of battery energy loss is an easy way to increase efficiency. According
to the research, energy loss of OSCs is due to collection of carriers and transport of
holes and electrons. Therefore, the methods to improve OSCs in the future are as
follows: D/A doping with photosensitive small molecules; searching for better
electrode material; using a hole blocking layer; using a Phenyl-C61-butyric acid
methyl ester (PCBM) layer [40]; etc.
In an integrated circuit system, OSC can serve as energy source. Because it is not
limited by a fixed power source, it is of great mobility and capable of achieving self-
power supply for an integrated circuit system. The flexibility of the OSC makes it
easier to process than inorganic solar cells, which meets the diverse needs of
increasingly updating integrated circuit systems [41].

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Integrated Microsystem Technology
88
Wei Wang, Haixia Zhang, and Zhenchuan Yang

Contents
Implantable Microsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916
Nano Energy Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
Bulk Silicon Micromachining Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
Surface Silicon Micromachining Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918
Lithographie-Galvanoformung-Abformung (LIGA) Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1919
Smart Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921

Abstract
With the development of integrated circuit technology, the functionality and
complexity of CMOS circuitry increase greatly. It is important to integrate
different materials and device technologies to create integrated micro and nano
systems. Integrated microsystem technology has been developed to integrate the
devices and components into microsystems that meet the high-performance
requirements. Integration of microelectromechanical systems (MEMS) devices
with silicon CMOS enables new high-performance integrated circuits, enhancing
the capabilities of existing systems for a wide range of applications. Several
integrated microsystem technologies, including Implantable microsystem, nano
energy devices, bulk silicon micromachining process, and others, are discussed in
this chapter. The progresses and main applications of the microsystem technology
are briefly described.

W. Wang
Peking University, Beijing, China
Institute of Microelectronics, Peking University, Beijing, China
H. Zhang · Z. Yang (*)
Institute of Microelectronics, Peking University, Beijing, China
e-mail: Z.yang@pku.edu.cn

© Publishing House of Electronics Industry 2024 1915

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_88
1916 W. Wang et al.

Keywords
MEMS · Implantable microsystem · Nano energy devices · Bulk silicon
micromachining process · Surface silicon micromachining process ·
Lithographie-galvanoformung-abformung (LIGA) process · Smart sensors

Implantable Microsystem

Implantable microsystems are micro/nano devices and systems that can be used in
the body for a long time and can achieve specific bio/medical functions, which is one
of the important research directions of micro/nano technology. Unlike the demand-
ing requirements of low-cost micro/nano devices for consumer electronics and
wearable device applications, implantable microsystems can afford higher
manufacturing costs due to their special values in clinical applications. The devel-
opment of implantation microsystems at all costs to achieve specific functions has
also driven the advancement of related MEMS techniques. In addition, the long-term
in vivo implantation also sets strict requirements for the biocompatibility and
physiological environment compatibility of materials, energy collection, storage,
and supply of device, which also promotes the development of related micro/nano
techniques.
Currently, the main implantable microsystems include cochlear implants, artifi-
cial retinal chips, implantable tonometers, nerve stimulation/control microsystems,
implantable drug release pumps (including intraocular drug pumps, insulin pumps,
etc.), etc. In addition, system packaging, energy harvesting, and signal processing
and transmission are key issues in the implantable microsystems.
In order to be compatible in vivo with soft tissue, most implantable microsystems
are developed based on a flexible MEMS strategy. Parylene C, which has been
approved by the FDA of US, is the main substrate material for current implantable
microsystems, such as the parylene C-based flexible microelectrode array for artifi-
cial retina [1]. Implantation-grade polydimethylsiloxane (PDMS) is also commonly
used in implantable microsystems for certain highly flexible applications, such as
oxygen transporter for retina in clinical treatment [2].
Packaging is the key challenge for implantable microsystems. On the one hand,
most implantable microsystems require direct contact with biological tissue to
execute functions such as microelectrode stimulation and signal acquisition; there-
fore the long-term implantation may induce degradation of the electrical properties
of the electrode interface due to tissue hyperplasia on the surface. On the other hand,
long-term implantation may cause tissue fluid to penetrate into the implantable
system. Tissue fluid with high ion concentration will severely affect the performance
of control circuits inside the implantable system. Therefore, the isolation of tissue
fluid is another key issue that must be addressed in the development of implantable
microsystems.
Most implantable microsystems are active microsystems and thereby consuming
energy to perform specific functions, including electrical loading, mechanical
88 Integrated Microsystem Technology 1917

motion, signal processing and transmission. At present, such problems have been
solved to some extent by near-body wireless transmission, but higher efficiency,
higher power energy transmission, stable and reliable energy storage are still the
keys to current energy management systems for implantable microsystems.
Signal processing circuit is another important component for implantable micro-
systems, especially for implantable microsystems that rely on large-scale microelec-
trode arrays for high-resolution stimulation or signal acquisition, such as artificial
retina chips.

Nano Energy Devices

Nano energy technology refers to methods that adopt nano materials or nano devices
to realize harvesting, converting, storing, and utilizing of energy. Researching on
nano energy technology explores the physical mechanisms for harvesting,
converting, storing, and utilizing of energy on the nanoscale, which is not only an
important way to solve the problem of energy supply for micro/nano devices and
systems, but also a crucial support for stability and reliability of micro/nano devices
and systems. Nano energy is significant to both applications such as implantable
microsystems, IoT sensor nodes, portable/wearable devices, and some important
energy technologies like battery (including fuel cells), generation and storage of
hydrogen, and photovoltaic technology [3].
Nano energy devices can be divided into two parts according to their functions.
One part is the generator, which can harvest energy from the surrounding environ-
ment and convert it to electricity energy via various modes of energy conversion [4],
including triboelectricity (mechanical friction), piezoelectricity, electromagnetism,
thermoelectricity, photoelectricity, etc. Second part is micro-scale energy storing
devices like micro supercapacitors and micro-lithium battery, which occupying a
tiny area but storing a certain amount of energy, are able to power micro/nano
systems like micro electric devices and wireless networks. In recent years, from
profound studies on physical mechanism of energy generation process, it is found
that Maxwell Displacement Current containing the contribution of time-varying
slight motion of charges bound in atoms and dielectric polarization in materials is
an important way to generate nano energy. Based on this, novel nano energy
technologies such as piezoelectric nanogenerators and triboelectric nanogenerators
have emerged [5].
The key of nano energy lies on the cross-fusion of materials science, physics, and
micro/nano system technology, which is the typical interdisciplinary research.

Bulk Silicon Micromachining Process

The bulk silicon micromachining process is one of the main silicon micromachining
[6] to fabricate MEMS devices. The bulk silicon micromachining process mainly
refers to a method of selectively removing silicon material to obtain a microstructure,
1918 W. Wang et al.

which is usually a three-dimensional structure. The bulk silicon micromachining

process could be anisotropic etching, i.e., a specific chemical reagent (either liquid or
gas) is used for orientation selectively removal of silicon substrate. Commonly used
wet etching reagents include potassium hydroxide, tetramethylammonium hydrox-
ide, and HNA; the physical/chemical reaction can be applied to achieve anisotropic
dry etching (such as deep reactive ion etching, i.e., DRIE). In addition, isotropic
etching (such as HNA etching solution, a combination of hydrofluoric acid, nitric
acid, and glacial acetic acid) and etching (gaseous corrosion without bias, such as
XeF2) are also widely used in bulk silicon micromachining to prepare three-
dimensional silicon structures and devices.
An important parameter of the bulk silicon micromachining process is the
selectivity of the mask and the substrate during the etching. The selectivity directly
determines the geometry that the bulk silicon micromachining process could reach,
which is not only affected by the mask material and its preparation method, but also
the etching solution agent composition, etching temperature, stirring degree, bias
voltage, and the equipment used. Etching with a self-stop controllability can be
obtained by a specific mask/substrate combination, which further improves the
control precision and robustness of the machinable geometry.
Single-crystalline silicon ensures the same anisotropic wet etching processes
following the crystal orientation, which can reach the target structure after a careful
predetermined design. Silicon wafers with different crystalline orientations require
different designs.
Recently, with the rapid development of silicon micromachining capabilities and
the in-depth understanding of silicon-based physicochemical properties, bulk silicon
micromachining processes have evolved towards a faster, higher geometrical control
capabilities and three-dimensional curved microstructure fabrications. For example,
according to the data from SPP Process Technology Systems Ltd. (SPTS) in 2016, the
silicon dry etching rate based on the Bosch etching principle can exceed 37 μm/min.
Devices fabricated by the bulk silicon micromachining process include comb-
type microgyroscopes and accelerometers, pressure gauges, etc.

Surface Silicon Micromachining Process

The surface silicon micromachining process is an important method of the silicon

micromachining [7], which refers to the combination of multilayer deposition and
their selective removal on silicon substrate to achieve thin film-shaped structure. The
surface silicon micromachining process mainly obtains the final microstructure
device by depositing, etching different structural layer/sacrificial layer materials,
where polysilicon is usually used as the structural layer material, while silicon oxide
as the sacrificial layer material. The thickness of each layer is on the micrometer
scale or smaller, and the final device is also at this size range. Recently, with the
repaid development of microfabrication technique, some low-cost substrates are
implemented to reduce the cost. For example, many devices such as thin-film
88 Integrated Microsystem Technology 1919

transistors (TFTs) or thin film solar cells that are currently implemented by surface
micromachining processes use polyethylene terephthalate (PET) as the substrate.
The key technique of the surface silicon micromachining process is the etching-
based release techniques of the sacrificial layer. Since the thicknesses of the struc-
tural and sacrificial layers are usually small, the surface tension plays an important
role during the releasing process, especially during the final drying process. Adhe-
sion of the thin-film-shaped structure can lead to device failure. In order to avoid this
issue, it is generally necessary to optimize the device structure, such as optimizing
the sacrificial layer thickness, designing according releasing holes to facilitate the
exchange of etchant and reagent, and designing the support structures so that the
contact area is reduced when the adhesion occurs so as to avoid device failure. In
addition, the use of sublimation (such as ethanol/CO2 combined method) for struc-
ture releasing can significantly reduce the structural adhesion caused by surface
tension during drying. Studies have shown that the hydrophobic surface of the
microstructure is able to reduce the adhesion.
Another issue that should be taken into consideration during the surface silicon
micromachining process is the stress mismatch between the multilayer materials,
such as the thermal stress mismatching generated during the thermal process caused
by the mismatch of the thermal expansion coefficients of used materials. Therefore,
careful selection of materials is required for combination and the structure should be
optimized when applying surface silicon micromachining. Recently, a variety of
flexible three-dimensional silicon structures have been developed by the methods of
stress control.
Devices fabricated using surface silicon micromachining processes include accel-
erometers, flexible multi-channel nerve electrodes, and nano-relays.

Lithographie-Galvanoformung-Abformung (LIGA) Process

Lithographie-galvanoformung-abformung (LIGA) process is a special micro-

electromechanical system process based on X-ray lithography. X-ray deep synchro-
tron lithography is used to produce a photoresist structure with an aspect ratio of
500 with a smooth side wall and the submicrometer scale parallelism deviation. The
photoresist is then used as metal plating mold, thereby transferring the photoresist
structure into a metal mold. The metal mold then performs polymer production such
as injection molding to achieve low-cost manufacturing of nanometer scale polymer
structure.
The traditional LIGA process relies severely on expensive X-rays as light source
to obtain a very high aspect ratio photoresist structure. The mask of X-ray lithogra-
phy is also extremely complicated and costly, which impedes the applications of
LIGA. Recently, the traditional X-ray lithography is replaced by low-cost thick-film
lithography, which is often referred as quasi-LIGA technique. The most representa-
tive approach is UV-LIGA process, where UV source light enables the fabrication of
high aspect ratio photoresist (such as SU8, KMPR, etc.) microstructures at a
relatively lower cost. Electroplating injection molding and other operations, which
1920 W. Wang et al.

has become the main direction of LIGA technology development, can be fulfilled
from such photoresist structures of high-aspect ratio [8].
The main advantage of LIGA/quasi-LIGA process is its capability to fabricate
microstructures with large aspect ratios. It can realize metal and polymer devices
with complex structures, such as micro-springs and special-shaped metal nozzles,
metal double-layer micro-gears, metal inertial devices, etc. Quasi-LIGA process has
the characteristics of low cost, mass production and good repeatability, which is one
of the important ways to develop metal or polymer MEMS devices, especially micro
devices requiring high aspect ratio structures.

Smart Sensors

Smart sensors are devices that can provide specific information acquired with
sensing elements from the environment and processed with the integrated storage
and processing unit. These sensors generally include sensors used for information
acquisition, information processing units used for information processing, as well as
other auxiliary functional units. Owing to their information processing capabilities,
smart sensors can automatically and more precisely acquire information in the
working environment, and are widely demanded on wireless sensor networks,
battlefield reconnaissance, environment inspections, etc.
With the rapid process of micro-nanoelectronic fabrication technologies and
integrated micro/nano systems, smart sensors are usually manufactured with inte-
grated micro-nanofabricaiton technologies to accomplish multi-functional and high-
density integration. One or more sensing structures with different functions are
integrated with signal conditioning circuits and/or control circuits in one unit.
Representative integrated smart sensors include integrated pressure sensors, inte-
grated temperature sensors, inertial measurement units, etc.
One key technology to implement the integration of smart sensors is the integra-
tion processes for sensing structures and signal conditioning circuits. Currently, the
signal conditioning circuits are mostly fabricated with CMOS process in the main-
stream integration processes. According to different integration approaches, the
integration technologies for smart sensors can be either monolithic integration or
multi-chip integration.
For monolithic integration, the sensing structures and signal conditioning circuits
are co-designed and co-fabricated on a single chip. A well-developed monolithic
integration technology can minimize the influences of parasitic effects introduced by
interconnection wires between different sensor units, improve performances, and
reduce chip size and total fabrication cost. However, due to the requirement conflicts
between CMOS processing steps and micromachining processing steps on pro-
cessing temperature, cleanness, etc., monolithic integration technologies have to
deal with the challenges of complicated process, long development cycle, etc.
Depending on how the micromachining process steps coordinated with the
standard CMOS process sequences, the monolithic integration technologies can be
classified as pre-CMOS (one or more micromachining process steps are carried out
88 Integrated Microsystem Technology 1921

before CMOS process), hybrid-CMOS (the micromachining process steps are in

between the standard CMOS process sequences), or post-CMOS (the micro-
machining process steps are carried out totally after CMOS process) [9]. The
pre-CMOS and post-CMOS integration processes can reduce the restrictions on
micromachining process parameters, however, in the cost of modified CMOS
process sequences or parameters. It normally requires specific process capabilities
instead of readily available standard CMOS foundry services. The representative
work is the iMEMS integration process developed by Analog Devices Inc. The post-
CMOS monolithic integration technologies can use standard foundry services to
accomplish the circuits, the micromachining processes are carried out afterwards.
One of the representative post-CMOS technologies is the integration process used in
MEMSIC’s convective accelerometer products.
Different to the monolithic integration technologies, multi-chip integration tech-
nologies use specific integration techniques to cooperate the separately designed and
fabricated sensing chips and CMOS circuit chips. Since it has no restrictions due to
the conflicts of process conditions in co-fabrication, each chip can be developed and
optimized separately, leading to shortened development cycle. With the advance-
ments of TSV (Through Silicon Via) and other 3D integration technologies, the
multi-chip integrated sensors become more competitive regarding chip size,
cost, etc.
With the advancement of microelectronics and sensor integration technologies,
the smart sensors’ capabilities on information acquisition and processing have made
great process, leading to higher precision, higher reliability and lower cost, as well as
multi-functional capabilities. Hence, the industrial and consumer applications of
smart sensors have had a rapid growth in the past decade. The motion processing
unit (MPU) developed by STMicroelectronics is one representative of the smart
sensors based on MEMS technologies, which include triaxial compass, accelerom-
eters, gyroscopes, and temperature sensor. It can directly obtain the information of
user’s speed, gesture, etc., and has already widely used in many smart devices.

References
1. D.C. Rodger, Y.-C. Tai, IEEE Eng. Med. Biol. 24(5), 52–57 (2005)
2. D. Kang, K. Murali, N. Scianmarello, et al., IEEE International Conference on Micro Electro
Mechanical Systems (IEEE, Estoril, 2015)
3. Nano energy. https://www.journals.elsevier.com/nano-energy
4. Z.L. Wang, On Maxwell’s displacement current for energy and sensors: The origin of
nangenerators. Mater. Today 20(2), 74–82 (2017)
5. H.X. Zhang, Nano Energy 11, 304–322 (2015)
6. G.T.A. Kovacs, N.I. Maluf, K.E. Petersen, Proc. IEEE 86(8), 1536–1551 (1998)
7. J.M. Bustillo, R.T. Howe, R.S. Muller, Proc. IEEE 86(8), 1552–1574 (1998)
8. H. Guckel, Proc. IEEE 86(8), 1586–1593 (1998)
9. O. Brand, G.K. Fedder, CMOS-Mems (Wiley, Weinheim, 2005)
Advanced Characterization and Testing
Techniques 89
Runsheng Wang, Jianhua Feng, and Jiayang Zhang

Contents
Conductive Atomic Force Microscope (C-AFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1924
Atom Probe Tomography (APT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925
Inelastic Electron Tunneling Spectroscopy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
Technology of Femtosecond Lasers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
Power-Aware Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
3D IC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
Embedded Core Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1931
Defect Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1933
Adaptive Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934
Hardware Security and Trust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1936
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1937

Abstract
With the rapid development of integrated circuit process technology, advanced
electronic materials are widely applied in the IC devices. The advanced material
characterization technologies are used to research and develop new electronic
materials, especially for the characterization of nanoscale materials or in extreme
experimental conditions. Meanwhile, as the IC chip integration continues to
increase, the function of the chip is becoming more and more complex, and
more requirements are put forward to the test of IC chip. This chapter focuses on
the advanced material characteristics and IC testing techniques, such as conduc-
tive atomic force microscope, atom probe tomography, inelastic electron tunnel-
ing spectroscopy, technology of femtosecond lasers, power-aware Testing, 3D IC
testing, etc. The principle and application of advanced characterization and
testing techniques are discussed.

R. Wang (*) · J. Feng · J. Zhang

Institute of Microelectronics, Peking University, Beijing, China
e-mail: wrs@pku.edu.cn

© Publishing House of Electronics Industry 2024 1923

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_89
1924 R. Wang et al.

Keywords
Conductive atomic force microscope (C-AFM) · Atom probe tomography
(APT) · Inelastic electron tunneling spectroscopy · Technology of femtosecond
lasers · Power-aware testing · 3D IC testing · Embedded core test · Defect
tolerance · Adaptive test · Hardware security and trust

Conductive Atomic Force Microscope (C-AFM)

Conductive atomic force microscope (C-AFM) is an improvement of atomic force

microscope (AFM) and scanning tunneling microscope (STM) which has higher
spatial resolution. C-AFM can measure the surface roughness and conductivity
distribution of the semiconductor sample, thus, it is widely used in the research on
the crystal orientation and grain boundary of polycrystalline materials [1].
The structure of C-AFM is illustrated in Fig. 89.1. Unlike the sharpened wire/tips
of the STM, the C-AFM has a conductive cantilever with a silicon probe coated with
metal or metal alloy (such as Pt-Ir alloy) on the bottom. When the probe approaches
the surface of the sample and the repulsive force of the sample and prone tip will
cause the cantilever to bend. A high spatial resolution surface topography image can
be obtained by the measurement of the system driven force and the distance between
the tip and the surface. At the same time, a negative voltage is applied between the
sample and the probe. By measuring the amount of tunneling current between them,
the conductance value around the contact point of the probe can be calculated,
thereby obtaining the surface conductance distribution of the sample. Since the
current through the cantilever can reach several pA, a current amplifier is required
to suppress the electrical noise to several fA.

Fig. 89.1 Schematic of C-AFM structure

89 Advanced Characterization and Testing Techniques 1925

C-AFM has two operation modes: imaging mode and spectral mode. In routing
imaging mode, the probe tip scans over a small area (typically a few square microns)
on the sample and applies a negative bias to collect electrons that tunnel from the
sample to the probe. The reason for choosing the negative polarity is as follows. One
is that in this case the electron will tunnel the barrier from the conduction band to the
Si/Oxide interface rather than the higher barrier between conduction band and probe
tip/Oxide interface. Second, the emission area of the substrate implant is uniform and
depends primarily on the contact area of tip with the sample. In contrast, the
emission area depends on the shape of the tips in the case of tip injection. During
the measurement, the tip is in contact with the sample. And when the study material
is hydrophilic, the tip drags the water and other contaminants that adsorbed on the
surface to move. The applied voltage induces a strong electric field between the tip
and the substrate to ionize the water, and produce OH . If the tip is at a low potential,
OH ions are adsorbed to the surface of the sample, causing the surface to the
oxidized and break the circuit.
In the spectral mode, the tip is stationary while scanning the voltage applied
between the tip and the sample, thus obtaining current-voltage characteristics from
the tiny regions of the sample, and extracting information about local electronic
properties, such as local state density and so no.
Unlike STM, C-AFM can be used of the surface characterization of insulating
materials. In addition to the most basic surface topography and conductivity test, it
can also be used for dielectric property analysis such as ultra-thin oxide film
breakdown characteristics analysis, nano-capacitance measurement, and even for
nanoscale etching.

Atom Probe Tomography (APT)

Atom probe tomography (APT) is a three-dimensional imaging technology and

chemical composition measurement material analysis method, which can provide
atomic scale resolution (0.1–0.3 nm in depth and 0.3–0.5 nm in lateral direction) in
nanoscale devices [2].
The first generation of atomic-probe filed ion microscopy (APFIM) or
one-dimensional atom probe (1DAP) was proposed in the late 1960s [3]. A
1–2 mm filed ion detector is used for the entrance of spectrometer, a field or voltage
pulse is applied to evaporate the atoms, capable of processing 50,000 atoms. In 1982,
Kellogg and Tsong introduced a method of replacing voltage with laser pulses for
evaporation [4]. Due to the instability of early lasers, the method was not used on a
large scale. The second generation of APT was introduced in the 1980s. A variety of
space-sensitive single-atom detectors [5] have been used. This atomic probe has a
10–20 nm lateral view of sample and a data set of millions of atoms. The latest
generation named local electrode atomic probe (LEAP) detector was introduced
commercially by Kelly et al., the main advantage of the local electrode is that it
enables standing wave and pulse voltage with lower amplitude and further enhances
the field of view. The working principle of LEAP is shown in Fig. 89.2.
1926 R. Wang et al.

Fig. 89.2 Work principle of LEAP

LEAP needs to accurately align the apex of the sample with the central hole in the
local electrode. Since the local electrode increases sample position stability, and
the detector has a wider field of vision, the ability to rotate the sample to select the
position on the surface is not necessary. This avoids using field ion microscopy at the
beginning of the experiment. In voltage pulse mode, the test was carried out under
ultra-high vacuum conditions. The positive voltage residing on the sample was
increased and a negative pulse was applied to the local electrode for field evapora-
tion. The final alignment is performed by reducing the distance between the samples
to concentrating the ion signal on the detector, until the ion signal fills the detector. In
laser pulse mode, the precise position and focus of the laser beam is adjusted under
computer control while field evaporation is monitored to ensure that only the apex
regions of the sample are targeted. The rest of the imaging and analysis principles are
the same as the previous mode.

Inelastic Electron Tunneling Spectroscopy

Inelastic electron tunneling spectroscopy (IETS) is a method of recording and

analyzing the tunneling current and voltage of a metal-insulator-adsorber-metal
structure to obtain accurate vibration and electronic spectrum information in the
system, such as magnons and phonons. IETS has high resolution and high sensitivity
[6]. At the same time, the harmonic and combined energy bands in this method have
89 Advanced Characterization and Testing Techniques 1927

little effect, making the spectral identification simpler than the infrared and Raman
spectra. Optical ban transitions can also be observed using IETS [7]. Since the
spectral intensity of the oxide is weaker than that of the adsorbate, the spectrum of
the adsorbate can be obtained in the infrared region of the oxide spectrum. The
spectrum covered by IETS is very large (50 to 19,000 cm 1) which make the
measurement more efficient.
When electrons pass through an oxide layer, some electrons can lose energy by
exciting the vibration of the oxide or adsorbate, which is an inelastic process that
often leads to additional tunneling paths. In the absence of any inelastic interaction,
the I-V curve is a smooth curve with a second derivative of zero. In a typical MOS
structure, there are a variety of inelastic modes, including phonons, various bonding
vibrations, bonding defects, and impurities. When the voltage applied across the
oxide layer causes the Fermi level split to equal the energy loss due to the inelastic
interaction of the tunneling electrons, the additional conductive path causes the slope
of the I-V characteristic curve to increase and the second derivative of the I-V curve
peak appears. The voltage position of the peak corresponds to the characteristic
energy of the inelastic interaction, and the area enclosed by the coordinate axis is
proportional to the intensity of the nonlinear interaction.
The tunneling electrons lose energy after inelastic interaction and increase the
effective tunneling barrier, and the subsequent tunneling probability also decreases.
In the IETS spectrum, the intensity of the peak due to inelastic interaction near the
cathode is less than the intensity of the peak near the anode due to similar interac-
tions, because the former electron tunneling electrons pass most of the potential at
lower energies. Thus a higher tunneling barrier was observed. That is to say, IETS
more preferentially reveals inelastic interactions near the anode [8]. This dependency
of bias polarity can easily be used to identify structural defect and bonding defect, at
two different interfaces inside a MOS structure.
Keeping the tip of the scanning tunneling microscope (STM) at a fixed position
on the surface and scanning the bias voltage, the I-V characteristic at that point can
be recorded. This technique is called scanning tunneling spectroscopy (STS). It is
assumed that the state density is a constant at the tip, and then its first derivative
gives information about the local density of states (LDOS) of the substrate. And the
second derivative gives the information about the vibration of the adsorbate in the
IETS, which is the reason the method is usually called STM-IETS. In this case, the
insulating oxide layer corresponds to the gap between the tip and the adsorbate.
STM-IET was first proposed by Stipe, Rezaei and Ho in 1998 [9]. Extreme low
temperature and extreme mechanical stability (the amplitude of the mechanical
vibration of the tip on the adsorbate must be within pm or less) requirements make
this technology difficult to achieve in experiments. In recent years, a new method
has used. In this method, a single molecule is used to make a molecular transport
junction between two electrodes with an adsorbate, sometimes with an additional
gate electrode in the vicinity of the molecule [10]. The advantage of this method
over STM-IETS is that the two electrodes are in direct contact with the adsorbate
1928 R. Wang et al.

rather than having a gap. The disadvantage is that it is very difficult to create and
identify a junction of exactly one molecule between the two electrodes in the
experiment.

Technology of Femtosecond Lasers

Femtosecond lasers are ultrashort electromagnetic pulses of fs (10 15 s) level

duration or smaller. Such pulses, commonly referred to as ultrafast pulses, have a
broadband spectrum and can be generated by a mode-locked oscillator. Femtosec-
ond lasers have very high instantaneous power and precise targeted focus posi-
tioning characteristics, which make it gradually applied in micro-nano processing.
Femtosecond laser pulses are generated by femtosecond lasers. Femtosecond
lasers are generally classified into bulk lasers, fiber lasers, dye lasers, semiconductor
lasers, and other types (such as color center lasers and free electron lasers). Most of
the pulses generated by the femtosecond laser cannot be used directly, until pro-
cessed by the subsequent chirped pulse amplification, frequency change, phase
matching, and compression shaping.
The research field using femtosecond laser technology mainly includes two
aspects. First, due to the ultrafast frequency of femtosecond laser, it can be applied
to the study of some ultrafast transient processes, such as femtosecond time-
resolved spectra, femtosecond chemistry, femtosecond biology, and so on. On
the other hand, since the femtosecond laser can provide a focusing intensity of
up to 1020 W/cm2, a light pressure of 1012 bar, an acceleration of 1021g, and a
magnetic field of 109 Gauss, it also becomes a means of providing extreme
experimental conditions, appearing in higher harmonics, laser plasma, laser
nuclear fusion/fission, and other strong field physics research. For example,
Ahmed H. Zewail won the Nobel Prize in Chemistry in 1999 for observing the
photo dissociation process of NaI with ultrafast lasers [11]. Using femtosecond
laser to bombard uranium ore with gold foil result in high-energy electrons
(>100 MeV), which can further cause nuclear fission of U, and obtaining Kr, Ba
and positron. This is the very first nuclear fission of U, and obtaining Kr, Ba and
positron, which is the first light-induced nuclear fission reaction discovered by
humans. It is also the first example of producing antimatter under the light drive.
Femtosecond lasers can also be used in advanced micro/nano-structured pro-
cesses to produce three-dimensional data storage devices, photonic crystals,
submicron-micro devices, and some special shaped optical waveguide devices
with the guidance of femtosecond two-photon polymerization. Nanoscale spring
structures have been made using this technology, and this achievement was
published in the 2001 Nature [12].
With the development of science and technology, the demand for femtosecond
lasers with higher frequency and higher energy is becoming more and more urgent.
Shorter pulse methods have also been proposed, such as dual-wavelength synchro-
nization technology, coherence and interference technology, high-order harmonic
superposition technology [13, 14], and so on.
89 Advanced Characterization and Testing Techniques 1929

Power-Aware Testing

As the integration or the components in an IC design and the size of the chip
continues to increase, the function of the chip becomes more and more complex,
the data volume and testing time of the chip test increase rapidly, and the power
consumption of the chip during testing is much larger than that in the working mode
[15]. Therefore, the chip will overheat, causing problems such as test errors,
reliability and yield, and even worse, burning the device. Therefore, Power-Aware
Testing has attracted widespread attention.
The main methods to reduce the power consumption of the chip during testing are
as follows.

1. The low-power automatic test pattern generation (ATPG) method, whose core
idea is to develop test vectors that minimize switching activity, significantly
reduces test power consumption without affecting area or circuit timing. At
present, ATPG-based low-power test vector generation methods mainly include
low-power X-filling [16], test vector ordering [17], and low-power vector gener-
ation mechanism [18].
2. The low-power test method based on scan design mainly includes four methods.
The first one is to set an input control module for the full scan circuit to reduce or
eliminate the switching activity of the circuit combination part. The second is
scan path segmentation, which can significantly reduce test power consumption
without increasing test time. The third is the scanning circuit conversion proposed
by Whetzel et al., by adding an adaptive circuit to block the scan control output
from the tester and converting it into independent scan control outputs to each
new scan path [17]. The fourth is to improve the clock structure, for example,
Sankaralingam et al. [19] proposed a full scan circuit with multiple scan chains,
so that some scan chains use their clocks to make part of the test set, while
Bonhomme et al. [20] proposed a technique based on a scan path of the gated
clock and a scan path fed by a clock tree.
3. The low-power test data compression method needs to reduce the scan power
consumption and the amount of test data during the test. At present, there are
three main types of data compression methods: linear decompression-based
schemes, broadcast scan-based schemes, and code-based schemes.

3D IC Testing

The 3D IC that based on through-silicon via (TSV) has developed rapidly in recent
years and is considered to be a technology with broad application prospects. 3D ICs
have some outstanding advantages: shortening interconnections, reducing power
consumption, increasing integration, reducing noise, and increasing circuit operation
speed, enabling new multi-function devices and circuit systems.
Despite the many advantages, the development of 3D IC has brought many
technical challenges, especially in testing. On the one hand, 3D IC vertical bonding
1930 R. Wang et al.

multi-layer chips, although the integration degree is greatly improved, due to the
space limitation of the package pins (i.e., the pins can only be arranged around the
chip), the number of pins used for testing is not increased in proportion. This will
result in relatively less resources for each module in the chip to be tested, reducing
the controllability and observability of the chip circuit, which greatly increases the
difficulty and complexity of the test. On the other hand, TSVs widely used in 3D
chip interconnects are susceptible to manufacturing defects [21]. At present, the TSV
process is not perfect enough, and it is urgent to improve the TSV yield. The new
defects introduced in the TSV manufacturing process bring in additional difficulties
to the test task.
Due to the special manufacturing process of 3D IC, the testing process is
relatively complicated [22, 23]. According to ITRS 2013, the 3D IC test process
mainly consists of four steps.

1. Pre-bond die test, which is a test on single chips before being integrated into
the stack, with the goal of increasing the yield of single chips and ensuring that
the failed chips do not enter the subsequent three-dimensional integration
process.
2. Mid-bond stack test, which tests on partial stacks and is mainly used to detect
defects that may occur during the bonding process.
3. Post-bond stack test, which is to test the complete stack to detect new defects in
wafer thinning, alignment, and bonding, and to ensure proper operation of the 3D
stack and TSV interconnect. After the bonding test, it is generally necessary to
comprehensively consider the Pre-bond die tests and Mid-bond stack tests, which
effectively reduces the testing cost. In addition, the 3D-IC integration degree
increases during the post-bond test phase, and the heat dissipation problem is
prominent, so effective test structure optimization is needed to improve the chip
heat dissipation efficiency.
4. Packaged test, after the completion of all chip stacking and final packaging, the
final full inspection of the 3D chip before leaving the factory.

For 3D ICs, the defect and failure models for traditional 2D ICs still need to be
considered in the test. In addition, due to the adoption of new processes, it is also
necessary to consider the fault model unique to 3D ICs. It mainly includes two
aspects [22]:

1. Defects related to TSV interconnection

TSV-related defects might occur either in the fabrication of the TSV themselves,
in the bonding of the TSVs to the next tier, or during the lifetime of the 3D stack. The
main problems that may arise are: During the fabrication of TSVs, micro-voids
might lead to weak opens in TSVs; Pinholes in the TSV oxide might lead to shorts
between TSV and substrate; Ineffective removal of the seed layer might lead to
shorts between TSVs. The bond quality might be negatively impacted by oxidation
or contamination of the bond surface, height variation of the TSVs, or particles in
89 Advanced Characterization and Testing Techniques 1931

between the two dies. Misalignment during bonding, in either x, y, or z direction,

might lead to opens or shorts.

2. New intra-die defects introduced by the 3D process

An important question is whether the 3D processing steps induce new defects, of

which the corresponding fault behavior is not covered by the conventional tests. For
example, wafer thinning is such a 3D processing step that can cause new defects.
Early results indicate degradation of some I-V characteristics, shifts in device
performances, and limited yield losses due to wafer thinning [24]. In addition,
thermal dissipation and thermo-mechanical stress may introduce new defects. In
densely packed stacks of thinned dies, the heat density might pile up quite high, and
has little way of escaping. The heat generated might easily impact the correct
operation of the various dies, especially since some dies are more heat-sensitive
than others. Due to the different coefficients of thermal expansion of the various
materials in the stack, the stack might also suffer from thermo-mechanical stress,
causing further malfunction.

Embedded Core Test

With the development of integrated circuit process technology and the improvement
of design ability, the whole system can be integrated on a single chip, namely, system
on chip (SoC). In order to improve design efficiency and shorten time to market,
Core IP reuse has become the main method of SoC design. However, it has brought
great difficulties to SoC testing based on embedded Cores.
In 1995, the IEEE Computer Society’s Test Technology Technical Council
(TTTC) began research on embedded core testing. In 1997, the Society established
the Embedded Core Test Working Group to develop Standard for Embedded Core
Test (SECT). In March 2005, the IEEE-SA Board of Directors passed the IEEE Std
1500 (IEEE Standard Testability Method for Embedded Core based Integrated
Circuits), which is a scalable standard architecture for enabling test reuse and
integration for embedded cores and associated circuitry. In July 2005, the American
National Standards Institute (ANSI) passed the formal standard for embedded core
testing. In August 2005, embedded core testing standards was officially
published [25].
The SoC design for testability (DFT) of the embedded core requires the testability
of each core in the SoC design process. The testability includes the controllability
and observability of the tested core. Observability refers to the ability to complete
access to an IP core. The solution is to use the test access mechanism of the SoC to
achieve data transfer between the SoC pin and the embedded core boundary. This
involves the problem of matching the data bit width to the core port bit width, so a
test wrapper needs to be designed outside the core to match different bit width data.
Controllability refers to the ability to control the IP core. If you need to test an IP core
in the chip, you need to activate the IP core and put it in the test state. When the test is
1932 R. Wang et al.

completed, the IP core is put into normal working state. The method for
implementing this test is artificially defined. The IP core operating mode and the
corresponding control commands, in turn, achieve control of the IP core under test.
The IEEE 1500 standard of SoC test based on embedded core mainly includes
two parts: core test structure and core test language (CTL) [26–28]. The core test
structure consists of a wrapper, a test access mechanism (TAM), a test generator, and
a test responder. The wrapper refers to the logic surrounding the IP core. It provides a
standard test environment for IP core testing. The test access mechanism can be used
to transmit test information, including test stimulus and test response. The test
generator is used to generate the test vector of the core. The test responder is used
to analyze and compare the test results. The standard medium for exchanging test
information provided by the core test language (CTL) when testing IP cores.
The hardware test wrapper mainly uses a register to establish a test environment
for the IP core test. The registers are divided into three categories: the Wrapper
Instruction Register, the Wrapper Data Registers, and the Core Data Register.
The wrapper instruction register puts the test wrapper into test mode and initializes
the test activity of the surrounded cores; the Wrapper Data Registers include the
Wrapper Boundary Register and the Wrapper Bypass Register, and the Wrapper
Boundary Register is used for the data serialization and deserialization, the Wrapper
Bypass Register provides a short path through the core. When the data needs to pass
through the core in as few clock cycles as possible, the Wrapper Bypass Register can
be used; the Core Data Register refers to the core internal register surrounded by the
wrapper. The embedded core test hardware structure is shown in Fig. 89.3.
The IEEE Std 1500 only standardizes the test wrapper around the core and the
interface to one or more TAMs. To facilitate core test reuse and SoC level test
development, the IEEE Std 1500 Working Group also established a Core Test
Language (CTL) working group. It can describe the complex signal timing required
by various complex signals, layered models and core tests and their multiplexing at

Fig. 89.3 Embedded core Test Hardware Structure

89 Advanced Characterization and Testing Techniques 1933

the SoC level. The test information is passed including test methods, test patterns and
test specifications, test vector data, fault model and fault coverage data, testability
hardware information, and diagnostic information.

Defect Tolerance

In the device manufacturing process, defects will occur due to problems such as
imperfect processes. As the process size continues to shrink, the problem of device
failure caused by defects becomes more serious [29]. Manufacturing defects can be
roughly classified into global defects and local defects. Global defects are relatively
large-scale defects, such as scratches from wafer mishandling, defects from mask
misalignment, and over- and under-etching. Local defects are random defects from
materials used in the process and from environmental causes, mostly the result of
undesired chemical and airborne particles deposited on the chip during the various
steps of the process.
Both global and local defects contribute to the yield loss. It is worth noting that
not all defects will cause faults such as open or short circuits. The location and size of
the defect and the layout and density of the circuit will determine if the defect will
cause a fault. As shown in the top part of Fig. 89.4, the defect does not cause an open
circuit of the conductor, so it does not cause a fault, while as shown in the low part of
Fig. 89.4, it can cause an open circuit fault [30]. Therefore, when considering
increasing the yield, it is only necessary to pay attention to the part of the defect
that can cause a circuit failure.
In the case where process improvement cannot continue to reduce defects, to
increase the yield, it is necessary to introduce a defect tolerance method. Under the

Fig. 89.4 Critical section of diameter x missing metal defects [30]

1934 R. Wang et al.

submicron process conditions, the defect-tolerance technique first estimates the

distribution of defects by modeling, and then some defect-tolerance techniques for
yield enhancement that can be employed during the design and manufacturing
process according to the estimated results, such as added redundancy and floorplan
and layout modifications.
Under nanoscale process conditions, the defect density becomes higher due to the
smaller size of, for example, the nanowires and nanoelectronic, devices. At present,
the existing defect-tolerance techniques [31] mainly include two methods: defect-
aware tolerance design and defect-unaware tolerance design. The key step in the
defects-tolerant design is the defect-tolerant logic mapping (DTLM), that is, given
the defective device structure and the logic functions that need to be implemented,
through algorithm analysis, find the correspondence between the device structure
and the logic function, and adjust the connection between defective device structures
enables logic functions. In the defect unknown tolerance design, the existence and
location of defects are unknown. Therefore, it is necessary to identify common
defect-free subsets in the defective chip through algorithm analysis and apply the
defect-free subset to the design flow. Based on the defect-free subset, a trusted
connection is established to realize the defect unknown tolerance design.

Adaptive Test

The earliest appearance of adaptive testing can be traced back to 1993, which is a
method for predicting the yield of the device under test by data obtained from
neighboring dies [32]. Using this test method, the test length (or fault coverage)
could be adjusted to obtain the desired defect level, resulting in improved test times
or improved quality for the same test time.
Adaptive testing uses data collected during the IC manufacturing process to
influence, change, or “adaptively” test methods of a device or system, or even
change the manufacturing process of a device [33]. Adaptive testing not only uses
fixed limits, fixed test procedures and operations for IC testing [34]. Common
adaptive test methods include statistical process control and partial averaging tests,
and many other techniques are used in actual production processes. Adaptive testing
is often considered an advanced testing strategy that can be used to achieve quality,
yield, and cost targets that are not possible with normal testing methods.
The purpose of adaptive testing is to improve the quality and reliability of the
product, identify abnormal parts during the manufacturing process as early as
possible (preferably in wafer testing), and adding tests or changing test conditions
to screen for risk material. There are also some adaptive testing methods that can
selectively skip test content for specific materials to save costs. Effectively screening
for riskier materials minimizes the costs associated with customer support and failure
analysis, and provides early feedback to prevent other quality problems from
occurring.
Adaptive testing can modify a production test process in the following five
fashions.
89 Advanced Characterization and Testing Techniques 1935

1. Test conditions: modifying voltage or clock frequency, such as VDD

2. Manufacturing flows: adding or deleting test insertions, such as burn-in test
3. Test content: adding or deleting specific patterns or tests, such as transition faults
or IDDQ, respectively
4. Test limits: changing the pass/fail limits such as DC power or minimum VDD test
specifications
5. Test outcomes: changing the binning of some die based on post-test analysis of
the die test results

Based on the modified device and the point in time at which the modification is
made, adaptive testing can be divided into in situ, feedforward, feedback, and post-
test [35]. Figure 89.5 shows the model of the entire end-to-end process for the device
under test and the adaptive test application. Note that there is a possibility of
feedforward, in situ, feedback, and post-test in each of test steps. Although
Fig. 89.5 shows a simple view of the database, the actual database structure may
contain 2–3 databases of different levels, different capacities, and delays.
Because adaptive testing has the ability to deal with variation and takes into
account a potentially wide range of test data, adaptive testing has many advantages,
including reduced test costs, improved quality and reliability, improved yield learn-
ing, and improved test efficiency.
At present, the application of adaptive testing is still in the early stage of testing,
and more in-depth research is needed to complete complex adaptive testing. The
biggest benefit of adaptive testing – that it provides significant improvements and

Fig. 89.5 Adaptive test flow

1936 R. Wang et al.

cost savings over traditional methods – the adaptive testing is expected to become
increasingly valuable in the electronics industry.
The shared database and offline-analysis system are a central part of adaptive
testing. (RT A/O: real-time analysis and optimization; PTAD: post-test analysis and
dispositioning.)

Hardware Security and Trust

Hardware security refers to the hardware in the design and manufacturing process,
due to some unknown factors; the hardware finished product performance does not
match the original design and may cause a security threat.
The main threats to hardware security in integrated circuits are IP theft, IC
cloning, overproduction, hardware Trojans, and counterfeit ICs [36]. Among them,
IP theft, IC cloning, and overproduction attempt to directly steal the intellectual
property of the chip designer for illegal profit. The counterfeit IC obtains the key
information of the original chip through reverse engineering for forgery or directly
refurbishes the old scrapped chip, and then sells it to the market. These chips have
low performance and reliability are not guaranteed, which may easily lead to product
failure. Hardware Trojan refers to malicious modification and insertion of the
original circuit [37]. By inserting these malicious modules into the original circuit,
the hardware Trojan can perform functions that change the original circuit function,
leak confidential information inside the circuit, assist the software Trojan control
system, or directly physically destroy.
With the development of microelectronics and computer technology, IC has been
applied in all aspects of society, and hardware security is directly related to people’s
information and property security. In some key areas such as finance and defense, the
threat of hardware security can cause incalculable losses. Therefore, it is of great
significance to take effective measures to ensure hardware security and trust. Hard-
ware trust research includes two aspects, one is the effective detection of hardware
product security threats, and the other is the effective defense against potential
hardware security threats. Among all security threats, hardware Trojans can be
said to be the most important and complex security threats. Effective detection and
protection of hardware Trojans is an important means to ensure hardware security
and trust.
At present, hardware Trojan detection methods mainly include three methods:
destructive detection, logic test, and bypass testing. (1) Destructive detection refers
to the reverse section of the chip, and then compares the measured chip layout with
the real layout to determine whether the chip has been tampered with. This method is
generally time consuming and labor intensive, and the cost is high, and the detected
chip cannot be reused. Bao et al. [38] used the idea of machine learning to apply
support vector machine (SVM) and k-means clustering algorithm to Trojan detec-
tion, which improved the effectiveness of reverse engineering and the detection
efficiency of Trojan. (2) The logic test detects the hardware Trojan by applying an
excitation to the chip under test and then comparing the actual output to the design
89 Advanced Characterization and Testing Techniques 1937

output. Banga et al. [39] studied the excitation generation of Trojan detection, which
improved the coverage of Trojan detection and the observability of Trojans.
(3) Since the insertion of a Trojan may cause a change in the raw circuit bypass
parameters, the bypass testing detects the hardware Trojan by measuring circuit
bypass information (circuit delay, power, radiation, thermal signals, etc.).
In order to achieve active defense against hardware Trojans, the design for trust
(DFT) has also been extensively studied. The main idea of the chip’s credibility
design is to consider the defense and detection of the Trojan in the design stage of the
circuit. By processing the original circuit, it becomes more difficult to insert the
Trojan into the original circuit, or make the subsequent detection process of Trojans
test easier. Rajendran et al. [40] logically encrypt the circuit, increasing the difficulty
of the attacker’s Trojan insertion.

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Aerospace Microelectronics
90
Yuanfu Zhao, Suge Yue, Hongchao Zheng, and Liang Wang

Contents
Space Radiation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1940
Radiation Effects on Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1942
Radiation Hardening Technology of Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944
Radiation Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946
Simulation of Radiation Effects on Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951

Abstract
Integrated circuit (IC) devices play unique role in the field of aerospace technol-
ogy applications. This chapter introduces the space radiation environment and
radiation effect sensitivity of common orbits of current spacecrafts. The radiation
effects of space radiation on microelectronics devices are discussed and radiation
hardening technology and radiation test evaluation technology for integrated
circuits are described. The conventional simulation methods of Integrated Circuit
radiation effects are also addressed.

Keywords
Aerospace microelectronics · Space radiation environment · Radiation effect ·
Radiation hardening · Radiation evaluation

Y. Zhao (*)
China Academy of Aerospace Electronics Technology, Beijing, China
e-mail: Zhaoyf@vip.163.com
S. Yue · H. Zheng · L. Wang
Beijing Microelectronics Technology Institute, Beijing, China

© Publishing House of Electronics Industry 2024 1939

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1_90
1940 Y. Zhao et al.

Space Radiation Environment

The space radiation environment is classified into the extraterrestrial radiation

environment and the Earth radiation belt environment, as shown in Fig. 90.1. The
extraterrestrial radiation is composed of galactic cosmic rays and solar cosmic rays
released by the universe and solar activities, which constitute the source of the entire
space radiation environment. The Earth radiation belt is generated by the spiral
motion of charged ions, which are captured by the Earth’s magnetic field lines, and
the Earth radiation belt is the main radiation source that may cause reliability issue or
damage to the electronic system inside a spacecraft.
The Galactic Cosmic Rays (GCR) in the radiation environment of extraterrestrial
space refer to charged particles from outside solar system that have extremely high
energy and low-flux (particles/cm2
s), and most of them originate from the galactic
or other galaxies. The energy range of the charged particles is generally from tens of
MeV to hundreds of GeV, covering almost all elements in the periodic table. They
comprise about 87% protons, 12% alpha particles, and 1% heavy ions [1].
Solar Cosmic Rays (SCR) are high-energy, high-flux charged particle streams
released by the nuclear fusion reaction in the Sun. The energy ranges from 10 MeV
to 1000 MeV. The charged particle streams are mainly composed of 95% protons and
4% Helium nucleus (α particles), and 1% heavy ions [2]. The two main manifesta-
tions of the solar radiation to the Earth space are the solar wind and the solar flare.
The solar wind is electrical neutral plasma emitted from the outer atmosphere of the
Sun. It flows out of the outer surface of the Sun at a speed of 300–900 km/s. The
Solar flare is a sudden explosion that occurs in a local area of the solar atmosphere. It
emits high-energy protons or heavy ions from tens of MeV to several thousand MeV
in a short time. Solar flare is also called solar proton event. It has an activity period of
11 years, including 4 years of low activity and 7 years of high activity.
The Earth radiation belts, also known as the Van Allen radiation belts, come into
being when the charged particles of the galactic cosmic rays and the solar cosmic
rays are captured by the geomagnetic field. In addition, the belts are mainly

Fig. 90.1 Composition of the

space radiation environment
90 Aerospace Microelectronics 1941

controlled by solar activities, as shown in Fig. 90.2. The belts include two concentric
ring radiation particle zones. The inner belt extends to about 2.4 Earth radii
(RE) above the Earth, and mainly contains protons with energy from several MeV
to several hundred MeV and electrons with energy less than 5 MeV. The outer belt
extends from about 2.8 to 12 RE above the Earth, and consists mainly of electrons
with energy up to about 7 MeV and protons of a few MeVor less [3]. In addition, at a
height of 200 km above the South Atlantic and beneath the inner radiation zone
boundary, where the Earth’s magnetic field lines bend downward, there is a zone
with high-flux high-energy particles known as the South Atlantic Anomaly (SAA).
The main orbits of current spacecrafts include low Earth orbit (LEO), medium
Earth orbit (MEO), geosynchronous equatorial orbit (GEO), high Earth orbit (HEO),
Sun-synchronous orbit (SSO), Lunar Orbit, Mars Orbit, Interstellar Exploration
Orbits, etc. The design life of a spacecraft is generally between 1 and 15 years.
The environmental parameters and radiation effect sensitivity of common orbits are
shown in Table 90.1.

Fig. 90.2 Schematic diagram

of the Van Allen radiation
belts

Table 90.1 Environmental parameters and radiation effect sensitivity of main orbits
Single event sensitivity Total dose sensitivity
Orbit Galactic ray Solar ray Earth radiation belt Solar ray Earth radiation belt
LEO Medium Weak Strong Medium Strong
MEO Strong Strong Strong Strong Strong
HEO Strong Strong Strong Strong Strong
GEO Strong Strong Strong Strong Strong
SSO Medium Weak Strong Medium Strong
Lunar Strong Strong Weak Weak Weak
Mars Strong Strong Strong Weak Weak
1942 Y. Zhao et al.

Radiation Effects on Integrated Circuits

Space radiation particles which interact with integrated circuits in the spacecraft will
lose its energy and produce radiation effects in the integrated circuits. These radia-
tion effects are classified into ionizing radiation and NIEL (nonionizing energy loss)
effects. The ionizing radiation effects include Single Event Effect (SEE) and Total
Ionizing Dose effect (TID), while the NIEL effect mainly refers to the displacement
damage.
TID refers to the performance degradation of integrated circuits caused by the
accumulation of radiation dose [4]. The electron-hole pairs are generated by radia-
tion acting on the oxide dielectrics. The radiation-induced charge is dependent on the
non-equilibrium carriers’ transition, recombination, capture, etc. Affected by the
electric field, the generated electrons and holes begin to drift. The generated elec-
trons, due to their higher mobility, are swiped away rapidly, and some positive
trapped charges are finally left in the oxides. Radiation also induces interface-
trapped charges at the Si-SiO2 interface. TID will cause the threshold voltage shift,
mobility reduction, leakage increase, and delay change.
SEE refers to the soft errors or hard damages caused by the interaction between a
single particle and a sensitive region of an integrated circuit [5]. When an energetic
particle passes through a sensitive region of an integrated circuit, it will generate
charges along its track which will in turn be collected by electrodes, causing a
change in the logic state or damage to the integrated circuit. Figure 90.3 shows the
transient conductive path formed between the drain and the substrate after the
transistor is irradiated by energetic particles. Due to the different locations and
influences, the single event effects can be categorized into Single Event Soft Errors
and Single Event Hard Errors. Single Event Soft Errors include Single Event Upset
(SEU), Single Event Transient (SET), and Single Event Function Interrupt (SEFI);

Fig. 90.3 The transient

conductive path
90 Aerospace Microelectronics 1943

and Single Event Hard Errors include Single Event Latchup (SEL), Single Event
Burnout (SEB), and Single Event Gate Rupture (SEGR).
Displacement Damage effect (DD) happens when the atoms in the material or
crystal lattice are displaced by its reaction with injected particles. As a result, the
interstitial atoms and/or lattice vacancies are formed, causing carrier’s lifetime and
mobility to decrease, circuit performance to be degraded, and even the whole
integrated circuit to fail. The radiation effect sensitivity of typical circuits is shown
in Table 90.2.
As the silicon technology develops and the gate oxide thickness decreases, the
threshold voltage drift of the MOS transistor caused by the TID is gradually reduced
to a negligible extent, and the main aspect affecting the integrated circuit character-
istics is the parasitic leakage current. The multi-bit upset (MBU) and SET will be
more serious due to the reduction of feature size and critical charges, which make the
soft errors to become the primary problem for radiation-hardened nanometer CMOS
integrated circuits.

Table 90.2 Radiation effect sensitivity of typical circuits

Radiation
effect Types of effect Phenomenon description Typical circuits
Single event Single event The data errors of memory cell SRAM,DRAM,DFF
effect upset
Single event The data errors of multiple memory
multi-bit upset cells causing by the single particles
Single event The impulse response of specific AD, DA, SENSOR,
transient amplitude and period linear circuit, power
Single event The function interrupt during the ASIC, CPU, SOC,
function process FPGA
interrupt
Single event Abnormal current increases CMOS, BiCMOS
latchup circuits
Single event High current and the device burned BJT, Power
burnout MOSFET
Single event The gate rupture leading to a short Power MOSFET
gate rupture circuit
Single event Permanent error Non-volatile
dielectric memory
rupture
Total Regular effect Threshold voltage drift, leakage MOS circuit
ionizing increase
dose effect Enhanced low Current gain degrade, offset voltage Bipolar circuit,
dose rate effect and bias current increase BiC-MOS circuit
Displacement damage Sensitivity reduce, dark current CCD/CMOS sensor
increase
Gain degrade Bipolar circuit
Conversion efficiency reduce Solar cell
Threshold current increase [6] Laser diode
1944 Y. Zhao et al.

Radiation Hardening Technology of Integrated Circuits

The radiation hardening technology of integrated circuits is a measure to ensure that

the integrated circuit can work normally or has a long service life in a space radiation
environment, mainly including Radiation Hardening by Shielding (RHBS), Radia-
tion Hardening by Process (RHBP), and Radiation Hardening by Design (RHBD).
RHBS refers to adding coating materials for the outer package of the protected
integrated circuit to absorb and/or block a part of the radiation, in turn to reduce the
radiation dose deposited on the chip. The shielding materials, such as a tungsten-
copper alloy, are usually used to form a package or applied to the top and bottom of
the package (as shown in Fig. 90.4), which are effective for reducing electron
radiation but not effective for shielding proton. The advantage of this method is
that radiation-tolerant integrated circuits can be implemented by using commercial
chips through rapid external shielding. One of its disadvantages, however, is that it
has little or no shielding effect on the single-event effect caused by high-energy
particles, and another is that shielding materials obviously increase the weight of the
packaged integrated circuit.
RHBP refers to Radiation Hardening of integrated circuits by special IC fabrica-
tion process technology, or addition of dedicated process modules to standard
process lines, or adjusting standard process flows and conditions [8]. The special
process steps usually include doping, gate oxidation, isolation, passivation, etc.,
while the special materials or structures include SOI/SOS (shown in Fig. 90.5), thin
epitaxial silicon films, built-in capacitor and resistor materials, etc. The advantage of
this method is that it is hardened at the physical level, with no or little penalty on IC’s

Fig. 90.4 Special CQFP package construction to provide 360 deg. radiation protections [7]

Fig. 90.5 Structure of the

SOI device
90 Aerospace Microelectronics 1945

performance. The disadvantage of RHBP is the high cost of running and maintaining
a dedicated radiation-hardened process.
RHBD refers to using design techniques to ensure the radiation hardness of
integrated circuits during design process. The integrated circuits are generally
hardened by different levels of design such as layout, circuit, and logic/system. At
the layout level, a special structure, such as an annular gate or an H-shaped gate, a
guard ring, and a node-separated layout, can be used to improve the hardness of
integrated circuits to TID and SEL, and to reduce multi-bit upsets. The circuit level
hardening techniques usually adopt triple-modular redundancy (TMR), dual-
modular redundancy (DMR), dual interlocked cell (DICE, as shown in Fig. 90.6),
and other special circuit structure to reduce the susceptibility of a circuit to single-
event upsets and transients. The logic/system level radiation hardening techniques
include error correction coding (ECC), scrubbing, multi-thread redundancy, watch-
dog, etc. The advantage of RHBD is that high-performance radiation-hardened
integrated circuits can be implemented with state-of-the-art commercial CMOS
process technology and with relatively lower cost. Nevertheless, this method usually
introduces more penalties in chip area and power consumption.
With the rapid scaling down of IC process technologies, radiation-induced soft
errors have become more serious. Therefore, RHBD techniques are increasingly
popular [9]. With the standard process and the RHBD techniques, Beijing Micro-
electronics Technology Institute (BMTI) has established several radiation-hardening
design platforms including standard cell libraries and I/O libraries, as well as PLL,
SRAM, LVDS, SerDes, DDR, and other IPs. Based on the design platforms with
submicron, deep submicron, and nano-scale technologies, BMTI has developed a
series of general-purpose products, such as the microprocessor, field programmable
gate array (FPGA), memory, analog-to-digital converter, high-speed bus and inter-
face, and formed relatively complete product system of the aerospace

Fig. 90.6 DICE-structure radiation hardened storage cell

1946 Y. Zhao et al.

microelectronics in China. These radiation-hardened IC products play an important

role for the stable operation of satellites in orbit.
In practice, RHBS, RHBP, and RHBD can be applied in combination with each
other to improve the radiation hardness of ICs. The choice of radiation hardening
strategy will play a decisive role in the competitiveness of a radiation-hardened IC.

Radiation Test

The radiation test of integrated circuits is an experimental activity for obtaining the
radiation effect of integrated circuits under radiation exposure and verifying the
effectiveness of integrated circuit hardening techniques. Corresponding to radiation
effects, there are mainly three types of radiation tests: single event effect (SEE) test,
total ionizing dose (TID) test, and displacement damage (DD) test.
The SEE test is generally carried out with two types of particle sources in silicon:
heavy ions with a LET range of 0.4–120 MeV
cm2/mg, and protons with an energy
range of 0.01–200 MeV.
The test methods for single event soft errors of different types of integrated
circuits are shown in Table 90.3. The hardness indicators refer to radiation-related
parameters in specification of the products, while the other measurable items mean
the items that may also affect the circuit. The SEL test is usually judged by the
current of the integrated circuit under test, because an SEL is always accompanied
with a sudden current increase.
Heavy ion SEE tests are generally carried out in a tandem accelerator or a
cyclotron accelerator. According to the test standard [10], the ion range in silicon
needs to be greater than 30 μm, and the total irradiation fluence needs to reach
107 ions/cm2. For SEL, SEB, and SEGR tests, integrated circuits under test are
usually biased at the maximum operation voltage, while for SEU and SEFI tests,
integrated circuits under test are usually biased at the minimum operation voltage
and with the maximum clock frequency. Parameters such as SEE saturation cross

Table 90.3 The single event soft errors (SET/ SEU/ SEFI) test methods
Representative Hardness Other measurable
Category circuits Test method indicators items
Memory SRAM,DRAM, Write a specific pattern and SEU SEFI in the read-
PROM, FLASH, read back to compare threshold, write control
etc. whether an error has in-orbit error module
occurred rate of SEU
Analog AD, DA, RF, Monitor the analog or digital SET Disturbance
DC/DC, etc. output signals disturbance affecting
subsequent circuits
VLSI ASIC, CPU, Run in a specific mode/ In-orbit single Get SEU
SoC, FPGA, etc. program to determine if the event function performance with
function is normal error rate test mode
(SCAN/MBIST)
90 Aerospace Microelectronics 1947

section and effective LET threshold can be obtained from a fitted Weibull curve.
With these parameters, together with specific spatial orbit and environment model
(usually CREME-M3 for heavy ion, AP-8 or AP-9 for proton, etc.) and sensitive
body models (usually RPP, IRPP, MSVs, NSV, etc.), the error rate calculation
software (such as Space Radiation, etc.) can give the on-orbit single event error
rate of an integrated circuit.
The proton test is generally carried out with a proton accelerator. The proton SEE
is not easy to be induced by direct ionization since the proton LET is less than
0.6 MeV
cm2/mg (as shown in Fig. 90.7). However, the SEU LET threshold for
integrated circuits decreases as the process technology advances, for example, the
SEU LET threshold for a 65 nm SRAM is less than 0.3 MeV
cm2/mg, so the direct
ionization is able to induce SEUs for advanced process integrated circuits. The
proton SEE can also be induced by heavier secondary particles with high LET
from interaction between a proton and target materials, for example, the LET of
secondary silicon particles can be up to about 15 MeV
cm2/mg [11]. So the proton
SEE test is generally recommended to assess integrated circuits when their LET
threshold of SEU is less than 15 MeV
cm2/mg.
Conventional heavy ion and proton tests are wide beam tests, which are mainly
used for the overall evaluation of integrated circuits. In addition, heavy ion micro
beams and pulsed laser are used as an effective auxiliary test means to achieve
positioning and quantitative irradiation. At present, the micro beams test uses a μm-
level slit hole to reduce the beam area on the target integrated circuit, while the
pulsed laser experiments commonly use picoseconds and femtoseconds pulsed
lasers, which focus laser on semiconductors to generate photocurrents, with the
advantages of rapid energy change, precise positioning, low cost, etc. The map of

Fig. 90.7 The LET of proton direct ionization and secondary particles produced by proton in
Silicon
1948 Y. Zhao et al.

single event sensitivity, the SEU/SEL threshold can be obtained through the laser
test [12].
A TID test usually adopts 60Co γ source as a radiation source. TID sensitivity of
an integrated circuit is a function of irradiation bias and dose rate. A worst-case bias
is required to be found and applied to the integrated circuit under test. Integrated
circuits with different process technologies have different dose rate dependence. To
assess the radiation hardness of integrated circuits, the CMOS circuits generally
adopt a relatively high dose rate, 50–300 Rad(Si)/s, following a 50% over-dose
irradiation and a high temperature annealing. The bipolar and BiCMOS circuits
generally use low dose rate, 0.01–0.1 Rad(Si)/s for TID test, due to an effect called
enhanced low dose rate (ELDR) [13]. In the low dose rate test, over-dose irradiation
and high temperature annealing are usually not conducted. An electrical test is
needed before and after irradiation to judge if the integrated circuit passes the
TID test.
Displacement Damage (DD) test is generally carried out in the proton accelerator
or neutron source. The protons and neutrons of different energies have different
non-ionizing energy losses (NIEL), which can be converted into irradiation evalu-
ation fluence according to the displacement indicator of the integrated circuit under
test (usually equivalent to 1 MeV neutron fluence). As in the TID test, the electrical
test is also needed to judge if the irradiated circuit passes the DD test. Special safety
attention should be paid to neutron test, since the integrated circuits and boards
irradiated by neutron may be radioactive.
The test standards and main radiation source institutions of the three types of
radiation tests are given in Table 90.4.
Radiation test of integrated circuits reveals the relation between the parameters of
materials/integrated circuits and radiation effects through the way of experimental
measurements, which provides the basic information for radiation hardening. With
the development of integrated circuits, more challenges will be brought to the
radiation test of ICs due to the new technology such as more complicated function,
higher speed, new transistor structure, and more complex packaging.

Simulation of Radiation Effects on Integrated Circuit

Conventional integrated circuit simulation mainly focuses on a circuit’s function,

timing, and performance, while the radiation effects of the target circuit cannot be
obtained through simulation. Basically, the radiation effect simulation builds a
special radiation model, and simulates the radiation-induced parameter degradation
of a device or a circuit, through which the radiation hardness of the circuit can be
estimated during the design phase. Different from the radiation test which mainly
focuses on the radiation evaluation of the overall circuit, the radiation effect simu-
lation can obtain the microcosmic variation process of radiation induced damages or
errors.
90 Aerospace Microelectronics 1949

Table 90.4 Standards and facilities for radiation tests

Major research institutes providing sources of
Effect Test standard radiation
Single Event Effect (SEE) GJB 7242-2011 China: HIRFL, HI-13
ESCC 25100 USA: LBNL, BNL, TAMU, MSU
ASTM F1192 France: GANIL, CNRS, CPO (proton)
EIA/JESD 57 Italy: LNL, LNS
Belgium: UCL
Finland: FLNR
Russia: FLNR
Germany: GSI
Switzerland: PSI (proton)
Japan: RIKEN
Total Ionizing Dose Effect GJB 548B-2005 China: XTIPC.CAS, NINT, PKU,NIM
(TID) GJB 5422-2005 USA: Aeroflex RAD
MIL-STD-883K France: ONERA
ESCC 22900 Germany: Fraunhofer INT
ASTM F1892 Belgium: UCL
Spain: ALTER
Japan: RIKEN
Displacement Damage Effect GJB 9397-2018 China: CIAE, NINT, PKU,CSNS
(DD) GJB 548B-2005 USA: WNL, LBNL, Aeroflex RAD
GJB762.1-1989 Belgium: UCL
MIL-STD-750E Switzerland: PSI
France: CPO, CNRS
Italy: LNL
Germany: Helmholtz, Fraunhofer INT
Japan: RIKEN

The space radiation effect simulation includes three types: total ionizing dose,
displacement damage, and single event effect. The simulation of integrated circuits is
focused on SEE here.
The SEE simulation of integrated circuits can be categorized into at least three
levels: material-level, transistor-level, and circuit-level. The radiation effect simu-
lating methods of different levels are shown in Fig. 90.8. Early researches focused on
material-level physical simulation and 2/3-dimensional transistor-level simulation to
reveal the particle energy transport and charge deposition processes. Recent
researches mainly focus on mixed-mode transistor-level simulation and circuit-
level overall simulation to get the failure nodes and the radiation sensitivity of a
circuit [14].
At material-level, the physical simulation of interaction between radiating parti-
cles and materials is based on the Monte Carlo method [15]. Both the direct
ionization reaction and indirect ionization reaction (such as the elastic collision,
inelastic collision) can be simulated, and the particle trajectories and energy depo-
sition in the semiconductor materials can be obtained. In the direct ionization, after
heavy ions transferred their energy to the material through Coulomb force,
1950 Y. Zhao et al.

Fig. 90.8 A schematic diagram of radiation effect simulations at different levels

electron-hole pairs are generated along the particle trajectory. The indirect ionization
is the ionization interaction of the recoil nucleus or nuclear debris produced by the
strong interaction between the particles and materials. If the indirect interaction is
ignored, the simulation results may not match the experimental results for radiation-
hardened integrated circuits.
At transistor-level, some research works on cell radiation effect simulation was
usually carried out by a mixed-mode simulation method. With a built-in three-
dimensional physical model of the attacked transistor and SPICE model of other
transistors, the transient current and voltage variation of the target transistor and the
influence on the state of the target cell can be obtained by TCAD. Other researches
on cell simulation conducted complete three-dimensional simulations using software
such as TCAD tools from Synopsys and Cogenda. For example, three-dimensional
(3D) simulations of a DICE SRAM cell have been performed to obtain the SEU
cross section (shown on Fig. 90.9) [16].
At circuit-level, the simulation of radiation effects is usually based on the fault
injection method. A gate-level circuit model needs to be constructed firstly, and then
the propagating and masking process of soft errors are simulated by injecting
characterized errors into the gate-level circuit model. Through such a simulation,
the information such as the soft error cross section of the whole circuit and the
distribution of sensitive nodes can be obtained. Due to huge complexity of this kind
of simulation, at present there are still no mature circuit-level SEE simulation tools
available.
The radiation effect simulation has the technical advantages of preliminary
prediction, accurate positioning and low cost. Furthermore, the radiation hardness
of a circuit can be improved through design or process parameter modification
90 Aerospace Microelectronics 1951

Fig. 90.9 3D model and simulation result of a DICE structure

according to the information implied by simulation. It is necessary to further

improve the accuracy of radiation effect models, as well as to optimize simulation
methods and algorithms. The radiation effect simulation technology is an effective
means of radiation performance evaluation, which will play an increasingly impor-
tant role in the future.

References
1. E.R. Benton, E.V. Benton, Space radiation dosimetry in low-earth orbit and beyond. Nucl.
Instrum. Meth. 184B, 255–294 (2001)
2. R. Velazco, P. Fouillat, Radiation Effects on Embedded System (Springer, 2007)
3. A. Holmes-Siedle, L. Adams, Handbook of Radiation Effects, 2nd edn. (Oxford University
Press, 2007)
1952 Y. Zhao et al.

4. H.J. Barnaby, Total-ionizing-dose effects in modern CMOS technologies. IEEE Trans. Nucl.
Sci. 53, 3103–3121 (2006)
5. J. Gasiot, Radiation Effects on Devices: Total Ionizing Dose, Displacement Effect, Single Event
Effect, CERN Training: Radiation effects on electronic components and systems for LHC
(2016)
6. Y.F. Zhao et al., 200MeV proton damage effects on multi-quantum well laser diodes. IEEE
Trans. Nucl. Sci. 44(6), 1898–1905 (1997)
7. R.K.R. Sampan, Enhanced X-ray shielding device package, in 2005 MAPLD International
Conference, Washington, DC, (September 2005)
8. M. Alles, Process technology and hardening, in 2007 Nuclear and Space Radiation Effects
Conference Short Course (IEEE NSREC, July 2007)
9. Y. Zhao, S. Yue, X. Zhao, Single event soft error in advanced integrated circuit. J. Semicond.
36(11), 111001 (2015)
10. ASTM F1192: Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced
by Heavy Ion Irradiation of Semiconductor Devices (2018)
11. Z. Wen, G. Xiaoqiang, C. Wei, Analysis of micro / nano level SRAM SEE affect due to nuclear
reaction of protons and metal wiring layers. Acta Phys. Sin. 64(17) (2015)
12. Y. Chunqing, L. Fan, S. Yue, et al., The investigation on sensitive mapping of memory cell in
microprocessor. J. Semicond. 36(11), 114005 (2015)
13. MIL-STD-883K-Method NO.1019.8: Ionizing radiation (total dose) test procedure, Test
Method Standard Microcircuits (2016)
14. D. Munteanu, J.-L. Autran, Modeling and simulation of single-event effects in digital devices
and ICs. IEEE Trans. Nucl. Sci. 55(4), 1854–1878 (2008)
15. C.C. Foster, P.M. O’Neill, Monte Carlo simulation of proton upsets in Xilinx Virtex-II FPGA
using a position dependent Qctit with PROPSET. IEEE Trans. Nucl. Sci. 53(6),
2886–2894 (2006)
16. L. Liu, Y. Zhao, S. Yue, The 65nm Double-DICE Storage Element Based on Error-Quenching
Layout Design to Reduce Single-Event Multiple Node Upsets, RADECS 2016 proceedings
Appendix A: List of Semiconductor Enterprises

Partial List of Semiconductor Companies with Technical Focus

Table A.1 is a partial list of world semiconductor companies, including their primary
business types or technical focuses, year of establishment, location of headquarter,
and their web address.

Table A.1 Partial list of global semiconductor companies (as of March 2021)
Short
name Full name Primary focus Founded, HQ Web address
ADI Analog Devices Design: AMS, 1965, www.analog.com
Incorporated DSP Norwood
AMAT Applied Materials, Equipment 1967, Santa www.
Inc. Clara appliedmaterials.com
AMD Advanced Micro Design: CPU, 1969, Santa www.amd.com
Devices, Inc. GPU Clara
Amkor Amkor Technology, Packaging, 1968, Tempe www.amkor.com
Inc. testing
Apple Apple Inc. Computer, 1976, www.apple.com
design Cupertino
ASE Adv. Semi. Packaging, 1984, www.aseglobal.com
Group Engineering, Inc. testing Kaoshiung
ASM ASM Int. (Advanced Equipment 1968, Almere www.asm.com
Semi. Materials)
ASML ASML Holding N.V. Equipment 1984, www.asml.com/en
Veldhoven
Bosch Robert Bosch GmbH MEMS 1886, www.bosch.com
Gerlingen
Broadcom Broadcom Ltd. Design 1991, www.broadcom.com
San Jose
Cadence Cadence Design EDA 1988, www.cadence.com
Systems, Inc. San Jose
(continued)

© Publishing House of Electronics Industry 2024 1953

Y. Wang et al. (eds.), Handbook of Integrated Circuit Industry,
https://doi.org/10.1007/978-981-99-2836-1
1954 Appendix A: List of Semiconductor Enterprises

Table A.1 (continued)

Short
name Full name Primary focus Founded, HQ Web address
ChipMOS ChipMOS Packaging, 1997, www.chipmos.com/
Technologies Inc. testing Hsinchu index-en.aspx
Denso Denso Corporation MEMS 1949, Aichi www.denso.com/
global/en
Dongbu Dongbu HiTekCo., Fab: BCD, 1997, dbhitek.com/kr/
Ltd. analog Gyeonggi-do default.asp
GF GlobalFoundries Inc. Fab 2009, Santa www.
Clara globalfoundries.com
HHNEC Hua Hong Semicon Fab 1997, www.
Ltd. Shanghai huahonggrace.com
HiSilicon HiSilicon Design 2004, www.hisilicon.com
Semiconductor Ltd. Shenzhen
Hitachi Hitachi High- Equipment 1947, Tokyo www.hitachi-
High-Tech Technologies hightech.com/global/
Hitachi Hitachi Kokusai Equipment 1949, Tokyo hitachi-kokusai.co.jp/
Kokusai Electric Inc. global/en/
Huatian Tianshui Huatian Packaging, 2003, http://en.tshtkj.com/
Technology Co., Ltd testing Tianshui
Infeneon Infineon Design 1999, www.infineon.com
Technologies AG Dresden
Intel Intel Corporation Design 1968, Santa www.intel.com
Clara
JCET Jiangsu Changjiang Packaging, 1972, www.cj-elec.com/en/
Elec. Tech. Co. Ltd. testing Jiangyin
KING King Yuan Packaging, 1987, www.kyec.com.tw/
YUAN Electronics Corp. testing Hsinchu
(KYEC)
KLA- KLA-Tencor Equipment 1997, www.kla-tencor.com
Tencor Corporation Milpitas
Knowles Knowles Electronics MEMS 1946, Itasca www.knowles.com/
Lam Lam Research Equipment 1980, www.lamresearch.
Research Corporation Fremont com
Marvell Marvell Technology Design 1995, Santa www.marvell.com
Group Clara
MediaTek MediaTek Inc. Design 1997, www.mediatek.com
Hsinchu
Microchip Microchip Design: MCU, 1989, www.microchip.com
Technology Inc. AMS, Flash Chandler
Micron Micron Technology, Design: 1978, Boise www.micron.com
Inc. DRAM,
NAND
Nikon Nikon Corporation Equipment 1917, www.nikon.com
Shinagawa
(continued)
Appendix A: List of Semiconductor Enterprises 1955

Table A.1 (continued)

Short
name Full name Primary focus Founded, HQ Web address
NVIDIA Nvidia Corporation Design: GPU 1993, Santa www.nvidia.com
Clara
NXP NXP Semiconductors Design: 1953, www.nxp.com
N.V. automotive Eindhoven
ONSemi ON Semiconductor Design: ASIC, 1999, www.onsemi.com
power Phoenix
Powerchip Powerchip Fab: memory 1994, powerchip.com/
Technology Hsinchu index_en.html
Corporation
PTI Powertech Packaging, 1997, www.ptixa.com/
Technology testing Hsinchu-
Integration Xi’an
Qorvo Qorvo Design: SAW, 2015, www.qorvo.com
BAW Greensboro
Qualcomm Qualcomm Design: 1985, San www.qualcomm.com
Incorporated telecomm Diego
Renesas Renesas Electronics Design: MCU, 2002, Tokyo www.renesas.com
Corporation SoC
Samsung Samsung Electronics Semiconductor 1969, www.samsung.com
Co., Ltd. Yeongtong-gu
SCREEN SCREEN Equipment 2006, Kyoto www.screen.co.jp/
Semiconductor eng/spe/
Solutions
Siemens Siemens EDA EDA 1981, eda.sw.siemens.com/
Wilsonville en-USA/
SKHynix SK Hynix Inc. IDM: DRAM, 1983, Icheon www.skhynix.com
Flash
SMIC Semi. Manufacturing Fab 2000, www.smics.com
Inte. Corp. Shanghai
Sony Sony Corporation IDM: Film, 1946, Tokyo www.sony.net
TV
SPIL Siliconware Precision Packaging, 1984, www.spil.com.tw
Industries Co. testing Taichung
STMicro STMicroelectronics Fab 1957, Geneva www.st.com
Synopsys Synopsys Inc. EDA 1986, www.synopsys.com
Mountain
View
TDK TDK-Corp. (ToKyo IDM: 1935, Tokyo www.global.tdk.com
DengiKagaKu Kogyo electronics
KK)
Tl Texas Instruments Design: analog 1930, Dallas www.ti.com
Inc.
(continued)
1956 Appendix A: List of Semiconductor Enterprises

Table A.1 (continued)

Short
name Full name Primary focus Founded, HQ Web address
Tokyo Tokyo Electron Equipment 1963, Tokyo www.tel.com
Electron Limited
Tongfu Tongfu Packaging, 1997, www.tfme.com/
Microelectronics Co., testing Nantong index.php/en
Ltd.
Toshiba Toshiba Corporation IDM: 1875, Tokyo www.toshiba.com.cn/
Electronics
TowerJazz Tower Semiconductor Fab: analog, 1993, Migdal www.towerjazz.com
Ltd. (TowerJazz) RF HaEmek
TSMC Taiwan Semi. Fab 1987, www.tsmc.com
Manufacturing Hsinchu
Comp., Ltd
UMC United Fab 1980, www.umc.com
Microelectronics Hsinchu
Corporation
UNISOC UNISOC Design 2001, www.unisoc.com/en_
(Spreadtrum) Shanghai us
Vanguard/ Vanguard Inte. Fab: DRAM 1994, www.vis.com.tw
VIS Semiconductor Corp. Hsinchu
X-Fab X-FAB Silicon Fab: Analog 1978, Eufurt www.xfab.com/
Foundries home/
Xilinx Xilinx, Inc. Fab: FPGA 1984, San www.xilinx.com
Jose
Source: Compiled from each company’s web site
Data Collection: Chun-Zhang Chen

Lists of Top Ten Semiconductor Companies in Various Technical

Sectors

Based on overall performance and sales, 2020 Top Ten Semiconductor Enterprises in
the world are listed in Table A.2. Compared to the prior year 2019, the order of top
five companies (i.e., Intel, Samsung, TSMC, SK Hynix, Micron) were unchanged
and remained in the Top Ten list.
Appendix A: List of Semiconductor Enterprises 1957

Table A.2 Top ten semiconductor companies by 2020 sales

2020 2019 2019 Revenue 2020 Revenue
Rank Rank Company HQ country (millions) (millions) Change
1 1 Intel USA 71,965 77,867 8%
2 2 Samsung S. Korea 55,709 60,482 9%
3 3 TSMC China Taiwan 39,384 47,950 25%
4 4 SK Hynix S. Korea 23,185 26,070 12%
5 5 Micron USA 20,229 22,375 11%
6 7 Qualcomm USA 14,391 19,374 35%
7 6 Broadcom USA 17,743 17,748 3%
8 10 Nvidia USA 10,835 14,605 35%
9 8 TI USA 13,651 13,088
4%
10 9 Infineon Europe 11,138 11,069
1%
Top Ten Worldwide Sales 278,230 310,408 13%
Source: Various sources, companies’ reports, etc.
Data Collection: Chun-Zhang Chen, Xiaohai Xu

Note: The financial numbers presented in Appendix A.2 are for reader’s refer-
ences only; they can be inaccurate and integrated with errors and miscalculations.
Due to the complexity of technical classification, business type, and time of financial
report, some data may change drastically with a large variance. Readers are advised
to seek additional sources for an update.

Top Ten IC Design Companies

The Top Ten IC Design Companies by 2020 Revenue are listed in Table A.3. On the
list, except for a new candidate, Novatek, which moved up from 11th in 2019 to 10th
position in 2020, all the other nine companies maintained the ranks of 1–9.

Table A.3 Top ten IC design companies by 2020 sales

2020 2019 HQ 2019 Revenue 2020 Revenue
Rank Rank Company country (millions) (millions) Change
1 1 Qualcomm USA 14,391 19,374 35%
2 2 Broadcom USA 15,521 15,971 3%
3 3 Nvidia USA 10,835 14,605 35%
4 4 MediaTek China 7972 10,985 38%
Taiwan
5 5 Apple USA 8015 10,180 27%
6 6 AMD USA 6731 9519 41%
7 7 Hisilicon China 7420 8680 17%
8 8 Xilinx USA 3235 3025
6%
9 9 Marvell USA 2708 2933 8%
10 11 Novatek China 2085 2723 31%
Taiwan
Top Ten Worldwide Sales 78,913 97,995 23%
Source: Various sources, companies’ reports, etc.
Data Collection: Chun-Zhang Chen, Xiaohai Xu
1958 Appendix A: List of Semiconductor Enterprises

Top Ten Semiconductor Manufacturing Enterprises

The Top Ten Semiconductor manufacturing enterprises, for short, Foundries or Fabs
in 2020 by sales are listed in Table A.4. There are a couple of them that have
switched positions on this list; most of them maintained their ranks.

Table A.4 Top ten semiconductor foundries (or fabs) by 2020 sales
2020 2019 HQ 2019 Revenue 2020 Revenue
Rank Rank Company country (billions) (billions) Change
1 1 TSMC China 34,668 45,572 31%
Taiwan
2 3 UMC China 4800 6011 25%
Group Taiwan
3 2 Global USA 5810 5710
2%
Foundries
4 4 SMIC China 3115 3890 25%
5 5 Huahong China 1630 1720 6%
Group
6 7 Powerchip China 1165 1553 33%
Semi Taiwan
7 6 TowerJazz Israel 1234 1260 2%
8 8 Vanguard China 917 1127 23%
Taiwan
9 9 WIN China 693 860 24%
Taiwan
10 10 DB HiTek S. Korea 692 785 13%
Top Ten Worldwide Sales 54,724 68,488 14%
Source: Various sources, companies’ reports, etc.
Data Collection: Chun-Zhang Chen, Xiaohai Xu

Top Ten Semiconductor Device Manufacturers

The Top Ten Integrated Device Manufacturers (IDMs) in 2020 by Sales are listed in
Table A.5. The list of IDMs includes those who are digital, analog, logic, and
memory manufacturers.
Appendix A: List of Semiconductor Enterprises 1959

Table A.5 Top ten integrated device manufacturers by 2020 sales

2020 2019 HQ 2019 Revenue 2020 Revenue
Rank Rank Company country (millions) (millions) Change
1 1 Intel USA 70,797 73,894 4%
2 2 Samsung S. Korea 55,709 60,482 9%
3 3 SK S. Korea 23,185 26,070 12%
Hynix
4 4 Micron USA 20,229 22,375 11%
5 5 TI USA 13,651 13,088
4%
6 6 Infineon Europe 11,138 11,069
1%
7 10 Kioxia Japan 8760 10,520 20%
8 7 ST Europe 9533 10,209 7%
9 8 Sony Japan 9483 9243
3%
10 9 NXP Europe 8877 8550
4%
Top Ten Worldwide Sales 231,362 245,500 5%
Source: Various sources, companies’ reports, etc.
Data Collection: Chun-Zhang Chen, Xiaohai Xu

Top Ten IC Packaging and Testing Companies

The Top Ten IC Packaging and Testing (aka Outsourced Semiconductor Assembly
and Test, OSAT) Companies in 2018 by Sales are listed in Table A.6. A variety of
mergers and acquisitions (M&A) took place, which are presented at the end of this
table.

Table A.6 Top ten OSAT companies by 2018 sales

2017 2018
2018 2017 HQ Revenue Revenue
Rank Rank Company country (millions) (millions) Change
1 1 ASE+SPILa China 7759 7966 3%
Taiwan
2 2 Amkorb N. America 4186 4317 3%
3 3 JCETc China 3539 3675 est 4%
4 4 Powertechd China 1962 2258 15%
Taiwan
5 6 Tongfu China 953 1083 15%
Microelectronics
6 5 Huatian China 1040 1079 4%
Technologye
7 7 UTAC Holdings Singapore 875 788
10%
8 8 KYECf China 647 690 7%
Taiwan
9 9 Chipbond China 606 620 2%
Taiwan
(continued)
1960 Appendix A: List of Semiconductor Enterprises

Table A.6 (continued)

2017 2018
2018 2017 HQ Revenue Revenue
Rank Rank Company country (millions) (millions) Change
10 10 ChipMOS China 587 613 4%
Taiwan
Top Ten Worldwide Sales 22,154 23,089 5%
Source: Various sources, companies’ reports, etc.
Data Collection: Chun-Zhang Chen, Xiaohai Xu
a
Pre-merger revenues for ASE and SPIL combined as if both companies were on throughout 2017
and 2018
b
Includes J-Devices and NANIUM
c
Includes STATS ChipPAC
d
Includes Greatek
e
Includes FlipChip Internationals
f
Provides primarily test services

Top Ten Semiconductor Equipment Providers

The Top Ten Semiconductor Equipment Companies in 2018 are listed in Table A.7.
The types of semiconductor equipment may be classified into a few categories, such
as wafer fab, wafer processing and other front-end equipment, assembly, and test/
back-end equipment.

Table A.7 Top ten semiconductor equipment providers by 2018 sales

2018 2017 HQ 2017 Revenue 2018 Revenue
Rank Rank Company country (millions) (millions) Change
1 1 Applied USA 13,155 14,016 6.5%
Materials
2 4 ASML Europe 9758 12,772 30.9%
3 3 Tokyo Japan 8675 10,915 25.8%
Electron
4 2 Lam USA 9558 10,871 13.7%
Research
5 5 KLA USA 3689 4210 14.1%
6 Advantest Japan 1674 2593 54.9%
7 6 SCREEN Japan 1864 2226 19.5%
8 Teradyne USA 1663 1492
10.3%
9 9 Kokusai Japan 1182 1486 25.8%
Electric
10 8 Hitachi Japan 1200 1403 16.9%
High-tech
Top Ten Worldwide Sales 52,418 61,984 20%
Source: VLSI Research
Data Collection: Chun-Zhang Chen, Xiaohai Xu
Appendix A: List of Semiconductor Enterprises 1961

Top Ten Automotive Semiconductor Suppliers

The Top Ten Automotive Semiconductors in 2018 by Sales are listed in Table A.8. In
2019, the market observed a total of $37.2M, with
1.3% decrease due to the
emerging restructuring business categories. Therefore, these declined data were
not available while the order of Top Five were unchanged.
Table A.8 Top ten automotive semiconductor suppliers by 2018 sales
2019 2018 HQ 2018 Revenue 2019 Revenue 2018 Market
Rank Rank Company country (millions) (millions) share (%)
1 1 Infineon* Europe 4927 4274 11.9%
2 4 NXP Europe 4507 4212 10.8%
3 3 Renesas Japan 3353 3414 8.1%
4 2 TI Europe 3040 7.3%
5 5 STMicro Europe 2875 6.9%
6 Bosch Europe 2059 5.0%
7 On Semi USA 1782 4.3%
8 Micron USA 1574 3.8%
9 Microchip USA 1144 2.8%
10 ROHM Japan 1057 2.5%
Top Ten Worldwide Sales 52,418 63%
Source: 2018 Strategy Analytics; Infineon*: includes 2.2% share from Cypress
Data Collection: Chun-Zhang Chen, Xiaohai Xu

Top Ten O-S-D Companies

The Top Ten Global Major Optoelectronic, Sensor and actuator, and Discrete compo-
nents (O-S-D or OSD) companies in 2018 by Sales are listed in Table A.9. The Top Ten
companies contributed approximately 39% in both 2017 and 2018 to the total market.

Table A.9 Top ten OSD companies by 2018 sales

2018 2017 Name of HQ 2017 Revenue 2018 Revenue
Rank Rank company country (millions) (millions) Change
1 1 Sony Japan 6865 7088 3%
2 2 Sharp Japan 3666 3952 8%
3 3 Infineon Europe 3285 3745 14%
4 4 ON Semi USA 2875 3198 11%
5 6 STMicro Europe 2402 2991 25%
6 5 Samsung S. Korea 2538 2843 12%
7 7 Nichia Japan 2586 2835 10%
8 8 Osram Europe 1948 1972 1%
9 9 Broadcom USA 1594 1735 9%
10 10 OmniVision China 1485 1640 10%
Total World-wide Sales 29,244 31,999 10%
Source: IC Insights, companies’ reports, etc.
Data Collection: Chun-Zhang Chen, Xiaohai Xu
Appendix B: Reference Tables

Greek Alphabet (Table B.1)

Table B.1 Greek alphabet list
Alphabet Uppercase Lowercase English pronunciation
Alpha A α /'ælfə/
Beta B β /'bi:tə/, USA: /'beitə/
Gamma Γ γ /'gæmə/
Delta Δ δ /'dεltə/
Epsilon E ε /' εpsɪlɒn, εp ' saɪlən/
Zeta Z ζ /'zi:tə/, USA: /' zeɪtə/
Eta H η /' i:tə/, USA: /' eɪtə/
Theta Θ θϑ /' θi:tə/, USA: /' θeɪtə/
Iota I ι /aɪ' oʊtə/
Kappa K κ /'kæpə/
Lambda Λ λ /'læmdə/
Mu M μ /mju:/
Nu N ν /nju:/
Xi Ξ ξ /zaɪ, ksaɪ/
Omicron Ο o /'ɒmɪkrɒn, oʊ'maɪkrɒn/
Pi Π π /paɪ/
Rho Ρ ρ /roʊ/
Sigma Σ σς /'sɪgmə/
Tau Τ τ /taʊ, tɔ:/
Upsilon Y υ /ju:p'saɪlən, 'ʊpsɪlon/
Phi Φ φ /faɪ/
Chi Χ χ /kaɪ/
Psi Ψ ψ /saɪ/, /psaɪ/
Omega Ω ω /'oʊmIgǝ/, USA: /oʊ' meɪgǝ/
Appendix B: Reference Tables 1963

Reference Tables of Physics and Chemistry

Periodic Table of Elements (Table B.2)

Table B.2 Periodic table
1964 Appendix B: Reference Tables

Chemical Elements Used in IC Manufacturing (Table B.3)

Table B.3 Commonly used chemical elements in IC fabrication

Physicochemical Properties of Gases (Table B.4)

Table B.4 Physicochemical constants of some common gases

CAS Mol. Molar mass Density Melting Boiling
No. Name number form (g/mol) (g/L) ( C) ( C)
1 Hydrogen 1333–74–0 H2 2.01588 0.0899 –259.16 –252.879
2 Helium 275–187–7 He 4.0026 0.1786 –272.20 –268.928
3 Nitrogen 7727–37–9 N2 28.0134 1.2510 –211.4 –195.8
4 Oxygen 7782–44–7 O2 31.9988 1.4291 –218.79 –182.962
5 Fluorine 7782–41–4 F2 37.9968 1.5540 –219.62 –188.1
6 Neon 7440–01–9 Ne 20.1797 0.9002 –248.59 –246.046
7 Chlorine 7782–50–5 Cl2 70.9 3.2100 –101.5 –34.04
8 Argon 7440–37–1 Ar 39.948 1.7840 –189.3 –185.8
9 Krypton 7439–90–9 Kr 83.8 3.7490 –157.37 –153.415
10 Xenon 7440–63–3 Xe 131.3 5.8940 –111.75 –108.099
(continued)
Appendix B: Reference Tables 1965

Table B.4 (continued)

CAS Mol. Molar mass Density Melting Boiling
No. Name number form (g/mol) (g/L) ( C) ( C)
11 Radon 10043–92–2 Rn 222 9.7300 –71 –61.7
12 Methane 74–82–8 CH4 16.043 0.6560 –182.5 –161.49
13 Acetylene 74–86–2 C2H2 26.038 1.0970 –80.8 –84
14 Ethylene 74–85–1 C2H4 28.054 1.1780 –169.2 –103.7
15 Ethane 74–84–0 C2H6 30.07 1.3553 –182.3 –88.5
16 Propene 115–07–1 C3H6 42.081 1.8100 –185.2 –47.6
17 Propane 74–98–6 C3H3 44.1 1.8300 –187.6 –42.25
18 1-Butene 106–98–9 C4H3 56.106 0.6200 –185.3 –6.47
19 Cis-2- 590–18–1 C4H3 56.106 0.6410 –138.9 3.7
butene
20 Trans-2- 624–64–6 C4H3 56.106 0.6260 –105.5 0.9
butene
21 Isobutene 115–11–7 C4H3 56.106 0.5879 –140.3 –6.9
22 n-Butane 106–97–8 C4H10 58.12 2.4800 –140 –1
23 Isobutane 75–28–5 C4H10 58.12 2.5100 –159.4 –11.73
24 1-Pentene 109–67–1 C5H10 70.135 0.6411 –165.2 30
25 Benzene 71–43–2 C6H6 78.114 0.8786 5.5 80
26 Carbon 630–08–0 CO 28.0104 1.2506 –205.1 –191.4
monoxide
27 Carbon 24–38–9 CO2 44.0098 1.9770 –78.45 –56.55
dioxide
28 Sulfur 7446–09–5 SO2 64.059 2.9275 –75.5 –10
dioxide
29 Hydrogen 7783–06–4 H2S 34.076 1.3630 –82 –60
sulfide
30 Water H2O 18.0154 0.8330 0 99.974
vapor
31 Air air 28.959 1.2931
CAS: Chemical Abstracts Service, a division of the American Chemical Society

Physicochemical Properties of Liquids (Table B.5)

 1966

Table B.5 Physicochemical constants of some common liquids

Chemical Mol. Mass Density Melting Boiling Refractive
No Chemical name CAS No. formula (g/mol) (g/cm3) ( C) ( C) index
1 Ammonia 7664–41–7 NH3 17.03
77.7
33.3 1.3327
2 Formaldehyde 50–00–0 CH2O 30.03 0.8153
92
19 1.3755–1.3775
3 Methanol 67–56–1 CH3OH 32.04 0.792
97.6 64.7 1.331
4 Acetonitrile 75–05–8 CH3CN 41.05 0.7857
46 81–82 1.344
5 Acetaldehyde 75–07–0 C2H4O 44.05 0.788
123.4 20.2 1.332
6 Formic acid 64–18–6 CH2O2 46.03 1.22 8.4 100.8 1.3701–1.3721
7 Dimethyl ether 115–10–6 C2H6O 46.07 0.735
141
24
8 Acetone 67–64–1 C3H6O 58.08 0.7845
94.7 56.05 1.3588
9 Ethanolamine 141–43–5 C2H7NO 61.08 1.0117 10.3 170 1.454
10 Pentane 109–66–0 C5H12 72.151 0.626
129.8 36.1 1.358
11 Hexane 110–54–3 C6H14 86.178 0.661
96 68.5 1.375
12 Toluene 108–88–3 C7H8 92.141 0.87
95 111 1.497
13 Benzonitrile 100–47–0 C7H5N 103.12 1.01
13 188 1.528
14 Chloroform 67–66–3 CHCl3 119.37 1.48
63.5 61.15 1.4459
15 Ethyl chloroacetate 105–39–5 C4H7ClO2 122.55 1.145
26 143 1.421
16 1,1,1-Trichloroethane 71–55–6 CH3CCl3 133.4 1.32
33 74 1.4366
17 1,2-Dichlorobenzene 95–50–1 C6H4Cl2 147.01 1.3
17.03 180.19 1.551
18 Bromobenzene 108–86–1 C6H5Br 157.01 1.495
30.8 156 1.5602
19 Benzyl bromide 100–39–0 C6H5CH2Br 171.04 1.438
3.9 201 1.5752
20 3, 5-Bis(trifluoromethyl) 328–70–1 C8H3BrF6 293 1.699
16 154 1.427
bromobenzene
CAS: Chemical Abstracts Service, a division of the American Chemical Society
Appendix B: Reference Tables
Appendix B: Reference Tables 1967

Properties of Semiconductor Materials (Table B.6)

Table B.6 Parameters of some common semiconductor materials
2H- 2H-
Property Si GaAs 4H-SiC 6H-SiC GaN AlN Diamond
Bandgap at 1.12 1.424 3.26 3.02 3.39 6.2 5.45
300 K (eV)
Lattice 5.43 5.65 a ¼ 3.08 a ¼ 3.08 a¼ a¼ 3.56
parameters c ¼ 10.08 c ¼ 15.12 3.19 3.11
(Å) c¼ c¼
5.18 4.98
Max. 350 460 1200 1200 1100
operating
temp. ( C)
Melting point 1414 1238 Sublimes Sublimes 2275 Graphitization
( C) > 2800 > 2800 > 1500
Electron 1400 8500 900 600 900 1100 2200
mobility
[cm2/(V.s)]
Hole mobility 600 400 40 40 150 1600
[cm2/(Vs)]
Breakdown 0.3 0.4 2.2 2.5 3.3 11.8 10
electric field
(108 V/m)
Thermal 149 54 490 490 130 200 2000
conductivity
(W/mK)
Saturation 1.0 2.0 2.7 2.0 2.9 1.8 2.7
drift velocity
(105 m/s)
Dielectric 11.8 12.8 10 9.7 8.9 8.5 5.5
constant
Mohs 7 4–5 9.2–9.3 10
hardness
1968 Appendix B: Reference Tables

Chemistry and Physics Constants (Table B.7)

Table B.7 General chemistry and physics constants
Quantity Symbol Value
Avogadro’s number NA 6.02214  1023 mol
1
Faraday constant F 96,482.33 C mol
1
Atomic mass constant 1 amu 1.660538  10
27 kg
Molar gas constant R 8.3144 J mol
1 K
1
Molar volume of ideal gases Vm 0.022414 m3/mol
Number density n ¼ N/V 2.6867774  1025 m
3
Stefan–Boltzmann constant σ ≈5.670400  10
8 J s
1 m
2 K
4
Wien’s displacement constant λ 2.897771955. . .  10
3 mK
Coulomb’s constant ke 8.987551  109 N m2 C
2
Speed of light (vacuum) c 299,792,458 ms
1
Boltzmann constant kb 1.38065  10
23 J K
1
Charge on a proton/electron e 1.602176  10
19 C
Standard acceleration of gravity g 9.80665 m s
2
Rydberg constant R1 1.0973731568539  107 m
1
Planck’s constant h 6.62607004  10
34 J s
Specific heat capacity of liquid water c 4.18 kJ kg
1 C
1

Mathematical Constants (Table B.8)

Table B.8 Some common mathematical constants

Symbol value Name Field
0 0 Zero General
1 1 One, unity General
i ¼√
1 Imaginary unit, unit imaginary Gen.,
number Ana.
π ≈3.14159 26535 89793 23846 26433 Pi, Archimedes’ constant or Gen.,
83279 50288 Ludolph’s number Ana.
e ≈2.71828 18284 59045 23536 02874 e, Napier’s constant, or Euler’s Gen.,
71352 66249 number Ana.
√2 ≈1.41421 35623 73095 04880 16887 Pythagoras’ constant, square General
24209 69807 root of 2
√3 ≈1.73205 08075 68877 29352 74463 Theodorus’ constant, square General
41505 87236 root of 3
√5 ≈2.23606 79774 99789 69640 91736 Square root of 5 General
68731 27623
ϕ ≈1.61803 39887 49894 84820 45868 Golden ratio General
34365 63811
(continued)
Appendix B: Reference Tables 1969

Table B.8 (continued)

Symbol value Name Field
P2 ≈2.29558 71493 92638 07403 42980 Universal parabolic constant General
49189 49039
γ ≈0.57721 56649 01532 86060 65120 Euler–Mascheroni constant Gen.,
90082 40243 NuT.
β* ≈0.70258 Embree–Trefethen constant Num.
theory

Physics Constants

General Physics Constants (Table B.9)

Table B.9 General physics constants
Relative standard
Quantity Symbol Value uncertainty
Speed of light in c 299,792,458 ms
1 Defined
vacuum
Newtonian constant of G 6.67408(31)  4.7  10
5
gravitation 10
11 m3kg
1s
2
Planck constant h 6.626070040(81)  1.2  10
8
10
34 Js
Reduced Planck h ¼ h=2π 1.054571800(13)  1.2  10
8
constant 10
34 Js
Avogadro constant NA, L 6.02214076  1023 (1/mol) 0
Boltzmann constant k, kB 1.380649  10
23 (J/K) 0
Fine-structure constant α ¼ e2/2ε0hc 7.2973525693(11) 10
3 1.5  10
10
Josephson constant KJ ¼ 2e/h 483,597.8484. . . 109 0
(Hz/V)
Molar gas constant R ¼ NAKB 8.314462618. . . (J/molK) 0
Rydberg constant R ¼ αmec/2h 10973831.568160(21) (1/m) 1.9  10
12

Electromagnetic Constants (Table B.10)

Table B.10 Electromagnetic constants
Relative
standard
Quantity Symbol Value (SI units) uncertainty
Magnetic constant μ0 5 4π 3 1.256 637 061. . .  Defined
(vacuum permeability) 10
7 10
6 N  A
2
Electric constant ε0 5 1/μ0c2 8.854 187 817. . .  Defined
(vacuum permittivity) 10
12 F  m
1
Characteristic Z0 5 μ0c 376.730 313 461. . .Ω Defined
impedance of vacuum
(continued)
1970 Appendix B: Reference Tables

Table B.10 (continued)

Relative
standard
Quantity Symbol Value (SI units) uncertainty
Coulomb’s constant ke 5 1/4πε0 8.987 551 787 368 176 4  Defined
109 kg  m3  s
4  A
2
Elementary charge e 1.602 176 6208(98)  10
19C 6.1  10
9
Bohr magneton μB 5 eℏ/2me 9.274 009 994(57)  6.2  10
9
10
24 J  T
1
Conductance quantum G0 5 2e2/h 7.748 091 7310(18)  10
5 s 2.3  10
10
Inverse conductance G
1
0 5h=2e
2 12 906.403 7278(29)Ω 2.3  10
10
quantum
Josephson constant KJ 5 2e/h 4.835 978 525(30)  6.1  10
9
1014 Hz  V
1
Magnetic flux quantum ϕ0 5 h/2e 2.067 833 831(13)  6.1  10
9
10
15 Wb
Nuclear magneton μN 5 eℏ/2mp 5.050 783 699(31)  6.2  10
9
10
27J  T
1
von Klitzing constant RK 5 h/e2 25 812.807 4555(59)Ω 2.3  10
10

Atomic and Nuclear Constants (Table B.11)

Table B.11 Atomic and nuclear constants
Relative standard
Quantity Symbol Value (SI units) uncertainty
Bohr radius a0 ¼ α/4πR1 5.291 772 1067(12)  10
11 m 2.3  10
9
Classical re ¼ e2/4πε0mec2 2.817 940 3227(19)  10
15 m 6.8  10
10
electron radius
Electron mass me 9.109 383 56(11)  10
31 kg 1.2  10
8
Fermi coupling GF/(ℏc)3 1.166 3787(6)  10
5 GeV
2 5.1  10
7
constant
Fine-structure α ¼ μ0e2c/2h ¼ e2/ 7.297 352 5664(17)  10
3 2.3  10
10
constant 4πε0ℏc
Hartree energy Eh ¼ 2R1hc 4.359 744 650(54)  10
18 J 1.2  10
8
Proton mass mp 1.672 621 898(21)  10
27 kg 1.2  10
8
Quantum of h/2me 3.636 947 5486(17)  10
4 m2/s 4.5  10
10
circulation
Rydberg R1 ¼ α2mec/2h 10 973 731.568 508(65)m
1 5.9  10
12
constant
Thomson cross ð8π=3Þr 2e 6.652 458 7158(91)  10
29 m2 1.4  10
9
section
Weak mixing sin2θW ¼ 1
0.2223(21) 9.5  10
3
angle (mW/mZ)2
Efimov factor 22.7
Appendix B: Reference Tables 1971

SI Units

The International System of Units (SI, abbreviated from the French Système
international d’unités). It has seven base units (Table B.12) and 22 derived units
(Table B.13).

Basic SI Units
Table B.12 Base SI units
Unit name Unit symbol Dimension symbol Quantity name
Second s T Time
Meter m L Length
Kilogram kg M Mass
Ampere A I Electric current
Kelvin kg Θ Thermodynamic Temperature
Mole mol N Amount of substance
Candela cd J Luminous intensity

Derived SI Units
Table B.13 Derived SI units
Name Symbol Quantity In SI base units
Radian rad Plane angle m/m
Steradian sr Solid angle m2/m2
Hertz Hz Frequency s
1
Newton N Force, weight kg ms
2
Pascal Pa Pressure, stress kg. m
1 s
2
Joule J Energy, work, heat kg m2 s
2
Watt W Power, radiant flux kg m2 s
3
Coulomb C Electric charge or quantity of electricity s A
Volt V Voltage (electrical potential), emf kg m2 s
3 A
1
Farad F Capacitance kg
1 m
2 s4 A2
Ohm Ω resistance, impedance, Reactance kg m2 s
3 A
2
Siemens S Electrical conductance kg
1 m
2 s3 A2
Weber Wb Magnetic flux kg m2 s
2 A
1
Tesla T magnetic flux density kg s
2 A
1
Henry H Inductance kg m2 s
2 A
2

Degree celsius C Temperature relative to 273.15 K K
Lumen Im Luminous flux cd sr
Lux lx Illuminance m
2 cd
Becquerel Bq Radioactivity (decays per unit time) s
1
Gray Gy Absorbed dose (of ionizing radiation) m2 s
2
Sievert Sv Equivalent dose (of ionizing radiation) m2 s
2
Katal kat Catalytic activity mol s
1
1972 Appendix B: Reference Tables

Non-SI Units (Table B.14)

Table B.14 Non-SI units
Name Symbol Quantity wrt SI
Time Minute min 1 min ¼ 60 s
Hour h 1 h ¼ 60 min ¼ 3600 s
Day d 1 d ¼ 24 h ¼ 86400 s

Plane and Degree 1  ¼ (π/180) rad
phase angle Minute 0
10 ¼ (1/60) ¼ (π/10800) rad
Second 00
100 ¼ (1/60)0 ¼ (π/648000) rad
Mass Tonne (metric ton) t 1 t ¼ 1000 kg
Dalton Da 1 Da ¼ 1.660539040(20)  10
27 kg
Logarithmic Neper Np 1 Np ¼ 8.68589 dB
ratio Bel B 1 B ¼ 10 dB
quantities Decibel dB 1 dB  0.11513 Np
Area Hectare ha 1 ha ¼ 1 hm2 ¼ 104 m2
Volume Liter I, L 1 I ¼ 1 L ¼ 1 dm3 ¼ 103cm3 ¼ 10
3m3
Energy Electronvolt eV 1 eV ¼ 1.602176634  10
19 J
Rotational Revolution per rpm, cps 1 r/ min ¼ (1/60)
1
speed minute
Length Nautical mile M, NM, nmi 1 n mile ¼ 1852 m (navigation only)
Speed Knot kn, kt 1 kn ¼ 1852 m/h
Linear Titer in textile tex 1 tex ¼ 10
6 kg/m
density engineering

SI Prefix (Table B.15)

Table B.15 List of SI Name Symbol Base 10 Name Symbol Base 10
prefix
Yotta Y 1024 Deci d 10
1
Zetta Z 1021 Centi c 10
2
Exa E 1018 Milli m 10
3
Peta P 1015 Micro m 10
6
Tera T 1012 Nano n 10
9
Giga G 109 Pico P 10
12
Mega M 106 Femto f 10
15
Kilo k 103 Atto a 10
18
Hecto h 102 Zepto z 10
21
Deca da 101 Yocto y 10
24
Appendix B: Reference Tables 1973

Conversion Tables of Commonly Used Units

Commonly used units include length units, area units, volume units, weight units,
and capacity and other units.

Conversion of Length Units (Table B.16)

Table B.16 Conversion Name Symbol SI Symbol Conversion factor

of commonly used length
Yard yd m 1 yd ¼ 0.9144 m
units
Foot ft cm 1 ft ¼ 30.48 cm
Inch in cm 1 in ¼ 2.54 cm
Mil mil μm 1 mil ¼ 25.4 μm
Angstrom Å nm 1Å ¼ 0.1 nm

Conversion of Area Units (Table B.17)

Table B.17 Conversion of commonly used area units

Name Symbol SI symbol Conversion factor
Square mile sq. mi. km2 1 sq. mi. ¼ 2.5899 km2
Square yard sq. yd. m2 1 sq yd ¼ 0.8361 m2
Square foot sq. ft. m2 1 sq ft ¼ 0.0929 m2
Square inch sq. in. cm2 1 sq in ¼ 6.4516 cm2

Conversion of Volume and Capacity Units (Table B.18)

Table B.18 Conversion of commonly used volume and capacity units

Unit
Name Symbol Conversion factor (capacity) Conversion of US and UK unit
Cubic yard yd3 1 yd3 ¼ 764:554858 dm3 1 yd3 ¼ 27 ft3
Cubic foot ft3 1 ft3 ¼ 28.316 85 dm3 1 ft3 ¼ 1728 in3
Cubic inch in3 1 in3 ¼ 16.3870 cm3
US barrel US bbl 1 US bbl (Iqd) ¼ 119.24 L 1 US bbl (Iqd) ¼ 31.5 US
(liquid) Iqd gal (Iqd)
US gallon US gal 1 US gal (Iqd) ¼ 1 US gal (Iqd) ¼ 4 US qt (Iqd)
(liquid) Iqd 3.785 412 L
US quart US qt Iqd 1 US qt (Iqd) ¼ 0.946 3 L 1 US qt (Iqd) ¼ 2 US pt (Iqd)
(liquid)
US quart (dry) US qt dry 1 US qt (dry) ¼ 1 US qt ðdryÞ ¼ 2 US pt ðdryÞ
1.1636 US qt (Iqd)
US pint US pt Iqd 1 US pt Iqd ¼ 0.473 176 5 L 1 US pt (Iqd) ¼ 4 US gi
(liquid)
(continued)
1974 Appendix B: Reference Tables

Table B.18 (continued)

Unit
Name Symbol Conversion factor (capacity) Conversion of US and UK unit
US pint (dry) US pt dry 1 US pt dry ¼ 0.550 610 5 L 1 US pt (dry) ¼
4.65454544 US gi
US cup US cup 1 US cup ¼ 236.588 mL 1 US cup ¼ 8 US fl oz
US gill US gi 1 US gi ¼ 118.294 mL 1 US gi ¼ 4 US fl oz
US fluid US fl oz 1US fl oz ¼ 29:574 mL 1 US fl oz ¼ 2 tbsb
ounce
US tablespoon US tbsb 1 US tbsb ¼ 14.787 mL 1 US tbsb ¼ 3 US tsb
UK gallon UK gal 1 UK gal ¼ 4.5461 L 1 UK gal ¼ 1.20 US gal
UK quart UK qt 1UK qt ¼ 1.1365 L 1 UK qt ¼ 2 UK pt
UK pint UK pt 1 UK pt ¼ 568:261 mL 1 UK pt ¼ 4 UK gi
UK gill UK gi 1 UKgi ¼ 142.1 mL 1 UK gi ¼ 5 UK fl oz
UK liquid UK fl oz 1 UK fl oz ¼ 28.41 mL
ounce
Note: 1 dm3 ¼ 1 L; 1 cm3 ¼ 1 mL; Imperial units are denoted as UK units

Conversion of Miscellaneous Units (Table B.19)

Table B.19 Conversion of miscellaneous units

Name Symbol Conversion factor Conversion
Pound lb 1 lb ¼ 0.4535924 kg 1 lb ¼ 16 oz
Common ounce OZ 1 oz ¼ 28.3495231 g 1 oz ¼ 16 dram
Troy ounce oz t 1 ozt ¼ 31.1034768 g 1 ozt ¼ 1.0971428 oz
Atmosphere atm 1 atm ¼ 101325 Pa
pressure
Millimeter of mmHg 1 mmHg ¼ 133.3224 Pa 1 mmHg ≈ 1 Torr
mercury
 
Fahrenheit F F to  C: T( C) ¼ (T( F)

C to  F: T( F) ¼ T( C)  9/5
32)  5/9 + 32
Kelvin K Kelvin to Celsius:  C ¼ K – Celsius to Kelvin: K ¼ 0  C þ
273.15 273.15

Monetary Conversion Table (Table B.20)

Table B.20 Currency exchange rate
Name Code Symbol Rate of Oct 1, 2017 Rate of Jan 15, 2020
Reminbi CNY ¥ – –
US dollar USD $ ¥100 ¼ $15.2161 ¥100 ¼ $15
Euro EUR € ¥100 ¼ €12.9026 ¥100 ¼ €13
British pound GBP £ ¥100 ¼ £11.5404 ¥100 ¼ £11.2
Japanese yen JPY ¥ ¥100 ¼ JPY¥1709.98 ¥100 ¼ JPY¥1598
Source: Data Collection: Chun-Zhang Chen
Appendix C: Abbreviations of IC Terminology

0–9
3GPP, Third Generation Partnership Project
5G, 5th Generation
5 Gb, 5 giga-bit
56 Gb/s, 56 giga-bit per second
77 GHz, 77 giga-Hertz
5 EFLOPS, 5 exa-FLOPS, cf. FLOPS

A
a-Si, Amorphous Silicon
AAC, Advanced Audio Coding
AAS, Automotive Active Safety (Systems)
ABC, Active Body Control
ABS, Anti-Lock Braking (Systems)
AC-3, Alias Cancellation Version 3
ACC, Adaptive Cruise Control
ADC, Analog-to-Digital Converter
ADAS, Advanced Driver-Assistance Systems
ADSL, Asymmetric DSL, cf. xDSL
AE/FAE, (Field) Applications Engineer
AES, Advanced Encryption Standard
AFC, Aviation Flight Control
AFE, Analog Front-End (design)
AI, Artificial Intelligence
ALD, Atomic Layer Deposition
ALE, Atomic Layer Etching
ALU, Arithmetic Logic Unit
AM, Amplitude Modulation
AMOLED, Active-Matrix Organic Light-Emitting Diode
AMPS, Advanced Mobile Phone System
AMQLED, Active Matrix QLED
AMS, Analog-Mixed Signal
ANN, Artificial Neural Networks
APC, Advanced Process Control
1976 Appendix C: Abbreviations of IC Terminology

APD, Avalanche Photodiode

APP, Application program/software
APS, Active Pixel Sensor
APT, Atom Probe Tomography
APU, Accelerated Processing Unit
AR, Augmented Reality
ARDE, Aspect Ratio-Dependent Etching
ARM, Acorn RISC Machine; Advanced RISC Machines
ASML, Advanced Semiconductor Material Lithography
ASIC, Application-Specific Integrated Circuit
ASP, Average Selling Price
ASSP, Application-Specific Standard Product
ATA, Advanced Technology Attachment
ATE, Automatic/Automated Test Equipment
ATSC, Advanced Television Systems Committee
AUI, Adaptive User Interface
AVB, Audio Video Bridging (system)
AVS, Advanced Video Standard
AWG, Arbitrary Waveform Generator

B
BB (or BO/BI) ratio, book-to-bill ratio
BBUL, Bumpless Build-Up Layer
BCD, Bipolar-CMOS-DMOS; Bipolar Complementary and Double-diffused
Metal-Oxide-Semiconductor
BCM, Body Control Module
BCS, Body Control System
BDS, BeiDou Navigation Satellite System
BFOM, Baliga’s Figure of Merit
BGA, Ball Grid Array
BGS, Bulk Gas System
BiCMOS, Bipolar Complementary Metal-Oxide-Semiconductor
BIM, Binary Intensity Mask
BISR, Built-In Self-Repair
BIST, Built-In Self-Test
BJT, Bipolar Junction Transistor
BL, Bit-Line, cf. Word-Line
BMS, Battery Management System
BNC, Bayonet Neill-Concelman (connector)
BOD, Breakover Diode
BOS, Brake Override System
BPL, Broadband over Power Line
BPSG, Borophosphosilicate Glass
BSD, Blind Spot Detection
BSG, Boron-doped Silicate Glass, Boro-silicate (Borosilicate) Glass
Appendix C: Abbreviations of IC Terminology 1977

BSS, Base Station System

BVA, Bond Via Array
BVS, Binocular Vision System

C
CAD, Computer-Aided Design
CAM, Computer-Aided Manufacturing
CAN, Controller Area Network
CAPEX, Capital Expenditure (Expense)
CAS, Collision Avoidance System (Pre-crash System)
CBA, Component Based Automation
CBE, Chemical-Phase Epitaxy
CCD, Charge-Coupled Device
CCP, Capacitively Coupled Plasma
CCRA, Common Criteria Recognition Arrangement
CDMA, Code-Division Multiple Access
CDN, Content Delivery Network
CEBL, Complementary E-Beam Lithography
CEO, Chief Executive Officer
CERN, Conseil Européen pour la Recherche Nucléaire
CFG, Creep-Feed Grinding
CFIUS, Committee on Foreign Investment in the United States
CIS, CMOS Image Sensor
CISC, Complex Instruction Set Computer
CLB, Configurable Logic Block
CMOS, Complementary Metal-Oxide- Semiconductor
CMP, Chemical Mechanical Polishing/ Planarization
CMS, Content Management System
CNN, Convolutional Neural Networks
CNT, Carbon Nanotube
COT, Customer-Owned Tooling/Technology
CPI, Chip-Package Interaction
CPLD, Complex Programmable Logic Devices
CPM, Cardiac Pace Maker
CPML/CPM2, Charged Particle Maskless Lithography
CPP, Contacted Poly Pitch
CPPR, Common Path Pessimism Removal
CPU, Central Processing Unit
CRT, Cathode Ray Tube
CSIA, China Semiconductor Industry Association
CSMA/CD, Carrier-Sense Multiple Access with Collision Detection
CSP, Chip-Scale Package (old: chip- size packaging)
CSS, Chemical Supply System
CTE, Coefficient of Thermal Expansion
CTL, Charge-Trapping Layer
1978 Appendix C: Abbreviations of IC Terminology

CTS, Clock-Tree Synthesis

CTTS, Closed Transition Transfer Switch
CUDA, Compute Unified Device Architecture
CUF, Capillary Underfill
CVBS, Composite Video Broadcasting Signal/ Composite Video Blanking and Sync
CVD, Chemical Vapor Deposition
AACVD, Aerosol-Assisted CVD
APCVD, Atmospheric Pressure CVD
FCVD, Flowable CVD
LPCVD, Low-Pressure CVD
MOCVD, Metalorganic CVD
PECVD, Plasma-Enhanced CVD
PICVD, Photo-Initiated CVD
RPCVD, Remote Plasma CVD
RTCVD, Rapid Thermal CVD
UHVCVD, Ultrahigh vacuum CVD
Cz-Si/CZ-Si, Czochralski silicon
C-AFM, Conductive Atomic Force Microscopy

D
DAB, Digital Audio Broadcasting
DAC, Design Automation Conference; Digital-to-Analog Converter
DAF, Die Attach Film
DAR, Display Aspect Ratio
DARPA, Defense Advanced Research Projects Agency
DB, Diffusion Break
DSB, Double Diffusion Break
SSB, Single Diffusion Break
DBO, Diffraction-Based Overlay
DBS, Deep Brain Stimulation
DCF, Discount Cash Flow
DCS, Distributed Control Systems; Dichlorosilane
DD, Due Diligence
DDD, Driver Drowsiness Detection
DDR, Double Data Rate (SDRAM)
D/E, Debt-to-Equity ratio
DEC, Digital Equipment Corporation
DES, Data Encryption Standard
DFM, Design for Manufacturability/ Manufacturing
DFR, Design for Reliability
DFT, Design for Testability/Test/Testing; Density Functional Theory
DFY, Design for Yield
DIMM, Dual In-Line Memory Module
DIP, Double In-line Package
DMD, Digital Micro-mirror Device
Appendix C: Abbreviations of IC Terminology 1979

DMOS, Double-diffused Metal-Oxide-Semiconductor

DNA, Deoxyribonucleic Acid
DNN, Deep Neural Network
DNS, Domain Name System
DOE/DOX, Design of Experiments
DOF, Depth of Focus
DPA, Destructive Physical Analysis
DPM, Dipole-Ring Magnetron
DPT, Double Patterning Technology
DRAM. cf. RAM
DRC, Design Rule Checking/Check(s)
DRFM, Digital Radio Frequency Memory
DRM, Digital Rights Management
DSL, Digital Subscriber Line (see xDSL)
DSP, Digital Signal Processor
DSW, Direct-Step-on-Wafer
DTCO, Design Technology Co-Optimization
DUT, Device Under Test
DVB, Digital Video Broadcasting
DVB-C, Digital Video Broadcasting-Cable
DVB-S, Digital Video Broadcasting-Satellite
DVB-T, Digital Video Broadcasting-Terrestrial
DVD, Digital Versatile Disc
DVFS, Dynamic Voltage (and) Frequency Scaling

E
EBA, Emergency Brake Assist (System)
EBIT, Earnings Before Interest and Tax
EBITDA, Earnings Before Interest and Tax, Depreciation and Amortization
EBFD, Electronic Brake-Force Distribution
EBL, Electron-Beam Lithography (System)
ECC, Elliptical Curve Cryptography
ECG, Electrocardiography
ECP, Electro-Chemical Plating
EPD, Electrochemical Plating Deposition; Electrophoretic deposition
ECR, Electron Cyclotron Resonance
ECS, Electronic Stability Control
ECT, Embedded Component Technology
ECU, Electronic Control Unit
EDA, Electronic Design Automation
EDGE, Enhanced Data rates for GSM Evolution (Enhanced GPRS (EGPRS))
EDS/EDX/EDXS/XEDS, Energy-Dis-persive X-ray Spectroscopy
EEPROM, cf. Read-Only Memory
EFEM, Equipment Front-End Module
EHF, Extremely High Frequency
1980 Appendix C: Abbreviations of IC Terminology

EIA, Electronic Industries Alliance

EMC, Epoxy Molding Compound
eMCP, embedded Multi-Chip Package
eMMC, embedded Multi-Media Card
ENIAC, Electronic Numerical Integrator and Computer
EPIC, Explicitly Parallel Instruction Computing
EPL, Electron-beam Projection Lithography
EPROM, cf. Read-Only Memory
EQE, External Quantum Efficiency
ESC, Electrostatic Chuck; Electronic Speed Control
ESD, Electrostatic Discharge
ESO, Employee Stock Option
ESPP, Employee Stock Purchase Plan
ETC, Electronic Tolling Collection
ETO, Emitter Turn-Off (thyristor)
EUV, Extreme Ultraviolet (radiation)
EUVL, Extreme Ultraviolet Lithography
eWLB, Embedded Wafer-Level Ball Grid Array
EZW, Embedded Zerotree Wavelet

F
FC-BGA, Flip-Chip Ball Grid Array
FC-CSP, Flip-Chip Chip Scale Package
FCW, Forward Collision Warning (Systems)
FDSOI/FD-SOI, Fully Depleted SOI
FDD, Frequency-Division Duplexing
FDDI, Fiber Distributed Data Interface
FET, Field-Effect Transistor
FIMI, Force Current Measure Current
FIMV, Force Current Measure Voltage
FeRAM, cf. RAM
FFT, Fast Fourier Transform
FFU, Fan Filter Unit
FinFET, Fin Field-Effect Transistor
FLOPS, Floating Point Operations Per Second
FM, Frequency Modulation
FMC, Fixed-Mobile Convergence
FOM, Figure of Merit, Figure-of-Merit
FOV, Field of View
FO-WLP, Fan-Out Wafer-Level Package
FPGA, Field-Programmable Gate Array
FPU, Floating-Point Unit
FRD, Fast Recovery Diode
FredFET, Fast Recovery Epitaxial Diode FET
FSA, Fabless Semiconductor Association
Appendix C: Abbreviations of IC Terminology 1981

FTIR, Fourier Transform Infrared

FVMI, Force Voltage Measure Current
FVMV, Force Voltage Measure Voltage
FZ, Floating Zone
FZ-Si, Floating Zone Silicon

G
GAA, Gate-All-Around FET/Device
GAAP, Generally Accepted Accounting Principles (United States; Practice, UK)
GaAs, Gallium Arsenide
GAL, Gate Array Logic
GAMS, Government/Authorities Meeting on Semiconductors
GaN, Gallium Nitride
GDDR, Graphics DDR (SDRAM)
GDP, Gross Domestic Product
GIDL, Gate-Induced Drain Leakage
GLONASS, Глобальная навигационная спутниковая система, Globalnaya
navigatsionnaya sputnikovaya Sistema, Global Navigation Satellite System
GMR, Gross Margin Rate
GNP, Gross National Product
GNSS, Global Navigation Satellite System
GOA, Global Outstanding Assessment
GPGPU, General-Purpose Computing on Graphics Processing Units
GPS, Global Positioning System
GPU, Graphics Processing Unit
GSA, Global Semiconductor Alliance
GSM, Global System for Mobile Communications (original: Groupe Spécial
Mobile)
GTO, Gate Turn-Off (thyristor)

H
HBT, Heterojunction Bipolar Transistor
HDD, Hard Disk Drive
HDL, Hardware Description Language
HDMI, High-Definition Multimedia Interface
HDP, High-Density Plasma
HDTV, High-Definition Television
HEMT, High-Electron-Mobility Transistor
HEVC, High-Efficiency Video Coding
Hi-Fi, High Fidelity
HiP, Head-in-Pillow (defects)
HKMG, High-k Metal Gate, High-K/Metal Gate
HLS, High-Level Synthesis
HPS, High-Performance Computing
HSA, Heterogeneous System Architecture
1982 Appendix C: Abbreviations of IC Terminology

HSM, Hardware Security Module

HTCC, High Temperature Co-fired Ceramics

I
IA-64, Itanium Architecture 64-Bit (Intel)
IaaS, Infrastructure as a Service
IBE, Ion-Beam Etching (Equipment)
IBIS, Input/output Buffer Information Specification
IBO, Image-Based Overlay
ICCAD, Integrated Circuit on Computer-Aided Design; International Conference on
Computer-Aided Design
ICP, Inductively Coupled Plasma
ICT, Information and Communication Technology
IDC, Internet Data Center
IDE, Integrated Drive Electronics
IDM, Integrated Device Manufacturer
IDSL, ISDN DSL, cf. xDSL
IEDM, (IEEE) International Electron Devices Meeting
IEEE, Institute of Electrical and Electronics Engineers
IETS, Inelastic Electron Tunneling Spectroscopy
IFG, In-Feed Grinding
IGBT, Insulated-Gate Bipolar Transistor
FS-IGBT, Field-Stop IGBT
L-IGBT, Lateral IGBT
NPT-IGBT, Non-Punch Through- IGBT
PT-IGBT, Punch Through-IGBT
RC-IGBT, Reverse-Conducting IGBT
IGCT, Integrated Gate-Commutated Thyristor
A-IGCT, Asymmetrical-IGCT
S-IGCT, Symmetrical-IGCT
IGS, Integrated Gas System
IIC/I2C, Inter-Integrated Circuit (bus)
ILD, Inter-Layer (Interlayer) Dielectric
IMB, Integrated Module Board
IMC, Intermetallic Compound
IMD, Inter-Metal Dielectric
IMEC, Interuniversity Microelectronics Center
IMS, IP Multimedia Subsystem; Intelligent Manufacturing System
IoT, Internet of Things
I/O, Input/Output
IP, Intellectual Property; Internet Protocol
IPG, Implantable Pulse Generator
IPO, Initial Public Offering
IPTV, Internet Protocol Television (and Video)
IQC, Incoming Quality Control
Appendix C: Abbreviations of IC Terminology 1983

IRT, Isochronous Real-Time

ISA, Instruction Set Architecture, Intelligent Speed Adaptation/Advice
ISDN, Integrated Services Digital Network
ISSCC, (IEEE) International Solid-State Circuits Conference
ITA, Information and Technology Association
ITRS, International Technology Roadmap for Semiconductors
IVI, In-Vehicle Infotainment
IXP, Internet Exchange Point

J
JEDEC, Joint Electron Device Engineering Council

K
KVM, Kernel-based Virtual Machine

L
LAN, Local Area Network
LBIST, Logic Built-In Self-Test
LCD, Liquid-Crystal Display
LDCM, Laser Differential Confocal Microscope
LDD, Lightly Doped Drain/Source
LDMOS/LDMOSFET, Lateral Double-diffused MOS (FET)
LDO, Low-Dropout Regulator
LDW, Laser Direct Writing; Lane Departure Warning (Systems)
LED, Light-Emitting Diode
LER, Line Edge Roughness
LGA, Land Grid Array
LIGA, Lithographie, Galvanoformung, Abformung (Lithography, Electroplating,
and Molding)
LIN, Local Interconnect Network
LNA, Low-Noise Amplifier
LOCOS, LOCal Oxidation of Silicon
LPC, Liquid Particle Counter
LPDDR, Low-Power DDR (SDRAM)
LPE, Liquid-Phase Epitaxy
LPG, Laser Pattern Generator
LPP, Laser-Produced Plasma
LPWAN, Low-Power Wide-Area Network
LTCC, Low Temperature Co-fired Ceramics
LTE, Long-Term Evolution
LTPS, Low Temperature Poly-Silicon
LUT, Look-Up Table
LVDS, Low-Voltage Differential Signaling
LVDT, Linear Variable Differential Transformer
LVS, Layout Versus Schematic
1984 Appendix C: Abbreviations of IC Terminology

M
M&A, Mergers and Acquisitions
MAC, Media Access Control
MAN, Metropolitan Area Network
MAU, Makeup Air Unit
MBE, Molecular Beam Epitaxy
MCM, Multichip Module
MCP, Multichip Package
MCT, MOS-Controlled Thyristor
MCU, Microcontroller Unit
MEBL, Multiple-Electron Beam Lithography
MFC, Mass Flow Controller
MGS, Metallurgical Grade Silicon
MGT, MOS-Gated Thyristor
MEMS, Microelectromechanical Systems
MESFET, Metal-Semiconductor FET
MFC, Mass Flow Controller
MFLOPS, Million FLOPS
MGT, MOS-Gated Thyristor
microLED (micro-LED, mLED or μLED), Micro Light-Emitting Diode
MIM, Metal-Insulator-Metal
MIPS, Microprocessor without Interlocked Pipeline Stages; Million Instructions
Per Second
MLP, Molded Laser Package
MMC, Multi-Media Card
mmWave, Millimeter Wave
MOCVD/MOVPE, Metalorganic Chemical Vapor Deposition/ Metalorganic Vapor
Phase Epitaxy
MOM, Metal-Oxide-Metal
MOPA, Master Oscillator Power Amplifier
MPEG-1, Moving Picture Experts Group Phase 1
MPLS, Multi-Protocol Label Switching
MPU, Microprocessor Unit
MR, Mixed Reality
MPW, Multi-Project Wafer
MRAM, cf. RAM
MRI, Magnetic Resonance Imaging
MSC, Mobile Switching Center
MTBF, Mean Time Between Failures
MTTR, Mean Time To Repair
MTF, Modulation Transfer Function
MTJ, Magnetic Tunnel Junction
MTP, Multi-Time Programmable
MUF, Molded Underfill
Appendix C: Abbreviations of IC Terminology 1985

N
NAND, NAND flash (memory)
NASA, National Aeronautics and Space Administration
NASDAQ, National Association of Securities Dealers Automated Quotations
NBE, Neutral Beam Etching
NEGF, Non-Equilibrium Green’s Function
NEMS, Nano-Electromechanical Systems
NGN, Next Generation Network
NIL, Nanoimprint Lithography
NOR, NOR flash (memory)
NPL, Narrowband over Power Line
NPU, Network Processor Unit
NPV/NPW, Net Present Value/Worth
NRAM, Nano-RAM (CNT RAM)
NVM, Non-Volatile Memory, Nonvolatile Memory
NW, Nanowire (Nano-Wire)
NYSE, New York Stock Exchange

O
OAI, Off-Axis Illumination
OCD, Optical Critical Dimension
OCV, On-Chip Variation
OEE, Overall Equipment Effectiveness
OFET, Organic Field-Effect Transistor
OFDM, Orthogonal Frequency Division Multiplexing
OHT, Overhead Hoist Transport
OLED, Organic Light-Emitting Diode
OLT, Optical Line Terminal
OML, Optical Maskless Lithography
ONTs, Optical Network Terminals
ONUs, Optical Network Units
Op-Amp, Operational Amplifier
OPC, Optical Proximity Correction
OpenCL, Open Computing Language
OpenGL, Open Graphics Library
OpenMP, Open Multi-Processing
OPEX, Operating Expenses
ORC, Optical Rule Checking/Check
OSAT, Outsourced Semiconductor Assembly and Test (Packaging and Test)
OTN, Optical Transport Network
OTP, One-Time Programmable
OQC, Outgoing Quality Control
1986 Appendix C: Abbreviations of IC Terminology

P
P&R, Place and Route
PaaS, Platform as a Service
PAI, Pre-Amorphization Implantation
PAL, Programmable Array Logic
PAS, Parking Assist System
PATA, Parallel AT (Advanced Technology) Attachment
PC, Personal Computer
PCB, Printed Circuit Board
PCell, Parameterized Cell
PCIe, Peripheral Component Interconnect Express
PCM, Phase-Change Memory/Material; Process Control Monitor/Monitoring
PCRAM, Phase-Change Memory/RAM
PCS, Powertrain Control System
PDK, Process Design Kit
PDSOI/PD-SOI, Partially Depleted SOI
PEALD, Plasma-Enhanced Atomic Layer Deposition
PEB, Post Exposure Bake
PECVD, see CVD
PEL, Proximity Electron Lithography
PER, Price/Earnings Ratio, P/E Ratio
PETEOS, 见TEOS
PFM, Pulse Frequency Modulation
PGA, Programmable-Gain Amplifier; Pin Grid Array
PHLX, Philadelphia Stock Exchange (NASDAQ OMX PHLX)
PI, Power Integrity
PiN/PIN/P-i-N (diode), p-intrinsic-n (diode)
PIND, Particle Impact Noise Detection
RISC, Reduced Instruction Set Computer
PLA, Programmable Logic Arrays
PLC, Power Line Communication/ Carrier
PLCC, Plastic Leaded Chip Carrier
PLD, Programmable Logic Devices
PLL, Phase-Locked Loop
PMD, Pre-Metal Dielectric
PMT, Photomultiplier Tubes
PMU, Power Management Unit
PON, Passive Optical Network
APON, Asynchronous Transfer Mode PON
EPON, Ethernet PON
GPON, Gigabit PON
PoP, Package on Package
POWER, Performance Optimization With Enhanced RISC (IBM)
PowerPC (PPC), POWER – Performance Computing, cf. POWER
Appendix C: Abbreviations of IC Terminology 1987

PPAC, Power-Performance-Area-Cost
PROFINET, Process Field Net
PROM, cf. Read-Only Memory
PSG, Phosphorus-doped silicon dioxide (silicate) glass
PSM, Phase Shift Mask; Photoactive Semiconductor Material
PSoC, Programmable System-on-Chip
PSRR, Power Supply Rejection Ratio
PTP, Precision Timing Protocol
PUF, Physical/Physically Unclonable Function
PVD, Physical Vapor Deposition
DCPVD, Direct Current PVD
EBPVD, Electron-Beam PVD
RFPVD, Radio Frequency PVD
PWM, Pulse Width Modulation

Q
QAM, Quadrature Amplitude Modulation
QFN, Quad Flat Nonleaded Package
QFP, Quad Flat Package
QKD, Quantum Key Distribution
QLED/QD-LED, Quantum Dot Light-Emitting Diode
QPSK, Quadrature Phase Shift Keying
Qubit/Qbit, Quantum Bit

R
R&D, Research and Development
Radar, Radio Detection and Ranging
RAID, Redundant Array of Independent Disks
RAM, Random-Access Memory
DRAM, Dynamic RAM
FeRAM/F-RAM/FRAM, Ferroelectric RAM
MRAM, Magnetoresistive RAM
nvRAM/NVRAM, Non-Volatile RAM
PRAM/PCRAM, Phase-Change Memory/ RAM
RRAM, Resistive (Switching) RAM
SDRAM, Synchronous Dynamic RAM
SRAM, Static RAM
RDL, Redistribution Layer
REBL, Reflective Electronic Beam Lithography
RESUF, REduced SURface
RET, Resolution Enhancement Technology
RF, Radio Frequency
RFIC, Radio-Frequency Integrated Circuit
RFID, Radio-Frequency Identification
RHEED, Reflection High-Energy Electron Diffraction
1988 Appendix C: Abbreviations of IC Terminology

RIBE, Reactive Ion-Beam Etching, cf. RIE

RIE, Reactive Ion Etching, cf. RIBE
DRIE, Deep Reactive Ion Etching
MERIE, Magnet Enhanced RIE
RISC, Reduced Instruction Set Computer
RMS, Root Mean Square
RNA, Ribonucleic Acid
RNN, Recurrent Neural Network
ROE, Rate of return on common stockholders’ Equity
ROI, Return on Investment
ROM, Read-Only Memory
EEPROM, Electrically Erasable Programmable ROM
EPROM, Erasable Programmable ROM
MROM, Mask ROM
PROM, Programmable ROM
RPG, Replacement (Poly) Gate
RPS, Remote Plasma Source
RRAM, cf. RAM
RSA, Rivest-Shamir-Adleman (cryptosystem)
RTA, Rapid Thermal Annealing/ Anneal
RTD, Rapid Thermal Diffusion
RTL, Register-Transfer Level
RTN, Rapid Thermal Nitridation
RTO, Rapid Thermal Oxidation
RTOS, Real-Time Operating System
RTP, Rapid Thermal Processing
RTS, Random Telegraph Signal
RVS, Reference Voltage Supplies

S
SaaS, Software as a Service
S&P 500, Standard & Poor’s 500
SAC, Self-Aligned Contact
SAPS, Space Alternating Phase Shift (Megpie)
SAR ADC, Successive Approximation Register ADC
SAS, Serial Attached SCSI, cf. SCSI
SATA, Serial AT (Advanced Technology) Attachment
SBD, Schottky Barrier Diode
SCADA, Supervisory Control And Data Acquisition System
SCE, Short-Channel Effect
SCL, Serial Clock Line
SCR, Silicon-Controlled Rectifier
SCS, Spinal Cord Stimulation
SCSI, Small Computer System Interface
SDE, Source-Drain Extension
Appendix C: Abbreviations of IC Terminology 1989

SDL, Serial Data Line

SDR, Software-Defined Radio
SDRAM, cf. RAM
SDTV, Standard-Definition Television
SEC, US Securities and Exchange Commission
SEG, Selective Epitaxial Growth
SEM, Scanning Electron Microscope
SEMATECH, Semiconductor Manufacturing Technology
SEMI, Semiconductor Equipment and Materials International
SerDes, Serializer/Deserializer
SFGR, Site Front Least-Squares Range
SFIL, Step and Flash Imprint Lithography
SG&A, Selling, General & Administration
SHARC, Super Harvard Architecture Single-Chip Computer
SI, Signal Integrity
SI Units, The International System of Units, Système international (d’unités)
SIA, Semiconductor Industry Association
SiC, Silicon Carbide (carborundum)
SiGe, Silicon-Germanium
SIM, Subscriber Identity Module (card)
SIMD, Single Instruction, Multiple Data
SIMM, Single Inline Memory Module
SIMOX, Separation by Implantation of oxygen
SIMT, Single Instruction, Multiple Threads
SiP, System in Package; System-in-a-Package
SiPM, Silicon Photomultiplier
SIP, Self-Ionized Plasma
SLAM, Simultaneous Localization And Mapping
SLM, Spatial Light Modulator
SMIC, Semiconductor Manufacturing International Corporation
SMO, Source Mask Optimization
SMT, Surface-Mount Technology; Stress Memorization Technique
SNN, Spiking Neural Network
SoC/SOC, System on a Chip; System on Chip
SOG, Spin-On Glass
SOI, Silicon on Insulator
SoPC, System on Programmable Chip
SOS, Silicon on Sapphire
SOT, Spin-Orbit Torque, Small Outline Transistor
SPARC, Scalable Processor ARChitecture
SPE, Solid Phase Epitaxy
SPI, Serial Peripheral Interface
SPICE, Simulation Program with Integrated Circuits Emphasis
SPOS, Single Particle Optical Sensor/Sizing
SPS, Sampling Per Second
1990 Appendix C: Abbreviations of IC Terminology

SRAF, Sub-Resolution Assist Feature

SRAM, cf. RAM
SSD, Solid-State Drive
STA, Static Timing Analysis
STI, Shallow Trench Isolation
STT-RAM, Spin-Transfer Torque RAM
SSTA, Statistical Static Timing Analysis
SVM, System Virtual Memory
SWP, Surface Wave Plasma

T
TAB, Tape-Automated Bonding
TCAD, Technology Computer Aided Design
TCP, Transmission Control Protocol; Transformer Coupled Plasma
TCS, Traction Control System; Trichlorosilane
TDD, Time-Division Duplexing
TD-CDMA, Time-Division-Code Division Multiple Access
TD-SCDMA, Time Division-Synchronous Code Division Multiple Access
TDEA, Triple Data Encryption Algorithm
TDI, Time Delay Integration
TDMAT, Tetrikis Dimethyl-Amido Titanium
TDR, Time-Domain Reflectometry
TEE, Trusted Execution Environment
TEM, Transmission Electron Microscope
TEOS, Tetraethyl Orthosilicate
PETEOS, Plasma-Enhanced TEOS
TFET, Tunnel Field-Effect Transistor
TFLOPS, Tera FLOPS
TFT, Thin-Film Transistor
THT, Through Hole Technology
THz, Tera Hertz (Hz)
TIM, Thermal Interface Material
TIS, Tool-Induced Shift
TMR, Tunneling Magnetoresistance
TMU, Time Measurement Unit; Total Measurement Uncertainty
TMV, Through Mold Via
TRIAC, Triode for Alternating Current
TPM, Trusted Platform Module
TPMS, Tire Pressure Monitoring System
TPU, Tensor Processing Unit
TSR, Traffic Sign Recognition
TSV, Through-Silicon Via
TTV, Total Thickness Variation
Appendix C: Abbreviations of IC Terminology 1991

U
UART, Universal Asynchronous Receiver/Transmitter
UATA, Ultra ATA
UAV, Unmanned/Unattended Aviation Vehicle (drone)
UHDTV, Ultra High-Definition Television
UHVCVD, see CVD
ULPA, Ultra-Low Penetration Air Filter
UPS, Uninterruptible Power Supply/Source
UPW, Ultrapure Water
USB, Universal Serial Bus
USG, Undoped Silicate Glass
UTB, Ultra-Thin Body

V
VCD, Video Compact Disc
VC/PE, Venture Capital/Private Equity
VDMOS/VDMOSFET, Vertical Double-diffused MOS (FET)
VGA, Variable Gain Amplifier; Video Graphics Array
VIE, Variable Interest Entity
VLIW, Very Long Instruction Word
VLSI, Very-Large-Scale Integration
VMI, Vendor-Managed Inventory
VPE, Vapor-Phase Epitaxy
VPN, Virtual Private Network
VR, Virtual Reality

W
Wi-Fi, Wireless Fidelity
WIS, Wafer-Induced Shift
WIW, Within Wafer
WL, Word-Line, cf. Bit-Line
WLAN, Wireless Local Area Network
WL-CSP, Wafer-Level Chip Scale Package
WLP, Wafer-Level Package
WLU, Wafer-Level Underfill
WOFE, Wholly Owned Foreign Enterprise
WPH, Wafers Per Hour
WSC, World Semiconductor Council
WSQ, Wavelet Scalar Quantization
WSTS, World Semiconductor Trade Statistics
WTW, Wafer-to Wafer
WWTP, Wastewater Treatment Plant
1992 Appendix C: Abbreviations of IC Terminology

X
xDSL
ADSL, Asymmetric DSL
HDSL, High-Speed DSL
IDSL, ISDN DSL
RADSL, Rate Adaptive DSL
SDSL, Symmetric DSL
VDSL, Very-High-Bit-Rate DSL

Y
Y, yotta
y, yocto

Z
ZCS, Zero Current Switching
ZPAL, Zone-Plate-Array Lithography
ZVS, Zero Voltage Switching

Data compilation: Chun-Zhang Chen

Appendix D: Common Glossaries of IC Industry

A
AC/DC Converter: a device that converts the power of an alternative current
(AC) to the power of an equivalent direct current (DC), and there are linear
AC/DC converters and switching power AC/DC converters.
Active-Matrix Organic Light-Emitting Diode (AMOLED): is a display device
technology; it is self-luminescent and has broad color gamut, wide field of view; it
provides an increased refresh rate and has reduced power consumptions, making
it particularly suitable for portable electronic devices such as in smartwatches,
smartphones, laptops, and televisions.
Advanced Driver-Assistance Systems (ADAS): is a subset of the driver assistance
system for supporting the driver in their primary driving task. It can detect and
evaluate the environment of the vehicle by means of sensors, and then inform and
warn the driver, provide feedback on driver actions, increase comfort, and reduce
the workload by actively stabilizing or maneuvering the car.
Advanced Encryption Standard (AES): is a specification for the encryption of
electronic data, used as Cryptography of Computer Security Standard; AES was
officially adopted and announced by NIST in Oct. 2001 (FIPS PUB 197). AES is
also known by its original name Rijndael (a portmanteau of two Belgian cryp-
tographers, Vincent Rijmen and Joan Daemen).
Amplitude Modulation (AM): in contrast with frequency modulation, AM is an
amplitude (signal strength) modulation technique at a constant frequency; AM is
widely used in electronic communication, most known for transmitting informa-
tion via a radio carrier wave, such as radio broadcasting. Several modes of AM
are available: general AM, double sideband (DSB) AM, single sideband (SSB)
modulation, and vestigial sideband (VSB) AM.
Analog Signal: an analog signal is continuous, meaning that there are no breaks or
interruptions. The analog signal is used to express messages from temperature,
humidity, pressure, length, current, voltage, etc. It can have numerous values
within a time period.
Analog-to-Digital Converter (ADC): a circuit or device that can convert analog
signal into digital signal, also known as A-D or A/D converter, etc.
1994 Appendix D: Common Glossaries of IC Industry

Application-Specific Integrated Circuit (ASIC): specially designed and/or

manufactured IC, participated by end-user, that aimed to solve electronic system
requirements, the features of an ASIC product include specific, optimized system-
level planning, optimized performance, secure consideration, etc.
Artificial Intelligence (AI): is a branch of computer sciences, a new subject to deal
with research and development in applying in simulating, extending, and
expanding human intelligence, such as theory, methodology, technology, and
application. AI is often meant to be a narrow or focused area in robotics, matching
learning, voice recognition visual pattern, language processing, etc.
Audio Codec: a device to encode and decode the audio data stream; based on a given
document or media audio coding format, the device can process compression or
decompression.
Audio Video Standard (AVS): is formulated by audio and video coding standard
workgroup of China according to the open international rules and used for the
digital audio and digital video series compression standard. The first generation
AVS (AVS1) initiated in 2002 and encompasses system, video, audio, and digital
authorization management. The second generation is referred to as AVS2. The
primary application target of AVS2 is Ultra HD (High Definition) video,
supporting the efficient compression of ultra-high resolution (4K above), HDR
(High Dynamic Range) videos. AVS2 has been submitted to the IEEE interna-
tional standard (Standard No.: IEEE1857.4) for application.
Augmented Reality (AR): is a technology that superimposes a computer-generated
image on a user’s view of the real world, such that a composite view and an
augmented reality is provided and experienced.
Automatic Test Equipment (ATE): test equipment used to check the performance
of a DUT and provide fault diagnosis and isolation. ATE is commonly used to test
the functional integrity and performance specifications of an IC and to ensure the
quality of IC product(s). Sometimes, ATE is also used to imply such a test
method.
Avalanche Photodiode (APD): a highly sensitive optoelectronic device, when a bias
voltage applied, the initial photocurrent is amplified via charge carries accumu-
lation and converted into electricity.
Aviation Flight Control: in such systems, a pilot uses to control the forces of flight
and the aircraft’s direction and attitude and to stabilize and control the centroid
motion (lift, forward, left, and right) and angular motion (pitch, yaw, and roll) of
an aircraft. Aircraft generally refers to airplanes but also includes airships,
balloons, helicopters, and rotorcrafts.

B
Battery Management System (BMS): is an electronic system that manages a
rechargeable battery (cell or battery pack), and the system can conduct many
functions, including data collection, status evaluation, heat management, and safe
operation of charge/discharge. Data display, breakdown diagnosis, safety
alarming, and data communication.
BeiDou Navigation Satellite System (BDS): is a Chinese satellite navigation
system. There have been three generations of BDS: BeiDou-1 (2000–2002)
Appendix D: Common Glossaries of IC Industry 1995

consisted of three satellites which was decommissioned. BeiDou-2 became

operational in 2011; it has been offering services with 15 satellites to AP region
since 2012. BeiDou-3 was launched in 2015, and it has 18 satellites as of 2018; it
will eventually consist of 35 satellites to provide global services on 2020.
Binocular Vision System: in biology, binocular vision is a type of vision in which
an animal having two eyes is able to perceive a single three-dimensional image of
its surroundings. In binocular vision system, through using two video cameras at
different locations taking images, a matching algorithm can be used to calculate
perspective relations between each pair of pixels to establish in-depth three-
dimensional image of the object.
Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS): a technique or
a process to integrate bipolar and CMOS into a single integrated circuit, such IC
has benefits of high integration and low power of CMOS, as well as advantages of
high-speed and large current driving capacity of bipolar.
Bipolar Complementary and Double-diffused Metal-Oxide-Semiconductor
(BCD): a silicon-based process used in manufacturing of power devices, to
integrate bipolar, CMOS and DMOS into a single integrated circuit.
Bluetooth: is a wireless technology used for data exchange between fixed and
mobile devices. The frequency used is 2.400–2.485 GHz UHF of ISM band for
over short distances suitable for personal area networks (PANs). Bluetooth was
originally developed by Ericsson in 1994, the latest version is 5.2 as of 2020, and
the IEEE standard is IEEE 802.15.1, while it is maintained by Bluetooth Special
Interest Group (SIG).
Body Control Module (BCM): a module designed to control electronics in an
automobile; these electronic components include the lighting, window brushes,
door locks, power windows, sunroof, rear mirror, remote control, etc. The module
can also have power management, voltage protection, relay control, and system
sleeping functions. BCM is a must have.
Brown Goods: in general refers to household appliances to provide entertaining and
leisure information, such as audios, videos, TVs, and game players.
Built-In Self-Test (BIST): a relevant circuit embedded in an IC design to enable the
design to be self-testable, such technique can increase the reliability and reduce
the repairing cycle.
Bulk Gas System: in semiconductor manufacturing, the provider or providing
system for heavily used nitrogen, hydrogen, oxygen, etc., is called bulk gas
system.
Bump: in packaging, a bump formed with metal material used as a connection
between chip and board; it also plays multiple roles of mechanical connection,
electronic connection, and heat dissipation.

C
Cable Modem: a cable modulation and demodulation device set at user’s end to
transmit data and communication message in a wired TV system.
Cellular Mobile Communication: also known as wireless mobile communication
systems, which divide a large geographic area into smaller sections or cells, each
1996 Appendix D: Common Glossaries of IC Industry

with a low-power wireless transmitter, to establish connects between end-users

and terminals, for the purpose of optimizing the use of a limited number of
frequencies.
Central Processing Unit (CPU): the core IC in computers, following computer
program to execute instructions, CPU is an essential unit that performs basic
arithmetic, logic, control, and input/output operations.
Charge-Coupled Device (CCD): is a solid device made of semiconductor materials
of high light-sensitive; through pulsed voltage to generate and control potential
wells, to transport messages stored in form of electric charges.
Chemical Vapor Deposition (CVD): a widely used technique and a basic tool in
semiconductor industry to produce thin films for IC manufacturing; CVD process
is based on thermally induced chemical reactions at the surface of a heated
substrate.
Chip: literally known as Integrated Circuit (IC), a product of an electronic circuit
integrated on a piece of semiconductor material.
Clean Room: in architecture, clean rooms are designed to be controllable, to reduce
indoor introduction, production of airborne contaminants; other environmental
parameters can be controlled following requirements. In semiconductor
manufacturing, it implies parameters such as cleanness, temperature, humidity,
pressure, etc., can be controlled in the confined area.
Closed-Transition Transfer Switch (CTTS): a switch that used in transitional mode
to connect electricity without interruption of the electric charges.
CMOS Image Sensor (CIS): consisted of photodiodes, MOSFETs, amplifiers, etc.
It is also known as active pixel sensor (APS).
Code-Division Multiple Access (CDMA): is a channel access method used by various
radio communication technologies; it has multiple access, where several transmit-
ters can send information simultaneously over a single communication channel.
Comparator: an integrated circuit that can compare the voltage or current at its two
inputs and output the result of the comparison.
Complementary Metal-Oxide-Semiconductor (CMOS): a voltage-controlled
amplifying device, a basic unit of digital IC. CMOS is widely used in micropro-
cessor, microcontroller, SRAM, other digital IC, as well as in sensors, data
convertor of communication circuits, etc.; its processes include planar silicon-
bulk, FinFET, SOI, etc. The technique was patented (US Patent 3356858) in 1963
by Frank Wanlass of Fairchild Semiconductor.
Complex Instruction Set Computer (CISC): the strategy of CISC architecture is to
use a great number of instructions (includes complex ones). Each instruction in
the program is executed in serial order, and each operation in an instruction is
executed in serial order too. Rich instruction set enables the program design
relatively simple, yet the control unit in circuit structure becomes complicated.
Composite Video Broadcasting Signal (CVBS): also known as base-band
video, CVBS is a conventional method for video data transmission that uses single
channel analog wave transmission to transmit video data (resolution is 480i or 576i).
Computer Peripheral: a general name for input, output, and external storage
equipment in computer system.
Appendix D: Common Glossaries of IC Industry 1997

Conductivity Sensor: can be used in various areas, such as the water quality, can be
used to determine in super pure-water, pure water, drinking water, contaminated
water, etc., the conductivity or ion density of aqueous sample.
Consumer Electronics: a general name for electronic products in daily usage can be
divided into personal consumer products and household consumer products.
Controller Area Network (CAN): a type of field bus using serial communication
network, CAN is widely used in industry measuring and control, as well as in
industry automation.

D
Data Center: a complex set of equipment, and it includes not only computer system
and other related equipment such as communication system and storage system
but also includes redundant data communication linkage, environmental control,
monitoring, and various security equipment and facilities.
Damascene: also called Damascus Damascene, is a process method used in IC
manufacturing for interconnections between devices.
DC-DC Converter: an electronic circuit or electromechanical device that converts a
source of direct current (DC) from one voltage level to another one for suitable
application.
Design for Manufacturability (DFM): a design methodology to simplify and
improve quality and reduce cost of parts, products, and process in manufacturing.
Design for Testability (DFT): also called design for test, is a method or a test circuit
used, not altering original product functionalities, to detect manufacturing faults
so as to increase product yield and reduce cost.
Die: is a half-way product of integrated circuit, completed the manufacturing but not
yet packaged; therefore, it is often called “naked die”.
Digital Signal Processor (DSP): a specific microprocessor, its architecture design is
most suitable for digital signal processing, widely used in communication and
information system, in signal and information processing, automatic control,
radar, military, aerospace, medical and home appliances, etc.
Digital Subscriber Line (DSL): a digital transmission linkage line between user
equipment and local communication provider.
Digital-to-Analog Converter (DAC): a circuit used to convert digital signal to
analog signal, it is also called D-A or D/A converter.
Digital Video Broadcasting (DVB): a set of international open standard of digital
video broadcasting used in Europe.
Duplexer: is an electronic device that allows bi-directional (duplex) communication
over a single path, and the function of a duplexer is to isolate emitting signal and
receiving signal, meanwhile to ensure reception and transmission of normal
signal simultaneously.

E
Electrically Erasable Programmable Read-Only Memory (EEPROM, also
E2PROM): a read-only memory whose contents can be erased and
reprogrammed by user using a pulsed voltage.
1998 Appendix D: Common Glossaries of IC Industry

Electronic Design Automation (EDA): is a specialized sector in semiconductor

industry focused on electronic design automation, including the tools, methodol-
ogies, and flows associated with the fabrication of electronic systems.
Electronic Toll Collection (ETC) system: through reading a vehicle’s RFID tag,
using a wireless system to automatically collect the usage fee or toll charged to
vehicles using toll roads, High-Occupancy Vehicle (HOV) lanes, toll bridges, and
toll tunnels. ETC technology was first introduced in Bergen, Norway, in 1986,
operating together with traditional toll booths.
Emitter Turn-Off (ETO) Thyristor: a new type of power semiconductor device, it
consists of an emitter switch (low-voltage MOSFET) in series with a gate turn-off
thyristor (GTO), combining the advantages of both the GTO and MOSFET.
Erasable Programmable Read-Only Memory (EPROM): a non-volatile and pro-
grammable ROM, it can be erasable by using different techniques, such as UV
light, and programmable again with different data and code.
Etching: a processing step in IC manufacturing, with a solution, mixture, or mixed
gases to erode a thin film or surface of substrate, so to remove the unwanted
material selectively or unselectively.
Extreme Ultraviolet (EUV) Lithograph: a soft X-ray technology, which has a
wavelength of 13.5 nm, it allows exposure of fine circuit patterns for CMOS
with a half-pitch below 22 nm that cannot be exposed by the conventional optical
lithography using an ArF excimer laser of 193 nm.
Extremely High Frequency (EHF): ITU designated band in radio frequencies of
30–300 GHz, wavelength of 1 cm to 1 mm (also called millimeter wave); EHF
lies between the super high-frequency band (SHF, 3–30 GHz), and the far infrared
band (FIR, 300 GHz–20 THz).

F
Fabless: means a semiconductor or IC company who designs and sells chips but
does not manufacture the silicon wafers, or chips, used in its products; instead, it
outsources the fabrication (“fab”) to a manufacturing plant or foundry.
Facility Monitoring and Control System (FMCS): used to monitor operational
status of equipment and to collect operational data in the central supplying
system, so as to provide a controlled operating conditions and extend the reli-
ability of critical systems.
Fast Recovery Diode (FRD): also called high-speed diode, its pn junction is
designed to make the reverse recovery time (trr) two to three times smaller,
compared with general rectifying diodes. FRD is mainly used in switching
power supply, PWM, frequency changing circuit; also used as high-frequency
rectifying, flyback or freewheeling, and damping diodes.
Field-Programmable Gate Array (FPGA): different from a logic gate that has a
fixed function, it is an integrated circuit using configurable logic block (CLB), to
be configured by a designer after manufacturing. FPGA has flexible architecture,
short design cycle, wide application, and easier to design than an ASIC.
Appendix D: Common Glossaries of IC Industry 1999

Fin Field-Effect Transistor (FinFET): a novel type of 3D structured CMOS device,

the main features are fin-shaped thin layer of silicon folded to form a conducting
channel, and double-sided or triple-folded form of gate that control the device.
Filter: a device or circuit selecting certain frequencies to allow specified signal
component to pass through normally, to filter frequencies out of interest
effectively.
Floating Point Operations Per Second (FLOPS): a measure of computer perfor-
mance, it is a more accurate measure than measuring million instructions per
second (MIPS), especially when floating-point calculations are required in sci-
entific computations.
Forward Collision Warning (FCW) Systems: through electronic system sensing
the degree of damage in the front part of a vehicle, to avoid collisions and to
provide warnings.
Foundry: a semiconductor fabrication plant, called a fab or foundry, which is
separated from an IC design to run manufacturing business.
Frequency Modulation (FM): in contrasts with amplitude modulation, FM is a
frequency modulation technique at a constant amplitude; FM is widely used in
electronic communication, most known for transmitting information via a radio
carrier wave, such as radio broadcasting.
Fully Depleted Silicon on Insulator (FD-SOI): It uses an ultra-thin body (UTB)
layer of silicon of a few nm over a buried oxide as a means to reduce leakage and
variation in chips. FD-SOI can effectively inhibit the short-channel effect due to
the gate length decrease and leakage increase.

G
Galileo: on live in 2016, is Europe’s Global Navigation Satellite System (GNSS),
which was developed and established by the European Union through the
European GNSS Agency (GSA). The first Galileo test satellite was launched in
2005; as of July 2018, 22 of the planned 30 active satellites are in orbit.
GLObal NAvigation Satellite System or GLONASS (Russian: ГЛОНАСС): the
satellite navigation system developed and by the Soviet Union in 1976, until the
completion of the constellation in 1995. As of October 2011 the full orbital
constellation of 24 satellites was restored, enabling full global coverage by
Russia.
Global Positioning System (GPS): the satellite navigation system was started by the
US Department of Defense in 1973, with the first prototype spacecraft launched
in 1978 and the full constellation of 24 satellites operational in 1993 and now for
use by both the military and the general public.
Global System for Mobile communications (GSM): is a communication standard
developed by the European Telecommunications Standards Institute (ETSI) to
describe the protocols for second-generation (2G) digital cellular networks used
by mobile devices such as mobile phones and tablets. GSM was first deployed in
Finland in 1991 and became a global standard for mobile communications by the
mid-2010s.
2000 Appendix D: Common Glossaries of IC Industry

Graphics Processing Unit (GPU): a specialized IC designed to process images or

graphs in parallel mode for the computing efficiency, compared with a central
processing unit (CPU) for algorithms that process large blocks of data in parallel.
GPUs are widely used in embedded systems, mobile phones, personal computers,
workstations, and game consoles.
Graphics Double Data Rate (GDDR): based on double data rate (DDR) SDRAM
technologies, GDDR is specialized and tailored for use with video graphics cards
containing GPUs.

H
Hall Effect Sensor: is consisted basically of a thin piece of rectangular p-type
semiconductor material (GaAs, InSb, or InAs) passing a continuous current
through itself. It can measure the change of magnetic field, as well as a physical
quantity producing and affecting the magnetic field.
Hardware Description Language (HDL): a specialized computer language, based
on C language and part of EDA system, HDL is used to describe the structure and
behavior of electronic circuits, and most commonly, digital logic circuits.
Heating, Ventilating, and Air-Conditioning (HVAC): the system provides control
of temperature, humidity, air cleanness, and circulation, to result in a comfort of
thermal environment.
Heterojunction Bipolar Transistor (HBT): is a type of bipolar junction transistor
(BJT), to generate a doping in favor of frequency, different semiconductor
materials are used in the emitter and base regions.
High-bandwidth Digital Content Protection (HDCP): an encryption protocol for
digital content that developed by Intel Corporation, when digital contents are
unauthorized duped, HDCP technology produce an interference to degrade the
quality of the coped contents, and hence the protection of the original data.
High-Definition Multimedia Interface (HDMI): is an audio/video interface for
transmitting high-quality and high-bandwidth streams of audio and video (such
as multichannel-surround audio and 4K video signals) between devices; it can be
a connector and cable capable of transmitting uncompressed digital data. The
HDMI technology is widely used with devices such as an HDTV, projector, DVD
player, or Blu-ray player.
High Efficiency Video Coding (HEVC): a.k.a. H.265 and MPEG-H Part 2, is a
video compression standard, offers double video data compression ratio,
designed as a successor to the widely used Advanced Video Coding (AVC,
H.264, or MPEG-4 Part 10). The resolution supported can be 8192  4320
pixels, including 8K ultra-high-definition (UHD).
High-Electron-Mobility Transistor (HEMT): also called heterostructure FET (HFET),
or modulation-doped FET (MODFET), invented in 1979 by Takashi Mimura of
Fujitsu. HEMT is a field-effect transistor incorporating a junction between two
materials with different band gaps (i.e., a heterojunction) as the channel.
High-k Metal Gate (HKMG): using a high dielectric constant material (high κ, e.g.,
hafnium, Hf) replacing commonly used SiO2 in gate insulation, together with
metal copper in place of metal aluminum, such that under the continuous
Appendix D: Common Glossaries of IC Industry 2001

shrinkage of gate oxide thickness, to increase gate thickness so as to inhibit the

gate leakage current.

I to K
Integrated Device Manufacturer (IDM): is a semiconductor company who
designs, manufactures and sells IC products.
Integrated Circuit (IC): is a circuit or system which executes certain functions, a
semiconductor chip which has gone through a series of special manufacturing
process, to have integrated a set of active devices (such as transistors and diodes)
and inactive devices (such as resistors, capacitors), etc., interconnected on a
semiconductor compound (Si or GaAs), sealed in a package.
Input/Output Buffer Information Specification (IBIS): a model used to describe
characteristics of I/O buffer information. Behavioral description of a single I/O
terminal can be decomposed into a serial of simple functional module; a collec-
tion of these simple functional modules form a complete IBIS model.
Institute of Electrical and Electronics Engineers (IEEE): an international
non-profit association for engineers in electronic technology and information
science. IEEE has 39 societies; each one is focused on a certain knowledge
area, providing specialized publications, conferences, business networking, etc.
Established in 1963, IEEE is the world largest technical professional
organization.
Integrated Gate-Commutated Thyristor (IGCT): jointly developed by Mitsubishi
and ABB in mid-1990s related to GTO thyristor, a power semiconductor elec-
tronic device, IGCT is used for switching electric current in industrial equipment.
Intellectual Property (IP): refers to a work or design whose result or function can be
used or reused in other related design. It is also called IP core/block.
Inter-Integrated Circuit (I2C): a synchronous serial protocol developed by Philips
in 1982 using two-wire, I2C (or I2C) can be used to connect between the bus and
device to provide serial communication.
International Technology Roadmap for Semiconductors (ITRS): a technical
organization formed of SIA, ESIA, JSIA, KSIA, and TSIA in 1998, the experts
form worldwide semiconductor industry work together to provide a technical
roadmap for improvement in performance of future IC design and products. The
new name since 2014 is ITRS 2.0.
Internet of Things (IoT): is a system of connected networks and devices; through
wireless communication of data, IoT has extended the application of internet, has
become critical component of IT, and is positioned at an important development
stage.
In-Vehicle Infotainment (IVI) System: a specialized processor used in automobile;
based on a bus system, mobile network, wireless communication and GPS, and
internet service, IVI has become a complete information process system in
automotive.
Joint Electron Device Engineering Council (JEDEC): established in 1958, JEDEC
is the global organization in developing open standards for the microelectronics
2002 Appendix D: Common Glossaries of IC Industry

industry, with more than 3000 volunteers representing nearly 300 member
companies.
Known Good Die (KGD): The term formed in 1990s. It was meant for tests of chips
on functional, parameters, aged selection, and reliability, to provide the quality
and reliability meeting the final requirements. In general, KGD is a chip fully
tested before being placed into its package such as used in a multichip module
(MCM).

L
Laser Diode (LD): similar to a LED and driven by the voltage, LD pumps directly
with electrical current to create lasing conditions at its pn-junction, which allows
for recombination of an electron with a hole and directly convert electrical energy
into light.
Light-Emitting Diode (LED): a semiconductor device that allows for recombina-
tion of an electron with a hole and directly convert electrical energy into specific
wavelengths for various light colors; corresponding to photons’ energy, the color
is determined by the energy required for electrons to cross the bandgap of the
semiconductor used in LED.
Liquid-Crystal Display (LCD): applied external voltage caused the orientation of
liquid molecules, such that the light intensity of the liquid can be modulated,
resulting in gray or color images.
Low-Dropout Regulator (LDO): is used to provide a stable power supply voltage
independent of load impedance, input-voltage variations, temperature, and time.
LDOs are distinguished by their ability to maintain regulation with small differ-
ences between supply voltage and load voltage.
Low Noise Amplifier (LNA): an LNA is typically designed to increase the desired
RF signal amplitude, meeting required gain without adding distortion or noise.

M
Magnetometer: a device used for measuring magnetism quantities, including the
direction, strength, or relative change of a magnetic field at an application
location.
Mask: also called photomask, is a series of specific geometric patterns from the
design and form of each IC layer ready for lithographic processing.
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET): a type of field-
effect transistor, manufactured through the control of oxidation of the silicon.
Microcontroller Unit (MCU): is a small system design on a single metal-oxide-
semiconductor (MOS) integrated circuit.
Microelectromechanical Systems (MEMS): can also be written as micro-electro-
mechanical systems. Developed from microelectronics, it has combined lithog-
raphy, etching, thin-film, LIGA, Si-micro-processing, non-Si processing, and
precision mechanical process techniques in the manufacturing; it has integrated
micro-sensor, micro-actuator, micro-mechanical structure, micro-power source,
micro-energy source, signal processing and control circuit, high-performance
electronic device, interface, and communication into one micro-device or system.
Appendix D: Common Glossaries of IC Industry 2003

MEMS are merging at the nanoscale into nanoelectromechanical systems

(NEMS) and nanotechnology.
Micro Light-Emitting Diode (microLED): is developed on an emerging flat-panel
display technology, it consists of arrays of microscopic LEDs forming the
individual pixel elements.
Microprocessor without Interlocked Piped Stages (MIPS): is an RSIC system
ISA originally developed at Stanford University, later at MIPS Computer Sys-
tems, now MIPS Technologies. MIPS also stands for Million Instructions Per
Second.
Mixed Reality (MR): MR is a fusion of virtual reality (VR) and augmented reality
(AR) technologies. In a real visual environment, MR technology can add a VR
visual space, and enable VR to change following the real space and interactional,
so to enhance the user’s experience.
Mixed-Signal Design: an IC design involves both digital signal and analog signal
processing circuits.
Mixer: a device that enables two (typically RF) signals of separate frequencies into
one output signal, the frequency of the output signal equals either the difference
of the two input frequencies (downconversion), or the summation of the two input
frequencies (upconversion).
Mobile Communication: is a communication technology that allows users to
communicate with each other in different locations without the use of any
physical connection (wires or cables).
Mobile DDR (mDDR): a.k.a. LPDDR, a new type memory storage device with
double data rate, often used in mobile low power application environment that
meets JEDEC’s standards.
Moore’s Law: is the observation that the number of transistors in a dense IC doubles
about every 2 years, it was proposed by Gordon Moore, the co-founder and
chairman emeritus of Intel Corporation in April 19, 1965.
MOS-Controlled Thyristor (MCT): is a power switch with a MOS gate controlling
the switch’s on and off; MCT is derived from a thyristor by adding the features of
a MOSFET.
Multi-Chip Module (MCM): is the earliest form of a system-in-package (SiP)
containing two or more ICs in a single package. MCM works as a single system
and is capable of executing a function.
Multi-Project Chip/Wafer (MPC/MPW): manufacturing multiple chips attribute to
different users on the same wafer so as to reduce cost, mainly used in early R&D
stages for production of small quantities.

N
Nanosilicon (or nano-silicon): a silicon material, other names include silicon nano-
powder, silicon nanocrystals, silicon nano-particles, and silicon nanopowder.
Nanoscale silicon nano-particles are in spherical form and are typically about
5–25 nm.
2004 Appendix D: Common Glossaries of IC Industry

Network Processor Unit (NPU): is a programmable IC specially used in commu-

nications to process various relevant tasks, including package process, protocol
analysis, search and find for routing, and collection, firewall and QoS of voice
data, etc.

O
Operational Amplifier: a voltage signal amplifying device that processes a feed-
back of resistor and capacitor circuit, results in a high-gain, high-input impedance
and low-output impedance features.
Optical Communication: a type of communication through optical fibers in which
light is used to carry the signal to the remote end, instead of electrical current.
Optical Proximity Correction (OPC): is a photolithography resolution enhance-
ment technique (RET) commonly used to compensate for image errors that occur
during sub-wavelength lithography: printing structures smaller than the wave-
length of light being used.
Organic Light-Emitting Diode (OLED): is a LED in which the emissive electro-
luminescent layer is a thin film of organic compound that emits light when an
electric current flows through.
Orthogonal Frequency-Division Multiplexing (OFDM): is a digital multi-carrier
modulation technique used in 4G communication. OFDM divides the available
spectrum into many carriers, each one being modulated by a low-rate data stream.

P
Printed Circuit Board (PCB): mechanically supports and electrically connects
electronic components through one or more sheet layers of copper laminated
onto and/or between sheet layers of a non-conductive substrate, PCB is prepared
with conductive tracks, pads, and other features etched for interconnecting
various components.
Performance Optimization with Enhanced RISC-Performance Computing
(PowerPC): a RISC-based ISA, the base design is originated from the micropro-
cessor that developed by Apple, IBM, and Motorola (AIM) alliance in 1991.
Phase-Shift Mask (PSM): is a photomask that takes advantage of the interference
generated by phase differences to improve image resolution in photolithography.
Photodiode: is a semiconductor device that converts light into an electrical current.
Photolithography: a patterning process in semiconductor manufacturing, first a
photosensitive polymer is selectively exposed to light through a mask, leaving
a latent image in the polymer, and then the polymer is selectively dissolved to
provide patterned access to an underlying substrate.
Photomask: or simply called mask, contains the pattern of an integrated circuit, the
mask is used in photolithography for selective exposure process in IC
manufacturing.
Photomultiplier Tubes (PMTs): used in light detection of very weak signals, PMTs
are photoemissive devices in which the absorption of a photon results in the
emission of an electron. PMTs have features of fast response, high gain, and high
signal-to-noise ratio; they are sensitive for detection of light in the UV, visible,
and near-IR region of 200–900 nm.
Appendix D: Common Glossaries of IC Industry 2005

Photoresist: a.k.a. resist, a sensitive liquid material to light, and it contains polymer,
solvent, sensitizers, and other additives. When exposed to the light, sensitizers
start chemical reactions which convert the pattern on the mask to silicon
substrate, etc.
Physical Implementation: is also called physical design, part of IC design flow,
which generates physical geometries based on circuit schematic (e.g., analog
design) or gate-level netlist (e.g., digital design); an engineering process using
EDA tools in preparing manufacturing masks in IC.
Physical Vapor Deposition (PVD): is a process used to produce metal vapor
forming thin films and coatings. The most common PVD processes are sputtering
and evaporation. The process is carried out in a vacuum chamber at high vacuum
(10–6 Torr) using a cathodic arc source.
Pizeo-electric Sensor: is a device that uses the piezoelectric effect to measure
environmental changes in physical quantities such as pressure, acceleration,
temperature, strain, or force by converting them to an electrical charge.
Place and Route (P&R): two important steps of digital IC design flow using EDA
tools, and the processes include automatically placing standards cells and/or IP
blocks effectively, as well as routing/connecting them correctly.
Planar CMOS: is the semiconductor manufacturing process used to build individual
components of a transistor and connect transistors together. Based on the surface
passivation and thermal oxidation methods originally by M. Atalla at Bell Labs in
1957, the planar CMOS process was developed by J. Hoerni at Fairchild Semi-
conductor in 1959.
Power Management Unit (PMU): is an IC used in power adjustment and control.
Power-Line Communication (PLC): is the communication technology which uses
the existing electrical power-line wiring for the transmission of the signals. PLC
has been successfully used for automatic meter reading. PLS can be a component
of Smart Grid.
Pressure Sensor: is a device for pressure measurement of gases or liquids; the
measured values are converted to electronic singles to output. Various types of
pressure sensor are available: barometric pressure sensor, differential pressure
sensor, absolute pressure sensor, static (a differential) pressure sensor and
dynamic pressure sensor, etc.
Process: in semiconductor industry, it implies the implementation process of IC
manufacturing.
Process Design Kit (PDK): is a set of documentary files used in IC design, such that
the flow and process methods can be simplified. PDK files include device library
information, verification file, technology file, rule decks, simulation models,
design rule manuals, etc.

Q to T
Quantum-Dot Light-Emitting Diode (QLED or QD-LED): is a LED that is based
on quantum-dot. There are two types of such LED in TVs display: one is QLED
that uses photo-emissive particles; the other is electro-emissive QD-LED TVs
which exist in laboratories stage.
2006 Appendix D: Common Glossaries of IC Industry

Radar: is a detection system that uses radio waves, typically wavelength of about
10 cm and frequency of about 3 GHz, to determine the range, angle, altitude, or
velocity of objects, for a distance up to 104 km.
Radio-Frequency Identification (RFID): an RFID tag is consisted of a tiny radio
transponder; a radio receiver and transmitter. Radio waves are used to read and
capture information stored on a tag attached to an object, and the tags can be
active (with battery) and passive (without battery).
Rectifier Diode: is a two-lead semiconductor device used to rectify AC into DC; the
diode is made of p-type (anode) and n-type (cathode) materials forming a p-n
junction.
Reduced Instruction Set Computer (RISC): the features of RISC are having the
same format of the instructions, same instruction cycle, using pipelined tech-
nique. The number of instructions and addressing method are both simplified for
easier realization, such that the instructions are better executed, and the efficiency
of compiler is high.
Register-Transfer Level (RTL): the principle abstraction used for defining elec-
tronic systems today, RTL is an abstraction for defining the digital portions of a
design and mostly characterize a system definition in terms of registers, multi-
plexors, and operations.
Resistance Sensor: is used to measure the resistance across a resistive load and
convert readings into resistance readings in ohm (Ω).
Resolution Enhancement Technology (RET): is a semiconductor manufacturing
method used to modify photomasks for integrated circuits (ICs) to compensate for
limitations in the lithographic processes.
Routing: used in PCB or IC design flow, with the help of EDA tools, the routing
process routes/connects electrically all devices and components following the
logic.
Schottky Diode: named after German physicist W. H. Schottky, it is a metal-
semiconductor diode with a low forward voltage drop and a very fast switching
speed.
Secure Cryptoprocessor: a processor that generates a crypto Key, not crypto data or
programing instructions.
Sensor: is a device that produces an output signal for the purpose of sensing a
physical phenomenon, e.g., an electronic signal, for various applications of
transmission, process, storage, display, recording, control, etc.
Separation by Implantation of Oxygen (SIMOX): a technology developed for
fabricating SOI-type devices. By implanting a high-dose of oxygen ions into
silicon, then through annealing after a super-high temperature, three layers are
formed, i.e., silicon layer, SiO2 isolation layer, and bulk silicon layer.
Shortwave Radio (SW): a radio wave for broadcasting, it has wavelengths of 100 m
to 10 m, frequencies of 3–30 MHz.
Silicon on Insulator (SOI): is a semiconductor structure consisting of a layer of
single crystalline silicon separated from the bulk substrate by a thin layer of SiO2
insulator.
System on Chip (SoC): also called System on a Chip, which integrates processor,
memories, and IP blocks on a single die/chip to perform system functions.
Appendix D: Common Glossaries of IC Industry 2007

Specialty Gases: represent gases which are rare or ultra-high purity (99.995% and
above). In semiconductor industry, when thin layers of different materials are
added to the surface of the silicon wafer, chemical reactions during deposition
(additive) and etching (subtractive) occur, which require various reactive gases
such as nitrogen trifluoride (NF3), tungsten hexafluoride (WF6), germane
(GeH4), and nitrous oxide (N2O).
Standard Definition Television (SDTV, SD): or simply called standard definition, is
a television system which has two video signal types of NTSC 480i and PAL
576i; two types of display aspect ratio (DAR) of 4:3 and 16:9; and several types
of resolution, e.g., 720  480 pixels and 720  576 pixels. SDTV and high-
definition television (HDTV) are the two categories of display formats for digital
television (DTV) transmissions.
Synthesis: is an automated transformation of high-level RTL codes (behavioral
description) to gate-level netlist (structural description) in IC design.
System in Package (SiP): is a technology to integrate two or more chips into one
package.
SystemVerilog: written as one word, it has been defined as IEEE 1800-2009
standard in 2005, a HDL used in both HW (IC) design and its verification.
Tensor Processing Unit (TPU): is an ASIC design especially for neural network
machine learning by Google in 2016; as well as TPU v2.0 in 2017 and TPU v3.0
in 2018.
Terahertz (THz) Waves: are the electromagnetic waves having frequencies or
0.1–10 THz, and wavelengths of 0.03–3 mm.
Thin-Film Transistor (TFT): is a special type of MOSFET and usually used in LCD
as active matrix display device. TFT LCDs are widely used in television sets,
computer monitors, mobile phones, etc.
Through-Silicon Via (TSV): a technology used in 3D packaging for compact size
and fast timing, it is a vertical interconnection for passing a silicon wafer and
chips.

U to W
Ultrapure Water (UPW): used in the study of ultrapure materials (semiconductor
materials, nano-ceramic materials). UPW that produced through distillation,
de-ionization, reverse osmosis, and supercritical fluid (SCF), with resistivity
greater than 18 MΩ cm or close to 18.3 MΩ cm (limit at 25  C), is often used
in manufacturing process for cleaning the contaminations on IC.
Universal Serial Bus (USB): a general name of interface protocol which uses serial
format to transmit digital signals in the bit order.
Uninterruptible Power Supply/Source (UPS): is an electrical apparatus that pro-
vides emergency power through its batteries to a load when the input power
source or mains power is out of order.
Unmanned Aerial Vehicle (UAV): also commonly known as drone, is an aircraft
without a pilot, rather piloted by remote control or onboard computers.
Verification IP (VIP): is a method or scheme providing IP verifications for protocol,
interface, and memory used in SoC design.
2008 Appendix D: Common Glossaries of IC Industry

Video Codec: is a circuit or software used to compress and/or de-compress digital

video signals.
Virtual Reality (VR): a technology for user to experience virtually inside a 3D
computer generated environment of interchangeable visual simulation; VR is
used in entrainment (e.g., video games) and educational purposes (medical and
military trainings).
Wafer: in electronics, a wafer is a thin slice of semiconductor, used for the fabrica-
tion of ICs and, in photovoltaics, to manufacture solar cells. The wafer serves as
the substrate for microelectronic devices built in and upon.
White Goods: are household appliances built for easy labor intensity or substitute
house work and improve people’s living quality.
Wireless Fidelity (Wi-Fi): an IEEE 802.11b standard, Wi-Fi is the most widely used
wireless LAN today.

X to Z
X-Ray: an electromagnetic radiation produced in a vacuum tube through the bom-
bardment of high-speed electrons on the target atoms. X-rays have wavelengths
of 0.01–10 nm, shorter than visible lights. X-ray is also known as Roentgen rays,
which was discovered in 1895 by Röentgen.
Yield: a quantity defined in product process, i.e., the ratio the quantity of QA passed
products to the total quantity of materials used in the products.
ZigBee: an IEEE 802.15.4 standard, ZigBee is used in short distance, low power
LAN protocol.

Data collection and compilation: Chun-Zhang Chen