By: Dr.

Ajit Jain
Contents
 Modes of Transfer
 Programmed I/O
 Interrupt-Initiated I/O
 Direct Memory Access (DMA)
Modes of Transfer
 Memory unit is the origin of data transfer
between central computer and I/O devices.
 The CPU merely executes the I/O
instructions and may accept the data
temporarily, but the ultimate source or
destination is the memory unit.
Modes of Transfer
 Data transfer between the central computer and I/O
devices may be handled in a variety of modes.
 Some modes use the CPU as an intermediate path;
others transfer the data directly to and from the
memory unit.
 Data transfer to and from peripherals may be handled
in one of three possible modes:
1. Programmed I/O
2. Interrupt-Initiated I/O
3. Direct Memory Access (DMA)
1. Programmed I/O
 Data transfer between CPU and the I/O devices
is initiated by an instruction in the program.
 Requires continuous monitoring of
peripheral by the CPU.
 I/O device does not have direct access to
memory.
Programmed I/O Example…
Data transfer from I/O device to CPU
Programmed I/O Example…
 The device transfers bytes of data one at a time as they are available.
 Steps:
1. When a byte of data is available, the device places it in the I/O bus and
enables its data valid line.
2. The interface accepts the byte into its data register and enables the data
accepted line.
3. A program at the CPU checks the Flag bit:
a) If it is 1 then
 CPU reads the data from the interface’s data register
 flag bit is cleared to 0
 the interface disables the data valid line
 the interface disables the data accepted line (ready for next byte)
b) If F is not 1 means data has not been completely placed into the data
register
4. After reading the byte into a CPU register, it is transferred to memory.
Programmed I/O…
 Limitation
 Not an efficient method.
Why?
 This method requires constant monitoring of peripheral
by the CPU (for checking the value of flag bit). This job
of monitoring wastes the CPU time which may be used
in some other useful processing task.
2. Interrupt-Initiated I/O
 An alternative to the CPU constantly
monitoring the flag is to let the interface
inform the computer when it is ready to
transfer data.
 This mode of transfer uses the interrupt
facility.
While the device is getting ready for
transferring of data, the CPU is able to do
something else. CPU is not getting tied-up.
2. Interrupt-Initiated I/O…
CPU is doing some other task

Whenever the I/O device is ready to transfer the data

I/O device will interrupt the CPU by sending the Interrupt Request
Signal (IRS)

When the CPU receives IRS, it come to know that the some I/O device is
ready to transfer the data

CPU will be jumping or branching to IRS routine where the data transfer
will take place

After it, CPU will return back to the program, which it was executing
previously
3. Direct Memory Access (DMA)
 Data transfer between I/O device and memory unit is
done without involving the CPU.
 Application:
 Some fast I/O device like magnetic disk generate a bulk
of data for transfer.
 In such a case the data transfer is limited by the speed of
CPU.
 Removing the CPU from the path and letting the
peripheral device manage the buses directly would
improve the speed of data transfer.
Direct Memory Access (DMA)…
 During DMA transfer, the CPU is idle and has no
control of the memory buses. A DMA controller
(DMAC) takes over the buses to manage the transfer
directly between the I/O device and memory.
 Special control signals are used to place the CPU in
idle state.
Direct Memory Access (DMA)…
• Bus Request (BR):
used by the DMA
controller to request
the CPU to
High- relinquish control
impedance of the buses.
CPU (disable)
• Bus Grant (BR):
when BG is
Enabled
CPU activates the
BG output to inform
the DMA that the
buses are in high-
CPU bus signals for DMA transfer impedance state
Direct Memory Access (DMA)…
 When the BG activates; the DMA, now, takes
control of the buses to conduct data transfer
without processor intervention.
 When the DMA terminate the data transfer, it
disables the BR line. The CPU disables the BG,
takes control of the buses, and returns to its
normal operation.
DMA Controller

Block Diagram of DMAC

DMA Controller
 Address Register
 The starting location in the memory to read from or
write to memory.
 Word Count Register:
 The size of the block. It keeps the count of words to be
read from or written to memory.
 Address Register:
 The address register is incremented after each word that
is transferred to memory.
 Control Register:
 Specifies the mode of transfer such as read or write.
Direct Memory Access (DMA)
 When the DMA take control of the bus system, it
communicates directly with the memory.
 The transfer of data is made as a block of data consisting of
a number of memory words. These blocks are transferred
one by one in a continuous manner when the DMA
controller is the master of buses.

Start Address

Block
Direct Memory Access (DMA)
 Two aspects in DMA:
1. Initialization of DMAC chip or chip
configuration phase
2. Data Transfer
DMAC Chip Initialization
 Before the actual transfer of data starts, the CPU initializes
the DMAC by:
1. Address Register: by the starting address of the memory
block where data are available (for read) or where data are
to be stored (for write).
2. Word Count Register: by the size of the memory block.
3. Control Register: by mode of transfer such as read or
write.
 Once the DMA Controller is initialized, the CPU stops
communicating with the DMA unless it receives an
interrupt signal or if it wants to check how many words
have been transferred.
 Data Transfer
1. The I/O device request for DMA.
2. The CPU initializes the DMAC chip (i.e. address, word-count, and control
registers).
3. DMA controller activates the BR line, informing the CPU to relinquish the
buses.
4. The CPU responds with its BG line, informing the DMA that its buses are
disabled.
5. DMA puts the current value of its address register into the address bus,
initiates RD or WR signal and sends a DMA acknowledge to the I/O device.
6. When I/O device receives a DMA acknowledge, it puts a word in the data
bus (for write) or receives a word from the data bus (for read).
7. For each word that is transferred, the DMA increments its address register
and decrements its word count register.
8. If the word count does not reach to 0, a second transfer is then initiated,
and the process continues until the entire block is transferred.
Direct Memory Access (DMA)
 Applications:
 DMA transfer is used for fast transformation of
information between magnetic disks and memory.
 It is also useful for displaying an image in an interactive
terminal by transferring the contents of the memory to
the screen periodically by means of the DMA transfer.
Thanks