E3 237 Integrated Circuits for Wireless

Communication

Lecture 4: Analog/RF CMOS Layout

Gaurab Banerjee
Department of Electrical Communication Engineering,
Indian Institute of Science, Bangalore
banerjee@iisc.ac.in
 Basic Layout Design Considerations

“Analog Integrated Circuit Design”, Carusone, Johns and Martin, Wiley

• All design rules written in terms of λ, smallest device has channel length = 2 λ
• Mask alignment is error prone -> worst case alignment is 0.75 λ
• Ιf the design rules are violated, catastrophic shorts can result.
• DRC is a part of standard design flow, many CAD flows “auto generate” transistor
layout from schematic -> no scope for DRC violations at transistor level.
 Modern CMOS - Special Requirements
Antenna charging effects

Well proximity effects (WPE) Shallow Trench Isolation (STI) Stress

• Planarity: Optics requires planarity -> special local and global “fill” requirements -> density
checks now standard like LVS/DRC.
• Unintended impact of dummies on analog: matching, inductor Q, increased parasitics.
• Antenna charging : Connect diodes to prevent oxide damage during fabrication.
• WPE: Extra dopants due to scattering near well edge -> threshold voltage shifts -> minimize
proximity to well edges
• STI stress: Affects mobility -> orient all devices the same way and use dummy devices
 Basic Transistor Layout

“Analog Integrated Circuit Design”, Carusone, Johns and Martin, Wiley

• Break up a large device into smaller “fingers”.

• Internal node (node 1) has lower capacitance than “perimeter” node (n2). Connect
n1 to bandwidth critical nets.
 Common-Centroid Layout

• Symmetric in X and Y directions -> robust to gradients, offsets.

• 4 fingers share 2 drain junctions -> less capacitance per node
• Drain and gate routed from opposite sides, less Miller capacitance
• Dummy fingers used to minimize peripheral effects, guard ring for isolation
• Multi-finger layout minimizes gate resistance -> important to make double sided
gate contacts for RF transistors!
 Capacitor Layout

• Common problem in capacitors: over-etching -> make a much smaller unit cell and
use multiples of the cell to implement large capacitors.
• Connect bottom plates together, locate over a well for shielding.
• Put “lid” on top of top plate for isolation
• Ensure uniform boundary conditions -> use dummies if needed.
 Matched Resistor Layout

• Block salicide in active region for resistor

• Maximize vias/contacts when connecting to the resistor
• Keep interconnect metal wide to minimize its impact on resistance
• Use dummy fingers to isolate edge effects
• About 0.1% mismatch possible with careful layout on salicide blocked poly-Si.
 Inductor Layout
Patterned Ground Shield

C.P.Yue, Stanford University

• 45% bends in the edges can improve performance slightly

• Symmetry ensured by layout, choice of crossovers
• Maximize the number of vias to preserve Q, PSG on poly might help in some cases
Next Class: RLC Networks