E3 237 Integrated Circuits for Wireless

Communication

Lecture 3: Advanced RF CMOS

Gaurab Banerjee
Department of Electrical Communication Engineering,
Indian Institute of Science, Bangalore
banerjee@iisc.ac.in
 Outline

• 0.13 um RF CMOS Components

• An advanced RF-CMOS process
 Resistors: Based on Diffusion

N-well resistance (about 400

Ohms/sq)

Diffusion resistance (about 10 Ohms/sq, salicided. 100-200

Ohms/sq, un-salicided)

• N-well and diffusion based resistors are characterized by large parasitics

• Salicide lowers resistance, good for MOS devices, bad for resistors
• Salicide blocking is expensive, some processes still do it for specialized poly-resistors.
 Resistors: Based on poly-silicon

N+/P+ poly - sheet resistance (about 10 Ohms/sq)

Salicide-blocked poly resistance (about 200 Ohms/sq)

• Low parasitic capacitance, better than diffusion based resistors

• Some processes customize the poly sheet resistance with salicide blocking – very expensive!
• Interconnect resistance ( about 100 mOhm/square) and vias can add series resistance
 Resistors: Based on MOS Device

• Device biased in triode –> bias dependent resistor –> nonlinear and PVT
variation sensitive
• Large Parasitic capacitance
• Large resistance – mega-ohms in tens of square microns
 Resistors: Equivalent Circuit Model

• Series inductor at high frequencies – meander to reduce impact

• Parasitic capacitance to substrate with dielectric losses
 MOS Capacitor

• Offers the highest capacitance per unit area – 10 fF/ sq. micron
• Channel length adds series resistance – needs to be minimized for high Q
• Can be used as a varactor in tuning circuits -> careful, not linear!
• Requires device to be kept in strong inversion
• Varactors use the MOS capacitor in accumulation mode – n+ diffusion in n well, to
avoid keeping the device in strong inversion. This makes the CV characteristics
monotonic (only depletion and accumulation possible).
• A smaller channel length has better Q (low resistance) but has lower tuning range due
to overlap caps making up a larger fraction of the total capacitance.
• The modelling of MOS varactors is very challenging. The Q-factor is dependent on the
n-well resistance that is hard to model.
 Metal Capacitors

Lateral Flux Capacitor Stacked and Inter-digitated

Metal-Insulator-Metal (MIM) capacitor is Metal-Oxide-Metal (MOM) capacitor is

like this with special dielectric layer like this with whatever insulator is
(usually on top of BEOL stack) available in BEOL stack

Aparacio et al, “Capacity limits and Matching Properties of integrated capacitors ”, JSSC, March 2002

• MOM capacitance per unit area – 1.5-2 fF/ sq. micron

• High Q and very linear.
• Symmetric parasitic capacitance – about 10% of total capacitance
• Accuracy determined by lithography – usually better than 10%
• Use arrayed unit cells to improve matching.
 Capacitors: Equivalent Circuit Model

• “Lead” inductance and resistance

• Parasitic capacitance to substrate with dielectric losses – sometimes
known as “cap-to-ground” or “bottom plate capacitance”.
 Integrated Spiral Inductors

1-turn with underpass

multi-turn, multi-crossover, with center-tap

• Generally uses top metal layer, with or without patterned ground shield
• Typically considered parameters (L=1-10 nH, Q = 5-10, self resonance frequency = 10-30 GHz )
• Width, length and area over substrate typically determine losses
• “Hollow” inductors typically provide better Q for same L – avoid inner turns
• Several closed form expressions exist –> Start with L = µ0 n2 r, refine with field solvers
• Usually rounded inductors are slightly more efficient –> does not make a huge difference!
 Inductors: Equivalent Circuit Model

• Series resistance representing metal losses (skin effect) and eddy current losses
(substrate)
• Parasitic capacitance to substrate with dielectric losses
• Turn to turn and cross-over capacitance – lowers self-resonance frequency
 Bond-wire Inductors

• Generally 1nH/mm (achieves 1-5 nH)

• Not well controlled, parasitic dominated
• Q much better than integrated inductors -> around 40
• Every instantiation requires a bond-pad: difficult for “internal” inductors
 Integrated Transformers

• Utilizes magnetic coupling between adjacent metal layers.

• Key Parameters : L, M=Mutual inductance.
• Typically very lossy, requires tight coupling between primary and secondary.
• Almost always requires EM field-solver for model extraction.
• Studies have shown that “stacked” transformers are more efficient than “planar” transformers.
 Outline

• 0.13 um RF CMOS Components

• An advanced RF-CMOS process
 Intel’s 32-nm CMOS for RF

C. H. Jan et al. “RF CMOS Technology Scaling in High-k/Metal Gate Era for RF SoC (System-on-Chip)
Applications”, Int. Electron Dev. Meeting, Dec. 2010

• Performance improvement in modern CMOS processes is not driven by geometrical

scaling anymore.
• Advances in materials (strained silicon, high-k gate dielectric, metal gate) are now
enabling high fTs, lower noise figures and better figures of merit for RFICs.
 fT Scaling Trends to 32-nm

• Steady improvement in peak fT over the last few generations -> major jump from 90
to 65-nm technology.
• Strong function of current density -> Burn more current if you need high fT.
 Flicker Noise Performance

• 10x reduction in flicker noise from 180 nm to 32 nm technology.

• Primarily due to increase in gate capacitance, aided by improvements in dielectric
materials.
• Better growth/deposition techniques for advanced processes may have a role to
play.
 Minimum Noise Figure Performance

• Steady improvement in NFmin over technology generations.

• Trend reversal (?) between 45-nm and 32-nm technologies?
• Generally a tradeoff between improving gm (materials) and parasitics (limitations in
fabrication).
 Interconnect Scaling

• Primarily driven by the performance and density requirements of digital processes.

• Generally, has a negative impact due to interconnect parasitics.
• In older processes, top metals were deliberately kept thicker for power distribution
and RF inductors -> This is getting limited by interconnect scaling.
 Thick Metal in Advanced Processes

• One possible solution -> Add a thick metal layer at the top.
• “Redistribution layer” offered by many foundries for RF/Analog.
Key RF Device Characteristics
Next Class: Analog/RF Layout