PORTS SERVE AS 8-BIT BI-DIRECTIONAL I/O PORTS

PORT PINS CAN PROVIDE INTERNAL PULL-UP RESISTORS.

THE PORT OUTPUT BUFFERS HAVE SYMMETRICAL DRIVE CHARACTERISTICS

WITH BOTH HIGH SINK AND SOURCE CAPABILITY.

WHEN PINS ARE USED AS INPUTS AND ARE EXTERNALLY PULLED LOW, THEY
WILL SOURCE CURRENT IF THE INTERNAL PULL-UP RESISTORS ARE

ACTIVATED.

THE PORT PINS ARE TRI-STATED WHEN A RESET CONDITION

BECOMES ACTIVE, EVEN IF THE CLOCK IS NOT RUNNING.
EACH PORT PIN CONSISTS OF THREE REGISTER BITS:
DDXN, PORTXN, AND PINXN.
THE DDXN BIT IN THE DDRX REGISTER SELECTS DIRECTION OF PIN.
IF DDXN IS WRITTEN LOGIC ONE, PXN IS CONFIGURED AS AN OUTPUT PIN.
IF DDXN IS WRITTEN LOGIC ZERO, PXN IS CONFIGURED AS AN INPUT PIN.
IF PORTXN IS WRITTEN LOGIC ONE WHEN THE PIN IS CONFIGURED AS

AN INPUT PIN, THE PULL-UP RESISTOR IS ACTIVATED.

TO SWITCH THE PULL-UP RESISTOR OFF, PORTXN HAS TO BE WRITTEN

LOGIC ZERO OR THE PIN HAS TO BE CONFIGURED AS AN OUTPUT PIN.

PORT A ALSO SERVES AS THE ANALOGUE INPUTS TO THE ANALOGUE TO
DIGITAL CONVERTER
THE ADC IS CONNECTED TO AN 8-CHANNEL ANALOG MULTIPLEXER WHICH

ALLOWS 8 SINGLE-ENDED VOLTAGE INPUTS CONSTRUCTED FROM THE PINS OF

PORT A.
THE SINGLE-ENDED VOLTAGE INPUTS REFER TO 0V (GND)
S EVEN DIFFERENTIAL ANALOG INPUT CHANNELS SHARE A COMMON
NEGATIVE TERMINAL (ADC1), WHILE ANY OTHER ADC INPUT CAN
BE SELECTED AS POSITIVE INPUT TERMINAL
T HE ADC CONTAINS A SAMPLE AND H OLD CIRCUIT WHICH
ENSURES THAT THE INPUT VOLTAGE TO THE ADC IS HELD AT A
CONSTANT LEVEL DURING CONVERSION .
AVCC
AVCC IS THE SUPPLY VOLTAGE PIN FOR P ORT A AND A/D C ONVERTER .
AREF
AREF IS THE ANALOG REFERENCE PIN FOR THE A/D C ONVERTER .
PORT B ALSO SERVES THE FUNCTIONS OF VARIOUS SPECIAL
FEATURES OF THE ATMEGA32.
THE SYSTEM CONSISTS OF TWO SHIFT REGISTERS, AND A MASTER CLOCK GENERATOR.
THE SPI MASTER INITIATES THE COMMUNICATION CYCLE WHEN PULLING LOW THE
SLAVE SELECT SS PIN OF THE DESIRED SLAVE.
MASTER AND SLAVE PREPARE THE DATA TO BE SENT IN THEIR RESPECTIVE SHIFT
REGISTERS, AND THE MASTER GENERATES THE REQUIRED CLOCK PULSES ON THE SCK.
DATA IS ALWAYS SHIFTED FROM MASTER TO SLAVE ON MOSI, AND FROM SLAVE TO
MASTER ON MISO.
AFTER EACH DATA PACKET, THE MASTER WILL SYNCHRONIZE THE SLAVE BY PULLING
HIGH THE SS LINE.
THE ANALOG COMPARATOR COMPARES THE INPUT VALUES ON THE
POSITIVE PIN AIN0 AND NEGATIVE PIN AIN1.

WHEN THE VOLTAGE ON THE POSITIVE PIN AIN0 IS HIGHER THAN

THE VOLTAGE ON THE NEGATIVE PIN AIN1, THE ANALOG
COMPARATOR OUTPUT, ACO, IS SET
THE PB3 PIN CAN SERVE AS AN EXTERNAL OUTPUT FOR THE
TIMER/COUNTER0 COMPARE MATCH.
THE PB3 PIN HAS TO BE CONFIGURED AS OUTPUT (DDB3 SET 1)
TO SERVE THIS FUNCTION.

THE OC0 PIN IS ALSO THE OUTPUT PIN FOR THE PWM MODE
TIMER FUNCTION
THE PB2 PIN CAN SERVE AS AN EXTERNAL INTERRUPT SOURCE TO
THE MCU
THE PB1 PIN CAN SERVE AS TIMER/COUNTER1 COUNTER SOURCE.

THE PB0 PIN CAN SERVE AS TIMER/COUNTER0 COUNTER SOURCE.

THE PB0 PIN CAN ALSO SERVE AS USART EXTERNAL CLOCK.

THE PB0 (XCK) PIN IS ACTIVE ONLY WHEN THE USART OPERATES IN

SYNCHRONOUS MODE.
PORT C ALSO SERVES THE FUNCTIONS OF VARIOUS SPECIAL
FEATURES OF THE ATMEGA32.
THE TIMER/COUNTER CAN BE CLOCKED BY AN INTERNAL
SYNCHRONOUS OR AN EXTERNAL ASYNCHRONOUS CLOCK SOURCE

THE CLOCK SOURCE IS TAKEN FROM THE TIMER/COUNTER OSCILLATOR

CONNECTED TO TOSC1 AND TOSC2
THE AVR IEEE STD. 1149.1 COMPLIANT JTAG INTERFACE
TESTING PCBS BY USING THE JTAG BOUNDARY-SCAN CAPABILITY
PROGRAMMING THE NON-VOLATILE MEMORIES, FUSES AND LOCK BITS
ON-CHIP DEBUGGING
THE JTAG INTERFACE IS ACCESSED THROUGH FOUR OF THE AVR’S PINS.
TEST MODE SELECT: THIS PIN IS USED FOR NAVIGATING THROUGH THE TAP-
CONTROLLER STATE MACHINE.
TEST CLOCK: JTAG OPERATION IS SYNCHRONOUS TO TCK.
TEST DATA IN: SERIAL INPUT DATA TO BE SHIFTED IN TO THE INSTRUCTION
REGISTER OR DATA REGISTER.
TEST DATA OUT: SERIAL OUTPUT DATA FROM INSTRUCTION REGISTER OR DATA
REGISTER.
THE 2 TWO-WIRE INTERFACE PINS SCL AND SDA HAVE ONE
ADDITIONAL CONTROL SIGNAL IN THE SCAN CHAIN.
SCL: CLOCK SIGNAL.
SDA: DATA INPUT/OUTPUT LINE
PORT D ALSO SERVES THE FUNCTIONS OF VARIOUS SPECIAL
FEATURES OF THE ATMEGA32.
OC2:
T IMER /C OUNTER 2 O UTPUT C OMPARE M ATCH OUTPUT
T HE OC2 PIN IS OUTPUT PIN FOR PWM MODE TIMER FUNCTION
ICP1:
I NPUT C APTURE P IN :
I T CAN ACT AS AN I NPUT C APTURE PIN FOR T IMER /C OUNTER 1
OC1 X :
T HESE PINS ARE OUTPUT PINS FOR PWM MODE TIMER FUNCTION
INT X :
E XTERNAL I NTERRUPT S OURCES
R X D & T X D:
R ECEIVE AND T RANSMIT DATA P INS FOR USART
RESET’
RESET INPUT:
A LOW LEVEL ON THIS PIN FOR LONGER THAN THE MINIMUM PULSE

LENGTH WILL GENERATE A RESET, EVEN IF THE CLOCK IS NOT RUNNING.

XTAL1
INPUT TO THE INVERTING OSCILLATOR AMPLIFIER AND INPUT TO THE

INTERNAL CLOCK OPERATING CIRCUIT.

XTAL2
OUTPUT FROM THE INVERTING OSCILLATOR AMPLIFIER.
THE ATMEGA32 CONTAINS 32
KBYTES ON-CHIP IN-SYSTEM
REPROGRAMMABLE FLASH
MEMORY FOR PROGRAM STORAGE.
SINCE ALL AVR INSTRUCTIONS ARE
16 BITS WIDE, THE FLASH IS
ORGANIZED AS 16K × 16.
FOR SOFTWARE SECURITY, THE
FLASH PROGRAM MEMORY SPACE
IS DIVIDED INTO TWO SECTIONS
BOOT PROGRAM SECTION
APPLICATION PROGRAM SECTION.
THE PROGRAM COUNTER IS USED BY THE CPU TO POINT TO THE
ADDRESS OF THE NEXT INSTRUCTION TO BE EXECUTED.

AS THE CPU FETCHES THE OPCODE FROM THE PROGRAM ROM, THE
PROGRAM COUNTER IS INCREMENTED AUTOMATICALLY TO POINT TO THE
NEXT INSTRUCTION.

THE WIDER THE PROGRAM COUNTER, THE MORE MEMORY LOCATIONS A

CPU CAN ACCESS.
THAT MEANS THAT A 14-BIT PROGRAM COUNTER CAN ACCESS A
MAXIMUM OF 16K (214 = 16K) PROGRAM MEMORY LOCATIONS.
IN NORMAL OPERATING MODE, WHENEVER THE PROCESSOR IS
POWERED ON OR RECEIVES A RESET SIGNAL IT IMMEDIATELY
PERFORMS A SEQUENCE OF THE FETCH–EXECUTE CYCLE.
ONE OF THOSE TASKS IS TO LOAD A ZERO INTO THE PC.
IF YOU PROVIDE A RESET SIGNAL TO THE PROCESSOR, YOU CAN
GUARANTEE THAT IT WILL FETCH AND EXECUTE THE INSTRUCTION
AT ADDRESS ZERO.
THUS, WE SHOULD PLACE OUR PROGRAM’S FIRST INSTRUCTION AT
ADDRESS ZERO OF PROGRAM MEMORY.
UPON FETCHING ANY INSTRUCTION, THE PC IS INCREMENTED.
THUS OUR SECOND INSTRUCTION SHOULD BE LOCATED AT NEXT
ADDRESS.
THE WIDENING OF THE DATA PATH BETWEEN THE PROGRAM ROM
AND THE CPU IS ANOTHER WAY IN WHICH THE AVR DESIGNERS
INCREASED THE PROCESSING POWER OF THE AVR FAMILY.
ANOTHER REASON TO MAKE THE CODE ROM 16 BITS WIDE IS TO
MATCH IT WITH THE INSTRUCTION WIDTH OF THE AVR BECAUSE
THE VAST MAJORITY OF THE INSTRUCTIONS ARE 2-BYTE
INSTRUCTIONS.
THIS WAY, THE CPU BRINGS IN AN INSTRUCTION FROM ROM EVERY TIME
IT MAKES A TRIP TO THE PROGRAM ROM.
MAKE INSTRUCTION FETCH A SINGLE CYCLE
THE AVR DESIGNERS HAVE MADE ALL INSTRUCTIONS EITHER 2-
BYTE OR 4-BYTE; THERE ARE NO 1-BYTE OR 3-BYTE INSTRUCTIONS
 EACH INSTRUCTION REQUIRES TWO CLOCK CYCLES TO BE EXECUTED
ONE TO FETCH IT, THE NEXT TO DECODE AND EXECUTE.
THE TWO-STAGE PIPELINE OVERLAPS THE FETCH AND EXECUTE OF
ADJACENT INSTRUCTIONS ALLOWING AN INSTRUCTION TO BE EXECUTED
DURING EACH CLOCK CYCLE.

Monday, August 17, 2015 2151001: Microcontroller& Interfacing 28

REGISTER ↔ REGISTER IN 1 CYCLE
REGISTER ↔ MEMORY IN 2 CYCLES
BRANCH INSTRUCTION 1-2 CYCLES
SUBROUTINE CALL & RETURN 3-5 CYCLES
IN A SINGLE CLOCK CYCLE AN ALU OPERATION USING TWO
REGISTER OPERANDS IS EXECUTED, AND THE RESULT IS STORED BACK

TO THE DESTINATION REGISTER.

I N AVR THERE ARE 32 GENERAL PURPOSE REGISTERS
T HEY ARE R0-R31 AND ARE LOCATED IN THE LOWEST LOCATIONS OF

MEMORY ADDRESSES (0 X 00 TO 0 X 1F).

T HE GENERAL PURPOSE REGISTERS IN AVR ARE THE SAME AS

THE ACCUMULATOR IN OTHER MICROPROCESSORS .

T HEY CAN BE USED BY ALL ARITHMETIC AND LOGIC INSTRUCTIONS .

T HE STATUS R EGISTER CONTAINS INFORMATION ABOUT THE

RESULT OF THE MOST RECENTLY EXECUTED ARITHMETIC

INSTRUCTION .

T HIS INFORMATION CAN BE USED FOR ALTERING PROGRAM FLOW IN

ORDER TO PERFORM CONDITIONAL OPERATIONS .

T HE S TATUS R EGISTER IS UPDATED AFTER ALL ALU OPERATIONS.

I T H S V N Z C
C: C ARRY F LAG
T HE C ARRY F LAG C INDICATES A CARRY IN AN ARITHMETIC OR LOGIC
OPERATION .

Z: Z ERO F LAG
T HE Z ERO F LAG Z INDICATES A ZERO RESULT IN AN ARITHMETIC OR
LOGIC OPERATION .

N: N EGATIVE F LAG
T HE N EGATIVE F LAG N INDICATES A NEGATIVE RESULT IN AN
ARITHMETIC OR LOGIC OPERATION .
I T H S V N Z C
V: T WO ’ S COMPLEMENT OVERFLOW F LAG
T HE T WO ’ S C OMPLEMENT OVERFLOW F LAG V SUPPORTS TWO ’ S
COMPLEMENT ARITHMETIC .
I T IS 2’ S COMPLEMENT OVERFLOW INDICATOR .
S: S IGN B IT (S = N ⊕ V)
T HE S- BIT IS ALWAYS AN EXCLUSIVE OR BETWEEN THE N EGATIVE
F LAG N AND THE T WO ’ S C OMPLEMENT OVERFLOW F LAG V.
H: H ALF C ARRY F LAG
T HE H ALF C ARRY F LAG H INDICATES A HALF CARRY IN SOME
ARITHMETIC OPERATIONS .
H ALF C ARRY IS USEFUL IN BCD ARITHMETIC .
I T H S V N Z C

T: B IT COPY STORAGE
A BIT FROM A REGISTER IN THE R EGISTER F ILE CAN BE COPIED INTO
T, AND A BIT IN T CAN BE COPIED INTO A BIT IN A REGISTER IN THE
R EGISTER F ILE BY THE
I: G LOBAL I NTERRUPT E NABLE
T HE G LOBAL I NTERRUPT E NABLE BIT MUST BE SET FOR THE
INTERRUPTS TO BE ENABLED. T HE INDIVIDUAL INTERRUPT ENABLE
CONTROL IS THEN PERFORMED IN SEPARATE CONTROL REGISTERS .
I F THE G LOBAL I NTERRUPT E NABLE R EGISTER IS CLEARED, NONE OF
THE INTERRUPTS ARE ENABLED INDEPENDENT OF THE INDIVIDUAL
INTERRUPT ENABLE SETTINGS .
T HE I/0 MEMORY IS DEDICATED TO SPECIFIC FUNCTIONS :
STATUS REGISTER ,
TIMERS ,
SERIAL COMMUNICATION ,
I/0 PORTS ,
ADC, AND SO ON .
T HE FUNCTION OFEACH I/0 MEMORY LOCATION IS FIXED BY THE
CPU DESIGNER AT THE TIME OF DESIGN BECAUSE IT IS USED FOR
CONTROL OF THE MICROCONTROLLER OR PERIPHERALS .
T HE AVR I/0 MEMORY IS MADE OF 8- BIT REGISTERS .
T HE NUMBER OF LOCATIONS IN THE DATA MEMORY SET ASIDE FOR
I/0 MEMORY DEPENDS ON THE PIN NUMBERS AND PERIPHERAL
FUNCTIONS SUPPORTED BY
T HE INTERNAL DATA SRAM ACCESS IS PERFORMED IN TWO
CLOCK CYCLES
THE ATMEGA32 CONTAINS 1024 BYTES OF DATA EEPROM
MEMORY.
IT IS ORGANIZED AS A SEPARATE DATA SPACE, IN WHICH SINGLE
BYTES CAN BE READ AND WRITTEN.
THE EEPROM HAS AN ENDURANCE OF AT LEAST 100,000 WRITE/ERASE
CYCLES.
THE ACCESS BETWEEN THE EEPROM AND THE CPU IS THROUGH SFR IN
I/O SPACE.
THE EEPROM ADDRESS REGISTERS,
THE EEPROM DATA REGISTER,
THE EEPROM CONTROL REGISTER.