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CSC405 Microprocessor
 8086 Microprocessor
Modes of Operation

Microprocessor rithesh.kini@thadomal.org
 8086 – Pin Diagram
 8086 operates in 2 modes:
i. Minimum Mode
ii. Maximum Mode
 The minimum mode is used for a small system with a
single processor

 The maximum mode is for medium size to large

systems with 2 or more processors.

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Microprocessor rithesh.kini@thadomal.org
 8086 – Functional Pin Diagram
VCC AD15 – AD0

GND AD16/ S3
GND AD17/ S4
AD18/ S5
CLK AD19/ S6
RESET 8 BHE/ S7
READY 0

8 MIN Mode MAX Mode

NMI 6 HOLD RQ0/ GT0

INTR HLDA RQ1/ GT1
WR LOCK
TEST DEN S0
MN/ MX DT/R S1
RD M/IO S2
ALE QS0
INTA QS1
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Microprocessor rithesh.kini@thadomal.org
 8086 – Pin Configuration
Pin Definitions:

1) Supply pins (3 pins)

2) Clock related pins (3 pins)

3) Address & Data pins (21 pins)

4) Interrupt pins (2 pins)

5) Other Control pins (3 pins)

6) Mode Multiplexed signals (8 pins)

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Microprocessor rithesh.kini@thadomal.org
 8086 – Pin Configuration
Pin Definitions:
Mode Multiplexed signals (8 pins)

MN/MX
MIN Mode MIN Mode 33 VCC

31 HOLD
HOLD DT/R 30 HLDA
29 WR
HLDA M/IO
28 M/I O
8086
WR ALE 27 DT/ R

26 DEN
DEN INTA
25 ALE

24 INTA

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Microprocessor rithesh.kini@thadomal.org
 8086 – Pin Configuration
Pin Definitions:
Mode Multiplexed signals (8 pins)

33 GND MN/MX
MAX Mode MAX Mode
31 RQ/ GT0

RQ0/ GT0 S1 30 RQ/ GT1

29 LOCK
RQ1/ GT1 S2 28 S2
8086
LOCK QS0 27 S1

26 S0

S0 QS1 25 QS0

24 QS1

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Microprocessor rithesh.kini@thadomal.org
 8086

Some common components of 8086 circuit in MIN or MAX mode

are:

1. 8282: (8 – bit) Octal Latch

2. 8286: (8 – bit) Octal bus Transreceiver

3. 8284: Clock Generator

4. 8288: Bus Controller

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Microprocessor rithesh.kini@thadomal.org
 8086

8284: Clock Generator

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Microprocessor rithesh.kini@thadomal.org
 8284: Clock Generator & Driver
i. Provides CLOCK (CLK) signal, a train of pulses at a constant frequency
ii. It synchronizes the READY (RDY) signal which indicates that an interface is ready for
data.
iii. Also synchronizes the RESET (RST) signal which is used to initialize the system
iv. 2 ways :
+ 5v

R D

EFI - (External Frequency Input ) 8086

X1,X2 – Oscillator Clock Input Crystal

C RES
X1

Clock Input selection C X2

CLK CLK

8284 RESET RESET

F/C = 1 clock given through EFI
F/C

READY READY
RDY1

F/C = 0 clock given through Crystal AEN1

RDY2

(Oscillator inputs X1,X2 pins) AEN2

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Microprocessor rithesh.kini@thadomal.org
 8086

8282: (8 – bit) Octal Latch

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Microprocessor rithesh.kini@thadomal.org
 8282: 8 bit latch
 The address data bus AD15-AD0 is
time multiplexed

 The address lines A16 – A19 are

time multiplexed with S3 -S6

 Also BHE & S7 is time multiplexed.

 The address bus and the BHE

signal are demultiplexed using the
ALE signal and then latched into
8282

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Microprocessor rithesh.kini@thadomal.org
 8282: 8 bit latch
 The high ALE asserts the STB of 8282, It enables the external latches to store the address.

 Thus to get the 20 bit address (A0-A7, A8-A15,A16-A19) and the BHE signal, 3 - 8282’s are
required (8 bit latch & 21 lines, so 3 latches reqd).

BHE
A19/S6 8 bit Latch
BHE/S7 8282
A16/S3 A19 - A16
STB OE

8086
ALE . STB
AD15 8 bit Latch 20 bit address to
A15 - A8
8282 the memory or
OE I/O
AD0

STB
8 bit Latch
A8 - A0
8282
OE

Multiplexed Address/ Data bus

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Microprocessor rithesh.kini@thadomal.org
 8086

8286: (8 – bit) Octal bus Transreceiver

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Microprocessor rithesh.kini@thadomal.org
 8286: Octal trans-receiver (Transmitters & Receivers)

i. Contains fully parallel 8 bit bus trans- receiver.  2 transceivers are required as data bus
is 16 – bits.

ii. Tri-state (high impedance outputs)

iii. Acts as bidirectional buffer and increases the driving capacity of the data bus.

iv. It is enabled when OE is low.

A0-A7
AD8-AD15
DT/R B0 – B7 D8 – D16
T controls the direction of DEN
T
8286
OE

flow of data 8086

16 bit data bus
 T =1 data is transmitted
A0-A7
AD0 – AD7 B0 – B7 D0-D7
 T=0 data is received
T 8286
OE

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Microprocessor rithesh.kini@thadomal.org
 8086 – Demultiplexing Address and Data Bus
BHE
A19/S6 8 bit Latch
BHE/S7 8282
A16/S3
STB OE A19 - A16

8086 ALE STB

AD15 8 bit Latch 20 bit address to
A15 - A8
8282 the memory or
AD0 OE I/O

STB
8 bit Latch
A8 - A0
8282
OE
Multiplexed Address/ Data bus A0-A7
AD8-AD15
DT/R B0 – B7 D8 – D16
T
DEN 8286
OE

8086
16 bit data bus

A0-A7
AD0 – AD7 B0 – B7 D0-D7

T 8286
OE

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Microprocessor rithesh.kini@thadomal.org
 8086 - Minimum Mode Minimum System Block Diagram
+ 5v MN/MX Vcc(5V) BHE
ALE
R D STB
BHE Address Bus
8282
A19- A16 (3)

Crystal AD15-AD0 OE
C RES
X1
CLK
C CLK
X2
F/C 8284 RESET RESET
Data Bus
RDY1
READY
READY
8286
AEN1 8086 (2)
RDY2 DEN
OE
AEN2
DT/R
T

M/IO IORD

Wait WR IOWR
State Generator RD 74LS138
HOLD Control 3:8 MRD
Bus Decoder
HLDA MWR
INTR
G2A G2B G1
INTA

Vcc(5V)
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Microprocessor rithesh.kini@thadomal.org
 8086
Read M/Cycle in Min Mode Write M/Cycle in Min Mode

Floating

RD

Make corrections drawn in the blue colour for AD15 - AD0 & DT / R
Note: DEN in Min mode is active low
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Microprocessor rithesh.kini@thadomal.org
 8086

8288: Bus Controller

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Microprocessor rithesh.kini@thadomal.org
 8086 : Operating Modes

 When the Minimum mode operation is selected, the 8086

provides all control signals needed to implement the
memory and I/O interface.

 While in Maximum mode operation, the 8288 provides all

control signals needed to implement the memory and I/O
interface.

.
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Microprocessor rithesh.kini@thadomal.org
 8288: Bus Controller

i. It is used in maximum mode configuration

ii. It accepts the CLK signal along with S0, S1, S 2

iii. It generates the command, control & timing signals at its

output

Microprocessor rithesh.kini@thadomal.org
 8288: Bus Controller + VCC

Multi bus Control Signals

Status S0 MRDC : Memory Read Command Signal
Signal from
8086 S1 Status MWTC : Memory Write Command Signal
Decoder
S2 AMWC : Advance Memory Write Command

Command IORC : I/O Read Command

Signal
Generator IOWC : I/O Write Command

AIOWC : Advanced I/O Write Command

INTA : Interrupt Acknowledge

Operating
mode control
Inputs

DT/ R Control Signals for Data Transceiver

CLK
8286
AEN Control Control Signal DEN
Logic Generator
CEN
MCE/ PDEN
IOB
Address Latch Enable Signal for Octal
ALE
Latch 8282/ 8283

GND

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Microprocessor rithesh.kini@thadomal.org
 8288: Bus Controller

To 8282 & 8286

Multi bus Control Signals

MN/MX
MRDC : Memory Read Command Signal
CLK ALE DT/R DEN
MWTC : Memory Write Command Signal (normal)

8086 AMWC : Advance Memory Write Command

S0
IORC : I/O Read Command
S1 8288
IOWC : I/O Write Comma (normal)
S2
AIOWC : Advanced I/O Write Command

INTA : Interrupt Acknowledge

CLK

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Microprocessor rithesh.kini@thadomal.org
 8086 – Machine Cycle
In Maximum Mode S0,S1, S2 lines are connected to 8288
S2 S1 S0 Bus Cycle/ Machine Cycle

0 0 0 INTA Cycle

0 0 1 I/O Read

0 1 0 I/O Write (Normal & Advanced)

0 1 1 Halt

1 0 0 Opcode Fetch

1 0 1 Memory Read

1 1 0 Memory Write (Normal & Advanced)

1 1 1 Inactive (Idle)

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Microprocessor rithesh.kini@thadomal.org
 8086 – Maximum Mode Maximum System Block Diagram
+ 5v
BHE
STB
R D BHE/S7 Address Bus
8282
A19- A16
A0 – A19
(3)
Crystal OE
C RES
X1
CLK CLK
C X2
F/C 8284 RESET RESET
Data Bus
READY READY
RDY1 8286
AEN1 8086 D0 – D15
RDY2
(2)
AEN2 QS0
QS1 T OE
NMI
INTR
RQ0/ GT0
Multi bus Control Signals
RQ1/ GT1
Wait ALE DT/R
DEN MRDC
State TEST MWTC
Generator MN/ MX S0
AMWC
RD
S1 8288
IORC
LOCK S2
IOWC

AIOWC
CLK INTA

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Microprocessor rithesh.kini@thadomal.org
 8086
Read M/Cycle in Max Mode Write M/Cycle in Max Mode

Note: DEN in Max mode is active high

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Microprocessor rithesh.kini@thadomal.org
 8086

Comparison between Min and Max mode

Self Study

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Microprocessor rithesh.kini@thadomal.org