IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO.
2, FEBRUARY 2022 707
Circuit-Level Exploration of Ternary Logic Using
Memristors and MOSFETs
Jeonggyu Yang , Member, IEEE, Hyundong Lee , Student Member, IEEE,
Jae Hoon Jeong , Graduate Student Member, IEEE, Taehak Kim , Student Member, IEEE,
Sin-Hyung Lee , and Taigon Song , Member, IEEE
Abstract— In recent decades, the performance of binary
computers has escalated through transistor scaling. However, due
to the impotent forecasts of transistor scaling, ternary systems
are regaining attention. Among many ternary device candidates,
a passive device called memristor that is based on resistance
switching is considered a good candidate when integrated with
MOSFETs. Therefore, in this paper, we design various terna-
ry logic based on memristors and MOSFETs from primitive
logic to sequential logic and perform a thorough diagnosis for
circuit design. We highlight design issues that should be resolved
(e.g., signal distortion and high static current) and present
practical solutions such as “Strength Design.” Then, we report
a proper design methodology of sequential circuits considering
the spike phenomena of memristor-based gates. We present
16 novel ternary logic cells and circuitry, including the design
of the first balanced ternary full-adder (TFA) and memristor-
based ternary pulsed-latch (MTPL). By our TFA, we emphasize
that it is possible to design the most practical ternary circuits
using memristors and MOSFETs. Our TFA uses 97 transistors
and 87 memristors, which is the most reasonable TFA design
that has the highest potential to be implemented in the near
future. Besides, the proposed MTPL uses 16 transistors and
10 memristors, and it occupies only 72.7% of the silicon area,
compared to the master-slave ternary flip-flop.
Index Terms— Multi-valued logic, ternary logic, ternary full-
adder, ternary pulsed-latch, memristor.
I. I NTRODUCTION
T HE concept of ternary systems emerged in the 1950s.
Starting from several studies that forecast the advantages
of these systems compared to binary [1], [2], these studies
reported that ternary systems could transmit more information
over a given set of lines and store more data for the same
Manuscript received June 7, 2021; revised August 30, 2021 and October 4,
2021; accepted October 4, 2021. Date of publication December 7, 2021;
date of current version January 28, 2022. This work was supported in part
by the National Research and Development Program through the National
Research Foundation of Korea (NRF) by the Ministry of Science and ICT
(MSIT) under Grant 2020M3H2A1078045; in part by the National Research
Foundation of Korea (NRF) Grant by the Korean Government (MSIT)
under Grant 2019R1G1A10947021; and in part by the BrainKorea21 FOUR
(BK21 FOUR) Project by the Ministry of Education, South Korea, under
Grant 4199990113966. This article was recommended by Associate Editor
M. Martina. (Corresponding author: Taigon Song.)
Jeonggyu Yang, Jae Hoon Jeong, Taehak Kim, Sin-Hyung Lee, and
Taigon Song are with the School of Electronic and Electrical Engineering,
Kyungpook National University (KNU), Daegu 41566, South Korea (e-mail:
jg.yang@knu.ac.kr; tsong@knu.ac.kr).
Hyundong Lee is with the School of Electronics Engineering, Kyungpook
National University (KNU), Daegu 41566, South Korea.
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register length. For example, Hurst [3] reported that ternary
systems require −36.9% fewer operations and data storage
compared to binary systems. However, despite the early inter-
est and reported advantages, the focus on ternary systems has
reduced with time owing to the significant advancements in
binary computers, which are the computing systems that are
most commonly used at present.
In recent decades, the performance of binary computers has
escalated through transistor scaling. Channel length scaled to
nanometer range and advanced devices such as FinFET and
Nanosheet FET have emerged to overcome physical limita-
tions. However, various studies report that device scaling will
eventually come to an end [5]. In fact, these latest studies
are leading to the returning attention of ternary systems.
For example, various novel devices such as ternary CMOS
(T-CMOS) [6], CNTFET [7], and memristor [8] are being
investigated aggressively in this regard. Regarding these
ternary device candidates, T-CMOS is a type of planar MOS-
FET that has the potential to be fabricated in commercial
CMOS foundries. However, it is difficult to design high-
performance ternary logic using T-CMOS because it operates
in the sub-threshold region. CNTFET is a device that uses
carbon nanotubes for its channels, and it is also reported in
recent studies that CNTFET can be fabricated in commercial
CMOS foundries. However, CNTFETs still suffer from hys-
teresis issues in which the Vt h shifts according to the forward
and reverse sweep of the gate voltage. Hysteresis is a critical
issue in CNTFET-based circuitry [9], and sophisticated Vt h
control is required for ternary implementation.
“Memristors” that we focus on in this paper is a passive
device based on resistance switching that depends on the
direction of the applied current. Memristors are considered a
good candidate for ternary computing due to their superior
advantages. For example, memristor logic can implement
Ternary AND (TAND) and Ternary OR (TOR) in a straightfor-
ward structure, as shown in Fig. 1 [8]. In addition, memristors
can be fabricated into the back end of the line (BEOL) [10],
[11] so that memristors are integrated with the CNTFET
or MOSFET into one chip [8], [12], [13], [14], [15]. This
interesting integration allows memristors not to consume any
substrate footprint. These advantages were enough to generate
much interest in memristors for circuit designers.
Thanks to these advantages of memristors, many different
design approaches of ternary logic have been proposed. For
example, by utilizing the non-volatile resistance property
 708 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 2, FEBRUARY 2022
Fig. 1. (a) Symbol and characteristics of a memristor. The resistance of the
memristor increases or decreases depending on the direction of the current.
(b) TAND/TOR schematics, and (c) AND/TOR symbols (see Sec. III-D for
details of TAND/TOR gates). Figure modified from [4].
of memristors, various non-volatile ternary logic has been
proposed, [16], [17]. They have the advantage of storing
non-volatile output using the resistance of the memristors
as logical values but require significant overhead for opera-
tion stage implementation, such as initialization steps [18].
Memristor-CNTFET ternary logic is a very popular design
approach that can take advantage of both memristor and
CNTFET [14], [15]. Therefore, it is possible to implement
ternary logic with excellent characteristics and high density,
but it inherits issues in the manufacturing process, such as
hysteresis, which is a disadvantage of CNTFETs [7], [9].
Memristor-MOSFET1 ternary logic is free from the afore-
mentioned shortcomings by using silicon-based transistors
that are standard in modern VLSI [8], [12]. For example,
memristor-MOSFET integration is currently available in com-
mercial processes, and it does not require multiple steps (e.g.,
initialization) for the operation. Due to these advantages,
memristor-MOSFET integration is forecasted to be the most
practical solution for ternary systems. However, lack of logic
design methodologies and design issues such as signal distor-
tion,2 design complexity, and static power consumption (see
Sec. II) are some of the current concerns that must be resolved
in the process of ternary systems design.
Considering these aspects, this paper presents a practical
implementation of ternary logic using memristors and MOS-
FETs. We present how general ternary logic is implemented
in memristor-MOSFET integration from primitive logic to
sequential logic and provide solutions to the design issues.
Below are our contributions:
1) We propose a practical implementation of various
ternary logic based on memristor-MOSFET. To the best
of the authors’ knowledge, we provide 16 novel ternary
logic cell designs, including the first balanced ternary
full-adder (TFA) design (see Table I), showing that it
is possible to design the most practical ternary circuitry
using memristors and MOSFETs.
1 Note that the term MOSFET includes various types of devices such as
planar MOSFETs and FinFETs. This study uses FinFETs for simulation, and
we emphasize that using FinFETs does not cause any issues in designing
Memristor-MOSFET ternary logic circuits.
2 Recently, a method of inserting a source follower has been proposed, but
the need for additional MOSFET overhead partially offsets the advantage
of ternary logic, and the static current problem is not resolved yet [12].
Our proposed ‘Strength Design’ method solves the signal distortion problem
without additional MOSFET overhead while simultaneously providing a
solution to the static current issue.
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TABLE I
O UR P ROPOSED T ERNARY L OGIC C ELLS AND C IRCUITRY
2) We propose a “Strength Design” method that solves
the signal distortion problem between logic gates in
memristor-MOSFET circuits. In addition, we minimized
the number of memristors used per ‘memristor subcir-
cuit’ to a maximum of four by optimizing the resistance
range of memristors.
3) We solve the design issues in memristor-MOSFET cir-
cuits such as half-V D D and increased design complexity.
4) We highlight the potential of the spike phenomena
and emphasize that this is not always something that
should be avoided. Notably, the proposed novel sequen-
tial logic (memristor-based ternary pulsed latch, MTPL)
aggressively employs the spiking phenomena for its
functionality.
The rest of this paper is organized as follows. In Sec. II,
we present the existing design issues for memristor-MOSFET
ternary logic. Sec. III explains the background information to
understand ternary logic. In Sec. IV, we propose our design
methodology to solve the issues mentioned in Sec. II. In Sec. V
and Sec. VI, we present the various novel ternary logics from
combinational to sequential circuits. Sec. VII presents the
layout of the memristor-MOSFET ternary gates. Sec. VIII
presents the experimental results, and Sec. IX concludes
this paper.
II. C URRENT I SSUES IN M EMRISTOR -
MOSFET C IRCUITS
This section illustrates the current issues in developing
a ternary system based on memristor-MOSFET integration.
We highlight the design issues overlooked by previous studies
([8], [12]) and present key approaches that are required to
overcome the current issues for better implementation.
A. Impedance Matching
We bring the concept of input/output impedance for the
analysis of memristor-based ternary systems. For explanation,
Fig. 2 (a) illustrates a simple driver-load scenario in which
the circuitry is modeled as resistors. In this figure, the input
impedance is the resistance of the load (Z I = R L ), and the
output impedance is the resistance of the driver (Z O = R D ).
The voltage that the driver can supply to the load is determined
by the ratio of Z O and Z I . Thus, it is best to have a
small Z O and a large Z I (∞). However, note that the input
imped-ance of memristor-MOSFET circuits may not always
 YANG et al.: CIRCUIT-LEVEL EXPLORATION OF TERNARY LOGIC USING MEMRISTORS AND MOSFETs
Fig. 2. Input/output Impedance. (a) Definition of input/output impedance.
(b) Impedance issue visualized in logic gates. A case with a low Z O and high
Z I is optimal, but memristor-MOSFET logic may encounter various Z O and
Z I values based on the circuit topologies. Figure modified from [4].
Fig. 3. (a) STI gate schematic proposed in [8] and (b) STI gate schematic
proposed in [12] (see Fig. 7 (a) for the operation of an STI gate). Based on
V D D , a static current of (a) 0.9[V]/1k[] and (b) 1.0[V]/10k[] constantly
flow through the static current path. Figure modified from [4].
be ∞. Due to the finite Z I , the output waveform from logic
gates becomes significantly distorted depending on the Z I
of the destination gate. However, previous studies did not
consider the importance of input/output impedance and the
relevant signal distortion. Therefore, we name our design
strategy “Strength Design” and discuss its details in Sec. IV to
provide a solution to the signal distortion in memristor-based
systems.
B. Half-V D D for Logic Cell Design
Fig. 3 shows the standard ternary inverter (STI) gate pro-
posed in [8] and [12]. Both circuits (a) and (b) use ±V D D /2
voltage sources for their design, which requires additional
circuitry or voltage source to provide ±V D D /2. Thus, our
study provides logic cell designs that require only one V D D .
C. High Static Power Consumption
Ron and Ro f f used in Fig. 3 are the values proposed in [8]
and [12]. However, using these values for memristor circuits
causes significant static power consumption. For example,
when the V D D voltage is applied and maintained as an input
in the circuit shown in Fig. 3 (a), a static current3 flows
through the ‘static current path.’ In these situations, a current
of 0.5V D D /1k[A] = 4.5[mA] continuously leaks through the
3 The distinction between leakage current and on-current becomes ambigu-
ous in memristor-MOSFET circuits, so we will call this ‘static current’
throughout this paper.
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709
static current path that becomes a significant value we cannot
ignore. In the case of the circuit shown in Fig. 3 (b), a static
current of V D D /10k[A] = 0.1[mA] flows through the ‘static
current path,’ which is also a significant value. We solve
this issue by proposing a reasonable resistance range for the
memristor and our design technique.
D. Noise Issues
Like any circuit, memristor-based ternary circuits suffer
from various noise issues. For example, a chronic issue with
memristor-based circuits is that they generate voltage spikes
in particular situations. TAND and TOR gates are good exam-
ples of memristor circuits that generate voltage spikes.4 One
important design metric that ternary circuits should consider
is the noise margin (NM). It is crucial to secure sufficient NM
for the proper operation of ternary logic. With the additional
state (0.5V D D ) required for operation, ternary circuits need
to secure 2 × NM compared to binary circuits. Despite
the importance of noise analysis required in memristor-based
ternary circuits, only few studies have mentioned the impact
of noise issues.
III. R EQUIRED BACKGROUND FOR T ERNARY L OGIC
This section describes some of the background required
for our memristor-MOSFET ternary logic: ternary inverter
(TINV), TAND, and TOR gates. We design balanced ternary
logic (i.e., three logical values of −1, 0, +1). The physical
values of (−1, 0, +1) are (0, V D D /2, V D D ).5
A. Memristor
A memristor is a passive device based on resistance switch-
ing that depends on the direction of the applied current.
Fig. 1 (a) shows the memristor symbol and its characteristics.
When current flows from ‘IN’ to ‘OUT,’ the memristor resis-
tance decreases to Ron . Conversely, the memristor resistance
increases to Ro f f when the current flows from ‘OUT’ to ‘IN.’
To reduce the static current described in Sec. II-C, higher Ron
and Ro f f values are required. Thus, we use Ron = 100k and
Ro f f = 3.2M. Reference [21] reported such memristors are
possible for fabrication.6
B. MOSFET
Our ternary circuits use a MOSFET [22] with the following
states at each voltage of the gate (VG S ).
• VG S = 0: NMOS is OFF and PMOS is ON.
• VG S = V D D /2: NMOS and PMOS are both ON.
• VG S = V D D : NMOS is ON and PMOS is OFF.
A typical ratio between the V D D and Vt h is 5 : 1 in
CMOS circuits to ensure a performance tradeoff [23]. Thus,
4 The voltage spikes generated in TAND/TOR are discussed in Sec. III-D.
5 The difference between a balanced and unbalanced system is due to an
arithmetic operation ([19], [20]). This paper’s arithmetic logic gates (TSUM,
CONS, ANY, TFA) are based on the balanced ternary operation.
6 The memristors used in our ternary logic (except TAND and TOR) can
be replaced with resistors. However, a resistor with very high resistance is
impractical to implement in VLSI. Therefore, we use memristors as resistors
by paying attention to the high-density characteristics of the memristor.
 710 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 2, FEBRUARY 2022

TABLE II TABLE III

O PERATION AND T RUTH TABLE OF T ERNARY I NVERTERS O PERATION OF THE TAND/TOR G ATE . ‘X’ M EANS ‘ DON ’ T C ARE .’ T HE
O UTPUT V OLTAGE I S BASED ON THE V OLTAGE D ISTRIBUTION L AW

Fig. 4. Schematic and symbol of our proposed (a) NTI, (b) PTI, and (c) STI
gates. The current direction is always constant from VDD to GND. Thus,
the resistance of the memristor is always Ro f f . Figure modified from [4].
Fig. 5. (a) TAND gate schematic, (b) the states of TAND depending on
the inputs, and (c) Spike phenomena of memristor-based TAND. When the
input pair is inverted, an unintended spike is caused by the intermediate states
it is reasonable for a MOSFET to be in the ON state at (‘state 2’ and ‘state 4’) at OUT.
VG S = V D D /2.
D. TAND/TOR
Fig. 1 shows the schematic and symbol of the TAND
C. Ternary Inverter and TOR.8 Table IV shows the truth table, and Table III
sum-marizes the operation of these gates according to each
Ternary logic requires three types of inverters: negative
logic input pair. The resistance of the memristor converges to
ternary inverter (NTI), positive ternary inverter (PTI), and
Ron or Ro f f depending on the difference in the voltage for
STI. Fig. 4 shows the schematic and symbol of our proposed
IN1 and IN2. Based on the voltage difference between these
TINV,7 and Table II shows the truth table and operations of
two inputs, the voltage at the OUT node is determined by
these gates.
applying the voltage distribution law between M1 and M2.
For the NTI, NMOS is turned on when the logic input is
Memristor-based TAND and TOR have the advantage of
‘0’ (V D D /2) and ‘+1’ (V D D ). The resistance of the memristor
occupying ‘zero’ silicon area since memristors can be inte-
must be high enough to allow the output to be pulled down
grated into the BEOL [12]. However, note that memristor-
when the NMOS is turned on. For the PTI, PMOS is turned
based TAND and TOR suffer from unintended voltage spikes,
on when the logic input is ‘−1’ (G N D) and ‘0’ (V D D /2).
as shown in Fig. 5. For example, if I N1 is V D D and I N2 is
For the STI, when the applied logic input is ‘−1’(G N D)
0V, then the corresponding current flows from I N1 to I N2,
or ‘+1’(V D D ), either PMOS or NMOS turns on, and the
and the TAND gate becomes ‘State 1.’ After that, if the
output is pulled up to V D D or pulled down to G N D. Thus,
input is inverted (I N1: V D D → 0V, I N2: 0V → V D D ),
the operation of this STI is very similar to a binary inverter.
the corresponding current flows from IN2 to IN1. At this
However, note that when the applied logic input is ‘0’(V D D /2),
time, the resistance of M1 and M2 begins to switch (‘State 2,’
the operation of the STI is very different from a binary
M1: Ro f f → Ron , M2: Ron → Ro f f ), and a spike occurs
inverter. In logic input ‘0’ (V D D /2), voltage distribution applies
at the OU T node according to the voltage distribution rule.
between M1 and M2 as PMOS and NMOS are all turned
After the resistance switching of the memristors is complete,
on. Because the resistance of both memristors is the same,
the TAND’s state eventually converges to ‘State 3.’ This spike
the voltage of the output node becomes V D D /2.
occurs equally as it changes its state to become ‘State 3 →
7 Our TINV circuits are inspired from [24], [25] that are based on ratioed State 4 → State 1’.
logic. Though ratioed logic possess issues such as uneven noise margin, static
power consumption, and delay, we resolve most of these issues by using high- 8 This schematic of the TAND/TOR gate was first reported as the binary
resistance memristors. AND/OR in [13], and its function was extended to the TAND/TOR in [8].

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 YANG et al.: CIRCUIT-LEVEL EXPLORATION OF TERNARY LOGIC USING MEMRISTORS AND MOSFETs
TABLE IV
T RUTH TABLE OF TOR, TAND, NCONS, TSUM, AND NANY G ATES
Fig. 6. Noise margin in the binary inverter. (a) VTC curve of the binary
inverter, (b) Binary noise margin definitions. DR is disallowed range, and IR
is indeterminate range.
E. Noise Margin for Ternary Inverter
This section briefly describes the concept of noise margin
in the binary inverter (N M B ) and then extends the concept of
N M B to noise margin in the ternary inverter (N MT ).9
1) Noise Margin in Binary Inverter: The NM is the standard
for determining the noise-immunity of a logic circuit. Fig. 6
shows the noise margin in the binary inverter. VI L , VI H ,
VO L , and VO H (Voltage of input-low, input-high, output-low,
and output-high) are the x- and y-intercept points at which
the slope (voltage gain) of the voltage transfer characteris-
tics (VTC) curve becomes −1. N M B is described as follows.
N M H = VO H − VI H (1)
N M L = VI L − VO L (2)
N M B = mi n(N M H , N M L ) (3)
VO H /VI H is the acceptable minimum output/input voltage
of the driver/load for the binary logic value ‘1.’ VO L /VI L is the
acceptable maximum output/input voltage of the driver/load
for the binary logic value ‘0.’ N M H /N M L represents the
maximum acceptable noise when the driver’s output voltage is
VO H /VO L . Finally, N M B , the maximum noise that the binary
logic can bear, is determined as the smallest value among
N M H and N M L .
Assuming the driver’s output voltage (Vd,o ) as Vd,o = VO H
and noise voltage of VN , the load’s input voltage (Vl,i ) be-
comes Vl,i = Vd,o − VN = VO H − VN . if the noise voltage
(VN ) be-comes VN > N M H , then Vl,i becomes Vl,i < VO H −
9 We note that the concept of noise margin explained in this paper can be
extended to various logic gates in both binary and ternary. However, this paper
focuses our analysis to inverter (binary) and STI (ternary) for clarity.
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711
Fig. 7. Noise margin in the ternary inverter. (a) VTC curve of the STI,
(b) Ternary noise margin definitions.
N M H = VI H . This means that Vl,i is in the indeterminate
range (IR, see Fig. 6 (b)) and VN is amplified by the load.
2) Noise Margin in Ternary Inverter: Fig. 7 (a) shows the
VTC curve of an STI gate, which is a typical inverter in
ternary logic. We intuitively expand the concept of the binary
NM to ternary logic, as shown in Fig. 7 (b) and describe the
corresponding equations below:
N M P = VO P − VI P (4)
N M Z + = VI Z + − VO Z + (5)
N M Z − = VO Z − − VI Z − (6)
N M M = VI M − VO M (7)
N MT = mi n(N M P , N M Z + , N M Z − , N M M ) (8)
VO P /VI P (Voltage of output-plus/input-plus) is the mini-
mum output/input voltage of the driver/load for ternary logic
value ‘+1.’ VO M /VI M (Voltage of output-minus/input-minus)
is the maximum output/input voltage of the driver/load for
ternary logic value ‘−1.’ VO Z + /VI Z + (Voltage of output-zero-
plus/input-zero-plus) is the maximum output/input voltage of
the driver/load for ternary logic value ‘0.’ VO Z − /VI Z − (Volt-
age of output-zero-minus/input-zero-minus) is the minimum
output/input voltage of the driver/load for ternary logic value
‘0.’ N M P , N M Z + , N M Z − and N M M represent the maximum
acceptable noise in each voltage range.
If noise exceeding each NM is introduced into the signal
line, this noise is amplified and cascaded as in the case of
binary NM and may cause logic failure. Thus, we determine
the ternary noise margin (N MT ) as the smallest value of
N M P , N M Z + , N M Z − and N M M .
From Fig. 7 (b), we easily anticipate that the ternary NM is
much tighter than the binary NM when the same V D D is given.
Due to these attributes, studies on the different characteristics
of ternary NM must be followed. Thus, Sec. VIII-E illustrates
our detailed analysis on the NM of the ternary inverter.
IV. S TRENGTH D ESIGN OF M EMRISTOR -MOSFET G ATES
This section proposes a Strength Design technique for any
memristor-based ternary logic. Our Strength Design technique
is inspired by drive strength concept used in many acad-
emic/industrial studies ([22], [26], [27]). In this paper, our
technique is characterized by memristor-network sizing (not
transistor sizing). We report that parameters such as Z I , Z O ,
propagation delay, and static current can be controlled by
doing so.
 712 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 2, FEBRUARY 2022
Fig. 8. Proposed strength designs of (a) NTI and (b) PTI gate. (c)–(g) Types of memristor subcircuits for strength design. (h) Typical TOR gate.
(i), (j) Applying strength design of a TOR gate. T-, S- and P- denote typical, serial and parallel, respectively. Figure modified from [4].
TABLE V
C HARACTERISTICS OF AN NTI G ATE D EPENDING ON S UBCIRCUIT
T YPES W HEN THE L OGIC I NPUT I S ‘−1’ (0V)
A. Memristor Network Sizing
We explain the fundamentals of our Strength Design based
on an NTI gate. The memristor in Fig. 4 (a) can be replaced by
a ‘memristor subcircuit’ as Fig. 8 (a). A memristor subcircuit
can be selected from one of Fig. 8 (c)–(g). In our proposed NTI
gate design, note that the direction of current flowing through
the memristor is always constant from V D D to G N D. Thus,
the resistance of each memristor in the T-OFF, S-OFF and
P-OFF subcircuits becomes Ro f f . Conversely, the resistance
of each memristor in the S-ON and P-ON designs becomes
Ron . We can control the total resistance (Rt ot al ) by connecting
memristors in series or parallel like this, thereby controlling
various characteristics of our gates.10
B. Memristor Network Sizing to Logic Output Waveforms
When an input of ‘−1’ (0V) is applied to the NTI gate,
the output current is provided by the memristor network.
Therefore, Rt ot al becomes Z O of the NTI gate. A circuit
designer can choose either S-OFF, S-ON, P-OFF, or P-ON
based on its design requirements. When circuits require tight
timing constraints, designers can use S-ON, P-OFF, or P-ON
since ri si ng pr opagati on delay = Rt ot al C L . Similarly, when
the timing constraints and Z O  Z I condition are loose,
a circuit designer can effectively reduce the static current
by adopting the S-OFF subcircuit. These characteristics of
10 Foundries that support Memristor + MOSFET provide memristors that
have the resistance in certain range. If the designer requires a certain resistance
value that is not supported by the foundry, that resistance value must be
designed by Memristor subcircuits.
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TABLE VI
C HARACTERISTICS OF A TOR G ATE D EPENDING ON S TRENGTH D ESIGN
W HEN THE L OGIC I NPUT PAIR I S ‘+1, −1’ (V D D , 0V)
TABLE VII
T OTAL R ESISTANCE AND D EVICE C OUNT OF O PTIMIZED
M EMRISTOR S UBCIRCUITS
the NTI gate, depending on subcircuit types, are summarized
in Table V. Note that the Z I of the NTI gate is assumed
to be infinite because of the gate oxide. Fig. 8 (b) shows the
Strength Design of the PTI gate. The characteristics of the PTI
gate, based on subcircuit type, are similar to those of the
NTI gate.
Similar to the NTI and PTI gates, The TOR gate can also
control Z I , and Z O . Fig. 8 (i) and (j) show the Strength
Designs of the TOR gate. The difference from the NTI gate is
that Z I is finite. A circuit designer can use Z I that is N times
higher than that of T-TOR’s by adopting S-TOR and can use
the Z O that is N times lower than that of T-TOR’s by adopting
P-TOR design. Table VI summarizes the characteristics of
these Strength Designs of the TOR gate. Z I and Z O of the
TAND can also be controlled in the same way as the TOR.
C. Memristor Subcircuit Optimization
Another point to note in our Strength Design is that we
select Ro f f = 32Ron . If a circuit designer requires R O =
0.2M (×64), 16 memristors are needed in the P-OFF type.
However, R O = 0.2M (×64) can be designed with only
two memristors in the S-ON type. That is, there is an
 YANG et al.: CIRCUIT-LEVEL EXPLORATION OF TERNARY LOGIC USING MEMRISTORS AND MOSFETs
Fig. 9. Optimized memristor subcircuits. The maximum device count for
our topology from ×1 to ×128 is only 4. Note the polarity of the memristors.
Figure modified from [4].
Fig. 10. Schematic and symbol of the proposed (a) STI, (b) TBUF, and
(c) NCONS. M1 and M2 are adopted as one of Fig. 9 (×1 - ×128).
Figure modified from [4].
optimal subcircuit type using the minimum memristor for each
strength.
Through the study of selecting the correct polarity of
the memristors, it is possible to design a wide range of
strengths using the minimum number of memristors. Fig. 9
and Table VII show our example of designing Rt ot al from
×1 to ×128 by using four memristors only.
V. T ERNARY L OGIC G ATE & F ULL -A DDER D ESIGN
This section presents the ternary gates required in designing
a balanced ternary full-adder (TFA). As mentioned in Sec. IV,
our proposed ternary logic gates are capable of strength-
controlling. For the ternary decoder (TDEC), we apply
impedance matching as discussed in Sec. IV.
A. STI (TINV) and TBUF
Fig. 10 (a) shows the schematic of our proposed STI gate.
Similar to the case of NTI, PTI described in Sec. IV-A, for the
strength design of STI, each memristor in Fig. 4 (c) can be
replaced by a ‘memristor subcircuit’ in Fig. 8 (c)–(g). For the
output to become V D D /2 in the input voltage V D D /2, the same
strength has to be chosen for M1 and M2.
Similar to a binary buffer, TBUF consists of two STI gates
connected in series (see Fig. 10 (b)).
B. NCONS and TDEC
NCONS is a consensus (CONS) gate with an inverted
output. Fig. 10 (c) and Table IV show the schematic and truth
table of our NCONS gate, respectively. The logic output of
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713
Fig. 11. TDEC (a) schematic and (b) symbol [12]. Note the impedance
matching is required in designing the TDEC gate. Figure modified from [4].
TABLE VIII
T RUTH TABLE OF T ERNARY D ECODER (TEDC)
Fig. 12. Schematics of our proposed (a) TSUM and (b) NANY gates.
Figure modified from [4].
NCONS is ‘−1’ if the logic input pair is (−1, −1), ‘+1’ if
the logic input pair is (+1, +1), and ‘0’ if otherwise.
TDEC is a logic gate that outputs ‘+1’ when a specific
input is applied and outputs ‘−1’ otherwise. Fig. 11 and
Table VIII show the schematic and truth table of our TDEC
gate, respectively [12]. Since the outputs of the gates L1 and
L2 do not always drive infinite Z I (i.e., gate oxide), designers
should match the impedance in the highlighted nodes to get
proper output waveforms. Note that the memristor subcircuits
used in the designs of L1, L2, and L3 are highly-dependent to
each other, meaning that an optimal L3 design is not possible
without considering the relationship between L1 and L2.
C. TSUM and NANY
Ternary summation (TSUM) is a logic gate that performs the
sum operation. Fig. 12 (a) and Table IV present the schematic,
symbol, and truth table of our TSUM gate. Negative-accept
anything (NANY) is the accept anything (ANY) logic with an
inverted output. This gate performs the carry operation in the
balanced ternary full-adder. Fig. 12 (b) and Table IV present
the schematic, symbol, and truth table of our NANY gate.
D. Balanced Ternary Full-Adder
Using the essential logic gates discussed in the previous
sections, we design a balanced ternary full-adder as shown
 714 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 2, FEBRUARY 2022
Fig. 13. Ternary full-adder schematic [19].
Fig. 14. Schematics of (a) TNAND-based ternary D-latch (TNAND-TL) and
(b) transmission gate-based ternary D-latch (TG-TL). For (a) D-latch, spikes
generated by TANDs may flow into the feedback loop. Therefore, we claim
that (b) D-latch avoiding the use of TAND is recommended.
in Fig. 13 [19]. The TSUM is composed of 29 memristors
and 31 transistors, and NANY is composed of 25 memristors
and 27 transistors. Thus, the total number of devices used to
construct our full-adder is 87 memristors and 97 transistors.
We emphasize that this is the first full-adder designed in
memristor-MOSFET.
VI. S EQUENTIAL T ERNARY L OGIC D ESIGN
In this section, we explore various sequential element
designs in memristor-MOSFET. We report the negative effect
of memristor’s spike phenomena on the sequential elements
and propose a proper design methodology of sequential cir-
cuits that avoids this effect. Furthermore, we propose a novel
pulsed-latch that utilizes the memristor’s spike phenomena.11
A. Ternary Latch
Fig. 14 (a) shows the schematic of a conventional TNAND-
based ternary D latch (TNAND-TL). This structure, modified
from the binary D latch, provides a function to store a ternary
value and has been reported in many studies [29], [30].
However, we report that this circuit is not usable in memristor-
based ternary logic due to the spike phenomena mentioned in
Sec. III-D. For example, when both inputs of L1 TAND are
switched conversely, a spike occurs at the output of L1. This
spike is delivered to the input of the L3 TAND through output
11 We note that there are not many studies on the ternary dynamic flip-flop
or various sequential circuit designs in the current status. Latest study [28]
in CNTFET-based ternary proposed new flip-flop designs such as the con-
ventional master-slave ternary D flip-flop (MSTFF) and quad-edge-triggered
flip-flop (QETFF).
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Fig. 15. Schematic of the master-slave ternary D flip-flop (MSTFF).
Q, and it remains on the feedback loop. In the same situation,
the spike generated in the L2 TAND is delivered to the input
of the L1 TAND through output Q. Therefore, a TAND-based
ternary D latch in memristor-based circuitry cannot operate
properly because these spikes flow in the feedback loop.
Therefore, we claim that a transmission gate-based ternary
D-latch (TG-TL) structure shown in Fig. 14 (b) is more a
feasible structure in memristor-based ternary logic as it avoids
using spike induced feedback loops. When the clock (C L K )
is ‘+1’, TG1 is transparent, and the input D is transmitted to
the Q. When C L K is switched to ‘−1’, TG2 is on, and the
feedback loop holds output Q. Note that we use L1 and L2 to
prevent the in/output noise from flowing in the feedback loop.
B. Ternary Flip-Flop
Fig. 15 shows the most common sequential component,
master-slave ternary flip-flop (MSTFF), which consists of two
latches in series. When C L K is −1, the master latch is
turned on, and input D is transmitted to N1, the input of
the slave latch. When C L K is +1, the slave latch is turned
on, and the value of N1 is output as Q. Input/output noises
are governed by L1 and L2. Note that the cascading feedback-
based latches for flip-flop design are implausible due to the
spike phenomena.
C. Ternary Pulsed-Latch
In modern digital VLSI, pulsed-latch is being studied as an
alternative to MSTFFs in order to reduce the area occupied
by sequential elements, which is approximately 20% of the
entire silicon area [31]. A Pulsed-latch performs the same role
as a flip-flop that stores the input value to the output from the
edge of the C L K , and the most notable difference from a
flip-flop is that a pulsed latch uses a narrow pulse signal as
an enable signal. A pulsed-latch requires a pulse generator
for converting the C L K signal into a narrow pulse. Fig. 16
shows a conventional binary pulsed-latch (CBPL), which uses
a pulse signal generated from the delay of an inverter chain
((td,I N V + (N × td,BU F ))) of the pulse generator. At the rising
edge of the C L K , a pulse is generated by the pulse generator.
By this pulse, the latch becomes transparent for a short time
that corresponds to the width of the pulse, and it stores the
input value in the output Q.
Inspired by CBPL, we propose a first memristor-based
ternary pulsed-latch (MTPL) that stores the ternary input value
to the output Q at the edge of the C L K . Fig. 17 shows the
schematic of our MTPL and operational waveform of a pulse
generator. We use the spike phenomena of the TAND gate to
generate a pulse (described in Sec. III-D), not by the delay
 YANG et al.: CIRCUIT-LEVEL EXPLORATION OF TERNARY LOGIC USING MEMRISTORS AND MOSFETs
Fig. 16. (a) Schematic of the conventional binary pulsed-latch (CBPL) and
(b) conventional pulse generator waveform.
Fig. 17. (a) Schematic of the proposed memristor-based ternary pulsed-latch
(MTPL) and (b) proposed memristor-based pulse generator waveform.
of the inverter chain, and the pulse width is dependent on
the switching delay of the TAND gate. (A pulse generator
can also be designed using a TOR gate.) Our MTPL consists
of 16 transistors and 10 memristors. In fact, it uses the area
of 16 transistors, so it only occupies 72.7% of the silicon area
compared to an MSTFF.
We emphasize that the pulse signal occurs at both the rising
and falling edge of C L K for our MTPL. In other words,
it provides the same functionality as a double edge-triggered
flip-flop, which means that the designer can use 1/2 times
the frequency of a single trigger flip-flop clock. Therefore,
we have a huge advantage on power consumption when using
the proposed MTPLs. Table IX presents a comparison of the
characteristics of MSTFF and MTPL.
VII. L AYOUT
This section presents the layout of the ternary gates in
memristor and MOSFET. First, 1) we present technology
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715
TABLE IX
C OMPARISON OF M ASTER -S LAVE T ERNARY D F LIP -F LOP (MSTFF)
AND M EMRISTOR -B ASED P ULSED -L ATCH (MTPL)
details behind our ternary gates and 2) describe the similarities
and differences of memristor-MOSFET to other ternary logic.
Then, we propose gate-level optimization that can be applied
in memristor-MOSFET logic. Finally, we present how module-
level area optimization of the ternary gates can be done in
memristor and MOSFET.
A. Design Rule of Memristor and MOSFET
Our memristor-MOSFET layouts are based on two ref-
erences: First, our MOSFETs and interconnects are based
on the design rules of the SAED 32/28nm technology
library [22]. Second, the size of our memristors is based
on [12]. In this study, a memristor can be fabricated to be
0.36μm 2 (0.6μm × 0.6μm). Fig. 18 (a) shows the structure
of our STI gate in memristor and MOSFET. Memristors
integrated into the BEOL are connected vertically to the vias
of the STI gate. Though (a) illustrates the Memristor-subcircuit
to be placed next to the transistors of STI, memristors can be
placed on top of the transistors as illustrated in Fig. 18 (b).
Due to this, note that (b) do not require an additional footprint
for memristor placement.
B. Gate-Level Layout Optimization
The uniqueness of memristor-MOSFET layout is that mem-
ristors and MOSFETs are placed in different regions (substrate
or BEOL). Thus, memristor-MOSFET layout has more poten-
tial to reduce area than any other ternary devices. Following
the typical layout style of standard cells, memristor-MOSFET
devices do not always fill the full layout area. For example,
Fig. 18 (c) and (d) show the layouts of NTI and PTI gates.
Note that PMOS region of NTI and NMOS region of PTI
are empty since NTI only uses NMOS and PTI only uses
PMOS. Understanding the uniqueness of memristor-MOSFET
layout, we propose a gate-level layout optimization technique.
As in Fig. 18 (e), we propose an NPTI gate that integrates
NTI and PTI in the same footprint as NTI and PTI. NPTI
is a gate that can only be designed in memristor-MOSFET
logic with minimum footprint, and designers must understand
the uniqueness of schematic and layout for the most optimal
ternary gate design.
C. System-Level Layout Optimization
A system-level ternary logic requires many gates in its
layout. The key idea of ternary gates requiring both mem-
ristors and MOSFETs lead to a unique optimization method
 716 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 2, FEBRUARY 2022
Fig. 18. (a) 3D structure and (b) layout design of our proposed STI gate. Layout design of our (c) NTI, (d) PTI, (e) NPTI, and (f) ternary half-adder (THA).
NPTI is a gate in which NTI and PTI are integrated.
TABLE X
L AYOUT A REA OF M EMRISTOR -MOSFET T ERNARY L OGIC GATES a
in system-level designs. Table X shows the layout area of
MOSFETs and memristors in some gates. Note that the
area between MOSFETs and memristors is highly-different
in each gate. MOSFETs consume more area in some gates,
and memristors consume more area in some other gates (note
that TAND and TOR require zero silicon area). Due to this
unbalance, a gate-level ternary logic in memristor-MOSFET
will always encounter less-optimized ternary gates. This means
that a fixed design methodology of ternary standard cells may
not be the best optimization method for memristor-MOSFET.
In addition, a recent study on memristor fabrication reported
that 8nm × 8nm memristors could be fabricated [32] success-
fully. Therefore, we forecast the two important points that must
be considered in a system-level ternary logic design: First,
a conventional standard cell and synthesis design may not be
the most optimized layout design in terms of layout due to the
area mismatch between MOSFETs and memristors. Designers
can find better area optimization if the MOSFETs and mem-
ristors can be designed separately in system level. Second,
the concept of separate optimization between MOSFETs and
memristors will highly depend on the device sizes. Based
on [32] that shows significantly small memristors compared to
MOSFETs, a highly-different optimization methodology will
be required for the smallest layout compared to the layouts
in Table X.
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TABLE XI
MOSFET D EVICE D IMENSIONS
VIII. E XPERIMENTAL R ESULTS & D ISCUSSIONS
This section presents the experimental results for the pro-
posed circuits described in Sec. IV, V, and VI.12 We use the
Verilog-A-based memristor model proposed in [33]. This is an
effective model that satisfies all three evaluation criteria (plau-
sibility of the i–v characteristics, nonlinearity of switching
kinetics, and applicability to simulate complementary resistive
switching behavior) of the memristor model for accurate sim-
ulation mentioned in [34]. Regarding the transistors, we use
typical 14nm FinFETs from [22], and Table XI shows the
detailed dimensions. We use Synopsys HSPICE P-2019.06 to
conduct the SPICE experiments13 and Synopsys Custom Com-
piler M-2017.03-SP1 for designing schematics.
A. Strength Design
Fig. 19 shows the waveform of our proposed logic cells.
From the results of the PTI, NTI, and STI gates, we note that
the strength and propagation delay are inversely proportional.
Moreover, the correct waveform of TDEC is the result of our
proper impedance matching. Fig. 20 shows the static current
of each logic gate when V D D = 1V. The largest static current
12 For the concentrated scope of our paper, we do not present layout results,
despite the area advantage that Memristor + MOSFET circuits have.
13 Current studies in ternary research are mostly based on CNTFET, CNT-
FET + memristor, and memristor + MOSFET. CNTFET-based designs show
the best performance (in simulation) and area, but the possibility of simulation
performance to be actually shown is currently low [35], [36]. In this regard,
we highlight that our study presents the most practical ternary results with
the highest performance.
 YANG et al.: CIRCUIT-LEVEL EXPLORATION OF TERNARY LOGIC USING MEMRISTORS AND MOSFETs
Fig. 19. Transient waveforms of our TINV (NTI, PTI, and STI) and TDEC.
Gate strength and propagation delay are inversely proportional.
Fig. 20. Static current of the (a) PTI, (b) NTI, and (c) STI gates according
to their input voltage when V D D = 1V.
occurs at the input in which both the NMOS and PMOS are
turned on, and it depends on their strength. Thus, designers
should choose an appropriate strength that fits their situation
and purpose (power, delay, and impedance matching) when
designing memristor-MOSFET ternary logic. We highlight
that our Strength Design does not require more memristors
for stronger strength. (See Sec. IV-C for memristor count
optimization.) Fig. 21 shows the device counts per strength
for the PTI, NTI, STI, and NCONS gates. A wide range of
strengths (resistance) can be expressed using proper size and
polarity with the minimum memristor count.
B. Ternary Full-Adder Design
Fig. 22 shows the waveforms of our balanced ternary full-
adder, and Table XII shows a comparison between our adder
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717
Fig. 21. Device count of the NTI, PTI, STI, and NCONS gates according to
its gate strengths. Note that the memristor count is limited to a certain number
despite the various circuit strength (See Sec. IV-C, from ×1 to ×128).
Fig. 22. Transient simulation result of our balanced ternary full-adder. Spikes
occur in Sum and Cin+1 due to the properties of the memristors described
in Sec. III-D.
TABLE XII
C OMPARISON OF T ERNARY F ULL -A DDERS
and other adder designs. Reference [37] designed a ternary
full-adder using 2D materials: black phosphorus (BPFET) and
MoS2 (MoS2 FET). However, these devices involve challenges
in commercialization, similar to the CNTFET-based ternary
logic [19]. The authors of [38] suggested a ternary full-
adder using only CMOS transistors, but this adder requires a
large number of devices. Unlike the adders mentioned above
(summarized in Table XII), we emphasize that we designed
the most practical ternary full-adder by using 97 transistors
and 87 memristors that can be integrated into BEOL [12].
In addition, memristor-MOSFET integration can be fabricated
using commercial processes [39], [40]. Therefore, we consider
 718 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 2, FEBRUARY 2022
Fig. 23. Transient simulation result of the ternary sequential elements. For
TNAND-TL, normal operation is not guaranteed due to the spike phenomena
of the TAND/TOR.
our design method the most practical solution for ternary
system implementation.
C. Sequential Logic Design
Fig. 23 shows the output waveforms of our proposed
sequential elements. TG-TL shows proper output waveform,
while the TNAND-TL does not in memristor-MOSFET. This
result shows how the memristor-based voltage-spikes contam-
inate the feedback loop and tamper with the output waveform
(mentioned in Sec. VI-A). The MSTFF and our proposed
MTPL also show correct functionality. Note that the MSTFF
is positive-edge triggered, whereas our MTPL is both-edge
triggered. Regarding pulsed-latches, our clock-generating cir-
cuit generates a uniform pulse on both the rising and falling
edges. A designer may use a pulse generator circuit based on
Fig. 16 or Fig. 17 based on the needs of its circuitry. Unlike
the conventional pulsed-latch, which only generate pulses on
the rising edge, our MTPL operates twice as fast as MSTFF
and conventional pulsed latches. The operation speed may be
controlled by using different pulse generators.
D. Comparison With Other Technology Nodes
Fig. 24 shows a delay/static current comparison between
various technology nodes (=SAED 90nm, 32nm, 14nm [22])
on some ternary gates. All the technology nodes exhibit
a similar propagation delay (inversely proportional to the
strength) and static current (proportional to the strength).
This is because the main factor of the propagation delay
is not on the transistors but is on the memristor Strength
Design (see Sec. IV). This means that both technology scaling
and memristor strength planning must be held to visualize
the impact on technology scaling for memristor-MOSFET
circuitry.
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Fig. 24. Delay and static current comparison between various technology
nodes (=SAED 90nm, 32nm, 14nm). The propagation delay and static current
are similar in different technology nodes since the critical factor for these is
the memristor strength.
Fig. 25. VTC result of our STI gate according to gate strengths. The
strength and logic ‘0’ output range are proportional, which will determine
the NM. ×1(Opt. tr. for NM) curve shows the VTC curve when transistors
are optimized for NM.
E. Noise Margin Analysis
Fig. 25 shows the VTC curves of our STI gate, which
vary according to their strengths. We analyzed the N MT
for each strength, and Fig. 26 shows the details. First, STI
with ×64 memristor subcircuit has the maximum N MT in
our configuration. Thus, for the best NM in STI gates for
sequential logic (e.g., for L1, L2 in Fig. 14 (b), 15, and 17),
×64 STI is preferable. However, note that differently-sized
STI may be preferred for the lowest power.
Regarding the NM of memristor-MOSFET circuits,
we compare the N MT of CNTFET STI with memristor-
MOSFET STI in Table XIII. First, comparing [41] and [42],
we see a noticeable difference of 8.3% improvement. Tran-
sistor sizing and Vt h adjusting are important design knobs in
CNTFET-based circuits, and [42] performed transistor sizing
to optimize the NM. On the other hand, note that the memristor
strength variation from ×1 to ×128 changes the intermediate
part of the VTC curve in Fig. 25. Weaker strength (×1) that
consists of higher resistance shows a steeper slope because
 YANG et al.: CIRCUIT-LEVEL EXPLORATION OF TERNARY LOGIC USING MEMRISTORS AND MOSFETs
Fig. 26. NM of our STI gate according to gate strengths. It has the best NM
at strength ×64.
TABLE XIII
C OMPARISON OF N OISE M ARGIN IN T ERNARY I NVERTER
the high resistance of the memristors strongly distributes the
voltage. However, memristor strength has minimal impact to
VI M and VI P . The values of these parameters can be changed
by adjusting the Vt h of transistors. An ideal memristor-
MOSFET circuit should have a |Vt h | that is 1/4 of the V D D
and weaker strength memristors (e.g., ×1) for steep VTC
curve. To prove this statement, the ‘Opt. tr. for NM’ curve
of Fig. 25 shows an ideal VTC curve of memristor-MOSFET
STI when all parameters are optimized for the NM using
×1 Strength Design. In this ideal case, we can see that the NM
of memristor-MOSFET STI can be improved as 20.0 percent.
IX. C ONCLUSION
In this paper, we present a practical design solution for
ternary logic gates based on memristor-MOSFET. Based
on our study, we highlight the following: (1) We present
memristor-MOSFET ternary gates that require only one V D D
to minimize design complexity. (2) We propose 10 novel prim-
itive gates, 5 novel combinational gates, and one novel sequen-
tial gate, including one ternary full-adder (TFA), which has
the smallest component count. (3) We propose our “Strength
Design” that can manage signal distortion and static current
issues of memristor-MOSFET circuits. In addition, we have
minimized the number of memristors used per ‘memristor
subcircuit’ to a maximum of four by optimizing the resistance
range of memristors. (4) We report that the spike phenomena
of memristor-based gates can contaminate the feedback loop
and propose a novel methodology of pulse generator design
for memristor-based ternary pulsed latch (MTPL).
Our future work includes (1) layout/performance optimiza-
tion of memristor-MOSFET ternary cells with a thorough
comparison to other ternary logic families, (2) issues to handle
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719
for proper technology scaling, and (3) fabrication/verification
in actual memristor-MOSFET VLSI.
ACKNOWLEDGMENT
The EDA tool was supported by the IC Design Education
Center (IDEC), South Korea.
R EFERENCES
[1] C. Y. Lee and W. H. Chen, “Several-valued combinational switching
circuits,” Trans. Amer. Inst. Electr. Eng., I, Commun. Electron., vol. 75,
no. 3, pp. 278–283, Jul. 1956.
[2] P. C. Balla and A. Antoniou, “Low power dissipation MOS ternary logic
family,” IEEE J. Solid-State Circuits, vol. SSC-19, no. 5, pp. 739–749,
Oct. 1984.
[3] S. L. Hurst, “Multiple-valued logic—Its status and its future,” IEEE
Trans. Comput., vol. C-33, no. 12, pp. 1160–1179, Dec. 1984.
[4] J. Yang, H. Lee, J. H. Jeong, T. H. Kim, S.-H. Lee, and T. Song,
“A practical implementation of the ternary logic using memristors
and MOSFETs,” in Proc. IEEE 51st Int. Symp. Multiple-Valued Log.
(ISMVL), May 2021, pp. 183–188.
[5] E. Prati and T. Shinada, “Atomic scale devices: Advancements and
directions,” in IEDM Tech. Dig., Dec. 2014, pp. 1.2.1–1.2.4.
[6] J. W. Jeong et al., “Tunnelling-based ternary metal–oxide–
semiconductor technology,” Nature Electron., vol. 2, no. 7, pp. 307–312,
Jul. 2019, doi: 10.1038/s41928-019-0272-8.
[7] M. D. Bishop et al., “Fabrication of carbon nanotube field-effect tran-
sistors in commercial silicon manufacturing facilities,” Nature Electron.,
vol. 3, no. 8, pp. 492–501, Aug. 2020.
[8] M. Khalid and J. Singh, “Memristor based unbalanced ternary logic
gates,” Anal. Integr. Circuits Signal Process., vol. 87, no. 3, pp. 399–406,
Jun. 2016.
[9] H. Shimauchi, Y. Ohno, S. Kishimoto, and T. Mizutani, “Suppression
of hysteresis in carbon nanotube field-effect transistors: Effect of con-
tamination induced by device fabrication process,” Jpn. J. Appl. Phys.,
vol. 45, no. 6B, pp. 5501–5503, Jun. 2006.
[10] L. Begon-Lours et al., “A back-end-of-line compatible, ferroelectric
analog non-volatile memory,” in Proc. IEEE Int. Memory Workshop
(IMW), May 2021, pp. 1–4.
[11] X. Sheng et al., “Low-conductance and multilevel CMOS-integrated
nanoscale oxide memristors,” Adv. Electron. Mater., vol. 5, no. 9,
Sep. 2019, Art. no. 1800876.
[12] X.-Y. Wang et al., “High-density memristor-CMOS ternary logic
family,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 68, no. 1,
pp. 264–274, Jan. 2021.
[13] S. Kvatinsky, N. Wald, G. Satat, A. Kolodny, U. C. Weiser, and
E. G. Friedman, “MRL—Memristor ratioed logic,” in Proc. 13th Int.
Workshop Cellular Nanosc. Netw. Appl., Aug. 2012, pp. 1–6.
[14] A. Mohammaden, M. E. Fouda, L. A. Said, and A. G. Radwan,
“Memristor-CNTFET based ternary full adders,” in Proc. IEEE 63rd
Int. Midwest Symp. Circuits Syst. (MWSCAS), Aug. 2020, pp. 562–565.
[15] N. Soliman, M. E. Fouda, A. G. Alhurbi, L. A. Said, A. H. Madian, and
A. G. Radwan, “Ternary functions design using memristive threshold
logic,” IEEE Access, vol. 7, pp. 48371–48381, 2019.
[16] A. A. El-Slehdar, A. H. Fouad, and A. G. Radwan, “Memristor-based
balanced ternary adder,” in Proc. 25th Int. Conf. Microelectron. (ICM),
Dec. 2013, pp. 1–4.
[17] H. Zhang et al., “Implementation of unbalanced ternary logic gates with
the combination of spintronic memristor and CMOS,” Electronics, vol. 9,
no. 4, p. 542, Mar. 2020.
[18] X. Hu, M. J. Schultis, M. Kramer, A. Bagla, A. Shetty, and
J. S. Friedman, “Overhead requirements for stateful memristor logic,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 1, pp. 263–273,
Jan. 2019.
[19] S. Kim, S.-Y. Lee, S. Park, K. R. Kim, and S. Kang, “A logic synthesis
methodology for low-power ternary logic circuits,” IEEE Trans. Circuits
Syst. I, Reg. Papers, vol. 67, no. 9, pp. 3138–3151, Sep. 2020.
[20] J. Ko, K. Park, S. Yong, T. Jeong, T. H. Kim, and T. Song, “An optimal
design methodology of ternary logic in ISO-device ternary CMOS,” in
Proc. IEEE 51st Int. Symp. Multiple-Valued Log. (ISMVL), May 2021,
pp. 189–194.
[21] A. Chanthbouala et al., “A ferroelectric memristor,” Nature Mater.,
vol. 11, pp. 860–864, Sep. 2012.
 720 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 2, FEBRUARY 2022
[22] Synopsys. (2021). 14 nm and 32/28 nm Process Design Kits.
[Online]. Available: https://www.synopsys.com/community/university-
program/teaching-resources.htm
[23] R. X. Gu and M. I. Elmasry, “Power dissipation analysis and optimiza-
tion of deep submicron CMOS digital circuits,” IEEE J. Solid-State
Circuits, vol. 31, no. 5, pp. 707–713, May 1996.
[24] K. Abbas, Ratioed Logic. Cham, Switzerland: Springer, 2020,
pp. 81–109.
[25] H. T. Mouftah and K. C. Smith, “Design and implementation of three-
valued logic systems with M.O.S. Integrated circuits,” IEE Proc. G-
Electron. Circuits Syst., vol. 127, no. 4, pp. 165–168, Aug. 1980.
[26] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems
Perspective, 4th ed. Reading, MA, USA: Addison-Wesley, 2010.
[27] Silvaco. (2021). Open-Cell 45 nm FreePDK Library. [Online]. Available:
https://si2.org/open-cell-library
[28] S. Kim, S.-Y. Lee, S. Park, and S. Kang, “Design of quad-edge-triggered
sequential logic circuits for ternary logic,” in Proc. IEEE 49th Int. Symp.
Multiple-Valued Log. (ISMVL), May 2019, pp. 37–42.
[29] Z. T. Sandhie, F. U. Ahmed, and M. H. Chowdhury, “Design of ternary
master-slave D-flip flop using MOS-GNRFET,” in Proc. IEEE 63rd Int.
Midwest Symp. Circuits Syst. (MWSCAS), Aug. 2020, pp. 554–557.
[30] B. D. Madhuri and S. Sunithamani, “Design of ternary D-latch using
graphene nanoribbon field effect transistor,” in Proc. Int. Conf. Vis.
Towards Emerg. Trends Commun. Netw. (ViTECoN), Mar. 2019, pp. 1–4.
[31] S. Dhong et al., “A 0.42 V Vccmin ASIC-compatible pulse-latch
solution as a replacement for a traditional master-slave flip-flop in a
digital SOC,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2014,
pp. 1–4.
[32] S. Pi, P. Lin, and Q. Xiaa, “Cross point arrays of 8 nm × 8 nm
memristive devices fabricated with nanoimprint lithography,” J. Vac. Sci.
Technol. B, Microelectron., vol. 31, no. 6, 2013, Art. no. 06FA02.
[33] X. Wang, B. Xu, and L. Chen, “Efficient memristor model implementa-
tion for simulation and application,” IEEE Trans. Comput.-Aided Design
Integr. Circuits Syst., vol. 36, no. 7, pp. 1226–1230, Jul. 2017.
[34] E. Linn, A. Siemon, R. Waser, and S. Menzel, “Applicability of well-
established memristive models for simulations of resistive switching
devices,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 8,
pp. 2402–2410, Aug. 2014.
[35] M. M. Shulaker et al., “Carbon nanotube computer,” Nature, vol. 501,
no. 7468, pp. 526–530, 2013.
[36] G. Hills et al., “Modern microprocessor built from complementary
carbon nanotube transistors,” Nature, vol. 572, no. 7771, pp. 595–602,
2019.
[37] M. Huang, X. Wang, G. Zhao, P. Coquet, and B. Tay, “Design and
implementation of ternary logic integrated circuits by using novel two-
dimensional materials,” Appl. Sci., vol. 9, no. 20, p. 4212, Oct. 2019.
[38] A. Srivastava and K. Venkatapathy, “Design and implementation of a low
power ternary full adder,” VLSI Des., vol. 4, no. 1, pp. 75–81, 1996.
[39] Taiwan Semiconductor Manufacturing Corporation. (2021). eFlash.
[Online]. Available: https://www.tsmc.com/english/dedicated-
Foundry/technology/specialty/eflash
[40] Circuits Multi-Projects. (2021). Memory Advanced Demonstrator
200 mm (MAD200). [Online]. Available: https://mycmp.fr/nvm-mad200
[41] S. Lin, Y. B. Kim, and F. Lombardi, “CNTFET-based design of ternary
logic gates and arithmetic circuits,” IEEE Trans. Nanotechnol., vol. 10,
no. 2, pp. 217–225, Mar. 2011.
[42] G. Cho and F. Lombardi, “Design and process variation analysis of
CNTFET-based ternary memory cells,” Integration, vol. 54, pp. 97–108,
Jun. 2016.
Jeonggyu Yang (Member, IEEE) received the B.S.
degree in electronic engineering from Keimyung
University (KU), Daegu, South Korea, in 2018. He is
currently pursuing the M.S. degree with the Intelli-
gent 3-Dimensional Very Large Scale Integrated Cir-
cuits (I3D VLSI) Laboratory, Kyungpook National
University (KNU), Daegu.
His current research interests include multi-valued
logic design and digital VLSI design for embedded
machine learning.
Authorized licensed use limited to: Indian Institute of Information Technology Design & Manufacturing. Downloaded on August 17,2023 at 07:56:29 UTC from IEEE Xplore. Restrictions apply.
Hyundong Lee (Student Member, IEEE) is
currently pursuing the B.S. degree in electronics
engineering with the School of Electronics Engineer-
ing, Kyungpook National University (KNU), Daegu,
South Korea. He is an Undergraduate Intern with
the Intelligent 3-Dimensional Very Large Scale Inte-
grated Circuits (I3D VLSI) Laboratory, KNU. His
current research interests include multi-valued logic
design and low power design of ternary circuits.
Jae Hoon Jeong (Graduate Student Member, IEEE)
received the B.S. degree in electrical engineering
from the School of Electronics Engineering, Kyung-
pook National University (KNU), Daegu, South
Korea, in 2021, where he is currently pursuing
the M.S. degree with the Intelligent 3-Dimensional
Very Large Scale Integrated Circuits (I3D VLSI)
Laboratory. His research interests include the logic
design in 5nm/3nm and VLSI implementation of
machine learning.
Taehak Kim (Student Member, IEEE) received the
B.S. degree in electrical engineering from the School
of Electronics Engineering, Kyungpook National
University (KNU), Daegu, South Korea, in 2021,
where he is currently pursuing the M.S. degree
with the Intelligent 3-Dimensional Very Large Scale
Integrated Circuits (I3D VLSI) Laboratory.
His research interests include the advanced PDK
development in 5nm/3nm and strategies for imple-
menting in-memory processing.
Sin-Hyung Lee received the B.S. degree in elec-
trical engineering from Seoul National University,
South Korea, in 2013, and the Ph.D. degree from
the School of Electrical and Computer Engineering,
Seoul National University, in 2019.
He joined the School of Electronics Engineer-
ing, Kyungpook National University (KNU), Daegu,
South Korea, as an Assistant Professor, in 2020.
His current research interests include neuromorphic
devices, next-generation memory systems, organic
electronics, and light-emitting devices.
Taigon Song (Member, IEEE) received the B.S.
degree in electrical engineering from Yonsei Uni-
versity, Seoul, South Korea, in 2007, the M.S.
degree in electrical engineering from the Korea
Advanced Institute of Science and Technology
(KAIST), Daejeon, South Korea, in 2009, and the
Ph.D. degree from the School of Electrical and Com-
puter Engineering, Georgia Institute of Technology,
Atlanta, GA, USA, in 2015.
He joined the School of Electronics Engineer-
ing, Kyungpook National University (KNU), Daegu,
South Korea, as an Assistant Professor, in 2019. Prior to joining KNU,
he was a Senior Research and Development Engineer at Synopsys Inc. His
research interests include modeling, design, and analysis in the advanced VLSI
technologies, including 3D integrated circuits (3D ICs) and gate-all-around
FETs (GAAFETs).