Professional Documents
Culture Documents
Chapter 1 Digital Design Review
Chapter 1 Digital Design Review
Binh Tran-Thanh
1 / 26
Outline
Technology Tradeoffs
Full-Custom
Market Volume IC
to Amortize
Standard Cells
Time to Prototype
FPGAs, Gate
Arrays
PLDs
2 / 26
Outline
Design Methodology
Simulation /
Post-Synthesis Verify Physical and
Functional
Design Validation Electrical Design Rules
4 Verification 8 12
Verilog-based
3 / 26
Outline
a y1
Combinational
b y2
Combinational logic: Logic
The outputs at any time, t,
c y3
are a function of only the
inputs at time t
Sequential logic:
a y1
The outputs at time t are a Sequential
function of the inputs at time b y2
Circuit
t and the outputs at time y3
t-1
4 / 26
Outline
Transistor
nMos
S G=0 G=1
S S
G
OFF ON
D D D
pMos
S G=0 G=1
S S
G
ON OFF
D D D
5 / 26
Outline
CMOS Technology
pMos
Pull-up
network
Complementary metal-oxide
semiconductor Input Output
VDD
A
Y
A Y A B
Y
B
GND
Inverter NAND gate NOR gate
6 / 26
Outline
g1 g1 g2
0 0 1 1 0 0 0 1 1 0 1 1
b
b b b b
g2 0 1 0 1 ON ON ON OFF
b b b b b
ON OFF OFF OFF 7 / 26
Outline
Y
CMOS gate’s output is always either 0 or 1 A
For example: NAND
Y=0 if and only if both inputs are 1 B
Y=1 if and only at least one input is 0
pMos transistors are parallel while nMos transistors are serial
The “Conduction Complements” rule
The pull-up network always complements the pull-down network
Parallel → Serial, Serial → Parallel
8 / 26
Outline
CMOS Inverter
VDD
A Y
0
1
A Y
A Y
GND
9 / 26
Outline
CMOS Inverter
VDD
A Y
0 1
ON
1
A=0 Y=1
A Y OFF
GND
10 / 26
Outline
CMOS Inverter
VDD
A
0
Y
1
OFF
1 0
A=1 Y=0
A Y ON
GND
11 / 26
Outline
A B Y
0
0
0
1 Y
1 0
1 1 A
B
12 / 26
Outline
A B Y ON ON
0 0 1
0 1 Y=1
1 0 A=0
1 1 OFF
B=0
OFF
13 / 26
Outline
A B Y
OFF ON
0 0 1
0 1 1 Y=1
1 0
A=0
1 1 OFF
B=1
ON
14 / 26
Outline
A B Y
ON OFF
0 0 1
0 1 1 Y=1
1 0 1
A=1
1 1 ON
B=0
OFF
15 / 26
Outline
A B Y
0 0 1 OFF OFF
0 1 1
1 0 1
Y=0
1 1 0 A=1
ON
B=1
ON
16 / 26
Outline
A B Y
0 0 1
A
0 1 0
1
1
0
1
0
0
B
Y
17 / 26
Outline
Y
A
B
C
18 / 26
Outline
Example
Using the CMOS Technology, draw transistor structure of a 4-input NOR
gate
A
B
C
D
Y
19 / 26
Outline
Example 2 (Homework)
Using the CMOS Technology, draw transistor structure of a 4-input NAND
gate
20 / 26
Outline
Compound Gates
21 / 26
Outline
Example: AOI22
Y = (A • B) + (C • D)
A C A C
B D B D
(a) (b)
C D
A B C D
A B
(c)
(d)
C D
A
A B
B
Y Y
C
A C
D
B D
(f)
(e)
22 / 26
Outline
AOI22
A
B 4 2
4 2 2 Y
C
D 4 2
OR
AND
23 / 26
Outline
Example: O3AI
Y = (A + B + C ) • D
A
B
C D
Y
D
A B C
24 / 26
Outline
Standard Cells
25 / 26
Outline
FPGAs
”Programmable” hardware
Use small memories as truth tables of functions
Decompose circuit into these blocks
Connect using programmable routing
SRAM bits control functionality
FPGA Tiles P1
P2
P P3 OUT
P4
P5
P6
P7
P8
I1 I2 I3
26 / 26