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-- Company:
-- Engineer:
--
-- Create Date: 23:01:00 11/24/2011
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
Port ( ALU_A : in STD_LOGIC_VECTOR (7 downto 0);
ALU_B : in STD_LOGIC_VECTOR (7 downto 0);
ALU_select : in STD_LOGIC_VECTOR (2 downto 0);
Fun_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end ALU;

architecture Behavioral of ALU is

begin

Fun_out <= ALU_A + ALU_B when ALU_select = "000"

else ALU_A - ALU_B when ALU_select = "001"
else ALU_A AND ALU_B when ALU_select = "010"
else ALU_A OR ALU_B when ALU_select = "011"
else ALU_A NOR ALU_B when ALU_select = "100"
else ALU_A XOR ALU_B when ALU_select = "101"
else ALU_A NAND ALU_B when ALU_select = "110"
else ALU_A XNOR ALU_B when ALU_select = "111"
else "ZZZZZZZZ";

end Behavioral;