2

Table of Contents
Introduction ..................................................................................................................................... 1
1.1 Seismic Sensor overview ...................................................................................................... 3
Sensor Types ............................................................................................................................... 3
Geophones................................................................................................................................... 3
Accelerometers ............................................................................................................................ 4
1.2 Block diagram Seismic Sensor System................................................................................. 5
Motivation and Organization of Thesis .......................................................................................... 6
Data Converters for Seismic Sensors .............................................................................................. 8
2.1 Basic ADC properties ........................................................................................................... 9
2.2 Errors associated with ADC................................................................................................ 10
2.3 Multi-channel ADC ............................................................................................................ 13
2.4 Oversampling for improvement of the dynamic range ....................................................... 13
2.5 ADC architectures in comparison ....................................................................................... 14
Conclusion ................................................................................................................................ 16
2.6. Advantages of the SAR ADC ............................................................................................ 17
2.7. Types of SAR ADC ........................................................................................................... 18
2.8. Specifications of ADC ....................................................................................................... 20
Single Ended Charge-Redistribution SAR ADC .......................................................................... 22
Fully Differential SAR ADC ........................................................................................................ 33
5.1 Advantages of Differential ADC over Single ended ADC ................................................. 33
5.2 Architecture of Differential ADC ....................................................................................... 35
5.3 Architecture of Dynamic Comparator ................................................................................ 42
1
5.4 Architecture of Synchronous Shift Register ....................................................................... 47
5.5 Architecture of DAC Control Logic ................................................................................... 51
5.6 Architecture of Delay Buffer .............................................................................................. 56
5.7 Architecture of Track and Hold .......................................................................................... 57
5.8 Architecture of Capacitive DAC ......................................................................................... 63
Multi-Channel Fully Differential SAR ADC ................................................................................ 68
Summary of Timing Diagram: .................................................................................................. 71
6.1 Architecture of Single-Ended to Differential Converter ................................................ 72
6.2 Architecture of Analog Multiplexer.................................................................................... 79
6.3 Architecture of 14-bit De-Multiplexer ................................................................................ 83
6.4 Architecture of 14-bit Multiplexer ...................................................................................... 87
6.5 Architecture of 14-bit Output Register ............................................................................... 90
6.6 Architecture of Clock Network ........................................................................................... 93
6.7 Architecture of Register Control ......................................................................................... 98
Validation of Fully Differential SAR ADC ................................................................................ 102
7.1 The Mathematical relationships between SINAD, SNR, AND THD ............................... 107
Conclusion and Future Work ...................................................................................................... 111
References ................................................................................................................................... 113
2
List of Figure Page no
Figure 1.1. Original trace and ground displacement of earthquake signal. 2
Figure 1.2. (a) Sea seismic Sensor (b) Geophone 4
Figure 1.3. Block diagram of Seismic Sensor System 5
Figure 3.1. The analog to the digital conversion process. 8
Figure 3.2. Offset error. 11
Figure 3.3. Gain error. 11
Figure 3.4. Full scale error. 12
Figure 3.5. Differential non-linearity. 12
Figure 3.6. Missing code. 13
Figure 3.7. ADC architectures in comparison. 14
Figure 3.8. ADC architectures, applications, resolution and sampling rates. 17
Figure 3.9. (a) Single-Ended Unipolar (b) Single-Ended True Bipolar 18
Figure 3.10. (a) Pseudo-Differential Unipolar (b) Pseudo-Differential Bipolar 19
(c) Pseudo-Differential True Bipolar
Figure 3.11. (a) Fully Differential (b) Fully Differential True Bipolar 20
Figure 4.1. Latch-Up in CMOS Process 24
Figure 4.2. Pin Configuration 25
Figure 4.3. Dummy Layers 27
3
Figure 4.4. Layout with Dummy Layers 28
Figure 4.5. Schematic diagram of 14- bit Single ended SAR ADC 29
Figure 4.6. GDS of 14- bit Single ended SAR ADC 30
Figure 5.1. Conventional Fully Differential SAR ADC 36
Figure 5.2. Fully Differential SAR ADC with Monotonic Switching 36
Figure 5.3. Flow chart of the proposed ADC 37
Figure 5.4. (a) Conventional Switching (b) Monotonic Switching 38
Figure 5.5. (a) Conventional Switching for 3-bit DAC 40
Figure 5.5. (b) Monotonic Switching for 3-bit DAC 41
Figure 5.6. Architecture of Dynamic Comparator 43
Figure 5.7. Schematic diagram of Dynamic Comparator 44
Figure 5.8. Output response of Dynamic Comparator 45
Figure 5.9. Layout of Dynamic Comparator 46
Figure 5.10. Schematic diagram of Transmission Gate based D FF 47
Figure 5.11. Layout of Transmission Gate based D FF 48
Figure 5.12. Pre-Layout waveform of Transmission Gate based D FF 48
Figure 5.13. 14-bit Shift Register using Transmission Gate based D FF 49
Figure 5.14. Schematic diagram of 14-bit Shift Register using Transmission
Gate based D FF 49
Figure 5.15. Layout of 14-bit Shift Register using Transmission Gate based D FF 49
4
Figure 5.16. Pre-Layout of 14-bit Shift Register using Transmission Gate based D FF 50
Figure 5.17. Post-Layout of 14-bit Shift Register using Transmission Gate based D FF 50
Figure 5.18. Post-Layout of 14-bit Shift Register using Transmission Gate based D FF 50
Figure 5.19. 1-bit DAC Control 51
Figure 5.20. Timing diagram of DAC Control 51
Figure 5.21. DAC Control with Switch to control Capacitor 52
Figure 5.22. DAC Control with SAR Logic 52
Figure 5.23. Schematic diagram of 1-bit DAC Control 53
Figure 5.24. Schematic diagram of 14-bit DAC Control 53
Figure 5.25. Layout of 1-bit DAC Control 53
Figure 5.26. Layout of 14-bit DAC Control 54
Figure 5.27. Pre-Layout of 14-bit DAC Control 54
Figure 5.28. Post-Layout of 14-bit DAC Control 54
Figure 5.29. Post-Layout and Pre-Layout comparison of 14-bit DAC Control 55
Figure 5.30. Schematic of Delay Buffer 56
Figure 5.31. Layout of Delay Buffer 56
Figure 5.32. NMOS switch for Sample and Hold 57
Figure 5.33. Track and Hold Concept 58
Figure 5.34. Schematic diagram of Track and Hold 59
Figure 5.35. Non-Overlapping Clock 60
Figure 5.36. Pre-layout Simulation of Track and Hold 60
Figure 5.37. Layout of Track and Hold 61
Figure 5.38. Post-layout Simulation of Track and Hold 62
5
Figure 5.39. Comparison of Pre-layout simulation and Post-layout simulation of 62
Track and Hold
Figure 5.40. DAC structure with switches 64
Figure 5.41. (a) Unit Capacitor of 20fF (b) 40fF using two 20fF 65
Figure 5.42. Placement Strategy of DAC Array 66
Figure 5.43. Schematic diagram of 14-bit Fully Differential SAR ADC 67
Figure 6.1. Block diagram of Multichannel ADC 69
Figure 6.2. Timing diagram of Multichannel ADC 70
Figure 6.3. (a) Schematic diagram of OPAMP (b) Bias circuit of OPAMP 72
Figure 6.4. Schematic diagram of Inverting Differential Signal generation 73
Figure 6.5. Pre-Layout of Inverting Differential Signal generation 73
Figure 6.6. Layout of Inverting Differential Signal generation 74
Figure 6.7. Post-Layout of Inverting Differential Signal generation 75
Figure 6.8. Post-Layout and Pre-Layout comparison of Inverting Differential 75
Signal generation
Figure 6.9. Schematic diagram of Non-Inverting Differential Signal generation 76
Figure 6.10. Pre-Layout of Non-Inver ting Differential Signal generation 76
Figure 6.11. Layout of Non-Inverting Differential Signal generation 77
Figure 6.12. Post-Layout of Non-Inverting Differential Signal generation 78
Figure 6.13. Post-Layout and Pre-Layout comparison of Non-Inverting Differential 78
Signal generation
Figure 6.14. Schematic of Analog Multiplexer 79
6
Figure 6.15. Schematic of Analog Multiplexer with Control C0 and C1 79
Figure 6.16. Layout of Analog Multiplexer Array 80
Figure 6.17. Pre-Layout of Analog Multiplexer Array 81
Figure 6.18. Post-Layout of Analog Multiplexer Array 81
Figure 6.19. Post-Layout and Pre-layout comparison of Analog Multiplexer Array 82
Figure 6.20. Schematic of 1-bit De-Mux 83
Figure 6.21. Schematic of 14-bit De-Mux 83
Figure 6.22. Layout of 1-bit De-Mux 84
Figure 6.23. Pre-Layout of 1-bit De-Mux 84
Figure 6.25. Post-Layout of 1-bit De-Mux 86
Figure 6.26. Post-Layout and Pre-Layout comparison of 1-bit De-Mux 86
Figure 6.27. Schematic of 1-bit Mux 87
Figure 6.28. Schematic of 14-bit Mux 87
Figure 6.29. Layout of 1-bit Mux 88
Figure 6.30. Pre-Layout of 1-bit De-Mux 88
Figure 6.31. Post-Layout of 1-bit De-Mux 89
Figure 6.32. Post-Layout and Pre-Layout comparison of 1-bit De-Mux 89
Figure 6.34. Schematic of 14-bit Output Register 90
7
Figure 6.35. Pre-Layout of 14-bit Output Register 90
Figure 6.36. Post-Layout of 14-bit Output Register 91
Figure 6.37. Post-Layout and Pre-Layout comparison of 14-bit Output Register 91
Figure 6.38. Layout of 14-bit Output Register 92
Figure 6.39. Block diagram of clock network 93
Figure 6.40. Schematic of Counter reset to ‘48’ 94
Figure 6.41. Layout of Counter reset to ‘48’ 94
Figure 6.42. Pre-Layout waveform of Counter reset to ‘48’ 94
Figure 6.43. Schematic of 6-64 Decoder 95
Figure 6.44. Layout of 6-64 Decoder 95
Figure 6.45. Pre-Layout of 6-64 Decoder 95
Figure 6.46. Schematic of Crossbar architecture using NMOS 96
Figure 6.47. Layout of ROM 96
Figure 6.48. Layout of Clock Control Unit developed using SPC 96
Figure 6.49. Pre-Layout of Clock Control Unit developed using SPC 97
Figure 6.50. Post-Layout of Clock Control Unit developed using SPC 97
Figure 6.51 Post-Layout and Pre-Layout comparison of Clock Control Unit 97
developed using SPC
Figure 6.52. Schematic of Register Control 98
Figure 6.53. Layout of Register Control 99
8
Figure 6.54. Pre- Layout waveform of Register Control 100
Figure 6.55. Post- Layout waveform of Register Control 100
Figure 6.56. Pre- Layout and Post- Layout comparison of Register Control 101
Figure 7.1. Output waveform of 14-bit ADC with Vip=0.825mV and Vin=0.975mV 103
Figure 7.2. Output waveform of 14-bit ADC with Vip=0.900062V and Vin=0.899938V 103
Figure 7.3. Reconstructed analog signal after an ideal DAC for input frequency 500Hz
and Sampling frequency 31.3 KHz 104
Figure 7.4. FFT of a reconstructed signal of ADC 106
Figure 7.5. FFT diagram of ADC with input frequency 500 Hz and Sampling 30 KHz 109
Figure 7.6. FFT diagram of ADC with input frequency 100 Hz and Sampling 5 KHz 109
Figure 7.7. Comparison of performance parameter with Sampling frequency 110
Figure 7.8. Comparison of performance parameter with Input frequency 110
9
Introduction
Chapter I
Introduction
Seismology would be a very different science without instruments. The real big advances
in seismology happened from around 1900 and onwards and were mainly due to advancement in
making more sensitive seismographs and devising timing systems so that earthquakes could be
located. Later, the importance accurate measurement of the true ground motion became evident
for studying seismic wave attenuation, and the Richter magnitude scale depends on being able to
calculate the ground displacement from our recorded seismogram (Figure 1.1).
The ability to do earthquake location and calculate magnitude immediately brings us into
two basic requirements of instrumentation: keeping accurate time and determining the frequency
dependent relation between the measurement and the real ground motion. Seismologists tend to
take their data for granted, hoping that the black boxes of seismographs and processing software
will take care of all the nasty problems to just give the correct ground motion (Figure 1.1), much
like driving a car and not worrying too much of how it works. But cars stop or malfunction and so
seismographs, so a basic understanding of seismic instrumentation is essential, even for the
seismologist who is never going to turn a knob on an instrument. Like getting some data with a
few instrumental constants and trying to figure out how it can be used to calculate the true ground
motion.
Seismologists tend to take their data for granted, hoping that the black boxes of
seismographs and processing software will take care of all the nasty problems to just give the
correct ground motion (Figure 1.1), much like driving a car and not worrying too much of how it
works. But cars stop or malfunction and so seismographs, so a basic understanding of seismic
instrumentation is essential, even for the seismologist who is never going to turn a knob on an
instrument. Like getting some data with a few instrumental constants and trying to figure out how
it can be used to calculate the true ground motion.
1
Introduction
Instrumentation is not just a topic for seismologists, since most equipment is in fact
installed and maintained by non-seismologists, so this group of professionals has just as much a
need for information on instrumentation.
Figure 1.1. The top trace shows the original digitally recorded signal from a magnitude 3 ea rthquake
recorded at a distance of 120 km. The maximum amplitude is just a number (called counts). The
bottom trace sho ws the signal converted to true ground displacement in nm from which the
magnitude can be calculated. The distance to the earthquake is p roportional to the arrival time
difference between the S -wave and P-wave, so having 3 stations makes it possible to locate the
earthquake. The seismometer is a 1 Hz sensor with velocity output. [15]
There have been numerous publications on instrumental topics in seismology, with very
special emphasis on particular topics, but few general textbooks. A general overview was made by
Lee and Stewart (1981), which, on the instrumental side, mainly dealt with microearthquake
networks. The old Manual of Seismological Observatory Practice (MSOP) (Wilmore, 1979) dealt
with all the classical analog seismographs but is partly outdated now. The New Manual of
Seismological Observatory Practice (NMSOP, Borman, 2002)) is the most up to date book on
seismic instruments.
The range of amplitudes is very large. The natural background noise, highly frequency
dependent, sets the limit for the smallest amplitudes we can measure, which is typically 1 nm
displacement at 1 Hz (Chapter 2), while the largest displacement is in the order of 1 m. The band
of frequencies also has a large range, from 10-5 to 1000 Hz (Table 1). The challenge is therefore
2
Introduction
to construct seismic instruments, both sensors, and recorders, which cover at least part of this large
frequency and dynamic range.
Table 1.1 Typical frequencies generated by different seismic sources
1.1 Seismic Sensor overview
Seismic sensors are devices used to measure seismic vibrations by converting ground
motion into a measurable electronic signal. As the signal is analog in nature, sensors must be linked
to a data acquisition unit to convert its output into a digital format that can be read by computers.
Some sensors contain Smart electronics to provide the sensor type, serial number and orientation
(dip and roll) in inclined boreholes.
Sensor Types
Seismic sensors are classified according to what form of ground motion it measures,
namely ground velocity (geophone) or ground acceleration (accelerometer and FBA); the number
of sense axes the sensor has and whether the sensor is deployed in a borehole or against a rock
surface. Each sensor type has different advantages in terms of amplitude range, frequency range,
reliability, and cost. A seismic network can be based on any combination of geophone,
accelerometer and force balance accelerometers, in uni and tri-axial combinations. The tri-axial
configuration affords the most accurate estimates of source parameters.
Geophones
Geophones are usually the sensor of choice in most mining applications, because of the
low cost, large bandwidth, and excellent reliability. We have different kinds of geophones
available in the market like some with natural frequencies of 5.5 Hz and other with 14 Hz. The 5.5
3
Introduction
Hz geophone has a usable frequency bandwidth of between 3 Hz and 2000 Hz but must be installed
to within two degrees of its pre-set orientation with respect to the vertical. The 14 Hz geophone is
omnidirectional and can be installed at any angle, with a usable frequency bandwidth of between
8 Hz (-3dB point) and 2000 Hz.
(a) (b)
Figure 1.2. (a) Seismic Sensor (b) Geophone
Accelerometers
Accelerometers are usually used where precision records of smaller (high-frequency)

seismic events are required. Some companies like IMS routinely manufactures two kinds of
accelerometers: a 2.3 kHz low-noise version with a useful bandwidth between 0.7 and 2,300 Hz,
and a 25-kHz high-frequency version with a useful bandwidth between 2 and 25,000 Hz.
4
Introduction
1.2 Block diagram Seismic Sensor System
Figure 1.3. Block diagram of Seismic Sensor System
5
Motivation and Organization of Thesis
Chapter II
The 21st century is a technological era dominated by electronic gadgets and sensors.
Electronics has entered every aspect of human life. It is used to exploit the natural resources of the
world for our benefit. It is also used to protect human lives from the wrath of nature. Electronics
technology is now much improved to provide us with sufficient time to escape from natural
calamities like storms, floods, volcanic eruptions, earthquakes etc. Out of these disasters,
earthquakes have been significantly more devastating. In the past few years, the region of south-
Asia has been struck by several earthquakes of different magnitudes. Recent Nepal earthquake
(2015) has ravaged the poor country. In addition to a material loss of around 10 billion rupees,
9000 lives were lost, and 22000 people were injured [1]. In India, the 2001 Gujarat earthquake
wreaked similar havoc. To prevent the loss of human lives, electronics technology can be used to
provide a heads-up for an impending earthquake. Earthquake sensing technology is already in use
in Japanese Shinkansen, which senses the fast traveling primary waves of an earthquake to provide
a window of 5-10 minutes before the actual earthquake hits (Secondary waves). India is
implementing a bullet train project between Mumbai and Ahmedabad where this technology can
be of vital assistance in providing safety for rail passengers. India has several earthquake-prone
zones in Kashmir, Gujarat, Himachal Pradesh, Uttarakhand and North-eastern states, where this
technology can be used. Conventionally, earthquakes are measured by seismographs. But, these
apparatuses are not capable of providing a sufficient warning. This is where electronics-based
earthquake sensing technology can be of great help. The earthquake ground vibrations are
converted into electrical signals and subsequently analyzed. The analog electrical signals
generated by the ground vibrations need to be converted to digital form for processing. For this,
an analog to digital converter (ADC) circuit is necessary. The ADC circuit design in this work is
tailor-made to a suite for earthquake sensing and integrated onto a silicon chip for better
performance, reliability, accuracy, less environmental interference and less power consumption.
6
The rest of the thesis has been organized as follows:
Chapter III discusses different architectures of Data Converters for Seismic Sensors. Also, some
basic property of Analog to Digital Conversion is described. Different errors associated with ADC
has also been discussed in this chapter.
Chapter IV discusses Single Ended SAR ADC. This is not designed by myself. I have done the
Layout integration and created the GDS itself.
Chapter V discusses Fully Differential SAR ADC. The working principle of all the components
has been discussed in this chapter. The Layout of each of the component has been done and Post
layout has been done for each component.
Chapter VI discusses Multichannel Channel Fully Differential ADC where the requirements of
Multichannel ADC has been discussed. All the blocks needed to design the Multichannel has been
discussed in this chapter. The clock control unit has been developed using procedure control to
reduce the complexity.
Chapter VII discussed about a few testing results on Fully Differential SAR ADC. FFT results and
variation of some performance quantities with the sampling frequency and input frequency has
been given in this chapter.
Chapter VIII Concludes the work and discussed the issues of the design. The future work has been
discussed in this Chapter.
7
Data Converters for Seismic Sensors
Chapter III
Since the computers are the heart of all data processing, we must convert our analog
signals to numbers. The process of converting a continuous analog signal to a series of numbers
representing the signal at discrete intervals is called analog to digital conversion and is performed
with analog to digital converters (ADC). Figure 5.1 shows a signal, where the amplitude is
measured at regular intervals Δt. In its simplest form, we could simply envisage measuring the
amplitude of a slowly changing signal with an analog voltmeter and write down the numbers.
Alternatively, if we have an analog plotted signal like in Figure 5.1, we just measure the amplitudes
with a ruler and enter the numbers into a computer.
Figure 3.1. The analog to the digital conversion process. The arrows sho w the location and values
(amplitudes) of the samples
The process of analog-digital conversion involves two steps: First, the signal is sampled at
discrete time intervals, then each sample is evaluated in terms of a number (usually an integer, but
in any case, with finite resolution) and output in form of a code.
This process will introduce errors into the data and limits the information in them, simply
because we replace a continuously varying signal, which can have any value between two limits,
with a discrete set of points - information between the points is lost- and with a limited number of
8
possible values (quantization). This creates errors in both the amplitude and frequency content and
much of the efforts in improving the ADC process are related to minimizing these errors.
2.1 Basic ADC properties
Some of the basic properties of ADC have to have in mind when continuing the description
of common ADC’s:
Resolution: The smallest step that can be detected. The smallest step is the resolution
corresponding to one change of the least significant bit (LSB, the rightmost bit). The higher the
resolution, the smaller a number is given. Most ADC’s have an internal noise higher than one
count: In this case, the effective resolution is limited by the number of noise-free bits, rather than
the total bits number. For instance, one count corresponds to 0.3µV in a 24 bit ADC with full-scale
of ±2.5V, but it may have a noise of 2µV peak-to-peak, and signals under this level may not be
resolved in practice.
Gain: The sensitivity expressed in counts/V which can be derived from resolution. If e.g. the
resolution is 10 µV, the gain would be 1count/(10-5V) = 105 counts/V.
Sample rate: Number of samples acquired per second. For seismology, the usual rates are in the
range 1 to 200 Hz (or, more specifically, samples per second – sps) while for exploration
seismology, sample rates can be more than 1000 Hz. In general, the performance of the ADC
degrades with increasing sample rate.
Maximum input or full-scale (FS): The maximum input for the ADC. Using any higher
input will result in the same output. The maximum input is 1.0 V or in the bipolar mode ±0.5V.
Dynamic range: Defined as the ratio between the largest and smallest value the ADC can give.
In the above example, the dynamic range = 4/1 = 4 or in dB, 20·log(4) = 12 dB. This can be a bit
misleading since both negative and positive numbers are input and the ADC has to work in a
bipolar mode. So the real dynamic range is only half, in this case, 6 dB. However, the dynamic
range given in dB for ADC’s is usually given for the full range.
9
Accuracy: The absolute accuracy is a measure of all error sources. It is defined as the difference
between the input voltage and the voltage representing the output. Ideally, this error should be
±LSB/2 and this is achieved by several low and medium-resolution commercial ADC’s.
Noise level: Number of counts out if the input is zero (subtracting DC offset). Ideally, an ADC
should give out 0 counts if the input is zero.
Conversion time: The minimum time required for a complete conversion. Often it is expressed
by the maximum data rate or sampling frequency. Due the finite time required to complete a
conversion, many converters use as input stage a sample and hold circuit, whose function is to
sample the analog signal before the start of a conversion and hold the converter input constant until
it is complete to avoid conversion errors.
Offset: If the input is zero, the offset is the DC level (the average) of the output. This could also
be called the DC shift of the ADC. There is nearly always some offset, either caused by the ADC
itself or caused by the components connected to the ADC. The ADC might have a possibility of
adjusting the offset by changing some reference voltage. A small offset if of no importance, but
any offset will limit the dynamic range since the ADC will reach its maximum value (positive or
negative) for smaller input values that its nominal full-scale.
2.2 Errors associated with ADC
Offset Error: The offset error is defined as the deviation of the actual ADC’s transfer function
from the perfect ADC’s transfer function at the point of zero to the transition measured in the LSB
bit. When the transition from output value 0 to 1 does not occur at an input value of 0.5LSB, then
we say that there is an offset error. With positive offset errors, the output value is larger than 0
when the input voltage is less than 0.5LSB from below. With negative offset errors, the input value
is larger than 0.5LSB when the first output value transition occurs. The figure shows the transfer
function of an ADC with positive offset error.
10
Figure 3.2. Offset Error
Gain Error: The gain error is defined as the deviation of the last step’s midpoint of the actual
ADC from the last step’s midpoint of the ideal ADC after compensated for offset error. After
compensating for offset errors, applying an input voltage of 0 always give an output value of 0.
However, gain errors cause the actual transfer function slope to deviate from the ideal slope. This
gain error can be measured and compensated for by scaling the output values.
Figure 3.3. Gain Error
Full-scale error: Full-scale error is the deviation of the last transition (full-scale transition) of
the actual ADC from the last transition of the perfect ADC, measured in LSB or volts. The full-
scale error is due to both gain and offset errors.
11
Figure 3.4. Full-Scale Error
Differential non-linearity: Differential non-linearity (DNL) is defined as the maximum and

minimum difference in the step width between actual transfer function and the perfect transfer
function. Non-linearity produces quantization steps with varying widths, some narrower and some
wider.
Figure 3.5. Differential Non-Linearity
Missing code: In the example below, the first code transition (from 000 to 001) is caused by an
input change of 250mV. This is exactly as it should be. The second transition, from 001 to 010,
has an input change that is 1.25LSB, so is too large by 0.25LSB. The input change for the third
transition is exactly the right size. The digital output remains constant when the input voltage
12
changes from 1000mV to 1500mV and the code 100 can never appear at the output. It is missing.
the higher the resolution of the ADC is, the less severe the missing code is.
Figure 3.6. Missing Code
2.3 Multi-channel ADC
The seismic sensor has more than one channel to digitize. For three-component stations,
there are 3, while for telemetric networks or small arrays, there might be up to 100 channels. The
simplest approach is to have one ADC for each channel. However, this might be overkill depending
on the application and in addition quite expensive. The ADC has, in the front, a so-called
multiplexer which connects the ADC to the next analog channel as soon as a conversion is finished.
The input signals are therefore not sampled at the same time and there is a time shift, called skew,
between the channels. If the ADC is fast, the skew might be very small, but in the worst case, the
ADC just has time to take all the samples and the skew is the sample interval divided by the number
of channels. For many applications, like digitizing the signal from a network, skew has no
importance, but in other application where a correlation between the traces will be made like for
arrays or three component stations, the samples should be taken at the same time.
2.4 Oversampling for improvement of the dynamic range
13
The method of oversampling to improve the dynamic range of a digital signal consists of
sampling the signal at a higher rate than desired, low pass filter the signal and resample at a lower
rate. Qualitatively what happens is then that the quantization errors of the individual samples in
the oversampled trace are averaged over neighboring samples by the low pass filter and the
averaged samples, therefore, have more accuracy and consequently a higher dynamic range.
2.5 ADC architectures in comparison
Figure 3.7. compares integrated circuit ADC architectures in terms of resolution and
bandwidth. The attentive reader will see which resolution and frequency range are attainable with
each of the architectures.
Figure 3.7.ADC architectures in comparison
Flash ADC: Flash ADCs (sometimes called parallel ADCs) are the fastest type of ADC, but
have limited resolution, high power dissipation, and relatively large chip size.
Successive Approximation ADC: “The successive approximation ADC is by far the most
popular architecture for data acquisition applications, especially when multiple channels require
input multiplexing. [13] The overall accuracy and linearity of the SAR ADC are determined
primarily by the internal DAC’s characteristics. [13] Switched-capacitor (or charge-redistribution)
14
DACs have become popular in newer CMOS-based SAR ADC, as their accuracy and linearity are
primarily determined by high-accuracy photolithography.” [Kester2005-2]. As SAR ADCs do not
have latency, they outperform Pipelined and Sigma-Delta ADCs in the case of single-shot
measurements or repeated ADC power-up and -down cycles. Remember the 14-bit ADC is
powered up for high-accuracy data conversion as soon as activities are observed in a specific area,
then powered down again. The challenge is to build a capacitor array that is at least 14-bit accurate,
which should be possible in SCL 0.18µm CMOS technology, as a 12-bit accurate capacitor array
has already been realized in a 0.6µm CMOS process, using a special common centroid layout
technique [Promitzer2001]. If a 14-bit accuracy is not achieved, calibration in the digital or analog
domain can be performed. However, the aim is to build a non-calibrating ADC, as calibration
would add a lot of extra circuitry, including a memory. Consequently, the ADC would consume
much more area. Calibration would also introduce a delay at each ADC start-up.
Subranging ADC: Subranging ADCs split the A/D conversion into several steps. For example,
an N-bit conversion could be split into a coarse N1-bit conversion and a fine N2-bit conversion,
where N1+N2=N. Each sub- conversion is carried out in a separate stage. Each stage will work
on the residue signal (error signal) of the previous stage. Residue signals are amplified to match
the input range of the next stage. Subranging ADCs always include operational amplifiers.
Subranging ADCs can be pipelined. In a pipelined subranging ADC, all stages work
simultaneously on different samples. A stage can be repeated in time instead of space. In a
cyclic/algorithmic/recirculating ADC, the residue signal is amplified and fed back to the same
stage several times.
Pipelined ADC: Pipelined ADCs are used for high-frequency applications. The critical
delay time of each stage diminishes, as it performs only a part of the conversion, which allows
increasing the frequency. However, to convert a sample, its residue signal needs to propagate
through the whole line of stages, which introduces the famous pipeline delay or latency. Due to
latency, the pipelined ADC architecture is not appropriate for single-shot operation or repeated
ADC start-up and shut-down cycles. However, a pipelined ADC is well suited for continuous data
conversion.
Cyclic/Algorithmic /Recirculating ADC: Different authors use different terminology to

refer to the same idea: the residue signal is recirculated several times through a single stage. Rudy
15
van de Plassche refers to it as Cyclic or Algorithmic [Plassche2003], while Walt Kester refers to
it as Recirculating [Kester2005-1]. This architecture can be adapted to achieve small area in
applications where speed is not critical. Cyclic ADC necessitates an operational amplifier.
Folding ADC: Folding ADCs have limited resolution, in general, lower than 10 bits
[Pelgrom2007].
Sigma-Delta ADC: The Sigma-Delta ADC architecture is one of the most popular high-
resolution medium-to-low-speed ADC architectures in use today. The Sigma-Delta ADC
architecture is typically used in applications requiring resolutions from 12 to 24 bits [Kester2005-
2]. A Sigma-Delta ADC contains very simple analog electronics (a comparator, voltage reference,
a switch and one or more integrators and analog summing circuits), and quite complex digital
computational circuitry [Kester2005-1]. Thus, requirements placed on the analog circuitry are
relaxed at the expense of more complicated digital circuitry, which becomes a more desirable
trade-off for modern submicron technologies [Johns1997].
High resolution, together with on-chip programmable-gain amplifiers (PGAs) allows direct
digitization of small output voltages of sensors, requiring no instrumentation amplifier. Sigma-
Delta ADCs offer therefore an attractive alternative to traditional approaches using an
instrumentation amplifier and a SAR ADC [Kester2005-2].
Sigma-Delta ADCs contain as building blocks a digital filter and decimator. The digital filter does
introduce inherent pipeline delay. Consequently, the Sigma-Delta ADC cannot be operated in a
single- shot or burst mode [Kester2005-2].
Conclusion
In conclusion, any of Counting, Successive Approximation, Pipelined or Sigma-Delta ADC

architectures could be used for converting 3 channels with 14-bit resolution. The Folding and
Flash ADC architectures are not taken into consideration because they hardly reach a 14-bit
resolution. The Counting ADC architecture can be excluded also because it would require large
no. of ADCs operating in parallel, which means an excessively big silicon area.
From the remaining Successive Approximation, Pipeline and Sigma-Delta ADC

architectures, none has an obvious advantage at first sight. However, the Successive
16
Approximation ADC architecture has been used extensively in multiplexed data acquisition
systems which are our application. Due to its popularity, the Pipelined ADC is taken as
representative of all Subranging ADCs.
Sigma-Delta ADC architecture is typical for precision industrial measurement as well as

voiceband and audio applications. Finally, the pipelined ADC architecture is most convenient for
high-speed applications like instrumentation, video, radar, communications and consumer
electronics [Kester2005-2]. Resolution versus sampling rate is displayed in Figure 3-2 for the
three remaining ADC architectures, along with their typical applications. Section 3.2 lists further
arguments in favor of the Successive Approximation ADC architecture.
Figure 3.8. ADC architectures, applications, resolution and sampling rates.
2.6. Advantages of the SAR ADC
❖ Very simple principle. SAR ADCs implement the binary search algorithm.
❖ Low power consumption. A SAR ADC does not contain an operational amplifier. operational
amplifiers are generally power-hungry. The SAR ADC contains solely a comparator;
comparators consume much less power than operational amplifiers. Pipelined and Sigma-
Delta ADC contains power-hungry operational amplifiers. From SAR, Pipelined, and Sigma-
Delta ADCs, the SAR ADC is most likely low-power.
17
❖ No pipeline delay (latency). In a pipelined ADC, the pipeline delay is a multiple of the
sampling clock period. For low sampling frequencies, there will be a considerable latency.
The SAR ADC can use an internal clock that is independent of (and – if desired – much faster
than) the sampling clock; output codes can thus be delivered with a delay negligible with
respect to sampling clock period. Closing the loop requires that ADC and DAC have no
latency, a further argument in favor of the SAR ADC.
2.7. Types of SAR ADC
Single-Ended Inputs: An ADC with single-ended inputs digitizes the analog input voltage
relative to the ground. Single-ended inputs simplify ADC driver requirements; reduce complexity
and lower power dissipation in the signal chain. Single-ended inputs can either be unipolar or
bipolar, where the analog input on a single-ended unipolar ADC swings only above GND (0V to
VFS, where VFS is the full-scale input voltage that is determined by a reference voltage) (Figure
3.9 (a)) and the analog input on a single-ended bipolar ADC also called true bipolar, swings above
or below GND (±VFS) (Figure 3.9 (b)).
(a) (b)
Figure 3.9. (a) Single-Ended Unipolar(b) Single-Ended True Bipolar
Pseudo-Differential Inputs: An ADC with pseudo-differential inputs digitizes the differential

analog input voltage (IN+– IN–) over a limited range. The IN+ Input has the actual analog input
signal, while the IN–input has a restricted range. A pseudo-differential unipolar ADC digitizes the
differential analog input voltage (IN+ – IN–) over a span of 0V to VFS. In this range, a single-
18
ended unipolar input signal, driven on the IN+ pin, is measured with respect to the signal ground
reference level, driven on the IN–pin. The IN+ pin is allowed to swing from GND to VFS, while
the IN–pin is restricted to around GND ± 100mV (Figure 3.10 (a)).
A pseudo-differential bipolar ADC digitizes the differential analog input voltage (IN+ – IN–) over
a span of ± VFS/2 n this range, a single-ended bipolar input signal, driven on the IN+ pin, is
measured with respect to the signal mid-scale reference level, driven on the IN–pin. The IN+ pin
is allowed to swing from GND to VFS, while the IN– pin is restricted to around VFS/2 ±
100mV(Figure 3.10 (b)).
A pseudo-differential true bipolar ADC digitizes the differential analog input voltage (IN+– IN–)
over a span of ±VFS. In this range, a true bipolar input signal, driven on the IN+ pin, is measured
with respect to the signal ground reference level, driven on the IN–pin. The IN+ pin is allowed to
swing above or below GND to ±VFS, while the IN–pin is restricted to around GND ± 100mV
(Figure 3.10 (c)).
Pseudo-differential inputs help separate signal ground from the ADC ground, allowing small
common-mode voltages to be canceled. They also allow single-ended input signals that are
referenced to ADC ground. Pseudo-differential ADCs are ideal for applications that require DC
common-mode voltage rejection, for single-ended input signals and for applications that do not
want the complexity of differential drivers. Pseudo-differential inputs simplify the ADC driver
requirement; reduce complexity and lower power dissipation in the signal chain.
(a) (b) (c)
Figure 3.10.(a) Pseudo-Differential Unipolar (b) Pseudo-Differential Bipolar (c) Pseudo -

Differential True Bipolar
19
Fully-Differential Inputs: An ADC with fully-differential inputs digitizes the differential

analog input voltage (IN+– IN–) over a span of ±VFS. In this range, the IN+ and IN– pins should
be driven 180º out-of-phase with respect to each other, centered on a fixed common mode voltage,
for example, VREF/2 ±50mV. In most fully-differential ADCs, both the IN+ and IN–pins are
allowed to swing from GND to VFS (Figure 3.11 (a)), while in fully-differential true bipolar
ADCs, both the IN+ and IN–pins are allowed to swing above or below GND to ±VFS (Figure 3.11
(b)). Fully-differential inputs offer wider dynamic range and better SNR performance over single-
ended or pseudo-differential inputs. Fully differential ADCs are ideal for applications that require
the highest performance.
(a) (b)
Figure 3.11.(a) Fully Differential (b) Fully Differential True Bipolar
2.8. Specifications of ADC
The analog input range of the14-bit ADC is [109uV, 1.8V]. Assuming a Comparator gain
of 86dB full analog input range is used. The ADC will work on voltage signals, and neither on
current nor on charge signals. The length and width of the ADC are not specified. As most
implantable chips are battery-powered, Low Power ADC is required.
20
The ADC must have a Differential Non-Linearity smaller than 1(DNL<1) and an Integral Non-
Linearity smaller than 1.5(INL<1.5).
Table 2.1Summarizes the elaborated specifications for the 14 -bit ADC
ADC Specifications
Topology SAR
Technology 180nm SCL
Supply voltage: 1.8 V
Resolution: 14 bits
ENOB targeted: 12 bits
Permissible Noise: <50 µV p-p
SAR clock 200 KHz
Vin 0 - 1.8 V
LSB: 109 µV
Sample rate: 5KHz
Dynamic Range: 86 dB
21
Single Ended Charge-Redistribution SAR ADC
CHAPTER IV
SAR ADC employs a successive approximation algorithm to convert analog input to a

digital code successively. In other words, one bit is determined in each clock cycle using binary
search algorithm.
To investigate the operation of the SAR ADC, consider a 4-bit ADC. In the first clock
cycle DAC voltage is set to half of Vref by setting the code to 1000, then the input voltage is
compared to Vref /2 and based on the comparison result, MSB is defined. If Vin >Vref /2 the MSB
will not be changed and will remain at one, otherwise the MSB is reset to zero. So here MSB (D3)
remains at one. In the next clock cycle the DAC input is set to 1100 and again Vin is compared to
3/4Vref. D2 retains its value since Vin>3/4Vref. For the next bit, the DAC input is set to 1110.
Based on the comparison, D1 is reset to zero since Vin< 7/8 Vref and finally, for defining LSB,
the DAC input is set to 1101. D0 is one because of Vin> 15/16 Vref. Thus, the analog input is
converted to the digital code 1101 in four clock cycles. Successive Approximation Register (SAR)
control logic determines each bit successively. The SAR register contains N bit for an N-bit ADC.
There are 3 possibilities for each bit, it can be set to ‘1’, reset to ‘0’ or keeps its value.
In the first step, MSB is set to ‘1’ and other bits are reset to ‘0’, the digital word is converted
to the analog value through DAC. The analog signal at the output of the DAC is inserted to the
input of the comparator and is compared to the sampled input. Based on the comparator result, the
SAR controller defines the MSB value. If the input is higher than the output of the DAC, the MSB
remains at ‘1’, otherwise, it is reset to ‘0’. The rest of bits are determined in the same manner. In
the last cycle, the converted digital word is stored. Therefore, an N-bit SAR ADC takes N+2 clock
cycles to perform a conversion.
22
An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a

microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor
material, normally silicon. The integration of large numbers of tiny transistors into a small chip
results in circuits that are orders of magnitude smaller, cheaper, and faster than those constructed
of discrete electronic components. The IC's mass production capability, reliability and building-
block approach to circuit design has ensured the rapid adoption of standardized ICs in place of
designs using discrete transistors. ICs are now used in virtually all electronic equipment and have
revolutionized the world of electronics. Computers, mobile phones, and other digital home
appliances are now inextricable parts of the structure of modern societies.
Here, individually each component’s schematic and layout is required for designing our
required SAR ADC. Now all the components must be placed at their corresponding position and
connection among them have to be done for both in schematic and layout. Placement and routing
should be done in such a way that performance of the circuits should not be hampered.
Before starting of integration, all the individual block’s DRC, LVS, and PEX must be
checked. Though some density related DRC may be present in the individual blocks. But in case
of LVS and PEX there should not be any warning or any error. These are the main prerequisites
for integration of an IC.
Now, there are two modules of integration,
1) Schematic integration.
2) Layout integration
Schematic Integration: All the component necessary for designing the ADC IC are
instantiated according to the proper design constraints. All the corresponding blocks as per as the
block diagram of SAR ADC are connected by wires. A similar thing has to be done in layout
window.
Layout integration: - Integration of individual layout is not as simple as we do in the

schematic. There are several steps which we have to follow are given below,
1) Guard ring to all the components.
2) IC framework.
23
3) Placement, Routing and Buffer Insertion.
Guard Ring for all individual components: Basically, the guard ring is done for two
purposes. One is for isolating all the components from other components. If any disturbance
happens in any components that will not affect nearby component. Another advantage is that there
are some taps within that guard rings. These taps will prevent latch-up the phenomenon that may
happen in any CMOS circuit. Due to PMOS and NMOS structure are present simultaneously in
any CMOS circuit hence, there two virtual PNP and NPN transistor is formed. Collector and base
of these two transistors are connected which provide a positive feedback path and chances of VDD
and GND are shorted. If no of taps is increased in guard-ring then Rwell and Rsub decreased.
Hence, transistors can’t conduct which will prevent latch-up.
Figure 4.1. Latch-Up in CMOS Process
After individual guard-ring, metal guarding has been placed after integrating all the components.
These metal rings provide the shortest connection between VDD and GND pin to those metal
rings. These rings also have normal guard-ring advantages whatever discussed above.
IC framework and Pins Decision: It is the frame where all the layout blocks are placed together.
This frame consists of I/O pads, filler cell, and corner pad. For this design, it is (1682 X 1682)
um^2. Filler cells are primarily non-functional cells used to continue the VDD and VSS rails.
They basically reduce the DRC violations created by the base layers. (N-Well, P-well, P+, and N+)
they also help to maintain the Power Rail connection continuously. I/O pads are used for the pin
24
connections with which external world can be connected. Corner pads don’t have any specific
purpose. These are used just for making the frame in-shape.
As 14 digital output pins, the chip was made for a chip of 28 pins. (7 pins on each side)
Two sides are occupied with output pins from D1-D14. Now, we have three external input pins
out of which two analog input and one digital input. Two analog inputs are connected to S/H block.
Hence, two pins are fixed near to the S/H block. Digital input pin is clock signal which is
connected to timing and control circuit. Hence, it is decided to fix that pin at the bottom left side.
Now VSS pin which provides -1.8V supply to the comparator. So, it is fixed near to the
comparator. Still, 10 pins are left but only two pins are required (VDD and GND). Hence, it is
decided to make 3 VDD pins and 3 GND pins and rest four are no connection pins(NC). There are
some advantages of using multiple VDD and GND pins instead of using a single pin for them.
VDD and GND signal is used in each block. That VDD and GND pins are connected to final
square guard-ring. For multiple VDD and GND, we get better voltage supply throughout the guard-
ring. IR drop will be less for it. Last but not the least no connection pins can be utilized in future
when we use differential ADC where more featured will be incorporated.
Figure 4.2. Pin Configuration
25
Table 4.1. Summarizes the pin type used from SCL 180 nm PDK
Pin types From SCL foundry
Digital output pc3001
Digital inputs Pc3d01
Analog inputs pc3d00
VDD pvdi
Ground pc0i
VSS (negative DC voltage) apv0i
No connection pc3o01
Corner PAD pfrelr
Filler cell Pfeed30000, pfeed10000…
Placement, routing and Buffer Insertion: Now placement of all the components in the
schematic and layout window must be started. During placement, it should be considered to decide
where which blocks need to be placed. Layout of DAC is very large for which it is placed at the
top of our layout frame. Next, S/H block and comparator are placed at the left side (near to input
pins) as an analog input signal and sampling signal connected to it. Now, timing control and pos-
clk block are placed at a middle position from where the distance of SAR, the output register is as
minimum as possible. This timing control block generates SOC, EOC and output register enabling
signal. At last SAR and output, register block is placed.
Layout Integration: In case of the layout by using different metal layers various necessary
components are connected. During routing, it should be kept in mind that the routing path must be
as small as possible. But, after doing proper routing it is realized that the routing paths are
somewhere very large (more than 100um). So, there is a possibility of losing signal levels. Hence,
26
some buffer circuits are placed at a regular distance between long metals to regain the proper signal
strength.
GDSII and Dummy insertion: After completing schematic and layout, it is required to convert
that integrated layout in a binary file which is nothing but GDSII file. GDSII is a database file
format which is the industry standard for data exchange of integrated circuit or IC layout artwork.
It is a binary file format representing planar geometric shapes, text labels, and other information
about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork
to be used in sharing layouts, transferring artwork between different tools, or creating photomasks.
It is the final binary file format that has been created from the Layout which is to be forwarded to
the foundry for the fabrication.
Generating the dummy fill strategy includes dividing a semiconductor design into grids.
Dummy fill strategy extracts the local pattern densities for a semiconductor design for each of the
grids and adds the dummy fill in empty areas of each of the grids. The objects of the dummy fill
pattern are placed to minimize full-chip film thickness variation. The objects of the dummy fill
pattern are placed to minimize full-chip variation in electrical parameters.
Figure 4.3. Dummy Layers
27
Dummy fill structures are placed in the layout to improve thickness and surface
topography uniformity of the manufactured wafer while maintaining the electrical parameters at
the intended or designed values. After the GDS file of dummy, layers has been created. The GDS
file is being translated (only contains the dummy layers). The GDS files are modified to improve
uniformity and electrical performance of the semiconductor device. The layout of the actual circuit
is being instantiated in the dummy layers. This stage defines the complete layout of the IC with
empty regions filled by dummy objects. Now the layout with dummy filled is available to us. Now
the final GDSII file needs to be created which will be used by fabrication lab to fabricate the chip.
Figure 4.4. Layout with Dummy Layers
Now we have the layout with dummy filled. Now finally we must run the final GDSII to make the
binary file which will be used by fabrication lab to fabricate the chip.
28
Figure 4.5. Schematic diagram of 14 - bit Single ended SAR ADC
29
Figure 4.6. GDS of 14- bit Single ended SAR ADC
30
Table 4.2. Comparison of specifications for the 14 -bit ADC
2
Size of the chip 1582x1582 µm
Targeted Achieved
Topology SAR Single Ended SAR
Technology 180nm 180nm
Supply voltage: 1.8 V 1.8 V
Input voltage < 1.8 V <1.8 V
Resolution: 14 bit 14 bit

+0.75 LSB,
INL ±0.5 LSB
-0.8LSB
DNL ±0.5 LSB +0.63LSB, -0.75LSB
SINAD (dB) 80 dB 52.48
SFDR (dB) 90 dB 55.46
ENOB: 12 bit 8.4203 bit
SNR achieved: 74 dB 52.48 dB
Input signal frequency: 10 Hz – 500 Hz 10 Hz – 500 Hz
Sample rate: 100 Hz –50 KHz 100 Hz –50 KHz
After the post layout simulation of the ADC, the ENOB found to be very poor. Also, the target did
not achieve. The reasons for this behavior is discussed in the next chapter. After this Fully
Differential SAR ADC with Multichannel has been started to be designed to improve the
performance.
31
Table 4.3 Summarizes the elaborated specifications for 14-bit Fully Differential SAR ADC
ADC Specifications
Type SAR
Topology Multi-channel differential
Technology 180nm SCL
Supply voltage: 1.8 V
Input voltage 1 V p-p
Resolution: 14 bit
Targeted ENOB: 13 bit
Noise: <30 µV p-p
LSB: 61.03 µV
Input frequency: 10 Hz – 500 Hz
Dynamic Range: 80 dB
32
Fully Differential SAR ADC
CHAPTER V
With a limited signal swing, the sampling capacitance must be large enough to achieve a
high signal-to-noise ratio (SNR), which leads to large current consumption. However, in SAR
architectures, no component consumes static power if preamplifiers are not used. A SAR ADC can
easily achieve a rail-to-rail signal swing, meaning that a small sampling capacitance is sufficient
for a high SNR. The conversion time and power dissipation become smaller with the advancement
of CMOS technologies. Since SAR ADCs take advantage of technological progress, for some
high-conversion-rate applications, power- and area-efficient SAR ADC can possibly replace
pipelined ADCs in nanometer scaled CMOS processes. In SAR ADC, the primary sources of
power dissipation are the digital control circuit, comparator, and capacitive reference DAC
network. Digital power consumption becomes lower with the advancement of technology.
Technology scaling also improves the speed of digital circuits. On the other hand, the power
consumption of the comparator and capacitor network is limited by mismatch and noise.
5.1 Advantages of Differential ADC over Single ended ADC
The primary advantage of differential ADC is high common-mode noise immunity

compared to single-ended ADC. This noise immunity is due to 1) the same noise being coupled
on both the inverting and non-inverting input signals of the ADC, and 2) this noise is rejected by
common-mode rejection capabilities of the differential ADC.
In differential ADCs, both input signals are physically run in parallel with each other. Thus the
same amount of noise gets coupled into both the signals. Also, when both signals are running in
33
parallel and run the same distance (same trace/wire length), they are in the same phase when they
reach the ADC. As noise coupled on both signals has the same amplitude and same phase, it gets
rejected to provide very high noise immunity. This high noise immunity makes differential ADCs
the best fit in the applications where the output signal from a sensor is very small and/or noise in
the system is very high.
One such example is load-cell interfacing used in industrial control applications. With a load-cell,
the output signal is differential in nature and the signal voltage swing is only a few millivolts. The
signal is riding on top of noise that may be a few volts in amplitude -- but the noise is common
mode.
One may think of using a differential to the single-ended stages like an instrumentation amplifier
or a transformer before applying a differential input signal to a single-ended ADC and hope to
achieve good noise performance by virtue of rejection of coupled noise on the long wires by this
converter stage. However, this will not provide the same performance that could be achieved using
a differential ADC.
One reason is that some noise may get coupled on the signal when it travels from the differential
to single-ended converter. In addition, the ADC offset and the offset of the converter stage will
play a major role and must be removed for accurate measurement. Generally, additional signal
conditioning stages add noise that reduces the overall SNR of the signal chain. There are ADCs
that have internal gain capabilities that provide better noise performance compared to external
amplifiers. Thus it is a good practice to avoid an external gain stage/differential to the single-ended
converter.
In differential ADCs, SNR is also improved because of the change in the dynamic range. The
dynamic range of a differential ADC is given by Vin- ± Vin+. In these ADCs, generally, both inputs
can range from Vss to Vdd (low supply rail to high supply rail). This makes the dynamic range twice
as much as in case of single-ended ADC – that is 2⋅Vdd.
Equation 1 gives the SNR for an ADC.
34
In case of a differential ADC, the signal amplitude can be twice as high compared to a single-
ended ADC. Thus the SNR is improved by 6dB just because of a higher dynamic range in the
differential ADC.
Also, any DC offset (limited only by common-mode voltage) can be provided for signals that are
too small and have amplitude close to the lower supply rail, or for signals that have a voltage below
the ADC ground. This DC offset gets removed by the common-mode rejection characteristics of
differential ADCs. It also reduces the significant overhead that would have been required to
remove the DC offset if a single-ended ADC was used.
5.2 Architecture of Differential ADC
To achieve 14-bit accuracy, a fully differential architecture suppresses the substrate and
supply noise and has good common-mode noise rejection. SAR ADCs usually use a binary-
weighted capacitor array rather than a C-2C capacitor array for better linearity. Figure. 5.1 shows
a conventional 14-bit fully differential SAR ADC. The fundamental building blocks are the
comparator, sample-and-hold (S/H) circuit, capacitor network, and successive approximation
registers. In this charge-redistribution based architecture, the capacitor network serves as both an
S/H circuit and a reference DAC capacitor array. Therefore, this architecture does not require a
monolithic S/H circuit. Since this ADC is fully differential, the operation of the two sides is
complimentary. For simplicity, only the positive side of the ADC operation is described below. At
the sampling phase, the bottom plates of the capacitors are charged to Vip, and the top plates are
reset to the common-mode voltage Vcm. Next, the largest capacitor C1 is switched to and the other
capacitors are switched to ground. The comparator then performs the first comparison. If Vip is
higher than Vcm, the most significant bit (MSB) is 1. Otherwise, is 0, and the largest capacitor is
reconnected to ground. Then, the second largest capacitor C2 is switched to Vref. The comparator
does the comparison again. The ADC repeats this procedure until the least significant bit (LSB) is
decided. Although the trial-and-error search procedure is simple and intuitive, it is not an energy
efficient switching scheme, especially when unsuccessful trials occur.
35
Figure 5.1. Conventional Fully Differential SAR ADC
Figure 5.2. Fully Differential SAR ADC with Monotonic Switching
36
Figure. 5.2 shows the proposed SAR ADC, where the proposed switching procedure can
be either upward or downward. For fast reference settling, i.e., discharging through n-type
transistors, downward switching was selected in this ADC. The proposed ADC samples the input
signal on the top plates via bootstrapped switches, which increases the settling speed and input
bandwidth. At the same time, the bottom plates of the capacitors are reset to Vref. Next, after the
ADC turns off the bootstrapped switches, the comparator directly performs the first comparison
without switching any capacitor. According to the comparator output, the largest capacitor C1 on
the higher voltage potential side is switched to ground and the other one (on the lower side) remains
unchanged. The ADC repeats the procedure until the LSB is decided. For each bit cycle, there is
only one capacitor switch, which reduces both charge transfer in the capacitive DAC network and
the transitions of the control circuit. and switch buffer, resulting in smaller power dissipation. The
flow chart of the proposed successive-approximation procedure is shown in Figure 5.3.
Figure 5.3. Flowchart of the proposed ADC
37
One of the major differences between the proposed method and the conventional one is
that the common-mode voltage of the reference DAC gradually decreases from half to ground as
shown in Figure. 5.5. The proposed switching sequence does not require an upward transition. At
the same transistor size, the on-resistance of an NMOS switch is only about 1/3 that of a PMOS
one. Having no upward transition speeds up the DAC settling. In addition, since sampling is done
on the top plate, the comparator can do the first comparison without any capacitor switching. For
an n-bit ADC, the number of unit capacitors in a capacitor array is 2(n-1), only half that of the
conventional one.
(a)
(b)
Figure 5.4. (a) Conventional Switching (b) Monotonic Switching
38
Figure. 5.5 shows 3-bit examples of the conventional and proposed switching methods.
The conventional switching method is based on a trial-and-error search procedure. Figure. 5.5(a)
shows all possible conversions. The quantitative energy consumption of each switching phase is
also shown in the figure. The conventional switching sequence is efficient when all the attempts
are successful, as in the upper cases. However, the switching sequence consumes a lot of energy
when attempts are unsuccessful, as in the lower cases. For an n-bit conventional SAR ADC, if
each digital output code is equiprobable, the average switching energy can be derived as
n
Eavg ,conventional =  2n+1−2i (2i − 1)CVref2
i =1
For a 14-bit case, the conventional switching procedure consumes 21841.3 CVref2 . Figure.
5.5(b) shows all possible switching cases of the proposed method. After the sampling switches
turn off, the comparator directly performs the first comparison without switching any capacitor.
Therefore, the proposed switching sequence consumes no energy before the first comparison. In
contrast, the conventional sequence consumes before the first comparison. The subsequent
switching sequence of the proposed method is also more efficient than that of the conventional
one.
n −1
Eavg ,monotonic =  (2n−2−i )CVref2
i =1
The switching energy transfer procedure in Figure 5.b is described below. The energy transfer can
be computed by the equation below
Energy Transfer = (Rest Energy) *(Equivalent capacitance after switching)
Case 1: No capacitor switching occurs. So, Energy Transfer is 0.
1
Case 2: Energy stored in capacitor before switching is .4C.Vref2 = 2.C.Vref2
2
2.C 1 1
Equivalent capacitor after switching is = . So, Energy Transfer = 2.C.Vref2  = C.Vref2
4.C 2 2
1
Case 2: Energy stored in capacitor before switching is .4C.Vref2 = 2.C.Vref2
2
39
2.C 1 1
Equivalent capacitor after switching is = . So, Energy Transfer = 2.C.Vref2  = C.Vref2
4.C 2 2
Figure 5.5. (a) Conventional Switching for 3 -bit DAC
40
Figure 5.5. (b) Monotonic Switching for 3 -bit DAC
41
5.3 Architecture of Dynamic Comparator
Each A/D Converter contains at least one comparator. A comparator itself can be
considered a 1-bit A/D Converter. In the presented ADC design, the comparator plays a key role;
it must be able to discriminate voltages as small as 61 µV.
Specifications
. Where comparators are incorporated into IC ADCs, their design must consider:
- Offset voltage
- Resolution
- Speed
- Power dissipation
- Area
A critical specification is the offset voltage. We require that the offset voltage be smaller than 30
µV.
Architecture
Each A/D Converter contains at least one comparator. A comparator itself can be
considered a 1-bit A/D Converter. In the presented ADC design, the comparator plays a key role;
it must be able to discriminate voltages as small as 61 µV.
Figure 5.6 is showing the proposed dynamic comparator [21] circuit. It is a two-stage
comparator: the first stage is the input gain stage and 2nd stage is the output latch. This architecture
made this comparator operate in a lower and stable offset. It also operates in a wide range of
common mode voltages and at a lower supply voltage. In pre-charge phase (CLK comp = 0), Di+
and Di- are grounded by MN1, MN2 transistors and the 𝑉out are pre-charged to zero by MP5,
MP8 transistors and Inverters. In comparison phase (CLK comp = 1), MP3 is on, so Di+ and Di-
nodes voltage start to charge from ground to 𝑉dd with a different time rate proportional to each
42
input voltage. So MP1 and MP2 generate a differential voltage at Di+ and Di- nodes. This
differential voltage is now passed to output latch through MN3 and MN4 transistors.
So MP1 and MP2 generate dd So the cross-coupled inverter in output latch regenerates the
𝑉 voltages according to the difference present at the input gain stage. Figure 5.6 is showing the
output generated out by the dynamic comparator.
The dynamic offset of the proposed comparator is minimized by adding MP4 transistor at
the top of the gain stage. As MP4 is in the saturation region, the change of its drain to source
voltage has a slight influence on the drain current. Hence MP4 keeps the effective voltage of the
input pair near a constant value when common mode voltage changes. The dynamic offset thus
has a minor influence on the conversion linearity. Again, the MP1 and MP2 have a large size to
minimize the offset.
Figure 5.6. The architecture of Dynamic Comparator
43
Figure 5.7. Schematic diagram of Dynamic Comparator
44
Figure 5.8. The output response of Dynamic Comparator
45
Figure 5.9. The layout of Dynamic Comparator
46
5.4 Architecture of Synchronous Shift Register
The Shift register is designed using D FF. The D FF is Designed based on Transmission Gate to
minimize the transistor count. The D FF has Enable, Rest and Set pin to operate. Initially all the
FF were Reset to zero, then on each rising edge of clock the data shifted from 1st output to last
output. The Reset and Set pins are low enable in the design. But the Enable is High enable.
Architecture of TG based DFF
the circuit diagram of TG based master-slave D flip-flop having enabled control. In the first part
of the circuit acts like master and latter one behaves as slave. Initially if reset and preset is 1 (not
active). When the clock signal is ‘0’ then first and fourth TG will on. Data will pass within the
master block. When the clock signal will be ‘1’ then it will on the second and fourth TG to pass
the data from master to slave cycle and from slave to output cycle. Output data will be passed in
the reversed form. Hence, we use an inverter. After that, we use an AND gate to make the flip-
flop enable dependent. But, in case the preset signal is activated then forcefully output will be ‘1’.
A similar case will happen for reset signal also which will make the output forcefully to ‘0’.
Figure 5.10. Schematic diagram of Transmission Gate based D FF
47
Figure 5.11. The layout of Transmission Gate based D FF
Figure 5.12. The pre-layout waveform of Transmission Gate based D FF
48
Figure 5.13. 14-bit Shift Register using Transmission Gate based D FF
Figure 5.14. Schematic diagram of 14 -bit Shift Register using Transmission Gate based D FF
Figure 5.15. The layout of 14-bit Shift Register using Transmission Gate based D FF
49
Figure 5.16. Pre-Layout of 14-bit Shift Register using Transmission Gate based D FF
Figure 5.17. Post-Layout of 14 -bit Shift Register using Transmission Gate based D FF
Figure 5.18. Post-Layout of 14 -bit Shift Register using Transmission Gate based D FF
50
5.5 Architecture of DAC Control Logic
shows a schematic and a timing diagram of the DAC control logic. At the rising edge of,
static flip-flop samples the comparator output. If the output is high, the relevant capacitor is
switched from to ground. If the output is low, the relevant capacitor is kept connected to. At the
falling edge of, all capacitors are reconnected to zero. The delay buffer guarantees that triggers the
AND gate after the output of the static flip-flop. This timing arrangement avoids unnecessary
transitions. This work uses an inverter as a switch buffer. The conventional architecture samples
both the input signal and reference voltages on the bottom plates. If the input swing is nearly rail-
to-rail, transmission gates are needed to sample input signal. This work uses bootstrapped switches
to sample input signal onto top plate of the capacitors and uses inverter buffers to switch between
positive and negative voltages. Hence, compared to the conventional architecture, no transmission
gates are used, which enables high-speed and low-power operation.
Figure 5.19. 1-bit DAC Control
Figure 5.20. The timing diagram of DAC Control
51
Figure 5.21. DAC Control with Switch to control Capacitor
Figure 5.22. DAC Control with SAR Logic
As shown in Figure 5.21, the DAC control logic parts include a DFF, an AND gate, and a
delay buffer to make sure that CLK triggers AND gate when the output of DFF generated; and the
last DAC control part is only a DFF that will generate last bit, D10. Figure 5.25 shows an example
of the simulated waveforms of DAC control logic. At the rising edge of CLK1 and CLK2, DFF
samples the comparator output 𝑉out +. As 𝑉 out+ is low, the DAC control signals DAC CON P1
and DAC CON P2 are high to switch the relevant capacitor switches again at rising edge of CLK
3 comparator output 𝑉out- is high, which results in DAC CON N3 being high to control the
corresponding capacitor switch.
52
Figure 5.23. Schematic diagram of 1 -bit DAC Control
Figure 5.24. Schematic diagram of 14 -bit DAC Control
Figure 5.25. The layout of 1-bit DAC Control
53
Figure 5.26. The layout of 14-bit DAC Control
Figure 5.27. Pre-Layout of 14-bit DAC Control
Figure 5.28. Post-Layout of 14 -bit DAC Control

54
Figure 5.29. Post-Layout and Pre -Layout comparison of 14-bit DAC Control
55
5.6 Architecture of Delay Buffer
The delay buffers have been used for two reasons. First to match the propagation delay
between Analog block and digital block and in layout two blocks will sit far apart from each other
so to maintain the signal integrity the delay buffers have been used.
Figure 5.30. Schematic of Delay Buffer
Figure 5.31. The layout of Delay Buffer
56
5.7 Architecture of Track and Hold
Conventional sample hold circuit is made either using transmission gate (TG) or simple a
Transistor and a holding capacitor. But, in those case transistors must be kept in linear region for
switching purposes. To operate the MOS in linear region 𝑉𝑔𝑠 must be constant or 𝑉𝑔𝑠 = 𝑉𝑑𝑑 . But
in case of Differential ADC sampling voltage is summation of common mode voltage (𝑉𝑐𝑚 ) and
input voltage (𝑉𝑖𝑛 ). Hence, source voltage of transistor depends on input voltage. If we keep gate
of NMOS at 𝑉𝑑𝑑 then,
𝑉𝑔𝑠 = 𝑉𝑑𝑑 − 𝑉𝑐𝑚 − 𝑉𝑖𝑛
From the equation we can see 𝑉𝑔𝑠 depends on the input voltage which is varying in nature.
So, transistor’s region of operation will change. Hence, sample and hold will not operate in linear
region. To solve this problem, some constant voltage must be added which will compensate the
effect of input voltage. So, track and hold switch or bootstrap switch is implemented for the
switching the transistor. But, practically voltage source can’t be added within the circuit. So,
voltage source will be replaced by a capacitor (𝑐𝑏𝑜𝑜𝑡 ) which will store the required voltage by
some switching mechanism.
Figure 5.32. NMOS switch for Sample and Hold
In this above figure 𝑐𝑏𝑜𝑜𝑡 will be needed in the hold phase for charging and in the track
phase it will provide the constant 𝑉𝑔𝑠 to keep the MOSs in linear region. Current through this
capacitor must be zero; otherwise charge loss will happen and MOSs will no longer in linear
region. In the hold phase all the ∅2 switches will be on and initially the capacitor (𝑐𝑏𝑜𝑜𝑡 ) will
charge through path 1 and in this stage M1 transistor will be off through path 2. In the track phase
57
all the ∅1 switches will be on. Hence, the 𝑐𝑏𝑜𝑜𝑡 will provide required voltage in the gate terminal
of M1 and the source voltage will pass to charge the holding capacitor. Now the switches can be
made using three combinations:
1) NMOS must be used when switching node voltage will be low.

2) PMOS must be used when switching node voltage will be high.
3) TG must be used when switching node voltage will be varying in nature.
Figure 5.33. Track and Hold Concept
Switch 1 will depend upon 𝑉𝑖𝑛 . We know the input voltage is varying in nature it will vary
from 0.4V to 1.4V. Depending on the input voltage different voltage will pass through switch 1.
Hence, this switch will be replaced by TG based switch.
Switch 2 and 3 will be implemented by NMOS as the voltage is zero at the terminal. Switch
2 will complete the charging path of 𝑐𝑏𝑜𝑜𝑡 capacitor to ground. Hence, it is a low voltage switching
case. Similarly, switch 3 will help to keep the M1 transistor off during the holding phase. M1 is
basically an NMOS transistor. So, to make it off, low voltage has to be given in the gate terminal
of M1. Hence, it is also a low voltage switching case.
Switch 4 will be used in the tracking phase to provide the constant amount of voltage at
the gate terminal of M1 transistor through 𝑐𝑏𝑜𝑜𝑡 capacitor. In this tracking phase of this switch it
is required high voltage. Hence, Pmos switch will be suitable here. The body of the PMOS is
connected to 𝑐𝑏𝑜𝑜𝑡 as it provides the higher voltage. If the body was connected to the other
58
terminal, then the transistor will be in saturation region and current will be drawn out form the
switching transistor.
Switch 5 will be used to charge the 𝑐𝑏𝑜𝑜𝑡 capacthe itor in the hold phase. Hence, we need
the PMOS transistor as 𝑐𝑏𝑜𝑜𝑡 capacitor needs to be charged at a high voltage which will be passed
via this switch. For this purpose, we must have certain ama ount of voltage in the gate terminal of
the PMOS. But to control the switch we need a higher voltage than 𝑉𝑑𝑑 to keep the transistor n
linear region. So, the controlling voltage must be ∅2 + 𝑉𝑑𝑑 . Now to generate the ∅2 + 𝑉𝑑𝑑 a
capacitor and a switch is needed, and the switch is controlled by 2 + Vdd , also to generate this
voltage another switch and capacitor is needed this switch is controlled by ∅2 + 𝑉𝑑𝑑 . So, two back
to back switches is needed and both is controlled by other. The input of the capacitors is connected
with 2 and 2 . This circuit arrangement is known as charge pump circuit or Nagakome Charge
Pump circuit.
Figure 5.34. Schematic diagram of Track and Hold
In the diagram of a bootstrap switch, we have seen there are two phases. These are tracking
or sampling phase and holding phase. There are five switches present in which two switches will
be on in the tracking phase and rest will be on in the holding phase. The most important criteria
for operation of the bootstrap switch is and switches can’t be on at the same time. That means
when is on is off and vice versa. Hence, two non-overlapping pulses must be needed which will
control those switches.
59
In this Figure below, we have seen a SR latch which will create two non-overlapping pulse.
Here, the sample signal is a pulse is 0 then one input of first NAND gate is 0 and another NAND
gate is 1. Now the output of second NAND will be 0 and that is feedback to the input of the first
NAND. Hence, the output of second NAND will be 1. It will continue until the sample signal
switches to 1. After sample signal’s switching to 1 output of the first NAND will fall to zero which
will go to the input of the second NAND and make that output 1. But, we have seen from the figure
below that there is some delay in the output which is nothing but the delay of individual NAND
gate. After the NAND gates output we use an inverter and buffer to get the non-overlapping signal
according to sample signal.
Figure 5.35. Non-Overlapping Clock
Figure 5.36. Pre-layout Simulation of Track and Hold
60
Figure 5.37. The layout of Track and Hold
61
Figure 5.38. Post-layout Simulation of Track and Hold
Figure 5.39. Comparison of Pre-layout simulation and Post -layout simulation of Track and Hold
62
5.8 Architecture of Capacitive DAC
This section examines the digital-to-analog conversion aspect. The input to the DAC is a
digital word consisting of parallel binary signals that are generated from DAC Control.
The factors that determine the speed of the DAC are the parasitic capacitors. Different DAC
architectures are:
1. Nyquist DAC architectures:
For example:
a) Binary-weighted DAC
b) Unit-element (or thermometer-coded) DAC
c) Segmented DAC
d) Resistor-string, current-steering, charge-redistribution DACs
2. Oversampling DAC:
a) Oversampling performed in the digital domain (zero stuffing)
b) Digital noise shaping (ΣΔ modulator)
c) 1-bit DAC can be used
d) Analog reconstruction/smoothing filter
The linearity of ADC is restricted by the linearity of the DAC which is caused by the capacitor
mismatch. Therefore, choosing an appropriate value for the unit capacitance is vital. Reducing the
unit capacitance value improves the linearity but deteriorates the noise performance at the same
time due to thermal noise. The minimum value of the unit capacitor is limited by several factors
including thermal noise, capacitor matching and the value of the parasitic capacitances. For
conventional differential ADC, the area required is also very large. A 14-bit conventional
differential ADC binary array structure requires 8192 unit capacitors (Cs) whereas a 14-bit
differential ADC with monotonic switching structure requires 4096 unit capacitors (Cs).
63
The unit capacitor sizing must consider 𝑘𝑇/𝐶 noise, 14-bit accurate matching, timing and
power consumption. Of course, to decrease power consumption and increase speed, the unit
capacitor should be as small as possible. On the other hand, to improve MIM capacitor matching,
noise immunity and consequently the ADC’s accuracy, the unit capacitor must be as big as
possible. The design approach chosen here gives priority to accuracy. Indeed, the minimum
unit capacitor size, dictated by either 𝑘𝑇/𝐶 noise or capacitor matching, is determined first. It
is then shown that timing requirements are met with the found unit capacitance value and that the
power consumption is reasonably small. For our design, the unit capacitor is equal to capacithe
tance of 20fF.
Figure 5.40. DAC structure with switches
Basically, there are two types of layout techniques of the capacitor. First one is the
conventional approach of designing and the second one is the common centroid approach for
layout. During layout of any capacitor, we should concern about the performance and accuracy of
any capacitor.
Common Centroid Layout Ratioed capacitors are frequently applied to many analog circuit
components, such as amplifiers, integrators, filters, and data converters. By taking advantage of
the charge ratio among capacitors, these circuit components are designed to be independent of the
absolute capacitance values of the capacitors because absolute capacitance values are much more
sensitive to process variation than the relative capacitance ratio among capacitors. Consequently,
the accuracy of the capacitance ratio among the ratioed capacitors is the key to circuit performance
64
and robustness. For example, the output voltage of the digital-to-analog converter (DAC) is a
function of the voltage division among the binary weighted capacitors or split array capacitors.
When designing analog layouts, the accuracy of capacitance ratios correlates closely with the
matching properties among the ratioed capacitors and the induced parasitic due to interconnecting
wires. The unwanted parasitic can even shift the design performance as high as 90%. To improve
the accuracy of capacitance ratios, each capacitor is divided into multiple identical square unit
capacitors with the largest practical physical dimension. The guidelines on the aspect ratio,
placement, and routing for a unit capacitor array were presented below.
Aspect ratio: - Matched capacitors must be arranged to form a rectangular array with equal column
and row spacing, respectively. The aspect ratio of the rectangular array should be close to 1.0.
Placement: - Matched capacitors should be placed to satisfy the properties of coincidence,

symmetry, dispersion, and compactness such that the systematic and random mismatches among
the capacitors can be minimized.
Routing: - The wire length of each net should be minimized and matched with respect to the
corresponding capacitor ratio. The coupling between wires connecting to the top and bottom plates
of the ratioed capacitors should be avoided. Consequently, both the induced parasitic resistance
and capacitance can be minimized.
(a) (b)
Figure 5.41. (a) Unit Capacitor of 20fF (b) 40fF using two 20fF
65
Figure 5.42. Placement Strategy of DAC Array
66
Figure 5.43. Schematic diagram of 14-bit Fully Differential SAR ADC
67
Multi-Channel Fully Differential SAR ADC
CHAPTER VI
In the introduction, it has been discussed that ADC for Seismic Sensor requires at least
Three channels. So, as per the requirement of Seismic Sensors Three Channel has been designed.
Moreover, the requirements of the project were:
1. The user will supply Single ended Signal at the input. The ADC must convert it to
Differential signal itself then convert to binary.
2. The user must able to access any of the output at any time during the conversion time.
3. There must be a provision to use the ADC as single channel also.
To overcome the issues the following actions were taken.
1. A Single-ended (SE) to Differential ended (DE) Converter was designed. The SE to DE

converter was designed using an Inverting and Non-Inverting Amplifier configuration.
2. To give the access to any channel at any time a combinational Circuit has been designed.
A 14 -bit De-Multiplexer and three Internal Registers has been designed to store the data
temporarily. After when the user wants to access the output the Data will be fed to the user
by a Multiplexer of and a Register.
3. As the Clock control circuit was difficult to design by FSM. So, the clock Network was
designed using Stored Procedure Control. The whole clock network was soft coded i.e.
Programmed into a ROM so that the Clock network can be changed at any time as per
requirements. As diode was not present in the SCL pdk the ROM was designed using
NMOS only. As NMOS consumes less area than PMOS. But the challenge was to design
the ROM such that the when a logic ‘1’ is coming to the NMOS must charge the crossbar
to a certain level such that the output buffer pulls the in-between logic to Logic ‘1’. The
ROM was controlled by a Counter and a Decoder. Both of them has been designed such
that they are Reset when they are Powered On.
68
Figure 6.1. Block diagram of Multichannel ADC
69
Figure 6.2. The timing diagram of Multichannel ADC
70
Summary of Timing Diagram:
1. Ext_Clk, CS and Conversion Start Signal will be provided by the user.

2. Internal Clk will be generated when CS and Conversion Start signal is High.
3. C0, C1 are internal signals generated to select the Analog Input Channel.
4. Sample Signal is given to Sample & Hold block as Sample Clock.
5. ADC Clk will generate at the positive edge of Internal Clk after the negative edge of
Sample Clock and it will follow the Internal Clk for 14 conversion cycle after that it will
stop to reduce the dynamic power.
6. After 14 Clock cycle the Register Clk will be enabled as depending upon C0 and C1 it
will put the output to the dedicated register.
C0 and C1 have been started from ’01’ combination as ‘00’ combination is a risk to false start
the ADC core.
71
6.1 Architecture of Single-Ended to Differential Converter
Single to Differential architecture have been made using Operational Amplifiers. But the
requirement is not only SE to DE conversion but also to add the Vcm to the single-ended signal.
The Vcm is chosen to be 900mv. Now as the single-ended signal is 1 V p-p. After adding the Vcm
the Signal swing will change to 1.4V-0.4V. So, the OPAMP must be designed in such a way that
ICMR matches the requirements of the signal also no clip off occurs in any magnitude of the signal.
The structure of OPAMP chosen as Two stage OPAMP where the Cc=800fF. The Gain and
Bandwidth for designing the OPAMP chosen as 70dB and 5KHz. The Bandwidth can be made
small also so that minimum noise affects the system.
(a) (b)
Figure 6.3. (a) Schematic diagram of OPAMP (b) Bias circuit of OPAMP
72
The transfer function of the inverting SE to DE converter is given below
Rf
Vout = − .Vin
Ri
But to add the common mode voltage to the Differential signal Vcm/2 i.e. 450mV is given at the
input of Non-inverting terminal of the OPAMP.
Figure 6.4. Schematic diagram of Inverting Differential Signal generation
Figure 6.5. Pre-Layout of Inverting Differential Signal generation
73
Figure 6.6. The layout of Inverting Differential Signal generation
74
Figure 6.7. Post-Layout of Inverting Differential Signal generation
Figure 6.8. Post-Layout and Pre-Layout comparison of Inverting Differential Signal generation
75
The non-inverting Differential signal has been generated with the transfer function below
( R2 .Vcm + R1.Vin )*( R3 + R4 + C1.R3 .R4 .s)

Vout =
R4 .( R1 + R2 ).(C1.R3 .s + 1)
Figure 6.9. Schematic diagram of Non -Inverting Differential Signal generation
Figure 6.10. Pre-Layout of Non-Inverting Differential Signal generation
76
Figure 6.11. The layout of Non-Inverting Differential Signal generation
77
Figure 6.12. Post-Layout of Non-Inverting Differential Signal generation
Figure 6.13. Post-Layout and Pre -Layout comparison of Non -Inverting Differential Signal
generation
78
6.2 Architecture of Analog Multiplexer
The architecture of Analog Multiplexer is shown in the Figure below. It is consisting of a

transmission gate. When control is high M1-M4 transistors are ON. So, the input Z passes to output
Y. also M3 and M4 transistors are used for impedance matching. When the control is LOW the
M5 transistor is ON making the residue charges to zero.
Figure 6.14. Schematic of Analog Multiplexer
Figure 6.15. Schematic of Analog Multiplexer with Control C0 and C1
79
Figure 6.16. The layout of Analog Multiplexer Array
80
Figure 6.17. Pre-Layout of Analog Multiplexer Array
Figure 6.18. Post-Layout of Analog Multiplexer Array
81
Figure 6.19. Post-Layout and Pre -layout comparison of Analog Multiplexer Array
82
6.3 Architecture of 14-bit De-Multiplexer
The De-MUX is used for writing the 14-bit output data to the specified registers. After 14
cycles of the clock when the data is ready to write the Enable signal is High and based on C0 and
C1 the De-MUX performs the write operation to the specified registers.
Figure 6.20. Schematic of 1-bit De-Mux
Figure 6.21. Schematic of 14-bit De-Mux
83
Figure 6.22. The layout of 1-bit De-Mux
Figure 6.23. Pre-Layout of 1-bit De-Mux
84
85
Figure 6.25. Post-Layout of 1 -bit De-Mux
Figure 6.26. Post-Layout and Pre -Layout comparison of 1 -bit De-Mux
86
6.4 Architecture of 14-bit Multiplexer
The Multiplexer is used for the user end. The user can see any of the three channel outputs
at any time. So, based on the user input S0 and S1 any of the three channels will appear at the
output.
Figure 6.27. Schematic of 1-bit Mux
Figure 6.28 Schematic of 14-bit Mux
87
Figure 6.29. The layout of 1-bit Mux
Figure 6.30. Pre-Layout of 1-bit De-Mux
88
Figure 6.31. Post-Layout of 1 -bit De-Mux
Figure 6.32. Post-Layout and Pre -Layout comparison of 1 -bit De-Mux
89
6.5 Architecture of 14-bit Output Register
The final digital code after conversion and De-Muxing of a sample must be stored
somewhere for the user to read it. So, a 14bit register is designed as shown in Figure to store the
value and pass it when needed. It is 14bit parallel input parallel output register designed using edge
triggered D Flip Flops. and the conversion time of a given signal is very less as compared to sample
rate. So, to reduce the power consumption we want our ADC core to remain ideal for the time
there is no new sample available after the conversion of the given sample.
Figure 6.34. Schematic o f 14-bit Output Register
Figure 6.35. Pre-Layout of 14-bit Output Register
90
Figure 6.36. Post-Layout of 14 -bit Output Register
Figure 6.37. Post-Layout and Pre -Layout comparison of 14 -bit Output Register
91
Figure 6.38. The layout of 14-bit Output Register
92
6.6 Architecture of Clock Network
For complex clock signals, it is difficult to design the clock network where input
variable is only an external clock. also, the circuit complexity increases, and a number of loop
increases. So, it might happen after layout these dependencies might not work as the set up and
hold time might get violated. Also, it might happen that the requirement of clock changes after
some issues. Then, it is difficult to redesign the clock using FSM. So, the clock circuit has been
programmed to a ROM. This architecture is like the procedure control in microprocessors i.e.
Stored Procedure Control. The architecture contains a counter, a decoder, and a ROM. All the FF’s
in the counter are Set at Power on using few delay buffers. So that, after the 1st clock pulse these
components are reset to 0. As diode was not present in the SCL pdk the ROM was designed using
NMOS only as NMOS consumes lesser area than PMOS and for homogeneity in the layout. But
the challenge was to design the ROM for a strong logic ‘1’ produced out of NMOS transistors. So,
an output buffer was provided to convert the weak ‘1’’s produced by NMOS transistors into strong
‘1’’s. To pull down the crossbar line to Logic ‘0’ the NMOS is sufficient as NMOS produces
strong Logic ‘0’. The crossbar architecture helps to reprogram the clock network as many times as
possible.
Figure 6.39. Block diagram of the clock network
93
Figure 6.40. Schematic of Counter reset to ‘48’
Figure 6.41. The layout of Counter reset to ‘48’
Figure 6.42. The pre-layout waveform of Counter reset to ‘48’
94
Figure 6.43. Schematic of 6-64 Decoder
Figure 6.44. The layout of 6-64 Decoder
Figure 6.45. Pre-Layout of 6-64 Decoder
95
Figure 6.46. Schematic of Crossbar architecture using NMOS
Figure 6.48. The layout of Clock Control Unit developed using SPC
96
Figure 6.49. Pre-Layout of Clock Control Unit developed using SPC
Figure 6.50. Post-Layout of Clock Control Unit developed using SPC
97
6.7 Architecture of Register Control
The register control was provided after the clock control unit to select the register to
store the 14-bit output to the dedicated registers. The register must hold the data until the next data
is coming from the same channel and the data must not write to any other registers. This also
reduces the dynamic power consumption as no node is switching in that time. The Register control
must be generated from the output register enable signal and C0, C1 generated by SPC.
Figure 6.52. Schematic of Register Control
98
Figure 6.53. The layout of Register Control
99
Figure 6.54. Pre- Layout waveform of Register Control
Figure 6.55. Post- Layout waveform of Register Control
100
Figure 6.56. Pre- Layout and Post- Layout comparison of Register Control
101
Validation of Fully Differential SAR ADC
CHAPTER VII
The ADC core has been simulated with different input voltages. A list of few such voltages
has been given in Table. The Single Chanel Operation is shown the Table below. The Output of
Multichannel is shown in the latter part of the chapter. But due to lack of time, I could not take
many data to validate the core.
Table 7.1 Output data of 14-bit Fully Differential SAR ADC for different analog voltages
Analog (V) Analog (V) Actual Binary ADC Output

Vip Vin
0.825 0.975 0110 1100 1100 11 0110 1100 1101 00
0.78 1.02 0110 0001 0100 01 0110 0001 0100 11
1 0.8 1001 1001 1001 10 1001 1001 100001
1.35 0.45 1111 0011 0011 00 1111 0011 0001 01
1.39 0.41 1111 1101 0111 00 1111 1101 010011
1.4 0.4 1111 1111 1111 11 1111 1111 1111 11
0.652 1.148 0100 0000 1000 00 0100 0000 1001 00
0.7 1.1 0100 1100 1100 11 0100 1100 110110
0.8 1 0110 0110 0110 01 0110 0110 0110 11
0.42 1.38 0000 0101 0001 11 0000 0101 0100 00
0.900062 0.899938 1000 0000 0000 01 1000 0000 0000 01
0.899938 0.900062 0111 1111 1111 10 0111 1111 1111 10
0.506 1.294 0001 1011 0010 00 0001 1011 0011 10
1.25 0.55 1101 1001 1001 10 1101 1001 1000 00
0.504 1.296 0001 1010 1001 11 0001 1010 1011 10
0.605 1.195 0011 0100 0111 10 0011 0100 0111 11
0.709 1.091 0100 1111 0001 10 0100 1111 0010 01
0.8996 0.9004 0111 1111 1110 01 0111 1111 1110 01
0.5 1.3 0001 1001 1001 10 0001 1001 1011 00
1.3 0.5 1110 0110 0110 01 1110 0110 0100 11
102
0.4 1.4 0000 0000 0000 00 0000 0000 0000 00

1.392245 0.407755 1111 1110 0000 00 1111 1101 1101 11
0.40781248 1.39218752 0000 0001 1111 11 0000 0001 1111 00
0.401 1.399 0000 0000 0100 00 0000 0000 0110 01
Figure 7.1. Output waveform of 14 -bit ADC with Vip=0.825 mV and Vin=0.975 mV
Figure 7.2. Output waveform of 14 -bit ADC with Vip=0.900062V and Vin=0. 899938V
103
Figure 7.3. Reconstructed analog signal after an ideal DAC for input frequency 500Hz and
Sampling frequency 31.3 KHz
Specifications for quantifying ADC dynamic performance are SINAD (signal-to-

noise-and-distortion ratio), ENOB (effective number of bits), SNR (signal-to-noise ratio), THD
(total harmonic distortion), THD + N (total harmonic distortion plus noise), and SFDR (spurious-
free dynamic range). There are a number of ways to quantify the distortion and noise of an ADC.
All of them are based on an FFT analysis using a generalized test setup such as shown in Figure
The spectral output of the FFT is a series of M/2 points in the frequency domain (M is the size of
the FFT—the number of samples stored in the buffer memory). The spacing between the points is
fs /M, and the total frequency range covered is dc to fs /2, where f width of each frequency "bin"
(sometimes called the resolution of the FFT) is fs is the sampling rate.
Harmonic distortion is normally specified in dBc (decibels below carrier), although in audio
applications it may be specified as a percentage. It is the ratio of the RMS signal to the RMS value
of the harmonic in question. Harmonic distortion is generally specified with an input signal near
full-scale (generally 0.5 to 1 dB below full-scale to prevent clipping), but it can be specified at any
104
level. For signals much lower than full-scale, other distortion products due to the differential
nonlinearity (DNL) of the converter—not direct harmonics—may limit performance.
Total harmonic distortion (THD) is the ratio of the RMS value of the fundamental signal to the
mean value of the root-sum-square of its harmonics (generally, only the first 5 harmonics are
significant). THD of an ADC is also generally specified with the input signal close to full-scale,
although it can be specified at any level.
Total harmonic distortion plus noise (THD + N) is the ratio of the RMS value of the fundamental
signal to the mean value of the root-sum-square of its harmonics plus all noise components
(excluding dc). The bandwidth over which the noise is measured must be specified. In the case of
an FFT, the bandwidth is dc to fs/2. (If the bandwidth of the measurement is dc to f/2 (the Nyquist
bandwidth), THD + N is equal to SINAD—see below). Be warned, however, that in audio
applications the measurement bandwidth may not necessarily be the Nyquist bandwidth.
Spurious-free dynamic range (SFDR) is the ratio of the RMS value of the signal to the RMS value
of the worst spurious signal regardless of where it falls in the frequency spectrum. The worst spur
may or may not be a harmonic of the original signal. SFDR is an important specification in
communications systems because it represents the smallest value of the signal that can be
distinguished from a large interfering signal (blocker). SFDR can be specified with respect to full-
scale (dBFS) or with respect to the actual signal amplitude (dBc). The definition of SFDR is shown
graphically in Figure 5.
105
Figure 7.4. FFT of a reconstructed signal of ADC
Signal-to-Noise-and-Distortion (SINAD or S/(N + D) is the ratio of the RMS signal

amplitude to the mean value of the root-sum-square (RSS) of all other spectral components,
including harmonics, but excluding dc. SINAD is a good indication of the overall dynamic
performance of an ADC because it includes all components which make up noise and distortion.
SINAD is often plotted for various input amplitudes and frequencies. For a given input frequency
and amplitude, SINAD is equal to THD + N, provided the bandwidth for the noise measurement
is the same for both (the Nyquist bandwidth).
SINAD plots such as these are very useful in evaluating the dynamic performance of
ADCs. SINAD is often converted to effective number-of-bits (ENOB) using the relationship for
the theoretical SNR of an ideal N-bit ADC: SNR= 6.02N + 1.76 dB. The equation is solved for N,
and the value of SINAD is substituted for SNR:
Signal-to-noise ratio (SNR, or sometimes called SNR-without-harmonics) is calculated from the

FFT data the same as SINAD, except that the signal harmonics are excluded from the calculation,
leaving only the noise terms. In practice, it is only necessary to exclude the first 5 harmonics, since
they dominate. The SNR plot will degrade at high input frequencies, but generally not as rapidly
as SINAD because of the exclusion of the harmonic terms.
106
7.1 The Mathematical relationships between SINAD, SNR, AND THD
There is a mathematical relationship between SINAD, SNR, and THD (assuming all are measured
with the same input signal amplitude and frequency. In the following equations, SNR, THD, and
SINAD are expressed in dB, and are derived from the actual numerical ratios S/N, S/D, and
S/(N+D) as shown below:
The above three equations can be solved for the numerical ratios N/S, D/S, and (N+D)/S as follows:
As in the above three equations all the denominators all equal to S, the root sum square of N/S and
D/S is equal to (N+D)/S as follows:
107
Therefore, S/(N+D) must equal:
and hence,
The core of ADC is simulated with different sampling frequency and all the quantities has been
measured in MATLAB. Variation of different quantities with the variation of input frequency is
also measured.
108
Figure 7.5. FFT diagram of ADC with input frequency 500Hz and Sampling 30KHz
Figure 7.6. FFT diagram of ADC with input frequency 100Hz and Sampling 5KHz
109
Figure 7.7. Comparison of performance parameter with Sampling Frequency
Figure 7.8. Comparison of performance parameter with Input Frequency
110
Conclusion and Future Work
CHAPTER VIII
After acquiring knowledge about seismic sensors and their applications, specifications for
an A/D converter to be integrated on a chip have been elaborated. Next, an extensive literature
research has been made, to select the Differential ADC architecture. The SAR ADC architecture
has been chosen because of its low power consumption, lack of latency, high enough resolution,
high enough frequency to avoid parallelism, simple principle and its popularity in multiplexed data
acquisition systems. Detailed specifications for the ADC have been elaborated. Its ideal transfer
characteristic and timing diagrams have been defined. The following building blocks of the ADC
core have been designed such as, comparator, Shift register, switches, delay elements, and drivers.
As soon as all building blocks met their requirements, they have been put together and pre-layout
simulations of the entire ADC core and post-layout simulations of individual blocks have been
carried out. These simulations confirm the correct operation of the ADC core.
Schematic design of each and individual block is completed, and integrated result is also taken for
the schematic. Output results are in the desired form though it is not exactly like manually
calculated Digital data. Similarly, the layout of individual blocks has done, and Post-layout
simulation is checked for every block except DAC. The results of the post-layout simulation are
within our required range. Other than these ENOB, SINAD, SNDR, and SFDR are also calculated.
Layout strategy of DAC is made already but due to lack of time layout of DAC yet not done.
Future work
1) Layout strategy has already been done in XL sheet. In the future layout of DAC needs
to be done according to XL sheet.
2) Layouts of individual components are already made. In the future integration of all those
components will be done.
3) Measuring of INL and DNL.

111
4) For N bit Differential ADC total N+2 clock pulses are required. But our maximum
input frequency is 500 Hz. Our sampling frequency is 31.25 kHz. Hence, some excess clock pulses
are available. Some calibration algorithm can be used by using those excess clock pulses and a
memory element for getting more accurate results.
112
References
References
[1] Chung-Yi Li, Hao-Tsun Chao, and Chin Hsia, “A 10-Bit Area-Efficient SAR ADC with Re-
Usable Capacitive Array,” in Anti-Counterfeiting, Security and Identification on 24-26 Aug, 2012
at Taipei. IEEE Conference Publication in Aug, 2012. pp. 1-5.
[2] Prakruthi T.G, and Siva Yellampalli, “Design and Implementation of Sample and Hold Circuit
in 180nm CMOS Technology”, in Advances in Computing, Communications, and Informatics
(ICACCI), 2015 International Conference on 10-13 Aug, 2015 at Kochi. IEEE Conference
Publication in Aug, 2012. pp. 1148-1151.
[3] Silvia Dondi, DavideVecchi, Andrea Boni, and Marco Bigi, “A 6-bit, 1.2 GHz Interleaved SAR
ADC in 9Onm CMOS”, 2006 Ph.D. Research in Microelectronics and Electronics. IEEE
International conference at Otranto in 2006. pp. 301-304.
[4] Wee Leong Son, Hasmayadi Abdul Majid, and Rohana Musa, “High-Resolution 12-Bit
Segmented Capacitor DAC in Successive Approximation ADC”, World Academy of Science,
Engineering and Technology. International Journal of Electrical, Computer, Energetic, Electronic
and Communication Engineering Vol:6, No:12, 2012. pp. 1383-1386.
[5] H.Khurramabadi ADC Converters (Lecture 13).UC Berkeley Course, Analog-Digital

Interfaces in VLSI Technology EE247.2006
[6] [Razavi2001] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill
Higher Education, 2001
[7] Raheleh Hedyati “A Study of Successive Approximation Registers and Implementation of an
Ultra-Low Power 10-bit SAR ADCin 65nm CMOS Technology”, Master thesis, Linkoping
University, 2011.
[8] M. Saberi, R. Lotfi, K. Mafinezhad, W. A. Serdijn, “Analysis of Power Consumption and

Lineary in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs,
”IEEE Transactions on Circuits and Systems, vol. 58, no. 8, August 2011. 73
113
References
[9] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92mW10-bit 50-MS/s SAR ADC in
0.13 um CMOS process,” in IEEE Symp. VLSI Circuits Dig., Jun. 2009, pp. 236–237.
[10] Hesener, M.; Eichler, T.; Hanneberg, A.; Herbison, D.; Kuttner, F.; Wenske, H.; “A 14 bit
40MS/s Redundant SAR ADC with 480 MHz Clock in 0.13um CMOS, ” Solid-State Circuit
conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 248-600, 11-
15 Feb. 2007.
[11]Gilbert Promitzer, 2001, “12-bit Low-Power Fully Differential Switched Capacitor

Noncalibrating Successive Approximation ADC With 1MS/s,” EEE JSSC, 36(7), pp. 1138–1143.
[12] [Meinerzhagen2008] Pascal Meinerzhagen, “Design of a 12-bit low-power SAR A/D
Converter for a Neurochip”, Master’s Thesis, Microelectronic Systems Laboratory, Swiss Federal
Institute of Technology, Lausanne (EPFL), Switzerland and University of California, Merced,
California, USA, 2008
[13] J. McNeill, M. Coln, and B. Larivee, “A split-adc architecture for deterministic digital
background calibration of a 16b 1 MS/s adc,” IEEE Journal of Solid-State Circuits, vol. 1, pp.
2437–2445, Feb 2005.
[14] M. Flynn, C. Donovan, and L. Sattler, “Digital calibration incorporating redundancy of fash
adcs,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.
50, no. 5, pp. 205–213, 2003.
[15] Instrumentation in Earthquake Seismology, by Jens Havskov and Gerardo Alguacil June 2002
114

2

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

2

Uploaded by

Copyright:

Available Formats

Table of Contents

1.1 Seismic Sensor overview ...................................................................................................... 3

Sensor Types ............................................................................................................................... 3

1.2 Block diagram Seismic Sensor System................................................................................. 5

Motivation and Organization of Thesis .......................................................................................... 6

Data Converters for Seismic Sensors .............................................................................................. 8

2.1 Basic ADC properties ........................................................................................................... 9

2.2 Errors associated with ADC................................................................................................ 10

2.3 Multi-channel ADC ............................................................................................................ 13

2.4 Oversampling for improvement of the dynamic range ....................................................... 13

2.5 ADC architectures in comparison ....................................................................................... 14

2.6. Advantages of the SAR ADC ............................................................................................ 17

2.7. Types of SAR ADC ........................................................................................................... 18

2.8. Specifications of ADC ....................................................................................................... 20

Single Ended Charge-Redistribution SAR ADC .......................................................................... 22

Fully Differential SAR ADC ........................................................................................................ 33

5.1 Advantages of Differential ADC over Single ended ADC ................................................. 33

5.2 Architecture of Differential ADC ....................................................................................... 35

5.3 Architecture of Dynamic Comparator ................................................................................ 42

5.5 Architecture of DAC Control Logic ................................................................................... 51

5.6 Architecture of Delay Buffer .............................................................................................. 56

5.7 Architecture of Track and Hold .......................................................................................... 57

5.8 Architecture of Capacitive DAC ......................................................................................... 63

Multi-Channel Fully Differential SAR ADC ................................................................................ 68

Summary of Timing Diagram: .................................................................................................. 71

6.1 Architecture of Single-Ended to Differential Converter ................................................ 72

6.2 Architecture of Analog Multiplexer.................................................................................... 79

6.3 Architecture of 14-bit De-Multiplexer ................................................................................ 83

6.4 Architecture of 14-bit Multiplexer ...................................................................................... 87

6.5 Architecture of 14-bit Output Register ............................................................................... 90

6.6 Architecture of Clock Network ........................................................................................... 93

6.7 Architecture of Register Control ......................................................................................... 98

Validation of Fully Differential SAR ADC ................................................................................ 102

Conclusion and Future Work ...................................................................................................... 111

References ................................................................................................................................... 113

Figure 1.2. (a) Sea seismic Sensor (b) Geophone 4

Figure 1.3. Block diagram of Seismic Sensor System 5

Figure 3.1. The analog to the digital conversion process. 8

Figure 3.2. Offset error. 11

Figure 3.3. Gain error. 11

Figure 3.4. Full scale error. 12

Figure 3.5. Differential non-linearity. 12

Figure 3.6. Missing code. 13

Figure 3.7. ADC architectures in comparison. 14

Figure 3.8. ADC architectures, applications, resolution and sampling rates. 17

Figure 3.9. (a) Single-Ended Unipolar (b) Single-Ended True Bipolar 18

Figure 3.10. (a) Pseudo-Differential Unipolar (b) Pseudo-Differential Bipolar 19

(c) Pseudo-Differential True Bipolar

Figure 4.1. Latch-Up in CMOS Process 24

Figure 4.2. Pin Configuration 25

Figure 4.3. Dummy Layers 27

Figure 4.6. GDS of 14- bit Single ended SAR ADC 30

Figure 5.1. Conventional Fully Differential SAR ADC 36

Figure 5.2. Fully Differential SAR ADC with Monotonic Switching 36

Figure 5.3. Flow chart of the proposed ADC 37

Figure 5.4. (a) Conventional Switching (b) Monotonic Switching 38

Figure 5.5. (a) Conventional Switching for 3-bit DAC 40

Figure 5.5. (b) Monotonic Switching for 3-bit DAC 41

Figure 5.6. Architecture of Dynamic Comparator 43

Figure 5.7. Schematic diagram of Dynamic Comparator 44

Figure 5.8. Output response of Dynamic Comparator 45

Figure 5.9. Layout of Dynamic Comparator 46

Figure 5.10. Schematic diagram of Transmission Gate based D FF 47

Figure 5.11. Layout of Transmission Gate based D FF 48