VHDL Class Project for 6th Sem ECE-CSE1

Enrolment
S.No. Name VHDL Project Title
Number
Write a VHDL program for a full adder that takes two
1 111502821 Ayush Ranjan binary numbers and a carry-in as inputs and outputs the
sum and carry-out.
Design a decoder that takes a 4-bit binary number as
2 211502821 Pratham kakkar input and activates one of its 16 outputs based on the
input value.
Implement a multiplexer with two data inputs, a select
3 211507322 Himanshi Chandra
line, and a single output.
Create a VHDL program for a 4-to-1 priority encoder
4 311502821 Kartik bhardwaj
that prioritizes higher-order bits.
Write code for a comparator that compares two 8-bit
5 311507322 Mukund Sinha binary numbers and outputs a signal indicating if they
are equal, greater than, or less than.
Design a combinational circuit that converts a 4-bit
6 511507322 S.P.Chandra Sai
Gray code to its equivalent binary representation.
Implement a parity generator that takes a data word and
7 711502821 Devansh Singhal generates an even or odd parity bit based on the chosen
mode.
Write VHDL code for a magnitude comparator that
8 811502821 RAVI RAJ
compares the magnitudes of two signed numbers.
Design a combinational circuit to implement a 2's
9 911502821 Viresh Singhal
complement number system.
Create a VHDL program for a Booth multiplier that
10 911507322 Khubab Iftekhar
multiplies two signed numbers.
11 1011507322 Prateek Sharma Write code for a T flip-flop that uses a clock signal.
Design a synchronous counter that counts from 0 to 9
12 1211502821 Ashun
and resets to 0 on a control signal.
Implement a shift register with a parallel load
13 1411502821 Harshit Bansal
capability and a specific shift direction (e.g., left shift).
Write VHDL code for a finite state machine (FSM) that
14 1411507322 Ratna Mishra controls a traffic light with three states (red, yellow,
green).
Design a Moore FSM that detects a specific sequence
15 1511507322 Nikhil
of button presses.
Implement a Mealy FSM that outputs a signal based on
16 1611502821 Ripunjay Sharma
the current state and input conditions.
Write VHDL code for a ring counter with a specific
17 1611507322 Raghav kaushik
number of stages (e.g., 4-stage ring counter).
Design a counter that counts up or down based on a
18 1711502821 Shonima gupta
control signal.
19 2111502821 Tushar Sharma Write code for a JK flip-flop.
 Write VHDL code for a random number generator
20 2311502821 Vishal Gupta
using a linear feedback shift register (LFSR).
Implement a parity checker circuit that detects even or
21 2411502821 Harshika Kapoor
odd parity errors in a data stream.
Write VHDL code for a Johnson counter, a variation of
22 2511502821 Jayani Sehgal
a ring counter with specific output behavior.
Design a combinational circuit that implements a
23 2611502821 Vishal Bhalla specific mathematical function (e.g., square root
approximation).
Implement a look-up table (LUT) for a complex
24 2711502821 Aadhar Tuteja
function and use it in your design.
Write VHDL code for a carry look-ahead adder for
25 2911502821 Gaurav chahar
faster addition operations.
Deepanshu kumar Design a decoder with additional functionalities like
26 3011502821
rai enabling/disabling outputs.
Implement a comparator that compares two signed
27 3211503821 HARSH JOSHI
numbers and outputs their relative magnitude.
Design a combinational circuit to implement a specific
28 3311502821 Kartik Prasad
error-correcting code.
Write VHDL code for a decoder-driver circuit that
29 3411502821 Aryan Mehndiratta activates and illuminates a specific LED based on a
binary input.
Design a combinational circuit that implements a 3-
30 3811502821 Sourav Kumar
to-8 decoder with active-low outputs.
Implement a multiplexer with multiple data inputs (e.g.,
31 3911502821 Sujal Garg
4) and a select signal to choose the output.
Write VHDL code for a priority encoder that prioritizes
32 4011502821 Archit Sharma lower-order bits (opposite of question 4 in previous
list).
Design a combinational circuit to convert a BCD
33 4111502821 Divyanshi (Binary-Coded Decimal) number to its equivalent 7-
segment display representation.
Implement a code converter that translates between two
34 4211502821 Ramik Tiwari
different encoding schemes (e.g., ASCII to EBCDIC).
Write VHDL code for a full adder with overflow
35 4311502821 Akshay Bisht
detection.
Design a combinational circuit that implements a
36 4411502821 Vinayak Garg specific Boolean expression (provided in truth table
format).
Implement a magnitude comparator for unsigned
37 4611502821 Varun Vij numbers with separate outputs for equal, greater than,
and less than.
Write VHDL code for a circuit that performs logical
38 4711502821 Satyam Tiwari
left shift operation on a binary number.
Design a combinational circuit to implement a specific
39 4911502821 Prabhat Mishra
error detection scheme (e.g., Hamming code).
 Implement a decoder with additional functionalities
40 5011502821 Piyush Banga
like output enable and decoding specific bit patterns.
Write VHDL code for a comparator that compares two
41 5111502821 Tanishq Jain binary numbers and outputs their Hamming distance
(number of differing bits).
Design a combinational circuit that performs a specific
42 5411502821 Manas sisodia bitwise operation (e.g., AND, OR, XOR) on two
numbers.
Implement a multiplexer with additional
43 5511502821 Isha Mehra functionalities like control signal for all-zero or all-one
output.
Write VHDL code for a JK flip-flop with preset and
44 5711502821 Musharraf Hayat
clear functionalities.
Design a synchronous counter that counts from a
45 5911502821 Pranav Bajaj specific starting value to a maximum value and then
wraps around.
Implement a shift register with a serial input and
46 6011502821 Gaurish Sehgal
parallel outputs for all stages.
Write VHDL code for a finite state machine (FSM)
47 6211502821 Sumegha Gupta that controls a simple traffic light with pedestrian
crossing signal.
Design a Moore FSM that detects a specific number
48 6511502821 Sakshi Gupta
of consecutive button presses.
Implement a Mealy FSM that outputs a control
49 6911502821 Varun Sharma signal based on the current state and a specific input
condition.
Write VHDL code for a counter with a variable
Vikram Singh
50 7211502821 counting direction based on an additional control
Chandel
signal.
Design a synchronous counter with asynchronous
51 7311502821 Dishansh joshi
reset capability (active-high or active-low).
Implement a debouncing circuit for a pushbutton
52 7511502821 Sribash Paul
using a D flip-flop and timer functionality.
Write VHDL code for a modulo-N counter that
53 7611502821 Vishav bhatla
counts from 0 to N-1 and then resets.
Design a synchronous counter with load
54 8311502821 Vaibhav goyal
functionality to initialize the counter value.
Implement a sequence detector circuit that identifies
55 8511502821 Tarun dagar a specific sequence of events with a timeout
mechanism.
Write VHDL code for a state machine-based
56 8711502821 Saksham kediyal controller for a simple door lock system with keypad
entry.
Design a Moore FSM that outputs a different signal
57 8811502821 Lakshya singhal
for each state of the machine (useful for debugging).
 Implement a pulse generator circuit that creates a
58 9211502821 Abhishek Paul single pulse of a specific duration based on a control
signal.
Write VHDL code for a decoder with an enable signal.
The decoder should only activate its outputs when the
59 9411502821 Sparsh Verma
enable signal is active (high or low, depending on your
chosen logic).
Design a combinational circuit that implements a
60 9511502821 Bhavya Minocha specific function related to sets (e.g., union,
intersection, difference) of two binary numbers.
Implement a BCD adder that adds two BCD numbers
61 9711502821 Sorashi Seth and outputs the result in BCD format, handling
potential overflows (e.g., adding 9 and 9).
Design a combinational circuit that performs a specific
bitwise rotation operation (e.g., left rotate by N bits,
62 9811502821 Paakhi Sharma right rotate by N bits) on a binary number. You can
choose the rotation amount (N) as a parameter to the
circuit.