Digital Design Report

Cover Page
LAB 01: Logic Gates

2022/5/1
2022/5/7
Digital Logic Lab (ECE 241)
Spring 2022
Suzhou City University
Suzhou, PR China
Group 2
YangYing
2017454072
1
Design
NOT:
Boolean expression:Y=~A
Theoretical Truth Table:
A Y
0 1
1 0
XNOR:
Boolean expression:Y=AB+~A~B
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
NOR3:
Boolean expression:Y=~(A1+A0+B)
A1 A0 B Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
2
AND4:
Boolean expression:Y=A1A0B1B0
A1 A0 B1 B0 Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
3
Simulation
NOT Gate
4
XNOR Gate
5
NOR3 Gate
6
AND4 Gate
7
Data Analysis
NOT :
A Y(Simulation) Y(Theoretical)
0 1 1
1 0 0
The Simulation Truth table from the Input and Output Traces matches the theoretical truth table.
XNOR:
A B Y(Simulation) Y(Theoretical)
0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1
NOR3:
A1 A0 B Y(Simulation) Y(Theoretical)
0 0 0 1 1
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 0 0
8
AND4:
A1 A0 B1 B0 Y(Simulation) Y(Theoretical)
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 0 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 0 1 0 0
1 1 1 0 0 0
1 1 1 1 1 1
9
HDL Code
NOT:
module NOT1 (input logic A ,
output logic Y);
assign Y= ~A;
endmodule
XNOR:
module XNOR2 (input logic A ,B,
output logic Y);
assign Y= ~(A^B);
endmodule
NOR3:
module NOR3 (input logic A1,A0,B,
output logic Y);
assign Y=~(A1|A0|B);
endmodule
AND4:
module AND4 (input logic A1 , A0 , B1, B0
output logic Y);
assign Y= A1∙A0∙B1∙B0 ;
endmodule
10
Cover Page
LAB 02: Universal Gates-I

2022/5/7
2022/5/10
Spring 2022
Suzhou, PR China
Group 2
YangYing
2017454072
1
Design
a)
NOT Gate
input: A
output:Y
Boolean expression:Y=~A
Circuit schematic:
Theoretical Truth table:

A Y
0 1
1 0
K-map:
A
~A A
1 0
Boolean simplification:
Y=~A
2
BUF Gate
input:A
output:Y
Boolean expression:Y=A
Circuit schematic:

A Y
0 0
1 1
K-map:
A
~A A
0 1
Y=A
3
AND Gate
inputs:A,B
output:Y
Boolean expression:Y=AB
Circuit schematic:

A B Y
0 0 0
0 1 0
1 0 0
1 1 1
K-map:
B
~B B
A
~A 0 0
A 0 1
Y=AB
4
OR Gate
inputs:A,B
output:Y
Boolean expression:Y=A+B
Circuit schematic:

A B Y
0 0 0
0 1 1
1 0 1
1 1 1
K-map:
B
~B B
A
~A 0 1
A 1 1
Y=A+B
5
NOR Gate
inputs:A,B
output:Y
Boolean expression:Y=~(A+B)
Circuit schematic:

A B Y
0 0 1
0 1 0
1 0 0
1 1 0
K-map:
B
~B B
A
~A 1 0
A 0 0
Y= ~A~B= ~(A+B)
6
XOR Gate
inputs:A,B
output:Y
Boolean expression:Y= A~B+ ~AB
Circuit schematic:

A B Y
0 0 0
0 1 1
1 0 1
1 1 0
K-map:
B
~B B
A
~A 0 1
A 1 0
Y= A~B+~AB
7
XNOR Gate
inputs:A,B
output:Y
Boolean expression:Y= AB+~A~B
Circuit schematic:

A B Y
0 0 1
0 1 0
1 0 0
1 1 1
K-map:
B
~B B
A
~A 1 0
A 0 1
Y= ~A~B+AB
8
b) F(A,B,C,D)=Σ(4,5,6,7,9,13,15)
inputs:A,B,C,D
output:Y
Boolean expression:Y= ~AB+BD+A~CD
Circuit schematic:

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
9
K-map:
CD
~C~D ~CD CD C~D
AB
~A~B 0 0 0 0
~AB 1 1 1 1
AB 0 1 1 0
A~B 0 1 0 0
Y= ~AB+BD+A~CD
10
Simulation
NOT Gate
11
BUF Gate
12
AND Gate
13
OR Gate
14
NOR Gate
15
XOR Gate
16
XNOR Gate
17
b)
F(A,B,C,D)=Σ(4,5,6,7,9,13,15)
18
Data analysis
a) Simulation Truth table
NOT Gate
A Y
0 1
1 0
BUF Gate
A Y
0 0
1 1
AND Gate
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
19
NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
XOR Gate
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
XNOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
20
b) Simulation Truth table
F(A,B,C,D)=Σ(4,5,6,7,9,13,15)
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
21
HDL Code
a)
NOT:
module NOT (input logic A ,
output logic Y);
assign Y= ~A;
endmodule
BUF:
module BUF (input logic A ,
output logic Y);
assign Y= A;
endmodule
AND:
module AND (input logic A,B,
output logic Y);
assign Y=A&B;
endmodule
OR:
module OR(input logic A,B
output logic Y);
assign Y= A|B ;
endmodule
22
NOR:
module NOR(input logic A,B
output logic Y);
assign Y= ~(A|B) ;
endmodule
XOR:
module XOR(input logic A,B
output logic Y);
assign Y= A^B ;
endmodule
XNOR:
module XNOR(input logic A,B
output logic Y);
assign Y= ~(A^B) ;
endmodule
b)
module Vox (input logic A,B,C,D
output logic Y);
assign Y= ~A&B|B&D|A~CD;
endmodule
23
Cover Page
LAB 03: Universal Gates-II

2022/5/10
2022/5/17
Spring 2022
Suzhou, PR China
Group 2
YangYing
2017454072
1
Design
a)
NOT Gate
input: 𝐴
output:𝑌
Boolean expression: 𝑌 = 𝐴̅
Circuit schematic:

𝐴 𝑌
0 1
1 0
K-map:
𝐴
𝐴̅ 𝐴
1 0
𝑌 = 𝐴̅
2
BUF Gate
input:𝐴
output:𝑌
Boolean expression:𝑌 = 𝐴
Circuit schematic:

𝐴 𝑌
0 0
1 1
K-map:
𝐴
𝐴̅ 𝐴
0 1
𝑌=𝐴
3
AND Gate
inputs:𝐴, 𝐵
output:𝑌
Boolean expression:𝑌 = 𝐴𝐵
Circuit schematic:

𝐴 𝐵 𝑌
0 0 0
0 1 0
1 0 0
1 1 1
K-map:
𝐵
𝐵̅ 𝐵
𝐴
𝐴̅ 0 0
𝐴 0 1
𝑌 = 𝐴𝐵
4
OR Gate
inputs:𝐴, 𝐵
output:𝑌
Boolean expression:𝑌 = 𝐴 + 𝐵
Circuit schematic:

𝐴 𝐵 𝑌
0 0 0
0 1 1
1 0 1
1 1 1
K-map:
𝐵
𝐵 𝐵
𝐴
𝐴̅ 0 1
𝐴 1 1
𝑌 =𝐴+𝐵
5
NOR Gate
inputs:𝐴, 𝐵
output:𝑌
Boolean expression:𝑌 = ̅̅̅̅̅̅̅̅
𝐴+𝐵
Circuit schematic:

𝐴 𝐵 𝑌
0 0 1
0 1 0
1 0 0
1 1 0
K-map:
𝐵
𝐵̅ 𝐵
𝐴
𝐴̅ 1 0
𝐴 0 0
𝑌 = 𝐴̅𝐵̅ = ̅̅̅̅̅̅̅̅
𝐴+𝐵
6
XOR Gate
inputs:𝐴, 𝐵
output:𝑌
Boolean expression:𝑌 = 𝐴𝐵̅ + 𝐴̅𝐵
Circuit schematic:

𝐴 𝐵 𝑌
0 0 0
0 1 1
1 0 1
1 1 0
K-map:
𝐵
𝐵̅ 𝐵
𝐴
𝐴̅ 0 1
𝐴 1 0
𝑌 = 𝐴𝐵̅ + 𝐴̅𝐵
7
XNOR Gate
inputs:𝐴, 𝐵
output:𝑌
Boolean expression:𝑌 = 𝐴𝐵 + 𝐴̅𝐵̅
Circuit schematic:
Theoretical Trutℎ 𝑡𝑎𝑏𝑙𝑒:

𝐴 𝐵 𝑌
0 0 1
0 1 0
1 0 0
1 1 1
K-map:
𝐵
𝐵̅ 𝐵
𝐴
𝐴̅ 1 0
𝐴 0 1
Y= 𝐴̅𝐵̅ + 𝐴𝐵
8
b)𝐹(𝐴, 𝐵, 𝐶, 𝐷) = 𝛴(4,5,6,7,9,13,15)
inputs:𝐴, 𝐵, 𝐶, 𝐷
output:𝑌
Boolean expression:𝑌 = 𝐴̅𝐵 + 𝐵𝐷 + 𝐴𝐶̅ 𝐷
Circuit schematic:

𝐴 𝐵 𝐶 𝐷 𝑌
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
9
K-map:
𝐶𝐷
𝐶̅ 𝐷
̅ 𝐶̅ 𝐷 𝐶𝐷 ̅
𝐶𝐷
𝐴𝐵
𝐴̅𝐵̅ 0 0 0 0
𝐴̅𝐵 1 1 1 1
𝐴𝐵 0 1 1 0
𝐴𝐵̅ 0 1 0 0
𝑌 = 𝐴̅𝐵 + 𝐵𝐷 + 𝐴𝐶̅ 𝐷
10
Simulation
NOT Gate
11
BUF Gate
12
AND Gate
13
OR Gate
14
NOR Gate
15
XOR Gate
16
XNOR Gate
17
b)
𝐹(𝐴, 𝐵, 𝐶, 𝐷) = 𝛴(4,5,6,7,9,13,15)
18
Data analysis
a) Simulation Truth table
NOT Gate
A Y
0 1
1 0
BUF Gate
A Y
0 0
1 1
AND Gate
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
19
NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
XOR Gate
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
XNOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
20
b) Simulation Truth table
𝐹(𝐴, 𝐵, 𝐶, 𝐷) = 𝛴(4,5,6,7,9,13,15)
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
21
HDL Code
a)
NOT:
module NOT (input logic A ,
output logic Y);
assign Y= ~A;
endmodule
BUF:
module BUF (input logic A ,
output logic Y);
assign Y= A;
endmodule
AND:
module AND (input logic A,B,
output logic Y);
assign Y=A&B;
endmodule
OR:
module OR(input logic A,B
output logic Y);
assign Y=A|B ;
endmodule
22
NOR:
module NOR(input logic A,B
output logic Y);
assign Y=~(A|B);
endmodule
XOR:
module XOR(input logic A,B
output logic Y);
assign Y=A^B;
endmodule
XNOR:
module XNOR(input logic A,B
output logic Y);
assign Y=~(A^B) ;
endmodule
b)
module Vox (input logic A,B,C,D
output logic Y);
assign Y=(A|B)&(~A|D)&(B+~C);
endmodule
23

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Cover Page

LAB 01: Logic Gates

LAB 02: Universal Gates-I

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

LAB 03: Universal Gates-II

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Truth table:

Theoretical Trutℎ 𝑡𝑎𝑏𝑙𝑒:

Theoretical Truth table:

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