Digital Electronics Lab Manual

3rd Semester, B.E, ECE

[21EC3C02]

Let it Go Up

Department of Electronics & Communication Engineering

The National Institute of Engineering, Mysuru
(An Autonomous Institute under VTU, Belagavi)
 CONTENTS

PART-A
Realize using Digital Trainer Kits

Page
Expt. No. Title of the Experiment
No.
Study of Trainer kit, Verification of Logic gates and
0 1-8
Realization of NAND and NOR as Universal gates.
Simplification and realization of Boolean expressions
using logic gates/universal gates.
1 (a) Demorgan’s Theorem for 2 variables. 9 - 16
(b) The sum-of product and product-of-sum
expressions using universal gates.
Design and implement
(a) Full Adder and subtractor using basic logic 17 - 21
2 gates.
(b) Design and implement 4-bit Parallel Adder/
22 - 23
subtractor using IC 7483.
Design and Verify
a. Binary to Gray code converter and vice-versa
3 b. Binary to Excess-3 code converter
24 - 31
c. 1-bit comparator and 4-bit comparator
Design and implementation of Multiplexers, De-
4 multiplexers and Priority Encoder
32 - 41

Shift Registers
Ring Counter
5 42 - 53
Johnson Counter
Mod-N Counter
 PART-B

Simulation, Synthesis and Implementation using Vivado and Artix 7/ Zynq

7 Developmental Boards. Verifying and optimizing the design by analyzing
the CLB’s and I/O’s for the given FPGA board.

Write the Verilog code for Logic Gates in

6 54 - 59
structural, data-flow and behavioral flow.
Write the Verilog code for in data-flow and
behavioral flow.
a. Full adder and 4-bit parallel adder
7 b. 2:1, 4:1 and 8:1 Mux 60 - 71
c. 1:2, 4:1 and 8:1 Demux
d. 8:3 encoder
e. 3:8 decoder
Write the Verilog code for in behavioral flow.
a. SR and D latch
b. JK, D and T flipflop
8 72- 84
c. 4 bit up/down counter
d. Design and verify 4-bit up/down counter
using FSM.
 STUDY EXPERIMENT
STUDY OF TRAINER KIT, VERIFICATION OF LOGIC GATES AND
REALIZATION OF NAND AND NOR AS UNIVERSAL GATES.

AIM: To study logic gates and to realize NAND and NOR as Universal gates.

COMPONENTS AND EQUIPMENTS REQUIRED:

Quad 2 input NAND gate (IC7400), Quad 2 input NOR gate (IC7402), Hex NOT gate
(IC 7404),
Quad 2 input AND gate (IC7408), Quad 2 input OR gate (IC7432), Quad 2 input XOR gate
(IC7486), Triple 3 input NAND gate (IC7410), Triple 3 input AND gate (IC7411), Dual 4
input AND gate (IC 7421), Dual 4 input NAND gate (IC7420), Digital IC trainer kit, Patch
chords.

NAND Gate
Logic Symbol Pin Diagram of IC 7400 Truth Table
(Quad 2-Input NAND
gate)

Input Outpu
s t
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

NOR Gate
Logic Symbol Pin Diagram of IC 7402 Truth Table
(Quad 2-Input NOR gate)

Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

NOT Gate

1
Logic Symbol Pin Diagram of IC 7404 Truth Table
(1-Input NOT Gate Hex Inverter)

Input Output
A Y
0 1
1 0

AND Gate
Logic Symbol Pin Diagram of IC 7408 Truth Table
(Quad 2-Input AND gate)
Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate
Logic Symbol Pin Diagram of IC 7432 Truth Table
(Quad 2-Input OR gate)
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

XOR Gate
Logic Symbol Pin Diagram of IC 7486 Truth Table
(Quad 2-Input XOR gate)
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

XNOR Gate

2
Logic Symbol Truth Table

Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1

3 Inputs NAND Gate

Logic Symbol Pin Diagram of IC 7410 Truth Table
(Triple 3-Input NAND gate)
Inputs Output
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

3 Inputs AND Gate

Logic Symbol Pin Diagram of IC 7411 Truth Table
(Triple 3-Input AND gate)
Inputs Output
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

3
 4 Inputs AND Gate
Logic Symbol Truth Table

Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
Pin Diagram of IC 7421 0 0 1 0 0
( Dual 4-input AND gate) 0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
4 inputs NAND Gate
Logic Symbol Truth Table

Inputs Output
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
Pin Diagram of IC 7420 0 1 0 1 1
( Dual 4-input NAND gate) 0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Realization of NAND and NOR as Universal gates:

4
 (I) By using NAND gates :

Realization of AND function: TRUTH

TABLE:
Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

Realization of OR function: TRUTH

TABLE:

Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Realization of NOT function: TRUTH

TABLE:
Input Output
A Y
0 1
1 0

Realization of X-OR function: TRUTH TABLE:

Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

5
Realization of X-NOR function: TRUTH TABLE:

Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1

(II) NOR gates

Realization of an AND function: TRUTH TABLE:
Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

6
Realization of an OR functions: TRUTH TABLE:
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Realization of NOT function: TRUTH

TABLE:

Inputs Output
A Y
0 1
1 0

Realization of X-OR function: TRUTH

TABLE:

Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Realization of X-NOR function: TRUTH

TABLE:

Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1

7
PROCEDURE:
1) Check the IC and fix it to the socket.
2) Rig up the circuit as shown in the logic diagram.
3) Apply various input data to the circuit via logic switches.
4) Note down the corresponding output and verify the truth table.

RESULT:
All the logic gates are verified and NAND and NOR gates are realized as Universal gates.

8
 EXPERIMENT NO.1
VERIFICATION OF SUM-OF-PRODUCT AND PRODUCT-OF-SUM EXPRESSION

AIM: To realize the Sum-Of –Product (SOP) and Product-Of-Sum (POS) expression using universal and
basic gates.

COMPONENTS AND EQUIPMENT REQUIRED:

NAND gate(IC 7400), NOR gate (IC 7402), NOT gate (IC 7404), AND gate(IC 7408), OR gate(IC
7432), Digital IC trainer kit, patch cords.

VERIFICATION OF SOP EXPRESSIONS:

a) Y= f (a, b, c) = 𝒂 𝒃 𝒄 + a 𝒃 𝒄 + a 𝒃 c
= ∑(𝟎, 𝟒, 𝟓)
Y= 𝒃 𝒄 (𝒂 + a) + a 𝒃 c
Y= 𝒃 𝒄 + a 𝒃 c
Y= 𝒃 ( 𝒄 + a c)
Y= 𝒃 ( 𝒄 + a) ( 𝒄 + c)
Y= 𝒃 ( 𝒄 + a)

Simplification Using K-Map:

i) (0,4) 𝒃𝒄
ii) (4,5) a𝒃

Y= 𝒃 𝒄 + a 𝒃
Y= 𝒃 ( 𝒄 + a)

9
LOGIC DIAGRAMS:
USING BASIC GATES:

USING NAND GATES:

Y=a𝒃 +𝒃𝒄
𝒀 = 𝒂𝒃 + 𝒃 𝒄 = 𝒂𝒃 ⦁ 𝒃 𝒄

Y= 𝒀 = 𝒂𝒃 ⦁ 𝒃 𝒄

10
 USING NOR GATES:

Y= 𝒃 (a + 𝒄 )
𝒀= 𝒃 (𝒂 + 𝒄 )
=𝒃+ 𝒂+𝒄
Y= 𝒀 = 𝒃 + 𝒂 + 𝒄

TRUTH TABLE:

Inputs Outputs
a b c Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

b) Y= f (a, b, c, d) = 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄𝒅 + 𝒂𝒃 𝒄𝒅 + 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄 𝒅 + 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄𝒅 +abcd

== ∑(𝟑, 𝟔, 𝟕, 𝟗, 𝟏𝟏, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓)
Y= 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄 𝒅 +abcd +𝒂𝒃 𝒄𝒅 + 𝒂𝒃 𝒄𝒅 + 𝒂𝒃𝒄𝒅 + 𝒂𝒃𝒄𝒅
Y= 𝒂𝒄𝒅(𝒃 + 𝒃) + 𝒃𝒄𝒅(𝒂 + 𝒂) + 𝒂𝒃𝒄 𝒅 +acd (𝒃 + 𝒃 ) + 𝒂 𝒄𝒅(𝒃 + 𝒃)
Y= 𝒂𝒄𝒅 + 𝒃𝒄𝒅 + 𝒂𝒃𝒄 𝒅 + acd + 𝒂 𝒄𝒅
Y= 𝒄𝒅 (𝒂 + 𝒂) + 𝒃𝒄𝒅 + 𝒂𝒃𝒄 𝒅 + 𝒂 𝒄𝒅
Y= 𝒄𝒅 + 𝒃𝒄𝒅 + 𝒂𝒃𝒄 𝒅 + 𝒂 𝒄𝒅
Y= 𝒅 (𝐜 + 𝐚𝐜) + 𝒅(𝒃𝒄 + 𝒂𝒃𝒄 )
Y= 𝒅 (𝐜 + 𝐚𝐜) + 𝒅𝒃(𝒄 + 𝒂𝒄 )
Y= (𝒅 + 𝒅𝒃)(𝒄 + 𝒂𝒄 )
Y= (𝒅 + 𝒅)(𝒅 + 𝒃)(𝒄 + 𝒂)(𝒄 + 𝒄)
Y=(𝒅 + 𝒃)(𝒄 + 𝒂)

11
 Simplification Using K-Map:

i) (12,13,14,15) ab
ii) (9,11,13,15) ad
iii) (3,7,11,15) cd
iv) (7,6,14,15) bc

Y= 𝒂𝒃 + 𝒂𝒅 + 𝒄𝒅 + 𝒃𝒄
Y= 𝒂(𝒃 + 𝒅) + 𝒄(𝒅 + 𝒃)
Y= (𝒂 + 𝒄)(𝒃 + 𝒅)

LOGIC DIAGRAM:
USING BASIC GATES:

12
 USING NAND GATES:
Y= 𝒂𝒃 + 𝒂𝒅 + 𝒄𝒅 + 𝒃𝒄
𝒀= 𝒂𝒃 ⦁ 𝒃𝒄 ⦁ 𝒄𝒅 ⦁ 𝒂𝒅
Y = 𝒀= 𝒂𝒃 ⦁ 𝒃𝒄 ⦁ 𝒄𝒅 ⦁ 𝒂𝒅

USING NOR GATES:

Y= (𝒃 + 𝒅)(𝒂 + 𝒄)
𝒀= (𝒃 + 𝒅)(𝒂 + 𝒄)
𝒀= (𝒃 + 𝒅 ) + (𝒂 + 𝒄)

13
TRUTH TABLE:

Inputs Outputs
a b c Y
0 0 0 0
0 0 0 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 0
0 1 1 1
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 1
1 0 1 1
1 1 0 1
1 1 0 1
1 1 1 1
1 1 1 1

VERIFICATION OF POS EXPRESSIONS:

c) Y= f (a, b, c, d) = ∏(𝟎, 𝟐, 𝟒, 𝟔, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒)

Simplification Using K-Map:

i) (0,2,4,6,8,10,12,14) d
ii) (8,9,12,13) 𝒂+c

Y= 𝒅(𝒂 + 𝒄)

14
LOGIC DIAGRAMS:
USING BASIC GATES:

USING NAND GATES:

𝒀 = 𝒂𝒅 + 𝒅𝒄
𝒀 = 𝒂𝒅 + 𝒄𝒅
𝒀 = 𝒂𝒅 + 𝒄𝒅
𝒀 = 𝒂𝒅 ⦁ 𝒄𝒅
𝒀 = 𝒂𝒅 ⦁ 𝒄𝒅
𝒀 = 𝒂𝒅 + 𝒄𝒅

15
 USING NOR GATES:

𝒀 = (𝒂 + 𝒄)𝒅
𝒀 = (𝒂 + 𝒄)𝒅
𝒀 = 𝒀 = (𝒂 + 𝒄) + 𝒅

TRUTH TABLE:

Inputs Outputs
a b c Y
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 0
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 0
1 1 1 0
1 1 1 1

PROCEDURE:
1) Mount the IC on the Zero Insertion Force (ZIF) socket and lock the socket.
2) Make connections as per the logic diagram.
3) Apply all input combinations using toggle switches.
4) Note down the corresponding output and verify the truth table.

RESULT:
POS and SOP expressions for three and four variables are simplified and realized using basic
and universal gates. Also the result are verified using truth table.

INFERENCE:
16
 EXPERIMENT NO.2 (a)
DESIGN AND IMPLEMENTATION OF FULL ADDERS USING LOGIC GATES

AIM: To design and implement full Adders using logic gates.

COMPONENTS AND EQUIPMENT REQUIRED:

AND gate(IC 7408), NAND gate(IC 7400), X-OR gate(IC 7486), OR gate(IC 7432),
Digital IC trainer kit, patch cords.

FULL ADDER

BLOCK DIAGRAM: TRUTH TABLE:

A INPUTS OUTPUTS
B FULL ADDER S A B Cin S Cout
Cin 0 0 0 0 0
Cout 0 0 1 1 0
0 1 0 1 0
BOOLEAN EXPRESSION: 0 1 1 0 1
1 0 0 1 0
𝑺 = 𝒇(𝑨, 𝑩, 𝑪𝒊𝒏) = 𝑨 𝑩𝑪𝒊𝒏 + 𝑨𝑩 𝑪𝒊𝒏 + 𝑨𝑩 𝑪𝒊𝒏 + 𝑨𝑩𝑪𝒊𝒏 1 0 1 0 1
=∑ (1, 2, 4, 7) 1 1 0 0 1
𝑺 = 𝑨( 𝑩𝑪𝒊𝒏 + 𝑩 𝑪𝒊𝒏) + 𝑨(𝑩 𝑪𝒊𝒏 + 𝑩𝑪𝒊𝒏) 1 1 1 1 1
𝑺 = 𝑨( 𝑩 ⊕ 𝑪𝒊𝒏) + 𝑨(𝑩 ⊕ 𝑪𝒊𝒏)
𝑺 = 𝑨 ⊕ 𝑩 ⊕ 𝑪𝒊𝒏

𝑪𝒐𝒖𝒕 = 𝒇(𝑨, 𝑩, 𝑪𝒊𝒏) = 𝑨 𝑩𝑪𝒊𝒏 + 𝑨𝑩𝑪𝒊𝒏 + 𝑨𝑩𝑪𝒊𝒏 + 𝑨𝑩𝑪𝒊𝒏

=∑ (3, 5, 6, 7)
𝑪𝒐𝒖𝒕 = 𝑪𝒊𝒏( 𝑨𝑩 + 𝑨 𝑩) + 𝑨𝑩( 𝑪𝒊𝒏 + 𝑪𝒊𝒏)
𝑪𝒐𝒖𝒕 = (𝑨 ⊕ 𝑩)𝑪𝒊𝒏 + 𝑨𝑩

BLOCK DIAGRAM OF A FULL ADDER USING TWO HALF ADDERS:

17
REALIZATION OF FULL ADDER USING BASIC GATES:

REALIZATION OF FULL ADDER USING 2 INPUT NAND GATES:

Simplification

𝑺 = 𝑨 ⊕ 𝑩 ⊕ 𝑪𝒊𝒏
𝑳𝒆𝒕 𝑨 ⊕ 𝑩 = 𝑿
𝑺 = 𝑿 ⊕ 𝑪𝒊𝒏
= 𝑿𝑿 + 𝑿𝑪𝒊𝒏 + 𝑿𝑪𝒊𝒏 + 𝑪𝒊𝒏 𝑪𝒊𝒏
= 𝑿(𝑿 + 𝑪𝒊𝒏) + 𝑪𝒊𝒏(𝑿 + 𝑪𝒊𝒏)
= 𝑿(𝑿𝑪𝒊𝒏) + 𝑪𝒊𝒏(𝑿𝑪𝒊𝒏)
𝑺 = 𝑿(𝑿𝑪𝒊𝒏) + 𝑪𝒊𝒏(𝑿𝑪𝒊𝒏)
𝑺 = 𝑿(𝑿𝑪𝒊𝒏) ⦁ 𝑪𝒊𝒏(𝑿𝑪𝒊𝒏)

𝑺 = 𝑺 = 𝑿(𝑿𝑪𝒊𝒏) ⦁ 𝑪𝒊𝒏(𝑿𝑪𝒊𝒏)

𝑾𝒉𝒆𝒓𝒆 𝑿 = 𝑨(𝑨𝑩) ⦁𝑩(𝑨𝑩)

𝑪𝒐𝒖𝒕 = (𝑨 ⊕ 𝑩)𝑪𝒊𝒏 + 𝑨𝑩
𝑪𝒐𝒖𝒕 = (𝑨 ⊕ 𝑩)𝑪𝒊𝒏 + 𝑨𝑩 = (𝑨 ⊕ 𝑩)𝑪𝒊𝒏 ⦁ 𝑨𝑩
𝑪𝒐𝒖𝒕 = 𝑪𝒐𝒖𝒕 = (𝑨 ⊕ 𝑩)𝑪𝒊𝒏 ⦁ 𝑨𝑩

18
PROCEDURE:
1) Mount the IC on the Zero Insertion Force (ZIF) socket and lock the socket.
2) Make connections as per the logic diagram.
3) Apply all input combinations using toggle switches.
4) Note down the corresponding output and verify the truth table.

RESULT:
Full Adder Circuits are realized using logic gates and truth tables are verified.

19
 EXPERIMENT NO.2 (b)
DESIGN AND IMPLEMENTATION OF FULL SUBTRACTORS USING LOGIC GATES

AIM: To design and implement Full Subtractor using logic gates.

COMPONENTS AND EQUIPMENT REQUIRED:

AND gate(IC 7408), NAND gate(IC 7400), X-OR gate(IC 7486), OR gate(IC 7432), NOT
gate(IC 7404), Digital IC trainer kit, patch chords.

FULL SUBTRACTOR
BLOCK DIAGRAM: TRUTH TABLE:

INPUTS OUTPUTS
A A B Bin D Bout
B D 0 0 0 0 0
FULL SUBTRACTOR 0 0 1 1 1
Bin Bout 0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
BOOLEAN EXPRESSIONS: 1 1 0 0 0
1 1 1 1 1
𝑫 = 𝒇(𝑨, 𝑩, 𝑪𝒊𝒏) = 𝑨 𝑩𝑩𝒊𝒏 + 𝑨𝑩 𝑩𝒊𝒏 + 𝑨𝑩 𝑩𝒊𝒏 + 𝑨𝑩𝑩𝒊𝒏
=∑ (1, 2, 4, 7)
𝑫 = (𝑨 𝑩 ⊕ 𝑨𝑩)𝑩𝒊𝒏) + 𝑩𝒊𝒏(𝑨 𝑩 + 𝑨𝑩)
𝑫 = (𝑨 ⊕ 𝑩)𝑩𝒊𝒏 + 𝑩𝒊𝒏(𝑨 ⊕ 𝑩)
𝑫 = (𝑨 ⊕ 𝑩)𝑩𝒊𝒏

𝑩𝒐𝒖𝒕 = 𝒇(𝑨, 𝑩, 𝑩𝒊𝒏) = 𝑨 𝑩 𝑩𝒊𝒏 + 𝑨 𝑩𝑩𝒊𝒏 + 𝑨 𝑩𝑩𝒊𝒏 + 𝑨𝑩𝑩𝒊𝒏

=∑ (1, 2, 3, 7)
𝑩𝒐𝒖𝒕 = 𝑩𝒊𝒏( 𝑨 𝑩 + 𝑨 𝑩) + 𝑨𝑩( 𝑩𝒊𝒏 + 𝑩𝒊𝒏)
𝑩𝒐𝒖𝒕 = 𝑩𝒊𝒏(𝑨 ⊕ 𝑩) + 𝑨𝑩

LOGIC DIAGRAM OF A FULL SUBTRACTOR USING TWO HALF SUBTRACTORS:

20
Realization of FULL SUBTRACTOR using 2 input NAND GATES:

PROCEDURE:
1) Mount the IC on the Zero Insertion Force (ZIF) socket and lock the socket.
2) Make connections as per the logic diagram.
3) Apply all input combinations using toggle switches.
4) Note down the corresponding output and verify the truth table.

RESULT:
Full Subtractor Circuits are realized using logic gates and truth tables are verified.

21
 EXPERIMENT NO. 2 (c)
DESIGN AND IMPLEMENTATION OF 4-BIT PARALLEL ADDER / SUBTRACTOR USING IC
7483(CODE CONVERSION)

AIM: To design and implement 4-bit parallel adder and subtractor using IC 7483.

COMPONENTS AND EQUIPMENT REQUIRED:

IC 7483, X-OR gate(IC 7486), Digital IC trainer kit, patch cords.

REALIZATION OF 4 BIT PARALLEL ADDER / SUBTRACTORS:

IC7483 PIN DIAGRAM

BLOCK DIAGRAM:

LOGIC DIAGRAM:

4 BIT BINARY PARALLEL ADDER:

22
TRUTH TABLE:

Input Data A Input Data B Outputs

DEC A3 A2 A1 A0 DEC B3 B2 B1 B0 Cin DEC Cout S3 S2 S1 S0
9 1 0 0 1 10 1 0 1 0 1 20 1 0 1 0 0
14 1 1 1 0 6 0 1 1 0 0 20 1 0 1 0 0
7 0 1 1 1 3 0 0 1 1 0 10 0 1 0 1 0
8 1 0 0 0 4 0 1 0 0 0 12 0 1 1 0 0
13 1 1 0 1 14 1 1 1 0 0 27 1 1 0 1 1
15 1 1 1 1 15 1 1 1 1 0 30 1 1 1 1 0

4 BIT BINARY PARALLEL SUBTRACTOR:

TRUTH TABLE:

Input Data A Input Data B Outputs

DEC A3 A2 A1 A0 DEC B3 B2 B1 B0 Cin DEC Cout S3 S2 S1 S0
8 1 0 0 0 4 0 1 0 0 1 4 1 0 1 0 0
12 1 1 0 0 6 0 1 1 0 1 6 1 0 1 1 0
15 1 1 1 1 7 0 1 1 1 1 8 1 1 0 0 0
2 0 0 1 0 4 0 1 0 0 1 2 0 1 1 1 0
7 0 1 1 1 15 1 1 1 1 1 8 0 1 0 0 0
9 1 0 0 1 4 0 1 0 0 1 5 1 0 1 0 1

23
 EXPERIMENT NO. 3
a. DESIGN AND IMPLEMENTATION OF Binary to gray code converter and vice
versa
AIM: To design and implement Binary to gray code converter and vice versa.

COMPONENTS AND EQUIPMENTS REQUIRED:

X-OR gate (IC 7486), Digital IC trainer kit, patch chords.

Binary to Gray code converter:

TRUTH TABLE:

Four Bit Binary Number Four Bit Gray Code

B4 B3 B2 B1 G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

BOOLEAN EXPRESSION:
G1 = B1
G2 = B1 XOR B2
G3 = B2 XOR B3
G4 = B3 XOR B4

LOGIC DIAGRAM:

24
 Gray code to Binary converter:
TRUTH TABLE:
Four Bit Gray Code Four Bit Binary Number
G1 G2 G3 G4 B1 B2 B3 B4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

BOOLEAN EXPRESSION:
B1 = G1
B2 = G2 XOR B1
B3 = G3 XOR B2
B4 = G4 XOR B3

LOGIC DIAGRAM:

25
 b. DESIGN AND IMPLEMENTATION OF Binary to Ex-3 code converter and vice
versa
AIM: To design and implement BCD to Ex-3 code converter.

COMPONENTS AND EQUIPMENTS REQUIRED:

AND gate (IC 7408), X-OR gate (IC 7486), NOT gate (IC7404), IC7485, Digital IC
trainer kit, patch chords.

BCD to Ex-3
TRUTH TABLE:
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

K-MAP AND BOOLEAN EXPRESSION:

FOR

c.

w = A+BC+BD x = B’C+B’D+BC’D’

y = C’D’+CD z = D’

26
LOGIC DIAGRAM:
A
w

x
B

C y

D z

Ex-3 to BCD
TRUTH TABLE:

27
K-MAP AND BOOLEAN EXPRESSION:
FOR

LOGIC DIAGRAM:

28
 c. DESIGN AND IMPLEMENTATION OF ONE BIT COMPARATOR AND 4-
BIT COMPARATOR USING IC 7485.

AIM: To design and implement one bit comparator and 4- bit comparator using IC 7485.

COMPONENTS AND EQUIPMENTS REQUIRED:

AND gate (IC 7408), X-OR gate (IC 7486), NOT gate (IC7404), IC7485, Digital IC
trainer kit, patch chords.

ONE BIT COMPARATOR:

TRUTH TABLE:

Inputs Outputs
A B A<B A=B A>B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

K-MAP AND BOOLEAN EXPRESSION:

FOR

𝑨 < 𝐵 = 𝑓(𝑨, 𝑩) = 𝑨𝑩 𝑨 = 𝑩 = 𝒇(𝑨, 𝑩) = 𝑨 𝑩 + 𝑨𝑩 = 𝑨 ⊕ 𝑩 𝑨>

𝐵 = 𝑓(𝑨, 𝑩) = 𝑩𝑨

29
 LOGIC DIAGRAM:

FOUR BIT MAGNITUDE COMPARATOR IC 7485:

TRUTH TABLE:
Inputs Outputs
A3B3 A2B2 A1B1 A0B0 A>B A=B A<B
A3>B3 X X X 1 0 0
A3<B3 X X X 0 0 1
A3=B3 A2>B2 X X 1 0 0
A3=B3 A2<B2 X X 0 0 1
A3=B3 A2=B2 A1>B1 X 1 0 0
A3=B3 A2=B2 A1<B1 X 0 0 1
A3=B3 A2=B2 A1=B1 A0>B0 1 0 0
A3=B3 A2=B2 A1=B1 A0<B0 0 0 1
A3=B3 A2=B2 A1=B1 A0=B0 0 1 0

30
TABULAR COLUMN:
Inputs Outputs
A3 A2 A1 A0 DEC B3 B2 B1 B0 DEC A>B A=B A<B
0 0 0 0 0 0 0 0 1 1 0 0 1
0 1 1 1 7 0 1 0 0 4 1 0 0
1 1 1 1 15 1 1 1 1 15 0 1 0
0 1 0 1 5 0 1 1 0 6 0 0 1
1 0 1 0 10 0 0 1 0 2 1 0 0
1 1 0 0 12 1 1 0 0 12 0 1 0

x7 x6 x 5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

0 A3 A2 A1 B3 B2 B1
I(A> A3 A2 A1 B3 B2 B1
I(A>
1 B)
Magnitude
A B B)
Magnitude
A B
0 I(A=Comparator I(A=Comparator
B)A<B A=B A>B B)A<B A=B A>B

A<B A=B A>B

PROCEDURE:
1) Check the IC and fix it to the socket.
2) Rig up the circuit as shown in the circuit diagram.
3) Apply various input data to the circuit via logic switches.
4) Note down the corresponding output and verify the truth table.

RESULT:
a. Gray to binary and binary to gray is designed and implemented and verified.
b. Ex-3 to binary and binary to Ex-3 is designed and implemented and verified.
c. One bit comparator has been designed and implemented as shown in the logic
diagram. Also a 4-Bit, magnitude comparator have been verified using IC 7485
and verified using the truth table.

31
 EXPERIMENT NO. 4
a. Design and implement Multiplexers

AIM: To realize 4:1 multiplexer using basic gates and NAND gates.

COMPONENTS AND EQUIPMENTS REQUIRED:

NOT Gate(IC 7404), NAND Gate(IC 7400), 4 input NAND gate (IC7420), 4 input
AND gate (IC 7421), OR gate (IC7432), IC 74151, Digital IC trainer kit, patch
chords.

LOGIC SYMBOL: TRUTH

TABLE:01

Inputs Output
E S1 S0 Y
0 X X 0
1 0 0 I0
1 0 1 I1
1 1 0 I2
1 1 1 I3

BOOLEAN EXPRESSSION:

𝐘 = 𝐈𝟎𝐒𝟏 𝐒𝟎𝐄 + 𝐈𝟏𝐒𝟏𝐒𝟎𝐄 + 𝐈𝟐𝐒𝟏𝐒𝟎𝐄 + 𝐈𝟑𝐒𝟏𝐒𝟎𝐄

TRUTH TABLE:0

Inputs Output
E S1 S0 I0 I1 I2 I3 Y
0 X X X X X X 0
1 0 0 0 X X X 0
1 0 0 1 X X X 1
1 0 1 X 0 X X 0
1 0 1 X 1 X X 1
1 1 0 X X 0 X 0
1 1 0 X X 1 X 1
1 1 1 X X X 0 0
1 1 1 X X X 1 1

32
REFERING TRUTH TABLE 01:

𝐘 = 𝐈𝟎𝐒𝟏 𝐒𝟎𝐄 + 𝐈𝟏𝐒𝟏𝐒𝟎𝐄 + 𝐈𝟐𝐒𝟏𝐒𝟎𝐄 + 𝐈𝟑𝐒𝟏𝐒𝟎𝐄

REALISATION USING BASIC GATES:

33
 PIN DIAGRAM:
IC 74151 (8:1 MUX)

TRUTH TABLE:
ENABLE I/P
Inputs Output

EN S2 S1 S0 D0 D1 D2 D3 D4 D5 D6 D7 Y
1 X X X X X X X X X X X 0
0 0 0 0 0 X X X X X X X 0
0 0 0 0 1 X X X X X X X 1
0 0 0 1 X 0 X X X X X X 0
0 0 0 1 X 1 X X X X X X 1
0 0 1 0 X X 0 X X X X X 0
0 0 1 0 X X 1 X X X X X 1
0 0 1 1 X X X 0 X X X X 0
0 0 1 1 X X X 1 X X X X 1
0 1 0 0 X X X X 0 X X X 0
0 1 0 0 X X X X 1 X X X 1
0 1 0 1 X X X X X 0 X X 0
0 1 0 1 X X X X X 1 X X 1
0 1 1 0 X X X X X X 0 X 0
0 1 1 0 X X X X X X 1 X 1
0 1 1 1 X X X X X X X 0 0
0 1 1 1 X X X X X X X 1 1

34
REALISATION OF 3-VRIABLE FUNCTION USING 8:1 MUX IC 74151:
i) F =f (x, y, z) = ∑ (1, 2, 4, 5, 7)

TRUTH TABLE:

Inputs Output
x y z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1

REALISATION USING IC 74151:

LOGIC DIAGRAM:

35
ii) P = f(x, y, z) = ∑ (1, 3, 5, 6)

TRUTH TABLE:

Inputs Output
x y z P
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

REALISATION USING IC 74151:

LOGIC DIAGRAM:

PROCEDURE:
1) Rig up the circuit as shown in the logic diagram.
2) Apply various input data to the circuit via logic switches.
3) Note down the corresponding output and verify the truth table.

RESULT:
The 4:1 Mux is designed and implemented using both basic gates and NAND gates
and the truth table is verified and 8:1 Mux and 3- Variable function are implemented using
IC 74151 and the truth table is verified.

36
 b. REALIZATION OF 1:8 DEMUX AND 3:8 DECODER USING IC 74138

AIM: To realize 1:8 Demux and 3:8 decoder using IC 74138.

COMPONENTS AND EQUIPMENTS REQUIRED:

IC 74138, 4 input NAND gate (IC7420), 4 input AND gate (IC7421), Digital IC
trainer kit, patch chords.

PIN DIAGRAM:
IC 74138 (1:8 DEMUX)

IC 74138 AS A DECODER:

TRUTH TABLE:
ENABLE I/PS DATA I/PS OUTPUTS

G1 𝑮𝟐𝑨 𝑮𝟐𝑩 C B A 𝒀𝟎 𝒀𝟏 𝒀𝟐 𝒀𝟑 𝒀𝟒 𝒀𝟓 𝒀𝟔 𝒀𝟕
0 1 1 X X X 1 1 1 1 1 1 1 1
1 1 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 1 1 0 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 1 1 1 1 1

37
1 0 0 0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 1 1 1 1 1 1 0 1 1
1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
IMPLEMENTATION OF 3-VRIABLE FUNCTION USING IC 74138:
P = f(x, y, z) = ∑ (1, 2, 4, 5)
Q = f(x, y, z) = ∏ (4, 5, 6, 7)

TRUTH TABLE:

Inputs Outputs
x y z P Q
0 0 0 0 1
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0 0 0
1 1 1 0 0

REALISATION USING IC 74138:

LOGIC DIAGRAM:

38
IC 74138 AS 1:8 DEMULTIPLEXERS:

HERE G1=1 AND 𝑮𝟐𝑩 = 𝟎 (PERMANENTLY GROUNDED)

TRUTH TABLE:

39
ENABLE I/P SELECT I/PS OUTPUTS

𝑮𝟐𝑨 C B A 𝒀𝟎 𝒀𝟏 𝒀𝟐 𝒀𝟑 𝒀𝟒 𝒀𝟓 𝒀𝟔 𝒀𝟕
0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1
1 0 0 1 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1
1 0 1 0 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1
1 1 1 0 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1

PROCEDURE:
1) Rig up the circuit as shown in the logic diagram.
2) Apply various input data to the circuit via logic switches.
3) Note down the corresponding output and verify the truth table.

RESULT:
The 8:1 demultiplexers and 3:8 decoders are realized using IC 74138 and
the truth table is verified.

40
 C. Priority Encoder
AIM:-To encode the binary inputs to Octal values.

COMPONENTS AND EQUIPMENTS REQUIRED:

IC 74148, Digital IC trainer kit, patch chords.

PIN DIAGRAM:

PROCEDURE:
1) Rig up the circuit as shown in the logic diagram.
2) Apply various input data to the circuit via logic switches.
3) Note down the corresponding output and verify the truth table.

RESULT:
The 8:3 priority encoder are realized using IC 74148 and the truth table is verified.

41
 EXPERIMENT NO. 5
a. REALIZATION OF THE FOLLOWING SHIFT REGISTERS USING IC 7474
(A) SISO (B) SIPO (C) PISO (D) PIPO

AIM: To realise the following shift registers using IC 7474.

a) Serial In Serial Out (SISO)
b) Serial In Parallel Out (SIPO)
c) Parallel In Serial Out (PISO)
d) Parallel In Parallel Out (PIPO)

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. Digital IC Trainer .... IC 74151
2. IC 74195 ... ...
3. ... ... ...

BRIEF THEORY:
A register is a group of binary storage cells capable of holding binary information. A group
of flipflops constitutes a register, since each flip-flop can work as a binary cell. An n-bit
register has n flip-flops and is capable of holding n-bits of information. In addition to flip-
flops a register can have a combinational part that performs data-processing tasks.
Shift Register: A register capable of shifting its binary contents either to the left or to the
right iscalled a shift register. The shift register permits the stored data to move from a
particular locationto some other location within the register. Registers can be designed
using discrete flip-flops (S- R, J-K, and D-type). The data in a shift register can be shifted
in two possible ways: (a) serial shifting and (b) parallel shifting. The serial shifting
method shifts one bit at a time for each clock pulse in a serial manner, beginning with
either LSB or MSB. On the other hand, in parallel shiftingoperation, all the data (input or
output) gets shifted simultaneously during a single clock pulse. Hence, we may say that
parallel shifting operation is much faster than serial shifting operation.
8- bit Universal Shift Register: IC 74195 is a 4-bit TTL MSI having both serial/parallel
input andserial/parallel output capability. The pinout diagram of IC 74195 is shown in
Figure 1.

Pin diagram of IC 74195.

42
 When the SH / LD input is LOW, the data on the parallel inputs, i.e., A, B, C, and D are
entered synchronously on the positive transition of the clock. When SH / LD is HIGH, the
stored data willshift right (QA to QD) synchronously with the clock. J and K are the serial
inputs to the first stageof the register (QA); QD can be used for getting a serial output
data. The active low clear is asynchronous.
TRUTH TABLE:
4-BIT SERIAL IN SERIAL OUT (SIPO) REGISTER:
DATA: 1011

4-BIT SERIAL IN PARALLEL OUT (SIPO) REGISTER:

TRUTH TABLE:
DATA: 1011

43
4-BIT PARALLEL IN SERIAL OUT (PISO) AND 4-BIT PARALLEL IN PARALLEL
OUT (PIPO) REGISTER:

TRUTH TABLE FOR PISO:

DATA: 1011

TRUTH TABLE FOR PISO:

DATA: 1011

PROCEDURE:
1) Rig up the circuit as shown in the logic diagram.
2) Apply various input data to the circuit via logic switches along with the clock pulse.
3) Note down the corresponding output and verify the truth table.

RESULT:
SISO, SIPO, PISO and PIPO Shift Register are implemented and realized using IC
7474 and verified using the truth table.

44
b. REALIZATIONS OF RING COUNTER AND JOHNSON COUNTER USING IC
7476

AIM: To realise Ring counter and Johnson counter using IC 7476.

COMPONENTS AND EQUIPMENTS REQUIRED:

IC 7476, NOT Gate (IC 7404), Digital IC trainer kit, patch chords.

PIN DIAGRAM:
IC 7476(DUAL JK FLIP FLOP WITH PRESET AND CLEAR)

LOGIC SYMBOL:

45
RING COUNTER:

TRUTH TABLE:

Input Outputs
CLOCK
Q1 Q2 Q3 Q4
CLK
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0 Output Repeats

46
JOHNSON COUNTER:

TRUTH TABLE:

Input Outputs
CLOCK
Q1 Q2 Q3 Q4
CLK
0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
0 0 0 0 Output Repeats

PROCEDURE:
1) Rig up the circuit as shown in the logic diagram.
2) For Ring counter, set the first bit J1 then after that apply the clock pulse.
3) For Johnson counter, first clear all the inputs, then apply clock pulse.
4) Check the outputs corresponding to their inputs.

47
RESULT:
Ring counter and Johnson counter are realised using IC 7476 and the truth table is
verified

48
c. REALIZATION OF MOD-N COUNTERS USING IC 7490

AIM: To realise the MOD-N Counter using IC 7490.

COMPONENTS AND EQUIPMENTS REQUIRED:

IC 7490, AND Gate (IC 7408), 4 Input AND Gate (IC 7411), Digital IC Trainer kit,
Patch Chords.

PIN DIAGRAM:

INTERNAL DIAGRAM:

IC 7490

NC: No Connection

FUNCTION TABLE:

49
TIMING DIAGRAM:

MOD - 2 COUNTER: TRUTH

TABLE:

Input Output

Q0

1 0
2 1

50
MOD - 5 COUNTER:

TRUTH TABLE:

Input Outputs

Q3 Q2 Q1

1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0

51
MOD -7 COUNTER:

TRUTH TABLE:

Input Outputs

Q3 Q2 Q1 Q0

1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
MOD – 10 COUNTER:

52
TRUTH TABLE:

Input Outputs

Q3 Q2 Q1 Q0

1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1

PROCEDURE:
 Check all the ICs and patch chords. 
1)
 Insert the appropriate IC into the IC base. 
2)
 Make connections as shown in the circuit diagram. 
3)
4) Apply the clock pulse and verify the Truth Table, observe the outputs. 

RESULT:
The MOD -2, MOD -5, MOD – 7 and MOD -10 Counters are realised and
implemented using IC -7490 and the truth table is verified.

53
 EXPERIMENT NO. 6
a. Verify the functionality of logic gates

AIM: Write a verilog code to verify the functionality of logic gates

i) NOT GATE: A logic gate whose input is complement of its input.

Logic Symbol Truth Table Verilog Code
module not1(a,y);
input a;
output y;
assign y= ~a;
Input Output endmodule
A Y
0 1
1 0

ii) AND GATE: A Logic circuit whose output is logic ‘1’ if and only if all of its
inputs are logic ‘1’.
Logic Symbol Truth Table Verilog Code
module and12(a,b,y);
input a,b;
Inputs Output output y;
A B Y assign y=a & b;
0 0 0 endmodule
0 1 0
1 0 0
1 1 1

54
 iii) OR GATE: A logic gate whose output is logic ‘0’ if and only if all of its inputs
are logic ‘0’.
Logic Symbol Truth Table Verilog Code

Inputs Outpu module or12(a,b,y);

t input a,b;
output y;
A B Y assign y=a | b;
0 0 0 endmodule
0 1 1
1 0 1
1 1 1

iv) NAND GATE: A logic gate which gives logic ‘0’ output if and only if all
its inputs are logic‘1’.
Logic Symbol Truth Table Verilog Code
module nand12(a,b,y);
input a,b;
output y;
Inputs Output assign y=~(a & b);
endmodule
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

55
 v) NOR GATE: A logic gate whose output logic ‘1’ if and only if all of its inputs
are logic ‘0’
Logic Symbol Truth Table Verilog Code

module nor12(a,b,y);
Inputs Output input a,b;
A B Y output y;
0 0 1 assign y=~(a | b);
0 1 0 endmodule
1 0 0
1 1 0

vi) EX-OR (Exclusive OR): A logic gate whose output is logic ‘0’ when all
the inputs are equal andlogic ‘1’ when they are unequal.
Logic Symbol Truth Table Verilog Code

Inputs Output module xor12(a,b,y);

input a,b;
A B Y
output y;
0 0 0
assign y=a ^ b;
0 1 1 endmodule
1 0 1
1 1 0

56
 vii) EX-NOR (Exclusive -NOR) gate: A logic gate that produces a logic ‘1’
only when the two inputsare equal
Logic Symbol Truth Table Verilog Code

module xnor12(a,b,y);
input a,b;
Inputs Outp output y;
ut assign y=~(a ^ b);
A B Y endmodule
0 0 1
0 1 0
1 0 0
1 1 1

57
 b. Verify the given SOP and POS equation
i. SOP equation, Y= f (a, b, c) = 𝑎 𝑏 𝑐 + a 𝑏 𝑐 + a 𝑏 c = ∑(0,4,5)
= 𝑏 𝑐 (𝑎 + a) + a 𝑏 c = 𝑏 𝑐 + a 𝑏 c = 𝑏 ( 𝑐 + a c)
= 𝑏 ( 𝑐 + a) ( 𝑐 + c)
= 𝑏 ( 𝑐 + a)

Using K-Map Simplification:

i) (0,4) 𝑏𝑐
ii) (4,5) a𝑏

Y= 𝑏 𝑐 + a 𝑏
Y= 𝑏 ( 𝑐 + a)
LOGIC DIAGRAM:

Verilog Code:
module SOP(a,b,c,d,y);
input a,b,c,d;
output y;
assign y=~b(~c | a);
endmodule

58
 ii. POS equation Y= f (a, b, c, d) = 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏 𝑐𝑑 +
𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐 𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 +abcd == ∑(3,6,7,9,11,12,13,14,15)
= 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐 𝑑 +abcd +𝑎𝑏 𝑐𝑑 + 𝑎𝑏 𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑
= 𝑎𝑐𝑑(𝑏 + 𝑏) + 𝑏𝑐𝑑(𝑎 + 𝑎) + 𝑎𝑏𝑐 𝑑 +acd (𝑏 + 𝑏 ) + 𝑎 𝑐𝑑(𝑏 + 𝑏)
= 𝑎𝑐𝑑 + 𝑏𝑐𝑑 + 𝑎𝑏𝑐 𝑑 + acd + 𝑎 𝑐𝑑
= 𝑐𝑑 (𝑎 + 𝑎) + 𝑏𝑐𝑑 + 𝑎𝑏𝑐 𝑑 + 𝑎 𝑐𝑑
= 𝑐𝑑 + 𝑏𝑐𝑑 + 𝑎𝑏𝑐 𝑑 + 𝑎 𝑐𝑑 = 𝑑 (c + ac) + 𝑑(𝑏𝑐 + 𝑎𝑏𝑐 )
= 𝑑 (c + ac) + 𝑑𝑏(𝑐 + 𝑎𝑐 ) = (𝑑 + 𝑑𝑏)(𝑐 + 𝑎𝑐 ) = (𝑑 + 𝑑)(𝑑 + 𝑏)(𝑐 + 𝑎)(𝑐 + 𝑐)
=(𝑑 + 𝑏)(𝑐 + 𝑎)
Using K-Map Simplification:

i) (12,13,14,15) ab
ii) (9,11,13,15) ad
iii) (3,7,11,15) cd
iv) (7,6,14,15) bc

Y= 𝑎𝑏 + 𝑎𝑑 + 𝑐𝑑 + 𝑏𝑐
Y= 𝑎(𝑏 + 𝑑) + 𝑐(𝑑 + 𝑏)
Y= (𝑎 + 𝑐)(𝑏 + 𝑑)

LOGIC DIAGRAM:

Verilog Code:
module POS(a,b,c,d,y);
input a,b,c,d;
output y;
assign y=(d | b)& (a | c);
endmodule

59
 EXPERIMENT NO. 7
a. Verify the functionality of Adder

AIM: Write a verilog code to verify the functionality of half adder, full adder and 4bit
parallel adder
i. Half Adder
Truth table Logic diagram Verilog Code

module HA(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a ^ b;
assign carry=a & b;
endmodule

ii. Full Adder

a. Using gates
Truth table Logic diagram Verilog Code

INPUTS OUTPUTS module FA(a,b,cin,sum,carry);

input a,b,cin;
A B Cin S Cout output sum,carry;
0 0 0 0 0 assign sum=a ^ b^cin;
0 0 1 1 0 assign carry=(a & b|(b &
cin)|(cin & a);
0 1 0 1 0
endmodule
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

b. Using half adders

Truth table Logic diagram Verilog Code

INPUTS OUTPUTS module

FA(a,b,cin,sum,carry);
A B Cin S Cout input a,b,cin;
0 0 0 0 0 output sum,carry;
0 0 1 1 0 wire s1, c1, c2;
HA H1(a,b,s1,c1);
0 1 0 1 0
HA H2(s1, cin,Sum,c2);
0 1 1 0 1 assign carry= c1 | c2;
1 0 0 1 0 endmodule
1 0 1 0 1
1 1 0 0 1 module
1 1 1 1 1 HA(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a ^ b;
assign carry=a & b;
endmodule

60
 iii. 4 bit Parallel adder
Logic diagram:

Verilog Code:
module 4bitadder(a,b,cin,s,cout);
input [3:0]a, [3:0]b, cin;
output [3:0]s, cout;
wire [2:0]c;
FA a1(a[0], b[0], cin, s[0], c[0]);
FA a2(a[1], b[1], c[0], s[1], c[1]);
FA a3(a[2], b[2], c[1], s[2], c[2]);
FA a4(a[3], b[3], c[2], s[3], cout);

endmodule

module FA(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
assign sum=a ^ b^cin;
assign carry=(a & b|(b & cin)|(cin & a);
endmodule

61
 b. Verify the functionality of MUX

AIM: Write a verilog code to verify the functionality of 4:1 and 8:1 mux

i. 4:1 Mux

Truth Table Logic diagram Verilog Code

Inp Output a. Using gate
uts module 41mux(I,S,E,y);
E S1 S0 Y input [3:0] I, [1:0]S, E;
0 X X 0 output y;
1 0 0 I0 wire x1, x2, x3, x4;
1 0 1 I1 assign x1=I[0] & ~S[0] & ~S[1] &E;
1 1 0 I2 assign x2=I[1] & S[0] & ~S[1] &E;
1 1 1 I3 assign x3=I[2] & ~S[0] & S[1] &E;
assign x4=I[4] & S[0] & S[1] &E;
𝐘 = 𝐈𝟎𝐒𝟏 𝐒𝟎𝐄 + 𝐈𝟏𝐒𝟏𝐒𝟎𝐄 assign y= x1 | x2 | x3 | x4;
+ 𝐈𝟐𝐒𝟏𝐒𝟎𝐄 endmodule
+ 𝐈𝟑𝐒𝟏𝐒𝟎𝐄
b. Using conditional statements
module 41mux(I,S,y);
input [3:0] I, [1:0]S;
output y;
assign y=s[1]?(s[0]?i[3]:i[2])(
s[0]?i[1]:i[0]);
endmodule

ii. 8:1 mux

Truth Table Logic diagram Verilog Code

Inputs Output a. Using gate
E S2 S1 S0 Y module 41mux(I,S,E,y);
0 X X X 0 input [7:0] I, [2:0]S, E;
1 0 0 0 I0 output y;
1 0 0 1 I1 wire [7:0] x;
1 0 1 0 I2 assign x[0]=I[0] & ~S[0] & ~S[1]
1 0 1 1 I3 &~S[2]&E;
1 1 0 0 I4 assign x[1]=I[1] & S[0] & ~S[1]
1 1 0 1 I5 &~S[2]&E;
1 1 1 0 I6 assign x[2]=I[2] & ~S[0] & S[1]
&~S[2]&E;
1 1 1 1 I7
assign x[3]=I[3] & S[0] & S[1]
&~S[2]&E;
assign x[4]=I[4] & ~S[0] & ~S[1]
&S[2]&E;

62
 assign x[5]=I[5] & S[0] & ~S[1]
&S[2]&E;
assign x[6]=I[6] & ~S[0] & S[1]
&S[2]&E;
assign x[7]=I[7] & S[0] & S[1] &
S[2]&E;
assign y= x[0] | x[1] | x[2] | x[3] | x[4] |
x[5] | x[6] | x[7];
endmodule

b. Using conditional statements

module 41mux(I,S,y);
input [7:0] I, [2:0]S;
output y;
assign y=s[2](s[1]?(s[0]?i[7]:i[6])(
s[0]?i[5]:i[4])) : (s[1]?(s[0]?i[3]:i[2])(
s[0]?i[1]:i[0]));
endmodule

iii. 8:1 MUX using 2:1 MUX

Truth Table Logic diagram Verilog Code

Inputs Output a. Using gate
E S2 S1 S0 Y module 41mux(I,S,E,y);
0 X X X 0 input [7:0] I, [2:0]S, E;
1 0 0 0 I0 output y;
1 0 0 1 I1 wire [7:0] x;
1 0 1 0 I2 21mux m1(I[1:0],S[0],x[0]);
1 0 1 1 I3 21mux m2(I[2:3],S[0],x[1]);
1 1 0 0 I4 21mux m3(I[4:5],S[0],x[2]);
1 1 0 1 I5 21mux m4(I[6:7],S[0],x[3]);
1 1 1 0 I6 21mux m5(x[1:0],S[1],x[4]);
21mux m6(x[2:3],S[1],x[5]);
1 1 1 1 I7
21mux m7(x[5:4],S[2],y);
endmodule

b. Using conditional statements

module 21mux(I,S,y);
input 17:0] I, S;
output y;
assign y= s?i[1]:i[0];
endmodule

63
 c. Verify the functionality of Demux
AIM: Write a verilog code to verify the functionality of 1:4 DEMUX

Truth Table Logic diagram Verilog Code

a. Using gate
module 14demux(I,S,y);
input I, [1:0]S;
output [7:0]y;
assign y[0]=I & ~S[0] & ~S[1];
assign y[1]=I & S[0] & ~S[1];
assign y[2]=I & ~S[0] & S[1];
assign y[3]=I & S[0] &S[1];
endmodule

d. Verify the functionality of Decoder

AIM: Write a verilog code to verify the functionality of 2:4 Decoder

Truth Table Logic diagram Verilog Code

64
 e. Verify the functionality of Encoder
AIM: Write a verilog code to verify the functionality of 8:3 Encoder with Priority and
without priority
i. Without priority

Truth Table Logic diagram Verilog Code

module encoder (din, dout);
input [7:0] din;
output [2:0] dout;
assign dout[0] = din[1] |din[3] |din[5]
|din[7]);
assign dout[1] = din[2] | din[3] |
din[6] | din[7]);
assign dout[2] = din[4] | din[5] | din[6]
| din[7]);
endmodule

65
 ii. With priority

Truth Table Logic diagram Verilog Code

module prio_enco_8x3(dout, din);
output [2:0] dout;
input [7:0] din ;
assign dout = (din[7] ==1'b1 ) ? 3'b111:
(din[6] ==1'b1 ) ? 3'b110:
(din[5] ==1'b1 ) ? 3'b101:
(din[4] ==1'b1) ? 3'b100:
(din[3] ==1'b1) ? 3'b011:
(din[2] ==1'b1) ? 3'b010:
(din[1] ==1'b1) ? 3'b001:
(din[0] ==1'b1) ? 3'b000: 3'bxxx;
endmodule

66
 EXPERIMENT NO. 8
a. Verify the functionality of Adder using behavioural modelling

AIM: Write a verilog code to verify the functionality of half adder, full adder and 4bit
parallel adder
i. Half Adder
Truth table Logic diagram Verilog Code

module
HA(a,b,sum,carry);
input a,b;
output reg sum,carry;
always @ (a,b)
begin
sum=a ^ b;
carry=a & b;
endmodule

ii. Full Adder

Truth table Logic diagram Verilog Code

INPUTS OUTPUTS module

A B Cin S Cout FA(a,b,cin,sum,carry);
0 0 0 0 0 input a,b,cin;
0 0 1 1 0 output reg sum,carry;
0 1 0 1 0 always @ (a,b,cin)
0 1 1 0 1 begin
1 0 0 1 0 sum=a ^ b^cin;
1 0 1 0 1 carry=(a & b|(b &
1 1 0 0 1 cin)|(cin & a);
1 1 1 1 1 endmodule

b. Verify the functionality of MUX

AIM: Write a verilog code to verify the functionality of 4:1 and 8:1 mux
i. 4:1 Mux
Truth Table Logic diagram Verilog Code
Inp Output module 41mux(I,S,E,y);
uts input [3:0] I, [1:0]S, E;
E S1 S0 Y output reg y;
0 X X 0 always @ (I, S, E)
1 0 0 I0 begin
1 0 1 I1 case (S)
1 1 0 I2 00: y<= I[0];
1 1 1 I3 01:y<=I[1];
10: y<=I[2];
𝐘 = 𝐈𝟎𝐒𝟏 𝐒𝟎𝐄 + 𝐈𝟏𝐒𝟏𝐒𝟎𝐄
11: y<=I[3];
+ 𝐈𝟐𝐒𝟏𝐒𝟎𝐄 Default: y<=x;
+ 𝐈𝟑𝐒𝟏𝐒𝟎𝐄 endcase
end
endmodule

67
 ii. 8:1 mux

Truth Table Logic diagram Verilog Code

Inputs Output module 41mux(I,S,E,y);
E S2 S1 S0 Y input [7:0] I, [2:0] S, E;
0 X X X 0 output reg y;
1 0 0 0 I0 always @ (I, S, E)
1 0 0 1 I1 begin
1 0 1 0 I2 if (S(2))
1 0 1 1 I3 if (S(1))
1 1 0 0 I4 if (S(0))
1 1 0 1 I5 y>=I[7];
1 1 1 0 I6 else
1 1 1 1 I7 y<=I[6];
else
if (S(0))
y>=I[5];
else
y<=I[4];
else
if (S(1))
if (S(0))
y>=I[3];
else
y<=I[2];
else
if (S(0))
y>=I[1];
else
y<=I[0];
end
endmodule

c. Verify the functionality of Demux

AIM: Write a verilog code to verify the functionality of 1:4 DEMUX

Truth Table Logic diagram Verilog Code

a. Using gate
module 14demux(I,S,y);
input I, [1:0]S;
output reg [7:0]y;
always @ (I, S)
begin
y[0]=I & ~S[0] & ~S[1];
y[1]=I & S[0] & ~S[1];
y[2]=I & ~S[0] & S[1];
y[3]=I & S[0] &S[1];
endmodule

68
 d. Verify the functionality of Decoder
AIM: Write a verilog code to verify the functionality of 2:4 Decoder

Truth Table Logic diagram Verilog Code

module decoder (input [1:0] a, output reg [3:0]
y);
always @ (a)
begin
case(a)
2’b00: y<=4’b1110;
2’b01: y<=4’b1101;
2’b10: y<=4’b1011;
2’b11: y<=4’b0111;
default:y<=4’bxxxx;
endcase
endmodule

e. Verify the functionality of Encoder

69
 AIM: Write a verilog code to verify the functionality of 8:3 Encoder with Priority and
without priority
i. Without priority

Truth Table Logic diagram Verilog Code

module encoder (din, dout);
input [7:0] din;
output reg [2:0] dout;
always @ (din)
begin
if (din ==8'b00000001)
dout=3'b000;
else if (din==8'b00000010)
dout=3'b001;
else if (din==8'b00000100)
dout=3'b010;
else if (din==8'b00001000)
dout=3'b011;
else if (din==8'b00010000)
dout=3'b100;
else if (din==8'b00100000)
dout=3'b101;
else if (din==8'b01000000)
dout=3'b110;
else if (din==8'b10000000)
dout=3'b111;
else
dout=3'bX ;
end
endmodule

70
 ii. with priority

Truth Table Logic diagram Verilog Code

module prio_enco_8x3(dout, din);
input [7:0] din;
output reg [2:0] dout;
always @ (din)
begin
if (din ==8'b00000001)
dout=3'b000;
else if (din==8'b0000001X)
dout=3'b001;
else if (din==8'b000001XX)
dout=3'b010;
else if (din==8'b00001XXX)
dout=3'b011;
else if (din==8'b0001XXXX)
dout=3'b100;
else if (din==8'b001XXXXX)
dout=3'b101;
else if (din==8'b01XXXXXX)
dout=3'b110;
else if (din==8'b1XXXXXXX)
dout=3'b111;
else
dout=3'bX ;
end
endmodule

71
Experiment No. 9:
a. Flip Flops
Aim: - Develop and simulate the Verilog code for the following flip-flopsSR
JK
D
T

Theory: -
SR flip-flop: A SR flip-flop is the simplest possible memory element. The SR flip flop has
two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops.

D flip-flop: This is a flip-flop with a delay (D) equal to exactly equal to one cycle of the
clock. The defect with SR FF is the indeterminate output when the data inputs at S and R
are 1. In order to avoid this the input to R is through an inverter from S so that the input to
R is always the complement of S and never same. The S input is redesignated as D.

JK flip-flop: The JK flip-flop is called a “universal flip flop” because the other flip flops
like D, SR, T can be derived from it. The “racing or race around condition” takes place in a
JK FF when J=1 and K=1 and clock=1.

T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and
K.

S-R flip-flop Truth table:

Block diagram :

72
Truth Table :

Verilog Code :

module sr_ff(sr, clk, rst, q, qb);

input [1:0]sr;
input rst, clk;
output q,qb;
reg q,qb;
always @ (posedge clk)
begin
if (rst==1)
begin
q=0;
qb=1;
end
else
case (sr)
2'b00: begin q=q; qb=qb; end
2'b01: begin q=0; qb=1; end
2'b10: begin q=1; qb=0; end
2'b11: begin q=1'bx; qb=1'bx; end
default:begin end
endcase
end
endmodule

73
Simulation Result of SR flip-flop:-

D Flip Flop :

Block diagram:

Truth Table

74
Simulation Results:-

J-K flip-flop :

Block diagram :

75
Truth table:

Verilog Code :

module jk_ff(j, k, clk, reset, q, qb);

input [1:0]jk;
input clk,rst;
output q, qb;
reg q, qb;
reg [22:0] div;
reg clkdiv;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if(rst==1)
begin
q=0;
qb=1;
end
else
case (jk)
2'b00: begin q=q; qb=qb; end
2'b01: begin q=0; qb=1; end
2'b10: begin q=1; qb=0; end
2'b11: begin q=~(q); qb=~(qb); end
default: begin end

76
endcase
end
endmodule

Simulation Result of JK flip-flop:-

T flip-flop :

Block diagram

77
Truth Table :

Verilog Code :
module t_ff (t, clk, rst, q, qb);
input t, clk, rst;
output q, qb;
reg q,qb;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if (rst==1)
begin
q=0;
qb=1;
end
else
case ( t)
1’b0:begin q=q; qb=qb; end
1’b1:begin q=~(q); qb=~(qb); end
default: begin end
endcase
end
endmodule

Results:-
Developed the HDL code for flip flops SR,JK,D,T and simulated the designs and
verified the truth table of all the flip-flops with simulation Results.

78
 b. Counters
Objective: - Design and simulate the Verilog code for a 4-bit binary, BCD counters with
 Synchronous Reset
 Asynchronous Reset
 Any sequence
Theory: -

Basically the counters are the sequential blocks where in we use to generate a
sequence of numbers with respect to the clock counts which is a control signal provided for
the design. Counter can count and store the number of time any particular event or process
have occurred, depending on a clock signal. Counters can be modeled of synchronous or
Asynchronous types based on the clock applied for the design to execute the logic,
Asynchronous counters are those whose output is free from the clock signal. Because the
flip flops in asynchronous counters are supplied with different clock signals, there may be
delay in producing output. Counters can start counting not only from the zero, In fact it can
be initiated to any random value to make a count from some non-zero number and it is also
possible to increment the counter with more than one in one clock period.

6 (a). 4-bit Binary counter with Synchronous Reset

Block diagram :

Verilog Code :
module syncnt(clk, rst, bin_out)
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
always @ (posedge clk)
begin
if(rst) begin
bin_out<=4‘b0;
end
else
bin_out<=bin_out +1;
end
endmodule

79
Simulation Results:-

6 (b). 4 - bit Binary Counter with Asynchronous reset :

Block diagram:

Verilog Code :
module asyncnt(clk, rst, bin_out);
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
always @ (posedge clk or posedge rst)
begin
if(rst) begin
bin_out<=4'b0;
end

80
else
bin_out<=bin_out+1;
end
endmodule

Simulation Results:-

6 (c). 4-bit BCD counter with Synchronous reset :

Block diagram :

81
Verilog Code :

module syncnt_bcd(clk, rst, bcd_out);

input clk, rst;
output [3:0] bcd_out;
reg [3:0] temp;
assign bcd_out=temp;
always @ (posedge clk)
begin
if(rst)
begin
temp<=4'b0000;
end
else
begin
temp<=temp+1'b1;
if(temp==4'b1001)
temp<=4'b0000;
end
end
endmodule

Simulation Results

82
6 (d). 4-bit BCD counter with Asynchronous reset :

Block diagram :
rst BCD bcd_out
Asynchronous
inputs
Reset Counter outputs

clk

Verilog Code :
module Asyncnt_bcd(clk, rst, bcd_out);
input clk, rst;
output [3:0] bcd_out;
reg [3:0] temp;
assign bcd_out=temp;
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
temp<=4'b0000;
end
else
begin
temp<=temp+1'b1;
if(temp==4'b1001)
temp<=4'b0000;
end
end
endmodule

83
Simulation Results :

Result: - Designed and simulated the HDL code for a 4-bit binary, BCD counters with
 Synchronous Reset
 Asynchronous Reset
And verified the simulation Results for the counting sequence
and theSynchronous and Asynchronous counting.

84