1) JK Flip-Flop

Code:
--jk flipflop
--UGA BUGA
library ieee; use
ieee.std_logic_1164.all;

entity jk_flipflop is
port(j,k,clk: in std_logic; q,ql : out std_logic);
end jk_flipflop;

architecture beh of jk_flipflop is

begin;
process(j,k,clk); variable
var: std_logic; begin;
if(clk =’1’ and clk’event) then
if (j='0' and k='0') then
var := var;
elsif (j='0' and k='1') then
var :='0';
elsif (j='1' and k='0') then
var :='1';
elsif (j='1' and k='1') then
var := not var;
end if; end
if; q<=var;
ql<=not var;
end process; end
beh
2) SR Flip-Flop :

Code:
--UGA BUGA
--SR FLIPFLOP using if-then
library ieee;
use ieee.std_logic_1164.all;

entity SR is port(S,R,CLK:in
std_logic;
Q,Qb:out std_logic);
end SR;

architecture beh of SR is
begin; process(S,R,CLK);
variable temp: std_logic;
begin;

if(CLK='1' and CLK'event) then

if(S='0' and R='0') then
temp:=temp;
elsif (S='1' and R = '1') then
temp:= 'Z';
elsif(S=’0’ and R=’1’) then
temp :='0';
else temp :='1'; end
if;
end if;

Q<=temp;
Qb <=not temp;
end process; end
beh;
3) MUX 8:1
Code :
-- MUX 8:1
--UGA BUGA

library ieee;
use ieee.std_logic_1164.all;

entity mux8 is
port(I: in std_logic_vector(7 downto 0);
sel: in std_logic_vector(2 downto 0); Y: out std_logic); end mux8;

architecture seq of mux8 is

begin;
process(I,sel);
begin;
case sel is
when "000"=>Y<= I(0);
when "001"=>Y<= I(1);
when "010"=>Y<= I(2);
when "011"=>Y<= I(3);
when "100"=>Y<= I(4);
when "101"=>Y<= I(5);
when "110"=>Y<= I(6);
when others=>Y<= I(7);
end case;
end process;
end seq;
4) BCD to 7 Segment:
Code :
--UGA BUGA

library ieee;
use ieee.std_logic_1164.all;
entity bcd7 is
Port ( INPUT : in STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_SEVEN_SEGMENT : out STD_LOGIC_VECTOR (6 downto 0));
end bcd7;

architecture beh of bcd7 is

begin process(INPUT);
begin;
case INPUT is
when "0000" =>OUTPUT_SEVEN_SEGMENT <= "1111110";
when "0001" =>OUTPUT_SEVEN_SEGMENT <= "0110000";
when "0010"=>OUTPUT_SEVEN_SEGMENT <="1101101";
when "0011" =>OUTPUT_SEVEN_SEGMENT <= "1111001";
when "0100" =>OUTPUT_SEVEN_SEGMENT <= "0110011";
when "0101" =>OUTPUT_SEVEN_SEGMENT<="1011011";
when "0110" =>OUTPUT_SEVEN_SEGMENT <= "1011111";
when "0111" =>OUTPUT_SEVEN_SEGMENT <="1110000";
when "1000" =>OUTPUT_SEVEN_SEGMENT <= "1111111";
when "1001" =>OUTPUT_SEVEN_SEGMENT <= "1111011";
when others =>OUTPUT_SEVEN_SEGMENT <= "0000000";
end case;
end process;
end beh;
Mux0

INPUT[3..0]

OUTPUT_SEVEN_SEGMENT[6..0]
 5) 4-bit Comparator :

Code :
--UGA BUGA
library
ieee;
use ieee.std_logic_1164.all;

entity fourbitComparator is
port (A,B : in std_logic_vector(3 downto 0);
G,E,L: out std_logic);
end fourbitComparator;

architecture behv of fourbitComparator is

begin
G <= '1' when (A > B)
else '0';
E <= '1' when (A = B)
else '0';
L <= '1' when (A < B)
else '0';
end behv;

= LE SS _ TH A
E qu a l0N
A[3..0]
A[3..0] E
LessThan1 B[3..0]
B[3..0]

<
< L LEeQsUsALThan0
A[3..0]

B[3..0] G

LESS_THAN
A[3..0]

B[3..0]