Sanjivani Rural Education Society‟s

SANJIVANI K. B. P. POLYTECHNIC
DEPARTMENT OF COMPUTER TECHNOLOGY

CERTIFICATE
This is to certify that the project report entitled

Built/test 4 bit ripple counter using 7476

Submitted By
[156]Miss. Shaikh Mariyam Fakaruddin[157]Miss.Shevate Vaishnavi Sanjay

[169]Miss.Gawail Siddhi Balasaheb[170]Miss.Gondkar Samiksha Annasaheb

Under our supervision and guidance for partial fulfillment of the requirement for
Diploma in Computer Technology affiliated to
Maharashtra State Board of Technical Education, Mumbai
For academic year
2022-2023

Prof.V.G.WATTAMWAR Mr.G .N. Jorvekar

Project Guide HOD
 INDEX

Sr. Title Page

no No.
1). INTRODUCTION 1.
2). WHATS IS RIPPLE COUNTER ? 2.

3). RIPPLE COUNTER CIRCUIT 4.

4). RIPPLE COUNTER DIAGRAM &TIMING 5.

5). 3 BIT RIPPLE COUNTER 7.

6). 4 BIT RIPPLE COUNTER 9.

7). 4 BIT RIPPLE COUNTER USING D FLIP 10.

FLOP.
8). DRAWBACKS OF RIPPLE COUNTER 11.

9). APPLICATION OF RIPPLE COUNTER 12.

10). DESIGN OF RIPPLE COUNTER 13.

11). DESIGN OF ASYCHRONOUS RIPPLE MODE 14.

12) REFERENCE 20
 INTRODUCTION

While carefully observing the production line of glass bottles, which were
being packed as 10 bottles per package by machines, an inquisitive mind questions
– How does the machine knows to count the number of bottles? What teaches the
machines how to count? Searching an answer to solve this curiosity will lead to a
very interesting invention named – “Counter‟s”.Counters are the circuit which
count‟s the applied clock pulses. These are usually designed using flip-flops. Based
on the way clock is applied for their functioning counters are classified as
Synchronous and Asynchronous counters. In this article, let us look at an
Asynchronous counter which is notoriously known as Ripple counter.
 WHAT IS A RIPPLE COUNTER?

Before jumping to Ripple Counter let‟s get familiarized with the terms
Synchronous and Asynchronous counters. Counters are circuits made using flip-
flops. Synchronous counter, as the name suggests have all the flip-flops working in
sync with clock pulse as well as each other. Here clock pulse is applied to every
flip flop.
Whereas in Asynchronous counter clock pulse is applied only to the initial
flip flop whose value would be considered as LSB. Instead of the clock pulse, the
output of first flip-flop acts as a clock pulse to the next flip flop, whose output is
used as a clock to the next in line flip-flop and so on.
Thus, in Asynchronous counter after the transition of the previous flip flop
transition of the next flip flop takes place, not at the same time as seen in
Synchronous counter. Here flip-flops are connected in Master-Slave arrangement.

RIPPLE COUNTER

Ripple counter is an Asynchronous counter. It got its name because the clock
pulse ripples through the circuit. An n-MOD ripple counter contains n number of
flip-flops and the circuit can count up to 2n values before it resets itself to the
initial value.
These counters can count in different ways based on their circuitry.
UP COUNTER: Counts the values in ascending order.
DOWN COUNTER: Counts the values in descending order.
UP-DOWN COUNTER: A counter which can count values either in the forward
direction or reverse direction is called an up-down counter or reversible counter.
DIVIDE by N COUNTER: Instead of a binary, we may sometimes require to count
up to N which is of base 10. Ripple counter which can count up to value N which
is not a power of 2 is called Divide by N counter.

RIPPLE COUNTER CIRCUIT DIAGRAM AND TIMING

DIAGRAM

The working of the ripple counter can be best understood with the help of an
example. Based on the number of flip flops used there are 2-bit, 3-bit, 4-bit…..
ripple counters can be designed. Let us look at the working of a 2-bit binary ripple
counter to understand the concept.
A binary counter can count up to 2-bit values .i.e. 2-MOD counter can count
22 = 4 values. As here n value is 2 we use 2 flip-flops. While choosing the type of
flip-flop it should be remembered that Ripple counters can be designed only using
those flip-flops which have a condition for toggling like in JK and T flip flops.
BINARY RIPPLE COUNTER USING JK FLIP FLOP

The circuit arrangement of a binary ripple counter is as shown in the figure

below. Here two JK flip flops J0K0 and J1K1 are used. JK inputs of flip flops are
supplied with high voltage signal maintaining them at a state 1. The symbol for the
clock pulse indicates a negative triggered clock pulse. From the figure, it can be
observed that the output Q0 of the first flip flop is applied as a clock pulse to the
second flip flop.
 Here the output Q0 is the LSB and the output Q1 is the MSB bit. The
functioning of the counter can be easily understood using the Truth Table of JK
flip flop.
 So, according to the Truth table, when both the inputs are 1 the next state
will be the complement of the previous state. This condition is used in ripple flip
flop. As we have applied a high voltage to all the JK inputs of flip-flops they are at
the state 1, so they must toggle the state at the negative going end of the clock
pulse .i.e. at the transition 1 to 0 of the clock pulse. The timing diagram of the
binary ripple counter clearly explains the operation.

From the timing diagram, we can observe that Q0 changes state only during
the negative edge of the applied clock. Initially, the flip flop is at state 0. Flip-flop
stays in the state until the applied clock goes from 1 to 0. As the JK values are 1,
the flip flop should toggle. So, it changes state from 0 to 1. The process continues
for all pulses of the clock.
 Coming to the second flip flop, here the waveform generated by flip flop 1 is
given as clock pulse. So, as we can see in the timing diagram when Q0 goes
transition from 1 to 0 the state of Q1 changes. Here don‟t consider the above clock
pulse, only follow the waveform of Q0. Note that the output values of Q0 are
considered as LSB and Q1 are considered as MSB. From the timing diagram, we
can observe that the counter counts the values 00,01,10,11 then resets itself and
starts again from 00,01,… until clock pulses are applied to J0K0 flip flop.

3-bit Ripple counter using JK flip-flop – Truth Table/Timing Diagram

In the 3-bit ripple counter, three flip-flops are used in the circuit. As here „n‟ value
is three, the counter can count up to 23 = 8 values .i.e.
000,001,010,011,100,101,110,111. The circuit diagram and timing diagram are
given below.
 3 BIT RIPPLE COUNTER TIMING DIAGRAM

Here the output waveform of Q1 is given as clock pulse to the flip flop
J2K2. So, when Q1 goes from 1 to 0 transitions, the state of Q2 is changed. The
output of Q2 is the MSB.
CIRCUIT DIAGRAM AND TIMING DIAGRAM
In 4-bit ripple counter, n value is 4 so, 4 JK flip flops are used and the counter can
count up to 16 pulses. Below the circuit diagram and timing diagram are given
along with the truth table.
 4 BIT RIPPLE COUNTER TIMING DIAGRAM

4 BIT RIPPLE COUNTER USING D FLIP FLOP

When it comes to selecting a Flip Flop for Ripple counter designing an
important point to be considered is that the flip flop should contain a condition for
toggling of states. This condition is satisfied by only T and JK flip flops.
From the truth table of D flip flop, it can be clearly seen that it doesn‟t
contain the toggling condition. So, when a used as Ripple counter D flip flop has
initial value as 1. When the clock pulse undergoes the transition from 1 to 0 the flip
flop should change the state. But according to truth table when D value is 1 it stays
on 1 until D value is changed to 0. So, the waveform of D0-flip flop will always
stay 1, which is not useful for counting. So, D flip flop is not considered for
construction of Ripple Counters.

DIVIDE BY N COUNTER

Ripple counter counts values up to 2n. So, to count values which are not
powers of 2 is not possible with the circuitry that we have seen till now. But by
modification, we can make ripple counter to count the value which cannot be
expressed as a power of 2. Such a counter is called Divide by N counter.

DECADE COUNTER

The number of flip flops n to be used in this design are chosen in such a way
that 2n > N where N is the count of the counter. Along with flip flops, a feedback
gate is added so that at count N all the flip flops get reset to zero. This feedback
circuit is simply a NAND gate whose inputs are the outputs Q of those flip flops
whose output Q = 1 at the count N.
 Let us see the circuit of a counter for which N value is 10. This counter is
also known as Decade counter as it counts up to 10. Here the number of flip flops
should be 4 because of 24= 16 > 10. And at a count of N= 10 the outputs Q1 and
Q3 will be 1. So, these are given as inputs to the NAND gate. The output of the
NAND gate is applied to all the flip flops thereby resetting them to zero.

DRAWBACKS OF RIPPLE COUNTER

The carry propagation time is the time taken by a counter to complete its
response to the given input pulse. As in ripple counter, the clock pulse is
Asynchronous, it requires more time to complete the response.

APPLICATIONS OF RIPPLE COUNTER

 These counters are frequently used for measurement of Time.

 Measurement of Frequency.
 Measurement of Distance .
 Measurement of Speed.
 Waveform generation.
 Frequency Division.
 Digital Computers.
 Direct Counting.

Thus this is all about brief information about ripple counter, the working of
binary, 3bit And 4-bit counters construction using JK-Flip Flop along with circuit
diagram, ripple counter timing diagram, and truth table. The main reason behind
the construction of the ripple counter with D-Flip Flop, disadvantages and
applications of Ripple Counter.
 DESIGN RIPPLE COUNTER USING JK FLIP FLOP FOR THE
STATE

The uncertainity in the state of SR flipflop when S=R=1 can be eliminated in

JK flip-flop.The logic symbol and truth table of JK flipflop are given below.

A counter is a register capable of counting the number of clock pulses

arriving at the clock input. The n-bit counter has n flipflops and it has 2n distinct
states.
Mod-5 Asynchronous ripple down Counter:-
 In asynchronous ripple counter flipflops are connected in such a way that the
complement output of first flip flop drives the clock for the next flip flop and
so on. when n flipflops are used in the counter the count sequence starts
from 2n-1 to 0000 . In Asynchronous counter are not clocked
simultaneously, so the speed of operation will be less.

 Mod counter with less than 2n states can be constructed by allowing the
counter to skip states that are not required. When Mod-x counter is to be
designed a AND gate output is connected to the SET inputs of each flipflop.
 SET is an active high. So as soon as the AND gate output is low it will not
effect the count sequence. When AND gate output is high it will set all the
flip flops so that the counter immediately goes to the the 1111 state. Mod-5
asynchronous ripple down Counter can count from 111 to 011 and on next
clock pulse it returns back to initial state i.e. 111.For Mod-5 counter the
counter has to be reset as soon as count 011 is completed. That is it has to
reset when it reaches 010.

DESIGN OF ASYNCHRONOUS RIPPLE MOD-5 DOWN

COUNTER USING CLOCKED JK FLIP-FLOPS.

1.Find the number of flip flops for the required MOD counter.
2.Choose the type of flipflops to be used.
3. Draw a Digram.
4.Determine the flipflop inputs at which the counter has to be set.
5.Decide the inputs required for the AND gate to SET the Counter.
6.Connect the circuit using flipflops and other gates .

Step 1: Find the number of flip flops for the required MOD counter.
• As we have to construct Mod-5 counter i.e N = 5.
• Number of flipflops required can be caluculated for minimum value of n which
satisfies the below equation
• 2n≥N
• As N=5 then n=3.
• Thus Number of flipflops required = 3
Step 2: Choose the type of flipflops to be used.
• As we have to design Mod-5 counter with JK flipflop, so the selected flipflop is
JK.
Step 3: Draw the state diagram of required Mod counter.

• The states of a Mod-5 ripple down counter can be represented by a state diagram.
Each counter state in the state diagram is represented by a circle containg a binary
value. The prograssion is shown by a series of directional arrows.

Step 4: Determine the flipflop inputs at which the counter has to be set. Decide the
inputs required for the AND gate to SET the Counter.

Step 5: Connect the circuit using flipflops and other gates .

•The state table and timing diagram of 3-bit ripple counter is given below.
 REFERENCE
 https://www.elprocus.com/
 https://www.indiabix.com/
 https://www.ques10.com/