Efficient Digital PID Controller Implementation based on Virtex-5 FPGA

Amit Tripathi
Electrical and Electronics Communication
PEC University of Technology
Chandigarh, India
amit.tripathi87@gmail.com
V.Rihani
Electrical and Electronics Communication
PEC University of Technology
Chandigarh, India
v.rihani @yahoo.com

Abstract Proportional-Integral-Derivative (PID) controllers
are widely used in automation systems. They are usually
implemented either in hardware using analog components or
in software using computer-based systems. They may also be
implemented using Application Specific Integrated Circuits
(ASICs). In this paper, the implementation of software module
using Verilog for Xilinx FPGA Virtex-5 (XC5VLX50T) based
PID controller for automatic control application is presented.
The tool used for building and testing the software modules is
Xilinx ISE 10.1. Before verifying the design on FPGA the
complete design is simulated using Xilinx ISE Simulation tool.
A test bench is written where the input pattern can be changed
for the different application. It is observed that the estimated
pattern gradually changes to the set pattern and locks to the
set pattern. The change of estimated pattern depends on
process error and tuning of the parameters of PID controller.
In this implementation, less number of LUTs and IOBs are
used.
Keywords-Field Programmable Gate Array (FPGA), PID
Controller, Verilog, Virtex-5.
I. INTRODUCTION
FPGA - is an acronym for Field Programmable Gate
Array. It is a silicon chip containing an array of configurable
logic blocks (CLBs). Unlike an Application Specific
Integrated Circuit (ASIC) which can perform a single
specific function for the lifetime of the chip, an FPGA can be
reprogrammed to perform a different function in a matter of
microseconds. Before it is programmed an FPGA knows
nothing about how to communicate with the devices
surrounding it. This is both a blessing and a curse as it allows
a great deal of flexibility in using the FPGA while greatly
increasing the complexity of programming it. The ability to
reprogram FPGA has led them to be widely used by
hardware designers for prototyping circuits. The FPGA
configuration is generally specified using a hardware
description language (HDL), similar to that used for an ASIC.
FPGAs can be used to implement any logical function that an
ASIC could perform. The ability to update the functionality
after shipping, partial re-configuration of the portion of the
design and the low non-recurring engineering costs relative
to an ASIC design offer advantages for many applications.
The Proportional-Integral-Derivative (PID) controllers
have been widely used over the past five decades due to their
simplicity, robustness, effectiveness and applicability for a
broad class of systems. Despite the numerous control design
approaches that have appeared in the literature, it is
estimated that, nowadays PID controllers are still employed
in more than 95 % of industrial processes [1].
FPGA-based digital PID controller is proposed because
the operations on FPGA are hardware compatible operations.
However, FPGA-based digital PID controller still needs
multipliers for computation. These multipliers will decrease
the speed of processing time because the multiplying stage is
a time consuming process which introduces propagation
delay and uses large part of silicon area.
Implementation of PID controllers has gone through
several stages of evolution, from the early mechanical and
pneumatic designs to the Microprocessor based systems.
Recently, FPGAs have become an alternative solution for the
realization of digital control systems, which were earlier
dominated by the General purpose microprocessors. FPGA
based controllers offer advantages such as High speed
computation, complex functionality, real time processing
capabilities and low power consumption [2].
II. DIGITAL SYSTEM BASED ON FPGA
Hardware Description Languages (HDLs) are used to
describe hardware for the purpose of Simulation, Modeling,
Testing, Design, and Documentation of digital systems. The
most popular HDLs are VHDL [(Very High Speed
Integrated Circuit) Hardware Description Language], and
Verilog. VHDL can be used to describe hardware from the
abstract to the concrete level. Many of the Electronic Design
Automation (EDA) vendors are standardizing on VHDL and
Verilog as input and output from their tools. These tools
include simulation tools, synthesis tools, layout tools, testing
tools. Figure-1 shows hardware design flow for digital
systems.
HDL coding and synthesis process follow some general
guideline in terms of the structure of top-level design,
instantiation of bus macros, shared signals, and synthesis
attributes. This design flow describes the initial level to on
chip design implementation.
___________________________________
978-1-61284-836-5/11/$26.00 2011 IEEE

416

Figure-1: Hardware design flow
A. Initial Budgeting
In this phase, the design is floor planned and constrained
based on the properties of each module. This includes the
area-based floor plan of each module considering the
boundary properties of reconfigurable modules. All top-level
logic (IOBs and all global logic) should have fixed location
constraints. IOBs are Input-Output Blocks internally used in
FPGA devices. Global-level timing constraints are also
created in this phase. The result is a file with extension '.ucf'
that is used for active implementation phase. There are
various methods for entering constraint such as using Xilinx
GUI tools (Constraint Editor, Floor planner, etc.) [3] or
adding constraints directly in VHDL/Verilog code.
B. Active Implementation
This phase places and routes each module separately in
the context of the top-level logic and constraints. Before
running ngdbuild, map, and par [3] for each module, any
module specific constraints are added to the constraints file
created during the initial budgeting phase.
C. Final Assembly
This phase combines all the placed and routed modules
generated from the previous phase into a complete FPGA
design. To maintain the performance of each module,
placement and routing for each module are preserved. At
present, bitstreams generated for the full design require that
the initial bitstream include at least one variation of any
partially reconfigurable module. This means that the initial
bitstream should be a complete design since all global re-
sources such as clocking logic need to be placed and
properly constrained. Bitstream frames for global clocks are
separate from other frames [4].
III. PID CONTROL SYSTM
A PID controller, as its name suggests, provides
proportional, integral, and derivative compensation to an
existing system. These three forms of compensation increase
system performance in a variety of ways. Proportional
control can both increase gain margin and stabilize a
potentially unstable system. Integral control can minimize
steady state error. Derivative control can increase system
speed by increasing system bandwidth. One drawback of
PID control is overall complexity. This results in very
expensive means of implementing a digital version of a PID
controller. Of the many possibilities, FPGAs are the most
widely used to solve this problem, however other
possibilities exist which may be more cost-effective.
It was shown that DA (Distributed Arithmetic) based PID
controller saves 80% hardware utilization and 40% savings
in power consumption compared to the multiplier-based
scheme. Distributed Arithmetic is an algorithm which can be
used for implementing the mathematical equations efficiently.
It also offers good closed loop performance while using less
resource, resulting in cost reduction, high speed and low
power consumption which are desirable in embedded control
applications [5]. In PID control, increasing the proportional
gain k
p
can increase system response speed and it can
decrease steady state error but not eliminate it completely.
Additionally the performance of the closed loop system
becomes more oscillatory and takes longer time to settle
down after being disturbed as the gain is increased [2]. To
avoid these difficulties, integral control k
i
and derivative
control k
d
can eliminate steady state error and improve
system stability. The basic parallel form of PID controller is
shown in figure-2.
PID Controller Algorithm
Error e(t) is described from figure-2,
c(t) = r(t) -y(t)
Where r(t) is the process input and y(t) is the process
output.
On Chip design
verification and
debugging
Design
Code HDL
Synthesis
Simulation
Translate
Map
Place and Route
417

Figure-2: PID Controller

The PID controller is expressed as equation (1)

u(t) = k
P
_ c(t) +
1
I

_c(t)
t
0
Jt +I
d
J
Jt
c(t)_ (1)

Where, u(t) is control output, k
p
is the proportional
gain, T
i
is the integral time constant and T
d
is the derivative
time constant. Equation (1) is discretized for a small
sampling time T where continuous time domain t change to
discrete time domain n. The difference equation is given by


u(n) = k
P
_c(n) +
I
I

c(])
n
]=0
+
I
d
I
{c(n) - c(n -1)]
_ (2)


By using equation (2), PID algorithm can change to
simple form after using incremental algorithm; it converts
into equation (3). By equation (3) an output u(n) can be
calculated using past output u(n-1) and correction term. The
past output u(n-1) is calculated at discrete time n-1 with
correction term at discrete time n-2. The correction term
depends on Proportional, Integral and Derivative parameters
of PID controller. This approach is often called as the
velocity form of the PID algorithm.

u(n) = u(n - 1) + k
0
c(n) +k
1
c(n -1)
+k
2
c(n -2) (S)


Where
k
0
= k
P
+k

+k
d
,
k
1
= -k
P
-2k
d
,
k
2
= k
d


Where k
d
is differential gain and k
i
is integral gain
constant. This equation is implementable in FPGA using
Hardware Description Languages (HDLs).
IV. FPGA IMPLEMENTATION
After converting the PID control equation into simple
discrete form, the controller is implemented using Verilog
language with Xilinx ISE10.1 as a foundation tool [3] and
simulated at the Register Transfer Level (RTL) to verify the
correctness of the design using ISE simulator. By using the
Xilinx ISE Foundation tools, the logic synthesis was carried
out to optimize the design and the placement and routing
were carried out automatically to generate the FPGA
implementation file i.e. Bit file. The file is targeted to a
VIRTEX-5 XC5VLX50T-ff1136 with a speed grade of -1.
A. Verilog Hardware Description Language
Verilog is module based HDL [6, 12]. Advantage of
Verilog over VHDL, there is no need to use conversion
function for example signed and unsigned function directly
convert to STD logic function while in VHDL conversion
functions are necessary for same. Verilog codes are small
and less complex than VHDL code.
B. Xilinx Vertix-5 FPGA
The Virtex-5 architecture which is based on a real 6-
input LUT (Look Up Table) with dual LUT capacity,
provides substantial resources utilization advantages over
competing architectures. The Xilinx 6-input LUT is Look Up
Table with a total of 64 bits of logic programming space and
6-independent inputs. It is able to implement any function of
6-inputs and numerous combination of one and smaller
functions. In some portions of the logic, the 6-input LUT can
be additionally be used as 64- bits of RAM (Random Access
Memory) or 32-bits of shift register [7, 11].
C. Logic Simulation
Logic simulation in any FPGA design environment plays
a very vital role in verifying the functionality of the designs.
Simulation is a powerful way to test the system on a
computer, before it is turned into hardware. Simulators check
the values of signals inside the system. In the present study,
for functional verification, before verifying the performance
of proposed controller design on FPGA, the complete design
is simulated using ISE Simulation tool [3], which has pre-
compiled libraries for all Xilinx FPGAs. A test bench is
written where; the desired output can be changed for the PID
controller. In the test bench, the Top module of the design
PID Controller is instantiated. The inputs like Clock, Reset,
Error and Input pattern are defined and the output is
observed in the simulation window. Once all the signals are
taken into the waveform window, the simulation is run for
1000 nanosecond and the required changes in the signals are
observed in the waveform window. It is observed that the
418
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has 6-input LUT architecture, it reduces area of design and
cost. The successful hardware implementation of a PID
controller in FPGA technology must take into account
overall performance criteria expected of PID. These criteria
are data throughput rate, logic area and ease of configuration
and tuning. In LUTs (Look up Tables) based FPGAs circuits
the essential dynamic power consumption is caused by
transitions that take place at the inputs and outputs of LUTs
[9]. It results that the sum of the dynamic power should be
minimized over all the LUTs in the mapped network. Nets
having the greatest transition density have to be, if possible,
hidden in LUTs.
VI. CONCLUSION
In this paper PID controller has been implemented
successfully for different automatic control application that
can be used for DC motor speed control, temperature control
etc. The role of FPGA, from measurement and control point
of view, is to acquire the data from sensor through analog to
digital converter, do the processing on the acquired data and
then generate control signals to the actuator, which in turn
controls the parameter being measured. Virtex-5 FPGA
ensures ease of design, reduce development costs, more
product revenue, and the opportunity to speed products to
market. Building PID controllers on Virtex-5 FPGA
improves speed, accuracy, power-efficient, compactness and
cost effectiveness.
ACKNOWLEDGMENT
We are grateful to Electronics department of PEC
University of technology for providing necessary study
materials and Xilinx 10.1ISE tool, used in this paper.


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