804 IEEE TRANSACTIONS O N CIRCUITS AND SYSTEMS, VOL. 38, NO.
7, JULY 1991
We also paired the eigenvalues of F , and F , using the
matrices A and P, given in (17) and (18), respectively. With the
forward-only data matrix (71, the A matrix yielded 130 misses in
500 trials, while the P , matrix yielded 19 misses. The pairing
method given in this paper gave the correct pairing in all of the
trials. With the forward-backward data matrix (111, no misses
were observed with any pairing method.
ACKNOWLEDGMENT
The authors wish to thank an anonymous reviewer for helpful
comments and T. Manickam for performing the simulations.
REFER~NCES
J. Capon, “High-resolution frequency-wavenumber spectrum analy-
sis,” Proc. IEEE, vol. 57, pp. 1408-1418, Aug. 1969.
L. B. Jackson and C. H. Chien, “Frequency and bearing estimation
by two-dimensional linear prediction,” in Proc. IEEE ICASSP’79,
pp. 665-668, Apr. 1979.
0. L. Frost and T. M. Sullivan, “High resolution two-dimensional
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1979.
A. K. Jain and S. Raganath, “Two-dimensional spectral estima-
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1981.
J. H. McClellan, “Multidimensional spectral estimation,” Proc.
IEEE, vol. 70, pp. 1029-1039, Sept. 1982.
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125-128, Apr. 1982.
S. W. Lang and J. H. McClellan, “Spectral estimation for sensor
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T. S. Durrani and R. Chapman, “Eigenfilter methods for 2-D
spectral estimation,” in Proc. IEEE ICASSP’83, pp. 863-866, Apr.
1983.
R. Kumaresan and D. W. Tufts, “High-resolution frequency-wave-
number spectrum analysis,” Proc. IEEE, vol. 69, pp. 1515-1517,
Nov. 1981.
A. Efron and D. W. Tufts, “Estimation of frequencies of multiple
two-dimensional sinusoids: Improved methods of linear prediction,”
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M. Wax, T-J. Shan, and T. Kailath, “Covariance eigenstructure
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-, “Spatio-temporal spectral analysis by eigenstructure meth-
ods,” IEEE Trans. Acoust ., Speech, Signal Processing, vol. ASSP-32,
pp. 817-826, Aug. 1984.
D. Spielman, A. Paulraj, and T. Kailath, “ A high resolution algo-
rithm for combined time-of-arrival and direction-of-arrival estima-
tion,” in Proc. IEEE ICASSP’86, pp. 90-93, Apr. 1986.
S. Y. Kung, K. S. A r m , and D. V. Bhaskar Rao, “New state space
and singular value decomposition based approximation methods for
the harmonic retrieval,’’ J . Opt. Soc. A m . , vol. 73, pp. 1799-1811,
Dec. 1983.
D . V. Bhaskar Rao and S. Y. Kung, “ A state space approach for
the 2-D harmonic retrieval problem,” in Proc. IEEE ICASSP’84,
vol. 1, pp. 4.10.1-4.10.4, Apr. 1984.
S. Attasi, “Modelling and recursive estimation for double indexed
sequences,” in System Identification: Adi,ances and Case Studies,
R. K. Mehra and D. G. Lainiotis, Eds. New York: Academic
Press, 1976.
0098-4094/91/0700-0804$01.00 01991 I E E E
Small-Signal Analysis and Minimum Settling Time
Design of a One-Stage Folded-Cascode CMOS
Operational Amplifier
Howard C. Yang, Mahmoud A. Abu-Dayeh,
and David J. Allstot
Abstract -A small-signal analysis of the single-ended one-stage
folded-cascode CMOS operational amplifier i s presented. The analysis
results in a four-pole two-zero representation from which a two-pole
model is extracted that is sufficiently accurate for many applications in
s&ched-capacitor ( s c ) circuits. A design equation for obtaining the
minimum settling time (MST) response for SC applications is given.
I. INTRODUCTION
The CMOS folded-cascode operational amplifier (opamp)
provides higher frequency operation and better power supply
noise rejection in switched-capacitor (SC) circuits than conven-
tional cascode and two-stage designs. Although various versions
of folded-cascode opamps have been reported [1]-[4], a com-
plete small-signal analysis of the widely used single-ended one-
stage design has not been given. Moreover, it has recently been
shown that for SC applications there exists a well-defined mini-
mum settling time (MST) versus unity-gain phase margin for
two-pole opamps [5],[6]. Since the folded-cascode design is well
suited to high-frequency SC applications, it is desirable to de-
sign it for the MST response in order to obtain the maximum
operating frequency.
In this paper, we present a small-signal analysis of the CMOS
single-ended one-stage high-swing folded-cascode opamp shown
in Fig. 1. In Section 11, this opamp is accurately modeled with
four left-half-plane (LHP) poles and a complex pair of LHP
zeros. The fourth-order system is then simplified to a two-pole
model, which provides sufficient accuracy for many SC applica-
tions. In Section 111, a basic design equation for the MST
response is derived based on this two-pole model.
11. SMALL-SIGNAL
MODELLING
In SC circuits, the maximum output voltage step size between
sampling periods is usually small enough so that opamp slew-rate
limiting is negligible, and only small-signal analysis is necessary.
A small-signal model (Fig. 2) of the single-ended one-stage
folded-cascode opamp is associated with nodes a through e in
Fig. 1. The very high frequency pole associated with the node
between M5 and M6 is excluded from the model with negligible
error. The loading capacitance, C , ~ is
, included in C,, and Vout
Manuscript received December 9, 1989; revised January 9, 1991. This
work was supported in part by the National Science Foundation under
Contract MIP-8709158. This paper was recommended by Associate
Editor T. T. Vu.
H. C. Yang is with the Chips and Technologies, Inc., San Jose, C A
95134.
M. A. Abu-Dayeh is with National Semiconductor Corp., Santa Clara,
CA 95052.
D . J. Allstot is with the Department of Electrical and Computer
Engineering, Carnegie Mellon University, Pittsburgh, P A 15213.
I E E E Log Number 9144834.
IEEE TRANSACTIONS O N CIRCUITS AND SYSTEMS, VOL. 38, NO. 7, JULY 19Y1
Vdd
' rl10
t
vss
Fig. 1. One-stage single-ended folded-cascode CMOS operational am-
plifier.
is associated with node d . The node equations for the equivalent
circuit are
+
where Gm= gm gmbs. Complete expressions for the small-
signal parameter values are given in Table I. In writing these
equations, the small Cgd10(of MI01 in Fig. 2 is neglected since
with R,C, << R,Cc, Cgd10acts as a large Miller resistance [6],
[7] in parallel with the much smaller R , at node b. Using a
dominant-pole approximation, the transfer function for the cir-
cuit of Fig. 2 is
where the low-frequency voltage gain is given by
the dominant pole frequency is
805
and the nondominant pole/zero frequencies are
The numerator terms of (8) are the small-signal output conduc-
tances, g, and g,, associated with the n- (M9-MI0) and p -
channel (M7-M8) cascode current sources, respectively; Cd is
approximately equal to the loading capacitance, C,. Thus the
dominant pole w d = (g, + g p ) / C , is determined by the loading
capacitance C,. The nondominant poles are of the same order;
w b is associated with the cascode current mirror used for the
double-to-single-ended conversion, and w , and w e are associ-
ated with the cascode devices M9 and M8, respectively. Apply-
ing superposition to Fig. 1, it is clear that w,, w c , and w d
are associated with the V,,, signal path, while w e and w d are
associated with the path. When the transfer functions of
the parallel signal paths are summed at the output, w , and w ,
are combined into a single pole, w,, and w,, and w , remain as
separate nondominant poles. The LHP zeros of (12) usually
form a complex pair whose real part is the average of w b and
w,, R e ( s z l ,sZ2)= ( w , + w,)/2. T o make the analysis tractable,
assume that sz1 and sz2 are cancelled by w,,and w,. Conse-
quently, the fourth-order transfer function of (6) becomes a
second-order function
Fig. 3 shows the two-pole small-signal circuit model resulting
from (13) in which
The dominant pole associated with the output node is repre-
sented as the second stage in Fig. 3. Fig. 4 shows the simulated
frequency responses of the opamp (Fig. l), the complete small-
signal model (Fig. 21, and the two-pole model (Fig. 3). The
fourth-order model is accurate well beyond the unity-gain fre-
quency, while the two-pole model is less accurate near the
unity-gain frequency due to the inexact pole-zero cancellation.
However, the accuracy of the two-pole model in determining the
unity-gain phase margin is sufficient for designing the opamp to
realize the MST response.
 IEEE TRANSACTIONS O N CIRCUITS AND SYSTEMS, VOL. 38, NO. 7. JULY 1991
Fig. 2. A complete small-signal model for the opamp of Fig. 1. Node voltages Va-V, refer to nodes a - e in Fig. 1 , and V,,,
is associated with node d.
VI v out
Fig. 3 . A two-pole small-signal model for the folded-cascode opamp of
Fig. 1.
-200 I iO ' '''i00"''IK'
""i"bli0K' ';U 1OM O
M
; In SC applications, it has been shown that the minimum
FREQUENCY (Hz)
Fig. 4. SPICE (LEVEL = 2) simulated frequency responses for the
original opamp of Fig. 1 (curve 11, the fourth-order model of Fig. 2
(curve 2) and the two-pole model of Fig. 3 (curve 3 ) .
TABLE I
SMALL-SIGNALPARAMETER VALUES FOR THE COMPLETE SMALL-SIGNAL
MODEL OF FIG.2
111. FOLDED-CASCODE DESIGN
OPAMP FOR
THE MST RESPONSE
In two-stage opamps, frequency compensation is efficiently
implemented using a compensation capacitor in series with a
nulling resistor to cancel the first nondominant pole and split
the two remaining most dominant poles until the desired unity-
gain phase margin is obtained [8]. In the folded-cascode opamp,
frequency compensation is realized using the loading capaci-
tance, C,. Unlike the pole-splitting compensation in two-stage
opamps, C, compensation affects only the dominant pole asso-
ciated with the high impedance output node. Thus a desired
phase-margin is obtained by choosing C, to set the unity-gain
,
........................ ..................................................................
-
>
E
Y 1IL-L
10.1 ..................................
Vo(l+DI
............................
j
0 t,, t.2 100 200
TIME (nS1
Fig. 5. Simulated MST step response of the opamp with C, = 10 p F
(curve 2) compared with a more underdamped response with C, = 5 p F
(curve 1) and a more overdamped response with C, = 15 p F (curve 3).
The minimum settling time is indicated as t S l .
frequency. Excess phase shift due to the nondominant poles and
zeros is independent of C,.
small-signal settling time of a two-pole opamp is obtained with
an underdamped response so that the first peak of the step
response just touches the upper error bound [6], [7]. The pole
separation factor,
P = w , / ~ ~ = 4 ( a , , + l ) / [ l + ( . i r / l n D)']
= 4 a , / [ 1+ (n-/ln D)'] (16)
specifies the relative pole positions required to obtain the MST
response where D is the settling error bound (Fig. 5). Using (16)
with (7), (81, and (111, and assuming C, = C,, a general equa-
tion for the MST design of a single-ended one-stage folded-
cascode opamp is
Equation (17) can be used either to determine the optimum
loading capacitance for a given design, or to design the MST
opamp for a given C,.
To verify the analysis, the opamp of Fig. 1 was designed using
(17) and C, = 10 pF, D = 0.001, and the device sizes and dc bias
conditions listed in Table 11. The simulated frequency response
is shown in Fig. 4. Fig. 5 shows the simulated MST step
response (C, = 10 pF) compared with a more underdamped but
wider bandwidth response ( C , = 5 pF), and a more overdamped
but narrower bandwidth response ( C , = 15 pF). The two-pole
model correctly predicts longer settling times when C, is either
larger or smaller than the optimum design value. The simulated
unity-gain phase margin for the MST opamp is about 68", which
is slightly smaller than the MST phase margin of about 70"
predicted for an ideal two-pole opamp [6]. The discrepancy is
due to the inexact pole/zero cancellation assumed in develop-
ing the two-pole model.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 38, NO. 7, JULY 1991
0 ’ 0 [3] D. B. Ribner and M. A. Copeland, “Design techniques for cascoded
0 5 10 15 20
Loading Capacitance (pF)
Fig. 6. Simulated small-signal settling time versus C,. Curve 1: Set-
tling time normalized to the MST; Curve 2: Product of the unity-gain
frequency and the settling time; Curve 3: Unity-gain frequency, and
Curve 4: Unity-gain phase margin. The discontinuities in the settling
time characteristics are associated with the natural frequency of the
system and occur when response peaks or valleys just enter the bounded
region for changes in the loading capacitance.
M12OO/6 M7 460/6
M2 200/6 I M8 332/6
M3 460/6 M9 126/4
M4 332/6 M10 126/4
M5 126/4 I M11 252/4
M6 126/4 I M12 252/4
vdd = 5 v v,,= - 5 v
SPICE simulations of the small-signal settling characteristics
of the one-stage folded-cascode opamp versus output loading
capacitance are plotted in Fig. 6. Curves 1-4 present the total
settling time normalized to the MST, the product of the unity-
gain frequency and the settling time, the unity-gain frequency,
and the unity-gain phase margin, respectively. The settling time
is a strong function of C, with the MST obtained when C, = 10
pF as expected. From Fig. 6, note that as predicted by this
analysis, a higher unity-gain bandwidth does not necessarily
provide a faster settling response. Note further that Toumazou
et al. 191 have observed similar settling behavior in integrated
GaAs cascode opamps. Neither the unity-gain frequency nor the
settling time alone accurately describes opamp settling response,
but rather their product (curve 2 in Fig. 6). Thus ~ , t can
, serve
as a figure of merit for fast-settling opamp design.
IV. CONCLUSIONS
A detailed small-signal analysis of the single-ended one-stage
folded-cascode CMOS opamp has been presented. The small-
signal behavior of this opamp is well approximated by a simple
W98-4094/91/0700-0807$01 .OO 0 1991 IEEE
807
two-pole model. A design equation of the opamp to obtain the
minimum settling time response was derived based on the two-
pole model and the existing MST design theory. A design
example with SPICE simulations verified the analysis and the
validity of the simple two-pole model.
REFERENCES
[l] P. R. Gray and R. G. Meyer, “MOS operational amplifier design-A
tutorial overview,” IEEE J. Solid-State Circuits, vol. SC-17, pp.
969-982, Dec. 1982.
[2] T. C. Choi, R. T. Kaneshiro, R. W. Brodersen, P. R. Gray, W. B.
Jett, and M. Wilcox, “High-frequency CMOS switched-capacitor
filters for communications applications,” IEEE J. Solid-Srute Cir-
cuits, vol. SC-18, pp. 652-664, Dec. 1983.
CMOS opamps with improved PSRR and common-mode input
range,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 919-925, Dec.
1984.
[4] J. N. Babanezhad and R. Gregorian, “A programmable gain/loss
circuit,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 1082-1090,
Dec. 1987.
[SI H. C. Yang, J. R. Ireland, and D. J. Allstot, “Improved operational
amplifier compensation techniques for high-frequency switched-
capacitor circuits,” in Proc. 30th Midwest Symp. Circuits and Systems,
pp. 952-955, Aug. 1987.
[6] H. C. Yang and D. J. Allstot, “Considerations for fast-settling
operational amplifiers,” IEEE Trans. Circuits Syst., vol. 37, pp.
326-334, Mar. 1990.
[7] -, “An equivalent circuit model for two-stage operational ampli-
fiers,’’ in Proc. IEEE Int. Symp. Circuits and Systems, pp. 635-638,
June 1988.
[8] W. C. Black, Jr., D. J. Allstot, and R. A. Reed, “A high performance
low power CMOS channel filter,” IEEE J . Solid-State Circuits, vol.
SC-15, pp. 921-929, Dec. 1980.
[9] C. Toumazou, D. G. Haigh, S . J. Harrold, K. Steptoe, J. I. Sewell,
and R. Bayruns, “Design and testing of a GaAs switched-capacitor
filter,” in Proc. Int. Symp. Circuits and Systems, pp. 2825-2828,
1990.
Overtlow Oscillations in State-Space Digital Filters
Tamal Bose and Mei-Qin Chen
Abstmt-A new sufficient condition is established for the stability of
general state-space digital filters implemented with 2’s complement
arithmetic for the addition operation. Also, a necessary and sufficient
condition is established for the existence of period-T limit cycles in
second-order direct-form digital filters. This theorem can he used to
determine existence regions in the parameter plane for limit cycles of
arbitrary period. Also, given the filter coefficients, this theorem can be
used to find initial conditions that yield period-T limit cycles for any T ,
and all possible limit cycle vector sequences.
I. INTRODUC~ION
When digital filters are implemented with fixed point arith-
metic, overflow can occur during addition. The nonlinear effect
of this overflow is known to result in large amplitude oscillations
Manuscript received January 8, 1990; revised April 26, 1990. This
paper was recommended by Associate Editor E. Coyle.
T. Bose is with the Department of Electrical Engineering, The Citadel,
Charleston, SC 29409.
M.-Q. Chen is with the Department of Mathematics and Computer
Science, The Citadel, Charleston, SC 29409.
IEEE Log Number 9144835.