COMPUTER AIDED DIGITAL DESIGN

Sumanth Sakkara
Department of Electronics and Communication Engineering.
COMPUTER AIDED DIGITAL DESIGN

Hardware Description Language 2

Mr. Sumanth Sakkara

Department of Electronics and Communication
Engineering.
Computer Aided Digital Design
Hardware Description Language 2 : TESTBENCHES

TESTBENCH WITH TEST VECTOR FILE

example.tv is a text file containing the inputs and expected output written in binary
Computer Aided Digital Design
Hardware Description Language 2 : TESTBENCHES

TESTBENCH WITH TEST VECTOR FILE

Computer Aided Digital Design
Hardware Description Language 2 : TESTBENCHES

TESTBENCH WITH TEST

VECTOR FILE
 Computer Aided Digital Design
Hardware Description Language 2
:
Example:Write an HDL module for a hexadecimal seven-segment display
decoder. The decoder should handle the digits A, B, C, D, E, and F as well as 0–9
 Computer Aided Digital Design
Hardware Description Language 2
:
Example: The following SystemVerilog modules show errors that the authors
have seen students make in the laboratory. Explain the error in each module and
show how to fix it

module mux2(input logic [3:0] d0, d1,

input logic s,
output logic [3:0] y);
always @(posedge s)
if (s) y <= d1;
else y <= d0;
endmodule
 Computer Aided Digital Design
Hardware Description Language 2
:
Solution:

The sensitivity list should not include the word “posedge”. The always statement
needs to respond to any changes in s, not just the positive edge. Signals d0 and d1
need to be added to the sensitivity list. Also, the always statement implies
combinational logic, so blocking assignments should be used.

module mux2(input logic [3:0] d0, d1,

input logic s,
output logic [3:0] y);
always_comb
if (s) y = d1;
else y = d0;
endmodule
Computer Aided Digital Design
Hardware Description Language 2
:
Example:

The following SystemVerilog modules show errors that the authors have seen
students make in the laboratory. Explain the error in each module and show
how to fix it

module twoflops(input logic clk,

input logic d0, d1,
output logic q0, q1);
always @(posedge clk)
q1 = d1;
q0 = d0;
endmodule
Computer Aided Digital Design
Hardware Description Language 2
:
This module will actually work in this case, but it’s good practice to use
nonblocking assignments in always statements that describe sequential logic.
Because the always block has more than one statement in it, it requires a
begin and end.

module twoflops(input logic clk,

input logic d0, d1,
output logic q0, q1);
always_ff @(posedge clk)
begin
q1 <= d1; // nonblocking assignment
q0 <= d0; // nonblocking assignment
end
endmodule
 THANK YOU
Sumanth Sakkara
Department of Electronics and Communication
sumanthsakkara@pes.edu
+91 80 6666 3333 Ext 741