Department of Computer and Communication Systems Engineering

Faculty of Engineering
Universiti Putra Malaysia
43400 UPM Serdang
Selangor

Course : ECC3162 COMPUTER AND COMMUNICATION

SYSTEMS PRACTICAL II
Credit Hours : 1 (0+1)
Semester : 2 - 2022/2023
Lecturer : Pn. Roslizah binti Ali
Demonstrator : Aishah binti Abd Rahman
Wan Muhammad Haikal bin Sobri
Laboratory : Intelligent Systems Engineering Lab
Duration : 3 Hours

LAB 5: MULTIPLEXERS AND STATE MACHINE

Objectives:

1. To design, implement and test a three-bit wide 5-to-1 multiplexer and a finite
state machine for a sequence counter using Verilog design entry.
2. To implement testbenches and simulate the designs using ModelSim
software.
List of Equipment / Components:

NO. EQUIPMENT
QTY
Computer – Quartus Prime and
1 ModelSim-Intel FPGA Starter Edition 1
software
2 Terasic DE1-SoC Board 1

Introduction:

In this lab, students are required to design a multiplexer and a finite state machine
using Verilog. The design will be simulated using ModelSim-Intel FPGA software
and tested on the DE1-SoC board.

Procedures:

A. Multiplexer

Figure 1: A three-bit wide 5-to-1 multiplexer

1) Design a three-bit wide 5-to-1 multiplexer as shown in Figure 1 using Verilog

design entry with Quartus Prime.
2) Create a new project file (fivemux.v) and implement the 5-to-1 multiplexer
designed in Step 1. Partial listing of the code is shown in Listing 1.

2
 module fivemux (S, U, V, W, X, Y, M);
input [2:0] S, U, V, W, X, Y;
output [2:0] M;
//your code here
endmodule
Listing 1: Verilog code for a three-bit wide 5-to-1 multiplexer

3) Compile and verify the design. Fix any errors that exist.
4) Implement a testbench file (tfivemux.v) for the 5-to-1 multiplexer using
Verilog. Test all possible input to the multiplexer.
5) Simulate the 5-to-1 multiplexer using ModelSim-Intel FPGA. Observe and
record the waveform.
6) Test the functionality of the three-bit wide, 5-to-1 multiplexer by downloading the
circuit into the FPGA chip on DE1-SoC board. Use switches as inputs and LEDs
as outputs.

B. Finite state machine

1) Design a finite state machine to model a specified counting sequence counter.

The initial or reset state of the counter is 000. The predefined counting sequence
is:
000 → 110 → 111 → 011→ 010 → 101 → 000 → ….

2) Create a new project file (fsm_counter.v) and implement the counter

designed in Step 1 using Verilog design entry with Quartus Prime.
a. The counter should have at least two input (clock and reset).
b. Use a single initial block to initialize the initial state for the finite state
machine.
c. Use a single always block to compute the next logic state based on the
clock or reset signal.
d. Partial listing of the code is shown in Listing 2.

3) Compile and verify the design. Fix any errors that exist.

3
4) Simulate the sequence counter using ModelSim-Intel FPGA by creating a
testbench file using Verilog. Observe and record the waveform.
5) Test the functionality of the sequence counter by downloading the circuit into
the FPGA chip on DE1-SoC board. Use push buttons as inputs and LEDs as
outputs.

module fsm_counter (clk, reset, outp);

input clk, reset;
output [2:0] outp;
reg [2:0] outp;
reg [2:0] c_state; //store the current state
//define all possible state
parameter s1 = 3'b000; parameter s2 = 3'b110;
parameter s3 = 3'b111; parameter s4 = 3'b011;
parameter s5 = 3'b010; parameter s6 = 3'b101;

//your code here

endmodule
Listing 2: Verilog code for a sequence counter

Discussion / Conclusion:

Discuss all your experimental results and compare them with the simulation results.
Conclude the findings of your experiment.