Department of Computer and Communication Systems Engineering

Faculty of Engineering
Universiti Putra Malaysia
43400 UPM Serdang
Selangor

Course : ECC3162 COMPUTER AND COMMUNICATION

SYSTEMS PRACTICAL II
Credit Hours : 1 (0+1)
Semester : 2 - 2022/2023
Lecturer : Pn. Roslizah binti Ali
Demonstrator : Aishah binti Abd Rahman
Wan Muhammad Haikal bin Sobri
Laboratory : Intelligent Systems Engineering Lab
Duration : 3 Hours

LAB 6: FOUR JUNCTION TRAFFIC LIGHT CONTROL SYSTEM

Objectives:

1. To design and implement a traffic light module.

2. To design and implement a four-junction traffic light control system using
timers.
List of Equipment / Components:

NO. EQUIPMENT
QTY
1 Computer – Quartus Prime software 1
2 Terasic DE1-SoC Board 1

Introduction:

In this lab, students are required to design a four-junction traffic light control system
using Verilog. Students will be guided to implement the system using modular
design. The design will be tested on the DE1-SoC board.

Procedures:

A. Traffic Light Module

1) Create a new project file (traffic1) and implement a traffic light module using
Verilog entry with Quartus Prime.
2) The traffic light module has at least two inputs (reset and ctrl) and one output
(light). The following truth table shows the control signal for the traffic light
module.
Input Output
reset ctrl light
0 2'b00 RED
0 2'b01 YELLOW
0 2'b10 GREEN
1 XX RED

3) The initial state of the module should be RED. Partial listing of the code is shown
in Listing 1.
4) Compile and verify the design entry. Fix any errors that exist.

2
 module traffic1 (reset, ctrl, light);
input reset;
input [1:0] ctrl;
output [2:0] light;
//your code here
endmodule
Listing 1: Verilog code for a traffic light module

5) Test the functionality of the traffic light module by downloading the circuit into
the FPGA chip on DE1 SoC board. Use switches as input and LEDs as output.

B. Controller Module

1) Create a new project file (controller) and implement a traffic light controller
using Verilog entry with Quartus Prime.
2) The traffic light controller have at least two inputs (reset and clock) and four
outputs (ctrl1, ctrl2, ctrl3 and ctrl4)
3) Construct the state transition table for the controller module.
4) Implement, compile and verify the design entry. Fix any errors that exist.
5) Test the functionality of the controller module by downloading the circuit into the
FPGA chip on DE1 SoC board. Use switches as input and LEDs as output.

C. Four-Junction Traffic Light Control System

1) Create a new project file (fourjunction) and implement a four-junction traffic

light controller using Verilog entry with Quartus Prime.
2) From the same project import the traffic light module (traffic1.v) and
controller module (controller.v).
3) Implement the four-junction traffic light control system using the modules from
procedure A and procedure B.
4) Test the functionality of the traffic light control system by downloading the circuit
into the FPGA chip on DE1 SoC board. Derive the clock signal for the traffic
light control system from the 50-MHz clock signal (CLK_50) at four-second
intervals. Use SW0 as reset and LEDs as output.
3
Discussion / Conclusion:

1) The four-junction traffic light control system above has been implemented
without a pedestrian crossing. Discuss how you can implement a pedestrian
crossing using push button switch (KEY0 to KEY3) for all four junctions.

2) Discuss all your experimental results and conclude the findings of your
experiment.