A B C D E

204pin DDRIII-SO-DIMM X1
Memory BUS(DDR3) Single Channel page15
BANK 0, 1, 2
1.35V DDR3L 1333MHz
Digital Display Interfaces (DDI)
1 USB2.0 1

Port 1 Port 0
LVDS Conn. LVDS Translater HDMI Conn. Port 0 Port 1 Port 2 Port 3
page17 RTS2132R page16 page18 USB3.0 USB3.0 USB2.0 USB HUB USB
VGA VALLEYVIEW-M Conn.X1 Conn. FE1.1s(STT) Camera
page24 page24 page25 page17

VGA Conn.
page19
SOC Debug port Port 0 Port 1 Port 2
PCIE USB2.0 WLAN
Touch Screen
Conn. BT Combo
GPP2 GPP1 GPP0 FCBGA 1170 Pin page24 page24 page21
HD Audio(AZ)
10/100
2 Card Reader MINI Card 2

LAN Controller
RTS5239 (WLAN/BT)
page23 RTL8166-CG page6~13
page21 page23
SATA III SATA I
Port 0 Port1
SPI LPC Audio
Card Reader HDD ODD ALC3227
Transformer page20
Conn. Conn. Conn.
page23 RJ45 BIOS (8M) page22 page22
page23
ENE
KBC9012
FAN/LED page26
page28 Int. Speaker Combo Jacks
3 3
Conn. page20 page20
Int.KBD Touch Pad
Sub-borad page27 page27

USB/B
page24

PWR BTN/B
page28
4 4

TP BTN/B Security Classification Compal Secret Data Compal Electronics, Inc.

page27 2012/12/01 2013/07/10 Title
Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A994P
Date: Friday, February 21, 2014 Sheet 2 of 43
A B C D E
 A B C D E

Voltage Rails BOARD ID Table

Power Plane Description S0 S3 S4/S5 USOC1 217@ USOC1 186@
Board ID PCB Revision
VIN 19V Adapter power supply ON ON ON
DB 0.1
BATT+ 12V Battery power supply ON ON ON
SI 0.2 B3 2.17G B3 1.86G
B+ AC or battery power rail for power circuit. (19V/12V) ON ON ON
SA00007E920 SA00007EO10
1
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON
PV 0.3 1

+RTCVCC RTC Battery Power ON ON ON

MV 1.0 USOC1 CR1@ USOC1 PR1@

+1.0VALW +1.0v Always power rail ON ON ON

+1.2VALW +1.2v Always power rail ON ON ON BOM Option Table
+1.8VALW +1.8v Always power rail ON ON ON BTO Item BOM Structure CeleronR N2815 Dual 7.5W 2C PentiumR N3520 Quad 7.5W 4C
SA00007EO30 SA00007E940
+3VALW +3.3v Always power rail ON ON ON Unpop @
+5VALW +5.0v Always power rail ON ON ON USOC1 CR3@ USOC1 PR3@
Connector CONN@
+1.35V +1.35V power rail for DDR3L ON ON OFF XDP (Debug Port) XDP@
+SOC_VCC Core voltage for SOC ON OFF OFF EMI requirement EMI@
+SOC_VNN GFX voltage for SOC ON OFF OFF EMI requirement unpop @EMI@ CeleronR N2815 Dual 7.5W 2C PentiumR N3520 Quad 7.5W 4C
SA00007EO60 SA00007E950
+0.675VS +0.675V power rail for DDR3L Terminator ON OFF OFF ESD requirement ESD@
+1.0VS +1.0v system power rail ON OFF OFF ESD requirement unpop @ESD@
2 2
+1.05VS +1.05v system power rail ON OFF OFF 8161 LAN controller 8161@
+1.35VS +1.35v system power rail ON OFF OFF 8166 LAN controller 8166@
+1.5VS +1.5v system power rail ON OFF OFF LVDS LVDS@
+1.8VS +1.8v system power rail ON OFF OFF LVDS LDO mode LVDSLDO@
+3VS +3.3v system power rail ON OFF OFF LVDS SWR mode LVDSSWR@
+5VS +5.0v system power rail ON OFF OFF Translator RTS2132S 2132S@
Translator RTS2132R 2132R@
Short Pad RS@
Clean CMOS CMOS@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Jump JP@

3 3

EC SM Bus1 address EC SM Bus2 address

Device Address Device Address
Smart Battery 0001 011X b

SOC SM Bus address

Device Address
ChannelA DIMM0 JDIMM1(SPD)
43 level BOM table
A0 1010 000X

43 Level Description BOM Structure

4319P6BOL01 SMT MB AA231 V1UE3 HDMI

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/12/01 2013/07/10 Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A994P
Date: Monday, February 24, 2014 Sheet 3 of 43
A B C D E
 5 4 3 2 1

G3->S0 S0->S3 S3->S0 S0->S5

D D
ACIN
ACIN
+3VLP
+3VLP
EC_ON
EC_ON 1.53ms

+3VALW
+3VALW 1.58ms

+5VALW
+5VALW
SPOK
SPOK 7.28ms

+1.0VALW
+1.0VALW 8.23ms

+1.8VALW
+1.8VALW

ON/OFF
ON/OFF 95.38ms

101ms EC_RSMRST#
EC_RSMRST#
101ms PBTN_OUT#
PBTN_OUT#
102ms
EC_SLP_S4#
C
EC_SLP_S4# C

102ms
EC_SLP_S3#
EC_SLP_S3#
222ms 204ms
SYSON
SYSON 0.6ms
3.29ms
+1.35V
+1.35V 1.71ms
3.29ms
33.68ms DDR_PWROK
DDR_PWROK 21ms 22.32ms 36.20ms

VR_ON
VR_ON 2.49ms 2.50ms
8.85ms 9.81ms
+SOC_VCC
+SOC_VCC 2.50ms 2.50ms
10.55ms 11.5ms
+SOC_VNN
+SOC_VNN 0.28ms 279us

VGATE
VGATE 42.56ms
263ms 11.71ms 5.57ms
SUSP#
SUSP# 31.28us 31.12us
2.56ms 2.18ms
+1.0VS
+1.0VS 1.30ms 1.29ms
1.56ms 1.52ms
+1.05VS
+1.05VS 1.84ms 1.83ms
8ms 8.12ms
+1.35VS
+1.35VS 2.79ms 2.8ms
B 10.71ms 10.71ms B
+1.5VS
+1.5VS 2.11ms 2.08ms
16.59ms 16.63ms
+1.8VS
+1.8VS 3.77ms 3.77ms
15.31ms 15.34ms
+3VS
+3VS 4.41ms 4.41ms
20.48ms 20.27ms
+5VS
+5VS 12.83ms 12.77ms
19.61ms 19.60ms
+0.675VS
+0.675VS 49.83ms 49.87ms
148.3ms
144ms KBRST#
KBRST# 110ms 110ms
11.71ms
PMC_CORE_PWROK
MC_CORE_PWROK 110ms 110ms
11.71ms
DDR_CORE_PWROK
DR_CORE_PWROK 116ms 116ms
584ms 8.8ms SUSP#
PMC_PLTRST#
PMC_PLTRST#
2.38ms

NOTE:
1. T1 and T2 are recommended time for all the VR rails
A A
unless specified otherwise. The VR ramp up time T2 and
subsequent rail delay T3 are put in place to avoid
inrush current which may be caused by multiple loads
turning on simultaneously or fast charging of VR output
decoupling.

2. Platform devices other than SOC sequencing are not

Security Classification Compal Secret Data Compal Electronics, Inc.
2012/12/01 2013/07/10 Title
explicitly shown as they are not limited by the SOC
Issued Date Deciphered Date Power Sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
sequencing requirement. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A994P
Date: Friday, February 21, 2014 Sheet 4 of 43
5 4 3 2 1
 5 4 3 2 1

B+ PU801 +SOC_VCC
AC Adapter PWM +SOC_VNN
ISL95833HRTZ
19V Page. 37

Charger PU301 PU501 +0.675VS

PWM
D
BQ24725ARGRR RT8207MZQW +1.35V D

Page. 32 Page. 34

CHG_B+ +VBATT U37 +1.35VS

MOSFET
DMN3030LSS
Page. 28
BATTERY

8V~12V PU604 +1.0VALW

Regulator
SY8206DQNC
Page. 35
U36 +1.0VS
MOSFET
AO4304L
Page. 28

C PU401 +3VALW C
Regulator
SY8208BQNC
Page. 33
U35 +3VS
MOSFET
DMN3030LSS
Page. 28

PU601 +1.05VS
Regulator
SY8032ABC
Page. 35

PU701 +1.2VALW
Regulator
SY8032ABC
Page. 36
B B

PU703 +1.8VALW
Regulator
SY8033BDBC
Page. 36
U38 +1.8VS
MOSFET
DMN3030LSS
PU402 Page. 28
Regulator +5VALW PU702
SY8208CQNC LDO +1.5VS
APL5930KAI
Page. 33
U33 Page. 36
MOSFET +5VS
DMN3030LSS
Page. 28

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/12/01 2013/07/10 Title
Issued Date Deciphered Date Power Map
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A994P
Date: Friday, February 21, 2014 Sheet 5 of 43
5 4 3 2 1