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Compal Confidential UC1

Model Name : Diner_Crepe1.1(15")
U6 66
File Name : LA-D704P VRAM
AMD PCIex4
gDDR3 x4pcs Port #1~#4
R16M -M 1-70 D3(R7)
256M bx16(4 Gb)
512Mbx16(8Gb)
1Ch 64bits 1.5V R16M -M1-30
D3(R5) PCIe 2.0:5Gb/s
1
PCIe 3.0:8Gb/s 1
P.4 0 ~4 2 P.3 6 ~4 0 DDR4-SO-DIMM X 2
Dual Channel Interleaved
P.1 7 ~1 8
LVDS@
UT 1 DDR4 2133MHz 1.2V
J LVDS 1
eDP to LVDS Transmitter eDP x1Lane
RTD2132N
eDP/LVDS
CONN P. 20 P. 19
2.7Gb/s
Kabylake-U
JHD D
SATA 3.0 Port 0
eDP@ Skylake-U 2.5" SATA HDD P. 30
FHD eDPx2Lane GEN1 1.5Gb/s
GEN2 3Gb/s Port 1 JO DD
eDP@ 2.7Gb/s GEN3 6Gb/s ODD P.30
JCR T 1 U4 10 4 1356P BGA
CRT CONN DP to VGA Transmitter
RTD2168
DDIx2Lane Port 2
P. 22 CRT P.22 KBL-U 15W2+2 USB3.0
J H D M I1
DDIx4Lane Port 1 SKL-U 15W 2+2 5Gb/s
HDMI CONN HDMI USB2.0 Port 1 JUS B1 Port 1
P.21 297MHz USB3.0 port
U L1 480Mb/s (onboard-1) P.31
2 2
LAN
RTL8111HSH(Giga) PCIex1 Port #5 Port 2 JUS B2
RTL8166EH(10/100) P.23 PCIe Gen1:2.5Gb/s USB2.0 port
(onboard-2) P.31
PCIe Gen2:5Gb/s
Port 3 JIO 1
USB2.0 Port
(sub board) P.33
J W L AN 1
NGFF WLAN+BT PCIex1 Port #6
(Key E) PCIe 1.0:2.5Gb/s Port 4 J WLAN 1
P.32 PCIe 2.0:5Gb/s Bluetooth P.32

Port 5 J LVDS 1
Camera P.20

Port 6 J LVDS 1
Touch Screen P.20

3 JIO 1 3

Port 7 Card reader

SMbus RTS5141
(sub board) P.33
1MHz

JKB 1 UK1
Int.KBD P. 27 EC ENE LPC U A1
JTP1
KB9022QD 33MHz J SPK 1
PS2 HDA 24MHz HDA Aduio codec
TouchPad P.2 6 Internal SPK
P.27 U4
ALC3227
P.24
FAN P. 34 TPM JH P

SLB9 6 6 5 TT2 .0 Combo Jack

JPW R P.2 8
Lid switch
(sub board)
*default FWTPM
P.33 SPI
UC3 50MHz
4 4
Thermal sensor UC2

NCT 7718W P. 10 SPI ROM

8MBytes P. 07
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Tiitlle
Block Diagrams
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS, IINC... AND CONTAINS CONFIIIDENTIIIAL Size Document Number Rev
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVISION OF R&D v0.2
Custom
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS, IINC... NEITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS, IINC...
LA-D704P
Date: Wednesday, May 11, 2016 Sheet 2 of 60
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D D

@ 0 ohm
R

CPU GPU_PWRGD
PU801
DGPU_PWROK
+3VS 1. +3VS_VGA @
U4103 GPIO77
1.8V_PWRGD
PU8
DGPU_PWR_EN
C
GPIO78 EN C

PU801
2. VGA_CORE 0 ohm CPU

PXS_PWREN# DGPU_HOLD_RST#
NMOS
U4102
3. +1.05VS_VGA GPIO80
GPU_RST
+1.05VS GPU
B
PLT_RST# B

4. +1.5VS_VGA
U4102
+1.5VS

EN_1.8V
R 5. +1.8VS_VGA
PU8
C

A A

SecurrriiitttyCllassiifffiiicatttiiion Compalll Secrettt Dattta Compal Electronics, Inc.

Tiiitttlle
IIIssued Date Deciphered Date
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIDENTIAL AND
RSVD
TRADE SECRET IIINFORMATION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D Siiize Documenttt Numberrr Re v
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATION IIITCONTAIIINS D v0.2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC... LA-D707P
Dattte::: Wednesday, May 11, 2016 Sheettt 43 o fff60
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 5 4 3 2 1

AC
Adapter 19.5V
CPU DC/DC
RT8243AZQW NCP81206 52~54
P.45
INPUTS OUTPUTS
VCC_SA
B+ VCC_GT
VCC_VORE
D ECON D

EN +3VALW SYSTEM DC/DC

Vout +1.8V_PRIM RT8243AZQW
+19.5VB
Vout Vin SY8032A 48
Charge Charger PCH_PWR_EN
INPUTS OUTPUTS
Vin PGOOD +1.8V_PG B+ +5VALW/+3VALW
BQ24725 EN P.51 SYSTEM DC/DC
P.47
DC/DC RT8207P / 8032 49
(+5VALW/+3VALW) INPUTS OUTPUTS
+3VALW +1.2V_VDDQ+2.5V
Vout +2.5V B+ +0.6V_0.6
Vout Vin SY8032A VS
SYSTEM DC/DC
PM_SLP_S4# PGOOD +2.5V_PG SY8286
DC Discharge EN 50
Battery P.49
INPUTS OUTPUTS
3S1P PGOOD
4S1P P.48 B+ +1.0V_PRIM
P.46 SYSTEM DC/DC
SPOK SY8032A 51
INPUTS OUTPUTS
Vout +0.6V_0.6VS +3VALW +1.8V_PRIM
Vin DDR4 Vout +1.2V_VDDQ SYSTEM DC/DC
S5RT8027P PGOOD RT8880
C C
+2.5V_PG EN 56~57
DDR_PWROK
SM_PG_CTRL EN S3 P.49 INPUTS OUTPUTS
B+ +VGA_CORE

Vout +1.0V_PRIM SYSTEM DC/DC

SY8286 55
Vin +1.0V_PRIM
INPUTS OUTPUTS
+1.8V_PG SY8286 PGOOD +1.0V_VS_PG_PWR B+ +1.5VS_VGA
EN P.50

Vout +VCC_CORE
Vin NCP81206 Vout +VCC_GT
B

VR_ON DC/DC Vout +VCC_SA

B

VR_ON (CPU_CORE)
PGOOD VR_PWRGD
P.52,53

Vin RT8880 Vout +VGA_CORE

DC/DC
(VGA_CORE) PGOOD GPU_PGD
EN
DGPU_PWR_EN P.56

Vout +1.5VS_VGA
Vin SY8286
A
DC/DC A

(VGA_RAM) PGOOD VRAM_PG

EN
DGPU_PWR_EN
P.55

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 5 4 3 2 1

[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]

G3->S0 S0->S3/DS3 S0/DS3->S0 S0->S5

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#

+19VB +19VB

D +3VLP/+5VLP +3VLP/+5VLP D

EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#

PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

+3V_PRIM +3V_PRIM

+1.8V_PRIM +1.8V_PRIM

EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

gate may choose to completely ignore it

+1.0V_MPHYPLL +1.0V_MPHYPLL

+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM

SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C AC_PRESENT AC_PRESENT C

ON/OFF ON/OFF

PBTN_OUT# PBTN_OUT#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#

PM_SLP_S4# PM_SLP_S4#

SYSON SYSON

+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3# PM_SLP_S3#

SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms
B +1.0VS_VCCIO +1.0VS_VCCIO B

+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
T4 = Min : 20ms Max : 3 0ms(EC Control)
EC_VCCST_PG EC_VCCST_PG

VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA

+VCC_CORE +VCC_CORE

+VCC_GT +VCC_GT

VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK

H_CPUPWRGD H_CPUPWRGD

SYS_PWROK SYS_PWROK
A A

SUS_STAT# SUS_STAT#

SOC_PLTRST#
SOC_PLTRST#

SecuriiitttyClllassifffiiicatiiion Compalll Secret Data Compal Electronics, Inc.

IIIssued Dattte Tiitttlle
Deciiphered Datte
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS, IIINC...AND CONTAI NS CONFIIIDENTIIIAL AND
HW Reserve
TRAD E SEC RET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIIIVISION OF R&D Siiize Documenttt Numberrr Re v
Custom v0.2
DEPARTMEN T EXC EPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS, IIINC...NEITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAI NS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS, IIINC... LA-D707P
Dattte::: Wednesday, May 11, 2016 Sheettt 4 o ff60
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