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56

AC IN --> EC LOAD CODE

D D

ACIN

+3VPCU
EC load code finish

+3V_WAKE_ON

DEEP_EC_EN

S5_ON

+3V_WAKE

+3V_S5_DSW

+3V_S5

CFL Power-Up Sequencing (G3-->S0-->S3-->S4-->S5)

G3-->S5 Power button on S0-->S3-->S0

+3V_RTC
RTC_RST# tPCH01>9ms=54mS
ACIN
+3VPCU

NBSWON# S0-->G3
S5_ON (from EC)
5ms DC=OFF,AC=ON

(+3V_WAKE) (S5_ON)
(VCCPRIM_3p3) +3V_S5 3.65ms DC=1.0ms,AC OUT=20ms
DC=6.0ms,AC OUT=358ms
DC=10ms,AC
Load EC code form BIOS OUT=253ms 27us

(from +3V_S5 and +5V_S5 PG) the same DC=OFF,AC=ON

3V_5VPGD 10ms time

(S5_ON_2) Reserved VCCPRIM_1P0

(3V_5VPGD)
14.6ms
DC=20ms,AC
C
+1.05V_S5_VCCAMPHYPLL (3V_5VPGD) out=60.2ms C

+1.05V_S5 +1.05V_S5_VCCA_XTAL (3V_5VPGD)

+1.05V_S5_VCCAPLL

1V05S5_PWRGD
RSMRST#(And DSW_PWROK) (from EC, 1V05S5_PWRGD delay 15ms) (tPCH03 >10ms)
T3 15ms (Tu >40ns) 30.8ms
500us
(tPCH02 >10ms)

T4 50ms
AC_PRESENT(from EC,RSMRST# delay 50ms)

tPLT02<90ms

DNBSWON# T6 132ms S0-->S4-->S0 S0-->S5

T5 100ms
(tPCH43-1 >95ms=98ms)
(tPCH43-2 >16ms=132ms)

SLP_S4#(SUSC#) (T09 >30us) 52us 40us (Ta >30us)

SLP_S3#(SUSC#) (T10 >30us) 44us 52us (Tb >30us)

(S4 will be turn off) Note
SUS_ON_2.5V (from EC) T7 5ms 5ms
8.6ms
Befor SUS_ON 5ms
(from EC)
SUS_ON 5ms 5ms

(SUS_ON_2.5V+RC) (+3V_S5) (ALL_SYS_PWRGD) 363us 10ms

+2.5V_SUS After +1.2V_SUS
(SUS_ON+RC) (VIN) (ALL_SYS_PWRGD)
+1.2V_SUS

(from EC) 10ms (S3 will be turn off) 11.8ms

20.4ms 9.3ms
6.65ms

RUN_ON
+5V (X) (+5V_S5)

+3V (X) (+3V_S5)

+3V_SSD (X) (+3V_S5)

57.8ms

+1.5V(VDS) (100K+0.1U) (+3V_S5)

+1.2V(VM) (+1.2V_SUS)

+0.95V_VCCIO (X)
(VIN) (ALL_SYS_PWRGD)

B ALL_SYS_PWRGD (from +1.2V_SUS and +2.5V_SUS and VCCIO PG to EC) B

2ms
VR_ON (from EC)

H_VCCST_PWRGD (To CPU)

+0.675V_DDR_VTT (VR_ON)

VR_READY(To EC) 704us

+VCCSA (VR_ON)

5ms

EC_PWROK ( From EC to PCH_PWROK) (tPLT04>1ms)

10ms

VR_SVID_DATA

+VCC_GFX 1.68s

+VCC_CORE
(T14 >99ms)
(T14 99ms)
SYSPWROK (EC to SYS_PWRGD) 1ms

(T20 >2ms)
102.8ms
(0>tPCH33
PLTRST# >99ms)

(To EC) (0>tPCH33

SM_DRAMRST# >99ms)

DC mode for GC6

DGPU_PWR_EN (From PCH)
OR FBVDDQ_PD (From FBVDDQ Power GOOD)

1V8_AON_EN

+1.8V_GPU_AON (x) (+3V_S5) (ALL_SYS_PWRGD)

A
After +1.8V_GPU_AON high, the ALL_SYS_PWRGD will high)? A

1V8_MAIN_EN

+1.8V_GPU(1V8_MAIN)

NVVDD

Quanta Computer Inc.

PROJECT : FX506L/FX706L
Size Document Number Rev
POWER UP SEQUENCE 2A

Date: Thursday, March 26, 2020 Sheet 57 of 59

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