ALU Project

Salma Maher Mohamed

192100120
Part A code:

library ieee;

use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

entity parta is

Port (

A : in STD_LOGIC_VECTOR(15 downto 0);

B : in STD_LOGIC_VECTOR(15 downto 0);

S : in STD_LOGIC_VECTOR(1 downto 0);

CIN : in STD_LOGIC;

F : out STD_LOGIC_VECTOR(15 downto 0)

);

end parta;

architecture Behavioral of parta is

begin

process(A, B, S, CIN)

begin

case S is

when "00" =>

if (CIN = '0') then

F <= A;

else
 F <= A+1;

end if;

when "01" =>

if (CIN = '0') then

F <= A+B;

else

F <= A+B+1;

end if;

when "10" =>

if (CIN = '0') then

F <= A-B-1;

else

F <= A-B;

end if;

when "11" =>

if (CIN = '0') then

F<= A-1;

else

F <= "0000000000000000";

end if;

when others =>

F<= "0000000000000000";

end case;

end process;

end Behavioral;
wave Form for Part A:

operation F=A:

Operation F=A+b:

Operation F=A-B-1:

Operation F=A-1:
Operation F=A+1:

Operation F=A+B+1:

Operation F=A-B:

Operation F=0:
All parts code:
library ieee;

use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

entity ALU is

Port (

A : in STD_LOGIC_VECTOR(15 downto 0);

B : in STD_LOGIC_VECTOR(15 downto 0);

S : in STD_LOGIC_VECTOR(3 downto 0);

CIN : in STD_LOGIC;

F : out STD_LOGIC_VECTOR(15 downto 0)

);

end ALU;

architecture Behavioral of ALU is

signal F_A : std_logic_vector(15 downto 0);

signal F_B : std_logic_vector(15 downto 0);

signal F_C : std_logic_vector(15 downto 0);

signal F_D : std_logic_vector(15 downto 0);

COMPONENT partc

PORT(

A : IN std_logic_vector(15 downto 0);

S : IN std_logic_vector(1 downto 0);

CIN : in STD_LOGIC;

F : OUT std_logic_vector(15 downto 0)

);

END COMPONENT;

COMPONENT partd

PORT(

A : IN std_logic_vector(15 downto 0);

S : IN std_logic_vector(1 downto 0);

CIN : in STD_LOGIC;

F : OUT std_logic_vector(15 downto 0)

);

END COMPONENT;

COMPONENT partb

PORT(

A : IN std_logic_vector(15 downto 0);

B : IN std_logic_vector(15 downto 0);

S : IN std_logic_vector(1 downto 0);

F : OUT std_logic_vector(15 downto 0)

);

END COMPONENT;

COMPONENT parta

PORT(

A : IN std_logic_vector(15 downto 0);

B : IN std_logic_vector(15 downto 0);

S : IN std_logic_vector(1 downto 0);

CIN : IN STD_LOGIC;
F : OUT std_logic_vector(15 downto 0)

);

END COMPONENT;

begin

uut_D: partd PORT MAP (

A => A,

S => S(1 downto 0 ),

CIN => CIN,

F => F_D

);

uut_A: parta PORT MAP (

A => A,

B => B,

S => S(1 downto 0 ),

CIN => CIN,

F => F_A

);

uut_B: partb PORT MAP (

A => A,

B => B,

S => S(1 downto 0 ),

F => F_B

);
uut_C: partc PORT MAP (

A => A,

S => S(1 downto 0 ),

CIN => CIN,

F => F_C

);

process(F_A, F_B , F_C, F_D, S )

begin

case S(3 downto 2) is

when "00" =>

F<= F_A;

when "01" =>

F<= F_B;

when "10" =>

F<= F_C;

when "11" =>

F<= F_D ;

when others =>

F<= "0000000000000000";

end case;

end process ;

end Behavioral;