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8085 INSTRUCTION SET

Data Transfer Instructions:

Opcode Operand Description

1. Copy form source to destination This instruction copied the contents of the source register into the
MOV Rd, Rs destination register the contents of the source register are not
alterd.
M, Rs Eg:- MOV B C or MOV B M
Rd, M
2. Move immediate 8 bit The 8 bit data is stored in the destination register or memory.
MVI Rd, data Eg:- MVI B, 57H or MVI M, 57H
M, Data

3. Load Accumulator
LDA 16 – bit address The contents of the memory location, specified b a 16 – bit address
in
In the operand, are copied to the accumulator. The contents of the
Source are not altered.
Eg:- LDA 2034H
4. Load accumulator indirect
LDAX B/D Reg. Pair The contents of the designated register pair point to a memory
location. This instruction copies the contents of that memory
location
into the accumulator The contents of either the register pair or the
memory are not allowed.

ARITHMETIC Instructions:
Opcode Operand Description
1. Add register or memory to accumulator The contents of the operand ( register or memory) are added to the
ADD R contents of the accumulator and the result is stored in the
M accumulator.
Eg:- ADD B or ADD M
2. Add register to accumulator with carry.
ADC R The content of the operand ( register or memory) and the Carry
M flag are added to the contents of the accumulator and the result is
stored in the accumulator.
Eg:- ADC B or ADC M
3. Add immediate to accumulator
ADI 8 bit data The 8 bit data (operand) is added to the contents of the
accumulator and the result is stored in the accumulator.
Eg:- ADI 45H
4. Add immediate to accumulator with carry.
ACI 8 bit data The 8 bit data (operand) and the Carry flag are added to the
contents
Of the accumulator & result is stored in the accumulator.
Eg:- ACI 45H
PAGE :06
SUB :- Fundamental Of Microprocessors

Opcode Operand Description

5. Store Accumulator direct The contents of the accumulator are copied into the
memory
STA 16 bit address location specified by the operand.
Eg: STA 4350H

6. Store Accumulator Indirect

STAX Reg Pair The contents of the accumulator are copied into the
memory
location specified by the contents of the operand (reg pair)

7. Store H and L registers direct The contents of register L are stored into the memory
location
SHLD 16 – it address specified y the 16 bit address in the operand & the contents
of
H register are stored into the next memory location by
incrementing the operand.
Eg:- SHLD 2470H

8. Exchange H and L with D and E The contents of register H are exchanged with the contents
of
XCHG the register D, and the contents of register L are exchanged
With the contents of register E.
Eg:- XCHG

9. Subtract register or memory from accumulator The contents of the operand ( register or memory) are
SUB R subtracted from the contents of the accumulator and the
M result is stored in the accumulator.
Eg:- SUB B or SUB M

10. Subtract immediate from the accumulator The 8 bit data is subtracted from the contents of the
SUI 8 – bit data accumulator and the result is stored in the accumulator.
Eg:- SUI 45H

11. Increment register or memory by 1 The contents of the designated register or memory are
INR R incremented by 1 and the result is stored in the same place.
M Eg:- INR B or INR M
12. Increment register pair by 1 The contents of the designated register pair are
INX R incremented by 1 and the result is stored in the same place.
Eg:- INX H

13. Decrement register or memory by 1 The contents of the designated register or memory are
DCR R decremented by 1 and the result is stored in the same place.
M Ex:- DCR B or DCR M

14. Decrement Register pair by 1 The contents of the designate register pair are decremented
by
DCX R by 1 and the result is stored in the same place.
Eg:- DCX H

PAGE :07
SUB :- Fundamental Of Microprocessors

BRANCHING INSTRUCTIONS:

Opcode Operand Description

1. Jump unconditionally The program sequence is transferred to the memory
location
JMP 16 – bit address specified by the 16- bit address given in the operand.
Eg:- JMP 2034H or JMP XYZ

2. Jump conditionally The program sequence is transferred to the memory

location
Operand : 16 Bit address specified by the 16- bit address given in the operand based
on
The specified flag of the PSW as described below
Eg:- JZ 2034H or JZ XYZ

Opcode Description Flag Status

JC Jump on Carry CY = 1
JNC Jump on no Carry CY = 0
JP Jump on Positive S=0
JM Jump on Minus S=1
JZ Jump on zero Z=1
JNZ Jump on no zero Z=0
JPE Jump on parity even P=1
JPO Jump on Parity Odd P=0

2. Unconditional Call
CALL 16 – Bit Address The program sequence is transferred to the memory
location specified by the 16 – bit address given in the
operand.
Eg:- CALL 2034H or CALL XYZ
Call conditionally
Operand : 16 – Bit Address The Program sequence is transferred to the memory
location s specified by the 16- bit address given in the operand
based on the specified flag of the PSW as described below.
Eg:- CZ 2034 H or CZ XYZ
Opcode Description Flag Status

CC Call on Carry CY = 1
CNC Call on no Carry CY =0
CP Call on Positive S=0
CM Call on Minus S=1
CZ Call on Zero Z= 1
CNZ Call on no Zero Z=0
CPE Call on Parity even P=1
CPO Call on parity odd P =0

3. Return from subroutine unconditionally

RET none The program sequence is transferred from the subroutine to the
Calling program. The two bytes from the top of stack are copied
into
The program counter, and program execution begins at the new
Address. Eg:- RET PAGE :08

Opcode Operand Description

4. Load Program Counter with HL contents The contents of registers H and L are copied into the
PCHL none program counter. The contents of H are placed as the high
order byte and the contents of L as the low order byte.
Eg:- PCHL

5. Restart The RST instruction is equivalent to a 1 – byte call

instruction
RST 0-7 to one of eight memory locations depending upon the
number.

Instructions Restart Address

RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

The 8085 has four additional interrupts and these interrupts generate RST instructions internally and thus do not
require any external hardware. These instructions and their Restart addresses are –
Interrupt Restart Address
 TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
LOGICAL INSTRUCTIONS:
Opcode Operand Description
1. Compare register or memory with accumulator
CMP R The contents of the operand ( register or memory) are
M compared with the contents of the accumulator. Both
contents
are preserved.
If (A) < (reg /mem): Carry flag is set
If (A) =(reg / mem) : Zero Flag is set
If (A) > (Reg / memory): Carry & zero flag are reset.
Eg:- CMP B or CMP M

2. Compare immediate with accumulator The second byte (8 bit data) is compared with the contents
of
CPI 8 bit data the contents of the accumulator. The values being
compared
Remain unchanged. The result of the comparison is shown
by
Setting the flags of the OSW as follows:
If (A) < (reg /mem): Carry flag is set
If (A) =(reg / mem) : Zero Flag is set
If (A) > (Reg / memory): Carry & zero flag are reset
Eg:- CPI 89H
PAGE :09
SUB :- Fundamental Of Microprocessors

Opcode Operand Description

3. Logical AND register or memory with accumulator The contents of the accumulator are logically
ANDed
ANA R with the contents of the operand (register or memory), and
M the result is placed in the accumulator. If the operand is a
Memory location, its address is specified by the contents of
HL registers.
Eg:- ANA B or ANA M

4. Logical AND immediate with accumulator The contents of the accumulator are logically ANDed with
the
ANI 8 – bit data 8 bit data (operand) and the result is placed in the
accumulator.
Eg:- ANI 86H

5. Logical OR register or memory with The contents of the accumulator are logically ORed with
Accumulator. the contents of the operand (register or memory), and the
ORA R result is stored in accumulator.
M Eg:- ORA B or ORA M

6. Logical Or immediate with accumulator. The contents of the accumulator are logically ORed with
the
ORI 8 – bit – data 8 bit data (operand) and the result is placed in the
accumulator.
Eg:- ORI 86H

7. Rotate Accumulator Left Each binary bit of the accumulator is rotated left by one
RLC None position. Bit D7 is placed in the position of D0 as well as in
The Carry flag. CY is modified to bit D7.
Eg:- RLC

8. Rotate accumulator Right Each binary bit of the accumulator is rotated right by one
RRC None position. Bit D0 is placed in the position of D7 as well as in
the carry flag. Cy is modified according to bit D0
Eg:- RRC

9. Rotate accumulator left through carry Each binary bit of the accumulator is rotated left by one
RAL none position through the carry flag. Bit D7 is placed on the carry
flag, and the Carry flag is placed in the least significant
position D0. CY is modified to bit D7.
Eg:- RAL

10. Rotate accumulator right through carry Each binary bit of the accumulator is rotated right by one
RAR none position through the Carry flag. Bit D0 is placed in the
Carry
flag and he Carry flag is placed in the most significant
position D7. Cy is modified according to bit D0.
Eg:- RAR

11. Complement accumulator The contents of the accumulator are complemented. No

flags
CMA none are affected.
Eg:- CMA PAGE :10
SUB :- Fundamental Of Microprocessors

Opcode Operand Description

12. Complement Carry The Carry flag is complemented. No other flags are
affected.
CMC none Eg:- CMC

13. Set Carry The Carry flag is set to 1. No other flags are affected.
STC none Eg:- STC

CONTROL INSTRUCTIONS:
Opcode Operand Description
1. No Operation No operation is performed. The instruction is fetched and
NOP none decoded. However no operation is performed.
Eg:- NOP

2. Halt and enter wait state The CPU finishes executing the current instruction and
HLT none any further execution. An interrupt or reset is necessary
To exit from the halt state.
Eg:- HLT

3. Disable interrupts The interrupt enable flip – flop is reset and all the
DI none interrupts except the TRAP are disabled,. No flags are
affected.
Eg:- DI

4. Enable Interrupts The interrupt enable flip – flop is set and all interrupts are
EI none enabled. No flags are affected. After a system reset or the
Acknowledgement of an interrupt, the interrupt enable flip-
flop is reset, thus disabling the interrupts. This instructionis
necessary to re enable the interrupts ( except TRAP) .
Eg:- EI

Q.No. 38:- What is PSW?

Ans:- PSW ( Program Status Word) represents the contents of the accumulator and the flag register
together considering the accumulator as the high order and flag as the low order register as if it is the AF
register pair.

Q. NO. 39. What does Quality factor means?

Ans:- The Quality factor is also defined as Q. So it is a number, which reflects the lossness of a circuit.
Higher the Q, the lower are the losses.

Q. No. 40. What are the functions of an accumulator?

Ans:- The accumulator is the register with the ALU operations and sometimes I/O operarations. It is an
integral part of ALU. It holds one of data to be processed by ALU, It also temporarily stores the results of the
performed by the ALU. PAGE :11
Q. No. 41. What is Assembler?
Ans:- The Assembler translates the assembly language program text which is a given as input to the
assembler to their binary equivalents known as object code. The time required to translate the assembly lcode to
object code is called access time. The assembler checks foe syntax errors & displays before giving the object
code.
Q. No. 42. What is Loader?
Ans:- The loader copies the program into the computer’s main memory at load time and begins the
program execution at execution time.
 TAPOBAN STUDY CENTRE FOR Technical & Non-Technical
Cont. : 9681026768/ 8820022385 ( Whats app) ( 8.00 am to 6. Pm)
Custom Mail: support@tapobanstudycentre.com
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Our Online Exam Portal : www.tapobanstudycentre.in

Q. No. 43. What is Linker?

Ans:- A linker is a program used to join together several object files into one large object file. For large
programs it is more efficient to divide the large program modules into smaller modules. Each module is
individually written, tested & debugged. When all the modules work, they are linked together to form a large
functioning program.

Q.NO. 44. Compare Microprocessor & Microcontroller.

Ans:-
Microprocessor
1. Microprocessor contains ALU, General purpose
registers, Stack Pointer, Program Counter, Clock
timing circuit 7& interrupt circuit.
2. It has many instructions to move data between
memory and CPU.
3. It has one or two bit handling instructions.
4. Access times for memory and I/O devices are more. 4. Less access times foe built – in memory and I/O
5. Microprocessor based system requires more
hardware.
Microcontroller
1. Microcontroller contains the circuitry of
microprocessor and in addition it has built – in ROM,
RAM, I/O devices and counters.
2. It has one or two instructions to move data between
memory & CPU.
3. It has many bit handling instructions.
devices.
5. Microcontroller based system requires less
hardware reducing PCB size increasing the reliability.