SIMULATION OF

UNIVERSAL GATES
NAND,NOR AND A
MATHEMATICAL
FUNCTION

FEBRUARY 27, 2024

DEBASHISH KALITA
Aim:

Part 1:

To design and analyse the universal gates (NAND and NOR)

using Cadence VLSI EDA software. Using 180nm gpdk and
associated model parameters for cross-check of the results. We
need to perform the following steps:

1. Transistors sizing for optimal performance and effective rise

and fall resistances
equal to a unit inverter for 2-input NAND/NOR gates or any
Boolean function.
2. Estimate the worst- and best-case rising and falling time and
compare the delay
with Elmore delay model.
3. Estimate the power and operating frequency for different
configurations (process-
corners) and their dependence on supply voltage and sizing of
MOSFETs.
4. Optimize/trade-off of different design metrics for specific
applications.

Procedure:

Part 1

1. Design 2-input NAND and NOR gates as per the circuit

diagram having effective rise and fall resistances equal to a
unit inverter. Set Vdd=1.8V, and load capacitance CL=10ff.
2. For observations set input Vpulse wave with [period=2nS,
operating frequency= width=0.8nS] and voltage range of [0 to
1.8] V. Obtain all the cases by giving delay of 0.2ns to one of
the inputs in both cases.
3. Now perform DC analysis and estimate the noise margins for
both gates by taking derivative of the output voltage curve and
analysing point corresponding to slope =-1
4. Perform transient analysis and estimate the propagation delay
for both the configurations,
for different input patterns.
5. Identify the worst and best input patterns for both
configurations.
6. Calculate the maximum switching frequency and average
power (dynamic) if both configurations are operating at
500MHz.
7. Obtain the plots of DC and Transient analysis of the gates.

Part 2:

Design and simulate Bob Design 1 and Bob Design 2.

1. Alice asked Bob to Design a circuit that computes a

function F(x) so that she can authenticate the (x, F(x))
pairs as (username, password). Assume that F(x)=x^2
for x=0,1,2, 3....9.
2. Simulate both designs, using the cell libraries
developed in this lab with nominal transistor sizing.
3. Re-design both the Bob’s design using static
complementary approach.
 4. Simulate both designs, using the cell libraries
developed in this lab with nominal transistor sizing.
5. Calculate the propagation delay and average power
consumed for the best Bob design.

Formulas For Calculations:

Maximum Switching Frequency: f=1/ (tR+ tF)

Switching Speed= 1/[tp]
Power Calculations:
a. Dynamic Power =C*(Vdd^2) * f
b. Static Power= Ileakage VDD
Noise Margin:
a. Noise Margin High: NMH = VOH – VIH
b. Noise Margin Low: NML = VIL – VOL
Circuit Diagram:
Schematics:

Figure 4: NAND Gate

Figure 5: NOR Gate

Figure 6: Bob Design 1

Figure 7: Bob Design 2

Figure 8: Bob Design 1 using static cmos

 Figure 9: Bob Design 2 using static cmos

Observations:

Figure 10: DC response of NAND gate

Figure 11: DC response of NAND gate

Figure 12:Transient response of NAND gate

Figure 13: DC response of NOR gate

Figure 14: DC response of NOR gate

Figure 15: Transient response of NOR gate

Figure 16: Transient response of Bob Design 1

Figure 17: Transient response of Bob Design 2

Figure 18: Transient response of Bob Design 1 using static cmos

Figure 19: Transient response of Bob Design 2 using static cmos

Observation Table:
DC Analysis of NAND Gate: (Vdd=1.8V)

NMOS PMOS VOH VOL VIH VIL NMH NML

Width Width High Output Low Output High Input Low Input Noise Noise Margin
Voltage Voltage Voltage Voltage Margin High Low

2u 2u 1.8v 0v 0.866v 0.62v 0.934v 0.62v

2u 4u 1.8v 0v 0.965v 0.699v 0.835v 0.699v
4u 2u 1.8v 0v 0.791v 0.574v 1.009v 0.574v

DC Analysis of NOR Gate: (Vdd=1.8V)

NMOS PMOS VOH VOL VIH VIL NMH NML

Width Width High Output Low Output High Input Low Input Noise Noise Margin
Voltage Voltage Voltage Voltage Margin High Low

1u 4u 1.8v 0v 0.988v 0.699v 0.72v 1.08v

1u 2u 1.8v 0v 0.945v 0.617v 0.855v 0.617v
1u 8u 1.8v 0v 1.092v 0.843v 0.708v 0.843v

Transient Analysis of NAND Gate:

NMOS Width PMOS Width Propagation delay Propagation Propagation

time from high to delay time from Delay time
low low to high tp

2u 2u 0.02nS 0.00503nS 0.03515nS

2u 4u 0.06nS 0.06nS 0.06nS
4u 2u 0.029nS 0.087nS 0.058nS
Transient Analysis of NOR Gate:

NMOS Width PMOS Width Propagation Propagation Propagation

delay time from delay time from Delay time
high to low low to high tp

1u 4u 0.06nS 0.05nS 0.055nS

1u 2u 0.045nS 0.0821nS 0.06355nS
1u 8u 0.067nS 0.042nS 0.0545nS
Observation Plots:
For DC analysis of NAND Gate:
For DC analysis of NOR Gate:

For Transient analysis of NAND Gate:

For Transient analysis of NOR Gate:

For Transient analysis of Bob Design 1:

For Transient analysis of Bob Design 2:
For Transient analysis of Bob Design 1: [Using Static
CMOS]
For Transient analysis of Bob Design 2: [Using Static
CMOS]
CONCLUSIONS:

 We successfully determined the noise margins for both

configurations, i.e., 2-Input NAND and 2-Input NOR, and estimated the
propagation delay for both configurationsfor different input patterns.
 For 2-Input NAND Gate, Best Input Pattern is A=B=1→0 and Worst
Pattern is A= 1→0, B=1.
 For the 2-Input NOR Gate, the Best Input Pattern is A=B=1→0 and the
Worst Patternis A= B=0→1.
 We also determined the static and dynamic power and operating
frequency for differentconfigurations.
 We successfully simulated Bob’s both designs, using the cell
libraries developed inthis lab with nominal transistor sizing.
 We re-designed both of Bob’s designs using a static complementary approach.
 Average Power of Bob Design#1 is 47.04u Watts whereas, Bob
Design#2 is 47.60uWatts and as we know, When comparing two
designs based on average power, the design with lower average
power consumption is generally considered better from apower
efficiency standpoint. Hence, Bob Design #1 is better than Bob
Design #2.
 We also determined the static and dynamic power and operating
frequency for bothBob’s configurations.